Representation of each machine instruction. More...

#include "llvm/CodeGen/MachineInstr.h"

Inheritance diagram for llvm::MachineInstr:

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Collaboration diagram for llvm::MachineInstr:

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Public Types
enum	CommentFlag { ReloadReuse = 0x1, NoSchedComment = 0x2, TAsmComments = 0x4 }
	Flags to specify different kinds of comments to output in assembly code. More...

enum	MIFlag { NoFlags = 0, FrameSetup = 1 << 0, FrameDestroy = 1 << 1, BundledPred = 1 << 2, BundledSucc = 1 << 3, FmNoNans = 1 << 4, FmNoInfs = 1 << 5, FmNsz = 1 << 6, FmArcp = 1 << 7, FmContract = 1 << 8, FmAfn = 1 << 9, FmReassoc = 1 << 10, NoUWrap = 1 << 11, NoSWrap = 1 << 12, IsExact = 1 << 13 }

enum	QueryType { IgnoreBundle, AnyInBundle, AllInBundle }
	API for querying MachineInstr properties. More...

enum	MICheckType { CheckDefs, CheckKillDead, IgnoreDefs, IgnoreVRegDefs }

using	mmo_iterator = ArrayRef< MachineMemOperand * >::iterator

using	mop_iterator = MachineOperand *
	iterator/begin/end - Iterate over all operands of a machine instruction. More...

using	const_mop_iterator = const MachineOperand *

Public Member Functions
	MachineInstr (const MachineInstr &)=delete

MachineInstr &	operator= (const MachineInstr &)=delete

	~MachineInstr ()=delete

const MachineBasicBlock *	getParent () const

MachineBasicBlock *	getParent ()

const MachineFunction *	getMF () const
	Return the function that contains the basic block that this instruction belongs to. More...

MachineFunction *	getMF ()

uint8_t	getAsmPrinterFlags () const
	Return the asm printer flags bitvector. More...

void	clearAsmPrinterFlags ()
	Clear the AsmPrinter bitvector. More...

bool	getAsmPrinterFlag (CommentFlag Flag) const
	Return whether an AsmPrinter flag is set. More...

void	setAsmPrinterFlag (uint8_t Flag)
	Set a flag for the AsmPrinter. More...

void	clearAsmPrinterFlag (CommentFlag Flag)
	Clear specific AsmPrinter flags. More...

uint16_t	getFlags () const
	Return the MI flags bitvector. More...

bool	getFlag (MIFlag Flag) const
	Return whether an MI flag is set. More...

void	setFlag (MIFlag Flag)
	Set a MI flag. More...

void	setFlags (unsigned flags)

void	clearFlag (MIFlag Flag)
	clearFlag - Clear a MI flag. More...

bool	isInsideBundle () const
	Return true if MI is in a bundle (but not the first MI in a bundle). More...

bool	isBundled () const
	Return true if this instruction part of a bundle. More...

bool	isBundledWithPred () const
	Return true if this instruction is part of a bundle, and it is not the first instruction in the bundle. More...

bool	isBundledWithSucc () const
	Return true if this instruction is part of a bundle, and it is not the last instruction in the bundle. More...

void	bundleWithPred ()
	Bundle this instruction with its predecessor. More...

void	bundleWithSucc ()
	Bundle this instruction with its successor. More...

void	unbundleFromPred ()
	Break bundle above this instruction. More...

void	unbundleFromSucc ()
	Break bundle below this instruction. More...

const DebugLoc &	getDebugLoc () const
	Returns the debug location id of this MachineInstr. More...

const DILocalVariable *	getDebugVariable () const
	Return the debug variable referenced by this DBG_VALUE instruction. More...

const DIExpression *	getDebugExpression () const
	Return the complex address expression referenced by this DBG_VALUE instruction. More...

const DILabel *	getDebugLabel () const
	Return the debug label referenced by this DBG_LABEL instruction. More...

void	emitError (StringRef Msg) const
	Emit an error referring to the source location of this instruction. More...

const MCInstrDesc &	getDesc () const
	Returns the target instruction descriptor of this MachineInstr. More...

unsigned	getOpcode () const
	Returns the opcode of this MachineInstr. More...

unsigned	getNumOperands () const
	Retuns the total number of operands. More...

const MachineOperand &	getOperand (unsigned i) const

MachineOperand &	getOperand (unsigned i)

unsigned	getNumDefs () const
	Returns the total number of definitions. More...

bool	isOperandSubregIdx (unsigned OpIdx) const
	Return true if operand `OpIdx` is a subregister index. More...

unsigned	getNumExplicitOperands () const
	Returns the number of non-implicit operands. More...

unsigned	getNumExplicitDefs () const
	Returns the number of non-implicit definitions. More...

mop_iterator	operands_begin ()

mop_iterator	operands_end ()

const_mop_iterator	operands_begin () const

const_mop_iterator	operands_end () const

iterator_range< mop_iterator >	operands ()

iterator_range< const_mop_iterator >	operands () const

iterator_range< mop_iterator >	explicit_operands ()

iterator_range< const_mop_iterator >	explicit_operands () const

iterator_range< mop_iterator >	implicit_operands ()

iterator_range< const_mop_iterator >	implicit_operands () const

iterator_range< mop_iterator >	defs ()
	Returns a range over all explicit operands that are register definitions. More...

iterator_range< const_mop_iterator >	defs () const
	Returns a range over all explicit operands that are register definitions. More...

iterator_range< mop_iterator >	uses ()
	Returns a range that includes all operands that are register uses. More...

iterator_range< const_mop_iterator >	uses () const
	Returns a range that includes all operands that are register uses. More...

iterator_range< mop_iterator >	explicit_uses ()

iterator_range< const_mop_iterator >	explicit_uses () const

unsigned	getOperandNo (const_mop_iterator I) const
	Returns the number of the operand iterator `I` points to. More...

ArrayRef< MachineMemOperand * >	memoperands () const
	Access to memory operands of the instruction. More...

mmo_iterator	memoperands_begin () const
	Access to memory operands of the instruction. More...

mmo_iterator	memoperands_end () const
	Access to memory operands of the instruction. More...

bool	memoperands_empty () const
	Return true if we don't have any memory operands which described the memory access done by this instruction. More...

bool	hasOneMemOperand () const
	Return true if this instruction has exactly one MachineMemOperand. More...

unsigned	getNumMemOperands () const
	Return the number of memory operands. More...

MCSymbol *	getPreInstrSymbol () const
	Helper to extract a pre-instruction symbol if one has been added. More...

MCSymbol *	getPostInstrSymbol () const
	Helper to extract a post-instruction symbol if one has been added. More...

bool	hasProperty (unsigned MCFlag, QueryType Type=AnyInBundle) const
	Return true if the instruction (or in the case of a bundle, the instructions inside the bundle) has the specified property. More...

bool	isVariadic (QueryType Type=IgnoreBundle) const
	Return true if this instruction can have a variable number of operands. More...

bool	hasOptionalDef (QueryType Type=IgnoreBundle) const
	Set if this instruction has an optional definition, e.g. More...

bool	isPseudo (QueryType Type=IgnoreBundle) const
	Return true if this is a pseudo instruction that doesn't correspond to a real machine instruction. More...

bool	isReturn (QueryType Type=AnyInBundle) const

bool	isEHScopeReturn (QueryType Type=AnyInBundle) const
	Return true if this is an instruction that marks the end of an EH scope, i.e., a catchpad or a cleanuppad instruction. More...

bool	isCall (QueryType Type=AnyInBundle) const

bool	isBarrier (QueryType Type=AnyInBundle) const
	Returns true if the specified instruction stops control flow from executing the instruction immediately following it. More...

bool	isTerminator (QueryType Type=AnyInBundle) const
	Returns true if this instruction part of the terminator for a basic block. More...

bool	isBranch (QueryType Type=AnyInBundle) const
	Returns true if this is a conditional, unconditional, or indirect branch. More...

bool	isIndirectBranch (QueryType Type=AnyInBundle) const
	Return true if this is an indirect branch, such as a branch through a register. More...

bool	isConditionalBranch (QueryType Type=AnyInBundle) const
	Return true if this is a branch which may fall through to the next instruction or may transfer control flow to some other block. More...

bool	isUnconditionalBranch (QueryType Type=AnyInBundle) const
	Return true if this is a branch which always transfers control flow to some other block. More...

bool	isPredicable (QueryType Type=AllInBundle) const
	Return true if this instruction has a predicate operand that controls execution. More...

bool	isCompare (QueryType Type=IgnoreBundle) const
	Return true if this instruction is a comparison. More...

bool	isMoveImmediate (QueryType Type=IgnoreBundle) const
	Return true if this instruction is a move immediate (including conditional moves) instruction. More...

bool	isMoveReg (QueryType Type=IgnoreBundle) const
	Return true if this instruction is a register move. More...

bool	isBitcast (QueryType Type=IgnoreBundle) const
	Return true if this instruction is a bitcast instruction. More...

bool	isSelect (QueryType Type=IgnoreBundle) const
	Return true if this instruction is a select instruction. More...

bool	isNotDuplicable (QueryType Type=AnyInBundle) const
	Return true if this instruction cannot be safely duplicated. More...

bool	isConvergent (QueryType Type=AnyInBundle) const
	Return true if this instruction is convergent. More...

bool	hasDelaySlot (QueryType Type=AnyInBundle) const
	Returns true if the specified instruction has a delay slot which must be filled by the code generator. More...

bool	canFoldAsLoad (QueryType Type=IgnoreBundle) const
	Return true for instructions that can be folded as memory operands in other instructions. More...

bool	isRegSequenceLike (QueryType Type=IgnoreBundle) const
	Return true if this instruction behaves the same way as the generic REG_SEQUENCE instructions. More...

bool	isExtractSubregLike (QueryType Type=IgnoreBundle) const
	Return true if this instruction behaves the same way as the generic EXTRACT_SUBREG instructions. More...

bool	isInsertSubregLike (QueryType Type=IgnoreBundle) const
	Return true if this instruction behaves the same way as the generic INSERT_SUBREG instructions. More...

bool	mayLoad (QueryType Type=AnyInBundle) const
	Return true if this instruction could possibly read memory. More...

bool	mayStore (QueryType Type=AnyInBundle) const
	Return true if this instruction could possibly modify memory. More...

bool	mayLoadOrStore (QueryType Type=AnyInBundle) const
	Return true if this instruction could possibly read or modify memory. More...

bool	isCommutable (QueryType Type=IgnoreBundle) const
	Return true if this may be a 2- or 3-address instruction (of the form "X = op Y, Z, ..."), which produces the same result if Y and Z are exchanged. More...

bool	isConvertibleTo3Addr (QueryType Type=IgnoreBundle) const
	Return true if this is a 2-address instruction which can be changed into a 3-address instruction if needed. More...

bool	usesCustomInsertionHook (QueryType Type=IgnoreBundle) const
	Return true if this instruction requires custom insertion support when the DAG scheduler is inserting it into a machine basic block. More...

bool	hasPostISelHook (QueryType Type=IgnoreBundle) const
	Return true if this instruction requires adjustment after instruction selection by calling a target hook. More...

bool	isRematerializable (QueryType Type=AllInBundle) const
	Returns true if this instruction is a candidate for remat. More...

bool	isAsCheapAsAMove (QueryType Type=AllInBundle) const
	Returns true if this instruction has the same cost (or less) than a move instruction. More...

bool	hasExtraSrcRegAllocReq (QueryType Type=AnyInBundle) const
	Returns true if this instruction source operands have special register allocation requirements that are not captured by the operand register classes. More...

bool	hasExtraDefRegAllocReq (QueryType Type=AnyInBundle) const
	Returns true if this instruction def operands have special register allocation requirements that are not captured by the operand register classes. More...

bool	isIdenticalTo (const MachineInstr &Other, MICheckType Check=CheckDefs) const
	Return true if this instruction is identical to `Other`. More...

MachineInstr *	removeFromParent ()
	Unlink 'this' from the containing basic block, and return it without deleting it. More...

MachineInstr *	removeFromBundle ()
	Unlink this instruction from its basic block and return it without deleting it. More...

void	eraseFromParent ()
	Unlink 'this' from the containing basic block and delete it. More...

void	eraseFromParentAndMarkDBGValuesForRemoval ()
	Unlink 'this' from the containing basic block and delete it. More...

void	eraseFromBundle ()
	Unlink 'this' form its basic block and delete it. More...

bool	isEHLabel () const

bool	isGCLabel () const

bool	isAnnotationLabel () const

bool	isLabel () const
	Returns true if the MachineInstr represents a label. More...

bool	isCFIInstruction () const

bool	isPosition () const

bool	isDebugValue () const

bool	isDebugLabel () const

bool	isDebugInstr () const

bool	isIndirectDebugValue () const
	A DBG_VALUE is indirect iff the first operand is a register and the second operand is an immediate. More...

bool	isPHI () const

bool	isKill () const

bool	isImplicitDef () const

bool	isInlineAsm () const

bool	isMSInlineAsm () const

bool	isStackAligningInlineAsm () const

InlineAsm::AsmDialect	getInlineAsmDialect () const

bool	isInsertSubreg () const

bool	isSubregToReg () const

bool	isRegSequence () const

bool	isBundle () const

bool	isCopy () const

bool	isFullCopy () const

bool	isExtractSubreg () const

bool	isCopyLike () const
	Return true if the instruction behaves like a copy. More...

bool	isIdentityCopy () const
	Return true is the instruction is an identity copy. More...

bool	isMetaInstruction () const
	Return true if this instruction doesn't produce any output in the form of executable instructions. More...

bool	isTransient () const
	Return true if this is a transient instruction that is either very likely to be eliminated during register allocation (such as copy-like instructions), or if this instruction doesn't have an execution-time cost. More...

unsigned	getBundleSize () const
	Return the number of instructions inside the MI bundle, excluding the bundle header. More...

bool	readsRegister (unsigned Reg, const TargetRegisterInfo *TRI=nullptr) const
	Return true if the MachineInstr reads the specified register. More...

bool	readsVirtualRegister (unsigned Reg) const
	Return true if the MachineInstr reads the specified virtual register. More...

std::pair< bool, bool >	readsWritesVirtualRegister (unsigned Reg, SmallVectorImpl< unsigned > *Ops=nullptr) const
	Return a pair of bools (reads, writes) indicating if this instruction reads or writes Reg. More...

bool	killsRegister (unsigned Reg, const TargetRegisterInfo *TRI=nullptr) const
	Return true if the MachineInstr kills the specified register. More...

bool	definesRegister (unsigned Reg, const TargetRegisterInfo *TRI=nullptr) const
	Return true if the MachineInstr fully defines the specified register. More...

bool	modifiesRegister (unsigned Reg, const TargetRegisterInfo *TRI) const
	Return true if the MachineInstr modifies (fully define or partially define) the specified register. More...

bool	registerDefIsDead (unsigned Reg, const TargetRegisterInfo *TRI=nullptr) const
	Returns true if the register is dead in this machine instruction. More...

bool	hasRegisterImplicitUseOperand (unsigned Reg) const
	Returns true if the MachineInstr has an implicit-use operand of exactly the given register (not considering sub/super-registers). More...

int	findRegisterUseOperandIdx (unsigned Reg, bool isKill=false, const TargetRegisterInfo *TRI=nullptr) const
	Returns the operand index that is a use of the specific register or -1 if it is not found. More...

MachineOperand *	findRegisterUseOperand (unsigned Reg, bool isKill=false, const TargetRegisterInfo *TRI=nullptr)
	Wrapper for findRegisterUseOperandIdx, it returns a pointer to the MachineOperand rather than an index. More...

const MachineOperand *	findRegisterUseOperand (unsigned Reg, bool isKill=false, const TargetRegisterInfo *TRI=nullptr) const

int	findRegisterDefOperandIdx (unsigned Reg, bool isDead=false, bool Overlap=false, const TargetRegisterInfo *TRI=nullptr) const
	Returns the operand index that is a def of the specified register or -1 if it is not found. More...

MachineOperand *	findRegisterDefOperand (unsigned Reg, bool isDead=false, const TargetRegisterInfo *TRI=nullptr)
	Wrapper for findRegisterDefOperandIdx, it returns a pointer to the MachineOperand rather than an index. More...

int	findFirstPredOperandIdx () const
	Find the index of the first operand in the operand list that is used to represent the predicate. More...

int	findInlineAsmFlagIdx (unsigned OpIdx, unsigned *GroupNo=nullptr) const
	Find the index of the flag word operand that corresponds to operand OpIdx on an inline asm instruction. More...

const TargetRegisterClass *	getRegClassConstraint (unsigned OpIdx, const TargetInstrInfo TII, const TargetRegisterInfo TRI) const
	Compute the static register class constraint for operand OpIdx. More...

const TargetRegisterClass *	getRegClassConstraintEffectForVReg (unsigned Reg, const TargetRegisterClass CurRC, const TargetInstrInfo TII, const TargetRegisterInfo *TRI, bool ExploreBundle=false) const
	Applies the constraints (def/use) implied by this MI on `Reg` to the given `CurRC`. More...

const TargetRegisterClass *	getRegClassConstraintEffect (unsigned OpIdx, const TargetRegisterClass CurRC, const TargetInstrInfo TII, const TargetRegisterInfo *TRI) const
	Applies the constraints (def/use) implied by the `OpIdx` operand to the given `CurRC`. More...

void	tieOperands (unsigned DefIdx, unsigned UseIdx)
	Add a tie between the register operands at DefIdx and UseIdx. More...

unsigned	findTiedOperandIdx (unsigned OpIdx) const
	Given the index of a tied register operand, find the operand it is tied to. More...

bool	isRegTiedToUseOperand (unsigned DefOpIdx, unsigned *UseOpIdx=nullptr) const
	Given the index of a register def operand, check if the register def is tied to a source operand, due to either two-address elimination or inline assembly constraints. More...

bool	isRegTiedToDefOperand (unsigned UseOpIdx, unsigned *DefOpIdx=nullptr) const
	Return true if the use operand of the specified index is tied to a def operand. More...

void	clearKillInfo ()
	Clears kill flags on all operands. More...

void	substituteRegister (unsigned FromReg, unsigned ToReg, unsigned SubIdx, const TargetRegisterInfo &RegInfo)
	Replace all occurrences of FromReg with ToReg:SubIdx, properly composing subreg indices where necessary. More...

bool	addRegisterKilled (unsigned IncomingReg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)
	We have determined MI kills a register. More...

void	clearRegisterKills (unsigned Reg, const TargetRegisterInfo *RegInfo)
	Clear all kill flags affecting Reg. More...

bool	addRegisterDead (unsigned Reg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)
	We have determined MI defined a register without a use. More...

void	clearRegisterDeads (unsigned Reg)
	Clear all dead flags on operands defining register `Reg`. More...

void	setRegisterDefReadUndef (unsigned Reg, bool IsUndef=true)
	Mark all subregister defs of register `Reg` with the undef flag. More...

void	addRegisterDefined (unsigned Reg, const TargetRegisterInfo *RegInfo=nullptr)
	We have determined MI defines a register. More...

void	setPhysRegsDeadExcept (ArrayRef< unsigned > UsedRegs, const TargetRegisterInfo &TRI)
	Mark every physreg used by this instruction as dead except those in the UsedRegs list. More...

bool	isSafeToMove (AliasAnalysis *AA, bool &SawStore) const
	Return true if it is safe to move this instruction. More...

bool	mayAlias (AliasAnalysis *AA, MachineInstr &Other, bool UseTBAA)
	Returns true if this instruction's memory access aliases the memory access of Other. More...

bool	hasOrderedMemoryRef () const
	Return true if this instruction may have an ordered or volatile memory reference, or if the information describing the memory reference is not available. More...

bool	isDereferenceableInvariantLoad (AliasAnalysis *AA) const
	Return true if this load instruction never traps and points to a memory location whose value doesn't change during the execution of this function. More...

unsigned	isConstantValuePHI () const
	If the specified instruction is a PHI that always merges together the same virtual register, return the register, otherwise return 0. More...

bool	hasUnmodeledSideEffects () const
	Return true if this instruction has side effects that are not modeled by mayLoad / mayStore, etc. More...

bool	isLoadFoldBarrier () const
	Returns true if it is illegal to fold a load across this instruction. More...

bool	allDefsAreDead () const
	Return true if all the defs of this instruction are dead. More...

void	copyImplicitOps (MachineFunction &MF, const MachineInstr &MI)
	Copy implicit register operands from specified instruction to this instruction. More...

void	addOperand (MachineFunction &MF, const MachineOperand &Op)
	Add the specified operand to the instruction. More...

void	addOperand (const MachineOperand &Op)
	Add an operand without providing an MF reference. More...

void	setDesc (const MCInstrDesc &tid)
	Replace the instruction descriptor (thus opcode) of the current instruction with a new one. More...

void	setDebugLoc (DebugLoc dl)
	Replace current source information with new such. More...

void	RemoveOperand (unsigned OpNo)
	Erase an operand from an instruction, leaving it with one fewer operand than it started with. More...

void	dropMemRefs (MachineFunction &MF)
	Clear this MachineInstr's memory reference descriptor list. More...

void	setMemRefs (MachineFunction &MF, ArrayRef< MachineMemOperand *> MemRefs)
	Assign this MachineInstr's memory reference descriptor list. More...

void	addMemOperand (MachineFunction &MF, MachineMemOperand *MO)
	Add a MachineMemOperand to the machine instruction. More...

void	cloneMemRefs (MachineFunction &MF, const MachineInstr &MI)
	Clone another MachineInstr's memory reference descriptor list and replace ours with it. More...

void	cloneMergedMemRefs (MachineFunction &MF, ArrayRef< const MachineInstr *> MIs)
	Clone the merge of multiple MachineInstrs' memory reference descriptors list and replace ours with it. More...

void	setPreInstrSymbol (MachineFunction &MF, MCSymbol *Symbol)
	Set a symbol that will be emitted just prior to the instruction itself. More...

void	setPostInstrSymbol (MachineFunction &MF, MCSymbol *Symbol)
	Set a symbol that will be emitted just after the instruction itself. More...

uint16_t	mergeFlagsWith (const MachineInstr &Other) const
	Return the MIFlags which represent both MachineInstrs. More...

void	copyIRFlags (const Instruction &I)
	Copy all flags to MachineInst MIFlags. More...

void	untieRegOperand (unsigned OpIdx)
	Break any tie involving OpIdx. More...

void	addImplicitDefUseOperands (MachineFunction &MF)
	Add all implicit def and use operands to this instruction. More...

void	collectDebugValues (SmallVectorImpl< MachineInstr *> &DbgValues)
	Scan instructions following MI and collect any matching DBG_VALUEs. More...

void	changeDebugValuesDefReg (unsigned Reg)
	Find all DBG_VALUEs immediately following this instruction that point to a register def in this instruction and point them to `Reg` instead. More...


LLT	getTypeToPrint (unsigned OpIdx, SmallBitVector &PrintedTypes, const MachineRegisterInfo &MRI) const
	Debugging supportDetermine the generic type to be printed (if needed) on uses and defs. More...

bool	hasComplexRegisterTies () const
	Return true when an instruction has tied register that can't be determined by the instruction's descriptor. More...

void	print (raw_ostream &OS, bool IsStandalone=true, bool SkipOpers=false, bool SkipDebugLoc=false, bool AddNewLine=true, const TargetInstrInfo *TII=nullptr) const
	Print this MI to `OS`. More...

void	print (raw_ostream &OS, ModuleSlotTracker &MST, bool IsStandalone=true, bool SkipOpers=false, bool SkipDebugLoc=false, bool AddNewLine=true, const TargetInstrInfo *TII=nullptr) const

void	dump () const

Public Member Functions inherited from llvm::ilist_node_with_parent< MachineInstr, MachineBasicBlock, ilist_sentinel_tracking< true > >
MachineInstr *	getPrevNode ()

const MachineInstr *	getPrevNode () const
	Get the previous node, or `nullptr` for the list head. More...

MachineInstr *	getNextNode ()
	Get the next node, or `nullptr` for the list tail. More...

const MachineInstr *	getNextNode () const
	Get the next node, or `nullptr` for the list tail. More...

Public Member Functions inherited from llvm::ilist_node_impl< ilist_detail::compute_node_options< MachineInstr, Options... >::type >
self_iterator	getIterator ()

const_self_iterator	getIterator () const

reverse_self_iterator	getReverseIterator ()

const_reverse_self_iterator	getReverseIterator () const

bool	isSentinel () const
	Check whether this is the sentinel node. More...

Friends
struct	ilist_traits< MachineInstr >

struct	ilist_callback_traits< MachineBasicBlock >

class	MachineFunction

Additional Inherited Members
Protected Types inherited from llvm::ilist_node_impl< ilist_detail::compute_node_options< MachineInstr, Options... >::type >
using	self_iterator = ilist_iterator< ilist_detail::compute_node_options< MachineInstr, Options... >::type, false, false >

using	const_self_iterator = ilist_iterator< ilist_detail::compute_node_options< MachineInstr, Options... >::type, false, true >

using	reverse_self_iterator = ilist_iterator< ilist_detail::compute_node_options< MachineInstr, Options... >::type, true, false >

using	const_reverse_self_iterator = ilist_iterator< ilist_detail::compute_node_options< MachineInstr, Options... >::type, true, true >

Protected Member Functions inherited from llvm::ilist_node_with_parent< MachineInstr, MachineBasicBlock, ilist_sentinel_tracking< true > >
	ilist_node_with_parent ()=default

Protected Member Functions inherited from llvm::ilist_node_impl< ilist_detail::compute_node_options< MachineInstr, Options... >::type >
	ilist_node_impl ()=default

Detailed Description

Representation of each machine instruction.

This class isn't a POD type, but it must have a trivial destructor. When a MachineFunction is deleted, all the contained MachineInstrs are deallocated without having their destructor called.

Definition at line 64 of file MachineInstr.h.

Member Typedef Documentation

◆ const_mop_iterator

using llvm::MachineInstr::const_mop_iterator = const MachineOperand *

Definition at line 451 of file MachineInstr.h.

◆ mmo_iterator

using llvm::MachineInstr::mmo_iterator = ArrayRef<MachineMemOperand *>::iterator

Definition at line 68 of file MachineInstr.h.

◆ mop_iterator

using llvm::MachineInstr::mop_iterator = MachineOperand *

iterator/begin/end - Iterate over all operands of a machine instruction.

Definition at line 450 of file MachineInstr.h.

Member Enumeration Documentation

◆ CommentFlag

enum llvm::MachineInstr::CommentFlag

Flags to specify different kinds of comments to output in assembly code.

These flags carry semantic information not otherwise easily derivable from the IR text.

Enumerator
ReloadReuse
NoSchedComment
TAsmComments

Definition at line 74 of file MachineInstr.h.

◆ MICheckType

enum llvm::MachineInstr::MICheckType

Enumerator
CheckDefs
CheckKillDead
IgnoreDefs
IgnoreVRegDefs

Definition at line 931 of file MachineInstr.h.

◆ MIFlag

enum llvm::MachineInstr::MIFlag

Enumerator
NoFlags
FrameSetup
FrameDestroy
BundledPred
BundledSucc
FmNoNans
FmNoInfs
FmNsz
FmArcp
FmContract
FmAfn
FmReassoc
NoUWrap
NoSWrap
IsExact

Definition at line 80 of file MachineInstr.h.

◆ QueryType

enum llvm::MachineInstr::QueryType

API for querying MachineInstr properties.

They are the same as MCInstrDesc queries but they are bundle aware.

Enumerator
IgnoreBundle
AnyInBundle
AllInBundle

Definition at line 581 of file MachineInstr.h.

Constructor & Destructor Documentation

◆ MachineInstr()

llvm::MachineInstr::MachineInstr ( const MachineInstr & )

delete

◆ ~MachineInstr()

llvm::MachineInstr::~MachineInstr ( )

delete

Member Function Documentation

◆ addImplicitDefUseOperands()

void MachineInstr::addImplicitDefUseOperands ( MachineFunction & MF )

Add all implicit def and use operands to this instruction.

Definition at line 102 of file MachineInstr.cpp.

References addOperand(), llvm::MachineRegisterInfo::addRegOperandToUseList(), llvm::MachineFunction::allocateOperandArray(), assert(), llvm::MachineOperand::CreateReg(), getDebugLoc(), getDesc(), llvm::MCInstrDesc::getImplicitDefs(), llvm::MCInstrDesc::getImplicitUses(), llvm::MCInstrDesc::getNumImplicitDefs(), llvm::MCInstrDesc::getNumImplicitUses(), llvm::MCInstrDesc::getNumOperands(), getNumOperands(), getParent(), llvm::DebugLoc::hasTrivialDestructor(), llvm::MCInstrDesc::ImplicitDefs, llvm::MCInstrDesc::ImplicitUses, MI, MRI, operands(), llvm::MachineRegisterInfo::removeRegOperandFromUseList(), and setFlags().

Referenced by buildEXP(), llvm::SIInstrInfo::FoldImmediate(), hoistAndMergeSGPRInits(), llvm::SIInstrInfo::moveToVALU(), and untieRegOperand().

◆ addMemOperand()

void MachineInstr::addMemOperand	(	MachineFunction &	MF,
		MachineMemOperand *	MO
	)

Add a MachineMemOperand to the machine instruction.

This function should be used only occasionally. The setMemRefs function is the primary method for setting up a MachineInstr's MemRefs list.

Definition at line 360 of file MachineInstr.cpp.

References llvm::SmallVectorImpl< T >::append(), memoperands_begin(), memoperands_end(), llvm::SmallVectorTemplateBase< T >::push_back(), and setMemRefs().

Referenced by llvm::MachineInstrBuilder::addMemOperand(), computeBytesPoppedByCalleeForSRet(), llvm::TargetLoweringBase::emitPatchPoint(), llvm::TargetInstrInfo::foldMemoryOperand(), and setDebugLoc().

◆ addOperand() [1/2]

void MachineInstr::addOperand	(	MachineFunction &	MF,
		const MachineOperand &	Op
	)

Add the specified operand to the instruction.

addOperand - Add the specified operand to the instruction.

If it is an implicit operand, it is added to the end of the operand list. If it is an explicit operand it is added at the end of the explicit operand list (before the first implicit operand).

MF must be the machine function that was used to allocate this instruction.

MachineInstrBuilder provides a more convenient interface for creating instructions and adding operands.

If it is an implicit operand, it is added to the end of the operand list. If it is an explicit operand it is added at the end of the explicit operand list (before the first implicit operand).

Definition at line 199 of file MachineInstr.cpp.

◆ addOperand() [2/2]

void MachineInstr::addOperand ( const MachineOperand & Op )

Add an operand without providing an MF reference.

This only works for instructions that are inserted in a basic block.

MachineInstrBuilder and the two-argument addOperand(MF, MO) should be preferred.

Definition at line 176 of file MachineInstr.cpp.

References addOperand(), assert(), llvm::MachineBasicBlock::getParent(), and getParent().

◆ addRegisterDead()

bool MachineInstr::addRegisterDead	(	unsigned	Reg,
		const TargetRegisterInfo *	RegInfo,
		bool	AddIfNotFound = `false`
	)

We have determined MI defined a register without a use.

Look for the operand that defines it and mark it as IsDead. If AddIfNotFound is true, add a implicit operand if it's not found. Returns true if the operand exists / is added.

Definition at line 1837 of file MachineInstr.cpp.

References addOperand(), llvm::SmallVectorTemplateCommon< T, typename >::back(), llvm::MachineOperand::CreateReg(), llvm::SmallVectorBase::empty(), findInlineAsmFlagIdx(), getNumOperands(), getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::isDead(), llvm::MachineOperand::isDef(), isInlineAsm(), llvm::TargetRegisterInfo::isPhysicalRegister(), llvm::MachineOperand::isReg(), llvm::MCRegisterInfo::isSubRegister(), llvm::MCRegisterInfo::isSuperRegister(), llvm::MCRegAliasIterator::isValid(), llvm::SmallVectorTemplateBase< T, bool >::pop_back(), llvm::SmallVectorTemplateBase< T, bool >::push_back(), RemoveOperand(), and llvm::MachineOperand::setIsDead().

Referenced by llvm::LiveVariables::addVirtualRegisterDead(), llvm::Thumb1InstrInfo::copyPhysReg(), llvm::LiveRangeEdit::eraseVirtReg(), llvm::LiveVariables::HandleVirtRegDef(), isEFLAGSLive(), isFullCopyOf(), isRegTiedToDefOperand(), and llvm::LiveIntervals::shrinkToUses().

◆ addRegisterDefined()

void MachineInstr::addRegisterDefined	(	unsigned	Reg,
		const TargetRegisterInfo *	RegInfo = `nullptr`
	)

We have determined MI defines a register.

Make sure there is an operand defining Reg.

Definition at line 1906 of file MachineInstr.cpp.

References addOperand(), llvm::MachineOperand::CreateReg(), findRegisterDefOperand(), llvm::TargetRegisterInfo::isPhysicalRegister(), and operands().

Referenced by canInstrSubstituteCmpInstr(), llvm::SparcInstrInfo::copyPhysReg(), llvm::ARMBaseInstrInfo::copyPhysReg(), INITIALIZE_PASS(), isRegTiedToDefOperand(), llvm::LanaiInstrInfo::optimizeCompareInstr(), and setPhysRegsDeadExcept().

◆ addRegisterKilled()

bool MachineInstr::addRegisterKilled	(	unsigned	IncomingReg,
		const TargetRegisterInfo *	RegInfo,
		bool	AddIfNotFound = `false`
	)

We have determined MI kills a register.

Look for the operand that uses it and mark it as IsKill. If AddIfNotFound is true, add a implicit operand if it's not found. Returns true if the operand exists / is added.

Definition at line 1757 of file MachineInstr.cpp.

Referenced by addExclusiveRegPair(), llvm::LiveIntervals::addKillFlags(), llvm::LiveVariables::addVirtualRegisterKilled(), llvm::ARMBaseInstrInfo::breakPartialRegDependency(), llvm::X86InstrInfo::breakPartialRegDependency(), llvm::SparcInstrInfo::copyPhysReg(), llvm::ARMBaseInstrInfo::copyPhysReg(), emitAlignedDPRCS2Restores(), emitAlignedDPRCS2Spills(), llvm::XCoreFrameLowering::emitPrologue(), llvm::ARMBaseInstrInfo::expandPostRAPseudo(), llvm::LiveVariables::HandleVirtRegDef(), INITIALIZE_PASS(), isRegTiedToDefOperand(), and ReplaceDominatedUses().

◆ allDefsAreDead()

bool MachineInstr::allDefsAreDead ( ) const

Return true if all the defs of this instruction are dead.

allDefsAreDead - Return true if all the defs of this instruction are dead.

Definition at line 1368 of file MachineInstr.cpp.

References operands().

Referenced by llvm::LiveRangeEdit::eraseVirtReg(), INITIALIZE_PASS(), isFullCopyOf(), isRegTiedToDefOperand(), and llvm::LiveIntervals::shrinkToUses().

◆ bundleWithPred()

void MachineInstr::bundleWithPred ( )

Bundle this instruction with its predecessor.

This can be an unbundled instruction, or it can be the first instruction in a bundle.

Definition at line 721 of file MachineInstr.cpp.

References assert(), BundledPred, BundledSucc, llvm::ilist_node_impl< ilist_detail::compute_node_options< MachineInstr, Options... >::type >::getIterator(), isBundledWithPred(), and setFlag().

Referenced by llvm::MachineFunction::CloneMachineInstrBundle(), llvm::createR600ExpandSpecialInstrsPass(), llvm::SplitEditor::dump(), getMopState(), llvm::MIBundleBuilder::insert(), isBundledWithSucc(), and llvm::MIBundleBuilder::MIBundleBuilder().

◆ bundleWithSucc()

void MachineInstr::bundleWithSucc ( )

Bundle this instruction with its successor.

This can be an unbundled instruction, or it can be the last instruction in a bundle.

Definition at line 730 of file MachineInstr.cpp.

References assert(), BundledPred, BundledSucc, llvm::ilist_node_impl< ilist_detail::compute_node_options< MachineInstr, Options... >::type >::getIterator(), isBundledWithSucc(), and setFlag().

Referenced by llvm::MIBundleBuilder::insert(), and isBundledWithSucc().

◆ canFoldAsLoad()

bool llvm::MachineInstr::canFoldAsLoad ( QueryType Type = IgnoreBundle ) const

inline

Return true for instructions that can be folded as memory operands in other instructions.

The most common use for this is instructions that are simple loads from memory that don't modify the loaded value in any way, but it can also be used for instructions that can be expressed as constant-pool loads, such as V_SETALLONES on x86, to allow them to be folded when it is beneficial. This should only be set on instructions that return a value in their only virtual register definition.

Definition at line 753 of file MachineInstr.h.

References llvm::MCID::FoldableAsLoad, and hasProperty().

Referenced by llvm::LiveRangeEdit::eraseVirtReg(), llvm::TargetInstrInfo::foldMemoryOperand(), getNewSource(), isCopyFeedingInvariantStore(), and isFullCopyOf().

◆ changeDebugValuesDefReg()

void MachineInstr::changeDebugValuesDefReg ( unsigned Reg )

Find all DBG_VALUEs immediately following this instruction that point to a register def in this instruction and point them to Reg instead.

Definition at line 2095 of file MachineInstr.cpp.

References collectDebugValues().

Referenced by untieRegOperand().

◆ clearAsmPrinterFlag()

void llvm::MachineInstr::clearAsmPrinterFlag ( CommentFlag Flag )

inline

Clear specific AsmPrinter flags.

Definition at line 285 of file MachineInstr.h.

◆ clearAsmPrinterFlags()

void llvm::MachineInstr::clearAsmPrinterFlags ( )

inline

Clear the AsmPrinter bitvector.

Definition at line 272 of file MachineInstr.h.

◆ clearFlag()

void llvm::MachineInstr::clearFlag ( MIFlag Flag )

inline

clearFlag - Clear a MI flag.

Definition at line 311 of file MachineInstr.h.

Referenced by moveInstrOut(), llvm::MachineBasicBlock::remove_instr(), unbundleFromPred(), and unbundleFromSucc().

◆ clearKillInfo()

void MachineInstr::clearKillInfo ( )

Clears kill flags on all operands.

clearKillInfo - Clears kill flags on all operands.

Definition at line 1118 of file MachineInstr.cpp.

References operands().

Referenced by isRegTiedToDefOperand(), llvm::LanaiInstrInfo::optimizeSelect(), llvm::ARMBaseInstrInfo::optimizeSelect(), and llvm::rdf::Liveness::resetKills().

◆ clearRegisterDeads()

void MachineInstr::clearRegisterDeads ( unsigned Reg )

Clear all dead flags on operands defining register Reg.

Definition at line 1890 of file MachineInstr.cpp.

References operands(), and Reg.

Referenced by isCallerPreservedOrConstPhysReg(), isRegTiedToDefOperand(), llvm::ARMBaseInstrInfo::optimizeCompareInstr(), and llvm::PPCInstrInfo::optimizeCompareInstr().

◆ clearRegisterKills()

void MachineInstr::clearRegisterKills	(	unsigned	Reg,
		const TargetRegisterInfo *	RegInfo
	)

Clear all kill flags affecting Reg.

If RegInfo is provided, this includes all aliasing registers.

Definition at line 1824 of file MachineInstr.cpp.

References llvm::TargetRegisterInfo::isPhysicalRegister(), operands(), and llvm::TargetRegisterInfo::regsOverlap().

Referenced by llvm::LiveIntervals::addKillFlags(), isNopCopy(), and isRegTiedToDefOperand().

◆ cloneMemRefs()

void MachineInstr::cloneMemRefs	(	MachineFunction &	MF,
		const MachineInstr &	MI
	)

Clone another MachineInstr's memory reference descriptor list and replace ours with it.

Note that *this may be the incoming MI!

Prefer this API whenever possible as it can avoid allocations in common cases.

Definition at line 368 of file MachineInstr.cpp.

References assert(), getMF(), getPostInstrSymbol(), getPreInstrSymbol(), memoperands(), and setMemRefs().

Referenced by llvm::MachineInstrBuilder::cloneMemRefs(), cloneMergedMemRefs(), fixupGlobalSaddr(), and setDebugLoc().

◆ cloneMergedMemRefs()

void MachineInstr::cloneMergedMemRefs	(	MachineFunction &	MF,
		ArrayRef< const MachineInstr *>	MIs
	)

Clone the merge of multiple MachineInstrs' memory reference descriptors list and replace ours with it.

Note that *this may be one of the incoming MIs!

Prefer this API whenever possible as it can avoid allocations in common cases.

Definition at line 401 of file MachineInstr.cpp.

References llvm::SmallVectorImpl< T >::append(), assert(), cloneMemRefs(), dropMemRefs(), llvm::ArrayRef< T >::empty(), getMF(), hasIdenticalMMOs(), llvm::make_pointee_range(), memoperands(), memoperands_begin(), memoperands_empty(), memoperands_end(), setMemRefs(), llvm::ArrayRef< T >::size(), and llvm::ArrayRef< T >::slice().

Referenced by llvm::MachineInstrBuilder::cloneMergedMemRefs(), and setDebugLoc().

◆ collectDebugValues()

void MachineInstr::collectDebugValues ( SmallVectorImpl< MachineInstr *> & DbgValues )

Scan instructions following MI and collect any matching DBG_VALUEs.

Definition at line 2078 of file MachineInstr.cpp.

References llvm::MachineBasicBlock::end(), getOperand(), getParent(), llvm::MachineOperand::getReg(), llvm::MachineOperand::isReg(), MI, and llvm::SmallVectorTemplateBase< T, bool >::push_back().

Referenced by changeDebugValuesDefReg(), performSink(), untieRegOperand(), and llvm::WebAssemblyDebugValueManager::WebAssemblyDebugValueManager().

◆ copyImplicitOps()

void MachineInstr::copyImplicitOps	(	MachineFunction &	MF,
		const MachineInstr &	MI
	)

Copy implicit register operands from specified instruction to this instruction.

copyImplicitOps - Copy implicit register operands from specified instruction to this instruction.

Definition at line 1380 of file MachineInstr.cpp.

References addOperand(), getDesc(), llvm::MCInstrDesc::getNumOperands(), getNumOperands(), getOperand(), llvm::MachineOperand::isImplicit(), llvm::MachineOperand::isReg(), and llvm::MachineOperand::isRegMask().

Referenced by llvm::MachineInstrBuilder::copyImplicitOps(), enableAllocFrameElim(), fixupGlobalSaddr(), llvm::HexagonFrameLowering::getFrameIndexReference(), InsertLDR_STR(), and isRegTiedToDefOperand().

◆ copyIRFlags()

void MachineInstr::copyIRFlags ( const Instruction & I )

Copy all flags to MachineInst MIFlags.

Definition at line 522 of file MachineInstr.cpp.

References AllInBundle, llvm::FastMathFlags::allowContract(), llvm::FastMathFlags::allowReassoc(), llvm::FastMathFlags::allowReciprocal(), AnyInBundle, llvm::FastMathFlags::approxFunc(), assert(), llvm::ilist_node_impl< ilist_detail::compute_node_options< MachineInstr, Options... >::type >::getIterator(), isBundledWithPred(), llvm::BitmaskEnumDetail::Mask(), llvm::FastMathFlags::noInfs(), llvm::FastMathFlags::noNaNs(), llvm::FastMathFlags::noSignedZeros(), llvm::X86II::OB, and setFlag().

Referenced by computeValueLLTs(), getOffsetFromIndices(), and setDebugLoc().

◆ definesRegister()

bool llvm::MachineInstr::definesRegister	(	unsigned	Reg,
		const TargetRegisterInfo *	TRI = `nullptr`
	)		const

inline

Return true if the MachineInstr fully defines the specified register.

If TargetRegisterInfo is passed, then it also checks if there is a def of a super-register. NOTE: It's ignoring subreg indices on virtual registers.

Definition at line 1143 of file MachineInstr.h.

References findRegisterDefOperandIdx(), and TRI.

Referenced by addLiveInRegs(), llvm::ARMBaseInstrInfo::breakPartialRegDependency(), checkAndUpdateCPSRKill(), checkAndUpdateEFLAGSKill(), checkCCKill(), convertToNonFlagSettingOpc(), llvm::ARMBaseInstrInfo::expandPostRAPseudo(), getImplicitSPRUseForDPRUse(), llvm::ARMBaseInstrInfo::getPartialRegUpdateClearance(), ImposeStackOrdering(), INITIALIZE_PASS(), isCompareZero(), IsSafeToMove(), llvm::ARMBaseInstrInfo::isSchedulingBoundary(), llvm::PPCRegisterInfo::lowerCRBitRestore(), llvm::PPCRegisterInfo::lowerCRRestore(), llvm::PPCRegisterInfo::lowerVRSAVERestore(), llvm::AArch64InstrInfo::optimizeCompareInstr(), llvm::PPCInstrInfo::optimizeCompareInstr(), and llvm::rewriteT2FrameIndex().

◆ defs() [1/2]

iterator_range<mop_iterator> llvm::MachineInstr::defs ( )

inline

Returns a range over all explicit operands that are register definitions.

Implicit definition are not included!

Definition at line 481 of file MachineInstr.h.

References getNumExplicitDefs(), llvm::make_range(), and operands_begin().

Referenced by addRegsToSet(), llvm::biasPhysReg(), llvm::createSIWholeQuadModePass(), llvm::SplitEditor::dump(), findSingleRegDef(), INITIALIZE_PASS(), instModifiesReg(), isCrossCopy(), llvm::WebAssemblyMCInstLower::Lower(), llvm::GCNUpwardRPTracker::recede(), and false::Chain::str().

◆ defs() [2/2]

iterator_range<const_mop_iterator> llvm::MachineInstr::defs ( ) const

inline

Returns a range over all explicit operands that are register definitions.

Implicit definition are not included!

Definition at line 486 of file MachineInstr.h.

References getNumExplicitDefs(), llvm::make_range(), and operands_begin().

◆ dropMemRefs()

void MachineInstr::dropMemRefs ( MachineFunction & MF )

Clear this MachineInstr's memory reference descriptor list.

This resets the memrefs to their most conservative state. This should be used only as a last resort since it greatly pessimizes our knowledge of the memory access performed by the instruction.

Definition at line 319 of file MachineInstr.cpp.

References llvm::MachineFunction::createMIExtraInfo(), getPostInstrSymbol(), getPreInstrSymbol(), and memoperands_empty().

Referenced by cloneMergedMemRefs(), INITIALIZE_PASS(), setDebugLoc(), and setMemRefs().

◆ dump()

LLVM_DUMP_METHOD void MachineInstr::dump ( ) const

Definition at line 1430 of file MachineInstr.cpp.

References llvm::dbgs(), and print().

Referenced by canMoveInstsAcrossMemOp(), llvm::HexagonPacketizerList::canPromoteToDotCur(), llvm::HexagonPacketizerList::cleanUpDotCur(), computeBranchTargetAndInversion(), llvm::PPCInstrInfo::convertToImmediateForm(), llvm::createX86OptimizeLEAs(), doCandidateWalk(), llvm::ScheduleDAGInstrs::dumpNode(), llvm::AArch64TargetLowering::EmitInstrWithCustomInserter(), findPotentialBlockers(), fixupRegionExits(), getNewValueJumpOpcode(), getReassignedChan(), getRegClassForUnfoldedLoad(), INITIALIZE_PASS(), llvm::SMSchedule::insert(), llvm::HexagonInstrInfo::invertAndChangeJumpTarget(), isDataInvariant(), isDataInvariantLoad(), isDbgValueDescribedByReg(), isEFLAGSLive(), isIntersect(), llvm::HexagonInstrInfo::isLateInstrFeedsEarlyInstr(), isLEASimpleIncOrDec(), isNopCopy(), isPHIRegionIndex(), isRegTiedToDefOperand(), MoveAndTeeForMultiUse(), MoveForSingleUse(), llvm::AggressiveAntiDepBreaker::Observe(), packCmovGroup(), populateCandidates(), llvm::HexagonInstrInfo::PredicateInstruction(), RematerializeCheapDef(), removeRedundantBlockingStores(), llvm::HexagonInstrInfo::reversePredSense(), swapMIOperands(), and updateOperandRegConstraints().

◆ emitError()

void MachineInstr::emitError ( StringRef Msg ) const

Emit an error referring to the source location of this instruction.

This should only be used for inline assembly that is somehow impossible to compile. Other errors should have been handled much earlier.

If this method returns, the caller should try to recover from the error.

Definition at line 1965 of file MachineInstr.cpp.

References llvm::LLVMContext::emitError(), llvm::Module::getContext(), llvm::MachineFunction::getMMI(), llvm::MachineModuleInfo::getModule(), getNumOperands(), llvm::MDNode::getNumOperands(), getOperand(), llvm::MDNode::getOperand(), getParent(), and llvm::report_fatal_error().

Referenced by llvm::RegAllocBase::allocatePhysRegs(), getDebugLoc(), INITIALIZE_PASS(), and llvm::LowerARMMachineInstrToMCInst().

◆ eraseFromBundle()

void MachineInstr::eraseFromBundle ( )

Unlink 'this' form its basic block and delete it.

If the instruction is part of a bundle, the other instructions in the bundle remain bundled.

Definition at line 683 of file MachineInstr.cpp.

References assert(), llvm::MachineBasicBlock::erase_instr(), and getParent().

Referenced by VerifyLowRegs().

◆ eraseFromParent()

void MachineInstr::eraseFromParent ( )

Unlink 'this' from the containing basic block and delete it.

If this instruction is the header of a bundle, the whole bundle is erased. This function can not be used for instructions inside a bundle, use eraseFromBundle() to erase individual bundled instructions.

Definition at line 658 of file MachineInstr.cpp.

References assert(), llvm::MachineBasicBlock::erase(), and getParent().

◆ eraseFromParentAndMarkDBGValuesForRemoval()

void MachineInstr::eraseFromParentAndMarkDBGValuesForRemoval ( )

Unlink 'this' from the containing basic block and delete it.

For all definitions mark their uses in DBG_VALUE nodes as undefined. Otherwise like eraseFromParent().

Definition at line 663 of file MachineInstr.cpp.

References assert(), eraseFromParent(), llvm::MachineBasicBlock::getParent(), getParent(), llvm::MachineFunction::getRegInfo(), llvm::TargetRegisterInfo::isVirtualRegister(), llvm::MachineRegisterInfo::markUsesInDebugValueAsUndef(), operands(), and Reg.

Referenced by llvm::Combiner::combineMachineInstrs(), INITIALIZE_PASS(), llvm::InstructionSelect::runOnMachineFunction(), and llvm::Legalizer::runOnMachineFunction().

◆ explicit_operands() [1/2]

iterator_range<mop_iterator> llvm::MachineInstr::explicit_operands ( )

inline

Definition at line 465 of file MachineInstr.h.

References getNumExplicitOperands(), llvm::make_range(), and operands_begin().

Referenced by getConstant(), getVariantKind(), implicit_operands(), and usesExtendedRegister().

◆ explicit_operands() [2/2]

iterator_range<const_mop_iterator> llvm::MachineInstr::explicit_operands ( ) const

inline

Definition at line 469 of file MachineInstr.h.

References getNumExplicitOperands(), llvm::make_range(), and operands_begin().

◆ explicit_uses() [1/2]

iterator_range<mop_iterator> llvm::MachineInstr::explicit_uses ( )

inline

Definition at line 499 of file MachineInstr.h.

References getNumExplicitDefs(), getNumExplicitOperands(), llvm::make_range(), and operands_begin().

Referenced by findSingleRegDef(), findStartOfTree(), llvm::WebAssemblyMCInstLower::Lower(), and MoveAndTeeForMultiUse().

◆ explicit_uses() [2/2]

iterator_range<const_mop_iterator> llvm::MachineInstr::explicit_uses ( ) const

inline

Definition at line 503 of file MachineInstr.h.

References getNumExplicitDefs(), getNumExplicitOperands(), llvm::make_range(), and operands_begin().

◆ findFirstPredOperandIdx()

int MachineInstr::findFirstPredOperandIdx ( ) const

Find the index of the first operand in the operand list that is used to represent the predicate.

findFirstPredOperandIdx() - Find the index of the first operand in the operand list that is used to represent the predicate.

It returns -1 if none is found.

Definition at line 1006 of file MachineInstr.cpp.

References getDesc(), getNumOperands(), llvm::MCInstrDesc::isPredicable(), llvm::MCOperandInfo::isPredicate(), and llvm::MCInstrDesc::OpInfo.

Referenced by llvm::ARMBaseInstrInfo::commuteInstructionImpl(), llvm::ARMFrameLowering::determineCalleeSaves(), llvm::ThumbRegisterInfo::eliminateFrameIndex(), llvm::ARMBaseRegisterInfo::eliminateFrameIndex(), findRegisterDefOperand(), llvm::getInstrPredicate(), llvm::ARMBaseInstrInfo::getPredicate(), llvm::ARMBaseInstrInfo::isPredicated(), llvm::R600InstrInfo::isPredicated(), llvm::ARMBaseInstrInfo::PredicateInstruction(), and llvm::R600InstrInfo::PredicateInstruction().

◆ findInlineAsmFlagIdx()

int MachineInstr::findInlineAsmFlagIdx	(	unsigned	OpIdx,
		unsigned *	GroupNo = `nullptr`
	)		const

Find the index of the flag word operand that corresponds to operand OpIdx on an inline asm instruction.

Returns -1 if getOperand(OpIdx) does not belong to an inline asm operand group.

If GroupNo is not NULL, it will receive the number of the operand group containing OpIdx.

The flag operand is an immediate that can be decoded with methods like InlineAsm::hasRegClassConstraint().

Definition at line 772 of file MachineInstr.cpp.

References assert(), llvm::MachineOperand::getImm(), llvm::InlineAsm::getNumOperandRegisters(), getNumOperands(), getOperand(), llvm::MachineOperand::isImm(), isInlineAsm(), and llvm::InlineAsm::MIOp_FirstOperand.

Referenced by addRegisterDead(), addRegisterKilled(), findRegisterDefOperand(), and getRegClassConstraint().

◆ findRegisterDefOperand()

MachineOperand* llvm::MachineInstr::findRegisterDefOperand	(	unsigned	Reg,
		bool	isDead = `false`,
		const TargetRegisterInfo *	TRI = `nullptr`
	)

inline

Wrapper for findRegisterDefOperandIdx, it returns a pointer to the MachineOperand rather than an index.

Definition at line 1200 of file MachineInstr.h.

References findFirstPredOperandIdx(), findInlineAsmFlagIdx(), findRegisterDefOperandIdx(), findTiedOperandIdx(), getOperand(), getRegClassConstraint(), getRegClassConstraintEffect(), getRegClassConstraintEffectForVReg(), tieOperands(), TII, and TRI.

Referenced by addRegisterDefined(), llvm::SystemZInstrInfo::foldMemoryOperandImpl(), llvm::LiveVariables::HandleVirtRegDef(), isDataInvariant(), isDataInvariantLoad(), llvm::AggressiveAntiDepBreaker::Observe(), transferDeadCC(), and UpdateCPSRUse().

◆ findRegisterDefOperandIdx()

int MachineInstr::findRegisterDefOperandIdx	(	unsigned	Reg,
		bool	isDead = `false`,
		bool	Overlap = `false`,
		const TargetRegisterInfo *	TRI = `nullptr`
	)		const

Returns the operand index that is a def of the specified register or -1 if it is not found.

findRegisterDefOperandIdx() - Returns the operand index that is a def of the specified register or -1 if it is not found.

If isDead is true, defs that are not dead are skipped. If Overlap is true, then it also looks for defs that merely overlap the specified register. If TargetRegisterInfo is non-null, then it also checks if there is a def of a super-register. This may also return a register mask operand when Overlap is true.

If isDead is true, defs that are not dead are skipped. If TargetRegisterInfo is non-null, then it also checks if there is a def of a super-register.

Definition at line 977 of file MachineInstr.cpp.

References llvm::MachineOperand::clobbersPhysReg(), getNumOperands(), getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::isDead(), llvm::MachineOperand::isDef(), llvm::TargetRegisterInfo::isPhysicalRegister(), llvm::MachineOperand::isReg(), llvm::MachineOperand::isRegMask(), llvm::MCRegisterInfo::isSubRegister(), Reg, and llvm::TargetRegisterInfo::regsOverlap().

Referenced by addSegmentsWithValNo(), canFoldIntoCSel(), CriticalPathStep(), llvm::R600InstrInfo::definesAddressRegister(), definesRegister(), llvm::ARMBaseInstrInfo::expandPostRAPseudo(), findRegisterDefOperand(), findRegisterUseOperand(), getCompareSourceReg(), getMaddPatterns(), llvm::HexagonInstrInfo::getOperandLatency(), modifiesRegister(), llvm::AArch64InstrInfo::optimizeCompareInstr(), llvm::AArch64InstrInfo::optimizeCondBranch(), and registerDefIsDead().

◆ findRegisterUseOperand() [1/2]

MachineOperand* llvm::MachineInstr::findRegisterUseOperand	(	unsigned	Reg,
		bool	isKill = `false`,
		const TargetRegisterInfo *	TRI = `nullptr`
	)

inline

Wrapper for findRegisterUseOperandIdx, it returns a pointer to the MachineOperand rather than an index.

Definition at line 1175 of file MachineInstr.h.

References findRegisterUseOperandIdx(), getOperand(), isKill(), and TRI.

Referenced by addEpilogOnlyR10(), findRegisterUseOperand(), getRegClassForUnfoldedLoad(), hasVulnerableLoad(), isCopy(), isEFLAGSLive(), llvm::AggressiveAntiDepBreaker::Observe(), regOverlapsSet(), and UpdateCPSRUse().

◆ findRegisterUseOperand() [2/2]

const MachineOperand* llvm::MachineInstr::findRegisterUseOperand	(	unsigned	Reg,
		bool	isKill = `false`,
		const TargetRegisterInfo *	TRI = `nullptr`
	)		const

inline

Definition at line 1181 of file MachineInstr.h.

References findRegisterDefOperandIdx(), findRegisterUseOperand(), isKill(), and TRI.

◆ findRegisterUseOperandIdx()

int MachineInstr::findRegisterUseOperandIdx	(	unsigned	Reg,
		bool	isKill = `false`,
		const TargetRegisterInfo *	TRI = `nullptr`
	)		const

Returns the operand index that is a use of the specific register or -1 if it is not found.

findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of the specific register or -1 if it is not found.

It further tightens the search criteria to a use that kills the register if isKill is true.

Definition at line 928 of file MachineInstr.cpp.

References getNumOperands(), getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::isKill(), llvm::MachineOperand::isReg(), llvm::MachineOperand::isUse(), and llvm::TargetRegisterInfo::regsOverlap().

Referenced by findCondCodeUsedByInstr(), findRegisterUseOperand(), llvm::HexagonInstrInfo::getOperandLatency(), llvm::ARMBaseInstrInfo::getPartialRegUpdateClearance(), llvm::CoalescerPair::isCoalescable(), isVirtualRegisterOperand(), killsRegister(), readsRegister(), registerDefIsDead(), llvm::PPCInstrInfo::replaceInstrOperandWithImm(), and llvm::R600InstrInfo::usesAddressRegister().

◆ findTiedOperandIdx()

unsigned MachineInstr::findTiedOperandIdx ( unsigned OpIdx ) const

Given the index of a tied register operand, find the operand it is tied to.

Defs are tied to uses and vice versa. Returns the index of the tied operand which must exist.

Definition at line 1061 of file MachineInstr.cpp.

References assert(), llvm::MachineOperand::getImm(), llvm::InlineAsm::getNumOperandRegisters(), getNumOperands(), getOperand(), llvm::MachineOperand::isImm(), isInlineAsm(), llvm::MachineOperand::isReg(), llvm::MachineOperand::isTied(), llvm::MachineOperand::isUse(), llvm::InlineAsm::isUseOperandTiedToDef(), llvm_unreachable, llvm::InlineAsm::MIOp_FirstOperand, llvm::SmallVectorTemplateBase< T, bool >::push_back(), and llvm::SmallVectorBase::size().

Referenced by findRegisterDefOperand(), findSingleRegDef(), hasComplexRegisterTies(), INITIALIZE_PASS(), isRegTiedToDefOperand(), isRegTiedToUseOperand(), matchPair(), llvm::MIPrinter::print(), print(), untieRegOperand(), and llvm::SIInstrInfo::verifyInstruction().

◆ getAsmPrinterFlag()

bool llvm::MachineInstr::getAsmPrinterFlag ( CommentFlag Flag ) const

inline

Return whether an AsmPrinter flag is set.

Definition at line 275 of file MachineInstr.h.

Referenced by emitComments(), and llvm::X86AsmPrinter::EmitInstruction().

◆ getAsmPrinterFlags()

uint8_t llvm::MachineInstr::getAsmPrinterFlags ( ) const

inline

Return the asm printer flags bitvector.

Definition at line 269 of file MachineInstr.h.

Referenced by llvm::X86AsmPrinter::EmitInstruction().

◆ getBundleSize()

unsigned MachineInstr::getBundleSize ( ) const

Return the number of instructions inside the MI bundle, excluding the bundle header.

Return the number of instructions inside the MI bundle, not counting the header instruction.

This is the number of instructions that MachineBasicBlock::iterator skips, 0 for unbundled instructions.

Definition at line 904 of file MachineInstr.cpp.

References llvm::ilist_node_impl< ilist_detail::compute_node_options< MachineInstr, Options... >::type >::getIterator(), I, and Size.

Referenced by INITIALIZE_PASS(), and isTransient().

◆ getDebugExpression()

const DIExpression * MachineInstr::getDebugExpression ( ) const

Return the complex address expression referenced by this DBG_VALUE instruction.

Definition at line 810 of file MachineInstr.cpp.

References assert(), llvm::MachineOperand::getMetadata(), getOperand(), and isDebugValue().

Referenced by AssignProtectedObjSet(), computeExprForSpill(), llvm::createX86OptimizeLEAs(), emitDebugValueComment(), llvm::DbgVariableLocation::extractFromMachineInstruction(), getDebugLoc(), getDebugLocValue(), INITIALIZE_PASS(), llvm::DbgVariable::initializeDbgValue(), printExtendedName(), and llvm::SelectionDAGISel::runOnMachineFunction().

◆ getDebugLabel()

const DILabel * MachineInstr::getDebugLabel ( ) const

Return the debug label referenced by this DBG_LABEL instruction.

Definition at line 800 of file MachineInstr.cpp.

References assert(), llvm::MachineOperand::getMetadata(), getOperand(), and isDebugLabel().

Referenced by llvm::MachineInstrBuilder::addMetadata(), emitDebugLabelComment(), and getDebugLoc().

◆ getDebugLoc()

const DebugLoc& llvm::MachineInstr::getDebugLoc ( ) const

inline

Returns the debug location id of this MachineInstr.

Definition at line 383 of file MachineInstr.h.

References emitError(), getDebugExpression(), getDebugLabel(), and getDebugVariable().

◆ getDebugVariable()

const DILocalVariable * MachineInstr::getDebugVariable ( ) const

Return the debug variable referenced by this DBG_VALUE instruction.

Definition at line 805 of file MachineInstr.cpp.

References assert(), llvm::MachineOperand::getMetadata(), getOperand(), and isDebugValue().

Referenced by llvm::MachineInstrBuilder::addMetadata(), llvm::buildDbgValueForSpill(), computeExprForSpill(), llvm::createX86OptimizeLEAs(), emitDebugValueComment(), getDebugLoc(), INITIALIZE_PASS(), llvm::DbgVariable::initializeDbgValue(), isDbgValueDescribedByReg(), printExtendedName(), and llvm::SelectionDAGISel::runOnMachineFunction().

◆ getDesc()

const MCInstrDesc& llvm::MachineInstr::getDesc ( ) const

inline

Returns the target instruction descriptor of this MachineInstr.

Definition at line 406 of file MachineInstr.h.

◆ getFlag()

bool llvm::MachineInstr::getFlag ( MIFlag Flag ) const

inline

Return whether an MI flag is set.

Definition at line 295 of file MachineInstr.h.

Referenced by llvm::BTFDebug::beginInstruction(), llvm::CodeViewDebug::beginInstruction(), llvm::DwarfDebug::beginInstruction(), llvm::ARMAsmPrinter::EmitInstruction(), llvm::ARMAsmPrinter::EmitJumpTableTBInst(), getOModValue(), isBundledWithPred(), isBundledWithSucc(), isInsideBundle(), llvm::MIPrinter::print(), llvm::MachineBasicBlock::print(), and print().

◆ getFlags()

uint16_t llvm::MachineInstr::getFlags ( ) const

inline

Return the MI flags bitvector.

Definition at line 290 of file MachineInstr.h.

Referenced by llvm::GISelInstProfileBuilder::addNodeID(), IsMovepDestinationRegPair(), mergeFlagsWith(), and VerifyLowRegs().

◆ getInlineAsmDialect()

InlineAsm::AsmDialect MachineInstr::getInlineAsmDialect ( ) const

Definition at line 766 of file MachineInstr.cpp.

References assert(), llvm::InlineAsm::Extra_AsmDialect, llvm::MachineOperand::getImm(), getOperand(), isInlineAsm(), and llvm::InlineAsm::MIOp_ExtraInfo.

Referenced by EmitGCCInlineAsmStr(), isMSInlineAsm(), and print().

◆ getMF() [1/2]

const MachineFunction * MachineInstr::getMF ( ) const

Return the function that contains the basic block that this instruction belongs to.

Note: this is undefined behaviour if the instruction does not have a parent.

Definition at line 644 of file MachineInstr.cpp.

References llvm::MachineBasicBlock::getParent(), and getParent().

Referenced by llvm::BTFDebug::beginInstruction(), llvm::DwarfDebug::beginInstruction(), canFoldCopy(), cloneMemRefs(), cloneMergedMemRefs(), llvm::TargetInstrInfo::commuteInstructionImpl(), llvm::TargetSchedModel::computeOutputLatency(), emitComments(), llvm::TargetLoweringBase::emitPatchPoint(), llvm::TargetLoweringBase::emitXRayCustomEvent(), llvm::TargetLoweringBase::emitXRayTypedEvent(), llvm::LegalizerHelper::fewerElementsVector(), llvm::TargetInstrInfo::genAlternativeCodeSequence(), llvm::NVPTXAsmPrinter::getFunctionFrameSymbol(), llvm::RegisterBankInfo::getInstrMappingImpl(), getMF(), getParent(), getRegClassConstraint(), llvm::TargetInstrInfo::getSPAdjust(), INITIALIZE_PASS(), isCallerPreservedOrConstPhysReg(), isCopyFeedingInvariantStore(), isInvariantStore(), lookupCandidateBaseReg(), mayAlias(), llvm::MIPrinter::print(), llvm::RegisterBankInfo::OperandsMapper::print(), llvm::printMBBReference(), llvm::TargetInstrInfo::reassociateOps(), llvm::AsmPrinter::recordSled(), removePhis(), llvm::GCNRPTracker::reset(), llvm::RegScavenger::scavengeRegister(), llvm::CoalescerPair::setRegisters(), UpdatePredRedefs(), llvm::RegisterBankInfo::InstructionMapping::verify(), VisitGlobalVariableForEmission(), and llvm::LegalizerHelper::widenScalar().

◆ getMF() [2/2]

MachineFunction* llvm::MachineInstr::getMF ( )

inline

Definition at line 263 of file MachineInstr.h.

References getMF().

◆ getNumDefs()

unsigned llvm::MachineInstr::getNumDefs ( ) const

inline

Returns the total number of definitions.

Definition at line 424 of file MachineInstr.h.

References getNumExplicitDefs(), and llvm::MCInstrDesc::getNumImplicitDefs().

Referenced by isCallerPreservedOrConstPhysReg().

◆ getNumExplicitDefs()

unsigned MachineInstr::getNumExplicitDefs ( ) const

Returns the number of non-implicit definitions.

Definition at line 707 of file MachineInstr.cpp.

References E, llvm::MCInstrDesc::getNumDefs(), getNumOperands(), getOperand(), I, llvm::MachineOperand::isDef(), llvm::MachineOperand::isImplicit(), llvm::MachineOperand::isReg(), and llvm::MCInstrDesc::isVariadic().

Referenced by defs(), explicit_uses(), getNumDefs(), isOperandSubregIdx(), and uses().

◆ getNumExplicitOperands()

unsigned MachineInstr::getNumExplicitOperands ( ) const

Returns the number of non-implicit operands.

Definition at line 688 of file MachineInstr.cpp.

References E, llvm::MCInstrDesc::getNumOperands(), getNumOperands(), getOperand(), I, llvm::MachineOperand::isImplicit(), llvm::MachineOperand::isReg(), and llvm::MCInstrDesc::isVariadic().

Referenced by llvm::HexagonInstrInfo::analyzeBranch(), llvm::SystemZInstrInfo::analyzeCompare(), llvm::SIInstrInfo::buildExtractSubRegOrImm(), changeFCMPPredToAArch64CC(), llvm::constrainSelectedInstRegOperands(), createPHIsForSelects(), llvm::createSIWholeQuadModePass(), llvm::createX86FixupBWInsts(), explicit_operands(), explicit_uses(), fixupCalleeSaveRestoreStackOffset(), llvm::SystemZInstrInfo::foldMemoryOperandImpl(), llvm::RISCVInstrInfo::getBranchDestBlock(), getCompareSourceReg(), llvm::AArch64InstrInfo::getMemOpBaseRegImmOfsOffsetOperand(), llvm::MipsInstrInfo::GetMemOperand(), llvm::AArch64InstrInfo::getMemOperandWithOffsetWidth(), getRegClassFromGRPhysReg(), getTypeToPrint(), getUnconditionalBrDisp(), hoistAndMergeSGPRInits(), INITIALIZE_PASS(), isCompareZero(), isOperandSubregIdx(), performCustomAdjustments(), and llvm::SIInstrInfo::verifyInstruction().

◆ getNumMemOperands()

unsigned llvm::MachineInstr::getNumMemOperands ( ) const

inline

Return the number of memory operands.

Definition at line 552 of file MachineInstr.h.

References memoperands().

◆ getNumOperands()

unsigned llvm::MachineInstr::getNumOperands ( ) const

inline

Retuns the total number of operands.

Definition at line 412 of file MachineInstr.h.

◆ getOpcode()

unsigned llvm::MachineInstr::getOpcode ( ) const

inline

Returns the opcode of this MachineInstr.

Definition at line 409 of file MachineInstr.h.

References llvm::MCInstrDesc::Opcode.

◆ getOperand() [1/2]

const MachineOperand& llvm::MachineInstr::getOperand ( unsigned i ) const

inline

Definition at line 414 of file MachineInstr.h.

References assert(), and getNumOperands().

◆ getOperand() [2/2]

MachineOperand& llvm::MachineInstr::getOperand ( unsigned i )

inline

Definition at line 418 of file MachineInstr.h.

References assert(), and getNumOperands().

◆ getOperandNo()

unsigned llvm::MachineInstr::getOperandNo ( const_mop_iterator I ) const

inline

Returns the number of the operand iterator I points to.

Definition at line 509 of file MachineInstr.h.

References operands_begin().

Referenced by llvm::ScheduleDAGInstrs::addSchedBarrierDeps(), findSingleRegDef(), findStartOfTree(), llvm::Localizer::getAnalysisUsage(), getDataDeps(), isCandidateStore(), isCrossCopy(), llvm::SIInstrInfo::isInlineConstant(), isKImmOperand(), isKUImmOperand(), isUseSafeToFold(), tryChangeVGPRtoSGPRinCopy(), tryFoldInst(), updateOperand(), updatePhysDepsDownwards(), and updatePhysDepsUpwards().

◆ getParent() [1/2]

const MachineBasicBlock* llvm::MachineInstr::getParent ( ) const

inline

Definition at line 254 of file MachineInstr.h.

◆ getParent() [2/2]

MachineBasicBlock* llvm::MachineInstr::getParent ( )

inline

Definition at line 255 of file MachineInstr.h.

References getMF().

◆ getPostInstrSymbol()

MCSymbol* llvm::MachineInstr::getPostInstrSymbol ( ) const

inline

Helper to extract a post-instruction symbol if one has been added.

Definition at line 567 of file MachineInstr.h.

Referenced by cloneMemRefs(), dropMemRefs(), llvm::MIPrinter::print(), print(), setMemRefs(), setPostInstrSymbol(), and setPreInstrSymbol().

◆ getPreInstrSymbol()

MCSymbol* llvm::MachineInstr::getPreInstrSymbol ( ) const

inline

Helper to extract a pre-instruction symbol if one has been added.

Definition at line 555 of file MachineInstr.h.

Referenced by cloneMemRefs(), dropMemRefs(), llvm::MIPrinter::print(), print(), setMemRefs(), setPostInstrSymbol(), and setPreInstrSymbol().

◆ getRegClassConstraint()

const TargetRegisterClass * MachineInstr::getRegClassConstraint	(	unsigned	OpIdx,
		const TargetInstrInfo *	TII,
		const TargetRegisterInfo *	TRI
	)		const

Compute the static register class constraint for operand OpIdx.

For normal instructions, this is derived from the MCInstrDesc. For inline assembly it is derived from the flag words.

Returns NULL if the static register class constraint cannot be determined.

Definition at line 816 of file MachineInstr.cpp.

References assert(), findInlineAsmFlagIdx(), getDesc(), llvm::MachineOperand::getImm(), llvm::InlineAsm::getKind(), getMF(), getOperand(), getParent(), llvm::TargetRegisterInfo::getPointerRegClass(), llvm::TargetInstrInfo::getRegClass(), llvm::TargetRegisterInfo::getRegClass(), llvm::InlineAsm::hasRegClassConstraint(), isInlineAsm(), isReg(), isRegTiedToDefOperand(), llvm::InlineAsm::Kind_Mem, llvm::InlineAsm::Kind_RegDef, llvm::InlineAsm::Kind_RegDefEarlyClobber, and llvm::InlineAsm::Kind_RegUse.

Referenced by findRegisterDefOperand(), llvm::RegisterBankInfo::getRegBankFromConstraints(), getRegClassConstraintEffect(), getRegsUsedByPHIs(), isNopCopy(), llvm::TargetInstrInfo::reassociateOps(), UpdateOperandRegClass(), and llvm::SIInstrInfo::verifyInstruction().

◆ getRegClassConstraintEffect()

const TargetRegisterClass * MachineInstr::getRegClassConstraintEffect	(	unsigned	OpIdx,
		const TargetRegisterClass *	CurRC,
		const TargetInstrInfo *	TII,
		const TargetRegisterInfo *	TRI
	)		const

Applies the constraints (def/use) implied by the OpIdx operand to the given CurRC.

Returns the register class that satisfies both CurRC and the constraints set by OpIdx MI. Returns NULL if such a register class does not exist.

Precondition: CurRC must not be NULL.; The operand at OpIdx must be a register.

Definition at line 884 of file MachineInstr.cpp.

References assert(), llvm::TargetRegisterInfo::getCommonSubClass(), llvm::TargetRegisterInfo::getMatchingSuperRegClass(), getOperand(), getRegClassConstraint(), llvm::TargetRegisterInfo::getSubClassWithSubReg(), llvm::MachineOperand::getSubReg(), and llvm::MachineOperand::isReg().

Referenced by findRegisterDefOperand(), getRegClassConstraintEffectForVReg(), and llvm::MachineRegisterInfo::recomputeRegClass().

◆ getRegClassConstraintEffectForVReg()

const TargetRegisterClass * MachineInstr::getRegClassConstraintEffectForVReg	(	unsigned	Reg,
		const TargetRegisterClass *	CurRC,
		const TargetInstrInfo *	TII,
		const TargetRegisterInfo *	TRI,
		bool	ExploreBundle = `false`
	)		const

Applies the constraints (def/use) implied by this MI on Reg to the given CurRC.

If ExploreBundle is set and MI is part of a bundle, all the instructions inside the bundle will be taken into account. In other words, this method accumulates all the constraints of the operand of this MI and the related bundle if MI is a bundle or inside a bundle.

Returns the register class that satisfies both CurRC and the constraints set by MI. Returns NULL if such a register class does not exist.

Precondition: CurRC must not be NULL.

Definition at line 855 of file MachineInstr.cpp.

References assert(), getOperand(), llvm::MachineOperand::getReg(), getRegClassConstraintEffect(), llvm::MachineOperand::isReg(), llvm::MachineOperandIteratorBase::isValid(), Reg, TII, and TRI.

Referenced by findRegisterDefOperand(), and getNumAllocatableRegsForConstraints().

◆ getTypeToPrint()

LLT MachineInstr::getTypeToPrint	(	unsigned	OpIdx,
		SmallBitVector &	PrintedTypes,
		const MachineRegisterInfo &	MRI
	)		const

Debugging supportDetermine the generic type to be printed (if needed) on uses and defs.

Definition at line 1405 of file MachineInstr.cpp.

References getDesc(), getNumExplicitOperands(), getOperand(), llvm::MachineOperand::getReg(), llvm::MachineRegisterInfo::getType(), llvm::MachineOperand::isReg(), llvm::LLT::isValid(), isVariadic(), llvm::MCInstrDesc::OpInfo, and llvm::SmallBitVector::set().

Referenced by isRegTiedToDefOperand(), llvm::MIPrinter::print(), and print().

◆ hasComplexRegisterTies()

bool MachineInstr::hasComplexRegisterTies ( ) const

Return true when an instruction has tied register that can't be determined by the instruction's descriptor.

This is useful for MIR printing, to determine whether we need to print the ties or not.

Definition at line 1390 of file MachineInstr.cpp.

References E, findTiedOperandIdx(), getDesc(), getNumOperands(), getOperand(), llvm::MCInstrDesc::getOperandConstraint(), I, and llvm::MCOI::TIED_TO.

Referenced by isRegTiedToDefOperand(), llvm::MIPrinter::print(), and print().

◆ hasDelaySlot()

bool llvm::MachineInstr::hasDelaySlot ( QueryType Type = AnyInBundle ) const

inline

Returns true if the specified instruction has a delay slot which must be filled by the code generator.

Definition at line 741 of file MachineInstr.h.

References llvm::MCID::DelaySlot, and hasProperty().

Referenced by llvm::DwarfDebug::beginInstruction(), and hasUnoccupiedSlot().

◆ hasExtraDefRegAllocReq()

bool llvm::MachineInstr::hasExtraDefRegAllocReq ( QueryType Type = AnyInBundle ) const

inline

Returns true if this instruction def operands have special register allocation requirements that are not captured by the operand register classes.

e.g. ARM::LDRD's two def registers must be an even / odd pair, ARM::LDM registers have to be in ascending order. Post-register allocation passes should not attempt to change allocations for definitions of instructions with this flag.

Definition at line 927 of file MachineInstr.h.

References llvm::MCID::ExtraDefRegAllocReq, and hasProperty().

Referenced by CriticalPathStep(), and llvm::MachineOperand::isRenamable().

◆ hasExtraSrcRegAllocReq()

bool llvm::MachineInstr::hasExtraSrcRegAllocReq ( QueryType Type = AnyInBundle ) const

inline

Returns true if this instruction source operands have special register allocation requirements that are not captured by the operand register classes.

e.g. ARM::STRD's two source registers must be an even / odd pair, ARM::STM registers have to be in ascending order. Post-register allocation passes should not attempt to change allocations for sources of instructions with this flag.

Definition at line 917 of file MachineInstr.h.

References llvm::MCID::ExtraSrcRegAllocReq, and hasProperty().

Referenced by CriticalPathStep(), and llvm::MachineOperand::isRenamable().

◆ hasOneMemOperand()

bool llvm::MachineInstr::hasOneMemOperand ( ) const

inline

◆ hasOptionalDef()

bool llvm::MachineInstr::hasOptionalDef ( QueryType Type = IgnoreBundle ) const

inline

Set if this instruction has an optional definition, e.g.

ARM instructions which can set condition code if 's' bit is set.

Definition at line 613 of file MachineInstr.h.

References llvm::MCID::HasOptionalDef, and hasProperty().

Referenced by isCopy(), and llvm::ARMBaseInstrInfo::optimizeSelect().

◆ hasOrderedMemoryRef()

bool MachineInstr::hasOrderedMemoryRef ( ) const

Return true if this instruction may have an ordered or volatile memory reference, or if the information describing the memory reference is not available.

hasOrderedMemoryRef - Return true if this instruction may have an ordered or volatile memory reference, or if the information describing the memory reference is not available.

Return false if it is known to have no ordered or volatile memory references.

Return false if it is known to have no ordered memory references.

Definition at line 1273 of file MachineInstr.cpp.

References llvm::any_of(), hasUnmodeledSideEffects(), isCall(), llvm::MachineMemOperand::isUnordered(), mayLoad(), mayStore(), memoperands(), and memoperands_empty().

Referenced by areCandidatesToMergeOrPair(), llvm::LanaiInstrInfo::areMemAccessesTriviallyDisjoint(), llvm::AArch64InstrInfo::areMemAccessesTriviallyDisjoint(), llvm::SIInstrInfo::areMemAccessesTriviallyDisjoint(), llvm::HexagonInstrInfo::areMemAccessesTriviallyDisjoint(), canMoveInstsAcrossMemOp(), llvm::AArch64InstrInfo::isCandidateToMergeOrPair(), isDependenceBarrier(), isGlobalMemoryObject(), llvm::HexagonPacketizerList::isLegalToPacketizeTogether(), llvm::SwingSchedulerDAG::isLoopCarriedDep(), isRegTiedToDefOperand(), isSafeToMove(), DeadCodeElimination::SetQueue< T >::push_back(), and Query().

◆ hasPostISelHook()

bool llvm::MachineInstr::hasPostISelHook ( QueryType Type = IgnoreBundle ) const

inline

Return true if this instruction requires adjustment after instruction selection by calling a target hook.

For example, this can be used to fill in ARM 's' optional operand depending on whether the conditional flag register is used.

Definition at line 886 of file MachineInstr.h.

References llvm::MCID::HasPostISelHook, and hasProperty().

◆ hasProperty()

bool llvm::MachineInstr::hasProperty	(	unsigned	MCFlag,
		QueryType	Type = `AnyInBundle`
	)		const

inline

Return true if the instruction (or in the case of a bundle, the instructions inside the bundle) has the specified property.

The first argument is the property being queried. The second argument indicates whether the query should look inside instruction bundles.

Definition at line 592 of file MachineInstr.h.

References assert(), getDesc(), llvm::MCInstrDesc::getFlags(), IgnoreBundle, isBundled(), and isBundledWithPred().

Referenced by canFoldAsLoad(), hasDelaySlot(), hasExtraDefRegAllocReq(), hasExtraSrcRegAllocReq(), hasOptionalDef(), hasPostISelHook(), hasUnmodeledSideEffects(), isAsCheapAsAMove(), isBarrier(), isBitcast(), isBranch(), isCall(), isCommutable(), isCompare(), isConvergent(), isConvertibleTo3Addr(), isEHScopeReturn(), isExtractSubregLike(), isIndirectBranch(), isInsertSubregLike(), isMoveImmediate(), isMoveReg(), isNotDuplicable(), isPredicable(), isPseudo(), isRegSequenceLike(), isRematerializable(), isReturn(), isSelect(), isTerminator(), isVariadic(), mayLoad(), mayStore(), and usesCustomInsertionHook().

◆ hasRegisterImplicitUseOperand()

bool MachineInstr::hasRegisterImplicitUseOperand ( unsigned Reg ) const

Returns true if the MachineInstr has an implicit-use operand of exactly the given register (not considering sub/super-registers).

Definition at line 916 of file MachineInstr.cpp.

References getNumOperands(), getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::isImplicit(), llvm::MachineOperand::isReg(), llvm::MachineOperand::isUse(), and Reg.

Referenced by addEpilogOnlyR10(), registerDefIsDead(), and llvm::SIInstrInfo::verifyInstruction().

◆ hasUnmodeledSideEffects()

bool MachineInstr::hasUnmodeledSideEffects ( ) const

Return true if this instruction has side effects that are not modeled by mayLoad / mayStore, etc.

For all instructions, the property is encoded in MCInstrDesc::Flags (see MCInstrDesc::hasUnmodeledSideEffects(). The only exception is INLINEASM instruction, in which case the side effect property is encoded in one of its operands (see InlineAsm::Extra_HasSideEffect).

Definition at line 1350 of file MachineInstr.cpp.

References llvm::InlineAsm::Extra_HasSideEffects, llvm::MachineOperand::getImm(), getOperand(), hasProperty(), isInlineAsm(), llvm::InlineAsm::MIOp_ExtraInfo, and llvm::MCID::UnmodeledSideEffects.

Referenced by llvm::LanaiInstrInfo::areMemAccessesTriviallyDisjoint(), llvm::AArch64InstrInfo::areMemAccessesTriviallyDisjoint(), llvm::SIInstrInfo::areMemAccessesTriviallyDisjoint(), llvm::HexagonInstrInfo::areMemAccessesTriviallyDisjoint(), CanMovePastDMB(), llvm::TargetInstrInfo::genAlternativeCodeSequence(), hasOrderedMemoryRef(), INITIALIZE_PASS(), isCallerPreservedOrConstPhysReg(), isDependenceBarrier(), isGlobalMemoryObject(), isInvariantStore(), isLoadFoldBarrier(), llvm::SwingSchedulerDAG::isLoopCarriedDep(), llvm::InstructionSelector::isObviouslySafeToFold(), isRegTiedToDefOperand(), isSafeToMove(), isUnsafeToMoveAcross(), isVirtualRegisterOperand(), DeadCodeElimination::SetQueue< T >::push_back(), Query(), and regOverlapsSet().

◆ implicit_operands() [1/2]

iterator_range<mop_iterator> llvm::MachineInstr::implicit_operands ( )

inline

Definition at line 473 of file MachineInstr.h.

References llvm::sys::path::end(), explicit_operands(), llvm::make_range(), and operands_end().

Referenced by ContainsReg(), copyFlagsToImplicitVCC(), llvm::createX86FixupBWInsts(), llvm::createX86FixupSetCC(), findImplicitSGPRRead(), getPostIndexedLoadStoreOpcode(), INITIALIZE_PASS(), isNopCopy(), llvm::InstructionSelector::isObviouslySafeToFold(), and llvm::PPCInstrInfo::replaceInstrOperandWithImm().

◆ implicit_operands() [2/2]

iterator_range<const_mop_iterator> llvm::MachineInstr::implicit_operands ( ) const

inline

Definition at line 476 of file MachineInstr.h.

References llvm::sys::path::end(), explicit_operands(), llvm::make_range(), and operands_end().

◆ isAnnotationLabel()

bool llvm::MachineInstr::isAnnotationLabel ( ) const

inline

Definition at line 981 of file MachineInstr.h.

References llvm::ISD::ANNOTATION_LABEL, and getOpcode().

Referenced by isLabel().

◆ isAsCheapAsAMove()

bool llvm::MachineInstr::isAsCheapAsAMove ( QueryType Type = AllInBundle ) const

inline

Returns true if this instruction has the same cost (or less) than a move instruction.

This is useful during certain types of optimizations (e.g., remat during two-address conversion or machine licm) where we would like to remat or hoist the instruction, but not if it costs more than moving the instruction into the appropriate register. Note, we are not marking copies from and to the same register class with this flag.

Definition at line 906 of file MachineInstr.h.

References llvm::MCID::CheapAsAMove, and hasProperty().

Referenced by llvm::AArch64InstrInfo::isAsCheapAsAMove(), llvm::TargetInstrInfo::isAsCheapAsAMove(), and ShouldRematerialize().

◆ isBarrier()

bool llvm::MachineInstr::isBarrier ( QueryType Type = AnyInBundle ) const

inline

Returns true if the specified instruction stops control flow from executing the instruction immediately following it.

Examples include unconditional branches and return instructions.

Definition at line 640 of file MachineInstr.h.

References llvm::MCID::Barrier, and hasProperty().

Referenced by llvm::ScheduleDAGInstrs::addSchedBarrierDeps(), cannotCoexistAsymm(), llvm::MachineBasicBlock::getFallThrough(), llvm::ARMHazardRecognizer::getHazardType(), llvm::HexagonPacketizerList::hasControlDependence(), INITIALIZE_PASS(), isConditionalBranch(), isFpMulInstruction(), isUnconditionalBranch(), llvm::MSP430InstrInfo::isUnpredicatedTerminator(), llvm::X86InstrInfo::isUnpredicatedTerminator(), llvm::PPCInstrInfo::isUnpredicatedTerminator(), llvm::TargetInstrInfo::isUnpredicatedTerminator(), matchPair(), and ProfitableToMerge().

◆ isBitcast()

bool llvm::MachineInstr::isBitcast ( QueryType Type = IgnoreBundle ) const

inline

Return true if this instruction is a bitcast instruction.

Definition at line 711 of file MachineInstr.h.

References llvm::MCID::Bitcast, and hasProperty().

Referenced by getCopyRewriter().

◆ isBranch()

bool llvm::MachineInstr::isBranch ( QueryType Type = AnyInBundle ) const

inline

Returns true if this is a conditional, unconditional, or indirect branch.

Predicates below can be used to discriminate between these cases, and the TargetInstrInfo::AnalyzeBranch method can be used to get more information.

Definition at line 657 of file MachineInstr.h.

References llvm::MCID::Branch, and hasProperty().

Referenced by addLiveInRegs(), cannotCoexistAsymm(), llvm::BitTracker::MachineEvaluator::evaluate(), getCmpForPseudo(), llvm::rdf::DataFlowGraph::getNextShadow(), llvm::PPCInstrInfo::getOperandLatency(), llvm::ARMBaseInstrInfo::getOperandLatency(), getRegClassForUnfoldedLoad(), llvm::HexagonPacketizerList::hasControlDependence(), INITIALIZE_PASS(), llvm::HexagonInstrInfo::invertAndChangeJumpTarget(), isBranchRetTrap(), llvm::HexagonInstrInfo::isComplex(), llvm::HexagonInstrInfo::isCompoundBranchInstr(), isConditionalBranch(), isCopy(), llvm::rdf::TargetOperandInfo::isFixedReg(), llvm::HexagonPacketizerList::isLegalToPacketizeTogether(), llvm::HexagonInstrInfo::isNewValueJump(), llvm::HexagonInstrInfo::isTailCall(), isUnconditionalBranch(), llvm::MSP430InstrInfo::isUnpredicatedTerminator(), llvm::X86InstrInfo::isUnpredicatedTerminator(), llvm::PPCInstrInfo::isUnpredicatedTerminator(), llvm::TargetInstrInfo::isUnpredicatedTerminator(), llvm::rdf::operator<<(), llvm::X86InstrInfo::optimizeCompareInstr(), populateCandidates(), DeadCodeElimination::SetQueue< T >::push_back(), regOverlapsSet(), splitBlock(), and llvm::BitTracker::visit().

◆ isBundle()

bool llvm::MachineInstr::isBundle ( ) const

inline

Definition at line 1036 of file MachineInstr.h.

References getOpcode().

Referenced by llvm::HexagonInstrInfo::analyzeBranch(), llvm::TailDuplicator::canTailDuplicate(), llvm::TargetSchedModel::computeInstrLatency(), llvm::HexagonAsmPrinter::EmitInstruction(), llvm::MipsInstrInfo::findCommutedOpIndices(), llvm::TargetInstrInfo::findCommutedOpIndices(), llvm::HexagonInstrInfo::getBranchingInstrs(), llvm::HexagonInstrInfo::getBundleNoShuf(), llvm::ARMBaseInstrInfo::getOperandLatency(), llvm::HexagonInstrInfo::hasLoadFromStackSlot(), llvm::HexagonInstrInfo::hasStoreToStackSlot(), INITIALIZE_PASS(), isIdenticalTo(), IsMovepDestinationRegPair(), llvm::ARMBaseInstrInfo::isPredicable(), llvm::ARMBaseInstrInfo::isPredicated(), llvm::HexagonPacketizerList::isSoloInstruction(), llvm::TargetInstrInfo::PredicateInstruction(), llvm::HexagonPacketizerList::unpacketizeSoloInstrs(), and UpdateCPSRUse().

◆ isBundled()

bool llvm::MachineInstr::isBundled ( ) const

inline

Return true if this instruction part of a bundle.

This is true if either itself or its following instruction is marked "InsideBundle".

Definition at line 356 of file MachineInstr.h.

References isBundledWithPred(), and isBundledWithSucc().

Referenced by dumpMachineInstrRangeWithSlotIndex(), llvm::LiveRangeEdit::eraseVirtReg(), llvm::LiveIntervals::handleMove(), hasProperty(), llvm::X86FrameLowering::inlineStackProbe(), and isValidClauseInst().

◆ isBundledWithPred()

bool llvm::MachineInstr::isBundledWithPred ( ) const

inline

Return true if this instruction is part of a bundle, and it is not the first instruction in the bundle.

Definition at line 362 of file MachineInstr.h.

References BundledPred, and getFlag().

Referenced by bundleWithPred(), copyIRFlags(), hasProperty(), llvm::MachineBasicBlock::insert(), llvm::MachineBasicBlock::insertAfter(), isBundled(), moveInstrOut(), llvm::SlotIndexes::removeMachineInstrFromMaps(), llvm::SlotIndexes::removeSingleMachineInstrFromMaps(), unbundleFromPred(), and unbundleSingleMI().

◆ isBundledWithSucc()

bool llvm::MachineInstr::isBundledWithSucc ( ) const

inline

Return true if this instruction is part of a bundle, and it is not the last instruction in the bundle.

Definition at line 366 of file MachineInstr.h.

References BundledSucc, bundleWithPred(), bundleWithSucc(), getFlag(), unbundleFromPred(), and unbundleFromSucc().

Referenced by bundleWithSucc(), hasUnoccupiedSlot(), llvm::MachineBasicBlock::insert(), llvm::MachineBasicBlock::insertAfter(), isBundled(), moveInstrOut(), llvm::SlotIndexes::removeSingleMachineInstrFromMaps(), unbundleFromSucc(), and unbundleSingleMI().

◆ isCall()

bool llvm::MachineInstr::isCall ( QueryType Type = AnyInBundle ) const

inline

Definition at line 633 of file MachineInstr.h.

References llvm::MCID::Call, and hasProperty().

Referenced by addEpilogOnlyR10(), addLiveInRegs(), llvm::ScheduleDAGInstrs::addSchedBarrierDeps(), areCandidatesToMergeOrPair(), llvm::DwarfDebug::beginInstruction(), callHasRegMask(), llvm::EHStreamer::callToNoUnwindFunction(), CanMovePastDMB(), cannotCoexistAsymm(), CriticalPathStep(), llvm::X86AsmPrinter::EmitInstruction(), llvm::SystemZHazardRecognizer::emitInstruction(), llvm::MipsAsmPrinter::EmitInstruction(), getFPReg(), llvm::rdf::DataFlowGraph::getNextShadow(), llvm::AArch64InstrInfo::getOutliningCandidateInfo(), llvm::AArch64InstrInfo::getOutliningType(), getRegClassForUnfoldedLoad(), llvm::X86InstrInfo::getSPAdjust(), llvm::HexagonPacketizerList::hasControlDependence(), llvm::HexagonPacketizerList::hasDeadDependence(), hasOrderedMemoryRef(), hasRegisterDependency(), llvm::HexagonPacketizerList::hasRegMaskDependence(), hasYmmOrZmmReg(), INITIALIZE_PASS(), isCallerPreservedOrConstPhysReg(), llvm::rdf::TargetOperandInfo::isClobbering(), llvm::HexagonInstrInfo::isComplex(), llvm::HexagonInstrInfo::isConstExtended(), isDependenceBarrier(), llvm::rdf::TargetOperandInfo::isFixedReg(), isGlobalMemoryObject(), llvm::HexagonPacketizerList::isLegalToPacketizeTogether(), isLoadFoldBarrier(), llvm::AArch64InstrInfo::isMBBSafeToOutlineFrom(), isNoReturnDef(), llvm::HexagonInstrInfo::isPredicable(), IsSafeAndProfitableToMove(), isSafeToMove(), llvm::HexagonInstrInfo::isSchedulingBoundary(), llvm::ARMBaseInstrInfo::isSchedulingBoundary(), llvm::PPCInstrInfo::isSignOrZeroExtended(), llvm::TargetInstrInfo::isTailCall(), mayAlias(), llvm::WebAssembly::mayThrow(), needsStackFrame(), llvm::rdf::operator<<(), DeadCodeElimination::SetQueue< T >::push_back(), Query(), regOverlapsSet(), llvm::HexagonRegisterInfo::shouldCoalesce(), llvm::TailDuplicator::shouldTailDuplicate(), and UpdateCPSRUse().

◆ isCFIInstruction()

bool llvm::MachineInstr::isCFIInstruction ( ) const

inline

Definition at line 990 of file MachineInstr.h.

References getOpcode().

Referenced by countsAsInstruction(), getRegsUsedByPHIs(), llvm::HexagonPacketizerList::ignorePseudoInstruction(), INITIALIZE_PASS(), isPosition(), llvm::HexagonPacketizerList::isSoloInstruction(), llvm::MIPrinter::print(), print(), and llvm::TailDuplicator::shouldTailDuplicate().

◆ isCommutable()

bool llvm::MachineInstr::isCommutable ( QueryType Type = IgnoreBundle ) const

inline

Return true if this may be a 2- or 3-address instruction (of the form "X = op Y, Z, ..."), which produces the same result if Y and Z are exchanged.

If this flag is set, then the TargetInstrInfo::commuteInstruction method may be used to hack on the instruction.

Note that this flag may be set on instructions that are only commutable sometimes. In these cases, the call to commuteInstruction will fail. Also note that some instructions require non-trivial modification to commute them.

Definition at line 848 of file MachineInstr.h.

References llvm::MCID::Commutable, and hasProperty().

Referenced by addSegmentsWithValNo(), llvm::TargetInstrInfo::commuteInstruction(), foldImmediates(), getDPPOp(), isCallerPreservedOrConstPhysReg(), isLiveOut(), llvm::SIInstrInfo::legalizeOperandsVOP2(), matchSwap(), and tryConstantFoldOp().

◆ isCompare()

bool llvm::MachineInstr::isCompare ( QueryType Type = IgnoreBundle ) const

inline

Return true if this instruction is a comparison.

Definition at line 694 of file MachineInstr.h.

References llvm::MCID::Compare, and hasProperty().

Referenced by llvm::SystemZInstrInfo::analyzeCompare(), llvm::createHexagonHardwareLoops(), getCompareSourceReg(), INITIALIZE_PASS(), isCompareZero(), llvm::HexagonInstrInfo::isEarlySourceInstr(), isImmValidForOpcode(), isVirtualRegisterOperand(), lowerRIHigh(), lowerRILow(), and matchSwap().

◆ isConditionalBranch()

bool llvm::MachineInstr::isConditionalBranch ( QueryType Type = AnyInBundle ) const

inline

Return true if this is a branch which may fall through to the next instruction or may transfer control flow to some other block.

The TargetInstrInfo::AnalyzeBranch method can be used to get more information about this branch.

Definition at line 671 of file MachineInstr.h.

References isBarrier(), isBranch(), and isIndirectBranch().

Referenced by llvm::HexagonInstrInfo::getDotNewPredJumpOp(), and isVirtualRegisterOperand().

◆ isConstantValuePHI()

unsigned MachineInstr::isConstantValuePHI ( ) const

If the specified instruction is a PHI that always merges together the same virtual register, return the register, otherwise return 0.

isConstantValuePHI - If the specified instruction is a PHI that always merges together the same virtual register, return the register, otherwise return 0.

Definition at line 1337 of file MachineInstr.cpp.

References assert(), getNumOperands(), getOperand(), llvm::MachineOperand::getReg(), getReg(), isPHI(), and Reg.

Referenced by llvm::MachineSSAUpdater::GetValueInMiddleOfBlock(), and isRegTiedToDefOperand().

◆ isConvergent()

bool llvm::MachineInstr::isConvergent ( QueryType Type = AnyInBundle ) const

inline

Return true if this instruction is convergent.

Convergent instructions can not be made control-dependent on any additional values.

Definition at line 730 of file MachineInstr.h.

References llvm::MCID::Convergent, llvm::InlineAsm::Extra_IsConvergent, llvm::MachineOperand::getImm(), getOperand(), hasProperty(), isInlineAsm(), and llvm::InlineAsm::MIOp_ExtraInfo.

Referenced by performSink(), and llvm::TailDuplicator::shouldTailDuplicate().

◆ isConvertibleTo3Addr()

bool llvm::MachineInstr::isConvertibleTo3Addr ( QueryType Type = IgnoreBundle ) const

inline

Return true if this is a 2-address instruction which can be changed into a 3-address instruction if needed.

Doing this transformation can be profitable in the register allocator, because it means that the instruction can use a 2-address form if possible, but degrade into a less efficient form if the source and dest register cannot be assigned to the same register. For example, this allows the x86 backend to turn a "shl reg, 3" instruction into an LEA instruction, which is the same speed as the shift but has bigger code size.

If this returns true, then the target must implement the TargetInstrInfo::convertToThreeAddress method for this instruction, which is allowed to fail if the transformation isn't valid for this specific instruction (e.g. shl reg, 4 on x86).

Definition at line 866 of file MachineInstr.h.

References llvm::MCID::ConvertibleTo3Addr, and hasProperty().

◆ isCopy()

bool llvm::MachineInstr::isCopy ( ) const

inline

Definition at line 1040 of file MachineInstr.h.

References getOpcode().

Referenced by addSegmentsWithValNo(), llvm::HexagonSubtarget::adjustSchedDependency(), llvm::HexagonSubtarget::CallMutation::apply(), llvm::biasPhysReg(), canFoldCopy(), changeFCMPPredToAArch64CC(), computeBranchTargetAndInversion(), llvm::createCopyConstrainDAGMutation(), dumpMachineInstrRangeWithSlotIndex(), llvm::LiveRangeEdit::eraseVirtReg(), llvm::HexagonEvaluator::evaluate(), llvm::ARMBaseInstrInfo::expandPostRAPseudo(), findSRegBaseAndIndex(), llvm::TargetInstrInfo::foldMemoryOperand(), llvm::AArch64InstrInfo::foldMemoryOperandImpl(), llvm::X86InstrInfo::foldMemoryOperandImpl(), foldVGPRCopyIntoRegSequence(), getFPReg(), getNewSource(), getRegClassFromGRPhysReg(), getSingleDef(), getSubOpcode(), getWinAllocaAmount(), hasRegisterDependency(), INITIALIZE_PASS(), insertPHI(), isCopyFeedingInvariantStore(), llvm::TargetInstrInfo::isCopyInstr(), isCopyLike(), isCopyLike(), isCopyToReg(), isDebug(), isDefInSubRange(), isFpMulInstruction(), isFullCopy(), isFullCopyOf(), isIdentityCopy(), llvm::SIInstrInfo::isInlineConstant(), isLocalCopy(), isNopCopy(), isUseSafeToFold(), llvm::SIInstrInfo::isVGPRCopy(), isVirtualRegisterOperand(), llvm::TargetRegisterInfo::lookThruCopyLike(), MIIsInTerminatorSequence(), llvm::SIInstrInfo::moveToVALU(), llvm::AArch64InstrInfo::optimizeCondBranch(), regOverlapsSet(), llvm::GenericScheduler::reschedulePhysReg(), llvm::SelectionDAGISel::runOnMachineFunction(), llvm::AMDGPUInstructionSelector::select(), selectCopy(), llvm::SystemZRegisterInfo::shouldCoalesce(), swapAntiDependences(), llvm::TailDuplicator::tailDuplicateAndUpdate(), and llvm::VirtRegAuxInfo::weightCalcHelper().

◆ isCopyLike()

bool llvm::MachineInstr::isCopyLike ( ) const

inline

Return true if the instruction behaves like a copy.

This does not include native copy instructions.

Definition at line 1054 of file MachineInstr.h.

References isCopy(), and isSubregToReg().

Referenced by definesFullReg(), llvm::ARMBaseInstrInfo::getOperandLatency(), INITIALIZE_PASS(), isCallerPreservedOrConstPhysReg(), isCopyFeedingInvariantStore(), isSplitEdge(), isTerminalReg(), llvm::TargetRegisterInfo::lookThruCopyLike(), and regOverlapsSet().

◆ isDebugInstr()

bool llvm::MachineInstr::isDebugInstr ( ) const

inline

Definition at line 999 of file MachineInstr.h.

References isDebugLabel(), and isDebugValue().

Referenced by addRegsToSet(), llvm::GCNHazardRecognizer::AdvanceCycle(), llvm::CodeViewDebug::beginInstruction(), llvm::RegPressureTracker::bumpDownwardPressure(), llvm::RegPressureTracker::bumpUpwardPressure(), countsAsInstruction(), llvm::createBreakFalseDeps(), llvm::ARMHazardRecognizer::EmitInstruction(), llvm::PPCHazardRecognizer970::EmitInstruction(), llvm::RegScavenger::enterBasicBlockEnd(), llvm::BitTracker::MachineEvaluator::evaluate(), findStartOfTree(), getDataDeps(), llvm::ARMHazardRecognizer::getHazardType(), llvm::PPCHazardRecognizer970::getHazardType(), getNewValueJumpOpcode(), llvm::X86InstrInfo::getOutliningCandidateInfo(), llvm::AArch64InstrInfo::getOutliningType(), llvm::X86InstrInfo::getOutliningType(), getRetpolineSymbol(), getSchedRegions(), llvm::HexagonInstrInfo::getSize(), getStartOrEndSlot(), llvm::LiveVariables::HandleVirtRegDef(), hasRegisterDependency(), llvm::HexagonPacketizerList::ignorePseudoInstruction(), INITIALIZE_PASS(), llvm::SlotIndexes::insertMachineInstrInMaps(), isCallerPreservedOrConstPhysReg(), isFullCopyOf(), isFullUndefDef(), isIdenticalTo(), IsSafeAndProfitableToMove(), isSafeToMove(), llvm::HexagonInstrInfo::isSchedulingBoundary(), llvm::ARMBaseInstrInfo::isSchedulingBoundary(), isVirtualRegisterOperand(), matchPair(), MaySpeculate(), llvm::CriticalAntiDepBreaker::Observe(), Query(), readsVCCZ(), llvm::GCNUpwardRPTracker::recede(), removeRegisterOperands(), llvm::LiveIntervals::repairIntervalsInRange(), llvm::rdf::Liveness::resetKills(), llvm::RegScavenger::unprocess(), UpdateCPSRUse(), and llvm::VirtRegAuxInfo::weightCalcHelper().

◆ isDebugLabel()

bool llvm::MachineInstr::isDebugLabel ( ) const

inline

Definition at line 998 of file MachineInstr.h.

References getOpcode().

Referenced by llvm::DbgLabelInstrMap::addInstr(), llvm::MachineInstrBuilder::addMetadata(), llvm::ScheduleDAGInstrs::buildSchedGraph(), llvm::MipsAsmPrinter::EmitInstruction(), getDebugLabel(), isDebugInstr(), and print().

◆ isDebugValue()

bool llvm::MachineInstr::isDebugValue ( ) const

inline

Definition at line 997 of file MachineInstr.h.

References getOpcode().

Referenced by llvm::MachineInstrBuilder::addMetadata(), addSegmentsWithValNo(), AssignProtectedObjSet(), llvm::ScheduleDAGInstrs::buildSchedGraph(), llvm::createX86OptimizeLEAs(), llvm::ConnectedVNInfoEqClasses::Distribute(), llvm::XCoreRegisterInfo::eliminateFrameIndex(), llvm::ARCRegisterInfo::eliminateFrameIndex(), llvm::ThumbRegisterInfo::eliminateFrameIndex(), llvm::AArch64RegisterInfo::eliminateFrameIndex(), llvm::ARMBaseRegisterInfo::eliminateFrameIndex(), llvm::MipsAsmPrinter::EmitInstruction(), llvm::DbgVariableLocation::extractFromMachineInstruction(), getDebugExpression(), getDebugVariable(), getLoadStoreOffsetAlign(), getSingleDef(), hasRegisterDependency(), INITIALIZE_PASS(), llvm::Mips16RegisterInfo::intRegClass(), isDbgValueDescribedByReg(), isDebugInstr(), isDefBetween(), isDescribedByReg(), isFullCopyOf(), isFullUndefDef(), isIndirectDebugValue(), isValidClauseInst(), llvm::MachineRegisterInfo::markUsesInDebugValueAsUndef(), matchPair(), MIIsInTerminatorSequence(), needsReferenceType(), false::IntervalSorter::operator()(), print(), llvm::SelectionDAGISel::runOnMachineFunction(), llvm::DbgValueHistoryMap::startInstrRange(), llvm::TailDuplicator::tailDuplicateAndUpdate(), llvm::HexagonPacketizerList::unpacketizeSoloInstrs(), and llvm::AntiDepBreaker::UpdateDbgValue().

◆ isDereferenceableInvariantLoad()

bool MachineInstr::isDereferenceableInvariantLoad ( AliasAnalysis * AA ) const

Return true if this load instruction never traps and points to a memory location whose value doesn't change during the execution of this function.

isDereferenceableInvariantLoad - Return true if this instruction will never trap and is loading from a location whose value is invariant across a run of this function.

Examples include loading a value from the constant pool or from the argument area of a function (if it does not change). If the instruction does multiple loads, this returns true only if all of the loads are dereferenceable and invariant.

Definition at line 1295 of file MachineInstr.cpp.

References llvm::MachineFunction::getFrameInfo(), llvm::MachineBasicBlock::getParent(), getParent(), mayLoad(), memoperands(), memoperands_empty(), and llvm::AAResults::pointsToConstantMemory().

Referenced by llvm::ScheduleDAGInstrs::buildSchedGraph(), llvm::TargetInstrInfo::genAlternativeCodeSequence(), isCallerPreservedOrConstPhysReg(), isCopyFeedingInvariantStore(), isDependenceBarrier(), isGlobalMemoryObject(), llvm::X86InstrInfo::isReallyTriviallyReMaterializable(), isRegTiedToDefOperand(), isSafeToMove(), and Query().

◆ isEHLabel()

bool llvm::MachineInstr::isEHLabel ( ) const

inline

Definition at line 979 of file MachineInstr.h.

References llvm::ISD::EH_LABEL, and getOpcode().

Referenced by getRetpolineSymbol(), isLabel(), and llvm::HexagonPacketizerList::isSoloInstruction().

◆ isEHScopeReturn()

bool llvm::MachineInstr::isEHScopeReturn ( QueryType Type = AnyInBundle ) const

inline

Return true if this is an instruction that marks the end of an EH scope, i.e., a catchpad or a cleanuppad instruction.

Definition at line 629 of file MachineInstr.h.

References llvm::MCID::EHScopeReturn, and hasProperty().

◆ isExtractSubreg()

bool llvm::MachineInstr::isExtractSubreg ( ) const

inline

Definition at line 1048 of file MachineInstr.h.

References getOpcode().

Referenced by llvm::TargetInstrInfo::getExtractSubregInputs(), insertPHI(), and isOperandSubregIdx().

◆ isExtractSubregLike()

bool llvm::MachineInstr::isExtractSubregLike ( QueryType Type = IgnoreBundle ) const

inline

Return true if this instruction behaves the same way as the generic EXTRACT_SUBREG instructions.

E.g., on ARM, rX, rY VMOVRRD dZ is equivalent to two EXTRACT_SUBREG: rX = EXTRACT_SUBREG dZ, ssub_0 rY = EXTRACT_SUBREG dZ, ssub_1

Note that for the optimizers to be able to take advantage of this property, TargetInstrInfo::getExtractSubregLikeInputs has to be override accordingly.

Definition at line 782 of file MachineInstr.h.

References llvm::MCID::ExtractSubreg, and hasProperty().

Referenced by getCopyRewriter(), llvm::TargetInstrInfo::getExtractSubregInputs(), and llvm::ARMBaseInstrInfo::getExtractSubregLikeInputs().

◆ isFullCopy()

bool llvm::MachineInstr::isFullCopy ( ) const

inline

Definition at line 1044 of file MachineInstr.h.

References getOperand(), llvm::MachineOperand::getSubReg(), and isCopy().

Referenced by addSegmentsWithValNo(), llvm::AArch64InstrInfo::foldMemoryOperandImpl(), llvm::CoalescerPair::isCoalescable(), isFullCopyOf(), isFullExecCopy(), isRematerializable(), and removeCopies().

◆ isGCLabel()

bool llvm::MachineInstr::isGCLabel ( ) const

inline

Definition at line 980 of file MachineInstr.h.

References getOpcode().

Referenced by isLabel().

◆ isIdenticalTo()

bool MachineInstr::isIdenticalTo	(	const MachineInstr &	Other,
		MICheckType	Check = `CheckDefs`
	)		const

Return true if this instruction is identical to Other.

Two instructions are identical if they have the same opcode and all their operands are identical (with respect to MachineOperand::isIdenticalTo()). Note that this means liveness related flags (dead, undef, kill) do not affect the notion of identical.

Definition at line 573 of file MachineInstr.cpp.

References assert(), CheckKillDead, getDebugLoc(), llvm::ilist_node_impl< ilist_detail::compute_node_options< MachineInstr, Options... >::type >::getIterator(), llvm::ilist_node_impl< OptionsT >::getIterator(), getNumOperands(), getOpcode(), getOperand(), llvm::MachineOperand::getReg(), IgnoreDefs, IgnoreVRegDefs, isBundle(), llvm::MachineOperand::isDead(), isDebugInstr(), llvm::MachineOperand::isDef(), llvm::MachineOperand::isIdenticalTo(), llvm::MachineOperand::isKill(), llvm::MachineOperand::isReg(), and llvm::TargetRegisterInfo::isVirtualRegister().

Referenced by llvm::MachineInstrExpressionTrait::isEqual(), llvm::ARMBaseInstrInfo::produceSameValue(), and llvm::TargetInstrInfo::produceSameValue().

◆ isIdentityCopy()

bool llvm::MachineInstr::isIdentityCopy ( ) const

inline

Return true is the instruction is an identity copy.

Definition at line 1059 of file MachineInstr.h.

References getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::getSubReg(), and isCopy().

Referenced by llvm::VirtRegAuxInfo::weightCalcHelper().

◆ isImplicitDef()

bool llvm::MachineInstr::isImplicitDef ( ) const

inline

◆ isIndirectBranch()

bool llvm::MachineInstr::isIndirectBranch ( QueryType Type = AnyInBundle ) const

inline

Return true if this is an indirect branch, such as a branch through a register.

Definition at line 663 of file MachineInstr.h.

References hasProperty(), and llvm::MCID::IndirectBranch.

Referenced by llvm::MipsInstrInfo::analyzeBranch(), blockEndsInUnreachable(), llvm::MipsAsmPrinter::EmitInstruction(), llvm::rdf::DataFlowGraph::getNextShadow(), isConditionalBranch(), llvm::HexagonInstrInfo::isHVXMemWithAIndirect(), isUnconditionalBranch(), and llvm::TailDuplicator::shouldTailDuplicate().

◆ isIndirectDebugValue()

bool llvm::MachineInstr::isIndirectDebugValue ( ) const

inline

A DBG_VALUE is indirect iff the first operand is a register and the second operand is an immediate.

Definition at line 1003 of file MachineInstr.h.

References getOperand(), isDebugValue(), llvm::MachineOperand::isImm(), and llvm::MachineOperand::isReg().

Referenced by computeExprForSpill(), llvm::createX86OptimizeLEAs(), llvm::DbgVariableLocation::extractFromMachineInstruction(), llvm::AArch64InstrInfo::getOutliningType(), llvm::X86InstrInfo::getOutliningType(), INITIALIZE_PASS(), print(), and llvm::SelectionDAGISel::runOnMachineFunction().

◆ isInlineAsm()

bool llvm::MachineInstr::isInlineAsm ( ) const

inline

Definition at line 1015 of file MachineInstr.h.

References getOpcode(), and llvm::ISD::INLINEASM.

Referenced by addOperand(), addRegisterDead(), addRegisterKilled(), llvm::RegAllocBase::allocatePhysRegs(), llvm::BTFDebug::beginInstruction(), cannotCoexistAsymm(), llvm::HexagonPacketizerList::canPromoteToDotCur(), llvm::HexagonPacketizerList::canPromoteToDotNew(), CriticalPathStep(), llvm::PPCRegisterInfo::eliminateFrameIndex(), EmitGCCInlineAsmStr(), llvm::LiveRangeEdit::eraseVirtReg(), findInlineAsmFlagIdx(), findTiedOperandIdx(), llvm::TargetInstrInfo::genAlternativeCodeSequence(), getFPReg(), llvm::GCNHazardRecognizer::getHazardType(), getInlineAsmDialect(), getOffsetONFromFION(), getRegClassConstraint(), hasUnmodeledSideEffects(), llvm::SIInstrInfo::hasUnwantedEffectsWhenEXECEmpty(), llvm::HexagonPacketizerList::ignorePseudoInstruction(), INITIALIZE_PASS(), isCallerPreservedOrConstPhysReg(), isConvergent(), llvm::rdf::TargetOperandInfo::isFixedReg(), llvm::HexagonInstrInfo::isSchedulingBoundary(), llvm::HexagonPacketizerList::isSoloInstruction(), isStackAligningInlineAsm(), isUnsafeToMoveAcross(), isVirtualRegisterOperand(), matchPair(), mayLoad(), mayStore(), llvm::GCNHazardRecognizer::PreEmitNoops(), print(), removePhis(), removeRegisterOperands(), llvm::MipsInstrInfo::SafeInForbiddenSlot(), tieOperands(), llvm::HexagonPacketizerList::unpacketizeSoloInstrs(), and llvm::SIInstrInfo::verifyInstruction().

◆ isInsertSubreg()

bool llvm::MachineInstr::isInsertSubreg ( ) const

inline

Definition at line 1024 of file MachineInstr.h.

References getOpcode().

Referenced by llvm::TargetInstrInfo::getInsertSubregInputs(), llvm::ARMBaseInstrInfo::getOperandLatency(), INITIALIZE_PASS(), insertPHI(), isCopyToReg(), and isOperandSubregIdx().

◆ isInsertSubregLike()

bool llvm::MachineInstr::isInsertSubregLike ( QueryType Type = IgnoreBundle ) const

inline

Return true if this instruction behaves the same way as the generic INSERT_SUBREG instructions.

E.g., on ARM, dX = VSETLNi32 dY, rZ, Imm is equivalent to a INSERT_SUBREG: dX = INSERT_SUBREG dY, rZ, translateImmToSubIdx(Imm)

Note that for the optimizers to be able to take advantage of this property, TargetInstrInfo::getInsertSubregLikeInputs has to be override accordingly.

Definition at line 796 of file MachineInstr.h.

References hasProperty(), and llvm::MCID::InsertSubreg.

Referenced by getCopyRewriter(), llvm::TargetInstrInfo::getInsertSubregInputs(), and llvm::ARMBaseInstrInfo::getInsertSubregLikeInputs().

◆ isInsideBundle()

bool llvm::MachineInstr::isInsideBundle ( ) const

inline

Return true if MI is in a bundle (but not the first MI in a bundle).

A bundle looks like this before it's finalized:

| MI |

|

| MI * |

|

| MI * |

In this case, the first MI starts a bundle but is not inside a bundle, the next 2 MIs are considered "inside" the bundle.

After a bundle is finalized, it looks like this:

| Bundle |

|

| MI * |

|

| MI * |

|

| MI * |

The first instruction has the special opcode "BUNDLE". It's not "inside" a bundle, but the next three MIs are.

Definition at line 350 of file MachineInstr.h.

References BundledPred, and getFlag().

Referenced by llvm::BuildMI(), llvm::SlotIndexes::insertMachineInstrInMaps(), matchPair(), llvm::MIPrinter::print(), llvm::MachineBasicBlock::print(), llvm::HexagonPacketizerList::unpacketizeSoloInstrs(), and UpdateCPSRUse().

◆ isKill()

bool llvm::MachineInstr::isKill ( ) const

inline

Definition at line 1013 of file MachineInstr.h.

References getOpcode(), and llvm::AMDGPUISD::KILL.

Referenced by CriticalPathStep(), findRegisterUseOperand(), llvm::X86InstrInfo::getOutliningCandidateInfo(), llvm::AArch64InstrInfo::getOutliningType(), llvm::X86InstrInfo::getOutliningType(), isCallerPreservedOrConstPhysReg(), isCrossCopy(), isVirtualRegisterOperand(), llvm::CriticalAntiDepBreaker::Observe(), and registerDefIsDead().

◆ isLabel()

bool llvm::MachineInstr::isLabel ( ) const

inline

Returns true if the MachineInstr represents a label.

Definition at line 986 of file MachineInstr.h.

References isAnnotationLabel(), isEHLabel(), and isGCLabel().

Referenced by findStartOfTree(), isPosition(), and removeRegisterOperands().

◆ isLoadFoldBarrier()

bool MachineInstr::isLoadFoldBarrier ( ) const

Returns true if it is illegal to fold a load across this instruction.

Definition at line 1362 of file MachineInstr.cpp.

References hasUnmodeledSideEffects(), isCall(), and mayStore().

Referenced by isRegTiedToDefOperand(), and isVirtualRegisterOperand().

◆ isMetaInstruction()

bool llvm::MachineInstr::isMetaInstruction ( ) const

inline

Return true if this instruction doesn't produce any output in the form of executable instructions.

Definition at line 1066 of file MachineInstr.h.

References llvm::ISD::EH_LABEL, getOpcode(), llvm::AMDGPUISD::KILL, llvm::ISD::LIFETIME_END, and llvm::ISD::LIFETIME_START.

Referenced by llvm::BTFDebug::beginInstruction(), llvm::DwarfDebug::beginInstruction(), llvm::DebugHandlerBase::endInstruction(), INITIALIZE_PASS(), isTransient(), isUnsafeToMoveAcross(), and llvm::TailDuplicator::shouldTailDuplicate().

◆ isMoveImmediate()

bool llvm::MachineInstr::isMoveImmediate ( QueryType Type = IgnoreBundle ) const

inline

Return true if this instruction is a move immediate (including conditional moves) instruction.

Definition at line 700 of file MachineInstr.h.

References hasProperty(), and llvm::MCID::MoveImm.

Referenced by llvm::biasPhysReg(), llvm::SIInstrInfo::FoldImmediate(), foldImmediates(), getImmOrMaterializedImm(), getNewSource(), INITIALIZE_PASS(), isSafeToFoldImmIntoCopy(), llvm::SIInstrInfo::legalizeGenericOperand(), and llvm::GenericScheduler::reschedulePhysReg().

◆ isMoveReg()

bool llvm::MachineInstr::isMoveReg ( QueryType Type = IgnoreBundle ) const

inline

Return true if this instruction is a register move.

(including moving values from subreg to reg)

Definition at line 706 of file MachineInstr.h.

References hasProperty(), and llvm::MCID::MoveReg.

Referenced by llvm::MipsSEInstrInfo::isCopyInstrImpl(), llvm::ARMBaseInstrInfo::isCopyInstrImpl(), llvm::Mips16InstrInfo::isCopyInstrImpl(), and llvm::X86InstrInfo::isCopyInstrImpl().

◆ isMSInlineAsm()

bool llvm::MachineInstr::isMSInlineAsm ( ) const

inline

Definition at line 1017 of file MachineInstr.h.

References getInlineAsmDialect(), getOpcode(), llvm::ISD::INLINEASM, and isStackAligningInlineAsm().

◆ isNotDuplicable()

bool llvm::MachineInstr::isNotDuplicable ( QueryType Type = AnyInBundle ) const

inline

Return true if this instruction cannot be safely duplicated.

For example, if the instruction has a unique labels attached to it, duplicating it would cause multiple definition errors.

Definition at line 723 of file MachineInstr.h.

References hasProperty(), and llvm::MCID::NotDuplicable.

Referenced by llvm::TargetInstrInfo::duplicate(), llvm::TargetInstrInfo::genAlternativeCodeSequence(), and llvm::TailDuplicator::shouldTailDuplicate().

◆ isOperandSubregIdx()

bool llvm::MachineInstr::isOperandSubregIdx ( unsigned OpIdx ) const

inline

Return true if operand OpIdx is a subregister index.

Definition at line 429 of file MachineInstr.h.

References assert(), getNumExplicitDefs(), getNumExplicitOperands(), getOperand(), getType(), isExtractSubreg(), isInsertSubreg(), isRegSequence(), isSubregToReg(), and llvm::MachineOperand::MO_Immediate.

Referenced by llvm::MIPrinter::print(), and print().

◆ isPHI()

bool llvm::MachineInstr::isPHI ( ) const

inline

Definition at line 1009 of file MachineInstr.h.

References getOpcode().

Referenced by allPhiOperandsUndefined(), llvm::TailDuplicator::canTailDuplicate(), checkRegOnlyPHIInputs(), computeLiveOuts(), createBBSelectReg(), llvm::LiveRangeCalc::createDeadDefs(), llvm::SMSchedule::finalizeSchedule(), fixupRegionExits(), llvm::Localizer::getAnalysisUsage(), llvm::RegBankSelect::getAnalysisUsage(), llvm::SwingSchedulerDAG::getDistance(), llvm::AArch64RegisterBankInfo::getInstrMapping(), getPHIDeps(), getPHIDestReg(), getPHINumInputs(), getPHIPred(), getPhiRegs(), getPHISourceReg(), getRegsUsedByPHIs(), getUnderlyingObjects(), getZeroLatency(), llvm::LiveVariables::HandleVirtRegDef(), hasUseAfterLoop(), INITIALIZE_PASS(), insertUndefLaneMask(), llvm::RegBankSelect::InstrInsertPoint::InstrInsertPoint(), llvm::SSAUpdaterTraits< MachineSSAUpdater >::InstrIsPHI(), llvm::SwingSchedulerDAG::isBackedge(), isCallerPreservedOrConstPhysReg(), isConstantValuePHI(), isCopyLike(), isDebug(), isFunctionEntryBlock(), isIntersect(), llvm::SMSchedule::isLoopCarried(), llvm::SMSchedule::isLoopCarriedDefOfUse(), llvm::SwingSchedulerDAG::isLoopCarriedDep(), isSafeToMove(), llvm::isTriviallyDead(), llvm::SMSchedule::isValidSchedule(), isVirtualRegisterOperand(), matchPair(), parseCond(), ProcessSourceNode(), profitImm(), DeadCodeElimination::SetQueue< T >::push_back(), pushDepHeight(), removeExternalCFGEdges(), removePhis(), llvm::RegBankSelect::RepairingPlacement::RepairingPlacement(), llvm::MachineSSAUpdater::RewriteUse(), llvm::TailDuplicator::shouldTailDuplicate(), swapAntiDependences(), llvm::TailDuplicator::tailDuplicateAndUpdate(), llvm::MachineBasicBlock::transferSuccessorsAndUpdatePHIs(), llvm::CombinerHelper::tryCombineCopy(), and llvm::MachineTraceMetrics::Ensemble::updateDepth().

◆ isPosition()

bool llvm::MachineInstr::isPosition ( ) const

inline

Definition at line 995 of file MachineInstr.h.

References isCFIInstruction(), and isLabel().

Referenced by llvm::ScheduleDAGInstrs::buildSchedGraph(), llvm::AArch64InstrInfo::getOutliningType(), llvm::X86InstrInfo::getOutliningType(), llvm::HexagonInstrInfo::getSize(), isCallerPreservedOrConstPhysReg(), isFpMulInstruction(), isSafeToMove(), llvm::HexagonInstrInfo::isSchedulingBoundary(), llvm::ARMBaseInstrInfo::isSchedulingBoundary(), llvm::TargetInstrInfo::isSchedulingBoundary(), isVirtualRegisterOperand(), DeadCodeElimination::SetQueue< T >::push_back(), and Query().

◆ isPredicable()

bool llvm::MachineInstr::isPredicable ( QueryType Type = AllInBundle ) const

inline

Return true if this instruction has a predicate operand that controls execution.

It may be set to 'always', or may be set to other values. There are various methods in TargetInstrInfo that can be used to control and modify the predicate in this instruction.

Definition at line 687 of file MachineInstr.h.

References hasProperty(), and llvm::MCID::Predicable.

Referenced by AnyAliasLiveIn(), canFoldIntoMOVCC(), canFoldIntoSelect(), llvm::ThumbRegisterInfo::eliminateFrameIndex(), llvm::ARMBaseInstrInfo::isPredicable(), llvm::MSP430InstrInfo::isUnpredicatedTerminator(), llvm::X86InstrInfo::isUnpredicatedTerminator(), llvm::TargetInstrInfo::isUnpredicatedTerminator(), llvm::TargetInstrInfo::PredicateInstruction(), registerDefinedBetween(), and SinkingPreventsImplicitNullCheck().

◆ isPseudo()

bool llvm::MachineInstr::isPseudo ( QueryType Type = IgnoreBundle ) const

inline

Return true if this is a pseudo instruction that doesn't correspond to a real machine instruction.

Definition at line 619 of file MachineInstr.h.

References hasProperty(), and llvm::MCID::Pseudo.

Referenced by llvm::TargetSubtargetInfo::getSchedInfoStr(), INITIALIZE_PASS(), insertNopBeforeInstruction(), and llvm::ConvergingVLIWScheduler::SchedulingCost().

◆ isRegSequence()

bool llvm::MachineInstr::isRegSequence ( ) const

inline

Definition at line 1032 of file MachineInstr.h.

References getOpcode().

Referenced by llvm::HexagonSubtarget::adjustSchedDependency(), foldVGPRCopyIntoRegSequence(), llvm::ARMBaseInstrInfo::getOperandLatency(), llvm::TargetInstrInfo::getRegSequenceInputs(), llvm::getRegSequenceSubReg(), INITIALIZE_PASS(), insertPHI(), isDebug(), isOperandSubregIdx(), isUseSafeToFold(), and swapAntiDependences().

◆ isRegSequenceLike()

bool llvm::MachineInstr::isRegSequenceLike ( QueryType Type = IgnoreBundle ) const

inline

Return true if this instruction behaves the same way as the generic REG_SEQUENCE instructions.

E.g., on ARM, dX VMOVDRR rY, rZ is equivalent to dX = REG_SEQUENCE rY, ssub_0, rZ, ssub_1.

Note that for the optimizers to be able to take advantage of this property, TargetInstrInfo::getRegSequenceLikeInputs has to be override accordingly.

Definition at line 767 of file MachineInstr.h.

References hasProperty(), and llvm::MCID::RegSequence.

Referenced by getCopyRewriter(), llvm::TargetInstrInfo::getRegSequenceInputs(), and llvm::ARMBaseInstrInfo::getRegSequenceLikeInputs().

◆ isRegTiedToDefOperand()

bool llvm::MachineInstr::isRegTiedToDefOperand	(	unsigned	UseOpIdx,
		unsigned *	DefOpIdx = `nullptr`
	)		const

inline

Return true if the use operand of the specified index is tied to a def operand.

It also returns the def operand index by reference if DefOpIdx is not null.

Definition at line 1294 of file MachineInstr.h.

References addOperand(), addRegisterDead(), addRegisterDefined(), addRegisterKilled(), allDefsAreDead(), clearKillInfo(), clearRegisterDeads(), clearRegisterKills(), copyImplicitOps(), dump(), findTiedOperandIdx(), getOperand(), getTypeToPrint(), hasComplexRegisterTies(), hasOrderedMemoryRef(), hasUnmodeledSideEffects(), isConstantValuePHI(), isDereferenceableInvariantLoad(), isLoadFoldBarrier(), llvm::MachineOperand::isReg(), isSafeToMove(), llvm::MachineOperand::isTied(), llvm::MachineOperand::isUse(), mayAlias(), MI, MRI, Other, print(), setPhysRegsDeadExcept(), setRegisterDefReadUndef(), substituteRegister(), and UseTBAA.

Referenced by addRegisterKilled(), addSegmentsWithValNo(), llvm::MachineOperandIteratorBase::analyzeVirtReg(), llvm::LiveRangeCalc::createDeadDefs(), dumpMachineInstrRangeWithSlotIndex(), getRegClassConstraint(), isTwoAddrUse(), and matchPair().

◆ isRegTiedToUseOperand()

bool llvm::MachineInstr::isRegTiedToUseOperand	(	unsigned	DefOpIdx,
		unsigned *	UseOpIdx = `nullptr`
	)		const

inline

Given the index of a register def operand, check if the register def is tied to a source operand, due to either two-address elimination or inline assembly constraints.

Returns the first tied use operand index by reference if UseOpIdx is not null.

Definition at line 1281 of file MachineInstr.h.

References findTiedOperandIdx(), getOperand(), llvm::MachineOperand::isDef(), llvm::MachineOperand::isReg(), and llvm::MachineOperand::isTied().

Referenced by addSegmentsWithValNo(), llvm::constrainSelectedInstRegOperands(), CriticalPathStep(), llvm::SwingSchedulerDAG::fixupRegisterOverlaps(), INITIALIZE_PASS(), isVirtualRegisterOperand(), llvm::AggressiveAntiDepBreaker::Observe(), removePhis(), and llvm::SIInstrInfo::verifyInstruction().

◆ isRematerializable()

bool llvm::MachineInstr::isRematerializable ( QueryType Type = AllInBundle ) const

inline

Returns true if this instruction is a candidate for remat.

This flag is deprecated, please don't use it anymore. If this flag is set, the isReallyTriviallyReMaterializable() method is called to verify the instruction is really rematable.

Definition at line 894 of file MachineInstr.h.

References hasProperty(), and llvm::MCID::Rematerializable.

◆ isReturn()

bool llvm::MachineInstr::isReturn ( QueryType Type = AnyInBundle ) const

inline

◆ isSafeToMove()

bool MachineInstr::isSafeToMove	(	AliasAnalysis *	AA,
		bool &	SawStore
	)		const

Return true if it is safe to move this instruction.

isSafeToMove - Return true if it is safe to move this instruction.

If SawStore is set to true, it means that there is a store (or call) between the instruction's location and its intended destination.

Definition at line 1148 of file MachineInstr.cpp.

References hasOrderedMemoryRef(), hasUnmodeledSideEffects(), isCall(), isDebugInstr(), isDereferenceableInvariantLoad(), isPHI(), isPosition(), isTerminator(), mayLoad(), and mayStore().

Referenced by canFoldIntoMOVCC(), canFoldIntoSelect(), definesFullReg(), llvm::LiveRangeEdit::eraseVirtReg(), findSinkableLocalRegDef(), isCopyFeedingInvariantStore(), isRegTiedToDefOperand(), llvm::isTriviallyDead(), MaySpeculate(), llvm::X86InstrInfo::optimizeLoadInstr(), performSink(), and regOverlapsSet().

◆ isSelect()

bool llvm::MachineInstr::isSelect ( QueryType Type = IgnoreBundle ) const

inline

Return true if this instruction is a select instruction.

Definition at line 716 of file MachineInstr.h.

References hasProperty(), and llvm::MCID::Select.

Referenced by isVirtualRegisterOperand().

◆ isStackAligningInlineAsm()

bool MachineInstr::isStackAligningInlineAsm ( ) const

Definition at line 757 of file MachineInstr.cpp.

References llvm::InlineAsm::Extra_IsAlignStack, llvm::MachineOperand::getImm(), getOperand(), isInlineAsm(), and llvm::InlineAsm::MIOp_ExtraInfo.

Referenced by isMSInlineAsm().

◆ isSubregToReg()

bool llvm::MachineInstr::isSubregToReg ( ) const

inline

Definition at line 1028 of file MachineInstr.h.

References getOpcode().

Referenced by isCopyLike(), isCopyToReg(), isOperandSubregIdx(), and llvm::TargetRegisterInfo::lookThruCopyLike().

◆ isTerminator()

bool llvm::MachineInstr::isTerminator ( QueryType Type = AnyInBundle ) const

inline

Returns true if this instruction part of the terminator for a basic block.

Typically this is things like return and branch instructions.

Various passes use this to insert code into the bottom of a basic block, but before control flow occurs.

Definition at line 649 of file MachineInstr.h.

References hasProperty(), and llvm::MCID::Terminator.

Referenced by AppendEndToFunction(), llvm::ScheduleDAGInstrs::buildSchedGraph(), cannotCoexistAsymm(), llvm::createSIWholeQuadModePass(), llvm::SystemZHazardRecognizer::emitInstruction(), llvm::RegBankSelect::getAnalysisUsage(), llvm::AArch64InstrInfo::getOutliningType(), llvm::X86InstrInfo::getOutliningType(), getRegClassForUnfoldedLoad(), llvm::TargetSubtargetInfo::getSchedInfoStr(), INITIALIZE_PASS(), llvm::SIInstrInfo::isBasicBlockPrologue(), isCallerPreservedOrConstPhysReg(), IsSafeAndProfitableToMove(), isSafeToMove(), llvm::ARMBaseInstrInfo::isSchedulingBoundary(), llvm::TargetInstrInfo::isSchedulingBoundary(), llvm::RegBankSelect::InstrInsertPoint::isSplit(), llvm::MSP430InstrInfo::isUnpredicatedTerminator(), llvm::X86InstrInfo::isUnpredicatedTerminator(), llvm::PPCInstrInfo::isUnpredicatedTerminator(), llvm::TargetInstrInfo::isUnpredicatedTerminator(), matchPair(), Query(), regOverlapsSet(), and llvm::RegBankSelect::RepairingPlacement::RepairingPlacement().

◆ isTransient()

bool llvm::MachineInstr::isTransient ( ) const

inline

Return true if this is a transient instruction that is either very likely to be eliminated during register allocation (such as copy-like instructions), or if this instruction doesn't have an execution-time cost.

Definition at line 1086 of file MachineInstr.h.

References getBundleSize(), getOpcode(), and isMetaInstruction().

Referenced by areCandidatesToMergeOrPair(), llvm::TargetSchedModel::computeOperandLatency(), llvm::createSIWholeQuadModePass(), llvm::TargetInstrInfo::defaultDefLatency(), llvm::HexagonInstrInfo::getInstrTimingClassLatency(), llvm::TargetSchedModel::getNumMicroOps(), IsMovepDestinationRegPair(), mayAlias(), updatePhysDepsUpwards(), llvm::SchedDFSImpl::visitPostorderNode(), and llvm::SchedDFSImpl::visitPreorder().

◆ isUnconditionalBranch()

bool llvm::MachineInstr::isUnconditionalBranch ( QueryType Type = AnyInBundle ) const

inline

Return true if this is a branch which always transfers control flow to some other block.

The TargetInstrInfo::AnalyzeBranch method can be used to get more information about this branch.

Definition at line 679 of file MachineInstr.h.

References isBarrier(), isBranch(), and isIndirectBranch().

Referenced by llvm::MipsInstrInfo::analyzeBranch(), llvm::RegBankSelect::getAnalysisUsage(), getUnconditionalBrDisp(), INITIALIZE_PASS(), and isSplitEdge().

◆ isVariadic()

bool llvm::MachineInstr::isVariadic ( QueryType Type = IgnoreBundle ) const

inline

Return true if this instruction can have a variable number of operands.

In this case, the variable operands will be after the normal operands but before the implicit definitions and uses (if any are present).

Definition at line 607 of file MachineInstr.h.

References hasProperty(), and llvm::MCID::Variadic.

Referenced by llvm::createBreakFalseDeps(), llvm::SIInstrInfo::getOpRegClass(), getTypeToPrint(), INITIALIZE_PASS(), and matchPair().

◆ killsRegister()

bool llvm::MachineInstr::killsRegister	(	unsigned	Reg,
		const TargetRegisterInfo *	TRI = `nullptr`
	)		const

inline

Return true if the MachineInstr kills the specified register.

If TargetRegisterInfo is passed, then it also checks if there is a kill of a super-register.

Definition at line 1134 of file MachineInstr.h.

References findRegisterUseOperandIdx(), and TRI.

Referenced by llvm::X86InstrInfo::breakPartialRegDependency(), checkEFLAGSLive(), ContainsReg(), createPHIsForCMOVsInSinkBB(), createPHIsForSelects(), llvm::ARMTargetLowering::EmitInstrWithCustomInserter(), isPlainlyKilled(), llvm::X86InstrInfo::optimizeCompareInstr(), and UpdateCPSRUse().

◆ mayAlias()

bool MachineInstr::mayAlias	(	AliasAnalysis *	AA,
		MachineInstr &	Other,
		bool	UseTBAA
	)

Returns true if this instruction's memory access aliases the memory access of Other.

Assumes any physical registers used to compute addresses have the same value for both instructions. Returns false if neither instruction writes to memory.

Parameters

AA	Optional alias analysis, used to compare memory operands.
Other	MachineInstr to check aliasing against.
UseTBAA	Whether to pass TBAA information to alias analysis.

Definition at line 1177 of file MachineInstr.cpp.

References llvm::AAResults::alias(), llvm::TargetInstrInfo::areMemAccessesTriviallyDisjoint(), assert(), llvm::MachineMemOperand::getAAInfo(), llvm::MachineFunction::getFrameInfo(), llvm::TargetSubtargetInfo::getInstrInfo(), getMF(), llvm::MachineMemOperand::getOffset(), llvm::MachineMemOperand::getPseudoValue(), llvm::MachineMemOperand::getSize(), llvm::MachineFunction::getSubtarget(), llvm::MachineMemOperand::getValue(), hasOneMemOperand(), llvm::max(), llvm::PseudoSourceValue::mayAlias(), mayStore(), memoperands_begin(), llvm::NoAlias, and llvm::MemoryLocation::UnknownSize.

Referenced by llvm::ScheduleDAGInstrs::addChainDependency(), isRegTiedToDefOperand(), and mayAlias().

◆ mayLoad()

bool llvm::MachineInstr::mayLoad ( QueryType Type = AnyInBundle ) const

inline

Return true if this instruction could possibly read memory.

Instructions with this flag set are not necessarily simple load instructions, they may load a value and modify it, for example.

Definition at line 807 of file MachineInstr.h.

References llvm::InlineAsm::Extra_MayLoad, llvm::MachineOperand::getImm(), getOperand(), hasProperty(), isInlineAsm(), llvm::MCID::MayLoad, and llvm::InlineAsm::MIOp_ExtraInfo.

Referenced by AnyAliasLiveIn(), llvm::HexagonSubtarget::HVXMemLatencyMutation::apply(), llvm::HexagonSubtarget::BankConflictMutation::apply(), areCandidatesToMergeOrPair(), llvm::SIInstrInfo::areMemAccessesTriviallyDisjoint(), llvm::HexagonInstrInfo::areMemAccessesTriviallyDisjoint(), llvm::TargetInstrInfo::areMemAccessesTriviallyDisjoint(), llvm::ScheduleDAGInstrs::buildSchedGraph(), canMoveInstsAcrossMemOp(), CanMovePastDMB(), llvm::HexagonPacketizerList::canPromoteToNewValueStore(), llvm::TargetInstrInfo::defaultDefLatency(), llvm::HexagonFrameLowering::determineCalleeSaves(), llvm::WebAssemblyRegisterInfo::eliminateFrameIndex(), llvm::ThumbRegisterInfo::eliminateFrameIndex(), llvm::HexagonHazardRecognizer::EmitInstruction(), llvm::TargetLoweringBase::emitPatchPoint(), llvm::HexagonEvaluator::evaluate(), llvm::SIInstrInfo::expandPostRAPseudo(), llvm::TargetInstrInfo::foldMemoryOperand(), llvm::TargetInstrInfo::genAlternativeCodeSequence(), llvm::HexagonInstrInfo::getBaseAndOffsetPosition(), llvm::TargetInstrInfo::getInstrLatency(), llvm::GCNSubtarget::getMaxNumVGPRs(), llvm::SIInstrInfo::getMemOperandWithOffset(), getNewSource(), llvm::ARMBaseInstrInfo::getOperandLatency(), getPostIncrementOperand(), getRegClassForUnfoldedLoad(), getUnderlyingObjects(), hasOrderedMemoryRef(), INITIALIZE_PASS(), isCallerPreservedOrConstPhysReg(), isCopyFeedingInvariantStore(), isDependenceBarrier(), isDereferenceableInvariantLoad(), llvm::HexagonInstrInfo::isEarlySourceInstr(), isEFLAGSLive(), llvm::HexagonInstrInfo::isHVXMemWithAIndirect(), llvm::HexagonPacketizerList::isLegalToPacketizeTogether(), llvm::SIInstrInfo::isLoadFromStackSlot(), llvm::ARMBaseInstrInfo::isLoadFromStackSlotPostFE(), llvm::SwingSchedulerDAG::isLoopCarriedDep(), isSafeToMove(), isValidClauseInst(), matchPair(), mayLoadFromGOTOrConstantPool(), mayLoadOrStore(), llvm::AArch64RegisterInfo::needsFrameBaseReg(), packCmovGroup(), Query(), readsVCCZ(), llvm::HexagonHazardRecognizer::ShouldPreferAnother(), and SinkingPreventsImplicitNullCheck().

◆ mayLoadOrStore()

bool llvm::MachineInstr::mayLoadOrStore ( QueryType Type = AnyInBundle ) const

inline

Return true if this instruction could possibly read or modify memory.

Definition at line 830 of file MachineInstr.h.

References mayLoad(), and mayStore().

Referenced by areCandidatesToMergeOrPair(), llvm::LanaiInstrInfo::areMemAccessesTriviallyDisjoint(), llvm::AArch64InstrInfo::areMemAccessesTriviallyDisjoint(), canMoveInstsAcrossMemOp(), llvm::createX86OptimizeLEAs(), llvm::SITargetLowering::EmitInstrWithCustomInserter(), llvm::ARMHazardRecognizer::getHazardType(), llvm::AArch64InstrInfo::getMemOpBaseRegImmOfsOffsetOperand(), llvm::AArch64InstrInfo::getMemOperandWithOffsetWidth(), getMemOpKey(), llvm::AArch64InstrInfo::getOutliningCandidateInfo(), isFirstInstructionInSequence(), llvm::InstructionSelector::isObviouslySafeToFold(), mayAlias(), llvm::SIRegisterInfo::needsFrameBaseReg(), usedAsAddr(), and VerifyLowRegs().

◆ mayStore()

bool llvm::MachineInstr::mayStore ( QueryType Type = AnyInBundle ) const

inline

Return true if this instruction could possibly modify memory.

Instructions with this flag set are not necessarily simple store instructions, they may store a modified value based on their operands, or may not actually modify anything, for example.

Definition at line 820 of file MachineInstr.h.

References llvm::InlineAsm::Extra_MayStore, llvm::MachineOperand::getImm(), getOperand(), hasProperty(), isInlineAsm(), llvm::MCID::MayStore, and llvm::InlineAsm::MIOp_ExtraInfo.

Referenced by llvm::SUnit::addPredBarrier(), addRegsToSet(), AnyAliasLiveIn(), llvm::HexagonSubtarget::HVXMemLatencyMutation::apply(), llvm::HexagonSubtarget::BankConflictMutation::apply(), llvm::SIInstrInfo::areMemAccessesTriviallyDisjoint(), llvm::TargetInstrInfo::areMemAccessesTriviallyDisjoint(), llvm::ScheduleDAGInstrs::buildSchedGraph(), llvm::HexagonInstrInfo::canExecuteInBundle(), CanMovePastDMB(), cannotCoexistAsymm(), llvm::HexagonPacketizerList::canPromoteToNewValueStore(), llvm::ARMBaseInstrInfo::convertToThreeAddress(), llvm::createSIAddIMGInitPass(), llvm::createSIWholeQuadModePass(), llvm::HexagonFrameLowering::determineCalleeSaves(), llvm::WebAssemblyRegisterInfo::eliminateFrameIndex(), llvm::ThumbRegisterInfo::eliminateFrameIndex(), llvm::HexagonHazardRecognizer::EmitInstruction(), llvm::ARMAsmPrinter::EmitJumpTableTBInst(), llvm::TargetInstrInfo::foldMemoryOperand(), llvm::TargetInstrInfo::genAlternativeCodeSequence(), llvm::HexagonInstrInfo::getBaseAndOffsetPosition(), getInstrVecReg(), llvm::GCNSubtarget::getMaxNumVGPRs(), llvm::SIInstrInfo::getMemOperandWithOffset(), getUnderlyingObjects(), llvm::HexagonPacketizerList::hasDualStoreDependence(), hasOrderedMemoryRef(), hasRAWHazard(), llvm::SIInstrInfo::hasUnwantedEffectsWhenEXECEmpty(), INITIALIZE_PASS(), InstructionStoresToFI(), isCallerPreservedOrConstPhysReg(), isCopyFeedingInvariantStore(), llvm::HexagonInstrInfo::isEarlySourceInstr(), isFullCopyOf(), llvm::HexagonInstrInfo::isHVXMemWithAIndirect(), isInvariantStore(), llvm::HexagonPacketizerList::isLegalToPacketizeTogether(), isLoadFoldBarrier(), llvm::SwingSchedulerDAG::isLoopCarriedDep(), llvm::HexagonPacketizerList::isNewifiable(), isSafeToMove(), llvm::SIInstrInfo::isStoreToStackSlot(), llvm::ARMBaseInstrInfo::isStoreToStackSlotPostFE(), isValidClauseInst(), matchPair(), mayAlias(), mayAlias(), llvm::HexagonInstrInfo::mayBeNewStore(), mayLoadOrStore(), llvm::AArch64RegisterInfo::needsFrameBaseReg(), populateCandidates(), DeadCodeElimination::SetQueue< T >::push_back(), Query(), readsVCCZ(), and llvm::SIInstrInfo::verifyInstruction().

◆ memoperands()

ArrayRef<MachineMemOperand *> llvm::MachineInstr::memoperands ( ) const

inline

Access to memory operands of the instruction.

If there are none, that does not imply anything about whether the function accesses memory. Instead, the caller must behave conservatively.

Definition at line 516 of file MachineInstr.h.

References llvm::makeArrayRef().

Referenced by llvm::VLIWPacketizerList::alias(), AnyAliasLiveIn(), cloneMemRefs(), cloneMergedMemRefs(), createPHIsForSelects(), llvm::createX86FixupBWInsts(), findIncDecAfter(), llvm::TargetInstrInfo::foldMemoryOperand(), llvm::LegalizerInfo::getAction(), getCompareSourceReg(), getNumMemOperands(), getPostIndexedLoadStoreOpcode(), getStoreTarget(), getUnderlyingObjectsForInstr(), hasOneMemOperand(), hasOrderedMemoryRef(), INITIALIZE_PASS(), InstructionStoresToFI(), isDereferenceableInvariantLoad(), llvm::AArch64InstrInfo::isLdStPairSuppressed(), llvm::AArch64InstrInfo::isStridedAccess(), matchPair(), llvm::SIInstrInfo::mayAccessFlatAddressSpace(), mayLoadFromGOTOrConstantPool(), memoperands_begin(), memoperands_empty(), memoperands_end(), llvm::MIPrinter::print(), print(), readsVCCZ(), removePhis(), setPostInstrSymbol(), setPreInstrSymbol(), llvm::X86InstrInfo::unfoldMemoryOperand(), and VerifyLowRegs().

◆ memoperands_begin()

mmo_iterator llvm::MachineInstr::memoperands_begin ( ) const

inline

Access to memory operands of the instruction.

If memoperands_begin() == memoperands_end(), that does not imply anything about whether the function accesses memory. Instead, the caller must behave conservatively.

Definition at line 534 of file MachineInstr.h.

References memoperands().

Referenced by addMemOperand(), llvm::SIInstrInfo::areMemAccessesTriviallyDisjoint(), llvm::SystemZInstrInfo::areMemAccessesTriviallyDisjoint(), changeFCMPPredToAArch64CC(), cloneMergedMemRefs(), emitClzero(), emitComments(), llvm::PPCHazardRecognizer970::EmitInstruction(), llvm::ARMTargetLowering::EmitInstrWithCustomInserter(), expandLoadStackGuard(), llvm::AArch64InstrInfo::expandPostRAPseudo(), llvm::LegalizerHelper::fewerElementsVector(), findPotentialBlockers(), llvm::TargetInstrInfo::foldMemoryOperand(), llvm::SystemZInstrInfo::foldMemoryOperandImpl(), llvm::X86InstrInfo::foldMemoryOperandImpl(), llvm::PPCHazardRecognizer970::getHazardType(), llvm::ARMBaseInstrInfo::getNumLDMAddresses(), llvm::ARMBaseInstrInfo::getNumMicroOps(), llvm::ARMBaseInstrInfo::getOperandLatency(), getRetpolineSymbol(), getSmrdOpcode(), getStoreTarget(), getUnderlyingObjects(), llvm::TargetInstrInfo::hasLoadFromStackSlot(), llvm::TargetInstrInfo::hasStoreToStackSlot(), INITIALIZE_PASS(), InsertFPConstInst(), InsertFPImmInst(), InsertSPConstInst(), InsertSPImmInst(), isInstrUniform(), llvm::SwingSchedulerDAG::isLoopCarriedDep(), isMemoryOp(), IsSafeAndProfitableToMove(), llvm::SIInstrInfo::isStackAccess(), llvm::LegalizerHelper::lower(), matchPair(), mayAlias(), memOpsHaveSameBasePtr(), llvm::LegalizerHelper::narrowScalar(), offsetsDoNotOverlap(), false::IntervalSorter::operator()(), ReplaceFrameIndex(), RewriteP2Align(), llvm::AArch64InstrInfo::suppressLdStPair(), updateKillStatus(), VerifyLowRegs(), and X86SelectAddress().

◆ memoperands_empty()

bool llvm::MachineInstr::memoperands_empty ( ) const

inline

Return true if we don't have any memory operands which described the memory access done by this instruction.

If this is true, calling code must be conservative.

Definition at line 546 of file MachineInstr.h.

References memoperands().

Referenced by llvm::VLIWPacketizerList::alias(), AnyAliasLiveIn(), cloneMergedMemRefs(), dropMemRefs(), llvm::SITargetLowering::EmitInstrWithCustomInserter(), llvm::TargetInstrInfo::foldMemoryOperand(), llvm::PPCHazardRecognizer970::getHazardType(), getStoreTarget(), hasOrderedMemoryRef(), InstructionStoresToFI(), isDereferenceableInvariantLoad(), llvm::SIInstrInfo::isStackAccess(), llvm::SIInstrInfo::mayAccessFlatAddressSpace(), mayLoadFromGOTOrConstantPool(), llvm::MIPrinter::print(), print(), readsVCCZ(), removePhis(), setPostInstrSymbol(), setPreInstrSymbol(), and llvm::AArch64InstrInfo::suppressLdStPair().

◆ memoperands_end()

mmo_iterator llvm::MachineInstr::memoperands_end ( ) const

inline

Access to memory operands of the instruction.

If memoperands_begin() == memoperands_end(), that does not imply anything about whether the function accesses memory. Instead, the caller must behave conservatively.

Definition at line 541 of file MachineInstr.h.

References memoperands().

Referenced by addMemOperand(), cloneMergedMemRefs(), emitClzero(), llvm::TargetInstrInfo::foldMemoryOperand(), llvm::ARMBaseInstrInfo::getNumLDMAddresses(), getRetpolineSymbol(), llvm::TargetInstrInfo::hasLoadFromStackSlot(), llvm::TargetInstrInfo::hasStoreToStackSlot(), matchPair(), and false::IntervalSorter::operator()().

◆ mergeFlagsWith()

uint16_t MachineInstr::mergeFlagsWith ( const MachineInstr & Other ) const

Return the MIFlags which represent both MachineInstrs.

This should be used when merging two MachineInstrs into one. This routine does not modify the MIFlags of this MachineInstr.

Definition at line 516 of file MachineInstr.cpp.

References getFlags().

Referenced by setDebugLoc().

◆ modifiesRegister()

bool llvm::MachineInstr::modifiesRegister	(	unsigned	Reg,
		const TargetRegisterInfo *	TRI
	)		const

inline

Return true if the MachineInstr modifies (fully define or partially define) the specified register.

NOTE: It's ignoring subreg indices on virtual registers.

Definition at line 1151 of file MachineInstr.h.

References findRegisterDefOperandIdx().

Referenced by areCFlagsAccessedBetweenInstrs(), canInstrSubstituteCmpInstr(), llvm::HexagonPacketizerList::canPromoteToNewValueStore(), llvm::HexagonInstrInfo::DefinesPredicate(), doesModifyCalleeSavedReg(), llvm::SIRegisterInfo::findReachingDef(), llvm::AArch64InstrInfo::getOutliningCandidateInfo(), llvm::AArch64InstrInfo::getOutliningType(), llvm::X86InstrInfo::getOutliningType(), INITIALIZE_PASS(), llvm::SIInstrInfo::isBasicBlockPrologue(), llvm::AArch64InstrInfo::isCandidateToMergeOrPair(), isEndCF(), llvm::HexagonPacketizerList::isLegalToPacketizeTogether(), llvm::SIInstrInfo::isSchedulingBoundary(), llvm::TargetInstrInfo::isSchedulingBoundary(), isUnsafeToMoveAcross(), llvm::LanaiInstrInfo::optimizeCompareInstr(), llvm::ARMBaseInstrInfo::optimizeCompareInstr(), llvm::PPCInstrInfo::optimizeCompareInstr(), llvm::X86InstrInfo::optimizeCompareInstr(), readsVCCZ(), and UseReg().

◆ operands() [1/2]

iterator_range<mop_iterator> llvm::MachineInstr::operands ( )

inline

Definition at line 459 of file MachineInstr.h.

References llvm::make_range(), operands_begin(), and operands_end().

Referenced by addDefsUsesToList(), addImplicitDefUseOperands(), llvm::LiveIntervals::addKillFlags(), llvm::GISelInstProfileBuilder::addNodeID(), addRegisterDefined(), llvm::ScheduleDAGInstrs::addSchedBarrierDeps(), addToListsIfDependent(), allDefsAreDead(), llvm::AMDGPUInstructionSelector::AMDGPUInstructionSelector(), AnyAliasLiveIn(), AppendEndToFunction(), callHasRegMask(), llvm::HexagonPacketizerList::canPromoteToNewValueStore(), ClearKillFlags(), clearKillInfo(), clearRegisterDeads(), clearRegisterKills(), collectVirtualRegUses(), llvm::ScheduleDAGMILive::collectVRegUses(), computeLiveOuts(), llvm::createBreakFalseDeps(), definesFullReg(), llvm::HexagonHazardRecognizer::EmitInstruction(), llvm::RegScavenger::enterBasicBlockEnd(), eraseFromParentAndMarkDBGValuesForRemoval(), llvm::HexagonEvaluator::evaluate(), llvm::BitTracker::MachineEvaluator::evaluate(), findSinkableLocalRegDef(), findSurvivorBackwards(), getCalledFunction(), getCompareSourceReg(), llvm::MachineInstrExpressionTrait::getHashValue(), getMopState(), getNewValueJumpOpcode(), llvm::rdf::DataFlowGraph::getNextShadow(), llvm::AArch64InstrInfo::getOutliningType(), llvm::X86InstrInfo::getOutliningType(), getPostIncrementOperand(), getPredicatedRegister(), getRetOpcode(), getRetpolineSymbol(), getStartOrEndSlot(), handleNormalInst(), llvm::HexagonPacketizerList::hasDeadDependence(), hasRegisterDependency(), llvm::HexagonPacketizerList::hasRegMaskDependence(), hasWriteToReadDep(), hasYmmOrZmmReg(), INITIALIZE_PASS(), instrDefsUsesSCC(), InstructionStoresToFI(), llvm::HexagonPacketizerList::isCallDependent(), isCallerPreservedOrConstPhysReg(), isCopyFeedingInvariantStore(), llvm::ARMBaseInstrInfo::isCPSRDefined(), isCrossCopy(), llvm::HexagonInstrInfo::isExtended(), llvm::rdf::TargetOperandInfo::isFixedReg(), isHighLatencyCPSR(), isImplicitDependency(), isInvariantStore(), isNopCopy(), IsSafeToMove(), llvm::HexagonInstrInfo::isTailCall(), llvm::isTriviallyDead(), isVirtualRegisterOperand(), llvm::AArch64MCInstLower::Lower(), llvm::LowerARMMachineInstrToMCInst(), llvm::AVRMCInstLower::lowerInstruction(), llvm::LowerRISCVMachineInstrToMCInst(), MaySpeculate(), needsStackFrame(), llvm::rdf::operator<<(), performSink(), llvm::HexagonInstrInfo::predCanBeUsedAsDotNew(), profitImm(), DeadCodeElimination::SetQueue< T >::push_back(), regOverlapsSet(), llvm::X86InstrInfo::reMaterialize(), llvm::rdf::Liveness::resetKills(), llvm::SIRegisterInfo::resolveFrameIndex(), scavengeFrameVirtualRegsInBlock(), llvm::RegScavenger::scavengeRegister(), setPhysRegsDeadExcept(), setRegisterDefReadUndef(), substituteRegister(), toggleKills(), unsupportedBinOp(), llvm::LiveIntervals::HMEditor::updateAllRanges(), UpdateCPSRDef(), and UpdateCPSRUse().

◆ operands() [2/2]

iterator_range<const_mop_iterator> llvm::MachineInstr::operands ( ) const

inline

Definition at line 462 of file MachineInstr.h.

References llvm::make_range(), operands_begin(), and operands_end().

◆ operands_begin() [1/2]

mop_iterator llvm::MachineInstr::operands_begin ( )

inline

◆ operands_begin() [2/2]

const_mop_iterator llvm::MachineInstr::operands_begin ( ) const

inline

Definition at line 456 of file MachineInstr.h.

◆ operands_end() [1/2]

mop_iterator llvm::MachineInstr::operands_end ( )

inline

◆ operands_end() [2/2]

const_mop_iterator llvm::MachineInstr::operands_end ( ) const

inline

Definition at line 457 of file MachineInstr.h.

◆ operator=()

MachineInstr& llvm::MachineInstr::operator= ( const MachineInstr & )

delete

◆ print() [1/2]

void MachineInstr::print	(	raw_ostream &	OS,
		bool	IsStandalone = `true`,
		bool	SkipOpers = `false`,
		bool	SkipDebugLoc = `false`,
		bool	AddNewLine = `true`,
		const TargetInstrInfo *	TII = `nullptr`
	)		const

Print this MI to OS.

Don't print information that can be inferred from other instructions if IsStandalone is false. It is usually true when only a fragment of the function is printed. Only print the defs and the opcode if SkipOpers is true. Otherwise, also print operands if SkipDebugLoc is true. Otherwise, also print the debug loc, with a terminating newline. TII is used to print the opcode name. If it's not present, but the MI is in a function, the opcode will be printed using the function's TII.

Definition at line 1436 of file MachineInstr.cpp.

References F(), llvm::MachineFunction::getFunction(), llvm::TargetSubtargetInfo::getInstrInfo(), getMFIfAvailable(), llvm::GlobalValue::getParent(), llvm::MachineFunction::getSubtarget(), and llvm::ModuleSlotTracker::incorporateFunction().

Referenced by dump(), llvm::XCoreRegisterInfo::eliminateFrameIndex(), llvm::ARMTargetLowering::EmitInstrWithCustomInserter(), llvm::ARMAsmPrinter::EmitJumpTableTBInst(), llvm::ScheduleDAGInstrs::getGraphNodeLabel(), getRegClassFromGRPhysReg(), getRetOpcode(), llvm::HexagonLowerToMC(), INITIALIZE_PASS(), isRegTiedToDefOperand(), llvm::LegalizerHelper::legalizeInstrStep(), llvm::MSP430MCInstLower::Lower(), llvm::BPFMCInstLower::Lower(), llvm::LanaiMCInstLower::Lower(), llvm::WebAssemblyMCInstLower::Lower(), llvm::AVRMCInstLower::lowerInstruction(), llvm::DiagnosticInfoMIROptimization::MachineArgument::MachineArgument(), llvm::operator<<(), llvm::SMSchedule::print(), llvm::MachineBasicBlock::print(), readsVCCZ(), false::Chain::str(), and llvm::MachineFunction::verify().

◆ print() [2/2]

void MachineInstr::print	(	raw_ostream &	OS,
		ModuleSlotTracker &	MST,
		bool	IsStandalone = `true`,
		bool	SkipOpers = `false`,
		bool	SkipDebugLoc = `false`,
		bool	AddNewLine = `true`,
		const TargetInstrInfo *	TII = `nullptr`
	)		const

Definition at line 1454 of file MachineInstr.cpp.

◆ readsRegister()

bool llvm::MachineInstr::readsRegister	(	unsigned	Reg,
		const TargetRegisterInfo *	TRI = `nullptr`
	)		const

inline

Return true if the MachineInstr reads the specified register.

If TargetRegisterInfo is passed, then it also checks if there is a read of a super-register. This does not count partial redefines of virtual registers as reads: reg1024:6 = OP.

Definition at line 1113 of file MachineInstr.h.

References findRegisterUseOperandIdx(), and TRI.

Referenced by areCFlagsAccessedBetweenInstrs(), canInstrSubstituteCmpInstr(), checkAndUpdateCPSRKill(), checkAndUpdateEFLAGSKill(), checkCCKill(), llvm::TargetSchedModel::computeOutputLatency(), ContainsReg(), llvm::ARMBaseInstrInfo::convertToThreeAddress(), CriticalPathStep(), llvm::ARMBaseInstrInfo::expandPostRAPseudo(), llvm::RegBankSelect::getAnalysisUsage(), llvm::HexagonInstrInfo::getCompoundOpcode(), getImplicitSPRUseForDPRUse(), llvm::AArch64InstrInfo::getOutliningCandidateInfo(), llvm::AArch64InstrInfo::getOutliningType(), llvm::X86InstrInfo::getOutliningType(), llvm::X86InstrInfo::getPartialRegUpdateClearance(), hasRAWHazard(), hasWriteToReadDep(), ImposeStackOrdering(), INITIALIZE_PASS(), isCompareZero(), llvm::HexagonPacketizerList::isLegalToPacketizeTogether(), isLiveOut(), IsSafeToMove(), isUnsafeToMoveAcross(), llvm::LanaiInstrInfo::optimizeCompareInstr(), llvm::ARMBaseInstrInfo::optimizeCompareInstr(), llvm::PPCInstrInfo::optimizeCompareInstr(), llvm::X86InstrInfo::optimizeCompareInstr(), scavengeVReg(), llvm::ARMBaseInstrInfo::setExecutionDomain(), and swapMIOperands().

◆ readsVirtualRegister()

bool llvm::MachineInstr::readsVirtualRegister ( unsigned Reg ) const

inline

Return true if the MachineInstr reads the specified virtual register.

Take into account that a partial define is a read-modify-write operation.

Definition at line 1121 of file MachineInstr.h.

References readsWritesVirtualRegister(), and Reg.

Referenced by llvm::LiveRangeEdit::eraseVirtReg(), llvm::TargetInstrInfo::genAlternativeCodeSequence(), llvm::ARMBaseInstrInfo::getPartialRegUpdateClearance(), llvm::X86InstrInfo::getPartialRegUpdateClearance(), INITIALIZE_PASS(), and llvm::SplitEditor::leaveIntvAfter().

◆ readsWritesVirtualRegister()

std::pair< bool, bool > MachineInstr::readsWritesVirtualRegister	(	unsigned	Reg,
		SmallVectorImpl< unsigned > *	Ops = `nullptr`
	)		const

Return a pair of bools (reads, writes) indicating if this instruction reads or writes Reg.

readsWritesVirtualRegister - Return a pair of bools (reads, writes) indicating if this instruction reads or writes Reg.

This also considers partial defines. If Ops is not null, all operand indices for Reg are added.

This also considers partial defines.

Definition at line 948 of file MachineInstr.cpp.

References getNumOperands(), getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::getSubReg(), llvm::MachineOperand::isReg(), llvm::MachineOperand::isUndef(), llvm::MachineOperand::isUse(), llvm::SmallVectorTemplateBase< T, bool >::push_back(), and Reg.

Referenced by llvm::LiveRangeEdit::eraseVirtReg(), readsVirtualRegister(), and llvm::VirtRegAuxInfo::weightCalcHelper().

◆ registerDefIsDead()

bool llvm::MachineInstr::registerDefIsDead	(	unsigned	Reg,
		const TargetRegisterInfo *	TRI = `nullptr`
	)		const

inline

Returns true if the register is dead in this machine instruction.

If TargetRegisterInfo is passed, then it also checks if there is a dead def of a super-register.

Definition at line 1158 of file MachineInstr.h.

References findRegisterDefOperandIdx(), findRegisterUseOperandIdx(), hasRegisterImplicitUseOperand(), isKill(), and TRI.

Referenced by llvm::ScheduleDAGInstrs::addPhysRegDeps(), createPHIsForSelects(), llvm::X86InstrInfo::optimizeCompareInstr(), and transferDeadCC().

◆ removeFromBundle()

MachineInstr * MachineInstr::removeFromBundle ( )

Unlink this instruction from its basic block and return it without deleting it.

If the instruction is part of a bundle, the other instructions in the bundle remain bundled.

Definition at line 653 of file MachineInstr.cpp.

References assert(), getParent(), and llvm::MachineBasicBlock::remove_instr().

◆ removeFromParent()

MachineInstr * MachineInstr::removeFromParent ( )

Unlink 'this' from the containing basic block, and return it without deleting it.

This function can not be used on bundled instructions, use removeFromBundle() to remove individual instructions from a bundle.

Definition at line 648 of file MachineInstr.cpp.

References assert(), getParent(), and llvm::MachineBasicBlock::remove().

Referenced by llvm::createX86OptimizeLEAs(), findUncondBrI(), HasArgumentDef(), llvm::SIInstrInfo::legalizeOperands(), and llvm::ARMBaseInstrInfo::optimizeCompareInstr().

◆ RemoveOperand()

void MachineInstr::RemoveOperand ( unsigned OpNo )

Erase an operand from an instruction, leaving it with one fewer operand than it started with.

RemoveOperand - Erase an operand from an instruction, leaving it with one fewer operand than it started with.

Definition at line 295 of file MachineInstr.cpp.

References assert(), getNumOperands(), isReg(), moveOperands(), N, llvm::MachineRegisterInfo::removeRegOperandFromUseList(), and untieRegOperand().

Referenced by addRegisterDead(), addRegisterKilled(), llvm::SITargetLowering::AdjustInstrPostInstrSelection(), AppendEndToFunction(), llvm::SIInstrInfo::buildExtractSubRegOrImm(), llvm::createSIWholeQuadModePass(), dumpMachineInstrRangeWithSlotIndex(), llvm::AVRRegisterInfo::eliminateFrameIndex(), llvm::HexagonRegisterInfo::eliminateFrameIndex(), eraseGPOpnd(), llvm::LiveRangeEdit::eraseVirtReg(), llvm::ARMBaseInstrInfo::expandPostRAPseudo(), llvm::X86InstrInfo::expandPostRAPseudo(), llvm::PPCInstrInfo::expandPostRAPseudo(), llvm::SIInstrInfo::FoldImmediate(), llvm::MipsInstrInfo::genInstrWithNewOpc(), getCompareSourceReg(), getLeaOP(), getRegsUsedByPHIs(), INITIALIZE_PASS(), isCompareZero(), isImmValidForOpcode(), llvm::SIInstrInfo::moveToVALU(), llvm::AArch64InstrInfo::optimizeCompareInstr(), llvm::PPCInstrInfo::optimizeCompareInstr(), llvm::X86InstrInfo::optimizeCompareInstr(), llvm::SystemZInstrInfo::PredicateInstruction(), llvm::HexagonInstrInfo::PredicateInstruction(), llvm::PPCInstrInfo::PredicateInstruction(), removeModOperands(), removeOperands(), llvm::PPCInstrInfo::replaceInstrOperandWithImm(), llvm::PPCInstrInfo::replaceInstrWithLI(), llvm::rewriteARMFrameIndex(), llvm::rewriteT2FrameIndex(), setDebugLoc(), llvm::ARMBaseInstrInfo::setExecutionDomain(), shrinkScalarLogicOp(), stripExtraCopyOperands(), swapMIOperands(), tieOpsIfNeeded(), tryConstantFoldOp(), tryFoldInst(), llvm::tryFoldSPUpdateIntoPushPop(), updateOperand(), and X86SelectAddress().

◆ setAsmPrinterFlag()

void llvm::MachineInstr::setAsmPrinterFlag ( uint8_t Flag )

inline

Set a flag for the AsmPrinter.

Definition at line 280 of file MachineInstr.h.

Referenced by llvm::AsmPrinter::EmitFunctionBody(), and performCustomAdjustments().

◆ setDebugLoc()

void llvm::MachineInstr::setDebugLoc ( DebugLoc dl )

inline

Replace current source information with new such.

Avoid using this, the constructor argument is preferable.

Definition at line 1465 of file MachineInstr.h.

References addMemOperand(), assert(), cloneMemRefs(), cloneMergedMemRefs(), copyIRFlags(), dropMemRefs(), llvm::DebugLoc::hasTrivialDestructor(), I, mergeFlagsWith(), RemoveOperand(), setMemRefs(), setPostInstrSymbol(), setPreInstrSymbol(), and llvm::ARMBuildAttrs::Symbol.

Referenced by definesFullReg(), expandLoadStackGuard(), INITIALIZE_PASS(), isCopyFeedingInvariantStore(), isRegUsedByPhiNodes(), and performSink().

◆ setDesc()

void llvm::MachineInstr::setDesc ( const MCInstrDesc & tid )

inline

Replace the instruction descriptor (thus opcode) of the current instruction with a new one.

Definition at line 1461 of file MachineInstr.h.

◆ setFlag()

void llvm::MachineInstr::setFlag ( MIFlag Flag )

inline

Set a MI flag.

Definition at line 300 of file MachineInstr.h.

Referenced by bundleWithPred(), bundleWithSucc(), copyIRFlags(), llvm::InstrEmitter::EmitDbgLabel(), llvm::MIBundleBuilder::insert(), llvm::MachineBasicBlock::insert(), llvm::MachineInstrBuilder::setMIFlag(), and toString().

◆ setFlags()

void llvm::MachineInstr::setFlags ( unsigned flags )

inline

Definition at line 304 of file MachineInstr.h.

References BundledPred, BundledSucc, and llvm::BitmaskEnumDetail::Mask().

Referenced by addImplicitDefUseOperands(), and llvm::MachineInstrBuilder::setMIFlags().

◆ setMemRefs()

void MachineInstr::setMemRefs	(	MachineFunction &	MF,
		ArrayRef< MachineMemOperand *>	MemRefs
	)

Assign this MachineInstr's memory reference descriptor list.

Unlike other methods, this will allocate them into a new array associated with the provided MachineFunction.

Definition at line 342 of file MachineInstr.cpp.

References llvm::MachineFunction::createMIExtraInfo(), dropMemRefs(), llvm::ArrayRef< T >::empty(), getPostInstrSymbol(), getPreInstrSymbol(), and llvm::ArrayRef< T >::size().

Referenced by addMemOperand(), cloneMemRefs(), cloneMergedMemRefs(), llvm::TargetInstrInfo::foldMemoryOperand(), removePhis(), setDebugLoc(), and llvm::MachineInstrBuilder::setMemRefs().

◆ setPhysRegsDeadExcept()

void MachineInstr::setPhysRegsDeadExcept	(	ArrayRef< unsigned >	UsedRegs,
		const TargetRegisterInfo &	TRI
	)

Mark every physreg used by this instruction as dead except those in the UsedRegs list.

On instructions with register mask operands, also add implicit-def operands for all registers in UsedRegs.

Definition at line 1924 of file MachineInstr.cpp.

References addRegisterDefined(), llvm::ArrayRef< T >::begin(), E, llvm::ArrayRef< T >::end(), I, llvm::TargetRegisterInfo::isPhysicalRegister(), llvm::none_of(), operands(), and llvm::TargetRegisterInfo::regsOverlap().

Referenced by isRegTiedToDefOperand(), llvm::FastISel::lowerCallTo(), and llvm::FastISel::selectPatchpoint().

◆ setPostInstrSymbol()

void MachineInstr::setPostInstrSymbol	(	MachineFunction &	MF,
		MCSymbol *	Symbol
	)

Set a symbol that will be emitted just after the instruction itself.

Setting this to a null pointer will remove any such symbol.

FIXME: This is not fully implemented yet.

Definition at line 484 of file MachineInstr.cpp.

References assert(), llvm::MachineFunction::createMIExtraInfo(), getPostInstrSymbol(), getPreInstrSymbol(), memoperands(), memoperands_empty(), and llvm::ARMBuildAttrs::Symbol.

Referenced by isEFLAGSLive(), and setDebugLoc().

◆ setPreInstrSymbol()

void MachineInstr::setPreInstrSymbol	(	MachineFunction &	MF,
		MCSymbol *	Symbol
	)

Set a symbol that will be emitted just prior to the instruction itself.

Setting this to a null pointer will remove any such symbol.

FIXME: This is not fully implemented yet.

Definition at line 452 of file MachineInstr.cpp.

References assert(), llvm::MachineFunction::createMIExtraInfo(), getPostInstrSymbol(), getPreInstrSymbol(), memoperands(), memoperands_empty(), and llvm::ARMBuildAttrs::Symbol.

Referenced by llvm::createX86RetpolineThunksPass(), llvm::X86InstrInfo::getSerializableDirectMachineOperandTargetFlags(), and setDebugLoc().

◆ setRegisterDefReadUndef()

void MachineInstr::setRegisterDefReadUndef	(	unsigned	Reg,
		bool	IsUndef = `true`
	)

Mark all subregister defs of register Reg with the undef flag.

This function is used when we determined to have a subregister def in an otherwise undefined super register.

Definition at line 1898 of file MachineInstr.cpp.

References operands().

Referenced by llvm::RegisterOperands::adjustLaneLiveness(), isRegTiedToDefOperand(), and llvm::LiveIntervals::shrinkToUses().

◆ substituteRegister()

void MachineInstr::substituteRegister	(	unsigned	FromReg,
		unsigned	ToReg,
		unsigned	SubIdx,
		const TargetRegisterInfo &	RegInfo
	)

Replace all occurrences of FromReg with ToReg:SubIdx, properly composing subreg indices where necessary.

Definition at line 1125 of file MachineInstr.cpp.

References llvm::MCRegisterInfo::getSubReg(), llvm::TargetRegisterInfo::isPhysicalRegister(), and operands().

Referenced by llvm::LiveRangeEdit::eraseVirtReg(), INITIALIZE_PASS(), llvm::CoalescerPair::isCoalescable(), isRegTiedToDefOperand(), llvm::ARMBaseInstrInfo::reMaterialize(), llvm::X86InstrInfo::reMaterialize(), and llvm::TargetInstrInfo::reMaterialize().

◆ tieOperands()

void MachineInstr::tieOperands	(	unsigned	DefIdx,
		unsigned	UseIdx
	)

Add a tie between the register operands at DefIdx and UseIdx.

tieOperands - Mark operands at DefIdx and UseIdx as tied to each other.

The tie will cause the register allocator to ensure that the two operands are assigned the same physical register.

Tied operands are managed automatically for explicit operands in the MCInstrDesc. This method is for exceptional cases like inline asm.

Use and def operands can be tied together, indicated by a non-zero TiedTo field. TiedTo can have these values:

0: Operand is not tied to anything. 1 to TiedMax-1: Tied to getOperand(TiedTo-1). TiedMax: Tied to an operand >= TiedMax-1.

The tied def must be one of the first TiedMax operands on a normal instruction. INLINEASM instructions allow more tied defs.

Definition at line 1036 of file MachineInstr.cpp.

References assert(), getOperand(), llvm::MachineOperand::isDef(), isInlineAsm(), llvm::MachineOperand::isTied(), llvm::MachineOperand::isUse(), and TiedMax.

Referenced by addOperand(), llvm::constrainSelectedInstRegOperands(), llvm::createSIAddIMGInitPass(), findRegisterDefOperand(), findSingleRegDef(), isImplicitOperandIn(), matchSwap(), llvm::LanaiInstrInfo::optimizeSelect(), llvm::ARMBaseInstrInfo::optimizeSelect(), removePhis(), llvm::SystemZInstrInfo::SystemZInstrInfo(), and tieOpsIfNeeded().

◆ unbundleFromPred()

void MachineInstr::unbundleFromPred ( )

Break bundle above this instruction.

Definition at line 739 of file MachineInstr.cpp.

References assert(), BundledPred, BundledSucc, clearFlag(), llvm::ilist_node_impl< ilist_detail::compute_node_options< MachineInstr, Options... >::type >::getIterator(), and isBundledWithPred().

Referenced by isBundledWithSucc(), moveInstrOut(), and unbundleSingleMI().

◆ unbundleFromSucc()

void MachineInstr::unbundleFromSucc ( )

Break bundle below this instruction.

Definition at line 748 of file MachineInstr.cpp.

References assert(), BundledPred, BundledSucc, clearFlag(), llvm::ilist_node_impl< ilist_detail::compute_node_options< MachineInstr, Options... >::type >::getIterator(), and isBundledWithSucc().

Referenced by isBundledWithSucc(), and unbundleSingleMI().

◆ untieRegOperand()

void llvm::MachineInstr::untieRegOperand ( unsigned OpIdx )

inline

Break any tie involving OpIdx.

Definition at line 1533 of file MachineInstr.h.

References addImplicitDefUseOperands(), changeDebugValuesDefReg(), collectDebugValues(), findTiedOperandIdx(), getOperand(), llvm::MachineOperand::isReg(), llvm::MachineOperand::isTied(), and llvm::BitmaskEnumDetail::Mask().

Referenced by findStartOfTree(), llvm::SIInstrInfo::FoldImmediate(), RemoveOperand(), and tryAddToFoldList().

◆ uses() [1/2]

iterator_range<mop_iterator> llvm::MachineInstr::uses ( )

inline

Returns a range that includes all operands that are register uses.

This may include unrelated operands which are not register uses.

Definition at line 492 of file MachineInstr.h.

References getNumExplicitDefs(), llvm::make_range(), operands_begin(), and operands_end().

Referenced by addRegsToSet(), AnyAliasLiveIn(), ContainsReg(), llvm::createSIWholeQuadModePass(), findSingleRegDef(), handleNormalInst(), INITIALIZE_PASS(), instReadsReg(), isCrossCopy(), isNopCopy(), loadSRsrcFromVGPR(), matchPair(), split(), and false::Chain::str().

◆ uses() [2/2]

iterator_range<const_mop_iterator> llvm::MachineInstr::uses ( ) const

inline

Returns a range that includes all operands that are register uses.

This may include unrelated operands which are not register uses.

Definition at line 496 of file MachineInstr.h.

References getNumExplicitDefs(), llvm::make_range(), operands_begin(), and operands_end().

◆ usesCustomInsertionHook()

bool llvm::MachineInstr::usesCustomInsertionHook ( QueryType Type = IgnoreBundle ) const

inline

Return true if this instruction requires custom insertion support when the DAG scheduler is inserting it into a machine basic block.

If this is true for the instruction, it basically means that it is a pseudo instruction used at SelectionDAG time that is expanded out into magic code by the target when MachineInstrs are formed.

If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method is used to insert this into the MachineBasicBlock.

Definition at line 878 of file MachineInstr.h.

References hasProperty(), and llvm::MCID::UsesCustomInserter.

Referenced by INITIALIZE_PASS().

Friends And Related Function Documentation

◆ ilist_callback_traits< MachineBasicBlock >

friend struct ilist_callback_traits< MachineBasicBlock >

friend

Definition at line 232 of file MachineInstr.h.

◆ ilist_traits< MachineInstr >

friend struct ilist_traits< MachineInstr >

friend

Definition at line 231 of file MachineInstr.h.

◆ MachineFunction

friend class MachineFunction

friend

Definition at line 246 of file MachineInstr.h.

The documentation for this class was generated from the following files:

include/llvm/CodeGen/MachineInstr.h
lib/CodeGen/MachineInstr.cpp

Public Types

Public Member Functions

Friends

Additional Inherited Members

Detailed Description

Member Typedef Documentation

◆ const_mop_iterator

◆ mmo_iterator

◆ mop_iterator

Member Enumeration Documentation

◆ CommentFlag

◆ MICheckType

◆ MIFlag

◆ QueryType

Constructor & Destructor Documentation

◆ MachineInstr()

◆ ~MachineInstr()

Member Function Documentation

◆ addImplicitDefUseOperands()

◆ addMemOperand()

◆ addOperand() [1/2]

◆ addOperand() [2/2]

◆ addRegisterDead()

◆ addRegisterDefined()

◆ addRegisterKilled()

◆ allDefsAreDead()

◆ bundleWithPred()

◆ bundleWithSucc()

◆ canFoldAsLoad()

◆ changeDebugValuesDefReg()

◆ clearAsmPrinterFlag()

◆ clearAsmPrinterFlags()

◆ clearFlag()

◆ clearKillInfo()

◆ clearRegisterDeads()

◆ clearRegisterKills()

◆ cloneMemRefs()

◆ cloneMergedMemRefs()

◆ collectDebugValues()

◆ copyImplicitOps()

◆ copyIRFlags()

◆ definesRegister()

◆ defs() [1/2]

◆ defs() [2/2]

◆ dropMemRefs()

◆ dump()

◆ emitError()

◆ eraseFromBundle()

◆ eraseFromParent()

◆ eraseFromParentAndMarkDBGValuesForRemoval()

◆ explicit_operands() [1/2]

◆ explicit_operands() [2/2]

◆ explicit_uses() [1/2]

◆ explicit_uses() [2/2]

◆ findFirstPredOperandIdx()

◆ findInlineAsmFlagIdx()

◆ findRegisterDefOperand()

◆ findRegisterDefOperandIdx()

◆ findRegisterUseOperand() [1/2]

◆ findRegisterUseOperand() [2/2]

◆ findRegisterUseOperandIdx()

◆ findTiedOperandIdx()

◆ getAsmPrinterFlag()

◆ getAsmPrinterFlags()

◆ getBundleSize()

◆ getDebugExpression()

◆ getDebugLabel()

◆ getDebugLoc()

◆ getDebugVariable()

◆ getDesc()

◆ getFlag()

◆ getFlags()

◆ getInlineAsmDialect()

◆ getMF() [1/2]

◆ getMF() [2/2]

◆ getNumDefs()

◆ getNumExplicitDefs()

◆ getNumExplicitOperands()

◆ getNumMemOperands()

◆ getNumOperands()