14 #ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONINSTRINFO_H 15 #define LLVM_LIB_TARGET_HEXAGON_HEXAGONINSTRINFO_H 27 #define GET_INSTRINFO_HEADER 28 #include "HexagonGenInstrInfo.inc" 32 class HexagonSubtarget;
33 class MachineBranchProbabilityInfo;
34 class MachineFunction;
37 class TargetRegisterInfo;
42 enum BundleAttribute {
43 memShufDisabledMask = 0x4
46 virtual void anchor();
67 int &FrameIndex)
const override;
110 bool AllowModify)
const override;
116 int *BytesRemoved =
nullptr)
const override;
131 int *BytesAdded =
nullptr)
const override;
147 unsigned Iter,
unsigned MaxIter)
const override;
155 unsigned ExtraPredCycles,
165 unsigned NumTCycles,
unsigned ExtraTCycles,
167 unsigned NumFCycles,
unsigned ExtraFCycles,
188 const DebugLoc &DL,
unsigned DestReg,
unsigned SrcReg,
189 bool KillSrc)
const override;
197 unsigned SrcReg,
bool isKill,
int FrameIndex,
206 unsigned DestReg,
int FrameIndex,
252 std::vector<MachineOperand> &Pred)
const override;
281 unsigned &SrcReg2,
int &
Mask,
int &
Value)
const override;
288 unsigned *PredCost =
nullptr)
const override;
305 unsigned &OffsetPos)
const override;
321 unsigned UseIdx)
const override;
325 std::pair<unsigned, unsigned>
368 bool isExpr(
unsigned OpType)
const;
440 unsigned &AccessSize)
const;
468 unsigned &PredRegPos,
unsigned &PredRegFlags)
const;
524 #endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONINSTRINFO_H
short getNonExtOpcode(const MachineInstr &MI) const
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override
Return an array that contains the direct target flag values and their names.
bool isVecALU(const MachineInstr &MI) const
bool DefinesPredicate(MachineInstr &MI, std::vector< MachineOperand > &Pred) const override
If the specified instruction defines any predicate or condition code register(s) used for predication...
short changeAddrMode_io_rr(const MachineInstr &MI) const
This class is the base class for the comparison instructions.
short changeAddrMode_rr_io(short Opc) const
unsigned nonDbgBBSize(const MachineBasicBlock *BB) const
getInstrTimingClassLatency - Compute the instruction latency of a given instruction using Timing Clas...
This class represents lattice values for constants.
short changeAddrMode_io_abs(const MachineInstr &MI) const
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Store the specified register of the given register class to the specified stack frame index...
void setBundleNoShuf(MachineBasicBlock::instr_iterator MIB) const
short getEquivalentHWInstr(const MachineInstr &MI) const
DFAPacketizer * CreateTargetScheduleState(const TargetSubtargetInfo &STI) const override
Create machine specific model for scheduling.
bool isAbsoluteSet(const MachineInstr &MI) const
bool isJumpR(const MachineInstr &MI) const
bool SubsumesPredicate(ArrayRef< MachineOperand > Pred1, ArrayRef< MachineOperand > Pred2) const override
Returns true if the first specified predicate subsumes the second, e.g.
bool isConstExtended(const MachineInstr &MI) const
bool getInvertedPredSense(SmallVectorImpl< MachineOperand > &Cond) const
unsigned nonDbgBundleSize(MachineBasicBlock::const_iterator BundleHead) const
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
Reverses the branch condition of the specified condition list, returning false on success and true if...
int getMaxValue(const MachineInstr &MI) const
ArrayRef< std::pair< unsigned, const char * > > getSerializableBitmaskMachineOperandTargetFlags() const override
Return an array that contains the bitmask target flag values and their names.
bool reversePredSense(MachineInstr &MI) const
int getDotNewPredOp(const MachineInstr &MI, const MachineBranchProbabilityInfo *MBPI) const
bool isExpr(unsigned OpType) const
bool isTailCall(const MachineInstr &MI) const override
unsigned const TargetRegisterInfo * TRI
unsigned reduceLoopCount(MachineBasicBlock &MBB, MachineInstr *IndVar, MachineInstr &Cmp, SmallVectorImpl< MachineOperand > &Cond, SmallVectorImpl< MachineInstr *> &PrevInsts, unsigned Iter, unsigned MaxIter) const override
Generate code to reduce the loop iteration by one and check if the loop is finished.
bool producesStall(const MachineInstr &ProdMI, const MachineInstr &ConsMI) const
unsigned getMemAccessSize(const MachineInstr &MI) const
unsigned getSize(const MachineInstr &MI) const
int getDotCurOp(const MachineInstr &MI) const
bool isLateResultInstr(const MachineInstr &MI) const
void immediateExtend(MachineInstr &MI) const
immediateExtend - Changes the instruction in place to one using an immediate extender.
int getDotNewPredJumpOp(const MachineInstr &MI, const MachineBranchProbabilityInfo *MBPI) const
short changeAddrMode_ur_rr(short Opc) const
bool hasLoadFromStackSlot(const MachineInstr &MI, SmallVectorImpl< const MachineMemOperand *> &Accesses) const override
Check if the instruction or the bundle of instructions has load from stack slots. ...
bool isToBeScheduledASAP(const MachineInstr &MI1, const MachineInstr &MI2) const
void insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override
Insert a noop into the instruction stream at the specified point.
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
Analyze the branching code at the end of MBB, returning true if it cannot be understood (e...
bool isHVXVec(const MachineInstr &MI) const
bool isComplex(const MachineInstr &MI) const
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Load the specified register of the given register class from the specified stack frame index...
unsigned getInvertedPredicatedOpcode(const int Opc) const
ScheduleHazardRecognizer * CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, const ScheduleDAG *DAG) const override
Allocate and return a hazard recognizer to use for this target when scheduling the machine instructio...
short changeAddrMode_abs_io(const MachineInstr &MI) const
unsigned getCompoundOpcode(const MachineInstr &GA, const MachineInstr &GB) const
bool isPredicatedNew(const MachineInstr &MI) const
bool canExecuteInBundle(const MachineInstr &First, const MachineInstr &Second) const
Can these instructions execute at the same time in a bundle.
bool predOpcodeHasNot(ArrayRef< MachineOperand > Cond) const
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
bool isVecUsableNextPacket(const MachineInstr &ProdMI, const MachineInstr &ConsMI) const
bool isDotNewInst(const MachineInstr &MI) const
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
bool isDeallocRet(const MachineInstr &MI) const
bool isExtended(const MachineInstr &MI) const
bool hasStoreToStackSlot(const MachineInstr &MI, SmallVectorImpl< const MachineMemOperand *> &Accesses) const override
Check if the instruction or the bundle of instructions has store to stack slots.
bool isSolo(const MachineInstr &MI) const
bool isLateInstrFeedsEarlyInstr(const MachineInstr &LRMI, const MachineInstr &ESMI) const
MachineBasicBlock::instr_iterator expandVGatherPseudo(MachineInstr &MI) const
bool expandPostRAPseudo(MachineInstr &MI) const override
This function is called for all pseudo instructions that remain after register allocation.
bool PredicateInstruction(MachineInstr &MI, ArrayRef< MachineOperand > Cond) const override
Convert the instruction into a predicated instruction.
bool predCanBeUsedAsDotNew(const MachineInstr &MI, unsigned PredReg) const
MachineInstr * findLoopInstr(MachineBasicBlock *BB, unsigned EndLoopOp, MachineBasicBlock *TargetBB, SmallPtrSet< MachineBasicBlock *, 8 > &Visited) const
Find the hardware loop instruction used to set-up the specified loop.
SmallVector< MachineInstr *, 2 > getBranchingInstrs(MachineBasicBlock &MBB) const
bool doesNotReturn(const MachineInstr &CallMI) const
bool isEndLoopN(unsigned Opcode) const
bool isCompoundBranchInstr(const MachineInstr &MI) const
short changeAddrMode_io_rr(short Opc) const
bool isPredictedTaken(unsigned Opcode) const
int getMinValue(const MachineInstr &MI) const
bool getBundleNoShuf(const MachineInstr &MIB) const
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Itinerary data supplied by a subtarget to be used by a target.
short changeAddrMode_io_pi(short Opc) const
bool isTC1(const MachineInstr &MI) const
unsigned getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr &MI, unsigned *PredCost=nullptr) const override
Compute the instruction latency of a given instruction.
short changeAddrMode_rr_ur(short Opc) const
bool getPredReg(ArrayRef< MachineOperand > Cond, unsigned &PredReg, unsigned &PredRegPos, unsigned &PredRegFlags) const
unsigned getCExtOpNum(const MachineInstr &MI) const
MachineOperand * getBaseAndOffset(const MachineInstr &MI, int64_t &Offset, unsigned &AccessSize) const
This class is intended to be used as a base class for asm properties and features specific to the tar...
bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, BranchProbability Probability) const override
Return true if it's profitable for if-converter to duplicate instructions of specified accumulated in...
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
HazardRecognizer - This determines whether or not an instruction can be issued this cycle...
bool getIncrementValue(const MachineInstr &MI, int &Value) const override
If the instruction is an increment of a constant value, return the amount.
bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg, unsigned &SrcReg2, int &Mask, int &Value) const override
For a comparison instruction, return the source registers in SrcReg and SrcReg2 if having two registe...
bool validateBranchCond(const ArrayRef< MachineOperand > &Cond) const
MachineInstrBuilder & UseMI
bool isPredicable(const MachineInstr &MI) const override
Return true if the specified instruction can be predicated.
bool isAccumulator(const MachineInstr &MI) const
bool getBaseAndOffsetPosition(const MachineInstr &MI, unsigned &BasePos, unsigned &OffsetPos) const override
For instructions with a base and offset, return the position of the base register and offset operands...
bool isZeroExtendingLoad(const MachineInstr &MI) const
short changeAddrMode_io_abs(short Opc) const
bool hasUncondBranch(const MachineBasicBlock *B) const
short changeAddrMode_abs_io(short Opc) const
unsigned getAddrMode(const MachineInstr &MI) const
int getNonDotCurOp(const MachineInstr &MI) const
bool invertAndChangeJumpTarget(MachineInstr &MI, MachineBasicBlock *NewTarget) const
bool isTC2Early(const MachineInstr &MI) const
bool isValidAutoIncImm(const EVT VT, const int Offset) const
bool isFloat(const MachineInstr &MI) const
HexagonII::SubInstructionGroup getDuplexCandidateGroup(const MachineInstr &MI) const
void genAllInsnTimingClasses(MachineFunction &MF) const
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
short getPseudoInstrPair(const MachineInstr &MI) const
bool isEarlySourceInstr(const MachineInstr &MI) const
bool isPostIncrement(const MachineInstr &MI) const override
Return true for post-incremented instructions.
bool isExtendable(const MachineInstr &MI) const
bool isPredicated(const MachineInstr &MI) const override
Returns true if the instruction is already predicated.
bool hasPseudoInstrPair(const MachineInstr &MI) const
bool isIndirectCall(const MachineInstr &MI) const
bool isTC4x(const MachineInstr &MI) const
bool isDotCurInst(const MachineInstr &MI) const
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements...
bool isNewValueStore(const MachineInstr &MI) const
HexagonInstrInfo(HexagonSubtarget &ST)
std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned TF) const override
Decompose the machine operand's target flags into two values - the direct target flag value and any o...
bool isNewValueInst(const MachineInstr &MI) const
MachineOperand class - Representation of each machine instruction operand.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
bool isVecAcc(const MachineInstr &MI) const
short changeAddrMode_ur_rr(const MachineInstr &MI) const
MachineInstrBuilder MachineInstrBuilder & DefMI
bool hasEHLabel(const MachineBasicBlock *B) const
bool isJumpWithinBranchRange(const MachineInstr &MI, unsigned offset) const
unsigned getUnits(const MachineInstr &MI) const
short getRegForm(const MachineInstr &MI) const
unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
If the specified machine instruction is a direct store to a stack slot, return the virtual or physica...
uint64_t getType(const MachineInstr &MI) const
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
Insert branch code into the end of the specified MachineBasicBlock.
bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, BranchProbability Probability) const override
Return true if it's profitable to predicate instructions with accumulated instruction latency of "Num...
bool isSignExtendingLoad(const MachineInstr &MI) const
bool isOperandExtended(const MachineInstr &MI, unsigned OperandNum) const
unsigned getInlineAsmLength(const char *Str, const MCAsmInfo &MAI) const override
Measure the specified inline asm to determine an approximation of its length.
bool isDuplexPair(const MachineInstr &MIa, const MachineInstr &MIb) const
Symmetrical. See if these two instructions are fit for duplex pair.
bool isLateSourceInstr(const MachineInstr &MI) const
bool isSpillPredRegOp(const MachineInstr &MI) const
bool getMemOperandWithOffset(MachineInstr &LdSt, MachineOperand *&BaseOp, int64_t &Offset, const TargetRegisterInfo *TRI) const override
Get the base register and byte offset of a load/store instr.
unsigned createVR(MachineFunction *MF, MVT VT) const
HexagonInstrInfo specifics.
bool isSchedulingBoundary(const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const override
Test if the given instruction should be considered a scheduling boundary.
unsigned reversePrediction(unsigned Opcode) const
bool isNewValue(const MachineInstr &MI) const
bool isSaveCalleeSavedRegsCall(const MachineInstr &MI) const
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
Remove the branching code at the end of the specific MBB.
unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
TargetInstrInfo overrides.
int getDotNewOp(const MachineInstr &MI) const
int getCondOpcode(int Opc, bool sense) const
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
Emit instructions to copy a pair of physical registers.
TargetSubtargetInfo - Generic base class for all target subtargets.
bool isPredicateLate(unsigned Opcode) const
Representation of each machine instruction.
bool addLatencyToSchedule(const MachineInstr &MI1, const MachineInstr &MI2) const
bool isDependent(const MachineInstr &ProdMI, const MachineInstr &ConsMI) const
int getDotOldOp(const MachineInstr &MI) const
bool isValidOffset(unsigned Opcode, int Offset, const TargetRegisterInfo *TRI, bool Extend=true) const
bool mayBeNewStore(const MachineInstr &MI) const
bool isPredicatedTrue(const MachineInstr &MI) const
bool isNewValueJump(const MachineInstr &MI) const
bool hasNonExtEquivalent(const MachineInstr &MI) const
unsigned getInstrTimingClassLatency(const InstrItineraryData *ItinData, const MachineInstr &MI) const
int getOperandLatency(const InstrItineraryData *ItinData, const MachineInstr &DefMI, unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const override
getOperandLatency - Compute and return the use operand latency of a given pair of def and use...
Instructions::iterator instr_iterator
bool isTC2(const MachineInstr &MI) const
bool isLoopN(const MachineInstr &MI) const
bool isHVXMemWithAIndirect(const MachineInstr &I, const MachineInstr &J) const
LLVM Value Representation.
bool PredOpcodeHasJMP_c(unsigned Opcode) const
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
bool mayBeCurLoad(const MachineInstr &MI) const
bool isAddrModeWithOffset(const MachineInstr &MI) const
short changeAddrMode_pi_io(short Opc) const
bool isMemOp(const MachineInstr &MI) const
short changeAddrMode_rr_io(const MachineInstr &MI) const
short changeAddrMode_rr_ur(const MachineInstr &MI) const
bool isBaseImmOffset(const MachineInstr &MI) const
bool analyzeLoop(MachineLoop &L, MachineInstr *&IndVarInst, MachineInstr *&CmpInst) const override
Analyze the loop code, return true if it cannot be understood.
Instructions::const_iterator const_instr_iterator
bool isIndirectL4Return(const MachineInstr &MI) const
bool areMemAccessesTriviallyDisjoint(MachineInstr &MIa, MachineInstr &MIb, AliasAnalysis *AA=nullptr) const override
HexagonII::CompoundGroup getCompoundCandidateGroup(const MachineInstr &MI) const