LLVM
8.0.1
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This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representation suitable for instruction selection. More...
#include "llvm/CodeGen/SelectionDAG.h"
Classes | |
struct | DAGNodeDeletedListener |
struct | DAGUpdateListener |
Clients of various APIs that cause global effects on the DAG can optionally implement this interface. More... | |
Public Types | |
enum | OverflowKind { OFK_Never, OFK_Sometime, OFK_Always } |
Used to represent the possible overflow behavior of an operation. More... | |
using | allnodes_const_iterator = ilist< SDNode >::const_iterator |
using | allnodes_iterator = ilist< SDNode >::iterator |
Public Member Functions | |
SelectionDAG (const TargetMachine &TM, CodeGenOpt::Level) | |
SelectionDAG (const SelectionDAG &)=delete | |
SelectionDAG & | operator= (const SelectionDAG &)=delete |
~SelectionDAG () | |
void | init (MachineFunction &NewMF, OptimizationRemarkEmitter &NewORE, Pass *PassPtr, const TargetLibraryInfo *LibraryInfo, LegacyDivergenceAnalysis *Divergence) |
Prepare this SelectionDAG to process code in the given MachineFunction. More... | |
void | setFunctionLoweringInfo (FunctionLoweringInfo *FuncInfo) |
void | clear () |
Clear state and free memory necessary to make this SelectionDAG ready to process a new block. More... | |
MachineFunction & | getMachineFunction () const |
const Pass * | getPass () const |
const DataLayout & | getDataLayout () const |
const TargetMachine & | getTarget () const |
const TargetSubtargetInfo & | getSubtarget () const |
const TargetLowering & | getTargetLoweringInfo () const |
const TargetLibraryInfo & | getLibInfo () const |
const SelectionDAGTargetInfo & | getSelectionDAGInfo () const |
LLVMContext * | getContext () const |
OptimizationRemarkEmitter & | getORE () const |
void | viewGraph (const std::string &Title) |
Pop up a GraphViz/gv window with the DAG rendered using 'dot'. More... | |
void | viewGraph () |
void | clearGraphAttrs () |
Clear all previously defined node graph attributes. More... | |
void | setGraphAttrs (const SDNode *N, const char *Attrs) |
Set graph attributes for a node. (eg. "color=red".) More... | |
const std::string | getGraphAttrs (const SDNode *N) const |
Get graph attributes for a node. More... | |
void | setGraphColor (const SDNode *N, const char *Color) |
Convenience for setting node color attribute. More... | |
void | setSubgraphColor (SDNode *N, const char *Color) |
Convenience for setting subgraph color attribute. More... | |
allnodes_const_iterator | allnodes_begin () const |
allnodes_const_iterator | allnodes_end () const |
allnodes_iterator | allnodes_begin () |
allnodes_iterator | allnodes_end () |
ilist< SDNode >::size_type | allnodes_size () const |
iterator_range< allnodes_iterator > | allnodes () |
iterator_range< allnodes_const_iterator > | allnodes () const |
const SDValue & | getRoot () const |
Return the root tag of the SelectionDAG. More... | |
SDValue | getEntryNode () const |
Return the token chain corresponding to the entry of the function. More... | |
const SDValue & | setRoot (SDValue N) |
Set the current root tag of the SelectionDAG. More... | |
void | VerifyDAGDiverence () |
void | Combine (CombineLevel Level, AliasAnalysis *AA, CodeGenOpt::Level OptLevel) |
This iterates over the nodes in the SelectionDAG, folding certain types of nodes together, or eliminating superfluous nodes. More... | |
bool | LegalizeTypes () |
This transforms the SelectionDAG into a SelectionDAG that only uses types natively supported by the target. More... | |
void | Legalize () |
This transforms the SelectionDAG into a SelectionDAG that is compatible with the target instruction selector, as indicated by the TargetLowering object. More... | |
bool | LegalizeOp (SDNode *N, SmallSetVector< SDNode *, 16 > &UpdatedNodes) |
Transforms a SelectionDAG node and any operands to it into a node that is compatible with the target instruction selector, as indicated by the TargetLowering object. More... | |
bool | LegalizeVectors () |
This transforms the SelectionDAG into a SelectionDAG that only uses vector math operations supported by the target. More... | |
void | RemoveDeadNodes () |
This method deletes all unreachable nodes in the SelectionDAG. More... | |
void | DeleteNode (SDNode *N) |
Remove the specified node from the system. More... | |
SDVTList | getVTList (EVT VT) |
Return an SDVTList that represents the list of values specified. More... | |
SDVTList | getVTList (EVT VT1, EVT VT2) |
SDVTList | getVTList (EVT VT1, EVT VT2, EVT VT3) |
SDVTList | getVTList (EVT VT1, EVT VT2, EVT VT3, EVT VT4) |
SDVTList | getVTList (ArrayRef< EVT > VTs) |
SDValue | getGlobalAddress (const GlobalValue *GV, const SDLoc &DL, EVT VT, int64_t offset=0, bool isTargetGA=false, unsigned char TargetFlags=0) |
SDValue | getTargetGlobalAddress (const GlobalValue *GV, const SDLoc &DL, EVT VT, int64_t offset=0, unsigned char TargetFlags=0) |
SDValue | getFrameIndex (int FI, EVT VT, bool isTarget=false) |
SDValue | getTargetFrameIndex (int FI, EVT VT) |
SDValue | getJumpTable (int JTI, EVT VT, bool isTarget=false, unsigned char TargetFlags=0) |
SDValue | getTargetJumpTable (int JTI, EVT VT, unsigned char TargetFlags=0) |
SDValue | getConstantPool (const Constant *C, EVT VT, unsigned Align=0, int Offs=0, bool isT=false, unsigned char TargetFlags=0) |
SDValue | getTargetConstantPool (const Constant *C, EVT VT, unsigned Align=0, int Offset=0, unsigned char TargetFlags=0) |
SDValue | getConstantPool (MachineConstantPoolValue *C, EVT VT, unsigned Align=0, int Offs=0, bool isT=false, unsigned char TargetFlags=0) |
SDValue | getTargetConstantPool (MachineConstantPoolValue *C, EVT VT, unsigned Align=0, int Offset=0, unsigned char TargetFlags=0) |
SDValue | getTargetIndex (int Index, EVT VT, int64_t Offset=0, unsigned char TargetFlags=0) |
SDValue | getBasicBlock (MachineBasicBlock *MBB) |
SDValue | getBasicBlock (MachineBasicBlock *MBB, SDLoc dl) |
SDValue | getExternalSymbol (const char *Sym, EVT VT) |
SDValue | getExternalSymbol (const char *Sym, const SDLoc &dl, EVT VT) |
SDValue | getTargetExternalSymbol (const char *Sym, EVT VT, unsigned char TargetFlags=0) |
SDValue | getMCSymbol (MCSymbol *Sym, EVT VT) |
SDValue | getValueType (EVT) |
SDValue | getRegister (unsigned Reg, EVT VT) |
SDValue | getRegisterMask (const uint32_t *RegMask) |
SDValue | getEHLabel (const SDLoc &dl, SDValue Root, MCSymbol *Label) |
SDValue | getLabelNode (unsigned Opcode, const SDLoc &dl, SDValue Root, MCSymbol *Label) |
SDValue | getBlockAddress (const BlockAddress *BA, EVT VT, int64_t Offset=0, bool isTarget=false, unsigned char TargetFlags=0) |
SDValue | getTargetBlockAddress (const BlockAddress *BA, EVT VT, int64_t Offset=0, unsigned char TargetFlags=0) |
SDValue | getCopyToReg (SDValue Chain, const SDLoc &dl, unsigned Reg, SDValue N) |
SDValue | getCopyToReg (SDValue Chain, const SDLoc &dl, unsigned Reg, SDValue N, SDValue Glue) |
SDValue | getCopyToReg (SDValue Chain, const SDLoc &dl, SDValue Reg, SDValue N, SDValue Glue) |
SDValue | getCopyFromReg (SDValue Chain, const SDLoc &dl, unsigned Reg, EVT VT) |
SDValue | getCopyFromReg (SDValue Chain, const SDLoc &dl, unsigned Reg, EVT VT, SDValue Glue) |
SDValue | getCondCode (ISD::CondCode Cond) |
SDValue | getVectorShuffle (EVT VT, const SDLoc &dl, SDValue N1, SDValue N2, ArrayRef< int > Mask) |
Return an ISD::VECTOR_SHUFFLE node. More... | |
SDValue | getBuildVector (EVT VT, const SDLoc &DL, ArrayRef< SDValue > Ops) |
Return an ISD::BUILD_VECTOR node. More... | |
SDValue | getBuildVector (EVT VT, const SDLoc &DL, ArrayRef< SDUse > Ops) |
Return an ISD::BUILD_VECTOR node. More... | |
SDValue | getSplatBuildVector (EVT VT, const SDLoc &DL, SDValue Op) |
Return a splat ISD::BUILD_VECTOR node, consisting of Op splatted to all elements. More... | |
SDValue | getCommutedVectorShuffle (const ShuffleVectorSDNode &SV) |
Returns an ISD::VECTOR_SHUFFLE node semantically equivalent to the shuffle node in input but with swapped operands. More... | |
SDValue | getFPExtendOrRound (SDValue Op, const SDLoc &DL, EVT VT) |
Convert Op, which must be of float type, to the float type VT, by either extending or rounding (by truncation). More... | |
SDValue | getAnyExtOrTrunc (SDValue Op, const SDLoc &DL, EVT VT) |
Convert Op, which must be of integer type, to the integer type VT, by either any-extending or truncating it. More... | |
SDValue | getSExtOrTrunc (SDValue Op, const SDLoc &DL, EVT VT) |
Convert Op, which must be of integer type, to the integer type VT, by either sign-extending or truncating it. More... | |
SDValue | getZExtOrTrunc (SDValue Op, const SDLoc &DL, EVT VT) |
Convert Op, which must be of integer type, to the integer type VT, by either zero-extending or truncating it. More... | |
SDValue | getZeroExtendInReg (SDValue Op, const SDLoc &DL, EVT VT) |
Return the expression required to zero extend the Op value assuming it was the smaller SrcTy value. More... | |
SDValue | getBoolExtOrTrunc (SDValue Op, const SDLoc &SL, EVT VT, EVT OpVT) |
Convert Op, which must be of integer type, to the integer type VT, by using an extension appropriate for the target's BooleanContent for type OpVT or truncating it. More... | |
SDValue | getNOT (const SDLoc &DL, SDValue Val, EVT VT) |
Create a bitwise NOT operation as (XOR Val, -1). More... | |
SDValue | getLogicalNOT (const SDLoc &DL, SDValue Val, EVT VT) |
Create a logical NOT operation as (XOR Val, BooleanOne). More... | |
SDValue | getObjectPtrOffset (const SDLoc &SL, SDValue Op, int64_t Offset) |
Create an add instruction with appropriate flags when used for addressing some offset of an object. More... | |
SDValue | getObjectPtrOffset (const SDLoc &SL, SDValue Op, SDValue Offset) |
SDValue | getCALLSEQ_START (SDValue Chain, uint64_t InSize, uint64_t OutSize, const SDLoc &DL) |
Return a new CALLSEQ_START node, that starts new call frame, in which InSize bytes are set up inside CALLSEQ_START..CALLSEQ_END sequence and OutSize specifies part of the frame set up prior to the sequence. More... | |
SDValue | getCALLSEQ_END (SDValue Chain, SDValue Op1, SDValue Op2, SDValue InGlue, const SDLoc &DL) |
Return a new CALLSEQ_END node, which always must have a glue result (to ensure it's not CSE'd). More... | |
bool | isUndef (unsigned Opcode, ArrayRef< SDValue > Ops) |
Return true if the result of this operation is always undefined. More... | |
SDValue | getUNDEF (EVT VT) |
Return an UNDEF node. UNDEF does not have a useful SDLoc. More... | |
SDValue | getGLOBAL_OFFSET_TABLE (EVT VT) |
Return a GLOBAL_OFFSET_TABLE node. This does not have a useful SDLoc. More... | |
SDValue | getNode (unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops) |
Gets or creates the specified node. More... | |
SDValue | getNode (unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDValue > Ops, const SDNodeFlags Flags=SDNodeFlags()) |
SDValue | getNode (unsigned Opcode, const SDLoc &DL, ArrayRef< EVT > ResultTys, ArrayRef< SDValue > Ops) |
SDValue | getNode (unsigned Opcode, const SDLoc &DL, SDVTList VTList, ArrayRef< SDValue > Ops) |
SDValue | getNode (unsigned Opcode, const SDLoc &DL, EVT VT) |
Gets or creates the specified node. More... | |
SDValue | getNode (unsigned Opcode, const SDLoc &DL, EVT VT, SDValue Operand, const SDNodeFlags Flags=SDNodeFlags()) |
SDValue | getNode (unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N1, SDValue N2, const SDNodeFlags Flags=SDNodeFlags()) |
SDValue | getNode (unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N1, SDValue N2, SDValue N3, const SDNodeFlags Flags=SDNodeFlags()) |
SDValue | getNode (unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N1, SDValue N2, SDValue N3, SDValue N4) |
SDValue | getNode (unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N1, SDValue N2, SDValue N3, SDValue N4, SDValue N5) |
SDValue | getNode (unsigned Opcode, const SDLoc &DL, SDVTList VTList) |
SDValue | getNode (unsigned Opcode, const SDLoc &DL, SDVTList VTList, SDValue N) |
SDValue | getNode (unsigned Opcode, const SDLoc &DL, SDVTList VTList, SDValue N1, SDValue N2) |
SDValue | getNode (unsigned Opcode, const SDLoc &DL, SDVTList VTList, SDValue N1, SDValue N2, SDValue N3) |
SDValue | getNode (unsigned Opcode, const SDLoc &DL, SDVTList VTList, SDValue N1, SDValue N2, SDValue N3, SDValue N4) |
SDValue | getNode (unsigned Opcode, const SDLoc &DL, SDVTList VTList, SDValue N1, SDValue N2, SDValue N3, SDValue N4, SDValue N5) |
SDValue | getStackArgumentTokenFactor (SDValue Chain) |
Compute a TokenFactor to force all the incoming stack arguments to be loaded from the stack. More... | |
SDValue | getMemcpy (SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, bool isVol, bool AlwaysInline, bool isTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) |
SDValue | getMemmove (SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, bool isVol, bool isTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) |
SDValue | getMemset (SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, bool isVol, bool isTailCall, MachinePointerInfo DstPtrInfo) |
SDValue | getAtomicMemcpy (SDValue Chain, const SDLoc &dl, SDValue Dst, unsigned DstAlign, SDValue Src, unsigned SrcAlign, SDValue Size, Type *SizeTy, unsigned ElemSz, bool isTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) |
SDValue | getAtomicMemmove (SDValue Chain, const SDLoc &dl, SDValue Dst, unsigned DstAlign, SDValue Src, unsigned SrcAlign, SDValue Size, Type *SizeTy, unsigned ElemSz, bool isTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) |
SDValue | getAtomicMemset (SDValue Chain, const SDLoc &dl, SDValue Dst, unsigned DstAlign, SDValue Value, SDValue Size, Type *SizeTy, unsigned ElemSz, bool isTailCall, MachinePointerInfo DstPtrInfo) |
SDValue | getSetCC (const SDLoc &DL, EVT VT, SDValue LHS, SDValue RHS, ISD::CondCode Cond) |
Helper function to make it easier to build SetCC's if you just have an ISD::CondCode instead of an SDValue. More... | |
SDValue | getSelect (const SDLoc &DL, EVT VT, SDValue Cond, SDValue LHS, SDValue RHS) |
Helper function to make it easier to build Select's if you just have operands and don't want to check for vector. More... | |
SDValue | getSelectCC (const SDLoc &DL, SDValue LHS, SDValue RHS, SDValue True, SDValue False, ISD::CondCode Cond) |
Helper function to make it easier to build SelectCC's if you just have an ISD::CondCode instead of an SDValue. More... | |
SDValue | simplifySelect (SDValue Cond, SDValue TVal, SDValue FVal) |
Try to simplify a select/vselect into 1 of its operands or a constant. More... | |
SDValue | simplifyShift (SDValue X, SDValue Y) |
Try to simplify a shift into 1 of its operands or a constant. More... | |
SDValue | getVAArg (EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, SDValue SV, unsigned Align) |
VAArg produces a result and token chain, and takes a pointer and a source value as input. More... | |
SDValue | getAtomicCmpSwap (unsigned Opcode, const SDLoc &dl, EVT MemVT, SDVTList VTs, SDValue Chain, SDValue Ptr, SDValue Cmp, SDValue Swp, MachinePointerInfo PtrInfo, unsigned Alignment, AtomicOrdering SuccessOrdering, AtomicOrdering FailureOrdering, SyncScope::ID SSID) |
Gets a node for an atomic cmpxchg op. More... | |
SDValue | getAtomicCmpSwap (unsigned Opcode, const SDLoc &dl, EVT MemVT, SDVTList VTs, SDValue Chain, SDValue Ptr, SDValue Cmp, SDValue Swp, MachineMemOperand *MMO) |
SDValue | getAtomic (unsigned Opcode, const SDLoc &dl, EVT MemVT, SDValue Chain, SDValue Ptr, SDValue Val, const Value *PtrVal, unsigned Alignment, AtomicOrdering Ordering, SyncScope::ID SSID) |
Gets a node for an atomic op, produces result (if relevant) and chain and takes 2 operands. More... | |
SDValue | getAtomic (unsigned Opcode, const SDLoc &dl, EVT MemVT, SDValue Chain, SDValue Ptr, SDValue Val, MachineMemOperand *MMO) |
SDValue | getAtomic (unsigned Opcode, const SDLoc &dl, EVT MemVT, EVT VT, SDValue Chain, SDValue Ptr, MachineMemOperand *MMO) |
Gets a node for an atomic op, produces result and chain and takes 1 operand. More... | |
SDValue | getAtomic (unsigned Opcode, const SDLoc &dl, EVT MemVT, SDVTList VTList, ArrayRef< SDValue > Ops, MachineMemOperand *MMO) |
Gets a node for an atomic op, produces result and chain and takes N operands. More... | |
SDValue | getMemIntrinsicNode (unsigned Opcode, const SDLoc &dl, SDVTList VTList, ArrayRef< SDValue > Ops, EVT MemVT, MachinePointerInfo PtrInfo, unsigned Align=0, MachineMemOperand::Flags Flags=MachineMemOperand::MOLoad|MachineMemOperand::MOStore, unsigned Size=0) |
Creates a MemIntrinsicNode that may produce a result and takes a list of operands. More... | |
SDValue | getMemIntrinsicNode (unsigned Opcode, const SDLoc &dl, SDVTList VTList, ArrayRef< SDValue > Ops, EVT MemVT, MachineMemOperand *MMO) |
SDValue | getMergeValues (ArrayRef< SDValue > Ops, const SDLoc &dl) |
Create a MERGE_VALUES node from the given operands. More... | |
SDValue | getLoad (EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, unsigned Alignment=0, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr) |
Loads are not normal binary operators: their result type is not determined by their operands, and they produce a value AND a token chain. More... | |
SDValue | getLoad (EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, MachineMemOperand *MMO) |
SDValue | getExtLoad (ISD::LoadExtType ExtType, const SDLoc &dl, EVT VT, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, EVT MemVT, unsigned Alignment=0, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes()) |
SDValue | getExtLoad (ISD::LoadExtType ExtType, const SDLoc &dl, EVT VT, SDValue Chain, SDValue Ptr, EVT MemVT, MachineMemOperand *MMO) |
SDValue | getIndexedLoad (SDValue OrigLoad, const SDLoc &dl, SDValue Base, SDValue Offset, ISD::MemIndexedMode AM) |
SDValue | getLoad (ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, SDValue Offset, MachinePointerInfo PtrInfo, EVT MemVT, unsigned Alignment=0, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr) |
SDValue | getLoad (ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, SDValue Offset, EVT MemVT, MachineMemOperand *MMO) |
SDValue | getStore (SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, unsigned Alignment=0, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes()) |
Helper function to build ISD::STORE nodes. More... | |
SDValue | getStore (SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachineMemOperand *MMO) |
SDValue | getTruncStore (SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, EVT SVT, unsigned Alignment=0, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes()) |
SDValue | getTruncStore (SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, EVT SVT, MachineMemOperand *MMO) |
SDValue | getIndexedStore (SDValue OrigStore, const SDLoc &dl, SDValue Base, SDValue Offset, ISD::MemIndexedMode AM) |
SDValue | getMemBasePlusOffset (SDValue Base, unsigned Offset, const SDLoc &DL) |
Returns sum of the base pointer and offset. More... | |
SDValue | getMaskedLoad (EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, SDValue Mask, SDValue Src0, EVT MemVT, MachineMemOperand *MMO, ISD::LoadExtType, bool IsExpanding=false) |
SDValue | getMaskedStore (SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, SDValue Mask, EVT MemVT, MachineMemOperand *MMO, bool IsTruncating=false, bool IsCompressing=false) |
SDValue | getMaskedGather (SDVTList VTs, EVT VT, const SDLoc &dl, ArrayRef< SDValue > Ops, MachineMemOperand *MMO) |
SDValue | getMaskedScatter (SDVTList VTs, EVT VT, const SDLoc &dl, ArrayRef< SDValue > Ops, MachineMemOperand *MMO) |
template<class TargetMemSDNode > | |
SDValue | getTargetMemSDNode (SDVTList VTs, ArrayRef< SDValue > Ops, const SDLoc &dl, EVT MemVT, MachineMemOperand *MMO) |
Return (create a new or find existing) a target-specific node. More... | |
SDValue | getSrcValue (const Value *v) |
Construct a node to track a Value* through the backend. More... | |
SDValue | getMDNode (const MDNode *MD) |
Return an MDNodeSDNode which holds an MDNode. More... | |
SDValue | getBitcast (EVT VT, SDValue V) |
Return a bitcast using the SDLoc of the value operand, and casting to the provided type. More... | |
SDValue | getAddrSpaceCast (const SDLoc &dl, EVT VT, SDValue Ptr, unsigned SrcAS, unsigned DestAS) |
Return an AddrSpaceCastSDNode. More... | |
SDValue | getShiftAmountOperand (EVT LHSTy, SDValue Op) |
Return the specified value casted to the target's desired shift amount type. More... | |
SDValue | expandVAArg (SDNode *Node) |
Expand the specified ISD::VAARG node as the Legalize pass would. More... | |
SDValue | expandVACopy (SDNode *Node) |
Expand the specified ISD::VACOPY node as the Legalize pass would. More... | |
SDValue | getSymbolFunctionGlobalAddress (SDValue Op, Function **TargetFunction=nullptr) |
Returs an GlobalAddress of the function from the current module with name matching the given ExternalSymbol. More... | |
SDNode * | UpdateNodeOperands (SDNode *N, SDValue Op) |
Mutate the specified node in-place to have the specified operands. More... | |
SDNode * | UpdateNodeOperands (SDNode *N, SDValue Op1, SDValue Op2) |
SDNode * | UpdateNodeOperands (SDNode *N, SDValue Op1, SDValue Op2, SDValue Op3) |
SDNode * | UpdateNodeOperands (SDNode *N, SDValue Op1, SDValue Op2, SDValue Op3, SDValue Op4) |
SDNode * | UpdateNodeOperands (SDNode *N, SDValue Op1, SDValue Op2, SDValue Op3, SDValue Op4, SDValue Op5) |
SDNode * | UpdateNodeOperands (SDNode *N, ArrayRef< SDValue > Ops) |
void | setNodeMemRefs (MachineSDNode *N, ArrayRef< MachineMemOperand *> NewMemRefs) |
Mutate the specified machine node's memory references to the provided list. More... | |
void | updateDivergence (SDNode *N) |
SDNode * | SelectNodeTo (SDNode *N, unsigned MachineOpc, EVT VT) |
These are used for target selectors to mutate the specified node to have the specified return type, Target opcode, and operands. More... | |
SDNode * | SelectNodeTo (SDNode *N, unsigned MachineOpc, EVT VT, SDValue Op1) |
SDNode * | SelectNodeTo (SDNode *N, unsigned MachineOpc, EVT VT, SDValue Op1, SDValue Op2) |
SDNode * | SelectNodeTo (SDNode *N, unsigned MachineOpc, EVT VT, SDValue Op1, SDValue Op2, SDValue Op3) |
SDNode * | SelectNodeTo (SDNode *N, unsigned MachineOpc, EVT VT, ArrayRef< SDValue > Ops) |
SDNode * | SelectNodeTo (SDNode *N, unsigned MachineOpc, EVT VT1, EVT VT2) |
SDNode * | SelectNodeTo (SDNode *N, unsigned MachineOpc, EVT VT1, EVT VT2, ArrayRef< SDValue > Ops) |
SDNode * | SelectNodeTo (SDNode *N, unsigned MachineOpc, EVT VT1, EVT VT2, EVT VT3, ArrayRef< SDValue > Ops) |
SDNode * | SelectNodeTo (SDNode *N, unsigned TargetOpc, EVT VT1, EVT VT2, SDValue Op1) |
SDNode * | SelectNodeTo (SDNode *N, unsigned MachineOpc, EVT VT1, EVT VT2, SDValue Op1, SDValue Op2) |
SDNode * | SelectNodeTo (SDNode *N, unsigned MachineOpc, SDVTList VTs, ArrayRef< SDValue > Ops) |
SDNode * | MorphNodeTo (SDNode *N, unsigned Opc, SDVTList VTs, ArrayRef< SDValue > Ops) |
This mutates the specified node to have the specified return type, opcode, and operands. More... | |
SDNode * | mutateStrictFPToFP (SDNode *Node) |
Mutate the specified strict FP node to its non-strict equivalent, unlinking the node from its chain and dropping the metadata arguments. More... | |
MachineSDNode * | getMachineNode (unsigned Opcode, const SDLoc &dl, EVT VT) |
These are used for target selectors to create a new node with specified return type(s), MachineInstr opcode, and operands. More... | |
MachineSDNode * | getMachineNode (unsigned Opcode, const SDLoc &dl, EVT VT, SDValue Op1) |
MachineSDNode * | getMachineNode (unsigned Opcode, const SDLoc &dl, EVT VT, SDValue Op1, SDValue Op2) |
MachineSDNode * | getMachineNode (unsigned Opcode, const SDLoc &dl, EVT VT, SDValue Op1, SDValue Op2, SDValue Op3) |
MachineSDNode * | getMachineNode (unsigned Opcode, const SDLoc &dl, EVT VT, ArrayRef< SDValue > Ops) |
MachineSDNode * | getMachineNode (unsigned Opcode, const SDLoc &dl, EVT VT1, EVT VT2, SDValue Op1, SDValue Op2) |
MachineSDNode * | getMachineNode (unsigned Opcode, const SDLoc &dl, EVT VT1, EVT VT2, SDValue Op1, SDValue Op2, SDValue Op3) |
MachineSDNode * | getMachineNode (unsigned Opcode, const SDLoc &dl, EVT VT1, EVT VT2, ArrayRef< SDValue > Ops) |
MachineSDNode * | getMachineNode (unsigned Opcode, const SDLoc &dl, EVT VT1, EVT VT2, EVT VT3, SDValue Op1, SDValue Op2) |
MachineSDNode * | getMachineNode (unsigned Opcode, const SDLoc &dl, EVT VT1, EVT VT2, EVT VT3, SDValue Op1, SDValue Op2, SDValue Op3) |
MachineSDNode * | getMachineNode (unsigned Opcode, const SDLoc &dl, EVT VT1, EVT VT2, EVT VT3, ArrayRef< SDValue > Ops) |
MachineSDNode * | getMachineNode (unsigned Opcode, const SDLoc &dl, ArrayRef< EVT > ResultTys, ArrayRef< SDValue > Ops) |
MachineSDNode * | getMachineNode (unsigned Opcode, const SDLoc &dl, SDVTList VTs, ArrayRef< SDValue > Ops) |
SDValue | getTargetExtractSubreg (int SRIdx, const SDLoc &DL, EVT VT, SDValue Operand) |
A convenience function for creating TargetInstrInfo::EXTRACT_SUBREG nodes. More... | |
SDValue | getTargetInsertSubreg (int SRIdx, const SDLoc &DL, EVT VT, SDValue Operand, SDValue Subreg) |
A convenience function for creating TargetInstrInfo::INSERT_SUBREG nodes. More... | |
SDNode * | getNodeIfExists (unsigned Opcode, SDVTList VTList, ArrayRef< SDValue > Ops, const SDNodeFlags Flags=SDNodeFlags()) |
Get the specified node if it's already available, or else return NULL. More... | |
SDDbgValue * | getDbgValue (DIVariable *Var, DIExpression *Expr, SDNode *N, unsigned R, bool IsIndirect, const DebugLoc &DL, unsigned O) |
Creates a SDDbgValue node. More... | |
SDDbgValue * | getConstantDbgValue (DIVariable *Var, DIExpression *Expr, const Value *C, const DebugLoc &DL, unsigned O) |
Creates a constant SDDbgValue node. More... | |
SDDbgValue * | getFrameIndexDbgValue (DIVariable *Var, DIExpression *Expr, unsigned FI, bool IsIndirect, const DebugLoc &DL, unsigned O) |
Creates a FrameIndex SDDbgValue node. More... | |
SDDbgValue * | getVRegDbgValue (DIVariable *Var, DIExpression *Expr, unsigned VReg, bool IsIndirect, const DebugLoc &DL, unsigned O) |
Creates a VReg SDDbgValue node. More... | |
SDDbgLabel * | getDbgLabel (DILabel *Label, const DebugLoc &DL, unsigned O) |
Creates a SDDbgLabel node. More... | |
void | transferDbgValues (SDValue From, SDValue To, unsigned OffsetInBits=0, unsigned SizeInBits=0, bool InvalidateDbg=true) |
Transfer debug values from one node to another, while optionally generating fragment expressions for split-up values. More... | |
void | RemoveDeadNode (SDNode *N) |
Remove the specified node from the system. More... | |
void | RemoveDeadNodes (SmallVectorImpl< SDNode *> &DeadNodes) |
This method deletes the unreachable nodes in the given list, and any nodes that become unreachable as a result. More... | |
void | ReplaceAllUsesWith (SDValue From, SDValue To) |
Modify anything using 'From' to use 'To' instead. More... | |
void | ReplaceAllUsesWith (SDNode *From, SDNode *To) |
ReplaceAllUsesWith - Modify anything using 'From' to use 'To' instead. More... | |
void | ReplaceAllUsesWith (SDNode *From, const SDValue *To) |
ReplaceAllUsesWith - Modify anything using 'From' to use 'To' instead. More... | |
void | ReplaceAllUsesOfValueWith (SDValue From, SDValue To) |
Replace any uses of From with To, leaving uses of other values produced by From.getNode() alone. More... | |
void | ReplaceAllUsesOfValuesWith (const SDValue *From, const SDValue *To, unsigned Num) |
Like ReplaceAllUsesOfValueWith, but for multiple values at once. More... | |
SDValue | makeEquivalentMemoryOrdering (LoadSDNode *Old, SDValue New) |
If an existing load has uses of its chain, create a token factor node with that chain and the new memory node's chain and update users of the old chain to the token factor. More... | |
unsigned | AssignTopologicalOrder () |
Topological-sort the AllNodes list and a assign a unique node id for each node in the DAG based on their topological order. More... | |
void | RepositionNode (allnodes_iterator Position, SDNode *N) |
Move node N in the AllNodes list to be immediately before the given iterator Position. More... | |
void | AddDbgValue (SDDbgValue *DB, SDNode *SD, bool isParameter) |
Add a dbg_value SDNode. More... | |
void | AddDbgLabel (SDDbgLabel *DB) |
Add a dbg_label SDNode. More... | |
ArrayRef< SDDbgValue * > | GetDbgValues (const SDNode *SD) const |
Get the debug values which reference the given SDNode. More... | |
bool | hasDebugValues () const |
Return true if there are any SDDbgValue nodes associated with this SelectionDAG. More... | |
SDDbgInfo::DbgIterator | DbgBegin () |
SDDbgInfo::DbgIterator | DbgEnd () |
SDDbgInfo::DbgIterator | ByvalParmDbgBegin () |
SDDbgInfo::DbgIterator | ByvalParmDbgEnd () |
SDDbgInfo::DbgLabelIterator | DbgLabelBegin () |
SDDbgInfo::DbgLabelIterator | DbgLabelEnd () |
void | salvageDebugInfo (SDNode &N) |
To be invoked on an SDNode that is slated to be erased. More... | |
void | dump () const |
SDValue | CreateStackTemporary (EVT VT, unsigned minAlign=1) |
Create a stack temporary, suitable for holding the specified value type. More... | |
SDValue | CreateStackTemporary (EVT VT1, EVT VT2) |
Create a stack temporary suitable for holding either of the specified value types. More... | |
SDValue | FoldSymbolOffset (unsigned Opcode, EVT VT, const GlobalAddressSDNode *GA, const SDNode *N2) |
SDValue | FoldConstantArithmetic (unsigned Opcode, const SDLoc &DL, EVT VT, SDNode *Cst1, SDNode *Cst2) |
SDValue | FoldConstantArithmetic (unsigned Opcode, const SDLoc &DL, EVT VT, const ConstantSDNode *Cst1, const ConstantSDNode *Cst2) |
SDValue | FoldConstantVectorArithmetic (unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDValue > Ops, const SDNodeFlags Flags=SDNodeFlags()) |
SDValue | FoldSetCC (EVT VT, SDValue N1, SDValue N2, ISD::CondCode Cond, const SDLoc &dl) |
Constant fold a setcc to true or false. More... | |
SDValue | GetDemandedBits (SDValue V, const APInt &Mask) |
See if the specified operand can be simplified with the knowledge that only the bits specified by Mask are used. More... | |
bool | SignBitIsZero (SDValue Op, unsigned Depth=0) const |
Return true if the sign bit of Op is known to be zero. More... | |
bool | MaskedValueIsZero (SDValue Op, const APInt &Mask, unsigned Depth=0) const |
Return true if 'Op & Mask' is known to be zero. More... | |
KnownBits | computeKnownBits (SDValue Op, unsigned Depth=0) const |
Determine which bits of Op are known to be either zero or one and return them in Known. More... | |
KnownBits | computeKnownBits (SDValue Op, const APInt &DemandedElts, unsigned Depth=0) const |
Determine which bits of Op are known to be either zero or one and return them in Known. More... | |
OverflowKind | computeOverflowKind (SDValue N0, SDValue N1) const |
Determine if the result of the addition of 2 node can overflow. More... | |
bool | isKnownToBeAPowerOfTwo (SDValue Val) const |
Test if the given value is known to have exactly one bit set. More... | |
unsigned | ComputeNumSignBits (SDValue Op, unsigned Depth=0) const |
Return the number of times the sign bit of the register is replicated into the other bits. More... | |
unsigned | ComputeNumSignBits (SDValue Op, const APInt &DemandedElts, unsigned Depth=0) const |
Return the number of times the sign bit of the register is replicated into the other bits. More... | |
bool | isBaseWithConstantOffset (SDValue Op) const |
Return true if the specified operand is an ISD::ADD with a ConstantSDNode on the right-hand side, or if it is an ISD::OR with a ConstantSDNode that is guaranteed to have the same semantics as an ADD. More... | |
bool | isKnownNeverNaN (SDValue Op, bool SNaN=false, unsigned Depth=0) const |
Test whether the given SDValue is known to never be NaN. More... | |
bool | isKnownNeverSNaN (SDValue Op, unsigned Depth=0) const |
bool | isKnownNeverZeroFloat (SDValue Op) const |
Test whether the given floating point SDValue is known to never be positive or negative zero. More... | |
bool | isKnownNeverZero (SDValue Op) const |
Test whether the given SDValue is known to contain non-zero value(s). More... | |
bool | isEqualTo (SDValue A, SDValue B) const |
Test whether two SDValues are known to compare equal. More... | |
bool | haveNoCommonBitsSet (SDValue A, SDValue B) const |
Return true if A and B have no common bits set. More... | |
bool | isSplatValue (SDValue V, const APInt &DemandedElts, APInt &UndefElts) |
Test whether V has a splatted value for all the demanded elements. More... | |
bool | isSplatValue (SDValue V, bool AllowUndefs=false) |
Test whether V has a splatted value. More... | |
SDValue | matchBinOpReduction (SDNode *Extract, ISD::NodeType &BinOp, ArrayRef< ISD::NodeType > CandidateBinOps) |
Match a binop + shuffle pyramid that represents a horizontal reduction over the elements of a vector starting from the EXTRACT_VECTOR_ELT node /p Extract. More... | |
SDValue | UnrollVectorOp (SDNode *N, unsigned ResNE=0) |
Utility function used by legalize and lowering to "unroll" a vector operation by splitting out the scalars and operating on each element individually. More... | |
bool | areNonVolatileConsecutiveLoads (LoadSDNode *LD, LoadSDNode *Base, unsigned Bytes, int Dist) const |
Return true if loads are next to each other and can be merged. More... | |
unsigned | InferPtrAlignment (SDValue Ptr) const |
Infer alignment of a load / store address. More... | |
std::pair< EVT, EVT > | GetSplitDestVTs (const EVT &VT) const |
Compute the VTs needed for the low/hi parts of a type which is split (or expanded) into two not necessarily identical pieces. More... | |
std::pair< SDValue, SDValue > | SplitVector (const SDValue &N, const SDLoc &DL, const EVT &LoVT, const EVT &HiVT) |
Split the vector with EXTRACT_SUBVECTOR using the provides VTs and return the low/high part. More... | |
std::pair< SDValue, SDValue > | SplitVector (const SDValue &N, const SDLoc &DL) |
Split the vector with EXTRACT_SUBVECTOR and return the low/high part. More... | |
std::pair< SDValue, SDValue > | SplitVectorOperand (const SDNode *N, unsigned OpNo) |
Split the node's operand with EXTRACT_SUBVECTOR and return the low/high part. More... | |
void | ExtractVectorElements (SDValue Op, SmallVectorImpl< SDValue > &Args, unsigned Start=0, unsigned Count=0) |
Append the extracted elements from Start to Count out of the vector Op in Args. More... | |
unsigned | getEVTAlignment (EVT MemoryVT) const |
Compute the default alignment value for the given type. More... | |
SDNode * | isConstantIntBuildVectorOrConstantInt (SDValue N) |
Test whether the given value is a constant int or similar node. More... | |
SDNode * | isConstantFPBuildVectorOrConstantFP (SDValue N) |
Test whether the given value is a constant FP or similar node. More... | |
bool | isConstantValueOfAnyType (SDValue N) |
SDValue | getConstant (uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false) |
Create a ConstantSDNode wrapping a constant value. More... | |
SDValue | getConstant (const APInt &Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false) |
SDValue | getAllOnesConstant (const SDLoc &DL, EVT VT, bool IsTarget=false, bool IsOpaque=false) |
SDValue | getConstant (const ConstantInt &Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false) |
SDValue | getIntPtrConstant (uint64_t Val, const SDLoc &DL, bool isTarget=false) |
SDValue | getTargetConstant (uint64_t Val, const SDLoc &DL, EVT VT, bool isOpaque=false) |
SDValue | getTargetConstant (const APInt &Val, const SDLoc &DL, EVT VT, bool isOpaque=false) |
SDValue | getTargetConstant (const ConstantInt &Val, const SDLoc &DL, EVT VT, bool isOpaque=false) |
SDValue | getBoolConstant (bool V, const SDLoc &DL, EVT VT, EVT OpVT) |
Create a true or false constant of type VT using the target's BooleanContent for type OpVT . More... | |
SDValue | getConstantFP (double Val, const SDLoc &DL, EVT VT, bool isTarget=false) |
Create a ConstantFPSDNode wrapping a constant value. More... | |
SDValue | getConstantFP (const APFloat &Val, const SDLoc &DL, EVT VT, bool isTarget=false) |
SDValue | getConstantFP (const ConstantFP &V, const SDLoc &DL, EVT VT, bool isTarget=false) |
SDValue | getTargetConstantFP (double Val, const SDLoc &DL, EVT VT) |
SDValue | getTargetConstantFP (const APFloat &Val, const SDLoc &DL, EVT VT) |
SDValue | getTargetConstantFP (const ConstantFP &Val, const SDLoc &DL, EVT VT) |
Static Public Member Functions | |
static const fltSemantics & | EVTToAPFloatSemantics (EVT VT) |
Returns an APFloat semantics tag appropriate for the given type. More... | |
Public Attributes | |
bool | NewNodesMustHaveLegalTypes = false |
When true, additional steps are taken to ensure that getConstant() and similar functions return DAG nodes that have legal types. More... | |
std::map< const SDNode *, std::string > | NodeGraphAttrs |
Friends | |
struct | DAGUpdateListener |
DAGUpdateListener is a friend so it can manipulate the listener stack. More... | |
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representation suitable for instruction selection.
This DAG is constructed as the first step of instruction selection in order to allow implementation of machine specific optimizations and code simplifications.
The representation used by the SelectionDAG is a target-independent representation, which has some similarities to the GCC RTL representation, but is significantly more simple, powerful, and is a graph form instead of a linear form.
Definition at line 222 of file SelectionDAG.h.
using llvm::SelectionDAG::allnodes_const_iterator = ilist<SDNode>::const_iterator |
Definition at line 435 of file SelectionDAG.h.
using llvm::SelectionDAG::allnodes_iterator = ilist<SDNode>::iterator |
Definition at line 440 of file SelectionDAG.h.
Used to represent the possible overflow behavior of an operation.
Never: the operation cannot overflow. Always: the operation will always overflow. Sometime: the operation may or may not overflow.
Enumerator | |
---|---|
OFK_Never | |
OFK_Sometime | |
OFK_Always |
Definition at line 1449 of file SelectionDAG.h.
|
explicit |
Definition at line 994 of file SelectionDAG.cpp.
References Other.
|
delete |
SelectionDAG::~SelectionDAG | ( | ) |
Definition at line 1016 of file SelectionDAG.cpp.
References assert(), llvm::ISD::Constant, llvm::ISD::ConstantFP, llvm::SDNode::getDebugLoc(), llvm::SDLoc::getDebugLoc(), llvm::SDNode::getIROrder(), llvm::SDLoc::getIROrder(), llvm::SDNode::getOpcode(), llvm_unreachable, N, and llvm::SDNode::setDebugLoc().
void SelectionDAG::AddDbgLabel | ( | SDDbgLabel * | DB | ) |
Add a dbg_label SDNode.
Definition at line 8502 of file SelectionDAG.cpp.
Referenced by getUnderlyingArgReg().
void SelectionDAG::AddDbgValue | ( | SDDbgValue * | DB, |
SDNode * | SD, | ||
bool | isParameter | ||
) |
Add a dbg_value SDNode.
AddDbgValue - Add a dbg_value SDNode.
If SD is non-null that means the value is produced by SD.
Definition at line 8494 of file SelectionDAG.cpp.
References assert(), llvm::SDNode::getHasDebugValue(), and llvm::SDNode::setHasDebugValue().
Referenced by getUnderlyingArgReg(), llvm::SelectionDAGBuilder::resolveDanglingDebugInfo(), salvageDebugInfo(), and transferDbgValues().
|
inline |
Definition at line 449 of file SelectionDAG.h.
References llvm::make_range().
Referenced by llvm::HexagonDAGToDAGISel::PreprocessISelDAG(), updateDivergence(), and VerifyDAGDiverence().
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inline |
Definition at line 452 of file SelectionDAG.h.
References llvm::make_range().
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inline |
Definition at line 437 of file SelectionDAG.h.
Referenced by AssignTopologicalOrder(), llvm::SelectionDAGISel::getUninvalidatedNodeId(), isTargetConstant(), and llvm::GraphTraits< SelectionDAG * >::nodes_begin().
|
inline |
Definition at line 442 of file SelectionDAG.h.
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inline |
Definition at line 438 of file SelectionDAG.h.
Referenced by AssignTopologicalOrder(), isTargetConstant(), and llvm::GraphTraits< SelectionDAG * >::nodes_end().
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inline |
Definition at line 443 of file SelectionDAG.h.
Definition at line 445 of file SelectionDAG.h.
Referenced by llvm::HexagonDAGToDAGISel::PreprocessISelDAG().
bool SelectionDAG::areNonVolatileConsecutiveLoads | ( | LoadSDNode * | LD, |
LoadSDNode * | Base, | ||
unsigned | Bytes, | ||
int | Dist | ||
) | const |
Return true if loads are next to each other and can be merged.
Check that both are nonvolatile and if LD is loading 'Bytes' bytes from a location that is 'Dist' units away from the location that the 'Base' load is loading from.
Definition at line 8976 of file SelectionDAG.cpp.
References llvm::MemSDNode::getChain(), llvm::EVT::getSizeInBits(), llvm::SDNode::getValueType(), llvm::LSBaseSDNode::isIndexed(), llvm::MemSDNode::isVolatile(), and llvm::BaseIndexOffset::match().
Referenced by EltsFromConsecutiveLoads(), and getBuildPairElt().
unsigned SelectionDAG::AssignTopologicalOrder | ( | ) |
Topological-sort the AllNodes list and a assign a unique node id for each node in the DAG based on their topological order.
AssignTopologicalOrder - Assign a unique node id for each node in the DAG based on their topological order.
Returns the number of nodes.
It returns the maximum id and a vector of the SDNodes* in assigned order by reference.
Definition at line 8405 of file SelectionDAG.cpp.
References allnodes_begin(), allnodes_end(), assert(), llvm::checkForCycles(), E, llvm::SDNode::getNumOperands(), I, and llvm::SDNode::setNodeId().
Referenced by llvm::SelectionDAGISel::getUninvalidatedNodeId().
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inline |
Definition at line 1364 of file SelectionDAG.h.
References llvm::SDDbgInfo::ByvalParmDbgBegin().
Referenced by llvm::ScheduleDAGSDNodes::EmitSchedule().
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inline |
Definition at line 1368 of file SelectionDAG.h.
References llvm::SDDbgInfo::ByvalParmDbgEnd().
Referenced by llvm::ScheduleDAGSDNodes::EmitSchedule().
void SelectionDAG::clear | ( | ) |
Clear state and free memory necessary to make this SelectionDAG ready to process a new block.
Definition at line 1073 of file SelectionDAG.cpp.
References llvm::SDDbgInfo::clear(), getEntryNode(), and llvm::BumpPtrAllocatorImpl< AllocatorT, SlabSize, SizeThreshold >::Reset().
void SelectionDAG::clearGraphAttrs | ( | ) |
Clear all previously defined node graph attributes.
clearGraphAttrs - Clear all previously defined node graph attributes.
Intended to be used from a debugging tool (eg. gdb).
Definition at line 170 of file SelectionDAGPrinter.cpp.
References llvm::errs().
void SelectionDAG::Combine | ( | CombineLevel | Level, |
AliasAnalysis * | AA, | ||
CodeGenOpt::Level | OptLevel | ||
) |
This iterates over the nodes in the SelectionDAG, folding certain types of nodes together, or eliminating superfluous nodes.
This is the entry point for the file.
The Level argument controls whether Combine is allowed to produce nodes and types that are illegal on the target.
This is the main entry point to this class.
Definition at line 19397 of file DAGCombiner.cpp.
Determine which bits of Op are known to be either zero or one and return them in Known.
For vectors, the known bits are those that are shared by every vector element. Targets can implement the computeKnownBitsForTargetNode method in the TargetLowering class to allow target nodes to be understood.
For vectors, the known bits are those that are shared by every vector element.
Definition at line 2286 of file SelectionDAG.cpp.
References llvm::APInt::getAllOnesValue(), llvm::SDValue::getValueType(), llvm::EVT::getVectorNumElements(), and llvm::EVT::isVector().
Referenced by adjustForRedundantAnd(), calculateByteProvider(), llvm::SelectionDAGISel::CheckOrMask(), combineSubToSubus(), combineVectorSignBitsTruncation(), computeKnownBits(), computeKnownBitsBinOp(), llvm::SparcTargetLowering::computeKnownBitsForTargetNode(), llvm::LanaiTargetLowering::computeKnownBitsForTargetNode(), llvm::AMDGPUTargetLowering::computeKnownBitsForTargetNode(), llvm::AArch64TargetLowering::computeKnownBitsForTargetNode(), llvm::ARMTargetLowering::computeKnownBitsForTargetNode(), llvm::SystemZTargetLowering::computeKnownBitsForTargetNode(), llvm::X86TargetLowering::computeKnownBitsForTargetNode(), ComputeNumSignBits(), computeOverflowKind(), llvm::XCoreTargetLowering::EmitInstrWithCustomInserter(), foldMaskAndShiftToScale(), generateEquivalentSub(), haveNoCommonBitsSet(), isBitfieldPositioningOp(), isKnownToBeAPowerOfTwo(), isTruncateOf(), isWordAligned(), LowerAndToBT(), LowerMUL(), LowerTruncateVecI1(), MaskedValueIsZero(), matchRotateSub(), llvm::AMDGPUTargetLowering::numBitsUnsigned(), llvm::ARMTargetLowering::PerformCMOVCombine(), llvm::ARMTargetLowering::PerformCMOVToBFICombine(), llvm::AMDGPUTargetLowering::performShlCombine(), llvm::AMDGPUTargetLowering::performTruncateCombine(), llvm::PPCTargetLowering::SelectAddressRegImm(), llvm::PPCTargetLowering::SelectAddressRegReg(), llvm::TargetLowering::SimplifyDemandedBits(), tryBitfieldInsertOpFromOr(), and tryBitfieldInsertOpFromOrAndImm().
KnownBits SelectionDAG::computeKnownBits | ( | SDValue | Op, |
const APInt & | DemandedElts, | ||
unsigned | Depth = 0 |
||
) | const |
Determine which bits of Op are known to be either zero or one and return them in Known.
The DemandedElts argument allows us to only collect the known bits that are shared by the requested vector elements. Targets can implement the computeKnownBitsForTargetNode method in the TargetLowering class to allow target nodes to be understood.
The DemandedElts argument allows us to only collect the known bits that are shared by the requested vector elements.
Definition at line 2297 of file SelectionDAG.cpp.
References llvm::ISD::ABS, llvm::ISD::ADD, llvm::ISD::ADDC, llvm::ISD::ADDCARRY, llvm::ISD::ADDE, llvm::ISD::AND, llvm::ISD::ANY_EXTEND, llvm::APInt::ashrInPlace(), assert(), llvm::ISD::AssertZext, llvm::ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, llvm::ISD::BITCAST, llvm::ISD::BITREVERSE, llvm::ISD::BSWAP, llvm::ISD::BUILD_VECTOR, llvm::ISD::BUILTIN_OP_END, llvm::APInt::byteSwap(), C, llvm::APInt::clearAllBits(), llvm::APInt::clearSignBit(), computeKnownBits(), llvm::TargetLowering::computeKnownBitsForFrameIndex(), llvm::TargetLowering::computeKnownBitsForTargetNode(), llvm::computeKnownBitsFromRangeMetadata(), llvm::ISD::CONCAT_VECTORS, llvm::countLeadingZeros(), llvm::KnownBits::countMaxLeadingZeros(), llvm::KnownBits::countMaxPopulation(), llvm::KnownBits::countMaxTrailingZeros(), llvm::KnownBits::countMinLeadingOnes(), llvm::KnownBits::countMinLeadingZeros(), llvm::KnownBits::countMinTrailingZeros(), llvm::ISD::CTLZ, llvm::ISD::CTLZ_ZERO_UNDEF, llvm::ISD::CTPOP, llvm::ISD::CTTZ, llvm::ISD::CTTZ_ZERO_UNDEF, llvm::dyn_cast(), llvm::ISD::EXTRACT_ELEMENT, llvm::ISD::EXTRACT_SUBVECTOR, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::APInt::extractBits(), llvm::ISD::FGETSIGN, llvm::ISD::FrameIndex, llvm::ISD::FSHL, llvm::ISD::FSHR, llvm::APInt::getAllOnesValue(), llvm::ConstantSDNode::getAPIntValue(), llvm::APInt::getBitsSet(), llvm::APInt::getBitWidth(), llvm::TargetLoweringBase::getBooleanContents(), llvm::APInt::getBoolValue(), llvm::SDValue::getConstantOperandVal(), getDataLayout(), llvm::LoadSDNode::getExtensionType(), llvm::APInt::getHiBits(), llvm::APInt::getHighBitsSet(), llvm::APInt::getLowBitsSet(), llvm::ShuffleVectorSDNode::getMask(), llvm::ShuffleVectorSDNode::getMaskElt(), llvm::MemSDNode::getMemoryVT(), llvm::SDValue::getNode(), llvm::SDValue::getNumOperands(), llvm::APInt::getNumSignBits(), llvm::APInt::getOneBitSet(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::MemSDNode::getRanges(), llvm::SDValue::getResNo(), llvm::EVT::getScalarSizeInBits(), llvm::SDValue::getScalarValueSizeInBits(), llvm::APInt::getSignMask(), llvm::EVT::getSizeInBits(), getValidShiftAmountConstant(), llvm::SDValue::getValueSizeInBits(), llvm::SDValue::getValueType(), llvm::EVT::getVectorNumElements(), llvm::ConstantSDNode::getZExtValue(), llvm::APInt::getZExtValue(), llvm::KnownBits::hasConflict(), if(), llvm::ISD::INSERT_SUBVECTOR, llvm::ISD::INSERT_VECTOR_ELT, llvm::APInt::intersects(), llvm::ISD::INTRINSIC_VOID, llvm::ISD::INTRINSIC_W_CHAIN, llvm::ISD::INTRINSIC_WO_CHAIN, llvm::isConstOrConstSplat(), isConstOrDemandedConstSplat(), llvm::EVT::isFloatingPoint(), llvm::EVT::isInteger(), llvm::DataLayout::isLittleEndian(), llvm::APInt::isNegative(), llvm::APInt::isNonNegative(), llvm::APInt::isPowerOf2(), llvm::KnownBits::isUnknown(), llvm::EVT::isVector(), llvm::ISD::isZEXTLoad(), llvm::ARM_MB::LD, LLVM_FALLTHROUGH, llvm::ISD::LOAD, llvm::Log2_32(), llvm::APInt::lshr(), llvm::APInt::lshrInPlace(), llvm::max(), llvm::ISD::MUL, llvm::ISD::NON_EXTLOAD, llvm::KnownBits::One, llvm::ISD::OR, RA, llvm::KnownBits::resetAll(), llvm::APInt::reverseBits(), llvm::ISD::SADDO, llvm::ISD::SCALAR_TO_VECTOR, llvm::ISD::SELECT, llvm::ISD::SELECT_CC, llvm::APInt::setAllBits(), llvm::APInt::setBit(), llvm::APInt::setBits(), llvm::APInt::setBitsFrom(), llvm::ISD::SETCC, llvm::APInt::setHighBits(), llvm::APInt::setLowBits(), llvm::KnownBits::sext(), llvm::ISD::SHL, llvm::APInt::shl(), llvm::ISD::SIGN_EXTEND, llvm::ISD::SIGN_EXTEND_INREG, llvm::ISD::SIGN_EXTEND_VECTOR_INREG, llvm::APInt::sle(), llvm::ISD::SMAX, llvm::ISD::SMIN, llvm::ISD::SMULO, llvm::ISD::SRA, llvm::ISD::SREM, llvm::ISD::SRL, llvm::ISD::SSUBO, llvm::ISD::SUB, llvm::ISD::SUBC, std::swap(), llvm::ISD::TargetFrameIndex, llvm::KnownBits::trunc(), llvm::APInt::trunc(), llvm::ISD::TRUNCATE, llvm::ISD::UADDO, llvm::ISD::UDIV, llvm::APInt::ule(), llvm::APInt::ult(), llvm::ISD::UMAX, llvm::ISD::UMIN, llvm::ISD::UMULO, llvm::ISD::UREM, llvm::ISD::USUBO, llvm::ISD::VECTOR_SHUFFLE, llvm::ISD::VSELECT, llvm::ISD::XOR, llvm::KnownBits::Zero, llvm::ISD::ZERO_EXTEND, llvm::ISD::ZERO_EXTEND_VECTOR_INREG, llvm::TargetLoweringBase::ZeroOrOneBooleanContent, llvm::KnownBits::zext(), llvm::APInt::zext(), llvm::APInt::zextOrSelf(), and llvm::APInt::zextOrTrunc().
Return the number of times the sign bit of the register is replicated into the other bits.
We know that at least 1 bit is always equal to the sign bit (itself), but other cases can give us information. For example, immediately after an "SRA X, 2", we know that the top 3 bits are all equal to each other, so we return 3. Targets can implement the ComputeNumSignBitsForTarget method in the TargetLowering class to allow target nodes to be understood.
Definition at line 3275 of file SelectionDAG.cpp.
References llvm::APInt::getAllOnesValue(), llvm::SDValue::getValueType(), llvm::EVT::getVectorNumElements(), and llvm::EVT::isVector().
Referenced by calculateByteProvider(), canReduceVMulWidth(), combineAndMaskToShift(), combineHorizontalPredicateResult(), combineLogicBlendIntoPBLENDV(), combineMulToPMULDQ(), combineSIntToFP(), combineVectorPack(), combineVectorSignBitsTruncation(), combineVSelectWithAllOnesOrZeros(), ComputeNumSignBits(), computeNumSignBitsBinOp(), llvm::AMDGPUTargetLowering::ComputeNumSignBitsForTargetNode(), llvm::SystemZTargetLowering::ComputeNumSignBitsForTargetNode(), llvm::X86TargetLowering::ComputeNumSignBitsForTargetNode(), llvm::TargetLowering::expandMUL_LOHI(), foldExtendedSignBitTest(), generateEquivalentSub(), getAsCarry(), getFauxShuffleMask(), getShiftAmountTyForConstant(), isADDADDMUL(), isS16(), isTruncateOf(), llvm::AMDGPUTargetLowering::LowerDIVREM24(), llvm::AMDGPUTargetLowering::LowerSDIVREM(), LowerTruncateVecI1(), lowerVSELECTtoVectorShuffle(), matchVectorShuffleWithPACK(), llvm::AMDGPUTargetLowering::numBitsSigned(), llvm::AMDGPUTargetLowering::PerformDAGCombine(), and llvm::X86TargetLowering::SimplifyDemandedBitsForTargetNode().
unsigned SelectionDAG::ComputeNumSignBits | ( | SDValue | Op, |
const APInt & | DemandedElts, | ||
unsigned | Depth = 0 |
||
) | const |
Return the number of times the sign bit of the register is replicated into the other bits.
We know that at least 1 bit is always equal to the sign bit (itself), but other cases can give us information. For example, immediately after an "SRA X, 2", we know that the top 3 bits are all equal to each other, so we return 3. The DemandedElts argument allows us to only collect the minimum sign bits of the requested vector elements. Targets can implement the ComputeNumSignBitsForTarget method in the TargetLowering class to allow target nodes to be understood.
Definition at line 3283 of file SelectionDAG.cpp.
References llvm::ISD::ADD, llvm::ISD::ADDC, llvm::ISD::AND, assert(), llvm::ISD::AssertSext, llvm::ISD::AssertZext, llvm::ISD::BITCAST, llvm::ISD::BUILD_VECTOR, llvm::ISD::BUILTIN_OP_END, C, llvm::APInt::clearBit(), computeKnownBits(), ComputeNumSignBits(), llvm::TargetLowering::ComputeNumSignBitsForTargetNode(), llvm::ISD::CONCAT_VECTORS, llvm::APInt::countLeadingZeros(), llvm::dyn_cast(), llvm::ISD::EXTRACT_ELEMENT, llvm::ISD::EXTRACT_SUBVECTOR, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::APInt::extractBits(), llvm::APInt::getAllOnesValue(), llvm::ConstantSDNode::getAPIntValue(), llvm::APInt::getBitsSet(), llvm::APInt::getBitWidth(), llvm::TargetLoweringBase::getBooleanContents(), llvm::SDValue::getConstantOperandVal(), getDataLayout(), llvm::ShuffleVectorSDNode::getMask(), llvm::ShuffleVectorSDNode::getMaskElt(), llvm::SDValue::getNumOperands(), llvm::APInt::getNumSignBits(), llvm::APInt::getOneBitSet(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getResNo(), llvm::EVT::getScalarSizeInBits(), llvm::SDValue::getScalarValueSizeInBits(), llvm::SDValue::getValueSizeInBits(), llvm::SDValue::getValueType(), llvm::EVT::getVectorNumElements(), llvm::ConstantSDNode::getZExtValue(), llvm::APInt::getZExtValue(), llvm::ISD::INSERT_SUBVECTOR, llvm::ISD::INSERT_VECTOR_ELT, llvm::ISD::INTRINSIC_VOID, llvm::ISD::INTRINSIC_W_CHAIN, llvm::ISD::INTRINSIC_WO_CHAIN, llvm::isConstOrConstSplat(), isConstOrDemandedConstSplat(), llvm::EVT::isFloatingPoint(), llvm::EVT::isInteger(), llvm::DataLayout::isLittleEndian(), llvm::KnownBits::isNegative(), llvm::KnownBits::isNonNegative(), llvm::EVT::isVector(), llvm::ARM_MB::LD, llvm::APInt::lshr(), llvm::BitmaskEnumDetail::Mask(), llvm::max(), llvm::KnownBits::One, llvm::ISD::OR, llvm::ISD::ROTL, llvm::ISD::ROTR, llvm::ISD::SADDO, llvm::ISD::SELECT, llvm::ISD::SELECT_CC, llvm::APInt::setBit(), llvm::ISD::SETCC, llvm::ISD::SEXTLOAD, llvm::ISD::SHL, llvm::APInt::shl(), llvm::ISD::SIGN_EXTEND, llvm::ISD::SIGN_EXTEND_INREG, llvm::ISD::SIGN_EXTEND_VECTOR_INREG, llvm::APInt::sle(), llvm::ISD::SMAX, llvm::ISD::SMIN, llvm::ISD::SMULO, llvm::ISD::SRA, llvm::ISD::SSUBO, llvm::ISD::SUB, std::swap(), llvm::APInt::trunc(), llvm::ISD::TRUNCATE, llvm::ISD::UADDO, llvm::APInt::uge(), llvm::APInt::ule(), llvm::APInt::ult(), llvm::ISD::UMAX, llvm::ISD::UMIN, llvm::ISD::UMULO, llvm::ISD::USUBO, llvm::ISD::VECTOR_SHUFFLE, llvm::ISD::VSELECT, llvm::ISD::XOR, llvm::KnownBits::Zero, llvm::TargetLoweringBase::ZeroOrNegativeOneBooleanContent, llvm::ISD::ZEXTLOAD, and llvm::APInt::zextOrSelf().
SelectionDAG::OverflowKind SelectionDAG::computeOverflowKind | ( | SDValue | N0, |
SDValue | N1 | ||
) | const |
Determine if the result of the addition of 2 node can overflow.
Definition at line 3203 of file SelectionDAG.cpp.
References computeKnownBits(), llvm::APInt::getBoolValue(), llvm::SDValue::getOpcode(), llvm::SDValue::getResNo(), llvm::isNullConstant(), OFK_Never, OFK_Sometime, llvm::ISD::UMUL_LOHI, and llvm::KnownBits::Zero.
Referenced by foldAddSubOfSignBit(), getAsCarry(), and isBooleanFlip().
Create a stack temporary, suitable for holding the specified value type.
If minAlign is specified, the slot size will have at least that alignment.
Definition at line 1922 of file SelectionDAG.cpp.
References llvm::MachineFrameInfo::CreateStackObject(), getContext(), getDataLayout(), getFrameIndex(), llvm::TargetLoweringBase::getFrameIndexTy(), llvm::MachineFunction::getFrameInfo(), getMachineFunction(), llvm::EVT::getStoreSize(), llvm::EVT::getTypeForEVT(), and llvm::max().
Referenced by llvm::StatepointLoweringState::allocateStackSlot(), llvm::TargetLowering::expandUnalignedLoad(), llvm::TargetLowering::expandUnalignedStore(), getExpandedMinMaxOps(), getMOVL(), llvm::SystemZTargetLowering::LowerCall(), LowerMULH(), lowerUINT_TO_FP_vec(), PrepareCall(), and unpackF64OnRV32DSoftABI().
Create a stack temporary suitable for holding either of the specified value types.
Definition at line 1933 of file SelectionDAG.cpp.
References llvm::AMDGPU::HSAMD::Kernel::Arg::Key::Align, llvm::MachineFrameInfo::CreateStackObject(), getContext(), getDataLayout(), getFrameIndex(), llvm::TargetLoweringBase::getFrameIndexTy(), llvm::MachineFunction::getFrameInfo(), getMachineFunction(), llvm::DataLayout::getPrefTypeAlignment(), llvm::EVT::getStoreSize(), llvm::EVT::getTypeForEVT(), and llvm::max().
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Definition at line 1361 of file SelectionDAG.h.
References llvm::SDDbgInfo::DbgBegin().
Referenced by llvm::ScheduleDAGSDNodes::EmitSchedule().
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inline |
Definition at line 1362 of file SelectionDAG.h.
References llvm::SDDbgInfo::DbgEnd().
Referenced by llvm::ScheduleDAGSDNodes::EmitSchedule().
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inline |
Definition at line 1372 of file SelectionDAG.h.
References llvm::SDDbgInfo::DbgLabelBegin().
Referenced by llvm::ScheduleDAGSDNodes::EmitSchedule().
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inline |
Definition at line 1375 of file SelectionDAG.h.
References llvm::computeKnownBits(), llvm::SDDbgInfo::DbgLabelEnd(), llvm::Depth, llvm::dump(), llvm::MaskedValueIsZero(), and llvm::salvageDebugInfo().
Referenced by llvm::ScheduleDAGSDNodes::EmitSchedule().
void SelectionDAG::DeleteNode | ( | SDNode * | N | ) |
Remove the specified node from the system.
This node must have no referrers.
Definition at line 740 of file SelectionDAG.cpp.
References assert(), llvm::SDNode::DropOperands(), llvm::ilist_node_impl< OptionsT >::getIterator(), N, and llvm::SDNode::use_empty().
Referenced by addStackMapLiveVars(), llvm::TargetLowering::DAGCombinerInfo::CommitTargetLoweringOpt(), and isAnyConstantBuildVector().
LLVM_DUMP_METHOD void SelectionDAG::dump | ( | ) | const |
Definition at line 744 of file SelectionDAGDumper.cpp.
Referenced by llvm::HexagonDAGToDAGISel::PreprocessISelDAG().
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inlinestatic |
Returns an APFloat semantics tag appropriate for the given type.
If VT is a vector type, the element semantics are returned.
Definition at line 1332 of file SelectionDAG.h.
References llvm::MVT::f128, llvm::MVT::f16, llvm::MVT::f32, llvm::MVT::f64, llvm::MVT::f80, llvm::EVT::getScalarType(), llvm::EVT::getSimpleVT(), llvm::APFloatBase::IEEEdouble(), llvm::APFloatBase::IEEEhalf(), llvm::APFloatBase::IEEEquad(), llvm::APFloatBase::IEEEsingle(), llvm_unreachable, llvm::APFloatBase::PPCDoubleDouble(), llvm::MVT::ppcf128, llvm::MVT::SimpleTy, and llvm::APFloatBase::x87DoubleExtended().
Referenced by FoldIntToFPToInt(), getConstantFP(), getExpandedMinMaxOps(), GetFPLibCall(), getMemsetValue(), getNode(), llvm::ConstantFPSDNode::isValueValidForType(), LowerFABSorFNEG(), LowerFCOPYSIGN(), replaceShuffleOfInsert(), and vectorEltWillFoldAway().
Expand the specified ISD::VAARG
node as the Legalize pass would.
Definition at line 1873 of file SelectionDAG.cpp.
Expand the specified ISD::VACOPY
node as the Legalize pass would.
Definition at line 1908 of file SelectionDAG.cpp.
Referenced by LowerVACOPY().
void SelectionDAG::ExtractVectorElements | ( | SDValue | Op, |
SmallVectorImpl< SDValue > & | Args, | ||
unsigned | Start = 0 , |
||
unsigned | Count = 0 |
||
) |
Append the extracted elements from Start to Count out of the vector Op in Args.
If Count is 0, all of the elements will be extracted.
Definition at line 9068 of file SelectionDAG.cpp.
Referenced by adjustLoadValueTypeImpl(), constructRetValue(), llvm::AMDGPUTargetLowering::LowerCONCAT_VECTORS(), llvm::AMDGPUTargetLowering::LowerSIGN_EXTEND_INREG(), parseTexFail(), and widenVectorToPartType().
SDValue SelectionDAG::FoldConstantArithmetic | ( | unsigned | Opcode, |
const SDLoc & | DL, | ||
EVT | VT, | ||
SDNode * | Cst1, | ||
SDNode * | Cst2 | ||
) |
Definition at line 4573 of file SelectionDAG.cpp.
References assert(), llvm::SmallVectorTemplateCommon< T >::back(), llvm::EVT::bitsGT(), llvm::EVT::bitsLT(), llvm::ISD::BUILTIN_OP_END, llvm::ISD::Constant, llvm::ISD::ConstantFP, llvm::dyn_cast(), FoldSymbolOffset(), getBuildVector(), getContext(), getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOperand(), llvm::EVT::getScalarType(), llvm::TargetLoweringBase::getTypeToTransformTo(), getUNDEF(), llvm::SDNode::getValueType(), llvm::EVT::getVectorNumElements(), I, llvm::TargetLoweringBase::isCommutativeBinOp(), llvm::EVT::isInteger(), llvm::SDValue::isUndef(), llvm::SDNode::isUndef(), isUndef(), llvm::EVT::isVector(), NewNodesMustHaveLegalTypes, llvm::SmallVectorTemplateBase< T >::push_back(), llvm::SmallVectorImpl< T >::resize(), llvm::ISD::SIGN_EXTEND, llvm::SmallVectorBase::size(), llvm::ISD::TRUNCATE, and llvm::NVPTX::PTXLdStInstCode::V2.
Referenced by calculateByteProvider(), foldAddSubOfSignBit(), getNode(), isAnyConstantBuildVector(), isBSwapHWordElement(), simplifyDivRem(), and tryFoldToZero().
SDValue SelectionDAG::FoldConstantArithmetic | ( | unsigned | Opcode, |
const SDLoc & | DL, | ||
EVT | VT, | ||
const ConstantSDNode * | Cst1, | ||
const ConstantSDNode * | Cst2 | ||
) |
Definition at line 4515 of file SelectionDAG.cpp.
References FoldValue(), llvm::ConstantSDNode::getAPIntValue(), getConstant(), and llvm::ConstantSDNode::isOpaque().
SDValue SelectionDAG::FoldConstantVectorArithmetic | ( | unsigned | Opcode, |
const SDLoc & | DL, | ||
EVT | VT, | ||
ArrayRef< SDValue > | Ops, | ||
const SDNodeFlags | Flags = SDNodeFlags() |
||
) |
Definition at line 4662 of file SelectionDAG.cpp.
References llvm::all_of(), llvm::EVT::bitsGT(), llvm::EVT::bitsLT(), llvm::ISD::BUILTIN_OP_END, llvm::ISD::CONDCODE, llvm::ISD::Constant, llvm::ISD::ConstantFP, llvm::dyn_cast(), getBuildVector(), getContext(), getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOperand(), llvm::EVT::getScalarType(), llvm::TargetLoweringBase::getTypeToTransformTo(), getUNDEF(), llvm::SDValue::getValueType(), llvm::EVT::getVectorNumElements(), llvm::MVT::i1, llvm::BuildVectorSDNode::isConstant(), llvm::EVT::isInteger(), llvm::SDValue::isUndef(), isUndef(), llvm::EVT::isVector(), NewNodesMustHaveLegalTypes, NewSDValueDbgMsg(), llvm::SmallVectorTemplateBase< T >::push_back(), llvm::ISD::SETCC, llvm::ISD::SIGN_EXTEND, and llvm::ISD::TRUNCATE.
Referenced by getNode(), and replaceShuffleOfInsert().
SDValue SelectionDAG::FoldSetCC | ( | EVT | VT, |
SDValue | N1, | ||
SDValue | N2, | ||
ISD::CondCode | Cond, | ||
const SDLoc & | dl | ||
) |
Constant fold a setcc to true or false.
Definition at line 1946 of file SelectionDAG.cpp.
References assert(), llvm::APFloatBase::cmpEqual, llvm::APFloatBase::cmpGreaterThan, llvm::APFloatBase::cmpLessThan, llvm::APFloatBase::cmpUnordered, getBoolConstant(), getSetCC(), llvm::ISD::getSetCCSwappedOperands(), llvm::EVT::getSimpleVT(), getUNDEF(), llvm::SDValue::getValueType(), llvm::TargetLoweringBase::isCondCodeLegal(), llvm::EVT::isInteger(), LLVM_FALLTHROUGH, llvm_unreachable, llvm::ISD::SETEQ, llvm::ISD::SETFALSE, llvm::ISD::SETFALSE2, llvm::ISD::SETGE, llvm::ISD::SETGT, llvm::ISD::SETLE, llvm::ISD::SETLT, llvm::ISD::SETNE, llvm::ISD::SETO, llvm::ISD::SETOEQ, llvm::ISD::SETOGE, llvm::ISD::SETOGT, llvm::ISD::SETOLE, llvm::ISD::SETOLT, llvm::ISD::SETONE, llvm::ISD::SETTRUE, llvm::ISD::SETTRUE2, llvm::ISD::SETUEQ, llvm::ISD::SETUGE, llvm::ISD::SETUGT, llvm::ISD::SETULE, llvm::ISD::SETULT, llvm::ISD::SETUNE, llvm::ISD::SETUO, llvm::APInt::sge(), llvm::APInt::sgt(), llvm::APInt::sle(), llvm::APInt::slt(), llvm::APInt::uge(), llvm::APInt::ugt(), llvm::APInt::ule(), and llvm::APInt::ult().
Referenced by getNode(), and llvm::TargetLowering::SimplifySetCC().
SDValue SelectionDAG::FoldSymbolOffset | ( | unsigned | Opcode, |
EVT | VT, | ||
const GlobalAddressSDNode * | GA, | ||
const SDNode * | N2 | ||
) |
Definition at line 4528 of file SelectionDAG.cpp.
References llvm::ISD::ADD, llvm::dyn_cast(), llvm::GlobalAddressSDNode::getGlobal(), getGlobalAddress(), llvm::GlobalAddressSDNode::getOffset(), llvm::SDNode::getOpcode(), llvm::ConstantSDNode::getSExtValue(), llvm::ISD::GlobalAddress, llvm::TargetLowering::isOffsetFoldingLegal(), and llvm::ISD::SUB.
Referenced by FoldConstantArithmetic().
SDValue SelectionDAG::getAddrSpaceCast | ( | const SDLoc & | dl, |
EVT | VT, | ||
SDValue | Ptr, | ||
unsigned | SrcAS, | ||
unsigned | DestAS | ||
) |
Return an AddrSpaceCastSDNode.
Definition at line 1842 of file SelectionDAG.cpp.
References llvm::FoldingSetNodeID::AddInteger(), AddNodeIDNode(), llvm::ISD::ADDRSPACECAST, E, llvm::SDLoc::getDebugLoc(), llvm::SDLoc::getIROrder(), and getVTList().
Referenced by hasOnlySelectUsers().
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inline |
Definition at line 566 of file SelectionDAG.h.
References llvm::APInt::getAllOnesValue(), getConstant(), and llvm::EVT::getScalarSizeInBits().
Referenced by calculateByteProvider(), combineHorizontalPredicateResult(), foldAddSubOfSignBit(), foldExtendedSignBitTest(), getBoolConstant(), getNode(), isBSwapHWordElement(), isLowerSaturatingConditional(), lowerVectorShuffleAsBitBlend(), lowerVectorShuffleAsBitMask(), matchRotateSub(), and simplifyDivRem().
Convert Op, which must be of integer type, to the integer type VT, by either any-extending or truncating it.
Definition at line 1100 of file SelectionDAG.cpp.
References llvm::ISD::ANY_EXTEND, llvm::EVT::bitsGT(), getNode(), llvm::SDValue::getValueType(), and llvm::ISD::TRUNCATE.
Referenced by combineBitcast(), combineToExtendBoolVectorInReg(), createGPRPairNode(), createMMXBuildVector(), findUser(), generateEquivalentSub(), getCopyFromPartsVector(), getCopyToPartsVector(), getExpandedMinMaxOps(), getNode(), getShiftAmountTyForConstant(), isTruncateOf(), llvm::HexagonTargetLowering::LowerBITCAST(), LowerBuildVectorAsInsert(), LowerBuildVectorv16i8(), LowerMUL(), scalarizeExtractedBinop(), and ShrinkLoadReplaceStoreWithStore().
SDValue SelectionDAG::getAtomic | ( | unsigned | Opcode, |
const SDLoc & | dl, | ||
EVT | MemVT, | ||
SDValue | Chain, | ||
SDValue | Ptr, | ||
SDValue | Val, | ||
const Value * | PtrVal, | ||
unsigned | Alignment, | ||
AtomicOrdering | Ordering, | ||
SyncScope::ID | SSID | ||
) |
Gets a node for an atomic op, produces result (if relevant) and chain and takes 2 operands.
Definition at line 6425 of file SelectionDAG.cpp.
References llvm::ISD::ATOMIC_LOAD, llvm::ISD::ATOMIC_STORE, getEVTAlignment(), getMachineFunction(), llvm::MachineFunction::getMachineMemOperand(), llvm::EVT::getStoreSize(), llvm::MachineMemOperand::MOLoad, llvm::MachineMemOperand::MOStore, and llvm::MachineMemOperand::MOVolatile.
Referenced by combineSetCCAtomicArith(), getAtomic(), getAtomicCmpSwap(), getExpandedMinMaxOps(), getReductionSDNode(), getShiftAmountTyForConstant(), getUniformBase(), and lowerAtomicArith().
SDValue SelectionDAG::getAtomic | ( | unsigned | Opcode, |
const SDLoc & | dl, | ||
EVT | MemVT, | ||
SDValue | Chain, | ||
SDValue | Ptr, | ||
SDValue | Val, | ||
MachineMemOperand * | MMO | ||
) |
Definition at line 6454 of file SelectionDAG.cpp.
References assert(), llvm::ISD::ATOMIC_LOAD_ADD, llvm::ISD::ATOMIC_LOAD_AND, llvm::ISD::ATOMIC_LOAD_CLR, llvm::ISD::ATOMIC_LOAD_MAX, llvm::ISD::ATOMIC_LOAD_MIN, llvm::ISD::ATOMIC_LOAD_NAND, llvm::ISD::ATOMIC_LOAD_OR, llvm::ISD::ATOMIC_LOAD_SUB, llvm::ISD::ATOMIC_LOAD_UMAX, llvm::ISD::ATOMIC_LOAD_UMIN, llvm::ISD::ATOMIC_LOAD_XOR, llvm::ISD::ATOMIC_STORE, llvm::ISD::ATOMIC_SWAP, getAtomic(), llvm::SDValue::getValueType(), getVTList(), and llvm::MVT::Other.
SDValue SelectionDAG::getAtomic | ( | unsigned | Opcode, |
const SDLoc & | dl, | ||
EVT | MemVT, | ||
EVT | VT, | ||
SDValue | Chain, | ||
SDValue | Ptr, | ||
MachineMemOperand * | MMO | ||
) |
Gets a node for an atomic op, produces result and chain and takes 1 operand.
Definition at line 6480 of file SelectionDAG.cpp.
References assert(), llvm::ISD::ATOMIC_LOAD, getAtomic(), getVTList(), and llvm::MVT::Other.
SDValue SelectionDAG::getAtomic | ( | unsigned | Opcode, |
const SDLoc & | dl, | ||
EVT | MemVT, | ||
SDVTList | VTList, | ||
ArrayRef< SDValue > | Ops, | ||
MachineMemOperand * | MMO | ||
) |
Gets a node for an atomic op, produces result and chain and takes N operands.
Definition at line 6365 of file SelectionDAG.cpp.
References llvm::FoldingSetNodeID::AddInteger(), AddNodeIDNode(), E, llvm::MachinePointerInfo::getAddrSpace(), llvm::SDLoc::getDebugLoc(), llvm::SDLoc::getIROrder(), llvm::MachineMemOperand::getPointerInfo(), and llvm::EVT::getRawBits().
SDValue SelectionDAG::getAtomicCmpSwap | ( | unsigned | Opcode, |
const SDLoc & | dl, | ||
EVT | MemVT, | ||
SDVTList | VTs, | ||
SDValue | Chain, | ||
SDValue | Ptr, | ||
SDValue | Cmp, | ||
SDValue | Swp, | ||
MachinePointerInfo | PtrInfo, | ||
unsigned | Alignment, | ||
AtomicOrdering | SuccessOrdering, | ||
AtomicOrdering | FailureOrdering, | ||
SyncScope::ID | SSID | ||
) |
Gets a node for an atomic cmpxchg op.
There are two valid Opcodes. ISD::ATOMIC_CMO_SWAP produces the value loaded and a chain result. ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS produces the value loaded, a success flag (initially i1), and a chain.
Definition at line 6387 of file SelectionDAG.cpp.
References assert(), llvm::ISD::ATOMIC_CMP_SWAP, llvm::ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, getEVTAlignment(), getMachineFunction(), llvm::MachineFunction::getMachineMemOperand(), llvm::EVT::getStoreSize(), llvm::SDValue::getValueType(), llvm::MachineMemOperand::MOLoad, llvm::MachineMemOperand::MOStore, and llvm::MachineMemOperand::MOVolatile.
Referenced by getExpandedMinMaxOps(), getShiftAmountTyForConstant(), and getUniformBase().
SDValue SelectionDAG::getAtomicCmpSwap | ( | unsigned | Opcode, |
const SDLoc & | dl, | ||
EVT | MemVT, | ||
SDVTList | VTs, | ||
SDValue | Chain, | ||
SDValue | Ptr, | ||
SDValue | Cmp, | ||
SDValue | Swp, | ||
MachineMemOperand * | MMO | ||
) |
Definition at line 6413 of file SelectionDAG.cpp.
References assert(), llvm::ISD::ATOMIC_CMP_SWAP, llvm::ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, getAtomic(), and llvm::SDValue::getValueType().
SDValue SelectionDAG::getAtomicMemcpy | ( | SDValue | Chain, |
const SDLoc & | dl, | ||
SDValue | Dst, | ||
unsigned | DstAlign, | ||
SDValue | Src, | ||
unsigned | SrcAlign, | ||
SDValue | Size, | ||
Type * | SizeTy, | ||
unsigned | ElemSz, | ||
bool | isTailCall, | ||
MachinePointerInfo | DstPtrInfo, | ||
MachinePointerInfo | SrcPtrInfo | ||
) |
Definition at line 6120 of file SelectionDAG.cpp.
References llvm::AMDGPU::HSAMD::Kernel::Key::Args, getContext(), getDataLayout(), getExternalSymbol(), llvm::DataLayout::getIntPtrType(), llvm::TargetLoweringBase::getLibcallCallingConv(), llvm::TargetLoweringBase::getLibcallName(), llvm::RTLIB::getMEMCPY_ELEMENT_UNORDERED_ATOMIC(), llvm::TargetLoweringBase::getPointerTy(), llvm::Type::getVoidTy(), llvm::TargetLowering::LowerCallTo(), llvm::TargetLoweringBase::ArgListEntry::Node, llvm::report_fatal_error(), llvm::TargetLowering::CallLoweringInfo::setChain(), llvm::TargetLowering::CallLoweringInfo::setDebugLoc(), llvm::TargetLowering::CallLoweringInfo::setLibCallee(), llvm::TargetLowering::CallLoweringInfo::setTailCall(), Size, and llvm::TargetLoweringBase::ArgListEntry::Ty.
Referenced by getUnderlyingArgReg().
SDValue SelectionDAG::getAtomicMemmove | ( | SDValue | Chain, |
const SDLoc & | dl, | ||
SDValue | Dst, | ||
unsigned | DstAlign, | ||
SDValue | Src, | ||
unsigned | SrcAlign, | ||
SDValue | Size, | ||
Type * | SizeTy, | ||
unsigned | ElemSz, | ||
bool | isTailCall, | ||
MachinePointerInfo | DstPtrInfo, | ||
MachinePointerInfo | SrcPtrInfo | ||
) |
Definition at line 6222 of file SelectionDAG.cpp.
References llvm::AMDGPU::HSAMD::Kernel::Key::Args, getContext(), getDataLayout(), getExternalSymbol(), llvm::DataLayout::getIntPtrType(), llvm::TargetLoweringBase::getLibcallCallingConv(), llvm::TargetLoweringBase::getLibcallName(), llvm::RTLIB::getMEMMOVE_ELEMENT_UNORDERED_ATOMIC(), llvm::TargetLoweringBase::getPointerTy(), llvm::Type::getVoidTy(), llvm::TargetLowering::LowerCallTo(), llvm::TargetLoweringBase::ArgListEntry::Node, llvm::report_fatal_error(), llvm::TargetLowering::CallLoweringInfo::setChain(), llvm::TargetLowering::CallLoweringInfo::setDebugLoc(), llvm::TargetLowering::CallLoweringInfo::setLibCallee(), llvm::TargetLowering::CallLoweringInfo::setTailCall(), Size, and llvm::TargetLoweringBase::ArgListEntry::Ty.
Referenced by getUnderlyingArgReg().
SDValue SelectionDAG::getAtomicMemset | ( | SDValue | Chain, |
const SDLoc & | dl, | ||
SDValue | Dst, | ||
unsigned | DstAlign, | ||
SDValue | Value, | ||
SDValue | Size, | ||
Type * | SizeTy, | ||
unsigned | ElemSz, | ||
bool | isTailCall, | ||
MachinePointerInfo | DstPtrInfo | ||
) |
Definition at line 6325 of file SelectionDAG.cpp.
References llvm::AMDGPU::HSAMD::Kernel::Key::Args, getContext(), getDataLayout(), getExternalSymbol(), llvm::Type::getInt8Ty(), llvm::DataLayout::getIntPtrType(), llvm::TargetLoweringBase::getLibcallCallingConv(), llvm::TargetLoweringBase::getLibcallName(), llvm::RTLIB::getMEMSET_ELEMENT_UNORDERED_ATOMIC(), llvm::TargetLoweringBase::getPointerTy(), llvm::Type::getVoidTy(), llvm::TargetLowering::LowerCallTo(), llvm::TargetLoweringBase::ArgListEntry::Node, llvm::report_fatal_error(), llvm::TargetLowering::CallLoweringInfo::setChain(), llvm::TargetLowering::CallLoweringInfo::setDebugLoc(), llvm::TargetLowering::CallLoweringInfo::setLibCallee(), llvm::TargetLowering::CallLoweringInfo::setTailCall(), Size, and llvm::TargetLoweringBase::ArgListEntry::Ty.
Referenced by getUnderlyingArgReg().
SDValue SelectionDAG::getBasicBlock | ( | MachineBasicBlock * | MBB | ) |
Definition at line 1470 of file SelectionDAG.cpp.
References AddNodeIDNode(), llvm::FoldingSetNodeID::AddPointer(), llvm::ISD::BasicBlock, E, getVTList(), llvm::None, and llvm::MVT::Other.
Referenced by AddNodeIDCustom(), CallingConvSupported(), findMatchingInlineAsmOperand(), llvm::SelectionDAGBuilder::getValueImpl(), llvm::SelectionDAGBuilder::ShouldEmitAsBranches(), llvm::SelectionDAGBuilder::visitBitTestCase(), llvm::SelectionDAGBuilder::visitBitTestHeader(), llvm::SelectionDAGBuilder::visitJumpTableHeader(), llvm::SelectionDAGBuilder::visitSPDescriptorParent(), and llvm::SelectionDAGBuilder::visitSwitchCase().
SDValue llvm::SelectionDAG::getBasicBlock | ( | MachineBasicBlock * | MBB, |
SDLoc | dl | ||
) |
Return a bitcast using the SDLoc of the value operand, and casting to the provided type.
Use getNode to set a custom SDLoc.
Definition at line 1835 of file SelectionDAG.cpp.
References llvm::ISD::BITCAST, getNode(), and llvm::SDValue::getValueType().
Referenced by BuildSplatI(), combineAnd(), combineAndMaskToShift(), combineANDXORWithAllOnesIntoANDNP(), combineBasicSADPattern(), combineBitcast(), combineCastedMaskArithmetic(), combineCompareEqual(), combineConcatVectorOfExtracts(), combineConcatVectorOfScalars(), combineExtractSubvector(), combineExtractVectorElt(), combineExtractWithShuffle(), combineFMA(), combineFneg(), combineHorizontalMinMaxResult(), combineHorizontalPredicateResult(), combineInsertSubvector(), combineLogicBlendIntoPBLENDV(), combineMaskedLoad(), combineMaskedStore(), combineMOVMSK(), combineMulToPMADDWD(), combineOr(), combineRedundantDWordShuffle(), combineSelect(), combineShuffle(), combineShuffleToVectorExtend(), combineStore(), combineTargetShuffle(), combineToExtendBoolVectorInReg(), combineTruncationShuffle(), combineVectorCompareAndMaskUnaryOp(), combineVectorSizedSetCCEquality(), combineVSelectWithAllOnesOrZeros(), combineX86ShuffleChain(), combineX86ShufflesConstants(), combineXor(), convertIntLogicToFPLogic(), convertShiftLeftToScale(), createMMXBuildVector(), createVariablePermute(), EltsFromConsecutiveLoads(), ExtractBitFromMaskVector(), foldBitcastedFPLogic(), FoldIntToFPToInt(), getBuildDwordsVector(), getConstVector(), getCopyFromPartsVector(), getCopyToPartsVector(), getMaskNode(), getMemCmpLoad(), getMemsetValue(), getMOVL(), getOnesVector(), GetPromotionOpcode(), getScalarMaskingNode(), getScalarValueForVectorElement(), getTargetVShiftByConstNode(), getTargetVShiftNode(), getv64i1Argument(), getVShift(), getZeroVector(), haveEfficientBuildVectorPattern(), llvm::TargetLowering::IncrementMemoryAddress(), isSortedByValueNo(), isTruncateOf(), isTruncWithZeroHighBitsInput(), lower256BitVectorShuffle(), LowerAVXExtend(), llvm::HexagonTargetLowering::LowerBITCAST(), LowerBITCAST(), LowerBITREVERSE_XOP(), LowerBUILD_VECTORAsVariablePermute(), LowerBUILD_VECTORvXi1(), lowerBuildVectorAsBroadcast(), LowerBuildVectorAsInsert(), LowerBuildVectorv16i8(), LowerBuildVectorv4x32(), llvm::HexagonTargetLowering::LowerCall(), LowerCTPOP(), LowerEXTEND_VECTOR_INREG(), LowerEXTRACT_VECTOR_ELT_SSE4(), LowerHorizontalByteSum(), LowerI64IntToFP_AVX512DQ(), LowerLoad(), lowerMasksToReg(), LowerMUL(), LowerMULH(), lowerRegToMasks(), LowerRotate(), LowerSCALAR_TO_VECTOR(), LowerScalarImmediateShift(), LowerScalarVariableShift(), LowerShift(), LowerStore(), LowerTruncateVecI1(), llvm::AMDGPUTargetLowering::LowerUDIVREM64(), LowerUINT_TO_FP_i32(), LowerUINT_TO_FP_i64(), lowerUINT_TO_FP_vec(), lowerUINT_TO_FP_vXi32(), lowerV16I32VectorShuffle(), lowerV16I8VectorShuffle(), lowerV2I64VectorShuffle(), lowerV4I32VectorShuffle(), lowerV4I64VectorShuffle(), lowerV8I16GeneralSingleInputVectorShuffle(), lowerV8I32VectorShuffle(), lowerV8I64VectorShuffle(), llvm::HexagonTargetLowering::LowerVECTOR_SHUFFLE(), LowerVectorAllZeroTest(), LowerVectorCTLZInRegLUT(), LowerVectorCTPOP(), lowerVectorShuffle(), lowerVectorShuffleAsBlend(), lowerVectorShuffleAsBlendOfPSHUFBs(), lowerVectorShuffleAsBroadcast(), lowerVectorShuffleAsByteRotate(), lowerVectorShuffleAsByteRotateAndPermute(), lowerVectorShuffleAsElementInsertion(), lowerVectorShuffleAsLanePermuteAndBlend(), lowerVectorShuffleAsPermuteAndUnpack(), lowerVectorShuffleAsShift(), lowerVectorShuffleAsSpecificZeroOrAnyExtend(), lowerVectorShuffleAsZeroOrAnyExtend(), lowerVectorShuffleWithPACK(), lowerVectorShuffleWithPSHUFB(), lowerVSELECTtoVectorShuffle(), LowerVSETCC(), lowerX86FPLogicOp(), matchVectorShuffleWithPACK(), mayTailCallThisCC(), narrowExtractedVectorBinOp(), narrowExtractedVectorLoad(), numVectorEltsOrZero(), parseTexFail(), Passv64i1ArgInRegs(), recoverFramePointer(), reduceBuildVecToShuffleWithZero(), reduceVMULWidth(), llvm::X86TargetLowering::ReplaceNodeResults(), replaceShuffleOfInsert(), scalarizeExtractedBinop(), ShrinkLoadReplaceStoreWithStore(), splitAndLowerVectorShuffle(), truncateVectorWithPACK(), visitFMinMax(), widenVec(), and XFormVExtractWithShuffleIntoLoad().
SDValue SelectionDAG::getBlockAddress | ( | const BlockAddress * | BA, |
EVT | VT, | ||
int64_t | Offset = 0 , |
||
bool | isTarget = false , |
||
unsigned char | TargetFlags = 0 |
||
) |
Definition at line 1781 of file SelectionDAG.cpp.
References llvm::FoldingSetNodeID::AddInteger(), AddNodeIDNode(), llvm::FoldingSetNodeID::AddPointer(), llvm::ISD::BlockAddress, E, getVTList(), llvm::None, and llvm::ISD::TargetBlockAddress.
Referenced by llvm::SelectionDAGBuilder::getValueImpl(), and llvm::LanaiTargetLowering::LowerBlockAddress().
Create a true or false constant of type VT
using the target's BooleanContent for type OpVT
.
Definition at line 1152 of file SelectionDAG.cpp.
References getAllOnesConstant(), llvm::TargetLoweringBase::getBooleanContents(), getConstant(), llvm_unreachable, llvm::TargetLoweringBase::UndefinedBooleanContent, llvm::TargetLoweringBase::ZeroOrNegativeOneBooleanContent, and llvm::TargetLoweringBase::ZeroOrOneBooleanContent.
Referenced by foldExtendedSignBitTest(), FoldSetCC(), getLogicalNOT(), and llvm::TargetLowering::SimplifySetCC().
Convert Op, which must be of integer type, to the integer type VT, by using an extension appropriate for the target's BooleanContent for type OpVT or truncating it.
Definition at line 1118 of file SelectionDAG.cpp.
References llvm::EVT::bitsLE(), llvm::TargetLoweringBase::getBooleanContents(), llvm::TargetLoweringBase::getExtendForContent(), getNode(), llvm::SDValue::getValueType(), and llvm::ISD::TRUNCATE.
Referenced by isBooleanFlip(), and llvm::TargetLowering::SimplifySetCC().
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inline |
Return an ISD::BUILD_VECTOR node.
The number of elements in VT, which must be a vector type, must match the number of operands in Ops. The operands must have the same type as (or, for integers, a type wider than) VT's element type.
Definition at line 734 of file SelectionDAG.h.
References llvm::ISD::BUILD_VECTOR.
Referenced by adjustLoadValueTypeImpl(), llvm::SparcTargetLowering::bitcastConstantFPToInt(), BuildExactSDIV(), buildScalarToVector(), llvm::TargetLowering::BuildSDIV(), llvm::TargetLowering::BuildUDIV(), buildVector(), calculateByteProvider(), CollectOpsToWiden(), combineConcatVectorOfExtracts(), combineConcatVectorOfScalars(), combineExtractSubvector(), combineShuffleOfScalars(), combineStore(), combineToExtendBoolVectorInReg(), combineX86ShuffleChain(), CompactSwizzlableVector(), ConstantBuildVector(), constructRetValue(), convertLocVTToValVT(), convertShiftLeftToScale(), decrementVectorConstant(), ExtendToType(), extractSubVector(), findUser(), foldBitcastedFPLogic(), FoldCONCAT_VECTORS(), FoldConstantArithmetic(), FoldConstantVectorArithmetic(), GeneratePerfectShuffle(), GenerateTBL(), getBuildDwordsVector(), getBuildVectorSplat(), getConstant(), getConstVector(), getCopyFromPartsVector(), getExpandedMinMaxOps(), getFPTernOp(), getGeneralPermuteNode(), getLoadExtOrTrunc(), getNode(), getTargetVShiftByConstNode(), getTargetVShiftNode(), getUnderlyingArgReg(), llvm::SelectionDAGBuilder::getValueImpl(), getVectorCompareInfo(), hasOnlySelectUsers(), haveEfficientBuildVectorPattern(), isClampZeroToOne(), isSETCCorConvertedSETCC(), IsSingleInstrConstant(), isTruncateOf(), LowerBITREVERSE(), LowerBITREVERSE_XOP(), LowerBUILD_VECTORAsVariablePermute(), LowerBUILD_VECTORvXi1(), lowerBuildVectorToBitOp(), LowerBuildVectorv4x32(), llvm::AMDGPUTargetLowering::LowerCONCAT_VECTORS(), llvm::AMDGPUTargetLowering::LowerFP64_TO_INT(), llvm::AMDGPUTargetLowering::LowerFTRUNC(), lowerMSABinaryBitImmIntr(), lowerMSABitClearImm(), lowerMSASplatZExt(), LowerMUL(), LowerMULH(), LowerShift(), llvm::AMDGPUTargetLowering::LowerSIGN_EXTEND_INREG(), LowerTruncateVectorStore(), llvm::AMDGPUTargetLowering::LowerUDIVREM64(), lowerVECTOR_SHUFFLE_VSHF(), LowerVECTOR_SHUFFLEv8i8(), LowerVectorCTLZInRegLUT(), LowerVectorCTPOPInRegLUT(), lowerVectorShuffleAsBitBlend(), lowerVectorShuffleAsBitMask(), lowerVectorShuffleAsBlend(), lowerVectorShuffleAsBlendOfPSHUFBs(), lowerVectorShuffleAsSpecificZeroOrAnyExtend(), lowerVectorShuffleWithPSHUFB(), narrowExtractedVectorLoad(), NormalizeBuildVector(), parseTexFail(), PerformBUILD_VECTORCombine(), llvm::R600TargetLowering::PerformDAGCombine(), llvm::AMDGPUTargetLowering::PerformDAGCombine(), llvm::AMDGPUTargetLowering::performShlCombine(), llvm::AMDGPUTargetLowering::performSraCombine(), llvm::AMDGPUTargetLowering::performSrlCombine(), ReorganizeVector(), ReplaceINTRINSIC_W_CHAIN(), ReplaceLoadVector(), llvm::R600TargetLowering::ReplaceNodeResults(), llvm::X86TargetLowering::ReplaceNodeResults(), replaceShuffleOfInsert(), scalarizeExtractedBinop(), llvm::TargetLowering::scalarizeVectorLoad(), ShrinkLoadReplaceStoreWithStore(), llvm::TargetLowering::SimplifyDemandedVectorElts(), skipExtensionForVectorMULL(), SkipExtensionForVMULL(), splitAndLowerVectorShuffle(), llvm::AMDGPUTargetLowering::splitBinaryBitConstantOpImpl(), tryBuildVectorShuffle(), tryToFoldExtendOfConstant(), vectorEltWillFoldAway(), and widenVectorToPartType().
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inline |
Return an ISD::BUILD_VECTOR node.
The number of elements in VT, which must be a vector type, must match the number of operands in Ops. The operands must have the same type as (or, for integers, a type wider than) VT's element type.
Definition at line 743 of file SelectionDAG.h.
References llvm::ISD::BUILD_VECTOR.
|
inline |
Return a new CALLSEQ_END node, which always must have a glue result (to ensure it's not CSE'd).
CALLSEQ_END does not have a useful SDLoc.
Definition at line 836 of file SelectionDAG.h.
References llvm::ISD::CALLSEQ_END, llvm::SDValue::getNode(), llvm::MVT::Glue, isUndef(), llvm::MVT::Other, and llvm::SmallVectorTemplateBase< T >::push_back().
Referenced by addStackMapLiveVars(), llvm::analyzeArguments(), AnalyzeReturnValues(), CC_Lanai32_VarArg(), llvm::ARMTargetLowering::CCAssignFnForReturn(), getMOVL(), llvm::ARCTargetLowering::getTargetNodeName(), llvm::HexagonTargetLowering::LowerCall(), llvm::SITargetLowering::LowerCall(), llvm::SystemZTargetLowering::LowerCall(), llvm::NVPTXTargetLowering::LowerCall(), llvm::SparcTargetLowering::LowerCall_32(), llvm::SparcTargetLowering::LowerCall_64(), LowerCallResult(), llvm::SparcTargetLowering::LowerGlobalTLSAddress(), llvm::BPFTargetLowering::LowerOperation(), LowerToTLSExecModel(), mayTailCallThisCC(), PrepareCall(), PrepareTailCall(), and unpackF64OnRV32DSoftABI().
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inline |
Return a new CALLSEQ_START node, that starts new call frame, in which InSize bytes are set up inside CALLSEQ_START..CALLSEQ_END sequence and OutSize specifies part of the frame set up prior to the sequence.
Definition at line 824 of file SelectionDAG.h.
References llvm::ISD::CALLSEQ_START, llvm::MVT::Glue, and llvm::MVT::Other.
Referenced by addStackMapLiveVars(), llvm::analyzeArguments(), AnalyzeReturnValues(), CC_Lanai32_VarArg(), llvm::ARMTargetLowering::CCAssignFnForReturn(), getMOVL(), llvm::ARCTargetLowering::getTargetNodeName(), llvm::HexagonTargetLowering::LowerCall(), llvm::SITargetLowering::LowerCall(), llvm::SystemZTargetLowering::LowerCall(), llvm::NVPTXTargetLowering::LowerCall(), llvm::SparcTargetLowering::LowerCall_32(), llvm::SparcTargetLowering::LowerCall_64(), LowerCallResult(), llvm::SparcTargetLowering::LowerGlobalTLSAddress(), llvm::BPFTargetLowering::LowerOperation(), LowerToTLSExecModel(), mayTailCallThisCC(), PrepareCall(), and unpackF64OnRV32DSoftABI().
SDValue SelectionDAG::getCommutedVectorShuffle | ( | const ShuffleVectorSDNode & | SV | ) |
Returns an ISD::VECTOR_SHUFFLE node semantically equivalent to the shuffle node in input but with swapped operands.
Example: shuffle A, B, <0,5,2,7> -> shuffle B, A, <4,1,6,3>
Definition at line 1719 of file SelectionDAG.cpp.
References llvm::ShuffleVectorSDNode::commuteMask(), llvm::ShuffleVectorSDNode::getMask(), llvm::SDNode::getOperand(), llvm::SDNode::getValueType(), and getVectorShuffle().
Referenced by lowerVectorShuffle(), and replaceShuffleOfInsert().
SDValue SelectionDAG::getCondCode | ( | ISD::CondCode | Cond | ) |
Definition at line 1526 of file SelectionDAG.cpp.
References N.
Referenced by getExpandedMinMaxOps(), GetFPLibCall(), lowerFCMPIntrinsic(), lowerICMPIntrinsic(), LowerVSETCC(), llvm::R600TargetLowering::ReplaceNodeResults(), and llvm::TargetLowering::softenSetCCOperands().
SDValue SelectionDAG::getConstant | ( | uint64_t | Val, |
const SDLoc & | DL, | ||
EVT | VT, | ||
bool | isTarget = false , |
||
bool | isOpaque = false |
||
) |
Create a ConstantSDNode wrapping a constant value.
If VT is a vector type, the constant is splatted into a BUILD_VECTOR.
If only legal types can be produced, this does the necessary transformations (e.g., if the vector element type is illegal).
Definition at line 1167 of file SelectionDAG.cpp.
References assert(), llvm::EVT::getScalarType(), and llvm::EVT::getSizeInBits().
Referenced by AddCombineBUILD_VECTORToVPADDL(), AddCombineToVPADD(), AddCombineVUZPToVPADDL(), addIPMSequence(), adjustForSubtraction(), adjustForTestUnderMask(), adjustICmpTruncate(), adjustSubwordCmp(), adjustZeroCmp(), AnalyzeReturnValues(), llvm::SparcTargetLowering::bitcastConstantFPToInt(), bitcastf32Toi32(), BuildExactSDIV(), BuildIntrinsicOp(), llvm::SITargetLowering::buildRSRC(), llvm::TargetLowering::BuildSDIV(), llvm::PPCTargetLowering::BuildSDIVPow2(), BuildSplatI(), llvm::TargetLowering::BuildUDIV(), buildVector(), calculateByteProvider(), CallingConvSupported(), canFoldInAddressingMode(), CC_Lanai32_VarArg(), llvm::AArch64TargetLowering::CCAssignFnForReturn(), llvm::ARMTargetLowering::CCAssignFnForReturn(), clampDynamicVectorIndex(), CollectOpsToWiden(), combineAcrossLanesIntrinsic(), combineADC(), combineAddOrSubToADCOrSBB(), combineADDToADDZE(), combineAndMaskToShift(), combineAndnp(), CombineANDShift(), CombineBaseUpdate(), combineBEXTR(), combineBitcast(), combineBitcastvxi1(), combineBrCond(), combineCCMask(), combineCMov(), combineCMP(), combineCompareEqual(), combineExtractSubvector(), combineExtractVectorElt(), combineExtractWithShuffle(), combineHorizontalMinMaxResult(), combineHorizontalPredicateResult(), combineLoopMAddPattern(), combineLoopSADPattern(), combineMaskedLoad(), combineMaskedStore(), combineMinNumMaxNum(), combineMOVMSK(), combineMul(), combineMulSpecial(), combineParity(), combineSelect(), combineSelectOfTwoConstants(), combineSetCC(), combineSetCCAtomicArith(), combineSext(), combineShiftLeft(), combineShiftRightArithmetic(), combineShiftRightLogical(), combineSub(), combineSubToSubus(), combineTargetShuffle(), combineToExtendBoolVectorInReg(), combineVectorCompare(), combineVectorShiftImm(), combineVectorShiftVar(), combineVectorSizedSetCCEquality(), combineVectorTruncationWithPACKUS(), CombineVMOVDRRCandidateWithVecOp(), combinevXi1ConstantToInteger(), combineX86ShuffleChain(), combineZext(), ConstantAddressBlock(), ConstantBuildVector(), constantFoldBFE(), ConvertBooleanCarryToCarryFlag(), ConvertCarryFlagToBooleanCarry(), ConvertI1VectorToInteger(), ConvertSelectToConcatVector(), convertShiftLeftToScale(), convertValVTToLocVT(), CreateCopyOfByValArgument(), createFPCmp(), createGPRPairNode(), createLoadLR(), createMMXBuildVector(), createPSADBW(), createStoreLR(), createVariablePermute(), decrementVectorConstant(), detectAVGPattern(), EltsFromConsecutiveLoads(), emitCLC(), EmitCMP(), emitConditionalComparison(), llvm::MipsSETargetLowering::EmitInstrWithCustomInserter(), llvm::XCoreTargetLowering::EmitInstrWithCustomInserter(), llvm::MipsTargetLowering::EmitInstrWithCustomInserter(), EmitKORTEST(), emitMemMem(), emitSETCC(), llvm::SystemZSelectionDAGInfo::EmitTargetCodeForMemchr(), llvm::BPFSelectionDAGInfo::EmitTargetCodeForMemcpy(), llvm::X86SelectionDAGInfo::EmitTargetCodeForMemcpy(), llvm::ARMSelectionDAGInfo::EmitTargetCodeForMemcpy(), llvm::SystemZSelectionDAGInfo::EmitTargetCodeForMemset(), llvm::X86SelectionDAGInfo::EmitTargetCodeForMemset(), llvm::SystemZSelectionDAGInfo::EmitTargetCodeForStrcmp(), llvm::SystemZSelectionDAGInfo::EmitTargetCodeForStrcpy(), llvm::SystemZSelectionDAGInfo::EmitTargetCodeForStrlen(), EmitTest(), EnsureStackAlignment(), Expand64BitShift(), llvm::TargetLowering::expandABS(), ExpandBITCAST(), expandf64Toi32(), llvm::TargetLowering::expandMUL_LOHI(), llvm::TargetLowering::expandUnalignedLoad(), llvm::TargetLowering::expandUnalignedStore(), ExtendToType(), ExtendUsesToFormExtLoad(), ExtractBitFromMaskVector(), extractF64Exponent(), extractShiftForRotate(), findUser(), flipBoolean(), foldAddSubBoolOfMaskedVal(), foldAddSubOfSignBit(), foldBitcastedFPLogic(), FoldConstantArithmetic(), foldExtendedSignBitTest(), FoldIntToFPToInt(), foldMaskAndShiftToExtract(), foldMaskAndShiftToScale(), foldMaskedShiftToBEXTR(), foldMaskedShiftToScaledMask(), foldXorTruncShiftIntoCmp(), fp16SrcZerosHighBits(), genConstMult(), generateEquivalentSub(), GeneratePerfectShuffle(), GenerateTBL(), getAArch64Cmp(), getAArch64XALUOOp(), getAbsolute(), llvm::MipsTargetLowering::getAddrNonPICSym64(), getARMIndexedAddressParts(), getAsCarry(), getBoolConstant(), getBuildVectorSplat(), getCCResult(), getConstant(), getConstVector(), getCopyFromParts(), getCopyFromPartsVector(), llvm::RegsForValue::getCopyFromRegs(), getCopyToPartsVector(), GetDemandedBits(), getDivRemArgList(), getDUPLANEOp(), getExpandedMinMaxOps(), GetExponent(), getExtendedControlRegister(), GetFPLibCall(), getFPTernOp(), getGeneralPermuteNode(), llvm::AMDGPUTargetLowering::getHiHalf64(), getIntPtrConstant(), llvm::XCoreTargetLowering::getJumpTableEncoding(), llvm::ARMTargetLowering::getJumpTableEncoding(), getLimitedPrecisionExp2(), getLoadExtOrTrunc(), llvm::AMDGPUTargetLowering::getLoHalf64(), getMad64_32(), getMaskNode(), getMemBasePlusOffset(), getMemCmpLoad(), getMemsetStringVal(), getMemsetValue(), getMOVL(), getNode(), getNOT(), getOnesVector(), getPermuteMask(), getPermuteNode(), llvm::PPCTargetLowering::getPICJumpTableRelocBaseExpr(), getPMOVMSKB(), llvm::AVRTargetLowering::getPostIndexedAddressParts(), llvm::AVRTargetLowering::getPreIndexedAddressParts(), GetPromotionOpcode(), getReadPerformanceCounter(), getReadTimeStampCounter(), getReductionSDNode(), getSETCC(), getShiftAmountTyForConstant(), getShuffleScalarElt(), GetSignificand(), llvm::NVPTXTargetLowering::getSqrtEstimate(), getT2IndexedAddressParts(), llvm::ARCTargetLowering::getTargetNodeName(), getTargetVShiftByConstNode(), getTargetVShiftNode(), llvm::MipsTargetLowering::getTypeForExtReturn(), getUnderlyingArgReg(), getUniformBase(), getV4X86ShuffleImm8ForMask(), llvm::SelectionDAGBuilder::getValueImpl(), getVectorCompareInfo(), llvm::TargetLowering::getVectorElementPointer(), getVShift(), getZeroExtendInReg(), getZeroVector(), hasOnlySelectUsers(), haveEfficientBuildVectorPattern(), llvm::TargetLowering::IncrementMemoryAddress(), initAccumulator(), insert1BitVector(), InsertBitToMaskVector(), llvm::intCCToAVRCC(), IntCondCCodeToICC(), isADDADDMUL(), isAddSubZExt(), isBLACompatibleAddress(), isBooleanFlip(), isBSwapHWordElement(), isClampZeroToOne(), isConditionalZeroOrAllOnes(), llvm::TargetLowering::isExtendedTrueVal(), isFloatingPointZero(), llvm::PPCTargetLowering::isLegalAddressingMode(), isLowerSaturatingConditional(), isMemOPCandidate(), isNEONModifiedImm(), llvm::ARMTargetLowering::isReadOnly(), isSETCCorConvertedSETCC(), IsSingleInstrConstant(), IsSmallObject(), isTargetConstant(), isTruncateOf(), isTruncWithZeroHighBitsInput(), llvm::SITargetLowering::isTypeDesirableForOp(), isVShiftRImm(), isWordAligned(), isXor1OfSetCC(), lower1BitVectorShuffle(), LowerABS(), LowerADDC_ADDE_SUBC_SUBE(), LowerADDSUBCARRY(), LowerADJUST_TRAMPOLINE(), LowerAndToBT(), LowerAsSplatVectorLoad(), LowerATOMIC_FENCE(), lowerAtomicArith(), LowerAVXExtend(), llvm::HexagonTargetLowering::LowerBITCAST(), LowerBITREVERSE(), LowerBITREVERSE_XOP(), llvm::LanaiTargetLowering::LowerBR_CC(), LowerBR_CC(), llvm::HexagonTargetLowering::LowerBUILD_VECTOR(), LowerBUILD_VECTORAsVariablePermute(), LowerBUILD_VECTORvXi1(), LowerBuildVectorv16i8(), llvm::HexagonTargetLowering::LowerCall(), llvm::SITargetLowering::LowerCall(), llvm::SystemZTargetLowering::LowerCall(), llvm::NVPTXTargetLowering::LowerCall(), llvm::SparcTargetLowering::LowerCall_32(), llvm::SparcTargetLowering::LowerCall_64(), lowerCallResult(), LowerCallResult(), llvm::TargetLowering::lowerCmpEqZeroToCtlzSrl(), llvm::HexagonTargetLowering::LowerCONCAT_VECTORS(), LowerCTLZ(), llvm::AMDGPUTargetLowering::LowerCTLZ_CTTZ(), LowerCTPOP(), LowerCTTZ(), llvm::AMDGPUTargetLowering::LowerDIVREM24(), llvm::HexagonTargetLowering::LowerDYNAMIC_STACKALLOC(), llvm::AMDGPUTargetLowering::LowerDYNAMIC_STACKALLOC(), LowerDYNAMIC_STACKALLOC(), LowerEXTEND_VECTOR_INREG(), LowerEXTRACT_SUBVECTOR(), LowerF128Load(), LowerF128Store(), lowerFCOPYSIGN32(), lowerFCOPYSIGN64(), LowerFGETSIGN(), llvm::R600TargetLowering::LowerFormalArguments(), llvm::HexagonTargetLowering::LowerFormalArguments(), llvm::NVPTXTargetLowering::LowerFormalArguments(), llvm::SparcTargetLowering::LowerFormalArguments_64(), llvm::AMDGPUTargetLowering::LowerFP_TO_FP16(), llvm::AMDGPUTargetLowering::LowerFROUND64(), llvm::AMDGPUTargetLowering::LowerFTRUNC(), LowerFunnelShift(), llvm::AMDGPUTargetLowering::LowerGlobalAddress(), llvm::HexagonTargetLowering::LowerGLOBALADDRESS(), LowerHorizontalByteSum(), llvm::AMDGPUTargetLowering::LowerINT_TO_FP32(), llvm::AMDGPUTargetLowering::LowerINT_TO_FP64(), LowerInterruptReturn(), llvm::HexagonTargetLowering::LowerINTRINSIC_VOID(), LowerINTRINSIC_W_CHAIN(), llvm::MSP430TargetLowering::LowerJumpTable(), LowerLabelRef(), llvm::MipsTargetLowering::lowerLOAD(), LowerLoad(), LowerMemOpCallTo(), LowerMINMAX(), lowerMSABinaryBitImmIntr(), lowerMSABitClear(), lowerMSABitClearImm(), lowerMSASplatImm(), lowerMSASplatZExt(), LowerMSCATTER(), llvm::LanaiTargetLowering::LowerMUL(), LowerMUL(), lowerMUL_LOHI32(), LowerMULH(), llvm::R600TargetLowering::LowerOperation(), llvm::BPFTargetLowering::LowerOperation(), llvm::RISCVTargetLowering::LowerOperation(), llvm::HexagonTargetLowering::LowerPREFETCH(), LowerPREFETCH(), llvm::NVPTXTargetLowering::LowerReturn(), llvm::SparcTargetLowering::LowerReturn_32(), llvm::SparcTargetLowering::LowerReturn_64(), llvm::MSP430TargetLowering::LowerRETURNADDR(), llvm::HexagonTargetLowering::LowerRETURNADDR(), LowerReverse_VECTOR_SHUFFLEv16i8_v8i16(), LowerRotate(), LowerScalarImmediateShift(), LowerScalarVariableShift(), LowerSDIV_v4i16(), LowerSDIV_v4i8(), llvm::AMDGPUTargetLowering::LowerSDIVREM(), llvm::LanaiTargetLowering::LowerSELECT_CC(), LowerSELECT_CC(), llvm::LanaiTargetLowering::LowerSETCC(), llvm::MSP430TargetLowering::LowerSETCC(), LowerSETCCCARRY(), LowerShift(), LowerShiftParts(), llvm::LanaiTargetLowering::LowerSHL_PARTS(), LowerSIGN_EXTEND_Mask(), llvm::LanaiTargetLowering::LowerSRL_PARTS(), LowerToTLSExecModel(), LowerTruncateVecI1(), LowerTruncateVectorStore(), LowerUDIV(), llvm::AMDGPUTargetLowering::LowerUDIVREM(), llvm::AMDGPUTargetLowering::LowerUDIVREM64(), lowerUINT_TO_FP_v2i32(), lowerUINT_TO_FP_vec(), lowerUINT_TO_FP_vXi32(), LowerUMULO_SMULO(), llvm::HexagonTargetLowering::LowerUnalignedLoad(), lowerV16I8VectorShuffle(), lowerV2F64VectorShuffle(), lowerV2X128VectorShuffle(), lowerV4F64VectorShuffle(), lowerV4X128VectorShuffle(), lowerV8F64VectorShuffle(), LowerVASTART(), LowerVECTOR_SHUFFLE(), lowerVECTOR_SHUFFLE_SHF(), LowerVECTOR_SHUFFLEv8i8(), LowerVectorAllZeroTest(), LowerVectorCTLZ_AVX512CDI(), LowerVectorCTLZInRegLUT(), LowerVectorCTPOPInRegLUT(), LowerVectorINT_TO_FP(), lowerVectorShuffleAsBitBlend(), lowerVectorShuffleAsBitMask(), lowerVectorShuffleAsBlend(), lowerVectorShuffleAsBlendOfPSHUFBs(), lowerVectorShuffleAsByteRotate(), lowerVectorShuffleAsByteRotateAndPermute(), lowerVectorShuffleAsElementInsertion(), lowerVectorShuffleAsInsertPS(), lowerVectorShuffleAsRotate(), lowerVectorShuffleAsShift(), lowerVectorShuffleAsSpecificZeroOrAnyExtend(), lowerVectorShuffleAsTruncBroadcast(), lowerVectorShuffleToEXPAND(), lowerVectorShuffleWithPSHUFB(), lowerVectorShuffleWithSHUFPD(), lowerVectorShuffleWithSSE4A(), lowerVSELECTtoVectorShuffle(), LowerVSETCC(), LowerVSETCCWithSUBUS(), LowerWRITE_REGISTER(), lowerX86CmpEqZeroToCtlzSrl(), LowerXALUO(), LowerXOR(), LowerZERO_EXTEND_Mask(), llvm::SparcTargetLowering::makeAddress(), mayTailCallThisCC(), memsetStore(), narrowExtractedVectorBinOp(), NegateCC(), NormalizeBuildVector(), numVectorEltsOrZero(), optimizeLogicalImm(), parseTexFail(), Passv64i1ArgInRegs(), PerformAddcSubcCombine(), PerformAddeSubeCombine(), performANDCombine(), PerformARMBUILD_VECTORCombine(), PerformBFICombine(), performBitcastCombine(), llvm::ARMTargetLowering::PerformCMOVCombine(), llvm::ARMTargetLowering::PerformCMOVToBFICombine(), performConcatVectorsCombine(), llvm::R600TargetLowering::PerformDAGCombine(), llvm::AMDGPUTargetLowering::PerformDAGCombine(), llvm::PPCTargetLowering::PerformDAGCombine(), performDSPShiftCombine(), performExtendCombine(), llvm::AMDGPUTargetLowering::performFAbsCombine(), performFDivCombine(), llvm::AMDGPUTargetLowering::performFNegCombine(), performFpToIntCombine(), performGlobalAddressCombine(), performIntegerAbsCombine(), PerformIntrinsicCombine(), performMulCombine(), PerformMULCombine(), performORCombine(), PerformORCombineToBFI(), performSetccAddFolding(), PerformShiftCombine(), llvm::AMDGPUTargetLowering::performShlCombine(), performSHLCombine(), PerformSHLSimplify(), llvm::AMDGPUTargetLowering::performSraCombine(), llvm::AMDGPUTargetLowering::performSrlCombine(), PerformSTORECombine(), performTBZCombine(), PerformVCVTCombine(), PerformVDIVCombine(), PerformVDUPCombine(), performXorCombine(), PrepareCall(), promoteExtBeforeAdd(), llvm::AArch64TargetLowering::ReconstructShuffle(), recoverFramePointer(), reduceBuildVecToShuffleWithZero(), ReorganizeVector(), ReplaceLongIntrinsic(), llvm::R600TargetLowering::ReplaceNodeResults(), llvm::AVRTargetLowering::ReplaceNodeResults(), llvm::SITargetLowering::ReplaceNodeResults(), llvm::X86TargetLowering::ReplaceNodeResults(), ReplaceREADCYCLECOUNTER(), replaceShuffleOfInsert(), scalarizeExtractedBinop(), llvm::TargetLowering::scalarizeVectorStore(), llvm::TargetLowering::ShrinkDemandedConstant(), ShrinkLoadReplaceStoreWithStore(), llvm::TargetLowering::SimplifyDemandedBits(), llvm::X86TargetLowering::SimplifyDemandedBitsForTargetNode(), llvm::TargetLowering::SimplifyDemandedVectorElts(), simplifyDivRem(), llvm::TargetLowering::SimplifySetCC(), simplifyShift(), skipExtensionForVectorMULL(), SkipExtensionForVMULL(), llvm::TargetLowering::softenSetCCOperands(), llvm::AMDGPUTargetLowering::split64BitValue(), llvm::AMDGPUTargetLowering::splitBinaryBitConstantOpImpl(), splitInt128(), splitStores(), splitStoreSplat(), llvm::AMDGPUTargetLowering::storeStackInputValue(), llvm::ARMTargetLowering::targetShrinkDemandedConstant(), llvm::X86TargetLowering::targetShrinkDemandedConstant(), TranslateX86CC(), truncateVecElts(), tryAdvSIMDModImm16(), tryAdvSIMDModImm32(), tryAdvSIMDModImm321s(), tryAdvSIMDModImm64(), tryAdvSIMDModImm8(), tryAdvSIMDModImmFP(), tryBuildVectorReplicate(), tryCombineShiftImm(), tryCombineToEXTR(), tryExtendDUPToExtractHigh(), tryFoldToZero(), tryFormConcatFromShuffle(), tryLowerToSLI(), TryMULWIDECombine(), tryToFoldExtendOfConstant(), unpackF64OnRV32DSoftABI(), UnpackFromArgumentSlot(), UnrollVectorShift(), llvm::SelectionDAGBuilder::visitBitTestCase(), llvm::SelectionDAGBuilder::visitBitTestHeader(), visitFMinMax(), llvm::SelectionDAGBuilder::visitJumpTableHeader(), llvm::SelectionDAGBuilder::visitSPDescriptorParent(), llvm::SelectionDAGBuilder::visitSwitchCase(), widenVec(), WidenVector(), willShiftRightEliminate(), WinDBZCheckDenominator(), and XFormVExtractWithShuffleIntoLoad().
SDValue SelectionDAG::getConstant | ( | const APInt & | Val, |
const SDLoc & | DL, | ||
EVT | VT, | ||
bool | isTarget = false , |
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bool | isOpaque = false |
||
) |
Definition at line 1176 of file SelectionDAG.cpp.
References llvm::ConstantInt::get(), and getConstant().
SDValue SelectionDAG::getConstant | ( | const ConstantInt & | Val, |
const SDLoc & | DL, | ||
EVT | VT, | ||
bool | isTarget = false , |
||
bool | isOpaque = false |
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) |
Definition at line 1181 of file SelectionDAG.cpp.
References llvm::FoldingSetNodeID::AddBoolean(), AddNodeIDNode(), llvm::FoldingSetNodeID::AddPointer(), assert(), llvm::ISD::BITCAST, llvm::ISD::Constant, llvm::SmallVectorTemplateCommon< T >::end(), llvm::ConstantInt::get(), llvm::ConstantInt::getBitWidth(), getBuildVector(), getConstant(), getContext(), getDataLayout(), getNode(), llvm::EVT::getScalarType(), llvm::EVT::getSizeInBits(), getSplatBuildVector(), llvm::TargetLoweringBase::getTypeAction(), llvm::TargetLoweringBase::getTypeToTransformTo(), llvm::ConstantInt::getValue(), llvm::EVT::getVectorNumElements(), llvm::EVT::getVectorVT(), getVTList(), llvm::SmallVectorImpl< T >::insert(), llvm::DataLayout::isBigEndian(), llvm::EVT::isInteger(), llvm::EVT::isVector(), llvm::APInt::lshr(), NewNodesMustHaveLegalTypes, NewSDValueDbgMsg(), llvm::None, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::reverse(), llvm::ISD::TargetConstant, llvm::TargetLoweringBase::TypeExpandInteger, llvm::TargetLoweringBase::TypePromoteInteger, and llvm::APInt::zextOrTrunc().
SDDbgValue * SelectionDAG::getConstantDbgValue | ( | DIVariable * | Var, |
DIExpression * | Expr, | ||
const Value * | C, | ||
const DebugLoc & | DL, | ||
unsigned | O | ||
) |
Creates a constant SDDbgValue node.
Definition at line 7869 of file SelectionDAG.cpp.
References assert(), and llvm::SDDbgInfo::getAlloc().
Referenced by getUnderlyingArgReg().
Create a ConstantFPSDNode wrapping a constant value.
If VT is a vector type, the constant is splatted into a BUILD_VECTOR.
If only legal types can be produced, this does the necessary transformations (e.g., if the vector element type is illegal). The forms that take a double should only be used for simple constants that can be exactly represented in VT. No checks are made.
Definition at line 1314 of file SelectionDAG.cpp.
References llvm::lltok::APFloat, llvm::APFloat::convert(), EVTToAPFloatSemantics(), llvm::MVT::f128, llvm::MVT::f16, llvm::MVT::f32, llvm::MVT::f64, llvm::MVT::f80, llvm::EVT::getScalarType(), llvm_unreachable, llvm::MVT::ppcf128, and llvm::APFloatBase::rmNearestTiesToEven.
Referenced by combineBitcast(), combineExtractWithShuffle(), combineFneg(), EltsFromConsecutiveLoads(), ExpandPowI(), foldFPToIntToFP(), FoldIntToFPToInt(), getConstantFP(), getConstVector(), getEstimate(), getF32Constant(), GetFPLibCall(), getFPTernOp(), getLog2EVal(), getMad64_32(), getMemsetStringVal(), getMemsetValue(), GetNegatedExpression(), getNode(), getShuffleScalarElt(), llvm::SelectionDAGBuilder::getValueImpl(), getVectorCompareInfo(), getZeroVector(), haveEfficientBuildVectorPattern(), llvm::SITargetLowering::isCanonicalized(), isContractable(), llvm::HexagonTargetLowering::LowerBITCAST(), LowerFABSorFNEG(), llvm::AMDGPUTargetLowering::LowerFCEIL(), LowerFCOPYSIGN(), llvm::AMDGPUTargetLowering::LowerFFLOOR(), llvm::AMDGPUTargetLowering::LowerFLOG(), llvm::AMDGPUTargetLowering::LowerFP64_TO_INT(), llvm::AMDGPUTargetLowering::LowerFRINT(), llvm::AMDGPUTargetLowering::LowerFROUND32_16(), llvm::AMDGPUTargetLowering::LowerFROUND64(), llvm::AMDGPUTargetLowering::LowerUDIVREM64(), LowerUINT_TO_FP_i32(), lowerUINT_TO_FP_v2i32(), lowerUINT_TO_FP_vec(), lowerUINT_TO_FP_vXi32(), parseTexFail(), llvm::AMDGPUTargetLowering::performRcpCombine(), PrepareCall(), reduceBuildVecToShuffleWithZero(), llvm::R600TargetLowering::ReplaceNodeResults(), llvm::X86TargetLowering::ReplaceNodeResults(), replaceShuffleOfInsert(), vectorEltWillFoldAway(), visitFMinMax(), widenVec(), and XFormVExtractWithShuffleIntoLoad().
SDValue SelectionDAG::getConstantFP | ( | const APFloat & | Val, |
const SDLoc & | DL, | ||
EVT | VT, | ||
bool | isTarget = false |
||
) |
Definition at line 1277 of file SelectionDAG.cpp.
References llvm::ConstantFP::get(), getConstantFP(), and getContext().
SDValue SelectionDAG::getConstantFP | ( | const ConstantFP & | V, |
const SDLoc & | DL, | ||
EVT | VT, | ||
bool | isTarget = false |
||
) |
Definition at line 1282 of file SelectionDAG.cpp.
References AddNodeIDNode(), llvm::FoldingSetNodeID::AddPointer(), assert(), llvm::ISD::ConstantFP, llvm::EVT::getScalarType(), getSplatBuildVector(), getVTList(), llvm::EVT::isFloatingPoint(), llvm::EVT::isVector(), NewSDValueDbgMsg(), llvm::None, and llvm::ISD::TargetConstantFP.
SDValue SelectionDAG::getConstantPool | ( | const Constant * | C, |
EVT | VT, | ||
unsigned | Align = 0 , |
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int | Offs = 0 , |
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bool | isT = false , |
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unsigned char | TargetFlags = 0 |
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) |
Definition at line 1399 of file SelectionDAG.cpp.
References llvm::FoldingSetNodeID::AddInteger(), AddNodeIDNode(), llvm::FoldingSetNodeID::AddPointer(), assert(), C, llvm::ISD::ConstantPool, E, llvm::DataLayout::getABITypeAlignment(), getDataLayout(), llvm::MachineFunction::getFunction(), llvm::DataLayout::getPrefTypeAlignment(), llvm::Value::getType(), getVTList(), llvm::None, llvm::Function::optForSize(), and llvm::ISD::TargetConstantPool.
Referenced by getAddressForMemoryInput(), getExpandedMinMaxOps(), haveEfficientBuildVectorPattern(), IsSmallObject(), LowerBUILD_VECTORAsVariablePermute(), lowerBuildVectorAsBroadcast(), LowerUINT_TO_FP_i64(), lowerUINT_TO_FP_vec(), and replaceShuffleOfInsert().
SDValue SelectionDAG::getConstantPool | ( | MachineConstantPoolValue * | C, |
EVT | VT, | ||
unsigned | Align = 0 , |
||
int | Offs = 0 , |
||
bool | isT = false , |
||
unsigned char | TargetFlags = 0 |
||
) |
Definition at line 1427 of file SelectionDAG.cpp.
References llvm::FoldingSetNodeID::AddInteger(), AddNodeIDNode(), llvm::MachineConstantPoolValue::addSelectionDAGCSEId(), assert(), C, llvm::ISD::ConstantPool, E, getDataLayout(), llvm::DataLayout::getPrefTypeAlignment(), llvm::MachineConstantPoolValue::getType(), getVTList(), llvm::None, and llvm::ISD::TargetConstantPool.
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inline |
Definition at line 407 of file SelectionDAG.h.
References Context.
Referenced by AddCombineVUZPToVPADDL(), llvm::RegsForValue::AddInlineAsmOperands(), addStackMapLiveVars(), adjustLoadValueTypeImpl(), llvm::analyzeArguments(), AnalyzeReturnValues(), buildPCRelGlobalAddress(), calculateByteProvider(), CallingConvSupported(), canFoldInAddressingMode(), CC_Lanai32_VarArg(), llvm::AArch64TargetLowering::CCAssignFnForReturn(), llvm::ARMTargetLowering::CCAssignFnForReturn(), CollectOpsToWiden(), combineConcatVectorOfExtracts(), combineConcatVectorOfScalars(), combineFMinNumFMaxNum(), combineGatherScatter(), combineHorizontalMinMaxResult(), combineHorizontalPredicateResult(), combineInsertSubvector(), combineLoad(), combineLoopMAddPattern(), combineMaskedLoad(), combineMaskedStore(), combineMinNumMaxNum(), combineShuffleToVectorExtend(), combineSIntToFP(), combineStore(), combineToExtendBoolVectorInReg(), combineToExtendVectorInReg(), combineTruncateWithSat(), combineUIntToFP(), combineVectorTruncationWithPACKUS(), CombineVMOVDRRCandidateWithVecOp(), combineVSelectWithAllOnesOrZeros(), combinevXi1ConstantToInteger(), ConstantAddressBlock(), ConstantBuildVector(), ConvertSelectToConcatVector(), CreateStackTemporary(), detectPMADDUBSW(), llvm::SelectionDAGBuilder::EmitBranchForMergedCondition(), llvm::XCoreTargetLowering::EmitInstrWithCustomInserter(), llvm::MipsTargetLowering::EmitInstrWithCustomInserter(), emitNonHSAIntrinsicError(), emitRemovedIntrinsicError(), llvm::ARMSelectionDAGInfo::EmitSpecializedLibcall(), llvm::HexagonSelectionDAGInfo::EmitTargetCodeForMemcpy(), llvm::XCoreSelectionDAGInfo::EmitTargetCodeForMemcpy(), llvm::AArch64SelectionDAGInfo::EmitTargetCodeForMemset(), llvm::X86SelectionDAGInfo::EmitTargetCodeForMemset(), EnsureStackAlignment(), errorUnsupported(), llvm::TargetLowering::expandMUL_LOHI(), llvm::TargetLowering::expandUnalignedLoad(), llvm::TargetLowering::expandUnalignedStore(), extractSubVector(), fail(), findMatchingInlineAsmOperand(), FindMemType(), findUser(), foldBitcastedFPLogic(), FoldConstantArithmetic(), FoldConstantVectorArithmetic(), foldXorTruncShiftIntoCmp(), getAtomicMemcpy(), getAtomicMemmove(), getAtomicMemset(), getBuildPairElt(), getConstant(), getConstantFP(), getCopyFromParts(), getCopyFromPartsVector(), llvm::SelectionDAGBuilder::getCopyFromRegs(), llvm::RegsForValue::getCopyFromRegs(), getCopyToParts(), getCopyToPartsVector(), llvm::RegsForValue::getCopyToRegs(), getDivRemArgList(), getEstimate(), getEVTAlignment(), getExpandedMinMaxOps(), GetFPLibCall(), getFPTernOp(), llvm::ARMTargetLowering::getJumpTableEncoding(), getLoadExtOrTrunc(), getMemcpy(), getMemcpyLoadsAndStores(), getMemmove(), getMemmoveLoadsAndStores(), getMemset(), getMemsetStringVal(), getMemsetValue(), getMOVL(), getPermuteMask(), GetPromotionOpcode(), GetRegistersForValue(), llvm::AVRTargetLowering::getSetCCResultType(), getShiftAmountTyForConstant(), llvm::ARCTargetLowering::getTargetNodeName(), getUniformBase(), llvm::SelectionDAGBuilder::getValueImpl(), hasOnlySelectUsers(), haveEfficientBuildVectorPattern(), llvm::TargetLowering::IncrementMemoryAddress(), llvm::SelectionDAGBuilder::init(), isClampZeroToOne(), llvm::SITargetLowering::isEligibleForTailCallOptimization(), isNegativeOne(), isSETCCorConvertedSETCC(), IsSingleInstrConstant(), IsSmallObject(), isSortedByValueNo(), isTruncateOf(), llvm::SITargetLowering::isTypeDesirableForOp(), isWordAligned(), LowerADDSUBCARRY(), llvm::X86TargetLowering::LowerAsmOperandForConstraint(), LowerAsSplatVectorLoad(), llvm::HexagonTargetLowering::LowerBITCAST(), LowerBUILD_VECTORAsVariablePermute(), lowerBuildVectorAsBroadcast(), llvm::HexagonTargetLowering::LowerCall(), llvm::SITargetLowering::LowerCall(), llvm::SystemZTargetLowering::LowerCall(), llvm::SparcTargetLowering::LowerCall_32(), llvm::SparcTargetLowering::LowerCall_64(), lowerCallResult(), llvm::HexagonTargetLowering::LowerCallResult(), llvm::SITargetLowering::LowerCallResult(), LowerCallResult(), llvm::AMDGPUTargetLowering::LowerCTLZ_CTTZ(), llvm::AMDGPUTargetLowering::LowerDIVREM24(), llvm::AMDGPUTargetLowering::LowerDYNAMIC_STACKALLOC(), llvm::SparcTargetLowering::LowerF128_LibCallArg(), llvm::SparcTargetLowering::LowerF128Compare(), llvm::SparcTargetLowering::LowerF128Op(), llvm::AMDGPUTargetLowering::LowerFCEIL(), llvm::AMDGPUTargetLowering::LowerFFLOOR(), llvm::R600TargetLowering::LowerFormalArguments(), llvm::HexagonTargetLowering::LowerFormalArguments(), llvm::SITargetLowering::LowerFormalArguments(), llvm::SystemZTargetLowering::LowerFormalArguments(), llvm::SparcTargetLowering::LowerFormalArguments_32(), llvm::SparcTargetLowering::LowerFormalArguments_64(), LowerFPOWI(), llvm::AMDGPUTargetLowering::LowerFRINT(), llvm::AMDGPUTargetLowering::LowerFROUND32_16(), llvm::AMDGPUTargetLowering::LowerFROUND64(), LowerFSINCOS(), llvm::AMDGPUTargetLowering::LowerFTRUNC(), llvm::AMDGPUTargetLowering::LowerGlobalAddress(), llvm::AMDGPUTargetLowering::LowerINT_TO_FP32(), LowerInterruptReturn(), LowerLoad(), LowerMSCATTER(), LowerMULH(), llvm::BPFTargetLowering::LowerOperation(), llvm::NVPTXTargetLowering::LowerOperation(), llvm::SelectionDAGBuilder::lowerRangeToAssertZExt(), lowerRegToMasks(), llvm::HexagonTargetLowering::LowerReturn(), llvm::SITargetLowering::LowerReturn(), llvm::SystemZTargetLowering::LowerReturn(), llvm::SparcTargetLowering::LowerReturn_32(), llvm::SparcTargetLowering::LowerReturn_64(), llvm::AMDGPUTargetLowering::LowerSDIVREM(), LowerStore(), llvm::TargetLowering::LowerToTLSEmulatedModel(), LowerToTLSExecModel(), llvm::AMDGPUTargetLowering::LowerUDIVREM64(), LowerUINT_TO_FP_i64(), lowerUINT_TO_FP_vec(), llvm::HexagonTargetLowering::LowerUnalignedLoad(), llvm::AMDGPUTargetLowering::lowerUnhandledCall(), LowerVASTART(), LowerVECTOR_SHUFFLE(), LowerVectorINT_TO_FP(), LowerVSETCC(), llvm::TargetLowering::makeLibCall(), MatchingStackOffset(), matchPMADDWD(), matchPMADDWD_2(), mayTailCallThisCC(), narrowExtractedVectorBinOp(), narrowExtractedVectorLoad(), numVectorEltsOrZero(), parseTexFail(), Passv64i1ArgInRegs(), PerformARMBUILD_VECTORCombine(), PerformBUILD_VECTORCombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), llvm::AMDGPUTargetLowering::PerformDAGCombine(), llvm::PPCTargetLowering::PerformDAGCombine(), performExtendCombine(), PerformInsertEltCombine(), llvm::AMDGPUTargetLowering::performLoadCombine(), performSelectCombine(), llvm::AMDGPUTargetLowering::performStoreCombine(), PerformSTORECombine(), llvm::AMDGPUTargetLowering::performTruncateCombine(), PrepareCall(), printMemOperand(), promoteToConstantPool(), llvm::AArch64TargetLowering::ReconstructShuffle(), reduceBuildVecToShuffleWithZero(), reduceVMULWidth(), ReplaceLoadVector(), llvm::R600TargetLowering::ReplaceNodeResults(), llvm::SITargetLowering::ReplaceNodeResults(), llvm::PPCTargetLowering::ReplaceNodeResults(), llvm::X86TargetLowering::ReplaceNodeResults(), replaceShuffleOfInsert(), scalarizeExtractedBinop(), llvm::TargetLowering::scalarizeVectorStore(), llvm::SelectionDAGBuilder::ShouldEmitAsBranches(), shouldTransformMulToShiftsAddsSubs(), ShrinkLoadReplaceStoreWithStore(), simplifyDivRem(), llvm::TargetLowering::SimplifySetCC(), llvm::TargetLowering::softenSetCCOperands(), splitStores(), truncateVectorWithPACK(), tryFormConcatFromShuffle(), tryToElideArgumentCopy(), unpackF64OnRV32DSoftABI(), UnpackFromArgumentSlot(), llvm::TargetLowering::verifyReturnAddressArgumentIsConstant(), llvm::SelectionDAGBuilder::visitBitTestCase(), llvm::SelectionDAGBuilder::visitBitTestHeader(), llvm::SelectionDAGBuilder::visitJumpTableHeader(), llvm::SelectionDAGBuilder::visitSPDescriptorParent(), llvm::SelectionDAGBuilder::visitSwitchCase(), widenVec(), and XFormVExtractWithShuffleIntoLoad().
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inline |
Definition at line 705 of file SelectionDAG.h.
References llvm::ISD::CopyFromReg, and llvm::MVT::Other.
Referenced by llvm::analyzeArguments(), AnalyzeReturnValues(), llvm::AVRDAGToDAGISel::select< ISD::BRIND >(), llvm::AVRDAGToDAGISel::select< ISD::LOAD >(), CallingConvSupported(), CC_Lanai32_VarArg(), llvm::AArch64TargetLowering::CCAssignFnForReturn(), llvm::ARMTargetLowering::CCAssignFnForReturn(), llvm::AMDGPUTargetLowering::CreateLiveInRegister(), EnsureStackAlignment(), findUnwindDestinations(), llvm::RegsForValue::getCopyFromRegs(), getDivRemArgList(), llvm::HexagonTargetLowering::GetDynamicTLSAddr(), getExtendedControlRegister(), getFRAMEADDR(), llvm::ARMTargetLowering::getJumpTableEncoding(), getMOVL(), getReadPerformanceCounter(), getReadTimeStampCounter(), llvm::ARCTargetLowering::getTargetNodeName(), GetTLSADDR(), llvm::MipsTargetLowering::getTypeForExtReturn(), getUnderlyingArgReg(), getv64i1Argument(), hasOnlySelectUsers(), llvm::ARCTargetLowering::isLegalAddressingMode(), llvm::PPCTargetLowering::isLegalAddressingMode(), llvm::SelectionDAGISel::IsLegalToFold(), llvm::ARMTargetLowering::isReadOnly(), isSortedByValueNo(), llvm::SITargetLowering::isTypeDesirableForOp(), llvm::HexagonTargetLowering::LowerCall(), llvm::SITargetLowering::LowerCall(), llvm::SystemZTargetLowering::LowerCall(), llvm::SparcTargetLowering::LowerCall_32(), llvm::SparcTargetLowering::LowerCall_64(), lowerCallResult(), llvm::HexagonTargetLowering::LowerCallResult(), llvm::SITargetLowering::LowerCallResult(), LowerCallResult(), LowerCMP_SWAP(), llvm::LanaiTargetLowering::LowerDYNAMIC_STACKALLOC(), LowerDYNAMIC_STACKALLOC(), lowerFCOPYSIGN64(), llvm::R600TargetLowering::LowerFormalArguments(), llvm::HexagonTargetLowering::LowerFormalArguments(), llvm::SITargetLowering::LowerFormalArguments(), llvm::SystemZTargetLowering::LowerFormalArguments(), llvm::SparcTargetLowering::LowerFormalArguments_32(), llvm::SparcTargetLowering::LowerFormalArguments_64(), llvm::LanaiTargetLowering::LowerFRAMEADDR(), llvm::MSP430TargetLowering::LowerFRAMEADDR(), llvm::HexagonTargetLowering::LowerFRAMEADDR(), llvm::SparcTargetLowering::LowerGlobalTLSAddress(), LowerINTRINSIC_W_CHAIN(), LowerMUL(), llvm::BPFTargetLowering::LowerOperation(), llvm::RISCVTargetLowering::LowerOperation(), lowerRegToMasks(), llvm::SparcTargetLowering::LowerReturn_32(), llvm::LanaiTargetLowering::LowerRETURNADDR(), llvm::HexagonTargetLowering::LowerRETURNADDR(), LowerRETURNADDR(), llvm::MSP430TargetLowering::LowerSETCC(), LowerToTLSExecModel(), llvm::HexagonTargetLowering::LowerToTLSInitialExecModel(), llvm::HexagonTargetLowering::LowerToTLSLocalExecModel(), LowerVASTART(), LowerVectorINT_TO_FP(), mayTailCallThisCC(), llvm::X86TargetLowering::needsFixedCatchObjects(), Passv64i1ArgInRegs(), performDivRemCombine(), PrepareCall(), recoverFramePointer(), llvm::SparcTargetLowering::ReplaceNodeResults(), llvm::X86TargetLowering::ReplaceNodeResults(), replaceZeroVectorStore(), llvm::HexagonDAGToDAGISel::SelectFrameIndex(), llvm::AVRDAGToDAGISel::SelectInlineAsmMemoryOperand(), unpackF64OnRV32DSoftABI(), UnpackFromArgumentSlot(), unpackFromRegLoc(), llvm::SelectionDAGBuilder::visitBitTestCase(), and llvm::SelectionDAGBuilder::visitJumpTable().
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Definition at line 714 of file SelectionDAG.h.
References llvm::ISD::CopyFromReg, getCondCode(), llvm::SDValue::getNode(), llvm::MVT::Glue, llvm::makeArrayRef(), llvm::BitmaskEnumDetail::Mask(), and llvm::MVT::Other.
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Definition at line 679 of file SelectionDAG.h.
References llvm::ISD::CopyToReg, llvm::SDValue::getValueType(), and llvm::MVT::Other.
Referenced by llvm::analyzeArguments(), AnalyzeReturnValues(), llvm::AVRDAGToDAGISel::select< AVRISD::CALL >(), llvm::AVRDAGToDAGISel::select< ISD::BRIND >(), llvm::AVRDAGToDAGISel::select< ISD::LOAD >(), CallingConvSupported(), CC_Lanai32_VarArg(), llvm::ARMTargetLowering::CCAssignFnForReturn(), llvm::X86SelectionDAGInfo::EmitTargetCodeForMemcpy(), llvm::X86SelectionDAGInfo::EmitTargetCodeForMemset(), findUser(), llvm::RegsForValue::getCopyToRegs(), getDivRemArgList(), getExtendedControlRegister(), llvm::ARMTargetLowering::getJumpTableEncoding(), getMOVL(), llvm::MipsTargetLowering::getOpndList(), getReadPerformanceCounter(), getReductionSDNode(), llvm::ARCTargetLowering::getTargetNodeName(), hasOnlySelectUsers(), llvm::SelectionDAGISel::IsLegalToFold(), isSortedByValueNo(), llvm::SITargetLowering::legalizeTargetIndependentNode(), llvm::HexagonTargetLowering::LowerCall(), llvm::SITargetLowering::LowerCall(), llvm::SystemZTargetLowering::LowerCall(), llvm::SparcTargetLowering::LowerCall_32(), llvm::SparcTargetLowering::LowerCall_64(), lowerCallResult(), llvm::HexagonTargetLowering::LowerCallResult(), LowerCallResult(), llvm::SelectionDAGBuilder::LowerCallTo(), LowerCMP_SWAP(), llvm::LanaiTargetLowering::LowerDYNAMIC_STACKALLOC(), LowerDYNAMIC_STACKALLOC(), llvm::HexagonTargetLowering::LowerEH_RETURN(), lowerFCOPYSIGN64(), llvm::SparcTargetLowering::LowerFormalArguments_32(), llvm::SparcTargetLowering::LowerGlobalTLSAddress(), LowerInterruptReturn(), llvm::BPFTargetLowering::LowerOperation(), llvm::HexagonTargetLowering::LowerReturn(), llvm::SITargetLowering::LowerReturn(), llvm::SystemZTargetLowering::LowerReturn(), llvm::SparcTargetLowering::LowerReturn_32(), llvm::SparcTargetLowering::LowerReturn_64(), LowerSETCCCARRY(), llvm::HexagonTargetLowering::LowerToTLSGeneralDynamicModel(), LowerToTLSGeneralDynamicModel32(), LowerToTLSLocalDynamicModel(), mayTailCallThisCC(), llvm::X86TargetLowering::needsFixedCatchObjects(), Passv64i1ArgInRegs(), llvm::ARMTargetLowering::PerformCMOVCombine(), PrepareCall(), llvm::X86TargetLowering::ReplaceNodeResults(), llvm::SelectionDAGISel::SelectCodeCommon(), llvm::AVRDAGToDAGISel::SelectInlineAsmMemoryOperand(), unpackF64OnRV32DSoftABI(), UnpackFromArgumentSlot(), llvm::SelectionDAGBuilder::visitBitTestHeader(), and llvm::SelectionDAGBuilder::visitJumpTableHeader().
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Definition at line 688 of file SelectionDAG.h.
References llvm::ISD::CopyToReg, llvm::SDValue::getNode(), llvm::SDValue::getValueType(), llvm::MVT::Glue, llvm::makeArrayRef(), and llvm::MVT::Other.
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Definition at line 697 of file SelectionDAG.h.
References llvm::ISD::CopyToReg, llvm::SDValue::getNode(), llvm::MVT::Glue, llvm::makeArrayRef(), N, llvm::MVT::Other, and Reg.
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Definition at line 401 of file SelectionDAG.h.
References llvm::MachineFunction::getDataLayout().
Referenced by AddCombineBUILD_VECTORToVPADDL(), AddCombineToVPADD(), AddCombineVUZPToVPADDL(), addShuffleForVecExtend(), addStackMapLiveVars(), llvm::analyzeArguments(), AnalyzeReturnValues(), llvm::AVRDAGToDAGISel::select< ISD::FrameIndex >(), llvm::SparcTargetLowering::bitcastConstantFPToInt(), BuildExactSDIV(), buildPCRelGlobalAddress(), llvm::TargetLowering::BuildSDIV(), llvm::TargetLowering::BuildUDIV(), calculateByteProvider(), CallingConvSupported(), canFoldInAddressingMode(), CC_Lanai32_VarArg(), llvm::AArch64TargetLowering::CCAssignFnForReturn(), llvm::ARMTargetLowering::CCAssignFnForReturn(), CollectOpsToWiden(), combineBVOfVecSExt(), combineFMinNumFMaxNum(), combineInsertSubvector(), combineLoad(), combineShuffleToVectorExtend(), combineStore(), combineTruncationShuffle(), combineVSelectWithAllOnesOrZeros(), computeKnownBits(), ComputeNumSignBits(), llvm::SelectionDAGBuilder::CopyValueToVirtualRegister(), createGPRPairNode(), CreateStackTemporary(), llvm::XCoreTargetLowering::EmitInstrWithCustomInserter(), llvm::MipsTargetLowering::EmitInstrWithCustomInserter(), llvm::ARMSelectionDAGInfo::EmitSpecializedLibcall(), llvm::X86TargetLowering::emitStackGuardXorFP(), llvm::HexagonSelectionDAGInfo::EmitTargetCodeForMemcpy(), llvm::XCoreSelectionDAGInfo::EmitTargetCodeForMemcpy(), llvm::AArch64SelectionDAGInfo::EmitTargetCodeForMemset(), llvm::X86SelectionDAGInfo::EmitTargetCodeForMemset(), llvm::TargetLowering::expandABS(), ExpandBITCAST(), expandf64Toi32(), llvm::TargetLowering::expandMUL_LOHI(), llvm::TargetLowering::expandUnalignedLoad(), llvm::TargetLowering::expandUnalignedStore(), findMatchingInlineAsmOperand(), findUnwindDestinations(), foldBitcastedFPLogic(), foldXorTruncShiftIntoCmp(), generateEquivalentSub(), getAddressForMemoryInput(), getAtomicMemcpy(), getAtomicMemmove(), getAtomicMemset(), getBuildPairElt(), getConstant(), getConstantPool(), getCopyFromParts(), getCopyFromPartsVector(), llvm::SelectionDAGBuilder::getCopyFromRegs(), getCopyToParts(), getCopyToPartsVector(), getDivRemArgList(), getEstimate(), getEVTAlignment(), getExpandedMinMaxOps(), GetExponent(), GetFPLibCall(), getFPTernOp(), llvm::SelectionDAGBuilder::getFrameIndexTy(), getGlobalAddress(), llvm::MipsDAGToDAGISel::getGlobalBaseReg(), getIntPtrConstant(), llvm::XCoreTargetLowering::getJumpTableEncoding(), llvm::ARMTargetLowering::getJumpTableEncoding(), getLimitedPrecisionExp2(), getLoadExtOrTrunc(), getLoadStackGuard(), getMemCmpLoad(), getMemcpy(), getMemcpyLoadsAndStores(), getMemmove(), getMemmoveLoadsAndStores(), getMemset(), getMemsetStringVal(), getMOVL(), getNextIntArgReg(), llvm::X86TargetLowering::getPICJumpTableRelocBase(), llvm::PPCTargetLowering::getPICJumpTableRelocBase(), llvm::TargetLowering::getPICJumpTableRelocBase(), llvm::PPCTargetLowering::getPICJumpTableRelocBaseExpr(), getPPCf128HiElementSelector(), getReductionSDNode(), llvm::X86TargetLowering::getReturnAddressFrameIndex(), llvm::AVRTargetLowering::getSetCCResultType(), getShiftAmountOperand(), getShiftAmountTyForConstant(), getSymbolFunctionGlobalAddress(), llvm::ARCTargetLowering::getTargetNodeName(), llvm::MipsTargetLowering::getTypeForExtReturn(), getUnderlyingArgReg(), getUniformBase(), llvm::SelectionDAGBuilder::getValueImpl(), getVectorCompareInfo(), llvm::PPC::getVSPLTImmediate(), hasOnlySelectUsers(), haveEfficientBuildVectorPattern(), llvm::SelectionDAGBuilder::init(), llvm::intCCToAVRCC(), isBLACompatibleAddress(), isExtendedBUILD_VECTOR(), isNEONModifiedImm(), IsPredicateKnownToFail(), llvm::ARMTargetLowering::isReadOnly(), isSETCCorConvertedSETCC(), IsSmallObject(), isSortedByValueNo(), isTargetConstant(), isTruncateOf(), llvm::SITargetLowering::isTypeDesirableForOp(), isVectorReductionOp(), llvm::PPC::isVMRGEOShuffleMask(), llvm::PPC::isVMRGHShuffleMask(), llvm::PPC::isVMRGLShuffleMask(), llvm::PPC::isVPKUDUMShuffleMask(), llvm::PPC::isVPKUHUMShuffleMask(), llvm::PPC::isVPKUWUMShuffleMask(), llvm::PPC::isVSLDOIShuffleMask(), isWordAligned(), LowerADDSUBCARRY(), LowerADJUST_TRAMPOLINE(), llvm::MSP430TargetLowering::LowerBlockAddress(), llvm::HexagonTargetLowering::LowerBlockAddress(), LowerBUILD_VECTORAsVariablePermute(), lowerBuildVectorAsBroadcast(), llvm::NVPTXTargetLowering::LowerCall(), llvm::SparcTargetLowering::LowerCall_32(), llvm::SparcTargetLowering::LowerCall_64(), LowerCallResult(), llvm::SelectionDAGBuilder::LowerCallTo(), llvm::TargetLowering::LowerCallTo(), llvm::LanaiTargetLowering::LowerConstantPool(), llvm::AMDGPUTargetLowering::LowerCTLZ_CTTZ(), LowerCTPOP(), llvm::AMDGPUTargetLowering::LowerDIVREM24(), llvm::HexagonTargetLowering::LowerEH_RETURN(), llvm::MSP430TargetLowering::LowerExternalSymbol(), LowerEXTRACT_SUBVECTOR(), llvm::SparcTargetLowering::LowerF128_LibCallArg(), llvm::SparcTargetLowering::LowerF128Compare(), llvm::SparcTargetLowering::LowerF128Op(), LowerF64Op(), llvm::AMDGPUTargetLowering::LowerFCEIL(), llvm::AMDGPUTargetLowering::LowerFFLOOR(), llvm::SystemZTargetLowering::LowerFormalArguments(), llvm::NVPTXTargetLowering::LowerFormalArguments(), llvm::SparcTargetLowering::LowerFormalArguments_32(), LowerFPOWI(), llvm::AMDGPUTargetLowering::LowerFRINT(), llvm::AMDGPUTargetLowering::LowerFROUND32_16(), llvm::AMDGPUTargetLowering::LowerFROUND64(), LowerFSINCOS(), llvm::AMDGPUTargetLowering::LowerFTRUNC(), llvm::HexagonTargetLowering::LowerGLOBAL_OFFSET_TABLE(), llvm::LanaiTargetLowering::LowerGlobalAddress(), llvm::MSP430TargetLowering::LowerGlobalAddress(), llvm::AMDGPUTargetLowering::LowerGlobalAddress(), llvm::HexagonTargetLowering::LowerGLOBALADDRESS(), llvm::NVPTXTargetLowering::LowerGlobalAddress(), llvm::SparcTargetLowering::LowerGlobalTLSAddress(), llvm::AMDGPUTargetLowering::LowerINT_TO_FP32(), LowerINTRINSIC_W_CHAIN(), llvm::SparcTargetLowering::LowerINTRINSIC_WO_CHAIN(), llvm::LanaiTargetLowering::LowerJumpTable(), llvm::MSP430TargetLowering::LowerJumpTable(), LowerLoad(), LowerMemOpCallTo(), lowerMSABitClearImm(), LowerMUL(), LowerMULH(), llvm::R600TargetLowering::LowerOperation(), llvm::NVPTXTargetLowering::LowerOperation(), llvm::NVPTXTargetLowering::LowerReturn(), llvm::SparcTargetLowering::LowerReturn_32(), llvm::MSP430TargetLowering::LowerRETURNADDR(), LowerRETURNADDR(), llvm::TargetLowering::LowerToTLSEmulatedModel(), LowerToTLSExecModel(), llvm::HexagonTargetLowering::LowerToTLSGeneralDynamicModel(), llvm::HexagonTargetLowering::LowerToTLSInitialExecModel(), llvm::HexagonTargetLowering::LowerToTLSLocalExecModel(), LowerUINT_TO_FP_i64(), lowerUINT_TO_FP_vec(), llvm::HexagonTargetLowering::LowerUnalignedLoad(), llvm::LanaiTargetLowering::LowerVASTART(), llvm::MSP430TargetLowering::LowerVASTART(), LowerVASTART(), LowerVectorINT_TO_FP(), LowerWRITE_REGISTER(), llvm::SparcTargetLowering::makeAddress(), llvm::TargetLowering::makeLibCall(), mapWasmLandingPadIndex(), mayTailCallThisCC(), narrowExtractedVectorLoad(), llvm::X86TargetLowering::needsFixedCatchObjects(), numVectorEltsOrZero(), Passv64i1ArgInRegs(), llvm::PPCTargetLowering::PerformDAGCombine(), PerformSTORECombine(), llvm::AMDGPUTargetLowering::performTruncateCombine(), PerformVMOVRRDCombine(), pickOpcodeForVT(), PrepareCall(), promoteToConstantPool(), recoverFramePointer(), reduceBuildVecToShuffleWithZero(), ReplaceCMP_SWAP_128Results(), ReplaceCMP_SWAP_64Results(), ReplaceLoadVector(), llvm::R600TargetLowering::ReplaceNodeResults(), llvm::PPCTargetLowering::ReplaceNodeResults(), replaceShuffleOfInsert(), scalarizeExtractedBinop(), llvm::TargetLowering::scalarizeVectorStore(), llvm::AVRDAGToDAGISel::SelectAddr(), llvm::PPCTargetLowering::SelectAddressRegImm(), llvm::SelectionDAGISel::SelectCodeCommon(), selectI64Imm(), llvm::AVRDAGToDAGISel::selectIndexedLoad(), llvm::AVRDAGToDAGISel::SelectInlineAsmMemoryOperand(), shouldGuaranteeTCO(), ShrinkLoadReplaceStoreWithStore(), llvm::TargetLowering::SimplifyDemandedBits(), llvm::TargetLowering::SimplifyDemandedVectorElts(), simplifyDivRem(), llvm::TargetLowering::SimplifySetCC(), SkipExtensionForVMULL(), llvm::TargetLowering::softenSetCCOperands(), tryToElideArgumentCopy(), unpackF64OnRV32DSoftABI(), UnpackFromArgumentSlot(), unpackFromMemLoc(), llvm::SelectionDAGBuilder::visitBitTestCase(), llvm::SelectionDAGBuilder::visitBitTestHeader(), llvm::SelectionDAGBuilder::visitJumpTable(), llvm::SelectionDAGBuilder::visitJumpTableHeader(), llvm::SelectionDAGBuilder::visitSPDescriptorParent(), widenVec(), WinDBZCheckDenominator(), and XFormVExtractWithShuffleIntoLoad().
SDDbgLabel * SelectionDAG::getDbgLabel | ( | DILabel * | Label, |
const DebugLoc & | DL, | ||
unsigned | O | ||
) |
Creates a SDDbgLabel node.
Definition at line 8004 of file SelectionDAG.cpp.
References assert(), DAGUpdateListener, E, and llvm::SDDbgInfo::getAlloc().
Referenced by getUnderlyingArgReg().
SDDbgValue * SelectionDAG::getDbgValue | ( | DIVariable * | Var, |
DIExpression * | Expr, | ||
SDNode * | N, | ||
unsigned | R, | ||
bool | IsIndirect, | ||
const DebugLoc & | DL, | ||
unsigned | O | ||
) |
Creates a SDDbgValue node.
getDbgValue - Creates a SDDbgValue node.
Definition at line 7859 of file SelectionDAG.cpp.
References assert(), and llvm::SDDbgInfo::getAlloc().
Referenced by getUnderlyingArgReg(), salvageDebugInfo(), and transferDbgValues().
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Get the debug values which reference the given SDNode.
Definition at line 1352 of file SelectionDAG.h.
References llvm::SDDbgInfo::getSDDbgValues().
Referenced by ProcessSDDbgValues(), salvageDebugInfo(), and transferDbgValues().
See if the specified operand can be simplified with the knowledge that only the bits specified by Mask are used.
If so, return the simpler operand, otherwise return a null SDValue.
(This exists alongside SimplifyDemandedBits because GetDemandedBits can simplify nodes with multiple uses more aggressively.)
Definition at line 2066 of file SelectionDAG.cpp.
References llvm::ISD::AND, llvm::ISD::ANY_EXTEND, assert(), llvm::ISD::Constant, llvm::APInt::getActiveBits(), llvm::ConstantSDNode::getAPIntValue(), llvm::APInt::getBitWidth(), getConstant(), llvm::SDValue::getNode(), getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::SDValue::getScalarValueSizeInBits(), llvm::SDValue::getValueType(), llvm::SDNode::hasOneUse(), llvm::isConstOrConstSplat(), llvm::APInt::isSubsetOf(), llvm::BitmaskEnumDetail::Mask(), MaskedValueIsZero(), llvm::ISD::OR, llvm::ISD::SIGN_EXTEND_INREG, llvm::ISD::SRL, llvm::APInt::trunc(), and llvm::ISD::XOR.
Referenced by combineBT(), combinePMULDQ(), isTruncateOf(), ShrinkLoadReplaceStoreWithStore(), and simplifyI24().
Definition at line 1758 of file SelectionDAG.cpp.
References llvm::ISD::EH_LABEL, and getLabelNode().
Referenced by llvm::SelectionDAGBuilder::lowerInvokable().
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Return the token chain corresponding to the entry of the function.
Definition at line 460 of file SelectionDAG.h.
Referenced by llvm::AMDGPUTargetLowering::addTokenForArgument(), AnalyzeReturnValues(), llvm::AVRDAGToDAGISel::select< ISD::BRIND >(), buildPCRelGlobalAddress(), CallingConvSupported(), CC_Lanai32_VarArg(), llvm::ARMTargetLowering::CCAssignFnForReturn(), clear(), llvm::SITargetLowering::copyToM0(), llvm::SelectionDAGBuilder::CopyValueToVirtualRegister(), llvm::AMDGPUTargetLowering::CreateLiveInRegister(), llvm::AMDGPUTargetLowering::CreateLiveInRegisterRaw(), llvm::MipsTargetLowering::EmitInstrWithCustomInserter(), findUnwindDestinations(), llvm::MipsTargetLowering::getAddrLocal(), llvm::SelectionDAGBuilder::getCopyFromRegs(), getDivRemArgList(), getExpandedMinMaxOps(), getFLUSHW(), getFPTernOp(), getFRAMEADDR(), getInputChainForNode(), llvm::ARMTargetLowering::getJumpTableEncoding(), getMemCmpLoad(), getMOVL(), llvm::PPCTargetLowering::getPICJumpTableRelocBaseExpr(), llvm::AVRTargetLowering::getSetCCResultType(), getStackArgumentTokenFactor(), getUnderlyingArgReg(), getUniformBase(), llvm::SelectionDAGBuilder::getValueImpl(), getVectorCompareInfo(), getZeroVector(), HandleMergeInputChains(), hasOnlySelectUsers(), haveEfficientBuildVectorPattern(), llvm::ARCTargetLowering::isLegalAddressingMode(), llvm::PPCTargetLowering::isLegalAddressingMode(), llvm::ARMTargetLowering::isReadOnly(), IsSmallObject(), isSortedByValueNo(), llvm::SITargetLowering::isTypeDesirableForOp(), llvm::AMDGPUTargetLowering::loadStackInputValue(), LowerADDSUBCARRY(), LowerADJUST_TRAMPOLINE(), LowerBUILD_VECTORAsVariablePermute(), lowerBuildVectorAsBroadcast(), LowerEXTRACT_SUBVECTOR(), llvm::SparcTargetLowering::LowerF128Compare(), llvm::SparcTargetLowering::LowerF128Op(), lowerFCOPYSIGN64(), llvm::SITargetLowering::LowerFormalArguments(), llvm::SparcTargetLowering::LowerFormalArguments_32(), LowerFPOWI(), llvm::LanaiTargetLowering::LowerFRAMEADDR(), llvm::MSP430TargetLowering::LowerFRAMEADDR(), llvm::HexagonTargetLowering::LowerFRAMEADDR(), LowerFSINCOS(), llvm::SparcTargetLowering::LowerGlobalTLSAddress(), LowerI64IntToFP_AVX512DQ(), LowerINTRINSIC_W_CHAIN(), LowerMUL(), LowerMULH(), llvm::RISCVTargetLowering::LowerOperation(), llvm::LanaiTargetLowering::LowerRETURNADDR(), llvm::MSP430TargetLowering::LowerRETURNADDR(), llvm::HexagonTargetLowering::LowerRETURNADDR(), LowerRETURNADDR(), llvm::MSP430TargetLowering::LowerSETCC(), LowerSETCCCARRY(), llvm::TargetLowering::LowerToTLSEmulatedModel(), LowerToTLSExecModel(), llvm::HexagonTargetLowering::LowerToTLSGeneralDynamicModel(), LowerToTLSGeneralDynamicModel32(), LowerToTLSGeneralDynamicModel64(), llvm::HexagonTargetLowering::LowerToTLSInitialExecModel(), LowerToTLSLocalDynamicModel(), llvm::HexagonTargetLowering::LowerToTLSLocalExecModel(), LowerUINT_TO_FP_i64(), lowerUINT_TO_FP_vec(), llvm::AMDGPUTargetLowering::lowerUnhandledCall(), LowerVectorINT_TO_FP(), llvm::SparcTargetLowering::makeAddress(), llvm::TargetLowering::makeLibCall(), mayTailCallThisCC(), llvm::X86TargetLowering::needsFixedCatchObjects(), parseTexFail(), llvm::ARMTargetLowering::PerformCMOVCombine(), performDivRemCombine(), PrepareCall(), recoverFramePointer(), llvm::R600TargetLowering::ReplaceNodeResults(), replaceShuffleOfInsert(), replaceZeroVectorStore(), llvm::SelectionDAGISel::SelectCodeCommon(), llvm::HexagonDAGToDAGISel::SelectFrameIndex(), UnpackFromArgumentSlot(), llvm::SelectionDAGBuilder::visitBitTestCase(), llvm::SelectionDAGBuilder::visitSPDescriptorParent(), widenVec(), and WinDBZCheckDenominator().
Compute the default alignment value for the given type.
Definition at line 985 of file SelectionDAG.cpp.
References llvm::PointerType::get(), llvm::DataLayout::getABITypeAlignment(), getContext(), getDataLayout(), llvm::Type::getInt8Ty(), llvm::EVT::getTypeForEVT(), and llvm::MVT::iPTR.
Referenced by getAtomic(), getAtomicCmpSwap(), getLoad(), getMemIntrinsicNode(), getStore(), getTruncStore(), getUniformBase(), and hasOnlySelectUsers().
Definition at line 1498 of file SelectionDAG.cpp.
Referenced by llvm::MipsTargetLowering::EmitInstrWithCustomInserter(), llvm::ARMSelectionDAGInfo::EmitSpecializedLibcall(), llvm::XCoreSelectionDAGInfo::EmitTargetCodeForMemcpy(), llvm::AArch64SelectionDAGInfo::EmitTargetCodeForMemset(), llvm::X86SelectionDAGInfo::EmitTargetCodeForMemset(), getAtomicMemcpy(), getAtomicMemmove(), getAtomicMemset(), getDivRemArgList(), getExpandedMinMaxOps(), llvm::ARMTargetLowering::getJumpTableEncoding(), getMemCmpLoad(), getMemcpy(), getMemmove(), getMemset(), llvm::AVRTargetLowering::getSetCCResultType(), getUnderlyingArgReg(), isWordAligned(), LowerADDSUBCARRY(), llvm::SparcTargetLowering::LowerF128Compare(), llvm::SparcTargetLowering::LowerF128Op(), LowerFPOWI(), LowerFSINCOS(), LowerMULH(), llvm::TargetLowering::LowerToTLSEmulatedModel(), LowerToTLSExecModel(), LowerVectorINT_TO_FP(), and llvm::TargetLowering::makeLibCall().
SDValue SelectionDAG::getExtLoad | ( | ISD::LoadExtType | ExtType, |
const SDLoc & | dl, | ||
EVT | VT, | ||
SDValue | Chain, | ||
SDValue | Ptr, | ||
MachinePointerInfo | PtrInfo, | ||
EVT | MemVT, | ||
unsigned | Alignment = 0 , |
||
MachineMemOperand::Flags | MMOFlags = MachineMemOperand::MONone , |
||
const AAMDNodes & | AAInfo = AAMDNodes() |
||
) |
Definition at line 6690 of file SelectionDAG.cpp.
References getLoad(), getUNDEF(), llvm::SDValue::getValueType(), llvm::RegState::Undef, and llvm::ISD::UNINDEXED.
Referenced by adjustSubwordCmp(), llvm::AArch64TargetLowering::CCAssignFnForReturn(), ConstantAddressBlock(), llvm::TargetLowering::expandUnalignedLoad(), llvm::TargetLowering::expandUnalignedStore(), ExtendUsesToFormExtLoad(), foldExtendedSignBitTest(), FoldIntToFPToInt(), getExpandedMinMaxOps(), GetFPLibCall(), getLoadExtOrTrunc(), getMemcpyLoadsAndStores(), getShiftAmountTyForConstant(), llvm::MipsTargetLowering::getTypeForExtReturn(), getVectorCompareInfo(), isAnyConstantBuildVector(), isTruncateOf(), llvm::SITargetLowering::isTypeDesirableForOp(), isWordAligned(), LowerLoad(), LowerToTLSExecModel(), lowerUINT_TO_FP_vec(), numVectorEltsOrZero(), PrepareCall(), llvm::SparcTargetLowering::ReplaceNodeResults(), replaceShuffleOfInsert(), llvm::TargetLowering::scalarizeVectorLoad(), ShrinkLoadReplaceStoreWithStore(), simplifyDivRem(), SkipLoadExtensionForVMULL(), llvm::AMDGPUTargetLowering::SplitVectorLoad(), tryToFoldExtOfExtload(), tryToFoldExtOfLoad(), and unpackFromMemLoc().
SDValue SelectionDAG::getExtLoad | ( | ISD::LoadExtType | ExtType, |
const SDLoc & | dl, | ||
EVT | VT, | ||
SDValue | Chain, | ||
SDValue | Ptr, | ||
EVT | MemVT, | ||
MachineMemOperand * | MMO | ||
) |
Definition at line 6701 of file SelectionDAG.cpp.
References getLoad(), getUNDEF(), llvm::SDValue::getValueType(), llvm::RegState::Undef, and llvm::ISD::UNINDEXED.
Convert Op, which must be of float type, to the float type VT, by either extending or rounding (by truncation).
Definition at line 1094 of file SelectionDAG.cpp.
References llvm::EVT::bitsGT(), llvm::ISD::FP_EXTEND, llvm::ISD::FP_ROUND, getIntPtrConstant(), getNode(), and llvm::SDValue::getValueType().
Referenced by getCopyFromPartsVector(), and LowerUINT_TO_FP_i32().
Definition at line 1365 of file SelectionDAG.cpp.
References llvm::FoldingSetNodeID::AddInteger(), AddNodeIDNode(), E, llvm::ISD::FrameIndex, getVTList(), llvm::None, and llvm::ISD::TargetFrameIndex.
Referenced by llvm::StatepointLoweringState::allocateStackSlot(), llvm::analyzeArguments(), AnalyzeReturnValues(), llvm::X86TargetLowering::BuildFILD(), CalculateTailCallArgDest(), CallingConvSupported(), CC_Lanai32_VarArg(), llvm::AArch64TargetLowering::CCAssignFnForReturn(), CreateStackTemporary(), llvm::MipsTargetLowering::EmitInstrWithCustomInserter(), EmitTailCallStoreFPAndRetAddr(), EmitTailCallStoreRetAddr(), EnsureStackAlignment(), getAddressForMemoryInput(), getMOVL(), getNextIntArgReg(), llvm::MSP430TargetLowering::getReturnAddressFrameIndex(), llvm::X86TargetLowering::getReturnAddressFrameIndex(), llvm::MipsTargetLowering::getTypeForExtReturn(), getUnderlyingArgReg(), llvm::SelectionDAGBuilder::getValueImpl(), getVectorCompareInfo(), haveEfficientBuildVectorPattern(), llvm::intCCToAVRCC(), isSortedByValueNo(), llvm::SITargetLowering::isTypeDesirableForOp(), llvm::AMDGPUTargetLowering::loadStackInputValue(), LowerADDSUBCARRY(), LowerADJUST_TRAMPOLINE(), llvm::SITargetLowering::LowerCall(), llvm::SparcTargetLowering::LowerCall_32(), lowerCallResult(), LowerCallResult(), llvm::TargetLowering::LowerCallTo(), llvm::SparcTargetLowering::LowerF128_LibCallArg(), llvm::SparcTargetLowering::LowerF128Op(), llvm::HexagonTargetLowering::LowerFormalArguments(), llvm::SystemZTargetLowering::LowerFormalArguments(), llvm::SparcTargetLowering::LowerFormalArguments_32(), llvm::SparcTargetLowering::LowerFormalArguments_64(), LowerI64IntToFP_AVX512DQ(), LowerINTRINSIC_W_CHAIN(), llvm::RISCVTargetLowering::LowerOperation(), lowerStatepointMetaArgs(), llvm::MipsTargetLowering::lowerSTORE(), lowerUINT_TO_FP_vec(), llvm::LanaiTargetLowering::LowerVASTART(), llvm::MSP430TargetLowering::LowerVASTART(), llvm::HexagonTargetLowering::LowerVASTART(), LowerVASTART(), mayTailCallThisCC(), PrepareCall(), shouldGuaranteeTCO(), unpackF64OnRV32DSoftABI(), UnpackFromArgumentSlot(), unpackFromMemLoc(), llvm::SelectionDAGBuilder::visitSPDescriptorParent(), and widenVec().
SDDbgValue * SelectionDAG::getFrameIndexDbgValue | ( | DIVariable * | Var, |
DIExpression * | Expr, | ||
unsigned | FI, | ||
bool | IsIndirect, | ||
const DebugLoc & | DL, | ||
unsigned | O | ||
) |
Creates a FrameIndex SDDbgValue node.
FrameIndex.
Definition at line 7879 of file SelectionDAG.cpp.
References assert(), llvm::SDDbgValue::FRAMEIX, and llvm::SDDbgInfo::getAlloc().
Referenced by getUnderlyingArgReg().
Return a GLOBAL_OFFSET_TABLE node. This does not have a useful SDLoc.
Definition at line 857 of file SelectionDAG.h.
References llvm::AMDGPU::HSAMD::Kernel::Arg::Key::Align, llvm::ISD::GLOBAL_OFFSET_TABLE, and Size.
Referenced by llvm::TargetLowering::getPICJumpTableRelocBase(), and llvm::HexagonTargetLowering::LowerGLOBALADDRESS().
SDValue SelectionDAG::getGlobalAddress | ( | const GlobalValue * | GV, |
const SDLoc & | DL, | ||
EVT | VT, | ||
int64_t | offset = 0 , |
||
bool | isTargetGA = false , |
||
unsigned char | TargetFlags = 0 |
||
) |
Definition at line 1332 of file SelectionDAG.cpp.
References llvm::FoldingSetNodeID::AddInteger(), AddNodeIDNode(), llvm::FoldingSetNodeID::AddPointer(), assert(), E, getDataLayout(), llvm::SDLoc::getDebugLoc(), llvm::SDLoc::getIROrder(), llvm::DataLayout::getPointerTypeSizeInBits(), llvm::GlobalValue::getType(), getVTList(), llvm::ISD::GlobalAddress, llvm::ISD::GlobalTLSAddress, llvm::GlobalValue::isThreadLocal(), llvm::None, llvm::SignExtend64(), llvm::ISD::TargetGlobalAddress, and llvm::ISD::TargetGlobalTLSAddress.
Referenced by FoldSymbolOffset(), llvm::XCoreTargetLowering::getJumpTableEncoding(), getSymbolFunctionGlobalAddress(), llvm::SelectionDAGBuilder::getValueImpl(), isWordAligned(), llvm::TargetLowering::LowerToTLSEmulatedModel(), performGlobalAddressCombine(), and tryFoldToZero().
Get graph attributes for a node.
getGraphAttrs - Get graph attributes for a node.
(eg. "color=red".) Used from getNodeAttributes.
Definition at line 194 of file SelectionDAGPrinter.cpp.
References llvm::errs(), and I.
Referenced by llvm::DOTGraphTraits< SelectionDAG * >::getNodeAttributes().
SDValue SelectionDAG::getIndexedLoad | ( | SDValue | OrigLoad, |
const SDLoc & | dl, | ||
SDValue | Base, | ||
SDValue | Offset, | ||
ISD::MemIndexedMode | AM | ||
) |
Definition at line 6709 of file SelectionDAG.cpp.
References assert(), llvm::MemSDNode::getAAInfo(), llvm::MemSDNode::getAlignment(), llvm::MemSDNode::getChain(), llvm::LoadSDNode::getExtensionType(), llvm::MachineMemOperand::getFlags(), getLoad(), llvm::MemSDNode::getMemOperand(), llvm::MemSDNode::getMemoryVT(), llvm::LoadSDNode::getOffset(), llvm::MemSDNode::getPointerInfo(), llvm::SDValue::getValueType(), llvm::SDValue::isUndef(), llvm::ARM_MB::LD, llvm::MachineMemOperand::MODereferenceable, and llvm::MachineMemOperand::MOInvariant.
Referenced by canFoldInAddressingMode(), and getVectorCompareInfo().
SDValue SelectionDAG::getIndexedStore | ( | SDValue | OrigStore, |
const SDLoc & | dl, | ||
SDValue | Base, | ||
SDValue | Offset, | ||
ISD::MemIndexedMode | AM | ||
) |
Definition at line 6842 of file SelectionDAG.cpp.
References llvm::FoldingSetNodeID::AddInteger(), AddNodeIDNode(), assert(), E, llvm::MachinePointerInfo::getAddrSpace(), llvm::MemSDNode::getChain(), llvm::SDLoc::getDebugLoc(), llvm::SDLoc::getIROrder(), llvm::MemSDNode::getMemOperand(), llvm::MemSDNode::getMemoryVT(), llvm::StoreSDNode::getOffset(), llvm::MemSDNode::getPointerInfo(), llvm::EVT::getRawBits(), llvm::MemSDNode::getRawSubclassData(), llvm::StoreSDNode::getValue(), llvm::SDValue::getValueType(), getVTList(), llvm::StoreSDNode::isTruncatingStore(), llvm::SDValue::isUndef(), NewSDValueDbgMsg(), llvm::MVT::Other, llvm::ARM_MB::ST, and llvm::ISD::STORE.
Referenced by canFoldInAddressingMode(), and getVectorCompareInfo().
Definition at line 1272 of file SelectionDAG.cpp.
References getConstant(), getDataLayout(), and llvm::TargetLoweringBase::getPointerTy().
Referenced by addStackMapLiveVars(), llvm::analyzeArguments(), AnalyzeReturnValues(), buildFromShuffleMostly(), CallingConvSupported(), CC_Lanai32_VarArg(), llvm::ARMTargetLowering::CCAssignFnForReturn(), combineBitcast(), combineBVOfVecSExt(), combineCompareEqual(), combineExtractWithShuffle(), combineHorizontalMinMaxResult(), combineInsertSubvector(), combineLoopSADPattern(), combineStore(), combineTargetShuffle(), combineToExtendVectorInReg(), combineVectorTruncationWithPACKUS(), CompactSwizzlableVector(), llvm::X86SelectionDAGInfo::EmitTargetCodeForMemcpy(), llvm::X86SelectionDAGInfo::EmitTargetCodeForMemset(), llvm::PPCTargetLowering::expandVSXStoreForLE(), ExtendToType(), ExtractBitFromMaskVector(), extractSubVector(), foldBitcastedFPLogic(), FoldIntToFPToInt(), getCopyToParts(), getExpandedMinMaxOps(), getFPExtendOrRound(), GetFPLibCall(), getFRAMEADDR(), llvm::ARMTargetLowering::getJumpTableEncoding(), getMaskNode(), getMOVL(), getNextIntArgReg(), getParamsForOneTrueMaskedElt(), GetPromotionOpcode(), llvm::X86TargetLowering::getRegisterByName(), getScalarMaskingNode(), getShiftAmountTyForConstant(), GetSplatValue(), llvm::ARCTargetLowering::getTargetNodeName(), llvm::MipsTargetLowering::getTypeForExtReturn(), insert1BitVector(), InsertBitToMaskVector(), insertSubVector(), llvm::intCCToAVRCC(), isSortedByValueNo(), isTruncWithZeroHighBitsInput(), lower1BitVectorShuffle(), LowerADDSUBCARRY(), lowerAddSubToHorizontalOp(), LowerAVXCONCAT_VECTORS(), LowerBITCAST(), LowerBITREVERSE_XOP(), LowerBUILD_VECTORAsVariablePermute(), LowerBUILD_VECTORvXi1(), LowerBuildVectorAsInsert(), LowerBuildVectorv16i8(), LowerBuildVectorv4x32(), llvm::HexagonTargetLowering::LowerCall(), llvm::SystemZTargetLowering::LowerCall(), llvm::NVPTXTargetLowering::LowerCall(), llvm::SparcTargetLowering::LowerCall_32(), llvm::SparcTargetLowering::LowerCall_64(), LowerCONCAT_VECTORS(), LowerCONCAT_VECTORSvXi1(), llvm::HexagonTargetLowering::LowerEH_RETURN(), LowerEXTRACT_SUBVECTOR(), LowerFABSorFNEG(), LowerFCOPYSIGN(), llvm::SystemZTargetLowering::LowerFormalArguments(), llvm::NVPTXTargetLowering::LowerFormalArguments(), llvm::LanaiTargetLowering::LowerFRAMEADDR(), LowerFSINCOS(), llvm::SparcTargetLowering::LowerGlobalTLSAddress(), lowerI128ToGR128(), LowerI64IntToFP_AVX512DQ(), LowerLoad(), lowerMasksToReg(), LowerMGATHER(), LowerMLOAD(), LowerMULH(), llvm::RISCVTargetLowering::LowerOperation(), lowerRegToMasks(), llvm::LanaiTargetLowering::LowerRETURNADDR(), LowerRETURNADDR(), LowerSDIV(), LowerSIGN_EXTEND_Mask(), llvm::AMDGPUTargetLowering::LowerSINT_TO_FP(), LowerStore(), LowerToTLSExecModel(), LowerTruncateVecI1(), LowerUDIV(), llvm::AMDGPUTargetLowering::LowerUINT_TO_FP(), LowerUINT_TO_FP_i32(), LowerUINT_TO_FP_i64(), lowerUINT_TO_FP_vec(), LowerUMULO_SMULO(), lowerV2X128VectorShuffle(), lowerV4X128VectorShuffle(), LowerVACOPY(), LowerVASTART(), LowerVectorINT_TO_FP(), lowerVectorShuffleWithUndefHalf(), LowerZERO_EXTEND_Mask(), mayTailCallThisCC(), llvm::X86TargetLowering::needsFixedCatchObjects(), llvm::PPCTargetLowering::PerformDAGCombine(), performMADD_MSUBCombine(), PerformSTORECombine(), PrepareCall(), PrepareTailCall(), recoverFramePointer(), reduceVMULWidth(), ReorganizeVector(), ReplaceLoadVector(), llvm::X86TargetLowering::ReplaceNodeResults(), replaceShuffleOfInsert(), shouldGuaranteeTCO(), SplitAndExtendv16i1(), splitAndLowerVectorShuffle(), unpackF64OnRV32DSoftABI(), widenSubVector(), and widenVec().
SDValue SelectionDAG::getJumpTable | ( | int | JTI, |
EVT | VT, | ||
bool | isTarget = false , |
||
unsigned char | TargetFlags = 0 |
||
) |
Definition at line 1380 of file SelectionDAG.cpp.
References llvm::FoldingSetNodeID::AddInteger(), AddNodeIDNode(), assert(), E, getVTList(), llvm::ISD::JumpTable, llvm::None, and llvm::ISD::TargetJumpTable.
Referenced by llvm::SelectionDAGBuilder::visitJumpTable().
SDValue SelectionDAG::getLabelNode | ( | unsigned | Opcode, |
const SDLoc & | dl, | ||
SDValue | Root, | ||
MCSymbol * | Label | ||
) |
Definition at line 1763 of file SelectionDAG.cpp.
References AddNodeIDNode(), llvm::FoldingSetNodeID::AddPointer(), E, llvm::SDLoc::getDebugLoc(), llvm::SDLoc::getIROrder(), getVTList(), and llvm::MVT::Other.
Referenced by getEHLabel(), and getUnderlyingArgReg().
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inline |
Definition at line 405 of file SelectionDAG.h.
Referenced by CanCombineFCOPYSIGN_EXTEND_ROUND().
SDValue SelectionDAG::getLoad | ( | EVT | VT, |
const SDLoc & | dl, | ||
SDValue | Chain, | ||
SDValue | Ptr, | ||
MachinePointerInfo | PtrInfo, | ||
unsigned | Alignment = 0 , |
||
MachineMemOperand::Flags | MMOFlags = MachineMemOperand::MONone , |
||
const AAMDNodes & | AAInfo = AAMDNodes() , |
||
const MDNode * | Ranges = nullptr |
||
) |
Loads are not normal binary operators: their result type is not determined by their operands, and they produce a value AND a token chain.
This function will set the MOLoad flag on MMOFlags, but you can set it if you want. The MOStore flag must not be set.
Definition at line 6673 of file SelectionDAG.cpp.
References getUNDEF(), llvm::SDValue::getValueType(), llvm::ISD::NON_EXTLOAD, llvm::RegState::Undef, and llvm::ISD::UNINDEXED.
Referenced by llvm::analyzeArguments(), AnalyzeReturnValues(), bitcastf32Toi32(), llvm::X86TargetLowering::BuildFILD(), buildPCRelGlobalAddress(), calculateByteProvider(), CalculateTailCallArgDest(), CC_Lanai32_VarArg(), llvm::ARMTargetLowering::CCAssignFnForReturn(), combineBVOfConsecutiveLoads(), combineLoad(), combineMaskedLoadConstantMask(), combineStore(), ConstantAddressBlock(), EltsFromConsecutiveLoads(), llvm::MipsSETargetLowering::EmitInstrWithCustomInserter(), llvm::MipsTargetLowering::EmitInstrWithCustomInserter(), llvm::ARMSelectionDAGInfo::EmitTargetCodeForMemcpy(), EnsureStackAlignment(), expandf64Toi32(), llvm::TargetLowering::expandUnalignedLoad(), llvm::TargetLowering::expandUnalignedStore(), findUser(), foldBitcastedFPLogic(), llvm::MipsTargetLowering::getAddrGlobal(), llvm::MipsTargetLowering::getAddrGlobalLargeGOT(), llvm::MipsTargetLowering::getAddrLocal(), getBuildPairElt(), getExpandedMinMaxOps(), getExtLoad(), GetFPLibCall(), getFRAMEADDR(), getIndexedLoad(), llvm::XCoreTargetLowering::getJumpTableEncoding(), llvm::ARMTargetLowering::getJumpTableEncoding(), getLoad(), getLoadExtOrTrunc(), getMemCmpLoad(), getMemmoveLoadsAndStores(), getMOVL(), llvm::PPCTargetLowering::getPICJumpTableRelocBaseExpr(), GetPromotionOpcode(), llvm::MipsTargetLowering::getTypeForExtReturn(), getUnderlyingArgReg(), getVectorCompareInfo(), hasOnlySelectUsers(), llvm::PPCTargetLowering::isLegalAddressingMode(), llvm::ARMTargetLowering::isReadOnly(), IsSmallObject(), isSortedByValueNo(), isTruncateOf(), llvm::SITargetLowering::isTypeDesirableForOp(), llvm::AMDGPUTargetLowering::loadStackInputValue(), LowerADDSUBCARRY(), LowerADJUST_TRAMPOLINE(), LowerAsSplatVectorLoad(), LowerBUILD_VECTORAsVariablePermute(), lowerBuildVectorAsBroadcast(), llvm::NVPTXTargetLowering::LowerCall(), llvm::SparcTargetLowering::LowerCall_64(), lowerCallResult(), LowerCallResult(), LowerEXTRACT_SUBVECTOR(), LowerF128Load(), llvm::SparcTargetLowering::LowerF128Op(), llvm::R600TargetLowering::LowerFormalArguments(), llvm::HexagonTargetLowering::LowerFormalArguments(), llvm::SystemZTargetLowering::LowerFormalArguments(), llvm::NVPTXTargetLowering::LowerFormalArguments(), llvm::SparcTargetLowering::LowerFormalArguments_32(), llvm::SparcTargetLowering::LowerFormalArguments_64(), llvm::LanaiTargetLowering::LowerFRAMEADDR(), llvm::MSP430TargetLowering::LowerFRAMEADDR(), llvm::HexagonTargetLowering::LowerFRAMEADDR(), LowerINTRINSIC_W_CHAIN(), LowerLoad(), lowerMSALoadIntr(), llvm::RISCVTargetLowering::LowerOperation(), llvm::LanaiTargetLowering::LowerRETURNADDR(), llvm::MSP430TargetLowering::LowerRETURNADDR(), llvm::HexagonTargetLowering::LowerRETURNADDR(), LowerRETURNADDR(), LowerToTLSExecModel(), llvm::HexagonTargetLowering::LowerToTLSInitialExecModel(), LowerTruncateVecI1(), LowerUINT_TO_FP_i64(), lowerUINT_TO_FP_vec(), llvm::HexagonTargetLowering::LowerUnalignedLoad(), LowerVASTART(), LowerVectorINT_TO_FP(), lowerVectorShuffleAsBroadcast(), llvm::SparcTargetLowering::makeAddress(), mayTailCallThisCC(), narrowExtractedVectorLoad(), numVectorEltsOrZero(), llvm::PPCTargetLowering::PerformDAGCombine(), performIntToFpCombine(), llvm::AMDGPUTargetLowering::performLoadCombine(), PrepareCall(), reduceMaskedLoadToScalarLoad(), llvm::R600TargetLowering::ReplaceNodeResults(), llvm::X86TargetLowering::ReplaceNodeResults(), replaceShuffleOfInsert(), shouldGuaranteeTCO(), ShrinkLoadReplaceStoreWithStore(), simplifyDivRem(), llvm::TargetLowering::SimplifySetCC(), SkipLoadExtensionForVMULL(), unpackF64OnRV32DSoftABI(), UnpackFromArgumentSlot(), llvm::SelectionDAGBuilder::visitSPDescriptorParent(), and widenVec().
SDValue SelectionDAG::getLoad | ( | EVT | VT, |
const SDLoc & | dl, | ||
SDValue | Chain, | ||
SDValue | Ptr, | ||
MachineMemOperand * | MMO | ||
) |
Definition at line 6683 of file SelectionDAG.cpp.
References getLoad(), getUNDEF(), llvm::SDValue::getValueType(), llvm::ISD::NON_EXTLOAD, llvm::RegState::Undef, and llvm::ISD::UNINDEXED.
SDValue SelectionDAG::getLoad | ( | ISD::MemIndexedMode | AM, |
ISD::LoadExtType | ExtType, | ||
EVT | VT, | ||
const SDLoc & | dl, | ||
SDValue | Chain, | ||
SDValue | Ptr, | ||
SDValue | Offset, | ||
MachinePointerInfo | PtrInfo, | ||
EVT | MemVT, | ||
unsigned | Alignment = 0 , |
||
MachineMemOperand::Flags | MMOFlags = MachineMemOperand::MONone , |
||
const AAMDNodes & | AAInfo = AAMDNodes() , |
||
const MDNode * | Ranges = nullptr |
||
) |
Definition at line 6599 of file SelectionDAG.cpp.
References assert(), getEVTAlignment(), getLoad(), getMachineFunction(), llvm::MachineFunction::getMachineMemOperand(), llvm::EVT::getStoreSize(), llvm::SDValue::getValueType(), InferPointerInfo(), llvm::PointerUnion< PT1, PT2 >::isNull(), llvm::MachineMemOperand::MOLoad, llvm::MachineMemOperand::MOStore, llvm::MVT::Other, and llvm::MachinePointerInfo::V.
SDValue SelectionDAG::getLoad | ( | ISD::MemIndexedMode | AM, |
ISD::LoadExtType | ExtType, | ||
EVT | VT, | ||
const SDLoc & | dl, | ||
SDValue | Chain, | ||
SDValue | Ptr, | ||
SDValue | Offset, | ||
EVT | MemVT, | ||
MachineMemOperand * | MMO | ||
) |
Definition at line 6624 of file SelectionDAG.cpp.
References llvm::FoldingSetNodeID::AddInteger(), AddNodeIDNode(), assert(), llvm::EVT::bitsLT(), E, llvm::MachinePointerInfo::getAddrSpace(), llvm::SDLoc::getDebugLoc(), llvm::SDLoc::getIROrder(), llvm::MachineMemOperand::getPointerInfo(), llvm::EVT::getRawBits(), llvm::EVT::getScalarType(), llvm::SDValue::getValueType(), llvm::EVT::getVectorNumElements(), getVTList(), Indexed, llvm::EVT::isInteger(), llvm::SDValue::isUndef(), llvm::EVT::isVector(), llvm::ISD::LOAD, NewSDValueDbgMsg(), llvm::ISD::NON_EXTLOAD, llvm::MVT::Other, and llvm::ISD::UNINDEXED.
Create a logical NOT operation as (XOR Val, BooleanOne).
Definition at line 1147 of file SelectionDAG.cpp.
References getBoolConstant(), getNode(), and llvm::ISD::XOR.
Referenced by llvm::HexagonTargetLowering::LowerAddSubCarry().
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inline |
Definition at line 398 of file SelectionDAG.h.
Referenced by llvm::RegsForValue::AddInlineAsmOperands(), llvm::StatepointLoweringState::allocateStackSlot(), llvm::analyzeArguments(), AnalyzeReturnValues(), areCallingConvEligibleForTCO_64SVR4(), llvm::X86TargetLowering::BuildFILD(), buildPCRelGlobalAddress(), llvm::TargetLowering::BuildSDIVPow2(), CalculateTailCallSPDiff(), CallingConvSupported(), CanCombineFCOPYSIGN_EXTEND_ROUND(), llvm::AArch64TargetLowering::canMergeStoresTo(), llvm::X86TargetLowering::canMergeStoresTo(), CC_Lanai32_VarArg(), llvm::AArch64TargetLowering::CCAssignFnForReturn(), llvm::ARMTargetLowering::CCAssignFnForReturn(), combineFMinNumFMaxNum(), combineMul(), combineOr(), combineStore(), llvm::AMDGPUTargetLowering::computeKnownBitsForTargetNode(), ConstantAddressBlock(), ConvertSelectToConcatVector(), llvm::AMDGPUTargetLowering::CreateLiveInRegister(), CreateStackTemporary(), llvm::MipsTargetLowering::EmitInstrWithCustomInserter(), emitNonHSAIntrinsicError(), emitRemovedIntrinsicError(), llvm::ARMSelectionDAGInfo::EmitSpecializedLibcall(), EmitTailCallStoreFPAndRetAddr(), EmitTailCallStoreRetAddr(), llvm::HexagonSelectionDAGInfo::EmitTargetCodeForMemcpy(), llvm::X86SelectionDAGInfo::EmitTargetCodeForMemcpy(), llvm::ARMSelectionDAGInfo::EmitTargetCodeForMemcpy(), llvm::AArch64SelectionDAGInfo::EmitTargetCodeForMemset(), llvm::X86SelectionDAGInfo::EmitTargetCodeForMemset(), EmitTest(), EnsureStackAlignment(), llvm::BaseIndexOffset::equalBaseIndex(), errorUnsupported(), expandf64Toi32(), llvm::X86TargetLowering::expandIndirectJTBranch(), ExpandPowI(), llvm::TargetLowering::expandUnalignedLoad(), llvm::TargetLowering::expandUnalignedStore(), fail(), findMatchingInlineAsmOperand(), llvm::SelectionDAGBuilder::FindMergedConditions(), FindOptimalMemOpLowering(), findUnwindDestinations(), findUser(), fixupFuncForFI(), foldFPToIntToFP(), getAddressForMemoryInput(), llvm::MipsTargetLowering::getAddrLocal(), getAtomic(), getAtomicCmpSwap(), getDivRemArgList(), llvm::HexagonTargetLowering::GetDynamicTLSAddr(), getExpandedMinMaxOps(), getFPTernOp(), getFRAMEADDR(), llvm::MipsTargetLowering::getGlobalReg(), llvm::DOTGraphTraits< SelectionDAG * >::getGraphName(), llvm::XCoreTargetLowering::getJumpTableEncoding(), llvm::ARMTargetLowering::getJumpTableEncoding(), getLoad(), getLoadExtOrTrunc(), getLoadStackGuard(), getMemCmpLoad(), getMemcpyLoadsAndStores(), getMemIntrinsicNode(), getMemmoveLoadsAndStores(), getMemsetStores(), getMOVL(), getNextIntArgReg(), llvm::MipsTargetLowering::getOpndList(), llvm::PPCTargetLowering::getPICJumpTableRelocBaseExpr(), getReductionSDNode(), llvm::X86TargetLowering::getRegisterByName(), GetRegistersForValue(), llvm::MSP430TargetLowering::getReturnAddressFrameIndex(), llvm::X86TargetLowering::getReturnAddressFrameIndex(), llvm::NVPTXTargetLowering::getSqrtEstimate(), getStore(), llvm::ARCTargetLowering::getTargetNodeName(), GetTLSADDR(), getTOCEntry(), getTruncStore(), llvm::MipsTargetLowering::getTypeForExtReturn(), getUnderlyingArgReg(), getUniformBase(), getv64i1Argument(), getVectorCompareInfo(), hasOnlySelectUsers(), hasReturnsTwiceAttr(), haveEfficientBuildVectorPattern(), InferPointerInfo(), InsertBitToMaskVector(), llvm::intCCToAVRCC(), isConsecutiveLSLoc(), llvm::HexagonTargetLowering::IsEligibleForTailCallOptimization(), llvm::SITargetLowering::isEligibleForTailCallOptimization(), llvm::ARCTargetLowering::isLegalAddressingMode(), llvm::PPCTargetLowering::isLegalAddressingMode(), llvm::ARMTargetLowering::isReadOnly(), isSortedByValueNo(), isTargetConstant(), llvm::SITargetLowering::isTypeDesirableForOp(), isXor1OfSetCC(), llvm::SITargetLowering::legalizeTargetIndependentNode(), llvm::AMDGPUTargetLowering::loadStackInputValue(), LowerADDSUBCARRY(), LowerADJUST_TRAMPOLINE(), LowerAndToBT(), LowerAsSplatVectorLoad(), LowerBUILD_VECTORAsVariablePermute(), lowerBuildVectorAsBroadcast(), llvm::HexagonTargetLowering::LowerCall(), llvm::SITargetLowering::LowerCall(), llvm::SystemZTargetLowering::LowerCall(), llvm::SparcTargetLowering::LowerCall_32(), llvm::SparcTargetLowering::LowerCall_64(), lowerCallResult(), llvm::HexagonTargetLowering::LowerCallResult(), llvm::SITargetLowering::LowerCallResult(), LowerCallResult(), llvm::TargetLowering::LowerCallTo(), llvm::AMDGPUTargetLowering::LowerDYNAMIC_STACKALLOC(), LowerDYNAMIC_STACKALLOC(), llvm::HexagonTargetLowering::LowerEH_RETURN(), LowerEXTRACT_SUBVECTOR(), llvm::SparcTargetLowering::LowerF128_LibCallArg(), llvm::SparcTargetLowering::LowerF128Op(), lowerFCOPYSIGN64(), llvm::R600TargetLowering::LowerFormalArguments(), llvm::HexagonTargetLowering::LowerFormalArguments(), llvm::SITargetLowering::LowerFormalArguments(), llvm::SystemZTargetLowering::LowerFormalArguments(), llvm::NVPTXTargetLowering::LowerFormalArguments(), llvm::SparcTargetLowering::LowerFormalArguments_32(), llvm::SparcTargetLowering::LowerFormalArguments_64(), LowerFPOWI(), llvm::LanaiTargetLowering::LowerFRAMEADDR(), llvm::MSP430TargetLowering::LowerFRAMEADDR(), llvm::HexagonTargetLowering::LowerFRAMEADDR(), LowerFunnelShift(), llvm::AMDGPUTargetLowering::LowerGlobalAddress(), llvm::SparcTargetLowering::LowerGlobalTLSAddress(), LowerI64IntToFP_AVX512DQ(), llvm::HexagonTargetLowering::LowerINLINEASM(), LowerInterruptReturn(), LowerINTRINSIC_W_CHAIN(), llvm::SelectionDAGBuilder::lowerInvokable(), LowerMUL(), llvm::R600TargetLowering::LowerOperation(), llvm::BPFTargetLowering::LowerOperation(), llvm::RISCVTargetLowering::LowerOperation(), llvm::SITargetLowering::LowerOperation(), lowerRegToMasks(), llvm::HexagonTargetLowering::LowerReturn(), llvm::SITargetLowering::LowerReturn(), llvm::SystemZTargetLowering::LowerReturn(), llvm::NVPTXTargetLowering::LowerReturn(), llvm::SparcTargetLowering::LowerReturn_32(), llvm::SparcTargetLowering::LowerReturn_64(), llvm::LanaiTargetLowering::LowerRETURNADDR(), llvm::MSP430TargetLowering::LowerRETURNADDR(), llvm::HexagonTargetLowering::LowerRETURNADDR(), LowerRETURNADDR(), llvm::MipsTargetLowering::lowerSTORE(), llvm::TargetLowering::LowerToTLSEmulatedModel(), LowerToTLSExecModel(), LowerToTLSLocalDynamicModel(), LowerUINT_TO_FP_i64(), lowerUINT_TO_FP_vec(), llvm::HexagonTargetLowering::LowerUnalignedLoad(), llvm::AMDGPUTargetLowering::lowerUnhandledCall(), LowerVACOPY(), llvm::LanaiTargetLowering::LowerVASTART(), llvm::MSP430TargetLowering::LowerVASTART(), llvm::HexagonTargetLowering::LowerVASTART(), LowerVASTART(), LowerVectorINT_TO_FP(), lowerVectorShuffleAsBroadcast(), LowerWRITE_REGISTER(), llvm::SparcTargetLowering::makeAddress(), MarkEHGuard(), MarkEHRegistrationNode(), MatchingStackOffset(), mayTailCallThisCC(), narrowExtractedVectorLoad(), llvm::X86TargetLowering::needsFixedCatchObjects(), parseTexFail(), Passv64i1ArgInRegs(), PerformADDCombineWithOperands(), performBRCONDCombine(), llvm::PPCTargetLowering::PerformDAGCombine(), performXorCombine(), PrepareCall(), printMemOperand(), promoteToConstantPool(), recoverFramePointer(), reduceVMULWidth(), llvm::X86TargetLowering::ReplaceNodeResults(), replaceShuffleOfInsert(), llvm::TargetLowering::CallLoweringInfo::setLibCallee(), setUsesTOCBasePtr(), shouldGuaranteeTCO(), shouldUseHorizontalOp(), ShrinkLoadReplaceStoreWithStore(), simplifyDivRem(), spillIncomingStatepointValue(), splitStores(), llvm::AMDGPUTargetLowering::storeStackInputValue(), StoreTailCallArgumentsToStackSlot(), llvm::X86InstrInfo::unfoldMemoryOperand(), unpackF64OnRV32DSoftABI(), UnpackFromArgumentSlot(), unpackFromMemLoc(), unpackFromRegLoc(), llvm::SelectionDAGBuilder::visitSPDescriptorParent(), and widenVec().
MachineSDNode * SelectionDAG::getMachineNode | ( | unsigned | Opcode, |
const SDLoc & | dl, | ||
EVT | VT | ||
) |
These are used for target selectors to create a new node with specified return type(s), MachineInstr opcode, and operands.
getMachineNode - These are used for target selectors to create a new node with specified return type(s), MachineInstr opcode, and operands.
Note that getMachineNode returns the resultant node. If there is already a node of the specified opcode and operands, it returns that node instead of the current one.
Definition at line 7704 of file SelectionDAG.cpp.
References getVTList(), and llvm::None.
Referenced by addStackMapLiveVars(), llvm::AVRDAGToDAGISel::select< AVRISD::CALL >(), llvm::AVRDAGToDAGISel::select< ISD::BRIND >(), llvm::AVRDAGToDAGISel::select< ISD::LOAD >(), llvm::AVRDAGToDAGISel::select< ISD::STORE >(), llvm::SITargetLowering::buildRSRC(), buildSMovImm32(), CallingConvSupported(), canLowerToLDG(), llvm::SITargetLowering::copyToM0(), createGPRPairNode(), llvm::HexagonDAGToDAGISel::DetectUseSxtw(), findUser(), getExtendedControlRegister(), getLeftShift(), getMachineNode(), getPrefetchNode(), getPTXCmpMode(), getScatterNode(), getTargetExtractSubreg(), getTargetInsertSubreg(), getUnderlyingArgReg(), getVectorCompareInfo(), isMemOPCandidate(), llvm::SITargetLowering::legalizeTargetIndependentNode(), llvm::HexagonDAGToDAGISel::LoadInstrForLoadIntrinsic(), LowerATOMIC_FENCE(), LowerBITCAST(), LowerF128Load(), LowerF128Store(), LowerF64Op(), lowerI128ToGR128(), LowerMGATHER(), llvm::RISCVTargetLowering::LowerOperation(), llvm::SystemZTargetLowering::LowerOperationWrapper(), mayTailCallThisCC(), optimizeLogicalImm(), parseTexFail(), performBitcastCombine(), pickOpcodeForVT(), ReplaceBITCASTResults(), ReplaceCMP_SWAP_128Results(), ReplaceCMP_SWAP_64Results(), llvm::NVPTXDAGToDAGISel::runOnMachineFunction(), llvm::PPCTargetLowering::SelectAddressRegImm(), llvm::HexagonDAGToDAGISel::SelectAddSubCarry(), llvm::HexagonDAGToDAGISel::SelectBrevLdIntrinsic(), llvm::SelectionDAGISel::SelectCodeCommon(), llvm::HexagonDAGToDAGISel::SelectConstant(), llvm::HexagonDAGToDAGISel::SelectConstantFP(), llvm::HexagonDAGToDAGISel::SelectD2P(), llvm::HexagonDAGToDAGISel::SelectFrameIndex(), selectI64Imm(), selectI64ImmDirect(), selectImm(), llvm::AVRDAGToDAGISel::selectIndexedLoad(), llvm::HexagonDAGToDAGISel::SelectIndexedLoad(), llvm::HexagonDAGToDAGISel::SelectIndexedStore(), llvm::HexagonDAGToDAGISel::SelectNewCircIntrinsic(), llvm::HexagonDAGToDAGISel::SelectP2D(), llvm::HexagonDAGToDAGISel::SelectQ2V(), llvm::HvxSelector::selectRor(), llvm::HexagonDAGToDAGISel::SelectSHL(), llvm::HexagonDAGToDAGISel::SelectV2Q(), llvm::HexagonDAGToDAGISel::SelectVAlign(), llvm::HvxSelector::selectVAlign(), llvm::HexagonDAGToDAGISel::SelectVAlignAddr(), llvm::HexagonTargetLowering::shouldExpandAtomicRMWInIR(), tryBitfieldInsertOpFromOr(), tryBitfieldInsertOpFromOrAndImm(), llvm::X86InstrInfo::unfoldMemoryOperand(), Widen(), and llvm::SITargetLowering::wrapAddr64Rsrc().
MachineSDNode * SelectionDAG::getMachineNode | ( | unsigned | Opcode, |
const SDLoc & | dl, | ||
EVT | VT, | ||
SDValue | Op1 | ||
) |
Definition at line 7710 of file SelectionDAG.cpp.
References getMachineNode(), and getVTList().
MachineSDNode * SelectionDAG::getMachineNode | ( | unsigned | Opcode, |
const SDLoc & | dl, | ||
EVT | VT, | ||
SDValue | Op1, | ||
SDValue | Op2 | ||
) |
Definition at line 7717 of file SelectionDAG.cpp.
References getMachineNode(), and getVTList().
MachineSDNode * SelectionDAG::getMachineNode | ( | unsigned | Opcode, |
const SDLoc & | dl, | ||
EVT | VT, | ||
SDValue | Op1, | ||
SDValue | Op2, | ||
SDValue | Op3 | ||
) |
Definition at line 7724 of file SelectionDAG.cpp.
References getMachineNode(), and getVTList().
MachineSDNode * SelectionDAG::getMachineNode | ( | unsigned | Opcode, |
const SDLoc & | dl, | ||
EVT | VT, | ||
ArrayRef< SDValue > | Ops | ||
) |
Definition at line 7732 of file SelectionDAG.cpp.
References getMachineNode(), and getVTList().
MachineSDNode * SelectionDAG::getMachineNode | ( | unsigned | Opcode, |
const SDLoc & | dl, | ||
EVT | VT1, | ||
EVT | VT2, | ||
SDValue | Op1, | ||
SDValue | Op2 | ||
) |
Definition at line 7738 of file SelectionDAG.cpp.
References getMachineNode(), and getVTList().
MachineSDNode * SelectionDAG::getMachineNode | ( | unsigned | Opcode, |
const SDLoc & | dl, | ||
EVT | VT1, | ||
EVT | VT2, | ||
SDValue | Op1, | ||
SDValue | Op2, | ||
SDValue | Op3 | ||
) |
Definition at line 7746 of file SelectionDAG.cpp.
References getMachineNode(), and getVTList().
MachineSDNode * SelectionDAG::getMachineNode | ( | unsigned | Opcode, |
const SDLoc & | dl, | ||
EVT | VT1, | ||
EVT | VT2, | ||
ArrayRef< SDValue > | Ops | ||
) |
Definition at line 7754 of file SelectionDAG.cpp.
References getMachineNode(), and getVTList().
MachineSDNode * SelectionDAG::getMachineNode | ( | unsigned | Opcode, |
const SDLoc & | dl, | ||
EVT | VT1, | ||
EVT | VT2, | ||
EVT | VT3, | ||
SDValue | Op1, | ||
SDValue | Op2 | ||
) |
Definition at line 7761 of file SelectionDAG.cpp.
References getMachineNode(), and getVTList().
MachineSDNode * SelectionDAG::getMachineNode | ( | unsigned | Opcode, |
const SDLoc & | dl, | ||
EVT | VT1, | ||
EVT | VT2, | ||
EVT | VT3, | ||
SDValue | Op1, | ||
SDValue | Op2, | ||
SDValue | Op3 | ||
) |
Definition at line 7769 of file SelectionDAG.cpp.
References getMachineNode(), and getVTList().
MachineSDNode * SelectionDAG::getMachineNode | ( | unsigned | Opcode, |
const SDLoc & | dl, | ||
EVT | VT1, | ||
EVT | VT2, | ||
EVT | VT3, | ||
ArrayRef< SDValue > | Ops | ||
) |
Definition at line 7778 of file SelectionDAG.cpp.
References getMachineNode(), and getVTList().
MachineSDNode * SelectionDAG::getMachineNode | ( | unsigned | Opcode, |
const SDLoc & | dl, | ||
ArrayRef< EVT > | ResultTys, | ||
ArrayRef< SDValue > | Ops | ||
) |
Definition at line 7785 of file SelectionDAG.cpp.
References getMachineNode(), and getVTList().
MachineSDNode * SelectionDAG::getMachineNode | ( | unsigned | Opcode, |
const SDLoc & | dl, | ||
SDVTList | VTs, | ||
ArrayRef< SDValue > | Ops | ||
) |
Definition at line 7792 of file SelectionDAG.cpp.
References AddNodeIDNode(), E, llvm::SDLoc::getDebugLoc(), llvm::SDLoc::getIROrder(), llvm::MVT::Glue, N, llvm::SDVTList::NumVTs, and llvm::SDVTList::VTs.
SDValue SelectionDAG::getMaskedGather | ( | SDVTList | VTs, |
EVT | VT, | ||
const SDLoc & | dl, | ||
ArrayRef< SDValue > | Ops, | ||
MachineMemOperand * | MMO | ||
) |
Definition at line 6929 of file SelectionDAG.cpp.
References AddNodeIDNode(), assert(), E, llvm::MachinePointerInfo::getAddrSpace(), llvm::SDLoc::getDebugLoc(), llvm::SDLoc::getIROrder(), llvm::MachineMemOperand::getPointerInfo(), llvm::EVT::getRawBits(), llvm::SDNode::getValueType(), llvm::EVT::getVectorNumElements(), llvm::ISD::MGATHER, NewSDValueDbgMsg(), and llvm::ArrayRef< T >::size().
Referenced by CollectOpsToWiden(), ConvertSelectToConcatVector(), getShiftAmountTyForConstant(), getUniformBase(), isSETCCorConvertedSETCC(), and llvm::X86TargetLowering::ReplaceNodeResults().
SDValue SelectionDAG::getMaskedLoad | ( | EVT | VT, |
const SDLoc & | dl, | ||
SDValue | Chain, | ||
SDValue | Ptr, | ||
SDValue | Mask, | ||
SDValue | Src0, | ||
EVT | MemVT, | ||
MachineMemOperand * | MMO, | ||
ISD::LoadExtType | ExtTy, | ||
bool | IsExpanding = false |
||
) |
Definition at line 6870 of file SelectionDAG.cpp.
References llvm::FoldingSetNodeID::AddInteger(), AddNodeIDNode(), E, llvm::MachinePointerInfo::getAddrSpace(), llvm::SDLoc::getDebugLoc(), llvm::SDLoc::getIROrder(), llvm::MachineMemOperand::getPointerInfo(), llvm::EVT::getRawBits(), getVTList(), llvm::BitmaskEnumDetail::Mask(), llvm::ISD::MLOAD, NewSDValueDbgMsg(), and llvm::MVT::Other.
Referenced by CollectOpsToWiden(), combineMaskedLoad(), combineMaskedLoadConstantMask(), ConvertSelectToConcatVector(), getShiftAmountTyForConstant(), getUniformBase(), and LowerMLOAD().
SDValue SelectionDAG::getMaskedScatter | ( | SDVTList | VTs, |
EVT | VT, | ||
const SDLoc & | dl, | ||
ArrayRef< SDValue > | Ops, | ||
MachineMemOperand * | MMO | ||
) |
Definition at line 6969 of file SelectionDAG.cpp.
References AddNodeIDNode(), assert(), E, llvm::MachinePointerInfo::getAddrSpace(), llvm::SDLoc::getDebugLoc(), llvm::SDLoc::getIROrder(), llvm::MachineMemOperand::getPointerInfo(), llvm::EVT::getRawBits(), llvm::SDNode::getValueType(), llvm::EVT::getVectorNumElements(), llvm::ISD::MSCATTER, NewSDValueDbgMsg(), and llvm::ArrayRef< T >::size().
Referenced by ConvertSelectToConcatVector(), getUniformBase(), isSETCCorConvertedSETCC(), and LowerMSCATTER().
SDValue SelectionDAG::getMaskedStore | ( | SDValue | Chain, |
const SDLoc & | dl, | ||
SDValue | Val, | ||
SDValue | Ptr, | ||
SDValue | Mask, | ||
EVT | MemVT, | ||
MachineMemOperand * | MMO, | ||
bool | IsTruncating = false , |
||
bool | IsCompressing = false |
||
) |
Definition at line 6898 of file SelectionDAG.cpp.
References llvm::FoldingSetNodeID::AddInteger(), AddNodeIDNode(), assert(), E, llvm::MachinePointerInfo::getAddrSpace(), llvm::SDLoc::getDebugLoc(), llvm::SDLoc::getIROrder(), llvm::MachineMemOperand::getPointerInfo(), llvm::SDValue::getValueType(), getVTList(), llvm::ISD::MSTORE, NewSDValueDbgMsg(), and llvm::MVT::Other.
Referenced by combineMaskedStore(), ConvertSelectToConcatVector(), getShiftAmountTyForConstant(), hasOnlySelectUsers(), isSETCCorConvertedSETCC(), LowerINTRINSIC_W_CHAIN(), and LowerMSTORE().
Definition at line 1506 of file SelectionDAG.cpp.
Referenced by CallingConvSupported(), getUnderlyingArgReg(), and recoverFramePointer().
Return an MDNodeSDNode which holds an MDNode.
Definition at line 1820 of file SelectionDAG.cpp.
References AddNodeIDNode(), llvm::FoldingSetNodeID::AddPointer(), E, getVTList(), llvm::ISD::MDNODE_SDNODE, llvm::None, and llvm::MVT::Other.
Referenced by findMatchingInlineAsmOperand(), and getUnderlyingArgReg().
Returns sum of the base pointer and offset.
Definition at line 5499 of file SelectionDAG.cpp.
References llvm::ISD::ADD, getConstant(), getNode(), and llvm::SDValue::getValueType().
Referenced by combineLoad(), combineStore(), getMemcpyLoadsAndStores(), getMemmoveLoadsAndStores(), getParamsForOneTrueMaskedElt(), lowerUINT_TO_FP_vec(), llvm::HexagonTargetLowering::LowerUnalignedLoad(), lowerVectorShuffleAsBroadcast(), and narrowExtractedVectorLoad().
SDValue SelectionDAG::getMemcpy | ( | SDValue | Chain, |
const SDLoc & | dl, | ||
SDValue | Dst, | ||
SDValue | Src, | ||
SDValue | Size, | ||
unsigned | Align, | ||
bool | isVol, | ||
bool | AlwaysInline, | ||
bool | isTailCall, | ||
MachinePointerInfo | DstPtrInfo, | ||
MachinePointerInfo | SrcPtrInfo | ||
) |
Definition at line 6047 of file SelectionDAG.cpp.
References llvm::AMDGPU::HSAMD::Kernel::Arg::Key::Align, llvm::AMDGPU::HSAMD::Kernel::Key::Args, assert(), checkAddrSpaceIsValidForLibcall(), llvm::dyn_cast(), llvm::SelectionDAGTargetInfo::EmitTargetCodeForMemcpy(), llvm::MachinePointerInfo::getAddrSpace(), getContext(), getDataLayout(), getExternalSymbol(), llvm::DataLayout::getIntPtrType(), llvm::TargetLoweringBase::getLibcallCallingConv(), llvm::TargetLoweringBase::getLibcallName(), getMemcpyLoadsAndStores(), llvm::SDValue::getNode(), llvm::TargetLoweringBase::getPointerTy(), llvm::EVT::getTypeForEVT(), llvm::SDValue::getValueType(), llvm::ConstantSDNode::getZExtValue(), llvm::ConstantSDNode::isNullValue(), llvm::TargetLowering::LowerCallTo(), llvm::ARMISD::MEMCPY, llvm::TargetLoweringBase::ArgListEntry::Node, llvm::TargetLowering::CallLoweringInfo::setChain(), llvm::TargetLowering::CallLoweringInfo::setDebugLoc(), llvm::TargetLowering::CallLoweringInfo::setLibCallee(), llvm::TargetLowering::CallLoweringInfo::setTailCall(), Size, and llvm::TargetLoweringBase::ArgListEntry::Ty.
Referenced by AnalyzeReturnValues(), CallingConvSupported(), CC_Lanai32_VarArg(), CreateCopyOfByValArgument(), llvm::X86SelectionDAGInfo::EmitTargetCodeForMemcpy(), getMemCmpLoad(), llvm::MipsTargetLowering::getTypeForExtReturn(), getUnderlyingArgReg(), llvm::SITargetLowering::LowerCall(), llvm::SparcTargetLowering::LowerCall_32(), lowerCallResult(), LowerCallResult(), LowerVACOPY(), mayTailCallThisCC(), and unpackF64OnRV32DSoftABI().
SDValue SelectionDAG::getMemIntrinsicNode | ( | unsigned | Opcode, |
const SDLoc & | dl, | ||
SDVTList | VTList, | ||
ArrayRef< SDValue > | Ops, | ||
EVT | MemVT, | ||
MachinePointerInfo | PtrInfo, | ||
unsigned | Align = 0 , |
||
MachineMemOperand::Flags | Flags = MachineMemOperand::MOLoad | MachineMemOperand::MOStore , |
||
unsigned | Size = 0 |
||
) |
Creates a MemIntrinsicNode that may produce a result and takes a list of operands.
Opcode may be INTRINSIC_VOID, INTRINSIC_W_CHAIN, or a target-specific opcode with a value not less than FIRST_TARGET_MEMORY_OPCODE.
Definition at line 6502 of file SelectionDAG.cpp.
References getEVTAlignment(), getMachineFunction(), llvm::MachineFunction::getMachineMemOperand(), and llvm::EVT::getStoreSize().
Referenced by adjustLoadValueTypeImpl(), llvm::X86TargetLowering::BuildFILD(), CombineBaseUpdate(), combineBVOfVecSExt(), CombineVLDDUP(), createLoadLR(), createStoreLR(), EltsFromConsecutiveLoads(), llvm::PPCTargetLowering::expandVSXLoadForLE(), llvm::PPCTargetLowering::expandVSXStoreForLE(), getFPTernOp(), getTOCEntry(), getUnderlyingArgReg(), getUniformBase(), getVectorCompareInfo(), haveEfficientBuildVectorPattern(), LowerADJUST_TRAMPOLINE(), lowerAtomicArithWithLOCK(), llvm::NVPTXTargetLowering::LowerCall(), LowerCMP_SWAP(), llvm::SystemZTargetLowering::LowerOperationWrapper(), llvm::NVPTXTargetLowering::LowerReturn(), lowerUINT_TO_FP_vec(), parseTexFail(), llvm::PPCTargetLowering::PerformDAGCombine(), performNEONPostLDSTCombine(), performPostLD1Combine(), PerformVDUPCombine(), PrepareCall(), ReplaceINTRINSIC_W_CHAIN(), ReplaceLoadVector(), llvm::R600TargetLowering::ReplaceNodeResults(), llvm::X86TargetLowering::ReplaceNodeResults(), and widenVec().
SDValue SelectionDAG::getMemIntrinsicNode | ( | unsigned | Opcode, |
const SDLoc & | dl, | ||
SDVTList | VTList, | ||
ArrayRef< SDValue > | Ops, | ||
EVT | MemVT, | ||
MachineMemOperand * | MMO | ||
) |
Definition at line 6519 of file SelectionDAG.cpp.
References llvm::FoldingSetNodeID::AddInteger(), AddNodeIDNode(), assert(), E, llvm::ISD::FIRST_TARGET_MEMORY_OPCODE, llvm::MachinePointerInfo::getAddrSpace(), llvm::SDLoc::getDebugLoc(), llvm::SDLoc::getIROrder(), llvm::MachineMemOperand::getPointerInfo(), llvm::MVT::Glue, llvm::ISD::INTRINSIC_VOID, llvm::ISD::INTRINSIC_W_CHAIN, llvm::ISD::LIFETIME_END, llvm::ISD::LIFETIME_START, llvm::max(), N, llvm::SDVTList::NumVTs, llvm::ISD::PREFETCH, and llvm::SDVTList::VTs.
SDValue SelectionDAG::getMemmove | ( | SDValue | Chain, |
const SDLoc & | dl, | ||
SDValue | Dst, | ||
SDValue | Src, | ||
SDValue | Size, | ||
unsigned | Align, | ||
bool | isVol, | ||
bool | isTailCall, | ||
MachinePointerInfo | DstPtrInfo, | ||
MachinePointerInfo | SrcPtrInfo | ||
) |
Definition at line 6161 of file SelectionDAG.cpp.
References llvm::AMDGPU::HSAMD::Kernel::Arg::Key::Align, llvm::AMDGPU::HSAMD::Kernel::Key::Args, assert(), checkAddrSpaceIsValidForLibcall(), llvm::dyn_cast(), llvm::SelectionDAGTargetInfo::EmitTargetCodeForMemmove(), llvm::MachinePointerInfo::getAddrSpace(), getContext(), getDataLayout(), getExternalSymbol(), llvm::DataLayout::getIntPtrType(), llvm::TargetLoweringBase::getLibcallCallingConv(), llvm::TargetLoweringBase::getLibcallName(), getMemmoveLoadsAndStores(), llvm::SDValue::getNode(), llvm::TargetLoweringBase::getPointerTy(), llvm::EVT::getTypeForEVT(), llvm::SDValue::getValueType(), llvm::ConstantSDNode::getZExtValue(), llvm::ConstantSDNode::isNullValue(), llvm::TargetLowering::LowerCallTo(), llvm::TargetLoweringBase::ArgListEntry::Node, llvm::TargetLowering::CallLoweringInfo::setChain(), llvm::TargetLowering::CallLoweringInfo::setDebugLoc(), llvm::TargetLowering::CallLoweringInfo::setLibCallee(), llvm::TargetLowering::CallLoweringInfo::setTailCall(), Size, and llvm::TargetLoweringBase::ArgListEntry::Ty.
Referenced by llvm::XCoreTargetLowering::EmitInstrWithCustomInserter(), and getUnderlyingArgReg().
SDValue SelectionDAG::getMemset | ( | SDValue | Chain, |
const SDLoc & | dl, | ||
SDValue | Dst, | ||
SDValue | Src, | ||
SDValue | Size, | ||
unsigned | Align, | ||
bool | isVol, | ||
bool | isTailCall, | ||
MachinePointerInfo | DstPtrInfo | ||
) |
Definition at line 6263 of file SelectionDAG.cpp.
References llvm::AMDGPU::HSAMD::Kernel::Arg::Key::Align, llvm::AMDGPU::HSAMD::Kernel::Key::Args, assert(), checkAddrSpaceIsValidForLibcall(), llvm::dyn_cast(), llvm::SelectionDAGTargetInfo::EmitTargetCodeForMemset(), llvm::MachinePointerInfo::getAddrSpace(), getContext(), getDataLayout(), getExternalSymbol(), llvm::DataLayout::getIntPtrType(), llvm::TargetLoweringBase::getLibcallCallingConv(), llvm::TargetLoweringBase::getLibcallName(), getMemsetStores(), llvm::SDValue::getNode(), llvm::TargetLoweringBase::getPointerTy(), llvm::EVT::getTypeForEVT(), llvm::SDValue::getValueType(), llvm::ConstantSDNode::getZExtValue(), llvm::ConstantSDNode::isNullValue(), llvm::TargetLowering::LowerCallTo(), llvm::TargetLoweringBase::ArgListEntry::Node, llvm::TargetLowering::CallLoweringInfo::setChain(), llvm::TargetLowering::CallLoweringInfo::setDebugLoc(), llvm::TargetLowering::CallLoweringInfo::setLibCallee(), llvm::TargetLowering::CallLoweringInfo::setTailCall(), Size, and llvm::TargetLoweringBase::ArgListEntry::Ty.
Referenced by llvm::X86SelectionDAGInfo::EmitTargetCodeForMemset(), and getUnderlyingArgReg().
Create a MERGE_VALUES node from the given operands.
getMergeValues - Create a MERGE_VALUES node from the given operands.
Definition at line 6491 of file SelectionDAG.cpp.
References getNode(), getVTList(), llvm::ISD::MERGE_VALUES, llvm::SmallVectorTemplateBase< T >::push_back(), llvm::SmallVectorImpl< T >::reserve(), and llvm::ArrayRef< T >::size().
Referenced by adjustLoadValueTypeImpl(), ConstantAddressBlock(), constructRetValue(), ConvertSelectToConcatVector(), llvm::MipsSETargetLowering::EmitInstrWithCustomInserter(), llvm::XCoreTargetLowering::EmitInstrWithCustomInserter(), findMatchingInlineAsmOperand(), findUser(), getDivRemArgList(), getFPTernOp(), llvm::XCoreTargetLowering::getJumpTableEncoding(), getLoadExtOrTrunc(), llvm::SelectionDAGBuilder::getValueImpl(), getVectorCompareInfo(), llvm::SITargetLowering::isTypeDesirableForOp(), isWordAligned(), LowerADDC_ADDE_SUBC_SUBE(), llvm::HexagonTargetLowering::LowerAddSubCarry(), llvm::AMDGPUTargetLowering::LowerDIVREM24(), lowerDSPIntr(), llvm::LanaiTargetLowering::LowerDYNAMIC_STACKALLOC(), llvm::AMDGPUTargetLowering::LowerDYNAMIC_STACKALLOC(), LowerDYNAMIC_STACKALLOC(), LowerF128Load(), lowerFCOPYSIGN64(), LowerINTRINSIC_W_CHAIN(), llvm::MipsTargetLowering::lowerLOAD(), LowerLoad(), LowerMGATHER(), LowerMLOAD(), llvm::NVPTXTargetLowering::LowerOperation(), llvm::SelectionDAGBuilder::lowerRangeToAssertZExt(), llvm::AMDGPUTargetLowering::LowerSDIVREM(), LowerShiftParts(), llvm::LanaiTargetLowering::LowerSHL_PARTS(), llvm::LanaiTargetLowering::LowerSRL_PARTS(), llvm::AMDGPUTargetLowering::LowerUDIVREM(), lowerUINT_TO_FP_vec(), LowerUMULO_SMULO(), llvm::HexagonTargetLowering::LowerUnalignedLoad(), mayTailCallThisCC(), parseTexFail(), llvm::AMDGPUTargetLowering::performLoadCombine(), llvm::AMDGPUTargetLowering::performMulLoHi24Combine(), PrepareCall(), recoverFramePointer(), ReorganizeVector(), llvm::TargetLowering::scalarizeVectorLoad(), llvm::AMDGPUTargetLowering::SplitVectorLoad(), and widenVec().
Gets or creates the specified node.
Definition at line 7066 of file SelectionDAG.cpp.
References llvm::ArrayRef< T >::begin(), llvm::ArrayRef< T >::end(), and llvm::ArrayRef< T >::size().
Referenced by AddCombineBUILD_VECTORToVPADDL(), AddCombineTo64bitMLAL(), AddCombineTo64BitSMLAL16(), AddCombineTo64bitUMAAL(), AddCombineToVPADD(), AddCombineVUZPToVPADDL(), addIPMSequence(), llvm::MipsSETargetLowering::addMSAFloatType(), addRequiredExtensionForVectorMULL(), AddRequiredExtensionForVMULL(), addShuffleForVecExtend(), addStackMapLiveVars(), llvm::AMDGPUTargetLowering::addTokenForArgument(), adjustLoadValueTypeImpl(), llvm::analyzeArguments(), AnalyzeReturnValues(), BuildExactSDIV(), buildFromShuffleMostly(), BuildIntrinsicOp(), buildMergeScalars(), buildPCRelGlobalAddress(), buildScalarToVector(), llvm::TargetLowering::BuildSDIV(), llvm::PPCTargetLowering::BuildSDIVPow2(), llvm::TargetLowering::BuildUDIV(), buildVector(), BuildVSLDOI(), calculateByteProvider(), CallingConvSupported(), CanCombineFCOPYSIGN_EXTEND_ROUND(), canFoldInAddressingMode(), CC_Lanai32_VarArg(), llvm::AArch64TargetLowering::CCAssignFnForReturn(), llvm::ARMTargetLowering::CCAssignFnForReturn(), chainLoadsAndStoresForMemcpy(), checkVSELConstraints(), clampDynamicVectorIndex(), CollectOpsToWiden(), combineAcrossLanesIntrinsic(), combineADC(), combineAdd(), combineAddOrSubToADCOrSBB(), combineADDToADDZE(), combineAddToSUBUS(), combineAnd(), combineAndMaskToShift(), combineAndnp(), CombineANDShift(), combineANDXORWithAllOnesIntoANDNP(), CombineBaseUpdate(), combineBasicSADPattern(), combineBEXTR(), combineBitcast(), combineBitcastvxi1(), combineBrCond(), combineBT(), combineBVOfVecSExt(), combineCastedMaskArithmetic(), combineCCMask(), combineCMov(), combineCMP(), combineCompareEqual(), combineConcatVectorOfExtracts(), combineConcatVectorOfScalars(), combineExtractSubvector(), combineExtractVectorElt(), combineExtractWithShuffle(), combineFaddFsub(), combineFAndFNotToFAndn(), combineFMA(), combineFMADDSUB(), combineFMinFMax(), llvm::AMDGPUTargetLowering::combineFMinMaxLegacy(), combineFMinNumFMaxNum(), combineFneg(), combineHorizontalMinMaxResult(), combineHorizontalPredicateResult(), combineIncDecVector(), combineInsertSubvector(), combineLoad(), combineLogicBlendIntoPBLENDV(), combineLoopMAddPattern(), combineLoopSADPattern(), combineMaskedLoad(), combineMaskedStore(), combineMinNumMaxNum(), combineMOVMSK(), combineMul(), combineMulSpecial(), combineMulToPMADDWD(), combineMulToPMULDQ(), combineOr(), combineOrCmpEqZeroToCtlzSrl(), combineParity(), combinePMULDQ(), combinePMULH(), combineRedundantDWordShuffle(), combineSBB(), combineScalarToVector(), combineSelect(), combineSelectAndUse(), combineSelectOfTwoConstants(), combineSetCC(), combineSext(), combineSextInRegCmov(), combineShiftLeft(), combineShiftRightArithmetic(), combineShiftRightLogical(), combineShuffle(), combineShuffleOfConcatUndef(), combineShuffleToAddSubOrFMAddSub(), combineShuffleToFMAddSub(), combineShuffleToVectorExtend(), combineSignExtendInReg(), combineSIntToFP(), combineStore(), combineSub(), combineSubToSubus(), combineTargetShuffle(), combineToExtendBoolVectorInReg(), combineToExtendCMOV(), combineToExtendVectorInReg(), combineTruncate(), combineTruncatedArithmetic(), combineTruncateWithSat(), combineUIntToFP(), combineVectorCompareAndMaskUnaryOp(), combineVectorPack(), combineVectorShiftImm(), combineVectorSizedSetCCEquality(), combineVectorTruncationWithPACKSS(), combineVectorTruncationWithPACKUS(), CombineVMOVDRRCandidateWithVecOp(), combineVSelectToBLENDV(), combineVSelectWithAllOnesOrZeros(), combineX86ShuffleChain(), combineXor(), combineZext(), CompactSwizzlableVector(), ConstantAddressBlock(), ConstantBuildVector(), constructRetValue(), ConvertBooleanCarryToCarryFlag(), ConvertCarryFlagToBooleanCarry(), convertIntLogicToFPLogic(), convertLocVTToValVT(), ConvertSelectToConcatVector(), convertShiftLeftToScale(), convertValVTToLocVT(), llvm::SITargetLowering::copyToM0(), createCMovFP(), createFPCmp(), createGPRPairNode(), createLoadLR(), createMMXBuildVector(), createPSADBW(), createStoreLR(), createVariablePermute(), detectAVGPattern(), detectPMADDUBSW(), detectUSatPattern(), distributeOpThroughSelect(), emitCLC(), EmitCMP(), emitComparison(), emitConditionalComparison(), llvm::MipsSETargetLowering::EmitInstrWithCustomInserter(), llvm::XCoreTargetLowering::EmitInstrWithCustomInserter(), llvm::MipsTargetLowering::EmitInstrWithCustomInserter(), emitIntrinsicWithCC(), emitIntrinsicWithCCAndChain(), EmitKORTEST(), emitMemMem(), emitSETCC(), llvm::ARMSelectionDAGInfo::EmitSpecializedLibcall(), llvm::SystemZSelectionDAGInfo::EmitTargetCodeForMemchr(), llvm::BPFSelectionDAGInfo::EmitTargetCodeForMemcpy(), llvm::X86SelectionDAGInfo::EmitTargetCodeForMemcpy(), llvm::ARMSelectionDAGInfo::EmitTargetCodeForMemcpy(), llvm::SystemZSelectionDAGInfo::EmitTargetCodeForMemset(), llvm::X86SelectionDAGInfo::EmitTargetCodeForMemset(), llvm::SystemZSelectionDAGInfo::EmitTargetCodeForStrcmp(), llvm::SystemZSelectionDAGInfo::EmitTargetCodeForStrcpy(), llvm::SystemZSelectionDAGInfo::EmitTargetCodeForStrnlen(), EmitTest(), EmitVectorComparison(), EnsureStackAlignment(), Expand64BitShift(), llvm::TargetLowering::expandABS(), ExpandBITCAST(), ExpandBVWithShuffles(), expandExp(), expandExp2(), expandf64Toi32(), ExpandHorizontalBinOp(), llvm::X86TargetLowering::expandIndirectJTBranch(), llvm::TargetLowering::expandIndirectJTBranch(), expandLog(), expandLog10(), expandLog2(), llvm::TargetLowering::expandMUL_LOHI(), expandPow(), ExpandPowI(), ExpandREAD_REGISTER(), llvm::TargetLowering::expandUnalignedLoad(), llvm::TargetLowering::expandUnalignedStore(), llvm::PPCTargetLowering::expandVSXLoadForLE(), llvm::PPCTargetLowering::expandVSXStoreForLE(), ExtendToType(), ExtendUsesToFormExtLoad(), ExtractBitFromMaskVector(), extractF64Exponent(), extractLOHI(), extractShiftForRotate(), extractSubVector(), findMatchingInlineAsmOperand(), findUnwindDestinations(), findUser(), flipBoolean(), foldAddSubBoolOfMaskedVal(), foldAddSubOfSignBit(), foldBitcastedFPLogic(), FoldConstantArithmetic(), FoldConstantVectorArithmetic(), foldExtendedSignBitTest(), foldFPToIntToFP(), foldFreeOpFromSelect(), FoldIntToFPToInt(), foldMaskAndShiftToExtract(), foldMaskAndShiftToScale(), foldMaskedShiftToBEXTR(), foldMaskedShiftToScaledMask(), foldVectorXorShiftIntoCmp(), foldXorTruncShiftIntoCmp(), genConstMult(), generateEquivalentSub(), GeneratePerfectShuffle(), GenerateTBL(), getAArch64Cmp(), getAArch64XALUOOp(), getAbsolute(), llvm::MipsTargetLowering::getAddrGlobal(), llvm::MipsTargetLowering::getAddrGlobalLargeGOT(), llvm::MipsTargetLowering::getAddrGPRel(), llvm::MipsTargetLowering::getAddrLocal(), llvm::MipsTargetLowering::getAddrNonPIC(), llvm::MipsTargetLowering::getAddrNonPICSym64(), getAnyExtOrTrunc(), getAsCarry(), getAsNonOpaqueConstant(), getBitcast(), getBoolExtOrTrunc(), getBuildVectorSplat(), getCCResult(), getConstant(), llvm::SelectionDAGBuilder::getControlRoot(), getCopyFromParts(), getCopyFromPartsVector(), llvm::RegsForValue::getCopyFromRegs(), getCopyToParts(), getCopyToPartsVector(), llvm::RegsForValue::getCopyToRegs(), GetDemandedBits(), getDivRemArgList(), getDUPLANEOp(), llvm::HexagonTargetLowering::GetDynamicTLSAddr(), getEstimate(), getEstimateRefinementSteps(), getExpandedMinMaxOps(), GetExponent(), getExtendedControlRegister(), getExtendInVec(), getFLUSHW(), getFPBinOp(), getFPExtendOrRound(), GetFPLibCall(), getFPTernOp(), getFRAMEADDR(), getGeneralPermuteNode(), llvm::AMDGPUTargetLowering::getHiHalf64(), getInputChainForNode(), llvm::XCoreTargetLowering::getJumpTableEncoding(), llvm::ARMTargetLowering::getJumpTableEncoding(), getLimitedPrecisionExp2(), getLoadExtOrTrunc(), getLogicalNOT(), llvm::AMDGPUTargetLowering::getLoHalf64(), getMad64_32(), getMaskNode(), getMemBasePlusOffset(), getMemCmpLoad(), getMemcpyLoadsAndStores(), getMemmoveLoadsAndStores(), getMemsetStringVal(), getMemsetValue(), getMergeValues(), getMOVL(), getMul24(), GetNegatedExpression(), getNextIntArgReg(), getNode(), getNOT(), getPermuteMask(), getPermuteNode(), llvm::HexagonTargetLowering::getPICJumpTableRelocBase(), llvm::X86TargetLowering::getPICJumpTableRelocBase(), llvm::PPCTargetLowering::getPICJumpTableRelocBase(), llvm::PPCTargetLowering::getPICJumpTableRelocBaseExpr(), getPMOVMSKB(), GetPromotionOpcode(), getReadPerformanceCounter(), getReadTimeStampCounter(), llvm::AMDGPUTargetLowering::getRecipEstimate(), getReductionSDNode(), GetRegistersForValue(), llvm::SelectionDAGBuilder::getRoot(), getScalarMaskingNode(), getSETCC(), llvm::AVRTargetLowering::getSetCCResultType(), getSExtOrTrunc(), getShiftAmountTyForConstant(), GetSignificand(), getSplatConstantFP(), GetSplatValue(), llvm::AMDGPUTargetLowering::getSqrtEstimate(), llvm::NVPTXTargetLowering::getSqrtEstimate(), getStackArgumentTokenFactor(), llvm::BPFTargetLowering::getTargetNodeName(), llvm::ARCTargetLowering::getTargetNodeName(), getTargetVShiftByConstNode(), getTargetVShiftNode(), GetTLSADDR(), getTOCEntry(), llvm::MipsTargetLowering::getTypeForExtReturn(), getUnderlyingArgReg(), getUniformBase(), getv64i1Argument(), getVAArg(), llvm::SelectionDAGBuilder::getValueImpl(), getVectorCompareInfo(), llvm::TargetLowering::getVectorElementPointer(), getVectorMaskingNode(), getVectorShuffle(), getVShift(), getX86XALUOOp(), getZeroExtendInReg(), getZeroVector(), getZExtOrTrunc(), HandleMergeInputChains(), hasOnlySelectUsers(), haveEfficientBuildVectorPattern(), llvm::TargetLowering::IncrementMemoryAddress(), initAccumulator(), insert1BitVector(), InsertBitToMaskVector(), insertSubVector(), llvm::intCCToAVRCC(), isADDADDMUL(), isAddSubZExt(), isAnyConstantBuildVector(), isBooleanFlip(), isBSwapHWordElement(), isClampZeroToOne(), isContractable(), llvm::TargetLowering::isExtendedTrueVal(), isFloatingPointZero(), isFNEG(), isFusableLoadOpStorePattern(), llvm::ARCTargetLowering::isLegalAddressingMode(), llvm::PPCTargetLowering::isLegalAddressingMode(), llvm::SelectionDAGISel::IsLegalToFold(), isLowerSaturatingConditional(), isMemOPCandidate(), isNegativeOne(), isNEONModifiedImm(), llvm::ARMTargetLowering::isReadOnly(), isSETCCorConvertedSETCC(), IsSingleInstrConstant(), isSlicingProfitable(), IsSmallObject(), isSortedByValueNo(), isTargetConstant(), isTruncateOf(), isTruncWithZeroHighBitsInput(), llvm::SITargetLowering::isTypeDesirableForOp(), isVectorReductionOp(), isVShiftRImm(), isWordAligned(), isXor1OfSetCC(), joinDwords(), lower1BitVectorShuffle(), Lower256IntVSETCC(), LowerABS(), LowerADDC_ADDE_SUBC_SUBE(), LowerADDSAT_SUBSAT(), lowerAddSub(), llvm::HexagonTargetLowering::LowerAddSubCarry(), LowerADDSUBCARRY(), lowerAddSubToHorizontalOp(), LowerADJUST_TRAMPOLINE(), LowerAndToBT(), LowerAsSplatVectorLoad(), llvm::HexagonTargetLowering::LowerATOMIC_FENCE(), LowerATOMIC_FENCE(), lowerAtomicArith(), LowerAVXCONCAT_VECTORS(), LowerAVXExtend(), llvm::HexagonTargetLowering::LowerBITCAST(), LowerBITCAST(), LowerBITREVERSE(), LowerBITREVERSE_XOP(), llvm::LanaiTargetLowering::LowerBlockAddress(), llvm::MSP430TargetLowering::LowerBlockAddress(), llvm::HexagonTargetLowering::LowerBlockAddress(), llvm::LanaiTargetLowering::LowerBR_CC(), llvm::MSP430TargetLowering::LowerBR_CC(), LowerBR_CC(), llvm::HexagonTargetLowering::LowerBUILD_VECTOR(), LowerBUILD_VECTORAsVariablePermute(), LowerBUILD_VECTORvXi1(), lowerBuildVectorAsBroadcast(), LowerBuildVectorAsInsert(), lowerBuildVectorToBitOp(), LowerBuildVectorv16i8(), LowerBuildVectorv4x32(), llvm::HexagonTargetLowering::LowerCall(), llvm::SITargetLowering::LowerCall(), llvm::SystemZTargetLowering::LowerCall(), llvm::NVPTXTargetLowering::LowerCall(), llvm::SparcTargetLowering::LowerCall_32(), llvm::SparcTargetLowering::LowerCall_64(), lowerCallResult(), llvm::SITargetLowering::LowerCallResult(), LowerCallResult(), llvm::TargetLowering::lowerCmpEqZeroToCtlzSrl(), llvm::AMDGPUTargetLowering::LowerCONCAT_VECTORS(), llvm::HexagonTargetLowering::LowerCONCAT_VECTORS(), LowerCONCAT_VECTORS(), LowerCONCAT_VECTORSvXi1(), llvm::LanaiTargetLowering::LowerConstantPool(), llvm::HexagonTargetLowering::LowerConstantPool(), LowerCTLZ(), llvm::AMDGPUTargetLowering::LowerCTLZ_CTTZ(), LowerCTPOP(), LowerCTTZ(), llvm::AMDGPUTargetLowering::LowerDIVREM24(), lowerDSPIntr(), llvm::LanaiTargetLowering::LowerDYNAMIC_STACKALLOC(), llvm::HexagonTargetLowering::LowerDYNAMIC_STACKALLOC(), LowerDYNAMIC_STACKALLOC(), llvm::HexagonTargetLowering::LowerEH_RETURN(), LowerEXTEND_VECTOR_INREG(), llvm::MSP430TargetLowering::LowerExternalSymbol(), LowerEXTRACT_SUBVECTOR(), LowerEXTRACT_VECTOR_ELT(), LowerEXTRACT_VECTOR_ELT_SSE4(), llvm::SparcTargetLowering::LowerF128Compare(), LowerF128Load(), LowerF128Store(), LowerF64Op(), LowerFABSorFNEG(), llvm::AMDGPUTargetLowering::LowerFCEIL(), lowerFCMPIntrinsic(), LowerFCOPYSIGN(), lowerFCOPYSIGN32(), lowerFCOPYSIGN64(), llvm::AMDGPUTargetLowering::lowerFEXP(), llvm::AMDGPUTargetLowering::LowerFFLOOR(), LowerFGETSIGN(), llvm::AMDGPUTargetLowering::LowerFLOG(), llvm::AMDGPUTargetLowering::LowerFNEARBYINT(), llvm::HexagonTargetLowering::LowerFormalArguments(), llvm::SITargetLowering::LowerFormalArguments(), llvm::SystemZTargetLowering::LowerFormalArguments(), llvm::NVPTXTargetLowering::LowerFormalArguments(), llvm::SparcTargetLowering::LowerFormalArguments_32(), llvm::SparcTargetLowering::LowerFormalArguments_64(), llvm::AMDGPUTargetLowering::LowerFP64_TO_INT(), LowerFP_EXTEND(), llvm::AMDGPUTargetLowering::LowerFP_TO_FP16(), llvm::AMDGPUTargetLowering::LowerFP_TO_SINT(), LowerFP_TO_SINT(), lowerFP_TO_SINT_STORE(), llvm::AMDGPUTargetLowering::LowerFP_TO_UINT(), LowerFPOWI(), llvm::LanaiTargetLowering::LowerFRAMEADDR(), llvm::AMDGPUTargetLowering::LowerFREM(), llvm::AMDGPUTargetLowering::LowerFRINT(), llvm::AMDGPUTargetLowering::LowerFROUND32_16(), llvm::AMDGPUTargetLowering::LowerFROUND64(), LowerFSINCOS(), llvm::AMDGPUTargetLowering::LowerFTRUNC(), LowerFunnelShift(), llvm::HexagonTargetLowering::LowerGLOBAL_OFFSET_TABLE(), llvm::LanaiTargetLowering::LowerGlobalAddress(), llvm::MSP430TargetLowering::LowerGlobalAddress(), llvm::HexagonTargetLowering::LowerGLOBALADDRESS(), llvm::NVPTXTargetLowering::LowerGlobalAddress(), llvm::SparcTargetLowering::LowerGlobalTLSAddress(), lowerGR128Binary(), lowerGR128ToI128(), LowerHorizontalByteSum(), lowerI128ToGR128(), LowerI64IntToFP_AVX512DQ(), lowerICMPIntrinsic(), llvm::AMDGPUTargetLowering::LowerINT_TO_FP32(), llvm::AMDGPUTargetLowering::LowerINT_TO_FP64(), LowerInterruptReturn(), llvm::HexagonTargetLowering::LowerINTRINSIC_VOID(), LowerINTRINSIC_W_CHAIN(), llvm::LanaiTargetLowering::LowerJumpTable(), llvm::MSP430TargetLowering::LowerJumpTable(), llvm::HexagonTargetLowering::LowerJumpTable(), LowerLabelRef(), llvm::MipsTargetLowering::lowerLOAD(), LowerLoad(), lowerMasksToReg(), LowerMemOpCallTo(), LowerMGATHER(), LowerMINMAX(), LowerMLOAD(), lowerMSABinaryBitImmIntr(), lowerMSABitClear(), lowerMSABitClearImm(), lowerMSACopyIntr(), lowerMSALoadIntr(), lowerMSASplatZExt(), lowerMSAStoreIntr(), LowerMSCATTER(), llvm::LanaiTargetLowering::LowerMUL(), LowerMUL(), lowerMUL_LOHI32(), LowerMULH(), llvm::R600TargetLowering::LowerOperation(), llvm::BPFTargetLowering::LowerOperation(), llvm::RISCVTargetLowering::LowerOperation(), llvm::NVPTXTargetLowering::LowerOperation(), llvm::HexagonTargetLowering::LowerPREFETCH(), LowerPREFETCH(), llvm::SelectionDAGBuilder::lowerRangeToAssertZExt(), llvm::HexagonTargetLowering::LowerREADCYCLECOUNTER(), lowerRegToMasks(), llvm::AMDGPUTargetLowering::LowerReturn(), llvm::HexagonTargetLowering::LowerReturn(), llvm::SITargetLowering::LowerReturn(), llvm::SystemZTargetLowering::LowerReturn(), llvm::NVPTXTargetLowering::LowerReturn(), llvm::SparcTargetLowering::LowerReturn_32(), llvm::SparcTargetLowering::LowerReturn_64(), llvm::LanaiTargetLowering::LowerRETURNADDR(), llvm::MSP430TargetLowering::LowerRETURNADDR(), llvm::HexagonTargetLowering::LowerRETURNADDR(), LowerRETURNADDR(), LowerReverse_VECTOR_SHUFFLEv16i8_v8i16(), LowerRotate(), LowerSCALAR_TO_VECTOR(), LowerScalarImmediateShift(), LowerScalarVariableShift(), LowerSDIV(), LowerSDIV_v4i16(), LowerSDIV_v4i8(), llvm::AMDGPUTargetLowering::LowerSDIVREM(), llvm::LanaiTargetLowering::LowerSELECT_CC(), llvm::MSP430TargetLowering::LowerSELECT_CC(), LowerSELECT_CC(), llvm::LanaiTargetLowering::LowerSETCC(), llvm::MSP430TargetLowering::LowerSETCC(), LowerSETCCCARRY(), LowerShift(), LowerShiftParts(), llvm::MSP430TargetLowering::LowerShifts(), llvm::LanaiTargetLowering::LowerSHL_PARTS(), llvm::MSP430TargetLowering::LowerSIGN_EXTEND(), LowerSIGN_EXTEND(), llvm::AMDGPUTargetLowering::LowerSIGN_EXTEND_INREG(), LowerSIGN_EXTEND_Mask(), llvm::AMDGPUTargetLowering::LowerSINT_TO_FP(), LowerSINT_TO_FP(), llvm::LanaiTargetLowering::LowerSRL_PARTS(), llvm::MipsTargetLowering::lowerSTORE(), LowerSTORE(), LowerStore(), lowerToAddSubOrFMAddSub(), LowerToTLSExecModel(), llvm::HexagonTargetLowering::LowerToTLSGeneralDynamicModel(), LowerToTLSGeneralDynamicModel32(), llvm::HexagonTargetLowering::LowerToTLSInitialExecModel(), LowerToTLSLocalDynamicModel(), llvm::HexagonTargetLowering::LowerToTLSLocalExecModel(), LowerTruncateVecI1(), LowerTruncateVectorStore(), LowerUDIV(), llvm::AMDGPUTargetLowering::LowerUDIVREM(), llvm::AMDGPUTargetLowering::LowerUDIVREM64(), llvm::AMDGPUTargetLowering::LowerUINT_TO_FP(), LowerUINT_TO_FP_i32(), LowerUINT_TO_FP_i64(), lowerUINT_TO_FP_v2i32(), lowerUINT_TO_FP_vec(), lowerUINT_TO_FP_vXi32(), LowerUMULO_SMULO(), llvm::HexagonTargetLowering::LowerUnalignedLoad(), lowerV16F32VectorShuffle(), lowerV16I32VectorShuffle(), lowerV16I8VectorShuffle(), lowerV2F64VectorShuffle(), lowerV2I64VectorShuffle(), lowerV2X128VectorShuffle(), lowerV4F32VectorShuffle(), lowerV4F64VectorShuffle(), lowerV4I32VectorShuffle(), lowerV4I64VectorShuffle(), lowerV4X128VectorShuffle(), lowerV8F32VectorShuffle(), lowerV8F64VectorShuffle(), lowerV8I16GeneralSingleInputVectorShuffle(), lowerV8I32VectorShuffle(), lowerV8I64VectorShuffle(), LowerVASTART(), llvm::HexagonTargetLowering::LowerVECTOR_SHUFFLE(), LowerVECTOR_SHUFFLE(), lowerVECTOR_SHUFFLE_SHF(), lowerVECTOR_SHUFFLE_VSHF(), LowerVECTOR_SHUFFLEv8i8(), LowerVectorAllZeroTest(), LowerVectorCTLZ_AVX512CDI(), LowerVectorCTLZInRegLUT(), LowerVectorCTPOP(), LowerVectorCTPOPInRegLUT(), LowerVectorFP_TO_INT(), LowerVectorINT_TO_FP(), LowerVectorIntUnary(), lowerVectorShuffleAsBitBlend(), lowerVectorShuffleAsBitMask(), lowerVectorShuffleAsBlend(), lowerVectorShuffleAsBlendOfPSHUFBs(), lowerVectorShuffleAsBroadcast(), lowerVectorShuffleAsByteRotate(), lowerVectorShuffleAsByteRotateAndPermute(), lowerVectorShuffleAsElementInsertion(), lowerVectorShuffleAsInsertPS(), lowerVectorShuffleAsPermuteAndUnpack(), lowerVectorShuffleAsRotate(), lowerVectorShuffleAsShift(), lowerVectorShuffleAsSpecificZeroOrAnyExtend(), lowerVectorShuffleAsTruncBroadcast(), lowerVectorShuffleAsUNPCKAndPermute(), lowerVectorShuffleAsZeroOrAnyExtend(), lowerVectorShuffleToEXPAND(), lowerVectorShuffleWithPACK(), lowerVectorShuffleWithPERMV(), lowerVectorShuffleWithPSHUFB(), lowerVectorShuffleWithSHUFPD(), lowerVectorShuffleWithSHUFPS(), lowerVectorShuffleWithSSE4A(), lowerVectorShuffleWithUndefHalf(), lowerVectorShuffleWithUNPCK(), lowerVectorShuffleWithVPMOV(), llvm::HexagonTargetLowering::LowerVSELECT(), lowerVSELECTtoVectorShuffle(), LowerVSETCC(), LowerVSETCCWithSUBUS(), LowerWRITE_REGISTER(), lowerX86CmpEqZeroToCtlzSrl(), lowerX86FPLogicOp(), LowerXALUO(), LowerXOR(), LowerZERO_EXTEND_Mask(), llvm::SparcTargetLowering::makeAddress(), makeEquivalentMemoryOrdering(), llvm::SparcTargetLowering::makeHiLoPair(), matchPMADDWD(), matchPMADDWD_2(), matchRotateSub(), mayTailCallThisCC(), minMaxOpcToMin3Max3Opc(), moveBelowOrigChain(), narrowExtractedVectorBinOp(), narrowExtractedVectorLoad(), llvm::X86TargetLowering::needsFixedCatchObjects(), NegateCC(), numVectorEltsOrZero(), operator!=(), optimizeLogicalImm(), parseTexFail(), partitionShuffleOfConcats(), Passv64i1ArgInRegs(), performADDCombine(), PerformADDCombineWithOperands(), PerformAddcSubcCombine(), PerformAddeSubeCombine(), performAddSubLongCombine(), performANDCombine(), PerformANDCombine(), PerformARMBUILD_VECTORCombine(), llvm::AMDGPUTargetLowering::performAssertSZExtCombine(), PerformBFICombine(), performBitcastCombine(), llvm::ARMTargetLowering::PerformBRCONDCombine(), performBRCONDCombine(), PerformBUILD_VECTORCombine(), llvm::ARMTargetLowering::PerformCMOVCombine(), performCMovFPCombine(), llvm::ARMTargetLowering::PerformCMOVToBFICombine(), performConcatVectorsCombine(), performCONDCombine(), llvm::R600TargetLowering::PerformDAGCombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), llvm::AMDGPUTargetLowering::PerformDAGCombine(), llvm::SITargetLowering::PerformDAGCombine(), llvm::PPCTargetLowering::PerformDAGCombine(), performDivRemCombine(), performDSPShiftCombine(), performExtendCombine(), PerformExtendCombine(), llvm::AMDGPUTargetLowering::performFAbsCombine(), performFDivCombine(), llvm::AMDGPUTargetLowering::performFNegCombine(), performFpToIntCombine(), performGlobalAddressCombine(), PerformInsertEltCombine(), performIntegerAbsCombine(), performIntrinsicCombine(), PerformIntrinsicCombine(), performIntToFpCombine(), llvm::AMDGPUTargetLowering::performLoadCombine(), performMADD_MSUBCombine(), performMulCombine(), PerformMULCombine(), llvm::AMDGPUTargetLowering::performMulhsCombine(), llvm::AMDGPUTargetLowering::performMulhuCombine(), llvm::AMDGPUTargetLowering::performMulLoHi24Combine(), performORCombine(), PerformORCombine(), PerformORCombineToBFI(), PerformORCombineToSMULWBT(), PerformREMCombine(), llvm::AMDGPUTargetLowering::performSelectCombine(), performSELECTCombine(), performSelectCombine(), performSetccAddFolding(), performSETCCCombine(), PerformSETCCCombine(), PerformShiftCombine(), llvm::AMDGPUTargetLowering::performShlCombine(), performSHLCombine(), PerformSHLSimplify(), llvm::AMDGPUTargetLowering::performSraCombine(), performSRACombine(), llvm::AMDGPUTargetLowering::performSrlCombine(), performSRLCombine(), llvm::AMDGPUTargetLowering::performStoreCombine(), PerformSTORECombine(), performTBZCombine(), llvm::AMDGPUTargetLowering::performTruncateCombine(), PerformUMLALCombine(), PerformVCVTCombine(), PerformVDIVCombine(), PerformVDUPLANECombine(), PerformVECTOR_SHUFFLECombine(), performVectorCompareAndMaskUnaryOpCombine(), PerformVMOVDRRCombine(), PerformVMULCombine(), performVSELECTCombine(), performVSelectCombine(), performXORCombine(), performXorCombine(), PrepareCall(), PrepareTailCall(), promoteExtBeforeAdd(), PromoteMaskArithmetic(), promoteToConstantPool(), llvm::AArch64TargetLowering::ReconstructShuffle(), recoverFramePointer(), reduceBuildVecToShuffleWithZero(), reduceMaskedLoadToScalarLoad(), reduceMaskedStoreToScalarStore(), reduceVMULWidth(), ReorganizeVector(), ReplaceAllUsesWith(), ReplaceBITCASTResults(), replaceInChain(), ReplaceINTRINSIC_W_CHAIN(), ReplaceLoadVector(), ReplaceLongIntrinsic(), llvm::R600TargetLowering::ReplaceNodeResults(), llvm::AVRTargetLowering::ReplaceNodeResults(), llvm::XCoreTargetLowering::ReplaceNodeResults(), llvm::SparcTargetLowering::ReplaceNodeResults(), llvm::SITargetLowering::ReplaceNodeResults(), llvm::PPCTargetLowering::ReplaceNodeResults(), llvm::X86TargetLowering::ReplaceNodeResults(), ReplaceREADCYCLECOUNTER(), ReplaceReductionResults(), replaceShuffleOfInsert(), scalarizeExtractedBinop(), llvm::TargetLowering::scalarizeVectorLoad(), llvm::TargetLowering::scalarizeVectorStore(), llvm::HexagonDAGToDAGISel::SelectIntrinsicWOChain(), llvm::SelectionDAGBuilder::ShouldEmitAsBranches(), shouldGuaranteeTCO(), llvm::TargetLowering::ShrinkDemandedConstant(), ShrinkLoadReplaceStoreWithStore(), llvm::TargetLowering::SimplifyDemandedBits(), llvm::X86TargetLowering::SimplifyDemandedBitsForTargetNode(), simplifyDivRem(), simplifyI24(), llvm::TargetLowering::SimplifySetCC(), SkipExtensionForVMULL(), llvm::TargetLowering::softenSetCCOperands(), split256IntArith(), split512IntArith(), llvm::AMDGPUTargetLowering::split64BitValue(), SplitAndExtendv16i1(), splitAndLowerVectorShuffle(), llvm::AMDGPUTargetLowering::splitBinaryBitConstantOpImpl(), llvm::SITargetLowering::splitBinaryVectorOp(), splitInt128(), SplitOpsAndApply(), splitStores(), splitStoreSplat(), llvm::SITargetLowering::splitUnaryVectorOp(), llvm::AMDGPUTargetLowering::SplitVectorLoad(), llvm::AMDGPUTargetLowering::SplitVectorStore(), SplitVSETCC(), stripModuloOnShift(), llvm::ARMTargetLowering::targetShrinkDemandedConstant(), llvm::X86TargetLowering::targetShrinkDemandedConstant(), truncateVecElts(), truncateVectorWithPACK(), tryAdvSIMDModImm16(), tryAdvSIMDModImm32(), tryAdvSIMDModImm321s(), tryAdvSIMDModImm64(), tryAdvSIMDModImm8(), tryAdvSIMDModImmFP(), tryBuildVectorReplicate(), tryCombineCRC32(), tryCombineFixedPointConvert(), tryCombineLongOpWithDup(), tryCombineShiftImm(), tryCombineToBSL(), tryCombineToEXTR(), tryExtendDUPToExtractHigh(), tryFoldToZero(), tryFormConcatFromShuffle(), tryLowerToSLI(), TryMULWIDECombine(), tryToFoldExtendOfConstant(), tryToFoldExtOfLoad(), unpackF64OnRV32DSoftABI(), UnpackFromArgumentSlot(), UnrollVectorShift(), llvm::SelectionDAGBuilder::UpdateSplitBlock(), vectorEltWillFoldAway(), llvm::SelectionDAGBuilder::visitBitTestCase(), llvm::SelectionDAGBuilder::visitBitTestHeader(), visitFMinMax(), llvm::SelectionDAGBuilder::visitJumpTable(), llvm::SelectionDAGBuilder::visitJumpTableHeader(), llvm::SelectionDAGBuilder::visitSPDescriptorParent(), llvm::SelectionDAGBuilder::visitSwitchCase(), widenSubVector(), widenVec(), WidenVector(), willShiftRightEliminate(), WinDBZCheckDenominator(), and XFormVExtractWithShuffleIntoLoad().
SDValue SelectionDAG::getNode | ( | unsigned | Opcode, |
const SDLoc & | DL, | ||
EVT | VT, | ||
ArrayRef< SDValue > | Ops, | ||
const SDNodeFlags | Flags = SDNodeFlags() |
||
) |
Definition at line 7082 of file SelectionDAG.cpp.
References AddNodeIDNode(), assert(), llvm::ISD::BR_CC, llvm::ISD::BUILD_VECTOR, llvm::ISD::CONCAT_VECTORS, E, FoldBUILD_VECTOR(), FoldCONCAT_VECTORS(), llvm::SDLoc::getDebugLoc(), llvm::SDLoc::getIROrder(), getNode(), getValueType(), getVTList(), llvm::MVT::Glue, N, NewSDValueDbgMsg(), llvm::ISD::SELECT_CC, and llvm::ArrayRef< T >::size().
SDValue SelectionDAG::getNode | ( | unsigned | Opcode, |
const SDLoc & | DL, | ||
ArrayRef< EVT > | ResultTys, | ||
ArrayRef< SDValue > | Ops | ||
) |
Definition at line 7148 of file SelectionDAG.cpp.
References getNode(), and getVTList().
SDValue SelectionDAG::getNode | ( | unsigned | Opcode, |
const SDLoc & | DL, | ||
SDVTList | VTList, | ||
ArrayRef< SDValue > | Ops | ||
) |
Definition at line 7153 of file SelectionDAG.cpp.
References AddNodeIDNode(), llvm::ISD::AND, E, llvm::SDLoc::getDebugLoc(), llvm::SDLoc::getIROrder(), getNode(), llvm::MVT::Glue, llvm::MVT::i1, N, NewSDValueDbgMsg(), llvm::SDVTList::NumVTs, llvm::ISD::SHL_PARTS, llvm::ISD::SIGN_EXTEND_INREG, llvm::ISD::SRA_PARTS, llvm::ISD::SRL_PARTS, and llvm::SDVTList::VTs.
Gets or creates the specified node.
Definition at line 4068 of file SelectionDAG.cpp.
References AddNodeIDNode(), E, llvm::SDLoc::getDebugLoc(), llvm::SDLoc::getIROrder(), getVTList(), NewSDValueDbgMsg(), and llvm::None.
SDValue SelectionDAG::getNode | ( | unsigned | Opcode, |
const SDLoc & | DL, | ||
EVT | VT, | ||
SDValue | Operand, | ||
const SDNodeFlags | Flags = SDNodeFlags() |
||
) |
Definition at line 4085 of file SelectionDAG.cpp.
References llvm::ISD::ABS, llvm::APInt::abs(), AddNodeIDNode(), llvm::ISD::ANY_EXTEND, llvm::ISD::ANY_EXTEND_VECTOR_INREG, llvm::lltok::APFloat, assert(), llvm::ISD::BITCAST, llvm::APFloat::bitcastToAPInt(), llvm::ISD::BITREVERSE, llvm::EVT::bitsGT(), llvm::EVT::bitsLE(), llvm::EVT::bitsLT(), llvm::ISD::BSWAP, llvm::ISD::BUILD_VECTOR, llvm::APInt::byteSwap(), C, llvm::APFloat::changeSign(), llvm::APFloat::clearSign(), llvm::ISD::CONCAT_VECTORS, llvm::APFloat::convert(), llvm::APFloat::convertFromAPInt(), llvm::APFloat::convertToInteger(), llvm::APInt::countLeadingZeros(), llvm::APInt::countPopulation(), llvm::APInt::countTrailingZeros(), llvm::ISD::CTLZ, llvm::ISD::CTLZ_ZERO_UNDEF, llvm::ISD::CTPOP, llvm::ISD::CTTZ, llvm::ISD::CTTZ_ZERO_UNDEF, E, EVTToAPFloatSemantics(), llvm::ISD::EXTRACT_VECTOR_ELT, llvm::MVT::f128, llvm::MVT::f16, llvm::MVT::f32, llvm::MVT::f64, llvm::ISD::FABS, llvm::ISD::FCEIL, llvm::ISD::FFLOOR, llvm::ISD::FNEG, FoldBUILD_VECTOR(), FoldConstantVectorArithmetic(), llvm::ISD::FP16_TO_FP, llvm::ISD::FP_EXTEND, llvm::ISD::FP_ROUND, llvm::ISD::FP_TO_FP16, llvm::ISD::FP_TO_SINT, llvm::ISD::FP_TO_UINT, llvm::ISD::FSUB, llvm::ISD::FTRUNC, llvm::APInt::getBitWidth(), getConstant(), getConstantFP(), llvm::SDValue::getConstantOperandVal(), llvm::SDLoc::getDebugLoc(), llvm::SDLoc::getIROrder(), llvm::SDValue::getNode(), getNode(), llvm::APInt::getNullValue(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::EVT::getScalarType(), llvm::EVT::getSizeInBits(), getTarget(), getUNDEF(), llvm::SDValue::getValueSizeInBits(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), getVTList(), llvm::APInt::getZExtValue(), llvm::MVT::Glue, llvm::SDNodeFlags::hasNoSignedZeros(), llvm::MVT::i128, llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i64, llvm::APFloatBase::IEEEdouble(), llvm::APFloatBase::IEEEhalf(), llvm::APFloatBase::IEEEquad(), llvm::APFloatBase::IEEEsingle(), llvm::tgtok::IntVal, llvm::EVT::isFloatingPoint(), llvm::EVT::isInteger(), llvm::SDValue::isUndef(), llvm::EVT::isVector(), LLVM_FALLTHROUGH, llvm_unreachable, llvm::ISD::MERGE_VALUES, N, NewSDValueDbgMsg(), llvm::APFloatBase::opInexact, llvm::APFloatBase::opInvalidOp, llvm::APFloatBase::opOK, llvm::APInt::reverseBits(), llvm::APFloatBase::rmNearestTiesToEven, llvm::APFloatBase::rmTowardNegative, llvm::APFloatBase::rmTowardPositive, llvm::APFloatBase::rmTowardZero, llvm::APFloat::roundToIntegral(), llvm::ISD::SCALAR_TO_VECTOR, llvm::SDNode::setFlags(), llvm::APInt::sextOrTrunc(), llvm::ISD::SIGN_EXTEND, llvm::ISD::SIGN_EXTEND_VECTOR_INREG, llvm::ISD::SINT_TO_FP, llvm::ISD::TokenFactor, transferDbgValues(), llvm::APInt::trunc(), llvm::ISD::TRUNCATE, llvm::ISD::UINT_TO_FP, llvm::ISD::UNDEF, llvm::ISD::ZERO_EXTEND, llvm::ISD::ZERO_EXTEND_VECTOR_INREG, and llvm::APInt::zextOrTrunc().
SDValue SelectionDAG::getNode | ( | unsigned | Opcode, |
const SDLoc & | DL, | ||
EVT | VT, | ||
SDValue | N1, | ||
SDValue | N2, | ||
const SDNodeFlags | Flags = SDNodeFlags() |
||
) |
Definition at line 4758 of file SelectionDAG.cpp.
References llvm::ISD::ADD, llvm::APFloat::add(), AddNodeIDNode(), llvm::ISD::AND, llvm::APInt::ashrInPlace(), assert(), llvm::ISD::AssertSext, llvm::ISD::AssertZext, llvm::EVT::bitsLE(), llvm::ISD::BUILD_PAIR, llvm::ISD::BUILD_VECTOR, C, llvm::ISD::CONCAT_VECTORS, llvm::APFloat::convert(), llvm::APFloat::copySign(), llvm::APFloat::divide(), llvm::dyn_cast(), E, llvm::ISD::EntryToken, EVTToAPFloatSemantics(), llvm::ISD::EXTRACT_ELEMENT, llvm::ISD::EXTRACT_SUBVECTOR, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::ISD::FADD, llvm::ISD::FCOPYSIGN, llvm::ISD::FDIV, llvm::ISD::FMUL, FoldBUILD_VECTOR(), FoldCONCAT_VECTORS(), FoldConstantArithmetic(), llvm::ISD::FP_ROUND, llvm::ISD::FP_ROUND_INREG, llvm::ISD::FREM, llvm::ISD::FSUB, getAllOnesConstant(), getAnyExtOrTrunc(), llvm::ConstantSDNode::getAPIntValue(), llvm::APInt::getBitWidth(), getBuildVector(), getConstant(), getConstantFP(), llvm::SDLoc::getDebugLoc(), llvm::SDLoc::getIROrder(), llvm::APFloat::getNaN(), llvm::SDValue::getNode(), getNode(), llvm::SDValue::getNumOperands(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::EVT::getScalarType(), getSExtOrTrunc(), llvm::SDValue::getSimpleValueType(), llvm::EVT::getSimpleVT(), llvm::EVT::getSizeInBits(), getUNDEF(), llvm::SDValue::getValueSizeInBits(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), getVTList(), llvm::ConstantSDNode::getZExtValue(), llvm::MVT::Glue, llvm::TargetLoweringBase::hasFloatingPointExceptions(), llvm::MVT::i1, llvm::ISD::INSERT_SUBVECTOR, llvm::ISD::INSERT_VECTOR_ELT, llvm::ISD::isBuildVectorOfConstantSDNodes(), llvm::TargetLoweringBase::isCommutativeBinOp(), llvm::EVT::isFloatingPoint(), llvm::EVT::isInteger(), llvm::EVT::isSimple(), llvm::SDValue::isUndef(), llvm::EVT::isVector(), LLVM_FALLTHROUGH, llvm::Log2_32_Ceil(), llvm::APInt::lshr(), llvm::APFloat::mod(), llvm::ISD::MUL, llvm::ISD::MULHS, llvm::ISD::MULHU, llvm::APFloat::multiply(), N, NewSDValueDbgMsg(), llvm::APFloatBase::opDivByZero, llvm::APFloatBase::opInvalidOp, llvm::ISD::OR, llvm::MVT::Other, llvm::SmallVectorTemplateBase< T >::push_back(), llvm::APFloatBase::rmNearestTiesToEven, llvm::ISD::ROTL, llvm::ISD::ROTR, llvm::ISD::SADDSAT, llvm::ISD::SDIV, llvm::SDNode::setFlags(), llvm::ISD::SHL, llvm::ISD::SIGN_EXTEND_INREG, simplifyShift(), llvm::ISD::SMAX, llvm::ISD::SMIN, llvm::ISD::SRA, llvm::ISD::SREM, llvm::ISD::SRL, llvm::ISD::SSUBSAT, llvm::ISD::SUB, llvm::APFloat::subtract(), std::swap(), llvm::ISD::TokenFactor, llvm::APInt::trunc(), llvm::ISD::UADDSAT, llvm::ISD::UDIV, llvm::ISD::UMAX, llvm::ISD::UMIN, llvm::ISD::UREM, llvm::ISD::USUBSAT, llvm::NVPTX::PTXLdStInstCode::V2, and llvm::ISD::XOR.
SDValue SelectionDAG::getNode | ( | unsigned | Opcode, |
const SDLoc & | DL, | ||
EVT | VT, | ||
SDValue | N1, | ||
SDValue | N2, | ||
SDValue | N3, | ||
const SDNodeFlags | Flags = SDNodeFlags() |
||
) |
Definition at line 5248 of file SelectionDAG.cpp.
References AddNodeIDNode(), assert(), llvm::ISD::BITCAST, llvm::ISD::BUILD_VECTOR, llvm::ISD::CONCAT_VECTORS, llvm::dyn_cast(), E, llvm::ISD::FMA, FoldBUILD_VECTOR(), FoldCONCAT_VECTORS(), FoldConstantVectorArithmetic(), FoldSetCC(), llvm::APFloat::fusedMultiplyAdd(), getConstantFP(), llvm::SDLoc::getDebugLoc(), llvm::SDLoc::getIROrder(), llvm::SDValue::getSimpleValueType(), llvm::EVT::getSimpleVT(), getUNDEF(), llvm::SDValue::getValueType(), llvm::EVT::getVectorNumElements(), getVTList(), llvm::ConstantSDNode::getZExtValue(), llvm::MVT::Glue, llvm::TargetLoweringBase::hasFloatingPointExceptions(), llvm::ISD::INSERT_SUBVECTOR, llvm::ISD::INSERT_VECTOR_ELT, llvm::EVT::isFloatingPoint(), llvm::EVT::isInteger(), llvm::EVT::isSimple(), llvm::EVT::isVector(), llvm_unreachable, N, NewSDValueDbgMsg(), llvm::APFloatBase::opInvalidOp, llvm::APFloatBase::rmNearestTiesToEven, llvm::ISD::SELECT, llvm::ISD::SETCC, llvm::SDNode::setFlags(), simplifySelect(), llvm::NVPTX::PTXLdStInstCode::V2, llvm::ISD::VECTOR_SHUFFLE, and llvm::ISD::VSELECT.
SDValue SelectionDAG::getNode | ( | unsigned | Opcode, |
const SDLoc & | DL, | ||
EVT | VT, | ||
SDValue | N1, | ||
SDValue | N2, | ||
SDValue | N3, | ||
SDValue | N4 | ||
) |
Definition at line 5378 of file SelectionDAG.cpp.
References getNode().
SDValue SelectionDAG::getNode | ( | unsigned | Opcode, |
const SDLoc & | DL, | ||
EVT | VT, | ||
SDValue | N1, | ||
SDValue | N2, | ||
SDValue | N3, | ||
SDValue | N4, | ||
SDValue | N5 | ||
) |
Definition at line 5384 of file SelectionDAG.cpp.
References getNode().
Definition at line 7203 of file SelectionDAG.cpp.
References getNode(), and llvm::None.
Definition at line 7208 of file SelectionDAG.cpp.
References getNode().
SDValue SelectionDAG::getNode | ( | unsigned | Opcode, |
const SDLoc & | DL, | ||
SDVTList | VTList, | ||
SDValue | N1, | ||
SDValue | N2 | ||
) |
Definition at line 7214 of file SelectionDAG.cpp.
References getNode().
SDValue SelectionDAG::getNode | ( | unsigned | Opcode, |
const SDLoc & | DL, | ||
SDVTList | VTList, | ||
SDValue | N1, | ||
SDValue | N2, | ||
SDValue | N3 | ||
) |
Definition at line 7220 of file SelectionDAG.cpp.
References getNode().
SDValue SelectionDAG::getNode | ( | unsigned | Opcode, |
const SDLoc & | DL, | ||
SDVTList | VTList, | ||
SDValue | N1, | ||
SDValue | N2, | ||
SDValue | N3, | ||
SDValue | N4 | ||
) |
Definition at line 7226 of file SelectionDAG.cpp.
References getNode().
SDValue SelectionDAG::getNode | ( | unsigned | Opcode, |
const SDLoc & | DL, | ||
SDVTList | VTList, | ||
SDValue | N1, | ||
SDValue | N2, | ||
SDValue | N3, | ||
SDValue | N4, | ||
SDValue | N5 | ||
) |
Definition at line 7232 of file SelectionDAG.cpp.
References getNode().
SDNode * SelectionDAG::getNodeIfExists | ( | unsigned | Opcode, |
SDVTList | VTList, | ||
ArrayRef< SDValue > | Ops, | ||
const SDNodeFlags | Flags = SDNodeFlags() |
||
) |
Get the specified node if it's already available, or else return NULL.
getNodeIfExists - Get the specified node if it's already available, or else return NULL.
Definition at line 7841 of file SelectionDAG.cpp.
References AddNodeIDNode(), E, llvm::MVT::Glue, llvm::SDVTList::NumVTs, and llvm::SDVTList::VTs.
Referenced by EmitTest(), and simplifyDivRem().
Create a bitwise NOT operation as (XOR Val, -1).
getNOT - Create a bitwise NOT operation as (XOR Val, -1).
Definition at line 1140 of file SelectionDAG.cpp.
References llvm::APInt::getAllOnesValue(), getConstant(), getNode(), llvm::EVT::getScalarType(), llvm::EVT::getSizeInBits(), and llvm::ISD::XOR.
Referenced by calculateByteProvider(), combineMinNumMaxNum(), combineSelectOfTwoConstants(), combineSetCC(), combineVSelectWithAllOnesOrZeros(), EmitVectorComparison(), findUser(), foldAddSubOfSignBit(), foldExtendedSignBitTest(), llvm::TargetLowering::isExtendedTrueVal(), isTruncWithZeroHighBitsInput(), LowerADDSAT_SUBSAT(), llvm::AMDGPUTargetLowering::LowerFROUND64(), llvm::AMDGPUTargetLowering::LowerFTRUNC(), lowerMSABitClear(), lowerMSABitClearImm(), LowerVSETCC(), llvm::R600TargetLowering::ReplaceNodeResults(), replaceShuffleOfInsert(), llvm::TargetLowering::SimplifyDemandedBits(), and llvm::TargetLowering::SimplifySetCC().
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inline |
Create an add instruction with appropriate flags when used for addressing some offset of an object.
i.e. if a load is split into multiple components, create an add nuw from the base pointer to the offset.
Definition at line 806 of file SelectionDAG.h.
References getConstant(), and llvm::SDValue::getValueType().
Referenced by llvm::TargetLowering::expandUnalignedLoad(), llvm::TargetLowering::expandUnalignedStore(), findUnwindDestinations(), findUser(), getExpandedMinMaxOps(), llvm::SITargetLowering::isTypeDesirableForOp(), llvm::TargetLowering::scalarizeVectorLoad(), llvm::TargetLowering::scalarizeVectorStore(), llvm::AMDGPUTargetLowering::SplitVectorLoad(), and llvm::AMDGPUTargetLowering::SplitVectorStore().
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inline |
Definition at line 811 of file SelectionDAG.h.
References llvm::ISD::ADD, llvm::SDValue::getValueType(), and llvm::SDNodeFlags::setNoUnsignedWrap().
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inline |
Definition at line 408 of file SelectionDAG.h.
Definition at line 399 of file SelectionDAG.h.
Referenced by llvm::SITargetLowering::LowerFormalArguments(), and llvm::SITargetLowering::passSpecialInputs().
Definition at line 1729 of file SelectionDAG.cpp.
References llvm::FoldingSetNodeID::AddInteger(), AddNodeIDNode(), E, getVTList(), llvm::TargetLowering::isSDNodeSourceOfDivergence(), llvm::None, llvm::ISD::Register, and llvm::SDNode::SDNodeBits.
Referenced by llvm::RegsForValue::AddInlineAsmOperands(), llvm::analyzeArguments(), AnalyzeReturnValues(), llvm::AVRDAGToDAGISel::select< AVRISD::CALL >(), llvm::AVRDAGToDAGISel::select< ISD::LOAD >(), CC_Lanai32_VarArg(), llvm::ARMTargetLowering::CCAssignFnForReturn(), ConvertCarryFlagToBooleanCarry(), createCMovFP(), llvm::AMDGPUTargetLowering::CreateLiveInRegister(), llvm::MipsTargetLowering::EmitInstrWithCustomInserter(), expandf64Toi32(), findUnwindDestinations(), findUser(), llvm::MipsTargetLowering::getAddrGPRel(), getAVX2GatherNode(), llvm::HexagonTargetLowering::GetDynamicTLSAddr(), getEstimate(), getGatherNode(), llvm::MipsDAGToDAGISel::getGlobalBaseReg(), llvm::MipsTargetLowering::getGlobalReg(), llvm::ARMTargetLowering::getJumpTableEncoding(), getMOVL(), llvm::MipsTargetLowering::getOpndList(), llvm::PPCTargetLowering::getPICJumpTableRelocBaseExpr(), getPrefetchNode(), getReductionSDNode(), getScatterNode(), llvm::ARCTargetLowering::getTargetNodeName(), getTOCEntry(), llvm::MipsTargetLowering::getTypeForExtReturn(), getVectorCompareInfo(), getZeroVector(), isFloatingPointZero(), isLowerSaturatingConditional(), llvm::SITargetLowering::legalizeTargetIndependentNode(), LowerATOMIC_FENCE(), llvm::HexagonTargetLowering::LowerCall(), llvm::SITargetLowering::LowerCall(), llvm::SystemZTargetLowering::LowerCall(), llvm::SparcTargetLowering::LowerCall_32(), llvm::SparcTargetLowering::LowerCall_64(), lowerCallResult(), LowerCallResult(), llvm::SelectionDAGBuilder::LowerCallTo(), llvm::LanaiTargetLowering::LowerConstantPool(), llvm::HexagonTargetLowering::LowerEH_RETURN(), lowerFCOPYSIGN64(), llvm::LanaiTargetLowering::LowerGlobalAddress(), llvm::SparcTargetLowering::LowerGlobalTLSAddress(), LowerInterruptReturn(), llvm::SparcTargetLowering::LowerINTRINSIC_WO_CHAIN(), llvm::LanaiTargetLowering::LowerJumpTable(), LowerMemOpCallTo(), llvm::BPFTargetLowering::LowerOperation(), llvm::HexagonTargetLowering::LowerReturn(), llvm::SITargetLowering::LowerReturn(), llvm::SystemZTargetLowering::LowerReturn(), llvm::SparcTargetLowering::LowerReturn_32(), llvm::SparcTargetLowering::LowerReturn_64(), LowerSETCCCARRY(), LowerVASTART(), mayTailCallThisCC(), llvm::X86TargetLowering::needsFixedCatchObjects(), Passv64i1ArgInRegs(), llvm::R600TargetLowering::PerformDAGCombine(), llvm::PPCTargetLowering::PerformDAGCombine(), performNEONPostLDSTCombine(), performPostLD1Combine(), PrepareCall(), llvm::PPCTargetLowering::SelectAddressRegImm(), llvm::PPCTargetLowering::SelectAddressRegRegOnly(), llvm::SelectionDAGISel::SelectCodeCommon(), selectImm(), unpackF64OnRV32DSoftABI(), and UnpackFromArgumentSlot().
Definition at line 1744 of file SelectionDAG.cpp.
References AddNodeIDNode(), llvm::FoldingSetNodeID::AddPointer(), E, getVTList(), llvm::None, llvm::ISD::RegisterMask, and llvm::MVT::Untyped.
Referenced by llvm::analyzeArguments(), CC_Lanai32_VarArg(), llvm::ARMTargetLowering::CCAssignFnForReturn(), llvm::HexagonTargetLowering::GetDynamicTLSAddr(), llvm::ARMTargetLowering::getJumpTableEncoding(), getMOVL(), llvm::MipsTargetLowering::getOpndList(), getReductionSDNode(), llvm::ARCTargetLowering::getTargetNodeName(), llvm::HexagonTargetLowering::LowerCall(), llvm::SITargetLowering::LowerCall(), llvm::SystemZTargetLowering::LowerCall(), llvm::SparcTargetLowering::LowerCall_32(), llvm::SparcTargetLowering::LowerCall_64(), llvm::SparcTargetLowering::LowerGlobalTLSAddress(), mayTailCallThisCC(), PrepareCall(), and unpackF64OnRV32DSoftABI().
Return the root tag of the SelectionDAG.
Definition at line 457 of file SelectionDAG.h.
Referenced by llvm::DOTGraphTraits< SelectionDAG * >::addCustomGraphFeatures(), llvm::checkForCycles(), findMatchingInlineAsmOperand(), llvm::SelectionDAGBuilder::getControlRoot(), getFPTernOp(), getMemCmpLoad(), llvm::SelectionDAGBuilder::getRoot(), getUnderlyingArgReg(), getUniformBase(), llvm::SelectionDAGISel::getUninvalidatedNodeId(), hasOnlySelectUsers(), llvm::NVPTXTargetLowering::LowerFormalArguments(), llvm::SparcTargetLowering::LowerFormalArguments_32(), LowerFPOWI(), RemoveDeadNode(), RemoveDeadNodes(), ReplaceAllUsesOfValueWith(), ReplaceAllUsesWith(), llvm::DAGTypeLegalizer::run(), tryToElideArgumentCopy(), and llvm::SelectionDAGBuilder::UpdateSplitBlock().
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inline |
Helper function to make it easier to build Select's if you just have operands and don't want to check for vector.
Definition at line 950 of file SelectionDAG.h.
References assert(), llvm::SDValue::getValueType(), llvm::EVT::isVector(), llvm::ISD::SELECT, and llvm::ISD::VSELECT.
Referenced by llvm::TargetLowering::BuildUDIV(), combineFMinNumFMaxNum(), combineLogicBlendIntoPBLENDV(), combineMaskedLoadConstantMask(), combineMinNumMaxNum(), combineSelect(), combineVSelectWithAllOnesOrZeros(), ConvertSelectToConcatVector(), foldExtendedSignBitTest(), getAsNonOpaqueConstant(), getExpandedMinMaxOps(), GetFPLibCall(), getLoadExtOrTrunc(), getPermuteMask(), getShiftAmountTyForConstant(), getUnderlyingArgReg(), isTruncWithZeroHighBitsInput(), llvm::HexagonTargetLowering::LowerBUILD_VECTOR(), LowerBUILD_VECTORvXi1(), llvm::AMDGPUTargetLowering::LowerFRINT(), llvm::AMDGPUTargetLowering::LowerINT_TO_FP32(), LowerMINMAX(), LowerRotate(), LowerShift(), llvm::LanaiTargetLowering::LowerSHL_PARTS(), LowerSIGN_EXTEND_Mask(), llvm::LanaiTargetLowering::LowerSRL_PARTS(), lowerUINT_TO_FP_vec(), lowerVectorShuffleAsBlend(), lowerVectorShuffleToEXPAND(), lowerVSELECTtoVectorShuffle(), LowerZERO_EXTEND_Mask(), performSelectCombine(), replaceShuffleOfInsert(), and simplifyDivRem().
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inline |
Helper function to make it easier to build SelectCC's if you just have an ISD::CondCode instead of an SDValue.
Definition at line 962 of file SelectionDAG.h.
References From, getCondCode(), llvm::SDValue::getValueType(), llvm::MachineMemOperand::MOLoad, llvm::MachineMemOperand::MONone, llvm::MachineMemOperand::MOStore, llvm::RISCVFenceField::O, llvm::RISCVFenceField::R, llvm::ISD::SELECT_CC, X, and Y.
Referenced by calculateByteProvider(), combineHorizontalPredicateResult(), ConvertCarryFlagToBooleanCarry(), createVariablePermute(), llvm::TargetLowering::expandMUL_LOHI(), GetFPLibCall(), isClampZeroToOne(), llvm::AMDGPUTargetLowering::LowerFP_TO_FP16(), llvm::AMDGPUTargetLowering::LowerSDIVREM(), llvm::AMDGPUTargetLowering::LowerUDIVREM(), llvm::AMDGPUTargetLowering::LowerUDIVREM64(), llvm::R600TargetLowering::PerformDAGCombine(), PrepareCall(), llvm::R600TargetLowering::ReplaceNodeResults(), and widenVec().
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inline |
Definition at line 406 of file SelectionDAG.h.
Referenced by getMemCmpLoad().
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inline |
Helper function to make it easier to build SetCC's if you just have an ISD::CondCode instead of an SDValue.
Definition at line 937 of file SelectionDAG.h.
References assert(), getCondCode(), llvm::SDValue::getValueType(), llvm::EVT::isVector(), llvm::ISD::SETCC, and llvm::ISD::SETCC_INVALID.
Referenced by llvm::TargetLowering::BuildUDIV(), calculateByteProvider(), combineExtSetcc(), combineFMinNumFMaxNum(), combineSelect(), combineSetCC(), combineToExtendBoolVectorInReg(), combineVectorSizedSetCCEquality(), combineVSelectWithAllOnesOrZeros(), ConvertSelectToConcatVector(), EmitVectorComparison(), findUser(), foldExtendedSignBitTest(), FoldSetCC(), foldXorTruncShiftIntoCmp(), generateEquivalentSub(), getEstimate(), getExpandedMinMaxOps(), GetFPLibCall(), getFPTernOp(), getMemCmpLoad(), llvm::PPCTargetLowering::getPICJumpTableRelocBaseExpr(), GetPromotionOpcode(), getShiftAmountTyForConstant(), getUnderlyingArgReg(), haveEfficientBuildVectorPattern(), llvm::TargetLowering::isExtendedTrueVal(), isTruncateOf(), isVectorReductionOp(), lower1BitVectorShuffle(), llvm::AMDGPUTargetLowering::LowerCTLZ_CTTZ(), llvm::AMDGPUTargetLowering::LowerDIVREM24(), LowerEXTEND_VECTOR_INREG(), llvm::AMDGPUTargetLowering::LowerFCEIL(), llvm::AMDGPUTargetLowering::LowerFFLOOR(), llvm::HexagonTargetLowering::LowerFormalArguments(), llvm::AMDGPUTargetLowering::LowerFRINT(), llvm::AMDGPUTargetLowering::LowerFROUND32_16(), llvm::AMDGPUTargetLowering::LowerFROUND64(), llvm::AMDGPUTargetLowering::LowerFTRUNC(), llvm::AMDGPUTargetLowering::LowerINT_TO_FP32(), LowerIntVSETCC_AVX512(), LowerMINMAX(), lowerMSABitClearImm(), LowerMULH(), LowerScalarImmediateShift(), llvm::HexagonTargetLowering::LowerSETCC(), LowerShift(), LowerShiftParts(), llvm::LanaiTargetLowering::LowerSHL_PARTS(), llvm::LanaiTargetLowering::LowerSRL_PARTS(), LowerTruncateVecI1(), lowerUINT_TO_FP_vec(), LowerUMULO_SMULO(), LowerVectorCTLZInRegLUT(), lowerVSELECTtoVectorShuffle(), llvm::AMDGPUTargetLowering::performSelectCombine(), performSELECTCombine(), performVSelectCombine(), llvm::X86TargetLowering::ReplaceNodeResults(), replaceShuffleOfInsert(), simplifyDivRem(), llvm::TargetLowering::SimplifySetCC(), llvm::SelectionDAGBuilder::visitBitTestCase(), llvm::SelectionDAGBuilder::visitBitTestHeader(), visitFMinMax(), llvm::SelectionDAGBuilder::visitJumpTableHeader(), llvm::SelectionDAGBuilder::visitSPDescriptorParent(), llvm::SelectionDAGBuilder::visitSwitchCase(), and widenVec().
Convert Op, which must be of integer type, to the integer type VT, by either sign-extending or truncating it.
Definition at line 1106 of file SelectionDAG.cpp.
References llvm::EVT::bitsGT(), getNode(), llvm::SDValue::getValueType(), llvm::ISD::SIGN_EXTEND, and llvm::ISD::TRUNCATE.
Referenced by combineGatherScatter(), combineHorizontalPredicateResult(), combineShuffleOfScalars(), combineToExtendBoolVectorInReg(), EmitVectorComparison(), FoldCONCAT_VECTORS(), foldExtendedSignBitTest(), generateEquivalentSub(), getExpandedMinMaxOps(), getFPTernOp(), getMad64_32(), getMemCmpLoad(), getNode(), getShiftAmountTyForConstant(), hasOnlySelectUsers(), isTruncateOf(), llvm::SITargetLowering::isTypeDesirableForOp(), LowerBITCAST(), llvm::AMDGPUTargetLowering::LowerINT_TO_FP32(), LowerLoad(), LowerMULH(), llvm::HexagonTargetLowering::LowerSETCC(), LowerShift(), lowerVSELECTtoVectorShuffle(), LowerVSETCC(), llvm::AMDGPUTargetLowering::performMulCombine(), llvm::AMDGPUTargetLowering::performMulhsCombine(), and scalarizeExtractedBinop().
Return the specified value casted to the target's desired shift amount type.
getShiftAmountOperand - Return the specified value casted to the target's desired shift amount type.
Definition at line 1865 of file SelectionDAG.cpp.
References getDataLayout(), llvm::TargetLoweringBase::getShiftAmountTy(), llvm::SDValue::getValueType(), getZExtOrTrunc(), and llvm::EVT::isVector().
Return a splat ISD::BUILD_VECTOR node, consisting of Op splatted to all elements.
VT must be a vector type. Op's type must be the same as (or, for integers, a type wider than) VT's element type.
Definition at line 751 of file SelectionDAG.h.
References assert(), llvm::EVT::bitsLE(), llvm::ISD::BUILD_VECTOR, llvm::SDValue::getOpcode(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::EVT::isInteger(), and llvm::ISD::UNDEF.
Referenced by ConstantBuildVector(), getConstant(), getConstantFP(), getMemsetValue(), getUniformBase(), getVectorShuffle(), and hasOnlySelectUsers().
Compute the VTs needed for the low/hi parts of a type which is split (or expanded) into two not necessarily identical pieces.
GetSplitDestVTs - Compute the VTs needed for the low/hi parts of a type which is split (or expanded) into two not necessarily identical pieces.
Definition at line 9040 of file SelectionDAG.cpp.
References llvm::EVT::getHalfNumVectorElementsVT(), and llvm::EVT::isVector().
Referenced by ConvertSelectToConcatVector(), ExtendUsesToFormExtLoad(), llvm::X86TargetLowering::ReplaceNodeResults(), ReplaceReductionResults(), llvm::AMDGPUTargetLowering::SplitVectorLoad(), llvm::AMDGPUTargetLowering::SplitVectorStore(), and SplitVSETCC().
Construct a node to track a Value* through the backend.
Definition at line 1802 of file SelectionDAG.cpp.
References AddNodeIDNode(), llvm::FoldingSetNodeID::AddPointer(), assert(), E, llvm::Value::getType(), getVTList(), llvm::Type::isPointerTy(), llvm::None, llvm::MVT::Other, and llvm::ISD::SRCVALUE.
Referenced by findMatchingInlineAsmOperand(), and getUnderlyingArgReg().
Compute a TokenFactor to force all the incoming stack arguments to be loaded from the stack.
getStackArgumentTokenFactor - Compute a TokenFactor to force all the incoming stack arguments to be loaded from the stack.
This is used in tail call lowering to protect stack arguments from being clobbered.
Definition at line 5393 of file SelectionDAG.cpp.
References getEntryNode(), getNode(), llvm::MVT::Other, llvm::SmallVectorTemplateBase< T >::push_back(), and llvm::ISD::TokenFactor.
Referenced by getMOVL(), and PrepareCall().
SDValue SelectionDAG::getStore | ( | SDValue | Chain, |
const SDLoc & | dl, | ||
SDValue | Val, | ||
SDValue | Ptr, | ||
MachinePointerInfo | PtrInfo, | ||
unsigned | Alignment = 0 , |
||
MachineMemOperand::Flags | MMOFlags = MachineMemOperand::MONone , |
||
const AAMDNodes & | AAInfo = AAMDNodes() |
||
) |
Helper function to build ISD::STORE nodes.
This function will set the MOStore flag on MMOFlags, but you can set it if you want. The MOLoad and MOInvariant flags must not be set.
Definition at line 6724 of file SelectionDAG.cpp.
References assert(), getEVTAlignment(), getMachineFunction(), llvm::MachineFunction::getMachineMemOperand(), llvm::EVT::getStoreSize(), llvm::SDValue::getValueType(), InferPointerInfo(), llvm::PointerUnion< PT1, PT2 >::isNull(), llvm::MachineMemOperand::MOLoad, llvm::MachineMemOperand::MOStore, llvm::MVT::Other, and llvm::MachinePointerInfo::V.
Referenced by llvm::analyzeArguments(), AnalyzeReturnValues(), CallingConvSupported(), CC_Lanai32_VarArg(), llvm::AArch64TargetLowering::CCAssignFnForReturn(), llvm::ARMTargetLowering::CCAssignFnForReturn(), combineStore(), llvm::MipsSETargetLowering::EmitInstrWithCustomInserter(), llvm::MipsTargetLowering::EmitInstrWithCustomInserter(), EmitTailCallStoreFPAndRetAddr(), EmitTailCallStoreRetAddr(), llvm::ARMSelectionDAGInfo::EmitTargetCodeForMemcpy(), llvm::SystemZSelectionDAGInfo::EmitTargetCodeForMemset(), EnsureStackAlignment(), llvm::TargetLowering::expandUnalignedLoad(), llvm::TargetLowering::expandUnalignedStore(), findMatchingInlineAsmOperand(), findUnwindDestinations(), getAddressForMemoryInput(), getExpandedMinMaxOps(), GetFPLibCall(), getMemcpyLoadsAndStores(), getMemmoveLoadsAndStores(), getMOVL(), getNextIntArgReg(), GetPromotionOpcode(), llvm::ARCTargetLowering::getTargetNodeName(), getTruncStore(), llvm::MipsTargetLowering::getTypeForExtReturn(), getUnderlyingArgReg(), getVectorCompareInfo(), hasOnlySelectUsers(), haveEfficientBuildVectorPattern(), llvm::intCCToAVRCC(), isSortedByValueNo(), LowerADJUST_TRAMPOLINE(), llvm::HexagonTargetLowering::LowerCall(), llvm::SITargetLowering::LowerCall(), llvm::SystemZTargetLowering::LowerCall(), llvm::SparcTargetLowering::LowerCall_32(), llvm::SparcTargetLowering::LowerCall_64(), lowerCallResult(), LowerCallResult(), llvm::HexagonTargetLowering::LowerEH_RETURN(), llvm::SparcTargetLowering::LowerF128_LibCallArg(), LowerF128Store(), llvm::SystemZTargetLowering::LowerFormalArguments(), llvm::SparcTargetLowering::LowerFormalArguments_32(), llvm::SparcTargetLowering::LowerFormalArguments_64(), lowerFP_TO_SINT_STORE(), LowerI64IntToFP_AVX512DQ(), LowerMemOpCallTo(), lowerMSAStoreIntr(), LowerMULH(), llvm::RISCVTargetLowering::LowerOperation(), LowerSTORE(), LowerStore(), LowerTruncateVectorStore(), lowerUINT_TO_FP_vec(), llvm::LanaiTargetLowering::LowerVASTART(), llvm::MSP430TargetLowering::LowerVASTART(), llvm::HexagonTargetLowering::LowerVASTART(), LowerVASTART(), mayTailCallThisCC(), memsetStore(), llvm::X86TargetLowering::needsFixedCatchObjects(), operator!=(), llvm::AMDGPUTargetLowering::performStoreCombine(), PerformSTORECombine(), PrepareCall(), reduceMaskedStoreToScalarStore(), llvm::R600TargetLowering::ReplaceNodeResults(), llvm::TargetLowering::scalarizeVectorStore(), ShrinkLoadReplaceStoreWithStore(), spillIncomingStatepointValue(), splitStores(), splitStoreSplat(), llvm::HexagonDAGToDAGISel::StoreInstrForLoadIntrinsic(), llvm::AMDGPUTargetLowering::storeStackInputValue(), StoreTailCallArgumentsToStackSlot(), unpackF64OnRV32DSoftABI(), and widenVec().
SDValue SelectionDAG::getStore | ( | SDValue | Chain, |
const SDLoc & | dl, | ||
SDValue | Val, | ||
SDValue | Ptr, | ||
MachineMemOperand * | MMO | ||
) |
Definition at line 6745 of file SelectionDAG.cpp.
References llvm::FoldingSetNodeID::AddInteger(), AddNodeIDNode(), assert(), E, llvm::MachinePointerInfo::getAddrSpace(), llvm::SDLoc::getDebugLoc(), llvm::SDLoc::getIROrder(), llvm::MachineMemOperand::getPointerInfo(), getUNDEF(), llvm::SDValue::getValueType(), getVTList(), NewSDValueDbgMsg(), llvm::MVT::Other, llvm::ISD::STORE, llvm::RegState::Undef, and llvm::ISD::UNINDEXED.
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Definition at line 403 of file SelectionDAG.h.
References llvm::MachineFunction::getSubtarget().
Referenced by emitComparison(), emitConditionalComparison(), llvm::HexagonSelectionDAGInfo::EmitTargetCodeForMemcpy(), llvm::XCoreSelectionDAGInfo::EmitTargetCodeForMemcpy(), EmitVectorComparison(), findMatchingInlineAsmOperand(), getHexagonSubtarget(), llvm::SDNode::getOperationName(), getReductionSDNode(), getUnderlyingArgReg(), hasOnlySelectUsers(), init(), isContractable(), llvm::PPC::isVPKUDUMShuffleMask(), LowerADDSUBCARRY(), lowerMSASplatZExt(), llvm::HexagonTargetLowering::LowerToTLSGeneralDynamicModel(), LowerVectorFP_TO_INT(), LowerVectorINT_TO_FP(), numVectorEltsOrZero(), patchMatchingInput(), printMemOperand(), recoverFramePointer(), replaceShuffleOfInsert(), and truncateVecElts().
SDValue SelectionDAG::getSymbolFunctionGlobalAddress | ( | SDValue | Op, |
Function ** | TargetFunction = nullptr |
||
) |
Returs an GlobalAddress of the function from the current module with name matching the given ExternalSymbol.
Additionally can provide the matched function. Panics the function doesn't exists.
Definition at line 8525 of file SelectionDAG.cpp.
References assert(), llvm::raw_ostream::flush(), llvm::GlobalValue::getAddressSpace(), getDataLayout(), llvm::Module::getFunction(), getGlobalAddress(), llvm::GlobalValue::getParent(), llvm::object::getSymbol(), llvm::report_fatal_error(), and llvm::ARMBuildAttrs::Symbol.
Referenced by llvm::NVPTXTargetLowering::LowerCall().
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Definition at line 402 of file SelectionDAG.h.
References llvm::SystemZISD::TM.
Referenced by CallingConvSupported(), combineFMinFMax(), combineFMinNumFMaxNum(), combineSelect(), llvm::MipsTargetLowering::EmitInstrWithCustomInserter(), foldFPToIntToFP(), FoldIntToFPToInt(), getFPTernOp(), llvm::ARMTargetLowering::getJumpTableEncoding(), getLoadExtOrTrunc(), getMad64_32(), getMOVL(), GetNegatedExpression(), getNode(), llvm::SDNode::getOperationName(), llvm::PPCTargetLowering::getPICJumpTableRelocBaseExpr(), getUnderlyingArgReg(), isClampZeroToOne(), isContractable(), llvm::SITargetLowering::isEligibleForTailCallOptimization(), isFMAddSubOrFMSubAdd(), isKnownNeverNaN(), isLegalToCombineMinNumMaxNum(), llvm::SelectionDAGBuilder::LowerCallTo(), LowerEXTRACT_SUBVECTOR(), llvm::SparcTargetLowering::LowerGlobalTLSAddress(), LowerToTLSExecModel(), lowerUINT_TO_FP_vXi32(), MatchingStackOffset(), mayTailCallThisCC(), PrepareCall(), shouldGuaranteeTCO(), llvm::SelectionDAGBuilder::UpdateSplitBlock(), and widenVec().
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Definition at line 673 of file SelectionDAG.h.
Referenced by getEstimate(), llvm::MipsTargetLowering::getGlobalReg(), llvm::PPCTargetLowering::getPICJumpTableRelocBaseExpr(), llvm::AVRTargetLowering::getSetCCResultType(), IsSmallObject(), llvm::MSP430TargetLowering::LowerBlockAddress(), llvm::HexagonTargetLowering::LowerBlockAddress(), LowerEXTRACT_SUBVECTOR(), llvm::RISCVTargetLowering::LowerOperation(), mayTailCallThisCC(), and llvm::SparcTargetLowering::withTargetFlags().
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Definition at line 576 of file SelectionDAG.h.
References getConstant().
Referenced by llvm::RegsForValue::AddInlineAsmOperands(), addStackMapLiveVars(), llvm::AVRDAGToDAGISel::select< ISD::FrameIndex >(), llvm::AVRDAGToDAGISel::select< ISD::STORE >(), llvm::SITargetLowering::buildRSRC(), buildSMovImm32(), CallingConvSupported(), combineADDToADDZE(), createGPRPairNode(), llvm::HexagonDAGToDAGISel::DetectUseSxtw(), findMatchingInlineAsmOperand(), findUser(), llvm::PPC::get_VSPLTI_elt(), getAL(), getAVX2GatherNode(), getCopyFromParts(), getEstimate(), getFPTernOp(), getGatherNode(), getIntOperandsFromRegisterString(), getLeftShift(), getMad64_32(), getPrefetchNode(), getPTXCmpMode(), getScatterNode(), getTargetExtractSubreg(), getTargetInsertSubreg(), llvm::MipsTargetLowering::getTypeForExtReturn(), getUnderlyingArgReg(), getUniformBase(), getVAArg(), getVectorCompareInfo(), getZeroVector(), hasOnlySelectUsers(), isNEONModifiedImm(), llvm::HexagonDAGToDAGISel::LoadInstrForLoadIntrinsic(), llvm::SparcTargetLowering::LowerAsmOperandForConstraint(), llvm::LanaiTargetLowering::LowerAsmOperandForConstraint(), llvm::AVRTargetLowering::LowerAsmOperandForConstraint(), llvm::ARMTargetLowering::LowerAsmOperandForConstraint(), llvm::SystemZTargetLowering::LowerAsmOperandForConstraint(), llvm::PPCTargetLowering::LowerAsmOperandForConstraint(), llvm::X86TargetLowering::LowerAsmOperandForConstraint(), llvm::TargetLowering::LowerAsmOperandForConstraint(), LowerATOMIC_FENCE(), LowerBITCAST(), llvm::SITargetLowering::LowerCall(), llvm::SparcTargetLowering::LowerCall_32(), LowerCMP_SWAP(), LowerCTTZ(), llvm::SparcTargetLowering::LowerF128Compare(), LowerF128Load(), LowerF128Store(), lowerVECTOR_SHUFFLE_VSHF(), LowerVectorINT_TO_FP(), mayTailCallThisCC(), narrowIfNeeded(), optimizeLogicalImm(), parseCachePolicy(), parseTexFail(), Passv64i1ArgInRegs(), performBitcastCombine(), llvm::R600TargetLowering::PerformDAGCombine(), llvm::PPCTargetLowering::PerformDAGCombine(), pickOpcodeForVT(), pushStackMapConstant(), ReplaceBITCASTResults(), llvm::AVRDAGToDAGISel::SelectAddr(), llvm::PPCTargetLowering::SelectAddressRegImm(), llvm::HexagonDAGToDAGISel::SelectAnyImmediate(), llvm::SelectionDAGISel::SelectCodeCommon(), llvm::HexagonDAGToDAGISel::SelectConstantFP(), llvm::HexagonDAGToDAGISel::SelectD2P(), llvm::HexagonDAGToDAGISel::SelectFrameIndex(), selectI64Imm(), selectI64ImmDirect(), selectImm(), llvm::HexagonDAGToDAGISel::SelectIndexedLoad(), llvm::HexagonDAGToDAGISel::SelectIndexedStore(), llvm::AVRDAGToDAGISel::SelectInlineAsmMemoryOperand(), llvm::NVPTXDAGToDAGISel::SelectInlineAsmMemoryOperand(), llvm::HexagonDAGToDAGISel::SelectInlineAsmMemoryOperand(), llvm::SelectionDAGISel::SelectInlineAsmMemoryOperands(), llvm::HexagonDAGToDAGISel::SelectNewCircIntrinsic(), llvm::HexagonDAGToDAGISel::SelectQ2V(), llvm::HvxSelector::selectRor(), llvm::HexagonDAGToDAGISel::SelectSHL(), llvm::HexagonDAGToDAGISel::SelectV2Q(), llvm::HexagonDAGToDAGISel::SelectVAlign(), llvm::HexagonDAGToDAGISel::SelectVAlignAddr(), tryBitfieldInsertOpFromOr(), tryBitfieldInsertOpFromOrAndImm(), Widen(), and llvm::SITargetLowering::wrapAddr64Rsrc().
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Definition at line 580 of file SelectionDAG.h.
References getConstant().
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Definition at line 584 of file SelectionDAG.h.
References getConstant().
Definition at line 608 of file SelectionDAG.h.
Referenced by llvm::NVPTXDAGToDAGISel::runOnMachineFunction(), and llvm::SelectionDAGISel::SelectCodeCommon().
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Definition at line 611 of file SelectionDAG.h.
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Definition at line 614 of file SelectionDAG.h.
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Definition at line 639 of file SelectionDAG.h.
References llvm::AMDGPU::HSAMD::Kernel::Arg::Key::Align.
Referenced by llvm::ARMTargetLowering::CCAssignFnForReturn(), llvm::MipsTargetLowering::getGlobalReg(), llvm::ARMTargetLowering::getJumpTableEncoding(), getTOCEntry(), llvm::ARMTargetLowering::isReadOnly(), IsSmallObject(), llvm::LanaiTargetLowering::LowerConstantPool(), llvm::HexagonTargetLowering::LowerConstantPool(), LowerEXTRACT_SUBVECTOR(), llvm::RISCVTargetLowering::LowerOperation(), LowerWRITE_REGISTER(), mayTailCallThisCC(), promoteToConstantPool(), and llvm::SparcTargetLowering::withTargetFlags().
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Definition at line 647 of file SelectionDAG.h.
References llvm::AMDGPU::HSAMD::Kernel::Arg::Key::Align, and Reg.
SDValue SelectionDAG::getTargetExternalSymbol | ( | const char * | Sym, |
EVT | VT, | ||
unsigned char | TargetFlags = 0 |
||
) |
Definition at line 1515 of file SelectionDAG.cpp.
Referenced by llvm::analyzeArguments(), AnalyzeReturnValues(), CallingConvSupported(), CC_Lanai32_VarArg(), llvm::ARMTargetLowering::CCAssignFnForReturn(), llvm::HexagonSelectionDAGInfo::EmitTargetCodeForMemcpy(), findMatchingInlineAsmOperand(), getEstimate(), llvm::MipsTargetLowering::getGlobalReg(), llvm::ARMTargetLowering::getJumpTableEncoding(), getMOVL(), getReductionSDNode(), llvm::ARCTargetLowering::getTargetNodeName(), llvm::HexagonTargetLowering::LowerCall(), llvm::SystemZTargetLowering::LowerCall(), llvm::NVPTXTargetLowering::LowerCall(), llvm::SparcTargetLowering::LowerCall_32(), llvm::SparcTargetLowering::LowerCall_64(), LowerCallResult(), llvm::MSP430TargetLowering::LowerExternalSymbol(), LowerEXTRACT_SUBVECTOR(), llvm::HexagonTargetLowering::LowerGLOBAL_OFFSET_TABLE(), llvm::SparcTargetLowering::LowerGlobalTLSAddress(), llvm::BPFTargetLowering::LowerOperation(), mayTailCallThisCC(), PrepareCall(), unpackF64OnRV32DSoftABI(), and llvm::SparcTargetLowering::withTargetFlags().
SDValue SelectionDAG::getTargetExtractSubreg | ( | int | SRIdx, |
const SDLoc & | DL, | ||
EVT | VT, | ||
SDValue | Operand | ||
) |
A convenience function for creating TargetInstrInfo::EXTRACT_SUBREG nodes.
getTargetExtractSubreg - A convenience function for creating TargetOpcode::EXTRACT_SUBREG nodes.
Definition at line 7821 of file SelectionDAG.cpp.
References getMachineNode(), getTargetConstant(), and llvm::MVT::i32.
Referenced by llvm::SITargetLowering::buildRSRC(), llvm::HexagonTargetLowering::LowerBITCAST(), llvm::HexagonTargetLowering::LowerCONCAT_VECTORS(), LowerF64Op(), lowerGR128Binary(), lowerGR128ToI128(), mayTailCallThisCC(), NarrowVector(), ReplaceCMP_SWAP_128Results(), ReplaceCMP_SWAP_64Results(), llvm::HexagonDAGToDAGISel::SelectIndexedStore(), and llvm::HexagonDAGToDAGISel::SelectVAlign().
Definition at line 628 of file SelectionDAG.h.
Referenced by addStackMapLiveVars(), llvm::AVRDAGToDAGISel::select< ISD::FrameIndex >(), CallingConvSupported(), lowerIncomingStatepointValue(), lowerStatepointMetaArgs(), reservePreviousStackSlotForValue(), llvm::AVRDAGToDAGISel::SelectAddr(), llvm::PPCTargetLowering::SelectAddressRegImm(), llvm::HexagonDAGToDAGISel::SelectAddrFI(), llvm::HexagonDAGToDAGISel::SelectFrameIndex(), and spillIncomingStatepointValue().
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Definition at line 622 of file SelectionDAG.h.
Referenced by addStackMapLiveVars(), llvm::analyzeArguments(), AnalyzeReturnValues(), buildPCRelGlobalAddress(), CallingConvSupported(), CC_Lanai32_VarArg(), llvm::ARMTargetLowering::CCAssignFnForReturn(), llvm::MipsTargetLowering::EmitInstrWithCustomInserter(), llvm::HexagonTargetLowering::GetDynamicTLSAddr(), getEstimate(), llvm::MipsTargetLowering::getGlobalReg(), getMOVL(), llvm::PPCTargetLowering::getPICJumpTableRelocBaseExpr(), llvm::AVRTargetLowering::getSetCCResultType(), llvm::BPFTargetLowering::getTargetNodeName(), llvm::ARCTargetLowering::getTargetNodeName(), GetTLSADDR(), getUnderlyingArgReg(), llvm::ARCTargetLowering::isLegalAddressingMode(), llvm::ARMTargetLowering::isReadOnly(), IsSmallObject(), isTargetConstant(), llvm::X86TargetLowering::LowerAsmOperandForConstraint(), llvm::TargetLowering::LowerAsmOperandForConstraint(), llvm::HexagonTargetLowering::LowerCall(), llvm::SystemZTargetLowering::LowerCall(), llvm::SparcTargetLowering::LowerCall_32(), llvm::SparcTargetLowering::LowerCall_64(), LowerCallResult(), LowerEXTRACT_SUBVECTOR(), llvm::LanaiTargetLowering::LowerGlobalAddress(), llvm::MSP430TargetLowering::LowerGlobalAddress(), llvm::HexagonTargetLowering::LowerGLOBALADDRESS(), llvm::NVPTXTargetLowering::LowerGlobalAddress(), llvm::BPFTargetLowering::LowerOperation(), llvm::RISCVTargetLowering::LowerOperation(), LowerToTLSExecModel(), llvm::HexagonTargetLowering::LowerToTLSGeneralDynamicModel(), llvm::HexagonTargetLowering::LowerToTLSInitialExecModel(), LowerToTLSLocalDynamicModel(), llvm::HexagonTargetLowering::LowerToTLSLocalExecModel(), LowerWRITE_REGISTER(), mayTailCallThisCC(), PrepareCall(), llvm::R600TargetLowering::ReplaceNodeResults(), llvm::HexagonDAGToDAGISel::SelectGlobalAddress(), unpackF64OnRV32DSoftABI(), and llvm::SparcTargetLowering::withTargetFlags().
SDValue SelectionDAG::getTargetIndex | ( | int | Index, |
EVT | VT, | ||
int64_t | Offset = 0 , |
||
unsigned char | TargetFlags = 0 |
||
) |
Definition at line 1453 of file SelectionDAG.cpp.
References llvm::FoldingSetNodeID::AddInteger(), AddNodeIDNode(), E, getVTList(), llvm::None, and llvm::ISD::TargetIndex.
SDValue SelectionDAG::getTargetInsertSubreg | ( | int | SRIdx, |
const SDLoc & | DL, | ||
EVT | VT, | ||
SDValue | Operand, | ||
SDValue | Subreg | ||
) |
A convenience function for creating TargetInstrInfo::INSERT_SUBREG nodes.
getTargetInsertSubreg - A convenience function for creating TargetOpcode::INSERT_SUBREG nodes.
Definition at line 7831 of file SelectionDAG.cpp.
References getMachineNode(), getTargetConstant(), and llvm::MVT::i32.
Referenced by LowerF64Op(), and mayTailCallThisCC().
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Definition at line 633 of file SelectionDAG.h.
References llvm::AMDGPU::HSAMD::Kernel::Arg::Key::Align, and C.
Referenced by CallingConvSupported(), expandf64Toi32(), llvm::MipsTargetLowering::getGlobalReg(), llvm::XCoreTargetLowering::getJumpTableEncoding(), llvm::HexagonTargetLowering::getPICJumpTableRelocBase(), llvm::PPCTargetLowering::getPICJumpTableRelocBaseExpr(), llvm::ARCTargetLowering::getTargetNodeName(), LowerEXTRACT_SUBVECTOR(), llvm::LanaiTargetLowering::LowerJumpTable(), llvm::MSP430TargetLowering::LowerJumpTable(), llvm::HexagonTargetLowering::LowerJumpTable(), and mayTailCallThisCC().
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Definition at line 404 of file SelectionDAG.h.
Referenced by AddCombineBUILD_VECTORToVPADDL(), AddCombineToVPADD(), AddCombineVUZPToVPADDL(), llvm::RegsForValue::AddInlineAsmOperands(), addStackMapLiveVars(), buildFromShuffleMostly(), llvm::TargetLowering::BuildSDIVPow2(), calculateByteProvider(), CallingConvSupported(), CanCombineFCOPYSIGN_EXTEND_ROUND(), llvm::ARMTargetLowering::CCAssignFnForReturn(), combineBEXTR(), combineConcatVectorOfExtracts(), combineConcatVectorOfScalars(), combineExtractSubvector(), combineFMA(), combineFMinNumFMaxNum(), combineFneg(), combineGatherScatter(), combineLoad(), combineLogicBlendIntoPBLENDV(), combineMaskedLoad(), combineMaskedStore(), combineMOVMSK(), combineMulToPMADDWD(), combineParity(), combinePMULDQ(), combineSelect(), combineSelectOfTwoConstants(), combineShuffle(), combineShuffleToFMAddSub(), combineStore(), combineToExtendVectorInReg(), combineTruncatedArithmetic(), combineTruncateWithSat(), combineVectorShiftImm(), combineVectorShiftVar(), combineVSelectToBLENDV(), combineVSelectWithAllOnesOrZeros(), combineX86INT_TO_FP(), combineX86ShuffleChain(), ConvertCarryFlagToBooleanCarry(), llvm::SelectionDAGBuilder::CopyValueToVirtualRegister(), EltsFromConsecutiveLoads(), llvm::XCoreTargetLowering::EmitInstrWithCustomInserter(), llvm::AArch64SelectionDAGInfo::EmitTargetCodeForMemset(), llvm::X86SelectionDAGInfo::EmitTargetCodeForMemset(), ExpandBITCAST(), expandf64Toi32(), findMatchingInlineAsmOperand(), findUnwindDestinations(), FoldCONCAT_VECTORS(), FoldIntToFPToInt(), foldXorTruncShiftIntoCmp(), getAddressForMemoryInput(), getConstVector(), getCopyFromParts(), getCopyFromPartsVector(), llvm::SelectionDAGBuilder::getCopyFromRegs(), llvm::RegsForValue::getCopyFromRegs(), getCopyToParts(), getCopyToPartsVector(), llvm::RegsForValue::getCopyToRegs(), llvm::SelectionDAGBuilder::getFrameIndexTy(), getHexagonLowering(), getLimitedPrecisionExp2(), getLoadStackGuard(), getMad64_32(), getMemCmpLoad(), getMemcpyLoadsAndStores(), getMemmoveLoadsAndStores(), getMemsetStores(), getMemsetValue(), GetNegatedExpression(), llvm::SDNode::getOperationName(), GetRegistersForValue(), getUnderlyingArgReg(), getUniformBase(), llvm::SelectionDAGBuilder::getValueImpl(), hasOnlySelectUsers(), isAddSubOrSubAdd(), isBLACompatibleAddress(), isConsecutiveLSLoc(), isFloatingPointZero(), isLowerSaturatingConditional(), isVectorReductionOp(), isWordAligned(), LowerADDC_ADDE_SUBC_SUBE(), LowerADDSUBCARRY(), LowerBITCAST(), lowerBuildVectorAsBroadcast(), lowerBuildVectorToBitOp(), llvm::SelectionDAGBuilder::LowerCallTo(), LowerCTPOP(), LowerFPOWI(), LowerFSINCOS(), llvm::SelectionDAGBuilder::lowerInvokable(), LowerLoad(), LowerMemOpCallTo(), LowerStore(), LowerTruncateVecI1(), LowerUINT_TO_FP_i64(), LowerVASTART(), lowerVectorShuffle(), lowerVectorShuffleAsElementInsertion(), lowerVectorShuffleAsShift(), LowerVSETCC(), LowerXALUO(), LowerXOR(), llvm::BaseIndexOffset::match(), mayTailCallThisCC(), narrowExtractedVectorBinOp(), narrowExtractedVectorLoad(), llvm::ScheduleDAGSDNodes::newSUnit(), numVectorEltsOrZero(), patchMatchingInput(), PerformADDCombineWithOperands(), PerformANDCombine(), PerformARMBUILD_VECTORCombine(), llvm::AMDGPUTargetLowering::PerformDAGCombine(), performExtendCombine(), PerformExtendCombine(), PerformLOADCombine(), performORCombine(), PerformORCombine(), performSelectCombine(), PerformShiftCombine(), PerformSTORECombine(), performTBISimplification(), PerformVECTOR_SHUFFLECombine(), PerformXORCombine(), PrepareCall(), PromoteMaskArithmetic(), recoverFramePointer(), reduceBuildVecToShuffleWithZero(), scalarizeExtractedBinop(), selectI64Imm(), llvm::TargetLowering::CallLoweringInfo::setLibCallee(), llvm::SelectionDAGBuilder::ShouldEmitAsBranches(), shouldTransformMulToShiftsAddsSubs(), simplifyDivRem(), simplifyI24(), tryToElideArgumentCopy(), VerifyDAGDiverence(), llvm::SelectionDAGBuilder::visitBitTestCase(), llvm::SelectionDAGBuilder::visitBitTestHeader(), llvm::SelectionDAGBuilder::visitJumpTable(), llvm::SelectionDAGBuilder::visitJumpTableHeader(), llvm::SelectionDAGBuilder::visitSPDescriptorFailure(), llvm::SelectionDAGBuilder::visitSPDescriptorParent(), WinDBZCheckDenominator(), and XFormVExtractWithShuffleIntoLoad().
SDValue llvm::SelectionDAG::getTargetMemSDNode | ( | SDVTList | VTs, |
ArrayRef< SDValue > | Ops, | ||
const SDLoc & | dl, | ||
EVT | MemVT, | ||
MachineMemOperand * | MMO | ||
) |
Return (create a new or find existing) a target-specific node.
TargetMemSDNode should be derived class from MemSDNode.
Compose node ID and try to find an existing node.
Existing node was not found. Create a new one.
Definition at line 1655 of file SelectionDAG.h.
References llvm::FoldingSetNodeID::AddInteger(), llvm::FoldingSetNodeID::AddPointer(), E, llvm::MachinePointerInfo::getAddrSpace(), llvm::SDLoc::getDebugLoc(), llvm::SDLoc::getIROrder(), getOpcode(), llvm::MachineMemOperand::getPointerInfo(), llvm::FoldingSetImpl< T >::InsertNode(), N, and llvm::SDVTList::VTs.
Referenced by EmitMaskedTruncSStore(), EmitTruncSStore(), LowerMGATHER(), LowerMSCATTER(), and llvm::X86TargetLowering::ReplaceNodeResults().
SDValue SelectionDAG::getTruncStore | ( | SDValue | Chain, |
const SDLoc & | dl, | ||
SDValue | Val, | ||
SDValue | Ptr, | ||
MachinePointerInfo | PtrInfo, | ||
EVT | SVT, | ||
unsigned | Alignment = 0 , |
||
MachineMemOperand::Flags | MMOFlags = MachineMemOperand::MONone , |
||
const AAMDNodes & | AAInfo = AAMDNodes() |
||
) |
Definition at line 6775 of file SelectionDAG.cpp.
References assert(), getEVTAlignment(), getMachineFunction(), llvm::MachineFunction::getMachineMemOperand(), llvm::EVT::getStoreSize(), llvm::SDValue::getValueType(), InferPointerInfo(), llvm::PointerUnion< PT1, PT2 >::isNull(), llvm::MachineMemOperand::MOLoad, llvm::MachineMemOperand::MOStore, llvm::MVT::Other, and llvm::MachinePointerInfo::V.
Referenced by chainLoadsAndStoresForMemcpy(), EnsureStackAlignment(), llvm::TargetLowering::expandUnalignedLoad(), llvm::TargetLowering::expandUnalignedStore(), getExpandedMinMaxOps(), GetFPLibCall(), getFPTernOp(), getMemcpyLoadsAndStores(), getShiftAmountTyForConstant(), getVectorCompareInfo(), haveEfficientBuildVectorPattern(), isWordAligned(), LowerINTRINSIC_W_CHAIN(), operator!=(), PrepareCall(), llvm::R600TargetLowering::ReplaceNodeResults(), llvm::TargetLowering::scalarizeVectorStore(), ShrinkLoadReplaceStoreWithStore(), llvm::AMDGPUTargetLowering::SplitVectorStore(), and llvm::HexagonDAGToDAGISel::StoreInstrForLoadIntrinsic().
SDValue SelectionDAG::getTruncStore | ( | SDValue | Chain, |
const SDLoc & | dl, | ||
SDValue | Val, | ||
SDValue | Ptr, | ||
EVT | SVT, | ||
MachineMemOperand * | MMO | ||
) |
Definition at line 6797 of file SelectionDAG.cpp.
References llvm::FoldingSetNodeID::AddInteger(), AddNodeIDNode(), assert(), llvm::EVT::bitsLT(), E, llvm::MachinePointerInfo::getAddrSpace(), llvm::SDLoc::getDebugLoc(), llvm::SDLoc::getIROrder(), llvm::MachineMemOperand::getPointerInfo(), llvm::EVT::getRawBits(), llvm::EVT::getScalarType(), getStore(), getUNDEF(), llvm::SDValue::getValueType(), llvm::EVT::getVectorNumElements(), getVTList(), llvm::EVT::isInteger(), llvm::EVT::isVector(), NewSDValueDbgMsg(), llvm::MVT::Other, llvm::ISD::STORE, llvm::RegState::Undef, and llvm::ISD::UNINDEXED.
Return an UNDEF node. UNDEF does not have a useful SDLoc.
Definition at line 852 of file SelectionDAG.h.
References llvm::ISD::UNDEF.
Referenced by addShuffleForVecExtend(), buildFromShuffleMostly(), buildMergeScalars(), buildScalarToVector(), buildVector(), calculateByteProvider(), CallingConvSupported(), CollectOpsToWiden(), combineBasicSADPattern(), combineBitcast(), combineBitcastvxi1(), combineBVOfConsecutiveLoads(), combineConcatVectorOfExtracts(), combineExtractWithShuffle(), combineInsertSubvector(), combineMaskedLoad(), combineMaskedLoadConstantMask(), combineMaskedStore(), combineSetCCAtomicArith(), combineShuffleOfConcatUndef(), combineShuffleOfScalars(), combineStore(), combineTargetShuffle(), combineToExtendVectorInReg(), combineVectorPack(), combineX86ShuffleChain(), combineX86ShufflesRecursively(), CompactSwizzlableVector(), concatSubVectors(), ConstantBuildVector(), constructRetValue(), convertLocVTToValVT(), convertShiftLeftToScale(), createMMXBuildVector(), EltsFromConsecutiveLoads(), emitNonHSAIntrinsicError(), emitRemovedIntrinsicError(), EmitTruncSStore(), ExpandBVWithShuffles(), ExpandHorizontalBinOp(), ExtendToType(), ExtractBitFromMaskVector(), findMatchingInlineAsmOperand(), findUser(), foldBitcastedFPLogic(), FoldBUILD_VECTOR(), FoldCONCAT_VECTORS(), FoldConstantArithmetic(), FoldConstantVectorArithmetic(), FoldSetCC(), fp16SrcZerosHighBits(), getBuildDwordsVector(), getConstVector(), getCopyFromPartsVector(), getExpandedMinMaxOps(), getExtLoad(), GetFPLibCall(), getGeneralPermuteNode(), getHopForBuildVector(), getLoad(), getMOVL(), getNode(), GetPromotionOpcode(), getShiftAmountTyForConstant(), getShuffleScalarElt(), getShuffleVectorZeroOrUndef(), getStore(), llvm::SystemZTargetLowering::getTargetNodeName(), getTargetVShiftNode(), getTruncStore(), getUnderlyingArgReg(), llvm::SelectionDAGBuilder::getValueImpl(), getVectorShuffle(), hasOnlySelectUsers(), insert1BitVector(), isAddSubOrSubAdd(), isBooleanFlip(), isFNEG(), isHopBuildVector(), isHorizontalBinOpPart(), isSETCCorConvertedSETCC(), IsSingleInstrConstant(), IsSplatVector(), isTruncateOf(), joinDwords(), LowerAsSplatVectorLoad(), LowerAVXCONCAT_VECTORS(), LowerAVXExtend(), llvm::HexagonTargetLowering::LowerBITCAST(), LowerBITCAST(), LowerBITREVERSE_XOP(), LowerBUILD_VECTORAsVariablePermute(), LowerBUILD_VECTORvXi1(), LowerBuildVectorv16i8(), LowerBuildVectorv4x32(), llvm::HexagonTargetLowering::LowerCONCAT_VECTORS(), LowerCONCAT_VECTORS(), LowerCONCAT_VECTORSvXi1(), LowerEXTEND_VECTOR_INREG(), LowerEXTRACT_SUBVECTOR(), lowerFCMPIntrinsic(), llvm::R600TargetLowering::LowerFormalArguments(), llvm::SITargetLowering::LowerFormalArguments(), LowerFP_EXTEND(), LowerI64IntToFP_AVX512DQ(), lowerICMPIntrinsic(), llvm::MipsTargetLowering::lowerLOAD(), LowerLoad(), LowerMSCATTER(), LowerMUL(), LowerMULH(), LowerSCALAR_TO_VECTOR(), LowerShift(), lowerShuffleAsRepeatedMaskAndLanePermute(), LowerSIGN_EXTEND(), LowerSIGN_EXTEND_Mask(), LowerStore(), LowerTruncateVecI1(), LowerTruncateVectorStore(), lowerUINT_TO_FP_v2i32(), llvm::AMDGPUTargetLowering::lowerUnhandledCall(), lowerV16I8VectorShuffle(), lowerV2F64VectorShuffle(), lowerV2X128VectorShuffle(), lowerV4X128VectorShuffle(), llvm::HexagonTargetLowering::LowerVECTOR_SHUFFLE(), LowerVECTOR_SHUFFLE(), lowerVectorShuffle(), lowerVectorShuffleAsBlend(), lowerVectorShuffleAsBlendAndPermute(), lowerVectorShuffleAsBlendOfPSHUFBs(), lowerVectorShuffleAsByteRotateAndPermute(), lowerVectorShuffleAsDecomposedShuffleBlend(), lowerVectorShuffleAsElementInsertion(), lowerVectorShuffleAsLanePermuteAndBlend(), lowerVectorShuffleAsLanePermuteAndPermute(), lowerVectorShuffleAsPermuteAndUnpack(), lowerVectorShuffleAsSpecificZeroOrAnyExtend(), lowerVectorShuffleAsUNPCKAndPermute(), lowerVectorShuffleWithPSHUFB(), lowerVectorShuffleWithSSE4A(), lowerVectorShuffleWithUndefHalf(), LowerZERO_EXTEND_Mask(), matchBinaryPermuteVectorShuffle(), matchBinaryVectorShuffle(), matchVectorShuffleAsInsertPS(), matchVectorShuffleWithUNPCK(), mayTailCallThisCC(), narrowExtractedVectorLoad(), NormalizeBuildVector(), numVectorEltsOrZero(), parseTexFail(), partitionShuffleOfConcats(), PerformARMBUILD_VECTORCombine(), llvm::R600TargetLowering::PerformDAGCombine(), PerformSTORECombine(), PerformVECTOR_SHUFFLECombine(), PrepareCall(), llvm::AArch64TargetLowering::ReconstructShuffle(), reduceBuildVecToShuffleWithZero(), reduceVMULWidth(), ReplaceBITCASTResults(), llvm::X86TargetLowering::ReplaceNodeResults(), replaceShuffleOfInsert(), scalarizeExtractedBinop(), ShrinkLoadReplaceStoreWithStore(), llvm::TargetLowering::SimplifyDemandedBits(), llvm::TargetLowering::SimplifyDemandedVectorElts(), llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(), simplifyDivRem(), llvm::TargetLowering::SimplifySetCC(), simplifyShift(), splitAndLowerVectorShuffle(), SplitVSETCC(), tryBuildVectorShuffle(), tryFoldToZero(), tryToFoldExtendOfConstant(), widenSubVector(), widenVec(), WidenVector(), widenVectorToPartType(), and XFormVExtractWithShuffleIntoLoad().
SDValue SelectionDAG::getVAArg | ( | EVT | VT, |
const SDLoc & | dl, | ||
SDValue | Chain, | ||
SDValue | Ptr, | ||
SDValue | SV, | ||
unsigned | Align | ||
) |
VAArg produces a result and token chain, and takes a pointer and a source value as input.
Definition at line 7060 of file SelectionDAG.cpp.
References getNode(), getTargetConstant(), getVTList(), llvm::MVT::i32, llvm::MVT::Other, and llvm::ISD::VAARG.
Referenced by findMatchingInlineAsmOperand(), GetFPLibCall(), and getShiftAmountTyForConstant().
Definition at line 1484 of file SelectionDAG.cpp.
References llvm::EVT::getSimpleVT(), llvm::EVT::isExtended(), llvm::EVT::isSimple(), and llvm::MVT::SimpleTy.
Referenced by llvm::analyzeArguments(), AnalyzeReturnValues(), llvm::X86TargetLowering::BuildFILD(), calculateByteProvider(), CC_Lanai32_VarArg(), CollectOpsToWiden(), combineShiftRightArithmetic(), combineVectorTruncationWithPACKSS(), ConstantAddressBlock(), convertLocVTToValVT(), llvm::SITargetLowering::copyToM0(), llvm::X86SelectionDAGInfo::EmitTargetCodeForMemcpy(), llvm::X86SelectionDAGInfo::EmitTargetCodeForMemset(), EnsureStackAlignment(), llvm::PPCTargetLowering::expandVSXStoreForLE(), FoldBUILD_VECTOR(), foldExtendedSignBitTest(), getAArch64Cmp(), getCopyFromParts(), llvm::RegsForValue::getCopyFromRegs(), getExpandedMinMaxOps(), getLoadExtOrTrunc(), getNode(), getPermuteMask(), getShiftAmountTyForConstant(), isAnyConstantBuildVector(), isSortedByValueNo(), isTruncateOf(), llvm::SITargetLowering::isTypeDesirableForOp(), llvm::SparcTargetLowering::LowerCall_64(), llvm::SITargetLowering::LowerCallResult(), llvm::AMDGPUTargetLowering::LowerDIVREM24(), llvm::SITargetLowering::LowerFormalArguments(), llvm::SparcTargetLowering::LowerFormalArguments_32(), llvm::SparcTargetLowering::LowerFormalArguments_64(), lowerMSACopyIntr(), lowerMSAStoreIntr(), llvm::BPFTargetLowering::LowerOperation(), llvm::SelectionDAGBuilder::lowerRangeToAssertZExt(), llvm::MSP430TargetLowering::LowerShifts(), llvm::MSP430TargetLowering::LowerSIGN_EXTEND(), llvm::AMDGPUTargetLowering::LowerSIGN_EXTEND_INREG(), lowerUINT_TO_FP_vec(), LowerVASTART(), llvm::ARMTargetLowering::PerformCMOVCombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), llvm::AMDGPUTargetLowering::PerformDAGCombine(), llvm::PPCTargetLowering::PerformDAGCombine(), PrepareCall(), PromoteMaskArithmetic(), llvm::R600TargetLowering::ReplaceNodeResults(), llvm::X86TargetLowering::ReplaceNodeResults(), UnpackFromArgumentSlot(), and widenVec().
SDValue SelectionDAG::getVectorShuffle | ( | EVT | VT, |
const SDLoc & | dl, | ||
SDValue | N1, | ||
SDValue | N2, | ||
ArrayRef< int > | Mask | ||
) |
Return an ISD::VECTOR_SHUFFLE node.
The number of elements in VT, which must be a vector type, must match the number of mask elements NumElts. An integer mask element equal to -1 is treated as undefined.
Definition at line 1546 of file SelectionDAG.cpp.
References llvm::FoldingSetNodeID::AddInteger(), AddNodeIDNode(), llvm::all_of(), llvm::BumpPtrAllocatorImpl< AllocatorT, SlabSize, SizeThreshold >::Allocate(), assert(), llvm::ArrayRef< T >::begin(), llvm::ISD::BITCAST, C, commuteShuffle(), llvm::copy(), E, llvm::ArrayRef< T >::end(), llvm::SDLoc::getDebugLoc(), llvm::SDLoc::getIROrder(), getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOperand(), getSplatBuildVector(), llvm::BuildVectorSDNode::getSplatValue(), getUNDEF(), llvm::SDValue::getValueType(), llvm::EVT::getVectorNumElements(), getVTList(), llvm::TargetLoweringBase::hasVectorBlend(), llvm::SDValue::isUndef(), NewSDValueDbgMsg(), llvm::BitVector::none(), llvm::ArrayRef< T >::size(), and llvm::ISD::VECTOR_SHUFFLE.
Referenced by addShuffleForVecExtend(), buildFromShuffleMostly(), BuildVSLDOI(), CollectOpsToWiden(), combineBasicSADPattern(), combineBVOfConsecutiveLoads(), combineConcatVectorOfExtracts(), combineHorizontalMinMaxResult(), combineInsertSubvector(), combineMaskedLoad(), combineMaskedStore(), combineSelect(), combineShuffle(), combineShuffleOfConcatUndef(), combineShuffleOfSplat(), combineStore(), combineToExtendBoolVectorInReg(), convertShiftLeftToScale(), createVariablePermute(), EltsFromConsecutiveLoads(), ExpandBVWithShuffles(), ExtractBitFromMaskVector(), foldBitcastedFPLogic(), GeneratePerfectShuffle(), getCommutedVectorShuffle(), getExpandedMinMaxOps(), getMOVL(), getShuffleVectorZeroOrUndef(), getUnpackh(), getUnpackl(), getVectorCompareInfo(), hasOnlySelectUsers(), InsertBitToMaskVector(), isBSwapHWordElement(), isFNEG(), isSETCCorConvertedSETCC(), IsSingleInstrConstant(), lower1BitVectorShuffle(), lower256BitVectorShuffle(), LowerAsSplatVectorLoad(), LowerBUILD_VECTORAsVariablePermute(), LowerBuildVectorv4x32(), LowerEXTEND_VECTOR_INREG(), LowerLoad(), LowerMUL(), LowerMULH(), LowerRotate(), LowerScalarImmediateShift(), LowerScalarVariableShift(), LowerShift(), lowerShuffleAsRepeatedMaskAndLanePermute(), LowerSIGN_EXTEND(), LowerTruncateVecI1(), LowerUINT_TO_FP_i64(), lowerV16I8VectorShuffle(), lowerV2I64VectorShuffle(), lowerV4I32VectorShuffle(), lowerVectorShuffle(), lowerVectorShuffleAsBlend(), lowerVectorShuffleAsBlendAndPermute(), lowerVectorShuffleAsByteRotateAndPermute(), lowerVectorShuffleAsDecomposedShuffleBlend(), lowerVectorShuffleAsElementInsertion(), lowerVectorShuffleAsLanePermuteAndBlend(), lowerVectorShuffleAsLanePermuteAndPermute(), lowerVectorShuffleAsPermuteAndUnpack(), lowerVectorShuffleAsSpecificZeroOrAnyExtend(), lowerVectorShuffleAsUNPCKAndPermute(), lowerVectorShuffleByMerging128BitLanes(), lowerVectorShuffleWithUndefHalf(), lowerVSELECTtoVectorShuffle(), LowerVSETCC(), partitionShuffleOfConcats(), performConcatVectorsCombine(), performSelectCombine(), PerformSTORECombine(), PerformVECTOR_SHUFFLECombine(), llvm::AArch64TargetLowering::ReconstructShuffle(), reduceBuildVecToShuffleWithZero(), reduceVMULWidth(), llvm::X86TargetLowering::ReplaceNodeResults(), replaceShuffleOfInsert(), scalarizeExtractedBinop(), ShrinkLoadReplaceStoreWithStore(), simplifyDivRem(), splitAndLowerVectorShuffle(), truncateVectorWithPACK(), widenVec(), and XFormVExtractWithShuffleIntoLoad().
SDDbgValue * SelectionDAG::getVRegDbgValue | ( | DIVariable * | Var, |
DIExpression * | Expr, | ||
unsigned | VReg, | ||
bool | IsIndirect, | ||
const DebugLoc & | DL, | ||
unsigned | O | ||
) |
Creates a VReg SDDbgValue node.
VReg.
Definition at line 7891 of file SelectionDAG.cpp.
References assert(), llvm::SDDbgInfo::getAlloc(), and llvm::SDDbgValue::VREG.
Referenced by getUnderlyingArgReg().
Return an SDVTList that represents the list of values specified.
Definition at line 7239 of file SelectionDAG.cpp.
References makeVTList().
Referenced by AddCombineTo64bitMLAL(), AddCombineTo64BitSMLAL16(), AddCombineTo64bitUMAAL(), addStackMapLiveVars(), adjustLoadValueTypeImpl(), llvm::analyzeArguments(), AnalyzeReturnValues(), llvm::X86TargetLowering::BuildFILD(), llvm::TargetLowering::BuildSDIV(), llvm::TargetLowering::BuildUDIV(), CallingConvSupported(), CC_Lanai32_VarArg(), llvm::ARMTargetLowering::CCAssignFnForReturn(), checkVSELConstraints(), CloneNodeWithValues(), CollectOpsToWiden(), combineADC(), combineAddOrSubToADCOrSBB(), combineADDToADDZE(), CombineBaseUpdate(), combineBVOfVecSExt(), combineCMP(), combineMinNumMaxNum(), combineParity(), combineSBB(), CombineVLDDUP(), ConstantBuildVector(), ConvertBooleanCarryToCarryFlag(), ConvertCarryFlagToBooleanCarry(), ConvertSelectToConcatVector(), createLoadLR(), createStoreLR(), EltsFromConsecutiveLoads(), emitCLC(), emitComparison(), llvm::XCoreTargetLowering::EmitInstrWithCustomInserter(), emitIntrinsicWithCCAndChain(), EmitKORTEST(), EmitMaskedTruncSStore(), llvm::SystemZSelectionDAGInfo::EmitTargetCodeForMemchr(), llvm::BPFSelectionDAGInfo::EmitTargetCodeForMemcpy(), llvm::X86SelectionDAGInfo::EmitTargetCodeForMemcpy(), llvm::ARMSelectionDAGInfo::EmitTargetCodeForMemcpy(), llvm::X86SelectionDAGInfo::EmitTargetCodeForMemset(), llvm::SystemZSelectionDAGInfo::EmitTargetCodeForStrcmp(), llvm::SystemZSelectionDAGInfo::EmitTargetCodeForStrcpy(), EmitTest(), EmitTruncSStore(), Expand64BitShift(), ExpandBITCAST(), expandf64Toi32(), llvm::TargetLowering::expandMUL_LOHI(), ExpandREAD_REGISTER(), llvm::PPCTargetLowering::expandVSXLoadForLE(), llvm::PPCTargetLowering::expandVSXStoreForLE(), findMatchingInlineAsmOperand(), findUser(), GeneratePerfectShuffle(), getAArch64XALUOOp(), llvm::MipsTargetLowering::getAddrGPRel(), getAddrSpaceCast(), getAsCarry(), getAtomic(), getAVX2GatherNode(), getBasicBlock(), getBlockAddress(), getBoundedStrlen(), getConstant(), getConstantFP(), getConstantPool(), llvm::RegsForValue::getCopyFromRegs(), getDivRemArgList(), llvm::HexagonTargetLowering::GetDynamicTLSAddr(), getExpandedMinMaxOps(), getExtendedControlRegister(), getFPBinOp(), getFPTernOp(), getFrameIndex(), getGatherNode(), getGlobalAddress(), getIndexedStore(), getJumpTable(), llvm::ARMTargetLowering::getJumpTableEncoding(), getLabelNode(), getLoad(), getMachineNode(), getMad64_32(), getMaskedLoad(), getMaskedStore(), getMDNode(), getMergeValues(), getMOVL(), getMul24(), getNode(), getReadPerformanceCounter(), getReadTimeStampCounter(), getReductionSDNode(), getRegister(), getRegisterMask(), getScatterNode(), getShiftAmountTyForConstant(), getSrcValue(), getStore(), getTargetIndex(), llvm::ARCTargetLowering::getTargetNodeName(), GetTLSADDR(), getTOCEntry(), getTruncStore(), getUnderlyingArgReg(), getUniformBase(), getVAArg(), getVectorCompareInfo(), getVectorShuffle(), getX86XALUOOp(), hasOnlySelectUsers(), haveEfficientBuildVectorPattern(), llvm::intCCToAVRCC(), isADDADDMUL(), isFloatingPointZero(), llvm::ARMTargetLowering::isReadOnly(), isSETCCorConvertedSETCC(), isTruncateOf(), isTruncWithZeroHighBitsInput(), isWordAligned(), LowerABS(), LowerADDC_ADDE_SUBC_SUBE(), LowerADDSUBCARRY(), LowerADJUST_TRAMPOLINE(), lowerAtomicArithWithLOCK(), llvm::HexagonTargetLowering::LowerCall(), llvm::SITargetLowering::LowerCall(), llvm::SystemZTargetLowering::LowerCall(), llvm::NVPTXTargetLowering::LowerCall(), llvm::SparcTargetLowering::LowerCall_32(), llvm::SparcTargetLowering::LowerCall_64(), LowerCallResult(), LowerCMP_SWAP(), LowerCTLZ(), LowerCTTZ(), llvm::HexagonTargetLowering::LowerDYNAMIC_STACKALLOC(), lowerFCOPYSIGN64(), LowerFSINCOS(), llvm::SparcTargetLowering::LowerGlobalTLSAddress(), LowerInterruptReturn(), LowerINTRINSIC_W_CHAIN(), LowerMGATHER(), LowerMSCATTER(), llvm::BPFTargetLowering::LowerOperation(), llvm::RISCVTargetLowering::LowerOperation(), llvm::SystemZTargetLowering::LowerOperationWrapper(), llvm::HexagonTargetLowering::LowerREADCYCLECOUNTER(), llvm::NVPTXTargetLowering::LowerReturn(), llvm::AMDGPUTargetLowering::LowerSDIVREM(), llvm::LanaiTargetLowering::LowerSELECT_CC(), llvm::MSP430TargetLowering::LowerSELECT_CC(), llvm::MSP430TargetLowering::LowerSETCC(), LowerSETCCCARRY(), LowerToTLSExecModel(), llvm::AMDGPUTargetLowering::LowerUDIVREM64(), lowerUINT_TO_FP_vec(), LowerVECTOR_SHUFFLE(), LowerVectorINT_TO_FP(), LowerXALUO(), mayTailCallThisCC(), llvm::X86TargetLowering::needsFixedCatchObjects(), NegateCC(), parseTexFail(), llvm::ARMTargetLowering::PerformCMOVCombine(), performCONDCombine(), llvm::PPCTargetLowering::PerformDAGCombine(), performIntegerAbsCombine(), performNEONPostLDSTCombine(), performPostLD1Combine(), PerformSETCCCombine(), PerformUMLALCombine(), PerformVDUPCombine(), pickOpcodeForVT(), PrepareCall(), recoverFramePointer(), ReplaceCMP_SWAP_128Results(), ReplaceCMP_SWAP_64Results(), ReplaceINTRINSIC_W_CHAIN(), ReplaceLoadVector(), ReplaceLongIntrinsic(), llvm::R600TargetLowering::ReplaceNodeResults(), llvm::PPCTargetLowering::ReplaceNodeResults(), llvm::X86TargetLowering::ReplaceNodeResults(), ReplaceREADCYCLECOUNTER(), llvm::SelectionDAGISel::SelectCodeCommon(), SelectNodeTo(), llvm::HexagonDAGToDAGISel::SelectTypecast(), unpackF64OnRV32DSoftABI(), llvm::SelectionDAGBuilder::visitBitTestCase(), and widenVec().
Return the expression required to zero extend the Op value assuming it was the smaller SrcTy value.
Definition at line 1127 of file SelectionDAG.cpp.
References llvm::ISD::AND, assert(), getConstant(), llvm::APInt::getLowBitsSet(), getNode(), llvm::EVT::getScalarType(), llvm::SDValue::getScalarValueSizeInBits(), llvm::EVT::getSizeInBits(), llvm::SDValue::getValueType(), and llvm::EVT::isVector().
Referenced by combineExtSetcc(), ConstantAddressBlock(), getExpandedMinMaxOps(), getLoadExtOrTrunc(), getShiftAmountTyForConstant(), isAnyConstantBuildVector(), isTruncateOf(), llvm::HexagonTargetLowering::LowerBITCAST(), llvm::MSP430TargetLowering::LowerShifts(), llvm::AMDGPUTargetLowering::PerformDAGCombine(), PromoteMaskArithmetic(), llvm::R600TargetLowering::ReplaceNodeResults(), and replaceShuffleOfInsert().
Convert Op, which must be of integer type, to the integer type VT, by either zero-extending or truncating it.
Definition at line 1112 of file SelectionDAG.cpp.
References llvm::EVT::bitsGT(), getNode(), llvm::SDValue::getValueType(), llvm::ISD::TRUNCATE, and llvm::ISD::ZERO_EXTEND.
Referenced by combineBitcast(), combineBitcastvxi1(), combineCompareEqual(), combineExtractWithShuffle(), combineMinNumMaxNum(), combineSelect(), combineShuffleOfScalars(), combineSubToSubus(), createVariablePermute(), llvm::SystemZSelectionDAGInfo::EmitTargetCodeForMemchr(), llvm::SystemZSelectionDAGInfo::EmitTargetCodeForStrnlen(), foldAddSubBoolOfMaskedVal(), FoldCONCAT_VECTORS(), generateEquivalentSub(), getExpandedMinMaxOps(), getMad64_32(), getMemCmpLoad(), getShiftAmountOperand(), getShiftAmountTyForConstant(), getUnderlyingArgReg(), llvm::TargetLowering::getVectorElementPointer(), hasOnlySelectUsers(), llvm::TargetLowering::IncrementMemoryAddress(), isTruncateOf(), llvm::SITargetLowering::isTypeDesirableForOp(), isVectorReductionOp(), llvm::HexagonTargetLowering::LowerBITCAST(), LowerBITCAST(), LowerBuildVectorv16i8(), LowerFGETSIGN(), llvm::AMDGPUTargetLowering::LowerFP_TO_FP16(), LowerINTRINSIC_W_CHAIN(), LowerMULH(), llvm::SystemZTargetLowering::LowerOperationWrapper(), LowerShift(), lowerX86CmpEqZeroToCtlzSrl(), llvm::AMDGPUTargetLowering::performMulCombine(), llvm::AMDGPUTargetLowering::performMulhuCombine(), llvm::AMDGPUTargetLowering::performShlCombine(), llvm::AMDGPUTargetLowering::performTruncateCombine(), llvm::X86TargetLowering::ReplaceNodeResults(), ShrinkLoadReplaceStoreWithStore(), simplifyDivRem(), tryFoldToZero(), llvm::SelectionDAGBuilder::visitBitTestCase(), llvm::SelectionDAGBuilder::visitBitTestHeader(), and llvm::SelectionDAGBuilder::visitJumpTableHeader().
|
inline |
Return true if there are any SDDbgValue nodes associated with this SelectionDAG.
Definition at line 1359 of file SelectionDAG.h.
References llvm::SDDbgInfo::empty().
Referenced by llvm::ScheduleDAGSDNodes::EmitSchedule().
Return true if A and B have no common bits set.
As an example, this can allow an 'add' to be transformed into an 'or'.
Definition at line 3978 of file SelectionDAG.cpp.
References assert(), computeKnownBits(), llvm::SDValue::getValueType(), and llvm::KnownBits::Zero.
Referenced by foldAddSubOfSignBit().
Infer alignment of a load / store address.
InferPtrAlignment - Infer alignment of a load / store address.
Return 0 if it cannot be inferred.
Definition at line 9001 of file SelectionDAG.cpp.
References llvm::AMDGPU::HSAMD::Kernel::Arg::Key::Align, llvm::computeKnownBits(), llvm::KnownBits::countMinTrailingZeros(), llvm::SDValue::getConstantOperandVal(), llvm::SDValue::getNode(), llvm::MachineFrameInfo::getObjectAlignment(), llvm::SDValue::getOperand(), llvm::GlobalValue::getType(), and llvm::MinAlign().
Referenced by llvm::ARMTargetLowering::CCAssignFnForReturn(), llvm::TargetLowering::computeKnownBitsForFrameIndex(), getMemCmpLoad(), getMemcpyLoadsAndStores(), getMemmoveLoadsAndStores(), LowerAsSplatVectorLoad(), numVectorEltsOrZero(), and ShrinkLoadReplaceStoreWithStore().
void SelectionDAG::init | ( | MachineFunction & | NewMF, |
OptimizationRemarkEmitter & | NewORE, | ||
Pass * | PassPtr, | ||
const TargetLibraryInfo * | LibraryInfo, | ||
LegacyDivergenceAnalysis * | Divergence | ||
) |
Prepare this SelectionDAG to process code in the given MachineFunction.
Definition at line 1002 of file SelectionDAG.cpp.
References llvm::Function::getContext(), llvm::MachineFunction::getFunction(), llvm::TargetSubtargetInfo::getSelectionDAGInfo(), getSubtarget(), and llvm::TargetSubtargetInfo::getTargetLowering().
Referenced by llvm::SelectionDAGISel::runOnMachineFunction().
Return true if the specified operand is an ISD::ADD with a ConstantSDNode on the right-hand side, or if it is an ISD::OR with a ConstantSDNode that is guaranteed to have the same semantics as an ADD.
This handles the equivalence: X|Cst == X+Cst iff X&Cst = 0.
Definition at line 3800 of file SelectionDAG.cpp.
References llvm::ISD::ADD, llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), MaskedValueIsZero(), and llvm::ISD::OR.
Referenced by getBaseWithConstantOffset(), isWordAligned(), LowerAsSplatVectorLoad(), replaceZeroVectorStore(), and llvm::AVRDAGToDAGISel::SelectAddr().
Test whether the given value is a constant FP or similar node.
Definition at line 9257 of file SelectionDAG.cpp.
References assert(), llvm::checkForCycles(), llvm::SDValue::getNode(), I, llvm::ISD::isBuildVectorOfConstantFPSDNodes(), llvm::max(), llvm::FoldingSetBase::Node::Node(), llvm::MVT::Other, llvm::SDNode::SDNodeBits, and llvm::ArrayRef< T >::size().
Test whether the given value is a constant int or similar node.
Definition at line 9243 of file SelectionDAG.cpp.
References llvm::SDValue::getNode(), llvm::ISD::GlobalAddress, and llvm::ISD::isBuildVectorOfConstantSDNodes().
Referenced by calculateByteProvider(), combineCCMask(), combinePMULDQ(), foldAddSubOfSignBit(), foldFPToIntToFP(), isAnyConstantBuildVector(), isBSwapHWordElement(), isTruncateOf(), salvageDebugInfo(), ShrinkLoadReplaceStoreWithStore(), simplifyDivRem(), stripConstantMask(), and tryFoldToZero().
N
is any kind of constant or build_vector of constants, int or float. If a vector, it may not necessarily be a splat. Definition at line 1595 of file SelectionDAG.h.
References isConstantFPBuildVectorOrConstantFP().
Referenced by llvm::AMDGPUTargetLowering::performSelectCombine(), and simplifySelect().
Test whether two SDValues are known to compare equal.
This is true if they are the same value, or if one is negative zero and the other positive zero.
Definition at line 3963 of file SelectionDAG.cpp.
Referenced by combineSelect().
Test whether the given SDValue is known to never be NaN.
If SNaN
is true, returns if Op
is known to never be a signaling NaN (it may still be a qNaN).
Definition at line 3813 of file SelectionDAG.cpp.
References llvm::ISD::BUILTIN_OP_END, C, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::ISD::FABS, llvm::ISD::FADD, llvm::ISD::FCANONICALIZE, llvm::ISD::FCEIL, llvm::ISD::FCOPYSIGN, llvm::ISD::FCOS, llvm::ISD::FDIV, llvm::ISD::FEXP, llvm::ISD::FEXP2, llvm::ISD::FFLOOR, llvm::ISD::FLOG, llvm::ISD::FLOG10, llvm::ISD::FLOG2, llvm::ISD::FMA, llvm::ISD::FMAD, llvm::ISD::FMAXIMUM, llvm::ISD::FMAXNUM, llvm::ISD::FMAXNUM_IEEE, llvm::ISD::FMINIMUM, llvm::ISD::FMINNUM, llvm::ISD::FMINNUM_IEEE, llvm::ISD::FMUL, llvm::ISD::FNEARBYINT, llvm::ISD::FNEG, llvm::ISD::FP_EXTEND, llvm::ISD::FP_ROUND, llvm::ISD::FPOW, llvm::ISD::FPOWI, llvm::ISD::FREM, llvm::ISD::FRINT, llvm::ISD::FROUND, llvm::ISD::FSIN, llvm::ISD::FSQRT, llvm::ISD::FSUB, llvm::ISD::FTRUNC, llvm::SDNode::getFlags(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), getTarget(), llvm::SDNodeFlags::hasNoNaNs(), llvm::ISD::INTRINSIC_VOID, llvm::ISD::INTRINSIC_W_CHAIN, llvm::ISD::INTRINSIC_WO_CHAIN, llvm::TargetLowering::isKnownNeverNaNForTargetNode(), isKnownNeverSNaN(), llvm::ISD::SELECT, llvm::ISD::SINT_TO_FP, and llvm::ISD::UINT_TO_FP.
Referenced by combineSelect(), llvm::AMDGPUTargetLowering::isKnownNeverNaNForTargetNode(), llvm::SITargetLowering::isKnownNeverNaNForTargetNode(), and isLegalToCombineMinNumMaxNum().
Op
is known to never be a signaling NaN. Definition at line 1496 of file SelectionDAG.h.
References A, B, llvm::Depth, llvm::haveNoCommonBitsSet(), llvm::isKnownNeverNaN(), and llvm::ARM_MB::LD.
Referenced by getSplatConstantFP(), llvm::SITargetLowering::isCanonicalized(), and isKnownNeverNaN().
Test whether the given SDValue is known to contain non-zero value(s).
Definition at line 3941 of file SelectionDAG.cpp.
References assert(), C, llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getValueType(), llvm::EVT::isFloatingPoint(), llvm::ConstantSDNode::isNullValue(), llvm::ISD::matchUnaryPredicate(), and llvm::ISD::OR.
Referenced by calculateByteProvider(), LowerShift(), and simplifyDivRem().
Test whether the given floating point SDValue is known to never be positive or negative zero.
Definition at line 3930 of file SelectionDAG.cpp.
References assert(), C, llvm::SDValue::getValueType(), and llvm::EVT::isFloatingPoint().
Referenced by combineSelect().
Test if the given value is known to have exactly one bit set.
This differs from computeKnownBits in that it doesn't necessarily determine which bit is set.
Definition at line 3234 of file SelectionDAG.cpp.
References llvm::all_of(), llvm::ISD::BUILD_VECTOR, C, computeKnownBits(), llvm::KnownBits::countMaxPopulation(), llvm::KnownBits::countMinPopulation(), E, llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::SDValue::getValueType(), llvm::isConstOrConstSplat(), llvm::SDNode::ops(), llvm::ISD::SHL, and llvm::ISD::SRL.
Referenced by llvm::TargetLowering::isExtendedTrueVal(), simplifyDivRem(), and tryFoldToZero().
Test whether V
has a splatted value for all the demanded elements.
isSplatValue - Return true if the vector V has the same value across all DemandedElts.
On success UndefElts
will indicate the elements that have UNDEF values instead of the splat value, this is only guaranteed to be correct for DemandedElts
.
NOTE: The function will return true for a demanded splat of UNDEF values.
Definition at line 2153 of file SelectionDAG.cpp.
References llvm::ISD::ADD, llvm::ISD::AND, assert(), llvm::ISD::BUILD_VECTOR, llvm::dyn_cast(), llvm::ISD::EXTRACT_SUBVECTOR, llvm::APInt::extractBits(), llvm::ConstantSDNode::getAPIntValue(), llvm::APInt::getBitWidth(), llvm::APInt::getNullValue(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getValueType(), llvm::EVT::getVectorNumElements(), llvm::ConstantSDNode::getZExtValue(), llvm::SDValue::isUndef(), llvm::EVT::isVector(), llvm::BitmaskEnumDetail::Mask(), llvm::APInt::shl(), llvm::ISD::SUB, llvm::APInt::ule(), llvm::ISD::VECTOR_SHUFFLE, and llvm::APInt::zextOrSelf().
Referenced by isSplatValue(), IsSplatVector(), and LowerRotate().
Test whether V
has a splatted value.
Helper wrapper to main isSplatValue function.
Definition at line 2236 of file SelectionDAG.cpp.
References assert(), llvm::APInt::getAllOnesValue(), llvm::SDValue::getValueType(), llvm::EVT::getVectorNumElements(), isSplatValue(), and llvm::EVT::isVector().
Return true if the result of this operation is always undefined.
Definition at line 4548 of file SelectionDAG.cpp.
References llvm::any_of(), assert(), llvm::ISD::isBuildVectorOfConstantSDNodes(), llvm::isNullConstant(), llvm::ISD::SDIV, llvm::ArrayRef< T >::size(), llvm::ISD::SREM, llvm::ISD::UDIV, and llvm::ISD::UREM.
Referenced by FoldConstantArithmetic(), FoldConstantVectorArithmetic(), and simplifyDivRem().
void SelectionDAG::Legalize | ( | ) |
This transforms the SelectionDAG into a SelectionDAG that is compatible with the target instruction selector, as indicated by the TargetLowering object.
This is the entry point for the file.
Note that this is an involved process that may invalidate pointers into the graph.
Definition at line 4546 of file LegalizeDAG.cpp.
References E, llvm::SmallPtrSetImpl< PtrType >::erase(), llvm::SmallPtrSetImpl< PtrType >::insert(), N, and llvm::SDNode::use_empty().
bool SelectionDAG::LegalizeOp | ( | SDNode * | N, |
SmallSetVector< SDNode *, 16 > & | UpdatedNodes | ||
) |
Transforms a SelectionDAG node and any operands to it into a node that is compatible with the target instruction selector, as indicated by the TargetLowering object.
N
is a valid, legal node after calling this.This essentially runs a single recursive walk of the Legalize
process over the given node (and its operands). This can be used to incrementally legalize the DAG. All of the nodes which are directly replaced, potentially including N, are added to the output parameter UpdatedNodes
so that the delta to the DAG can be understood by the caller.
When this returns false, N has been legalized in a way that make the pointer passed in no longer valid. It may have even been deleted from the DAG, and so it shouldn't be used further. When this returns true, the N passed in is a legal node, and can be immediately processed as such. This may still have done some work on the DAG, and will still populate UpdatedNodes with any new nodes replacing those originally in the DAG.
Definition at line 4595 of file LegalizeDAG.cpp.
References llvm::SmallPtrSetImpl< PtrType >::count(), and llvm::SmallPtrSetImpl< PtrType >::insert().
bool SelectionDAG::LegalizeTypes | ( | ) |
This transforms the SelectionDAG into a SelectionDAG that only uses types natively supported by the target.
Returns "true" if it made any changes.
Note that this is an involved process that may invalidate pointers into the graph.
Definition at line 1114 of file LegalizeTypes.cpp.
References llvm::DAGTypeLegalizer::DAGTypeLegalizer().
bool SelectionDAG::LegalizeVectors | ( | ) |
This transforms the SelectionDAG into a SelectionDAG that only uses vector math operations supported by the target.
This is necessary as a separate step from Legalize because unrolling a vector operation can introduce illegal types, which requires running LegalizeTypes again.
This returns true if it made any changes; in that case, LegalizeTypes is called again before Legalize.
Note that this is an involved process that may invalidate pointers into the graph.
Definition at line 1295 of file LegalizeVectorOps.cpp.
SDValue SelectionDAG::makeEquivalentMemoryOrdering | ( | LoadSDNode * | Old, |
SDValue | New | ||
) |
If an existing load has uses of its chain, create a token factor node with that chain and the new memory node's chain and update users of the old chain to the token factor.
This ensures that the new memory node will have the same relative memory dependency position as the old load. Returns the new merged load chain.
Definition at line 8506 of file SelectionDAG.cpp.
References assert(), llvm::SDValue::getNode(), getNode(), llvm::SDNode::hasAnyUseOfValue(), llvm::MVT::Other, ReplaceAllUsesOfValueWith(), llvm::ISD::TokenFactor, and UpdateNodeOperands().
Referenced by combineStore(), EltsFromConsecutiveLoads(), lowerVectorShuffleAsBroadcast(), and narrowExtractedVectorLoad().
Return true if 'Op & Mask' is known to be zero.
MaskedValueIsZero - Return true if 'V & Mask' is known to be zero.
We use this predicate to simplify operations downstream. Op and Mask are known to be the same type.
We use this predicate to simplify operations downstream. Mask is known to be zero for bits that V cannot have.
Definition at line 2146 of file SelectionDAG.cpp.
References computeKnownBits(), and llvm::APInt::isSubsetOf().
Referenced by calculateByteProvider(), llvm::SelectionDAGISel::CheckAndMask(), combineAnd(), combineMulToPMADDWD(), combineMulToPMULDQ(), combineVectorPack(), llvm::XCoreTargetLowering::EmitInstrWithCustomInserter(), llvm::XCoreSelectionDAGInfo::EmitTargetCodeForMemcpy(), llvm::TargetLowering::expandMUL_LOHI(), generateEquivalentSub(), GetDemandedBits(), getFauxShuffleMask(), getFPTernOp(), getVectorCompareInfo(), isADDADDMUL(), isBaseWithConstantOffset(), isBSwapHWordElement(), isTruncateOf(), isTruncWithZeroHighBitsInput(), LowerAndToBT(), llvm::AMDGPUTargetLowering::LowerUDIVREM64(), llvm::BaseIndexOffset::match(), matchVectorShuffleWithPACK(), llvm::PPCTargetLowering::PerformDAGCombine(), PerformORCombineToBFI(), PerformShiftCombine(), performSRLCombine(), ShrinkLoadReplaceStoreWithStore(), SignBitIsZero(), simplifyDivRem(), llvm::TargetLowering::SimplifySetCC(), and tryFoldToZero().
SDValue SelectionDAG::matchBinOpReduction | ( | SDNode * | Extract, |
ISD::NodeType & | BinOp, | ||
ArrayRef< ISD::NodeType > | CandidateBinOps | ||
) |
Match a binop + shuffle pyramid that represents a horizontal reduction over the elements of a vector starting from the EXTRACT_VECTOR_ELT node /p Extract.
The reduction must use one of the opcodes listed in /p CandidateBinOps and on success /p BinOp will contain the matching opcode. Returns the vector that is being reduced on, or SDValue() if a reduction was not matched.
Definition at line 8849 of file SelectionDAG.cpp.
References llvm::dyn_cast(), llvm::ISD::EXTRACT_VECTOR_ELT, llvm::ShuffleVectorSDNode::getMaskElt(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::SDValue::getValueType(), llvm::EVT::getVectorNumElements(), llvm::isNullConstant(), llvm::Log2_32(), and llvm::none_of().
Referenced by combineBasicSADPattern(), combineHorizontalMinMaxResult(), and combineHorizontalPredicateResult().
SDNode * SelectionDAG::MorphNodeTo | ( | SDNode * | N, |
unsigned | Opc, | ||
SDVTList | VTs, | ||
ArrayRef< SDValue > | Ops | ||
) |
This mutates the specified node to have the specified return type, opcode, and operands.
MorphNodeTo - This mutates the specified node to have the specified return type, opcode, and operands.
Note that MorphNodeTo returns the resultant node. If there is already a node of the specified opcode and operands, it returns that node instead of the current one. Note that the SDLoc need not be the same.
Using MorphNodeTo is faster than creating a new node and swapping it in with ReplaceAllUsesWith both because it often avoids allocating a new node, and because it doesn't require CSE recalculation for any of the node's users.
However, note that MorphNodeTo recursively deletes dead nodes from the DAG. As a consequence it isn't appropriate to use from within the DAG combiner or the legalizer which maintain worklists that would need to be updated when deleting things.
Definition at line 7576 of file SelectionDAG.cpp.
References AddNodeIDNode(), E, llvm::SmallPtrSetImplBase::empty(), llvm::SDUse::getNode(), llvm::MVT::Glue, I, llvm::SmallPtrSetImpl< PtrType >::insert(), N, llvm::SDVTList::NumVTs, llvm::SDNode::op_begin(), llvm::SDNode::op_end(), llvm::SmallVectorTemplateBase< T >::push_back(), RemoveDeadNodes(), llvm::SDNode::use_empty(), and llvm::SDVTList::VTs.
Referenced by CloneNodeWithValues(), SelectNodeTo(), and llvm::HexagonDAGToDAGISel::SelectTypecast().
Mutate the specified strict FP node to its non-strict equivalent, unlinking the node from its chain and dropping the metadata arguments.
The node must be a strict FP node.
Definition at line 7629 of file SelectionDAG.cpp.
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delete |
void SelectionDAG::RemoveDeadNode | ( | SDNode * | N | ) |
Remove the specified node from the system.
If any of its operands then becomes dead, remove them as well. Inform UpdateListener for each node deleted.
Definition at line 729 of file SelectionDAG.cpp.
References llvm::NVPTXISD::Dummy, getRoot(), and RemoveDeadNodes().
Referenced by llvm::AVRDAGToDAGISel::select< AVRISD::CALL >(), llvm::AVRDAGToDAGISel::select< ISD::BRIND >(), llvm::AVRDAGToDAGISel::select< ISD::LOAD >(), llvm::AVRDAGToDAGISel::select< ISD::STORE >(), llvm::SelectionDAGISel::IsLegalToFold(), llvm::SITargetLowering::legalizeTargetIndependentNode(), llvm::SelectionDAGISel::ReplaceNode(), llvm::HexagonDAGToDAGISel::SelectBrevLdIntrinsic(), llvm::SelectionDAGISel::SelectCodeCommon(), llvm::AVRDAGToDAGISel::selectIndexedLoad(), llvm::HexagonDAGToDAGISel::SelectIndexedLoad(), llvm::HexagonDAGToDAGISel::SelectIndexedStore(), llvm::HexagonDAGToDAGISel::SelectIntrinsicWChain(), llvm::HexagonDAGToDAGISel::SelectNewCircIntrinsic(), SelectNodeTo(), llvm::HvxSelector::selectVAlign(), and llvm::HexagonDAGToDAGISel::tryLoadOfLoadIntrinsic().
void SelectionDAG::RemoveDeadNodes | ( | ) |
This method deletes all unreachable nodes in the SelectionDAG.
RemoveDeadNodes - This method deletes all unreachable nodes in the SelectionDAG.
Definition at line 675 of file SelectionDAG.cpp.
References llvm::NVPTXISD::Dummy, and getRoot().
Referenced by GetVBR(), isPermutation(), isTargetConstant(), MorphNodeTo(), and RemoveDeadNode().
void SelectionDAG::RemoveDeadNodes | ( | SmallVectorImpl< SDNode *> & | DeadNodes | ) |
This method deletes the unreachable nodes in the given list, and any nodes that become unreachable as a result.
RemoveDeadNodes - This method deletes the unreachable nodes in the given list, and any nodes that become unreachable as a result.
Definition at line 695 of file SelectionDAG.cpp.
References llvm::ISD::DELETED_NODE, E, llvm::SmallVectorBase::empty(), llvm::SDUse::getNode(), llvm::SDNode::getOpcode(), I, N, llvm::SelectionDAG::DAGUpdateListener::Next, llvm::SDNode::op_begin(), llvm::SDNode::op_end(), llvm::SmallVectorImpl< T >::pop_back_val(), llvm::SmallVectorTemplateBase< T >::push_back(), and llvm::SDNode::use_empty().
void SelectionDAG::ReplaceAllUsesOfValuesWith | ( | const SDValue * | From, |
const SDValue * | To, | ||
unsigned | Num | ||
) |
Like ReplaceAllUsesOfValueWith, but for multiple values at once.
ReplaceAllUsesOfValuesWith - Replace any uses of From with To, leaving uses of other values produced by From.getNode() alone.
This correctly handles the case where there is an overlap between the From values and the To values.
The same value may appear in both the From and To list. The Deleted vector is handled the same way as for ReplaceAllUsesWith.
Definition at line 8346 of file SelectionDAG.cpp.
References E, llvm::SDValue::getNode(), llvm::SDValue::getResNo(), llvm::SDUse::getResNo(), llvm::SmallVectorTemplateBase< T >::push_back(), ReplaceAllUsesOfValueWith(), llvm::SmallVectorBase::size(), llvm::sort(), transferDbgValues(), llvm::SDNode::use_begin(), and llvm::SDNode::use_end().
Referenced by addStackMapLiveVars(), llvm::SelectionDAGISel::ReplaceUses(), and ShrinkLoadReplaceStoreWithStore().
Replace any uses of From with To, leaving uses of other values produced by From.getNode() alone.
ReplaceAllUsesOfValueWith - Replace any uses of From with To, leaving uses of other values produced by From.getNode() alone.
The Deleted vector is handled the same way as for ReplaceAllUsesWith.
Definition at line 8195 of file SelectionDAG.cpp.
References llvm::SDValue::getNode(), llvm::SDNode::getNumValues(), llvm::SDValue::getResNo(), llvm::SDUse::getResNo(), getRoot(), llvm::SDNode::use_iterator::getUse(), llvm::SDNode::isDivergent(), llvm::operator<(), ReplaceAllUsesWith(), setRoot(), transferDbgValues(), updateDivergence(), llvm::SDNode::use_begin(), and llvm::SDNode::use_end().
Referenced by AddCombineTo64bitMLAL(), AddCombineTo64BitSMLAL16(), AddCombineTo64bitUMAAL(), adjustSubwordCmp(), calculateByteProvider(), canFoldInAddressingMode(), combineSetCCAtomicArith(), combineSIntToFP(), combineVSelectToBLENDV(), ConvertSelectToConcatVector(), emitIntrinsicWithCCAndChain(), EmitTest(), ExtendUsesToFormExtLoad(), findUser(), foldBitcastedFPLogic(), foldExtendedSignBitTest(), generateEquivalentSub(), getCCResult(), isAnyConstantBuildVector(), isSlicingProfitable(), isTruncateOf(), lowerAtomicArith(), LowerCMP_SWAP(), llvm::HexagonTargetLowering::LowerDYNAMIC_STACKALLOC(), makeEquivalentMemoryOrdering(), numVectorEltsOrZero(), llvm::PPCTargetLowering::PerformDAGCombine(), performDivRemCombine(), performIntToFpCombine(), PerformORCombineToSMULWBT(), llvm::AMDGPUTargetLowering::performStoreCombine(), PerformVDUPCombine(), PrepareCall(), ReplaceAllUsesOfValuesWith(), llvm::R600TargetLowering::ReplaceNodeResults(), llvm::SelectionDAGISel::ReplaceUses(), ShrinkLoadReplaceStoreWithStore(), simplifyDivRem(), SkipExtensionForVMULL(), tryToFoldExtOfExtload(), and tryToFoldExtOfLoad().
Modify anything using 'From' to use 'To' instead.
ReplaceAllUsesWith - Modify anything using 'From' to use 'To' instead.
This can cause recursive merging of nodes in the DAG. Use the first version if 'From' is known to have a single result, use the second if you have two nodes with identical results (or if 'To' has a superset of the results of 'From'), use the third otherwise.
These methods all take an optional UpdateListener, which (if not null) is informed about nodes that are deleted and modified due to recursive changes in the dag.
These functions only replace all existing uses. It's possible that as these replacements are being performed, CSE may cause the From node to be given new uses. These new uses of From are left in place, and not automatically transferred to To.
This can cause recursive merging of nodes in the DAG.
This version assumes From has a single result value.
Definition at line 8041 of file SelectionDAG.cpp.
References assert(), From, llvm::SDValue::getNode(), llvm::SDNode::getNumValues(), llvm::SDValue::getResNo(), getRoot(), llvm::SDNode::use_iterator::getUse(), llvm::SDNode::isDivergent(), setRoot(), transferDbgValues(), updateDivergence(), llvm::SDNode::use_begin(), and llvm::SDNode::use_end().
Referenced by addStackMapLiveVars(), ConstantBuildVector(), EmitVectorComparison(), ExpandBITCAST(), findUser(), foldMaskAndShiftToExtract(), foldMaskAndShiftToScale(), foldMaskedShiftToBEXTR(), foldMaskedShiftToScaledMask(), getInputChainForNode(), isAnyConstantBuildVector(), isMemOPCandidate(), isTargetConstant(), llvm::SITargetLowering::legalizeTargetIndependentNode(), LowerMSCATTER(), PerformBFICombine(), performCONDCombine(), llvm::AMDGPUTargetLowering::performFNegCombine(), ReplaceAllUsesOfValueWith(), ReplaceAllUsesWith(), llvm::SelectionDAGISel::ReplaceNode(), llvm::SelectionDAGISel::ReplaceUses(), SelectNodeTo(), simplifyDivRem(), and VerifySDNode().
ReplaceAllUsesWith - Modify anything using 'From' to use 'To' instead.
This can cause recursive merging of nodes in the DAG.
This version assumes that for each value of From, there is a corresponding value in To in the same position with the same type.
Definition at line 8092 of file SelectionDAG.cpp.
References assert(), getNode(), llvm::SDNode::getNumValues(), getRoot(), llvm::SDNode::use_iterator::getUse(), llvm::SDNode::getValueType(), llvm::SDNode::hasAnyUseOfValue(), llvm::SDNode::isDivergent(), setRoot(), transferDbgValues(), updateDivergence(), llvm::SDNode::use_begin(), and llvm::SDNode::use_end().
ReplaceAllUsesWith - Modify anything using 'From' to use 'To' instead.
This can cause recursive merging of nodes in the DAG.
This version can replace From with any result values. To must match the number and types of values returned by From.
Definition at line 8148 of file SelectionDAG.cpp.
References getNode(), llvm::SDNode::getNumValues(), llvm::SDUse::getResNo(), getRoot(), llvm::SDNode::use_iterator::getUse(), llvm::SDNode::isDivergent(), ReplaceAllUsesWith(), setRoot(), transferDbgValues(), updateDivergence(), llvm::SDNode::use_begin(), and llvm::SDNode::use_end().
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inline |
Move node N in the AllNodes list to be immediately before the given iterator Position.
This may be used to update the topological ordering when the list of nodes is modified.
Definition at line 1326 of file SelectionDAG.h.
References llvm::iplist_impl< simple_ilist< T, Options... >, ilist_traits< T > >::insert(), and llvm::iplist_impl< simple_ilist< T, Options... >, ilist_traits< T > >::remove().
Referenced by insertDAGNode().
void SelectionDAG::salvageDebugInfo | ( | SDNode & | N | ) |
To be invoked on an SDNode that is slated to be erased.
This function mirrors llvm::salvageDebugInfo
.
Definition at line 7961 of file SelectionDAG.cpp.
References llvm::ISD::ADD, AddDbgValue(), llvm::dbgs(), llvm::SDNode::dumprFull(), llvm::SDNode::getConstantOperandVal(), getDbgValue(), GetDbgValues(), llvm::SDNode::getHasDebugValue(), llvm::SDValue::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::SDValue::getResNo(), isConstantIntBuildVectorOrConstantInt(), LLVM_DEBUG, llvm::DIExpression::NoDeref, llvm::DIExpression::prepend(), llvm::SmallVectorTemplateBase< T >::push_back(), and llvm::DIExpression::WithStackValue.
Referenced by llvm::SelectionDAGISel::SelectCodeCommon().
These are used for target selectors to mutate the specified node to have the specified return type, Target opcode, and operands.
SelectNodeTo - These are wrappers around MorphNodeTo that accept a machine opcode.
Note that target opcodes are stored as ~TargetOpcode in the node opcode field. The resultant node is returned.
Definition at line 7469 of file SelectionDAG.cpp.
References getVTList(), and llvm::None.
Referenced by llvm::AVRDAGToDAGISel::select< ISD::FrameIndex >(), llvm::SelectionDAGISel::IsLegalToFold(), SelectNodeTo(), tryBitfieldInsertOpFromOr(), and tryBitfieldInsertOpFromOrAndImm().
Definition at line 7475 of file SelectionDAG.cpp.
References getVTList(), and SelectNodeTo().
SDNode * SelectionDAG::SelectNodeTo | ( | SDNode * | N, |
unsigned | MachineOpc, | ||
EVT | VT, | ||
SDValue | Op1, | ||
SDValue | Op2 | ||
) |
Definition at line 7482 of file SelectionDAG.cpp.
References getVTList(), and SelectNodeTo().
SDNode * SelectionDAG::SelectNodeTo | ( | SDNode * | N, |
unsigned | MachineOpc, | ||
EVT | VT, | ||
SDValue | Op1, | ||
SDValue | Op2, | ||
SDValue | Op3 | ||
) |
Definition at line 7490 of file SelectionDAG.cpp.
References getVTList(), and SelectNodeTo().
SDNode * SelectionDAG::SelectNodeTo | ( | SDNode * | N, |
unsigned | MachineOpc, | ||
EVT | VT, | ||
ArrayRef< SDValue > | Ops | ||
) |
Definition at line 7498 of file SelectionDAG.cpp.
References getVTList(), and SelectNodeTo().
Definition at line 7510 of file SelectionDAG.cpp.
References getVTList(), llvm::None, and SelectNodeTo().
SDNode * SelectionDAG::SelectNodeTo | ( | SDNode * | N, |
unsigned | MachineOpc, | ||
EVT | VT1, | ||
EVT | VT2, | ||
ArrayRef< SDValue > | Ops | ||
) |
Definition at line 7504 of file SelectionDAG.cpp.
References getVTList(), and SelectNodeTo().
SDNode * SelectionDAG::SelectNodeTo | ( | SDNode * | N, |
unsigned | MachineOpc, | ||
EVT | VT1, | ||
EVT | VT2, | ||
EVT | VT3, | ||
ArrayRef< SDValue > | Ops | ||
) |
Definition at line 7516 of file SelectionDAG.cpp.
References getVTList(), and SelectNodeTo().
SDNode* llvm::SelectionDAG::SelectNodeTo | ( | SDNode * | N, |
unsigned | TargetOpc, | ||
EVT | VT1, | ||
EVT | VT2, | ||
SDValue | Op1 | ||
) |
SDNode * SelectionDAG::SelectNodeTo | ( | SDNode * | N, |
unsigned | MachineOpc, | ||
EVT | VT1, | ||
EVT | VT2, | ||
SDValue | Op1, | ||
SDValue | Op2 | ||
) |
Definition at line 7523 of file SelectionDAG.cpp.
References getVTList(), and SelectNodeTo().
SDNode * SelectionDAG::SelectNodeTo | ( | SDNode * | N, |
unsigned | MachineOpc, | ||
SDVTList | VTs, | ||
ArrayRef< SDValue > | Ops | ||
) |
Definition at line 7531 of file SelectionDAG.cpp.
References llvm::SDNode::getDebugLoc(), llvm::SDLoc::getDebugLoc(), llvm::SDNode::getIROrder(), llvm::SDLoc::getIROrder(), MorphNodeTo(), N, llvm::CodeGenOpt::None, RemoveDeadNode(), ReplaceAllUsesWith(), llvm::SDNode::setDebugLoc(), llvm::SDNode::setIROrder(), and llvm::SDNode::setNodeId().
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inline |
Definition at line 390 of file SelectionDAG.h.
References clear().
Set graph attributes for a node. (eg. "color=red".)
setGraphAttrs - Set graph attributes for a node.
(eg. "color=red".)
Definition at line 182 of file SelectionDAGPrinter.cpp.
References llvm::AMDGPU::HSAMD::Kernel::Key::Attrs, llvm::errs(), and N.
Convenience for setting node color attribute.
setGraphColor - Convenience for setting node color attribute.
Definition at line 212 of file SelectionDAGPrinter.cpp.
References llvm::SDNodeIterator::begin(), llvm::dbgs(), llvm::SDNodeIterator::end(), llvm::errs(), llvm::detail::DenseSetImpl< ValueT, DenseMap< ValueT, detail::DenseSetEmpty, ValueInfoT, detail::DenseSetPair< ValueT > >, ValueInfoT >::insert(), LLVM_DEBUG, N, and llvm::detail::DenseSetImpl< ValueT, DenseMap< ValueT, detail::DenseSetEmpty, ValueInfoT, detail::DenseSetPair< ValueT > >, ValueInfoT >::size().
void SelectionDAG::setNodeMemRefs | ( | MachineSDNode * | N, |
ArrayRef< MachineMemOperand *> | NewMemRefs | ||
) |
Mutate the specified machine node's memory references to the provided list.
Definition at line 7445 of file SelectionDAG.cpp.
References llvm::MachineSDNode::clearMemRefs(), llvm::copy(), llvm::ArrayRef< T >::empty(), and llvm::ArrayRef< T >::size().
Referenced by llvm::AVRDAGToDAGISel::select< ISD::LOAD >(), llvm::AVRDAGToDAGISel::select< ISD::STORE >(), CloneNodeWithValues(), parseTexFail(), pickOpcodeForVT(), ReplaceCMP_SWAP_128Results(), ReplaceCMP_SWAP_64Results(), llvm::HexagonDAGToDAGISel::SelectBrevLdIntrinsic(), llvm::SelectionDAGISel::SelectCodeCommon(), llvm::HexagonDAGToDAGISel::SelectIndexedLoad(), llvm::HexagonDAGToDAGISel::SelectIndexedStore(), and llvm::X86InstrInfo::unfoldMemoryOperand().
Set the current root tag of the SelectionDAG.
Definition at line 466 of file SelectionDAG.h.
References assert(), llvm::checkForCycles(), getConstant(), llvm::SDValue::getNode(), llvm::SDValue::getValueType(), N, and llvm::MVT::Other.
Referenced by addStackMapLiveVars(), findMatchingInlineAsmOperand(), findUnwindDestinations(), llvm::SelectionDAGBuilder::getControlRoot(), getFPTernOp(), getMemCmpLoad(), llvm::SelectionDAGBuilder::getRoot(), getUnderlyingArgReg(), getUniformBase(), llvm::SelectionDAGBuilder::getValueImpl(), hasOnlySelectUsers(), llvm::SelectionDAGBuilder::LowerCallTo(), llvm::NVPTXTargetLowering::LowerFormalArguments(), lowerIncomingStatepointValue(), llvm::SelectionDAGBuilder::lowerInvokable(), ReplaceAllUsesOfValueWith(), ReplaceAllUsesWith(), llvm::DAGTypeLegalizer::run(), llvm::SelectionDAGBuilder::ShouldEmitAsBranches(), llvm::SelectionDAGBuilder::UpdateSplitBlock(), llvm::SelectionDAGBuilder::visitBitTestCase(), llvm::SelectionDAGBuilder::visitBitTestHeader(), llvm::SelectionDAGBuilder::visitJumpTable(), llvm::SelectionDAGBuilder::visitJumpTableHeader(), llvm::SelectionDAGBuilder::visitSPDescriptorFailure(), llvm::SelectionDAGBuilder::visitSPDescriptorParent(), and llvm::SelectionDAGBuilder::visitSwitchCase().
Convenience for setting subgraph color attribute.
setSubgraphColor - Convenience for setting subgraph color attribute.
Definition at line 256 of file SelectionDAGPrinter.cpp.
References llvm::errs().
Return true if the sign bit of Op is known to be zero.
SignBitIsZero - Return true if the sign bit of Op is known to be zero.
We use this predicate to simplify operations downstream.
Definition at line 2138 of file SelectionDAG.cpp.
References llvm::SDValue::getScalarValueSizeInBits(), llvm::APInt::getSignMask(), and MaskedValueIsZero().
Referenced by calculateByteProvider(), canReduceVMulWidth(), combineGatherScatter(), combineUIntToFP(), foldExtendedSignBitTest(), foldFPToIntToFP(), getCmp(), LowerVSETCC(), and simplifyDivRem().
Try to simplify a select/vselect into 1 of its operands or a constant.
Definition at line 7006 of file SelectionDAG.cpp.
References F(), isConstantValueOfAnyType(), llvm::SDValue::isUndef(), and T.
Referenced by combineMinNumMaxNum(), combineSelect(), ConvertSelectToConcatVector(), and getNode().
Try to simplify a shift into 1 of its operands or a constant.
Definition at line 7036 of file SelectionDAG.cpp.
References getConstant(), llvm::SDValue::getNode(), llvm::SDValue::getScalarValueSizeInBits(), getUNDEF(), llvm::SDValue::getValueType(), llvm::isNullOrNullSplat(), llvm::SDValue::isUndef(), llvm::ISD::matchUnaryPredicate(), and X.
Referenced by calculateByteProvider(), and getNode().
std::pair< SDValue, SDValue > SelectionDAG::SplitVector | ( | const SDValue & | N, |
const SDLoc & | DL, | ||
const EVT & | LoVT, | ||
const EVT & | HiVT | ||
) |
Split the vector with EXTRACT_SUBVECTOR using the provides VTs and return the low/high part.
SplitVector - Split the vector with EXTRACT_SUBVECTOR and return the low/high part.
Definition at line 9054 of file SelectionDAG.cpp.
References assert(), llvm::ISD::EXTRACT_SUBVECTOR, getConstant(), llvm::SDValue::getValueType(), llvm::EVT::getVectorNumElements(), llvm::MipsISD::Hi, and llvm::MipsISD::Lo.
Referenced by combineBitcastvxi1(), ConvertSelectToConcatVector(), getPMOVMSKB(), LowerBITCAST(), llvm::AMDGPUTargetLowering::SplitVectorLoad(), llvm::AMDGPUTargetLowering::SplitVectorStore(), and SplitVSETCC().
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inline |
Split the vector with EXTRACT_SUBVECTOR and return the low/high part.
Definition at line 1566 of file SelectionDAG.h.
References llvm::SDValue::getValueType().
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inline |
Split the node's operand with EXTRACT_SUBVECTOR and return the low/high part.
Definition at line 1574 of file SelectionDAG.h.
References llvm::AMDGPU::HSAMD::Kernel::Key::Args, and llvm::SDNode::getOperand().
Referenced by llvm::X86TargetLowering::ReplaceNodeResults(), ReplaceReductionResults(), llvm::SITargetLowering::splitBinaryVectorOp(), llvm::SITargetLowering::splitUnaryVectorOp(), and SplitVSETCC().
void SelectionDAG::transferDbgValues | ( | SDValue | From, |
SDValue | To, | ||
unsigned | OffsetInBits = 0 , |
||
unsigned | SizeInBits = 0 , |
||
bool | InvalidateDbg = true |
||
) |
Transfer debug values from one node to another, while optionally generating fragment expressions for split-up values.
If InvalidateDbg
is set, debug values are invalidated after they are transferred.
Definition at line 7901 of file SelectionDAG.cpp.
References AddDbgValue(), assert(), llvm::DIExpression::createFragmentExpression(), getDbgValue(), GetDbgValues(), llvm::SDNode::getHasDebugValue(), llvm::SDValue::getNode(), llvm::SDValue::getResNo(), llvm::SmallVectorTemplateBase< T >::push_back(), and llvm::SDDbgValue::SDNODE.
Referenced by getNode(), isTruncateOf(), ReplaceAllUsesOfValuesWith(), ReplaceAllUsesOfValueWith(), and ReplaceAllUsesWith().
Utility function used by legalize and lowering to "unroll" a vector operation by splitting out the scalars and operating on each element individually.
If the ResNE is 0, fully unroll the vector op. If ResNE is less than the width of the vector op, unroll up to ResNE. If the ResNE is greater than the width of the vector op, unroll the vector op and fill the end of the resulting vector with UNDEFS.
Definition at line 8906 of file SelectionDAG.cpp.
References assert(), llvm::ISD::EXTRACT_VECTOR_ELT, llvm::ISD::FP_ROUND_INREG, getConstant(), llvm::SDNode::getFlags(), llvm::SDNode::getNumOperands(), llvm::SDNode::getNumValues(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorVT(), llvm::EVT::isVector(), llvm::AArch64CC::NE, llvm::SmallVectorTemplateBase< T >::push_back(), llvm::ISD::ROTL, llvm::ISD::ROTR, llvm::ISD::SELECT, llvm::ISD::SHL, llvm::ISD::SIGN_EXTEND_INREG, llvm::ISD::SRA, llvm::ISD::SRL, and llvm::ISD::VSELECT.
Referenced by CollectOpsToWiden(), combineCCMask(), isSETCCorConvertedSETCC(), LowerVectorFP_TO_INT(), LowerVectorINT_TO_FP(), llvm::X86TargetLowering::ReplaceNodeResults(), and UnrollVectorShift().
void SelectionDAG::updateDivergence | ( | SDNode * | N | ) |
Definition at line 8274 of file SelectionDAG.cpp.
References allnodes(), llvm::SDValue::getNode(), llvm::SDNode::getNumOperands(), llvm::SDValue::getValueType(), I, llvm::SDNode::isDivergent(), N, llvm::SDNode::ops(), llvm::MVT::Other, llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::reserve(), llvm::SDNode::SDNodeBits, and llvm::SDNode::uses().
Referenced by ReplaceAllUsesOfValueWith(), ReplaceAllUsesWith(), and UpdateNodeOperands().
Mutate the specified node in-place to have the specified operands.
UpdateNodeOperands - Mutate the specified node in-place to have the specified operands.
If the resultant node already exists in the DAG, this does not modify the specified node, instead it returns the node that already exists. If the resultant node does not exist in the DAG, the input node is returned. As a degenerate case, if you specify the same input operands as the node already has, the input node is returned.
Definition at line 7329 of file SelectionDAG.cpp.
References assert(), llvm::SDNode::getNumOperands(), llvm::SDNode::getOperand(), N, and updateDivergence().
Referenced by combineGatherScatter(), getExpandedMinMaxOps(), GetFPLibCall(), getFPTernOp(), getShiftAmountTyForConstant(), isTargetConstant(), isXor1OfSetCC(), llvm::SITargetLowering::legalizeTargetIndependentNode(), makeEquivalentMemoryOrdering(), moveBelowOrigChain(), operator!=(), llvm::PPCTargetLowering::PerformDAGCombine(), PrepareCall(), simplifyDivRem(), and UpdateNodeOperands().
Definition at line 7354 of file SelectionDAG.cpp.
References assert(), llvm::SDNode::getNumOperands(), llvm::SDNode::getOperand(), N, updateDivergence(), and UpdateNodeOperands().
Definition at line 7384 of file SelectionDAG.cpp.
References UpdateNodeOperands().
SDNode * SelectionDAG::UpdateNodeOperands | ( | SDNode * | N, |
SDValue | Op1, | ||
SDValue | Op2, | ||
SDValue | Op3, | ||
SDValue | Op4 | ||
) |
Definition at line 7390 of file SelectionDAG.cpp.
References UpdateNodeOperands().
SDNode * SelectionDAG::UpdateNodeOperands | ( | SDNode * | N, |
SDValue | Op1, | ||
SDValue | Op2, | ||
SDValue | Op3, | ||
SDValue | Op4, | ||
SDValue | Op5 | ||
) |
Definition at line 7397 of file SelectionDAG.cpp.
References UpdateNodeOperands().
Definition at line 7404 of file SelectionDAG.cpp.
References assert(), llvm::ArrayRef< T >::begin(), llvm::ArrayRef< T >::end(), llvm::lltok::equal, llvm::SDNode::getNumOperands(), N, llvm::SDNode::op_begin(), llvm::ArrayRef< T >::size(), and updateDivergence().
void SelectionDAG::VerifyDAGDiverence | ( | ) |
Definition at line 8313 of file SelectionDAG.cpp.
References allnodes(), assert(), llvm::SDValue::getNode(), getTargetLoweringInfo(), llvm::SDValue::getValueType(), llvm::SDNode::isDivergent(), llvm::TargetLowering::isSDNodeAlwaysUniform(), llvm::TargetLowering::isSDNodeSourceOfDivergence(), N, llvm::SDNode::ops(), and llvm::MVT::Other.
void SelectionDAG::viewGraph | ( | const std::string & | Title | ) |
Pop up a GraphViz/gv window with the DAG rendered using 'dot'.
viewGraph - Pop up a ghostview window with the reachable parts of the DAG rendered using 'dot'.
Definition at line 151 of file SelectionDAGPrinter.cpp.
References llvm::errs(), getName(), and ViewGraph().
void SelectionDAG::viewGraph | ( | ) |
Definition at line 164 of file SelectionDAGPrinter.cpp.
|
friend |
DAGUpdateListener is a friend so it can manipulate the listener stack.
Definition at line 325 of file SelectionDAG.h.
Referenced by getDbgLabel(), and IsPredicateKnownToFail().
When true, additional steps are taken to ensure that getConstant() and similar functions return DAG nodes that have legal types.
This is important after type legalization since any illegally typed nodes generated after this point will not experience type legalization.
Definition at line 321 of file SelectionDAG.h.
Referenced by FoldConstantArithmetic(), FoldConstantVectorArithmetic(), and getConstant().
Definition at line 415 of file SelectionDAG.h.