49 if (ARM::tGPRRegClass.hasSubClassEq(RC))
50 return &ARM::tGPRRegClass;
56 unsigned Kind)
const {
59 return &ARM::tGPRRegClass;
64 const DebugLoc &dl,
unsigned DestReg,
65 unsigned SubIdx,
int Val,
84 const DebugLoc &dl,
unsigned DestReg,
85 unsigned SubIdx,
int Val,
97 .addConstantPoolIndex(Idx)
106 const DebugLoc &dl,
unsigned DestReg,
unsigned SubIdx,
int Val,
112 "Thumb1 does not have ldr to high register");
126 const DebugLoc &dl,
unsigned DestReg,
unsigned BaseReg,
int NumBytes,
138 if (NumBytes < 0 && !isHigh && CanChangeCC) {
140 NumBytes = -NumBytes;
142 unsigned LdReg = DestReg;
143 if (DestReg == ARM::SP)
144 assert(BaseReg == ARM::SP &&
"Unexpected!");
148 if (NumBytes <= 255 && NumBytes >= 0 && CanChangeCC) {
149 BuildMI(MBB, MBBI, dl, TII.
get(ARM::tMOVi8), LdReg)
152 .setMIFlags(MIFlags);
153 }
else if (NumBytes < 0 && NumBytes >= -255 && CanChangeCC) {
154 BuildMI(MBB, MBBI, dl, TII.
get(ARM::tMOVi8), LdReg)
157 .setMIFlags(MIFlags);
158 BuildMI(MBB, MBBI, dl, TII.
get(ARM::tRSB), LdReg)
161 .setMIFlags(MIFlags);
163 BuildMI(MBB, MBBI, dl, TII.
get(ARM::t2MOVi32imm), LdReg)
170 int Opc = (isSub) ? ARM::tSUBrr
171 : ((isHigh || !CanChangeCC) ? ARM::tADDhirr : ARM::tADDrr);
173 if (Opc != ARM::tADDhirr)
175 if (DestReg == ARM::SP || isSub)
188 const DebugLoc &dl,
unsigned DestReg,
189 unsigned BaseReg,
int NumBytes,
193 bool isSub = NumBytes < 0;
194 unsigned Bytes = (
unsigned)NumBytes;
195 if (isSub) Bytes = -NumBytes;
198 unsigned CopyBits = 0;
199 unsigned CopyScale = 1;
200 bool CopyNeedsCC =
false;
202 unsigned ExtraBits = 0;
203 unsigned ExtraScale = 1;
204 bool ExtraNeedsCC =
false;
219 if (DestReg == ARM::SP) {
220 if (BaseReg == ARM::SP) {
225 CopyOpc = ARM::tMOVr;
228 ExtraOpc = isSub ? ARM::tSUBspi : ARM::tADDspi;
232 if (BaseReg == ARM::SP) {
234 assert(!isSub &&
"Thumb1 does not have tSUBrSPi");
235 CopyOpc = ARM::tADDrSPi;
238 }
else if (DestReg == BaseReg) {
243 CopyOpc = isSub ? ARM::tSUBi3 : ARM::tADDi3;
248 CopyOpc = ARM::tMOVr;
251 ExtraOpc = isSub ? ARM::tSUBi8 : ARM::tADDi8;
255 if (DestReg == BaseReg) {
260 CopyOpc = ARM::tMOVr;
268 assert(((Bytes & 3) == 0 || ExtraScale == 1) &&
269 "Unaligned offset, but all instructions require alignment");
271 unsigned CopyRange = ((1 << CopyBits) - 1) * CopyScale;
273 if (CopyOpc && Bytes < CopyScale) {
274 CopyOpc = ARM::tMOVr;
279 unsigned ExtraRange = ((1 << ExtraBits) - 1) * ExtraScale;
280 unsigned RequiredCopyInstrs = CopyOpc ? 1 : 0;
281 unsigned RangeAfterCopy = (CopyRange > Bytes) ? 0 : (Bytes - CopyRange);
285 assert(RangeAfterCopy % ExtraScale == 0 &&
286 "Extra instruction requires immediate to be aligned");
288 unsigned RequiredExtraInstrs;
290 RequiredExtraInstrs =
alignTo(RangeAfterCopy, ExtraRange) / ExtraRange;
291 else if (RangeAfterCopy > 0)
293 RequiredExtraInstrs = 1000000;
295 RequiredExtraInstrs = 0;
296 unsigned RequiredInstrs = RequiredCopyInstrs + RequiredExtraInstrs;
297 unsigned Threshold = (DestReg == ARM::SP) ? 3 : 2;
300 if (RequiredInstrs > Threshold) {
302 DestReg, BaseReg, NumBytes,
true,
309 unsigned CopyImm = std::min(Bytes, CopyRange) / CopyScale;
310 Bytes -= CopyImm * CopyScale;
316 if (CopyOpc != ARM::tMOVr) {
326 unsigned ExtraImm = std::min(Bytes, ExtraRange) / ExtraScale;
327 Bytes -= ExtraImm * ExtraScale;
360 unsigned FrameRegIdx,
361 unsigned FrameReg,
int &
Offset,
366 "This isn't needed for thumb2!");
373 if (Opcode == ARM::tADDframe) {
385 unsigned ImmIdx = FrameRegIdx + 1;
387 unsigned NumBits = (FrameReg == ARM::SP) ? 8 : 5;
390 Offset += InstrOffs * Scale;
391 assert((Offset & (Scale - 1)) == 0 &&
"Can't encode this offset!");
395 int ImmedOffset = Offset / Scale;
396 unsigned Mask = (1 << NumBits) - 1;
398 if ((
unsigned)Offset <= Mask * Scale) {
406 if (NewOpc != Opcode && FrameReg != ARM::SP)
413 Mask = (1 << NumBits) - 1;
417 if (Opcode == ARM::tLDRspi || Opcode == ARM::tSTRspi) {
421 ImmedOffset = ImmedOffset &
Mask;
423 Offset &= ~(Mask * Scale);
446 assert (Done &&
"Unable to resolve frame index!");
455 unsigned Reg)
const {
459 return ARMBaseRegisterInfo::saveScavengerRegister(MBB, I, UseMI, RC, Reg);
478 if (II->isDebugInstr())
481 for (
unsigned i = 0, e = II->getNumOperands(); i != e; ++i) {
491 if (MO.
getReg() == ARM::R12) {
508 int SPAdj,
unsigned FIOperandNum,
535 "Cannot use SP to access the emergency spill slot in " 536 "functions without a reserved call frame");
538 "Cannot use SP to access the emergency spill slot in " 539 "functions with variable sized frame objects");
545 MI.
getOperand(FIOperandNum). ChangeToRegister(FrameReg,
false );
552 "This eliminateFrameIndex only supports Thumb1!");
559 assert(Offset &&
"This code isn't needed if offset already handled!");
572 if (Opcode == ARM::tLDRspi) {
575 Offset,
false, TII, *
this);
585 MI.
setDesc(TII.get(UseRR ? ARM::tLDRr : ARM::tLDRi));
596 if (Opcode == ARM::tSTRspi) {
599 Offset,
false, TII, *
this);
607 MI.
setDesc(TII.get(UseRR ? ARM::tSTRr : ARM::tSTRi));
bool isRegMask() const
isRegMask - Tests if this is a MO_RegisterMask operand.
const MachineInstrBuilder & add(const MachineOperand &MO) const
The MachineConstantPool class keeps track of constants referenced by a function which must be spilled...
bool isScavengingFrameIndex(int FI) const
Query whether a frame index is a scavenging frame index.
DILocation * get() const
Get the underlying DILocation.
int findFirstPredOperandIdx() const
Find the index of the first operand in the operand list that is used to represent the predicate...
This class represents lattice values for constants.
static void removeOperands(MachineInstr &MI, unsigned i)
void ChangeToRegister(unsigned Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isDebug=false)
ChangeToRegister - Replace this operand with a new register operand of the specified value...
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Describe properties that are true of each instruction in the target description file.
unsigned getReg() const
getReg - Returns the register number.
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
bool isPredicable(QueryType Type=AllInBundle) const
Return true if this instruction has a predicate operand that controls execution.
uint64_t alignTo(uint64_t Value, uint64_t Align, uint64_t Skew=0)
Returns the next integer (mod 2**64) that is greater than or equal to Value and is a multiple of Alig...
bool isThumb1Only() const
static void emitThumbRegPlusImmInReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, unsigned DestReg, unsigned BaseReg, int NumBytes, bool CanChangeCC, const TargetInstrInfo &TII, const ARMBaseRegisterInfo &MRI, unsigned MIFlags=MachineInstr::NoFlags)
emitThumbRegPlusImmInReg - Emits a series of instructions to materialize a destreg = basereg + immedi...
static unsigned convertToNonSPOpcode(unsigned Opcode)
convertToNonSPOpcode - Change the opcode to the non-SP version, because we're replacing the frame ind...
void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override
bool genExecuteOnly() const
const ARMBaseInstrInfo * getInstrInfo() const override
bool saveScavengerRegister(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, MachineBasicBlock::iterator &UseMI, const TargetRegisterClass *RC, unsigned Reg) const override
saveScavengerRegister - Spill the register so it can be used by the register scavenger.
static void emitThumb2LoadConstPool(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, unsigned DestReg, unsigned SubIdx, int Val, ARMCC::CondCodes Pred, unsigned PredReg, unsigned MIFlags)
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
This file declares the MachineConstantPool class which is an abstract constant pool to keep track of ...
const HexagonInstrInfo * TII
unsigned getNumOperands() const
Retuns the total number of operands.
bool hasReservedCallFrame(const MachineFunction &MF) const override
hasReservedCallFrame - Under normal circumstances, when a frame pointer is not required, we reserve argument space for call sites in the function immediately on entry to the current function.
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
static std::array< MachineOperand, 2 > predOps(ARMCC::CondCodes Pred, unsigned PredReg=0)
Get the operands corresponding to the given Pred value.
static void emitThumb1LoadConstPool(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, unsigned DestReg, unsigned SubIdx, int Val, ARMCC::CondCodes Pred, unsigned PredReg, unsigned MIFlags)
virtual const TargetInstrInfo * getInstrInfo() const
const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const override
void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, int64_t Offset) const override
void ChangeToImmediate(int64_t ImmVal)
ChangeToImmediate - Replace this operand with a new immediate operand of the specified value...
TargetInstrInfo - Interface to description of machine instruction set.
unsigned getDefRegState(bool B)
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
bool mayStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly modify memory.
int ResolveFrameIndexReference(const MachineFunction &MF, int FI, unsigned &FrameReg, int SPAdj) const
This file declares the machine register scavenger class.
unsigned const MachineRegisterInfo * MRI
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
MachineInstrBuilder & UseMI
This is an important base class in LLVM.
This file contains the declarations for the subclasses of Constant, which represent the different fla...
void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
const ARMFrameLowering * getFrameLowering() const override
const TargetRegisterClass * getLargestLegalSuperClass(const TargetRegisterClass *RC, const MachineFunction &MF) const override
MachineConstantPool * getConstantPool()
getConstantPool - Return the constant pool object for the current function.
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function. ...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
void emitLoadConstPool(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, unsigned DestReg, unsigned SubIdx, int Val, ARMCC::CondCodes Pred=ARMCC::AL, unsigned PredReg=0, unsigned MIFlags=MachineInstr::NoFlags) const override
emitLoadConstPool - Emits a load from constpool to materialize the specified immediate.
void setDesc(const MCInstrDesc &tid)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one...
static MachineOperand t1CondCodeOp(bool isDead=false)
Get the operand corresponding to the conditional code result for Thumb1.
bool isDebugValue() const
MachineOperand class - Representation of each machine instruction operand.
static Constant * get(Type *Ty, uint64_t V, bool isSigned=false)
If Ty is a vector type, return a Constant with a splat of the given value.
const Function & getFunction() const
Return the LLVM function that this machine code represents.
static bool clobbersPhysReg(const uint32_t *RegMask, unsigned PhysReg)
clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
static cl::opt< unsigned > Threshold("loop-unswitch-threshold", cl::desc("Max loop size to unswitch"), cl::init(100), cl::Hidden)
const MachineBasicBlock * getParent() const
cl::opt< bool > ReuseFrameIndexVals
void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, int64_t Offset) const override
static bool isARMLowRegister(unsigned Reg)
isARMLowRegister - Returns true if the register is a low register (r0-r7).
Representation of each machine instruction.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
bool rewriteFrameIndex(MachineBasicBlock::iterator II, unsigned FrameRegIdx, unsigned FrameReg, int &Offset, const ARMBaseInstrInfo &TII) const
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
static IntegerType * getInt32Ty(LLVMContext &C)
const MachineInstrBuilder & setMIFlags(unsigned Flags) const
const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const override
ARMFunctionInfo - This class is derived from MachineFunctionInfo and contains private ARM-specific in...
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
void emitThumbRegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, unsigned DestReg, unsigned BaseReg, int NumBytes, const TargetInstrInfo &TII, const ARMBaseRegisterInfo &MRI, unsigned MIFlags=0)
emitThumbRegPlusImmediate - Emits a series of instructions to materialize a destreg = basereg + immed...
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
bool mayLoad(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read memory.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
const TargetRegisterClass * getLargestLegalSuperClass(const TargetRegisterClass *RC, const MachineFunction &MF) const override
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
void RemoveOperand(unsigned OpNo)
Erase an operand from an instruction, leaving it with one fewer operand than it started with...
const MachineOperand & getOperand(unsigned i) const
bool isThumbFunction() const
unsigned getConstantPoolIndex(const Constant *C, unsigned Alignment)
getConstantPoolIndex - Create a new entry in the constant pool or return an existing one...
unsigned createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
virtual void emitLoadConstPool(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, unsigned DestReg, unsigned SubIdx, int Val, ARMCC::CondCodes Pred=ARMCC::AL, unsigned PredReg=0, unsigned MIFlags=MachineInstr::NoFlags) const
emitLoadConstPool - Emits a load from constpool to materialize the specified immediate.