36 #define DEBUG_TYPE "regalloc" 38 STATISTIC(NumNewQueued ,
"Number of new live ranges queued");
55 void RegAllocBase::anchor() {}
72 void RegAllocBase::seedLiveRegs() {
108 <<
':' << *VirtReg <<
" w=" << VirtReg->weight <<
'\n');
112 VirtRegVec SplitVRegs;
113 unsigned AvailablePhysReg =
selectOrSplit(*VirtReg, SplitVRegs);
115 if (AvailablePhysReg == ~0u) {
129 MI->
emitError(
"inline assembly requires more registers than available");
138 if (AvailablePhysReg)
141 for (
unsigned Reg : SplitVRegs) {
147 assert(SplitVirtReg->empty() &&
"Non-empty but used interval");
148 LLVM_DEBUG(
dbgs() <<
"not queueing unused " << *SplitVirtReg <<
'\n');
153 LLVM_DEBUG(
dbgs() <<
"queuing new interval: " << *SplitVirtReg <<
"\n");
155 "expect split value in virtual register");
166 DeadInst->eraseFromParent();
bool reg_nodbg_empty(unsigned RegNo) const
reg_nodbg_empty - Return true if the only instructions using or defining Reg are Debug instructions...
ArrayRef< MCPhysReg > getOrder(const TargetRegisterClass *RC) const
getOrder - Returns the preferred allocation order for RC.
static const char TimerGroupDescription[]
const TargetRegisterClass * getRegClass(unsigned Reg) const
Return the register class of the specified virtual register.
void emitError(StringRef Msg) const
Emit an error referring to the source location of this instruction.
void RemoveMachineInstrFromMaps(MachineInstr &MI)
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
This class represents lattice values for constants.
static unsigned index2VirtReg(unsigned Index)
Convert a 0-based index to a virtual register number.
LiveInterval - This class represents the liveness of a register, or stack slot.
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
virtual unsigned selectOrSplit(LiveInterval &VirtReg, SmallVectorImpl< unsigned > &splitLVRs)=0
STATISTIC(NumFunctions, "Total number of functions")
const TargetRegisterInfo & getTargetRegInfo() const
SmallPtrSet< MachineInstr *, 32 > DeadRemats
Inst which is a def of an original reg and whose defs are already all dead after remat is saved in De...
const char * getRegClassName(const TargetRegisterClass *Class) const
Returns the name of the register class.
MachineFunction & getMachineFunction() const
This class is basically a combination of TimeRegion and Timer.
void freezeReservedRegs(const MachineFunction &)
freezeReservedRegs - Called by the register allocator to freeze the set of reserved registers before ...
static reg_instr_iterator reg_instr_end()
defusechain_iterator - This class provides iterator support for machine operands in the function that...
void assign(LiveInterval &VirtReg, unsigned PhysReg)
Assign VirtReg to PhysReg.
static cl::opt< bool, true > VerifyRegAlloc("verify-regalloc", cl::location(RegAllocBase::VerifyEnabled), cl::Hidden, cl::desc("Verify during register allocation"))
void invalidateVirtRegs()
Invalidate cached interference queries after modifying virtual register live ranges.
bool hasInterval(unsigned Reg) const
void removeInterval(unsigned Reg)
Interval removal.
MachineRegisterInfo & getRegInfo() const
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
void runOnMachineFunction(const MachineFunction &MF)
runOnFunction - Prepare to answer questions about MF.
void init(VirtRegMap &vrm, LiveIntervals &lis, LiveRegMatrix &mat)
unsigned getNumVirtRegs() const
getNumVirtRegs - Return the number of virtual registers created.
static const char TimerGroupName[]
virtual void enqueue(LiveInterval *LI)=0
enqueue - Add VirtReg to the priority queue of unassigned registers.
void assignVirt2Phys(unsigned virtReg, MCPhysReg physReg)
creates a mapping for the specified virtual register to the specified physical register ...
LiveInterval & getInterval(unsigned Reg)
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
virtual void aboutToRemoveInterval(LiveInterval &LI)
Method called when the allocator is about to remove a LiveInterval.
Representation of each machine instruction.
static bool VerifyEnabled
VerifyEnabled - True when -verify-regalloc is given.
const TargetRegisterInfo * TRI
bool hasPhys(unsigned virtReg) const
returns true if the specified virtual register is mapped to a physical register
virtual void postOptimization()
virtual void postOptimization()
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
RegisterClassInfo RegClassInfo
bool TimePassesIsEnabled
If the user specifies the -time-passes argument on an LLVM tool command line then the value of this b...
MachineRegisterInfo * MRI
reg_instr_iterator reg_instr_begin(unsigned RegNo) const
LocationClass< Ty > location(Ty &L)
virtual Spiller & spiller()=0
virtual LiveInterval * dequeue()=0
dequeue - Return the next unassigned register, or NULL.