TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDesc objects that represent all of the machine registers that the target has. More...
#include "llvm/CodeGen/TargetRegisterInfo.h"
Classes | |
| struct | RegClassInfo |
Public Types | |
| using | regclass_iterator = const TargetRegisterClass *const * |
| using | vt_iterator = const MVT::SimpleValueType * |
 Public Types inherited from llvm::MCRegisterInfo | |
| using | regclass_iterator = const MCRegisterClass * |
Public Member Functions | |
| unsigned | getRegSizeInBits (const TargetRegisterClass &RC) const |
| Return the size in bits of a register from class RC. More... | |
| unsigned | getSpillSize (const TargetRegisterClass &RC) const |
| Return the size in bytes of the stack slot allocated to hold a spilled copy of a register from class RC. More... | |
| unsigned | getSpillAlignment (const TargetRegisterClass &RC) const |
| Return the minimum required alignment in bytes for a spill slot for a register of this class. More... | |
| bool | isTypeLegalForClass (const TargetRegisterClass &RC, MVT T) const |
| Return true if the given TargetRegisterClass has the ValueType T. More... | |
| vt_iterator | legalclasstypes_begin (const TargetRegisterClass &RC) const |
| Loop over all of the value types that can be represented by values in the given register class. More... | |
| vt_iterator | legalclasstypes_end (const TargetRegisterClass &RC) const |
| const TargetRegisterClass * | getMinimalPhysRegClass (unsigned Reg, MVT VT=MVT::Other) const |
| Returns the Register Class of a physical register of the given type, picking the most sub register class of the right type that contains this physreg. More... | |
| const TargetRegisterClass * | getAllocatableClass (const TargetRegisterClass *RC) const |
| Return the maximal subclass of the given register class that is allocatable or NULL. More... | |
| BitVector | getAllocatableSet (const MachineFunction &MF, const TargetRegisterClass *RC=nullptr) const |
| Returns a bitset indexed by register number indicating if a register is allocatable or not. More... | |
| unsigned | getCostPerUse (unsigned RegNo) const |
| Return the additional cost of using this register instead of other registers in its class. More... | |
| bool | isInAllocatableClass (unsigned RegNo) const |
| Return true if the register is in the allocation of any register class. More... | |
| const char * | getSubRegIndexName (unsigned SubIdx) const |
| Return the human-readable symbolic target-specific name for the specified SubRegIndex. More... | |
| LaneBitmask | getSubRegIndexLaneMask (unsigned SubIdx) const |
| Return a bitmask representing the parts of a register that are covered by SubIdx. More... | |
| LaneBitmask | getCoveringLanes () const |
| The lane masks returned by getSubRegIndexLaneMask() above can only be used to determine if sub-registers overlap - they can't be used to determine if a set of sub-registers completely cover another sub-register. More... | |
| bool | regsOverlap (unsigned regA, unsigned regB) const |
| Returns true if the two registers are equal or alias each other. More... | |
| bool | hasRegUnit (unsigned Reg, unsigned RegUnit) const |
| Returns true if Reg contains RegUnit. More... | |
| virtual unsigned | lookThruCopyLike (unsigned SrcReg, const MachineRegisterInfo *MRI) const |
| Returns the original SrcReg unless it is the target of a copy-like operation, in which case we chain backwards through all such operations to the ultimate source register. More... | |
| virtual const MCPhysReg * | getCalleeSavedRegs (const MachineFunction *MF) const =0 |
| Return a null-terminated list of all of the callee-saved registers on this target. More... | |
| virtual const uint32_t * | getCallPreservedMask (const MachineFunction &MF, CallingConv::ID) const |
| Return a mask of call-preserved registers for the given calling convention on the current function. More... | |
| virtual const uint32_t * | getNoPreservedMask () const |
| Return a register mask that clobbers everything. More... | |
| bool | regmaskSubsetEqual (const uint32_t *mask0, const uint32_t *mask1) const |
Return true if all bits that are set in mask mask0 are also set in mask1. More... | |
| virtual ArrayRef< const uint32_t * > | getRegMasks () const =0 |
| Return all the call-preserved register masks defined for this target. More... | |
| virtual ArrayRef< const char * > | getRegMaskNames () const =0 |
| virtual BitVector | getReservedRegs (const MachineFunction &MF) const =0 |
| Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times, e.g. More... | |
| virtual bool | isAsmClobberable (const MachineFunction &MF, unsigned PhysReg) const |
| Returns false if we can't guarantee that Physreg, specified as an IR asm clobber constraint, will be preserved across the statement. More... | |
| virtual bool | isConstantPhysReg (unsigned PhysReg) const |
| Returns true if PhysReg is unallocatable and constant throughout the function. More... | |
| virtual bool | isCallerPreservedPhysReg (unsigned PhysReg, const MachineFunction &MF) const |
| Physical registers that may be modified within a function but are guaranteed to be restored before any uses. More... | |
| virtual void | adjustStackMapLiveOutMask (uint32_t *Mask) const |
| Prior to adding the live-out mask to a stackmap or patchpoint instruction, provide the target the opportunity to adjust it (mainly to remove pseudo-registers that should be ignored). More... | |
| unsigned | getMatchingSuperReg (unsigned Reg, unsigned SubIdx, const TargetRegisterClass *RC) const |
| Return a super-register of the specified register Reg so its sub-register of index SubIdx is Reg. More... | |
| virtual const TargetRegisterClass * | getMatchingSuperRegClass (const TargetRegisterClass *A, const TargetRegisterClass *B, unsigned Idx) const |
| Return a subclass of the specified register class A so that each register in it has a sub-register of the specified sub-register index which is in the specified register class B. More... | |
| virtual bool | shouldRewriteCopySrc (const TargetRegisterClass *DefRC, unsigned DefSubReg, const TargetRegisterClass *SrcRC, unsigned SrcSubReg) const |
| virtual const TargetRegisterClass * | getSubClassWithSubReg (const TargetRegisterClass *RC, unsigned Idx) const |
| Returns the largest legal sub-class of RC that supports the sub-register index Idx. More... | |
| unsigned | composeSubRegIndices (unsigned a, unsigned b) const |
| Return the subregister index you get from composing two subregister indices. More... | |
| LaneBitmask | composeSubRegIndexLaneMask (unsigned IdxA, LaneBitmask Mask) const |
| Transforms a LaneMask computed for one subregister to the lanemask that would have been computed when composing the subsubregisters with IdxA first. More... | |
| LaneBitmask | reverseComposeSubRegIndexLaneMask (unsigned IdxA, LaneBitmask LaneMask) const |
Transform a lanemask given for a virtual register to the corresponding lanemask before using subregister with index IdxA. More... | |
| const TargetRegisterClass * | getCommonSuperRegClass (const TargetRegisterClass *RCA, unsigned SubA, const TargetRegisterClass *RCB, unsigned SubB, unsigned &PreA, unsigned &PreB) const |
| Find a common super-register class if it exists. More... | |
| regclass_iterator | regclass_begin () const |
| Register class iterators. More... | |
| regclass_iterator | regclass_end () const |
| iterator_range< regclass_iterator > | regclasses () const |
| unsigned | getNumRegClasses () const |
| const TargetRegisterClass * | getRegClass (unsigned i) const |
| Returns the register class associated with the enumeration value. More... | |
| const char * | getRegClassName (const TargetRegisterClass *Class) const |
| Returns the name of the register class. More... | |
| const TargetRegisterClass * | getCommonSubClass (const TargetRegisterClass *A, const TargetRegisterClass *B, const MVT::SimpleValueType SVT=MVT::SimpleValueType::Any) const |
| Find the largest common subclass of A and B. More... | |
| virtual const TargetRegisterClass * | getPointerRegClass (const MachineFunction &MF, unsigned Kind=0) const |
| Returns a TargetRegisterClass used for pointer values. More... | |
| virtual const TargetRegisterClass * | getCrossCopyRegClass (const TargetRegisterClass *RC) const |
| Returns a legal register class to copy a register in the specified class to or from. More... | |
| virtual const TargetRegisterClass * | getLargestLegalSuperClass (const TargetRegisterClass *RC, const MachineFunction &) const |
| Returns the largest super class of RC that is legal to use in the current sub-target and has the same spill size. More... | |
| virtual unsigned | getRegPressureLimit (const TargetRegisterClass *RC, MachineFunction &MF) const |
| Return the register pressure "high water mark" for the specific register class. More... | |
| virtual unsigned | getRegPressureSetScore (const MachineFunction &MF, unsigned PSetID) const |
| Return a heuristic for the machine scheduler to compare the profitability of increasing one register pressure set versus another. More... | |
| virtual const RegClassWeight & | getRegClassWeight (const TargetRegisterClass *RC) const =0 |
| Get the weight in units of pressure for this register class. More... | |
| unsigned | getRegSizeInBits (unsigned Reg, const MachineRegisterInfo &MRI) const |
| Returns size in bits of a phys/virtual/generic register. More... | |
| virtual unsigned | getRegUnitWeight (unsigned RegUnit) const =0 |
| Get the weight in units of pressure for this register unit. More... | |
| virtual unsigned | getNumRegPressureSets () const =0 |
| Get the number of dimensions of register pressure. More... | |
| virtual const char * | getRegPressureSetName (unsigned Idx) const =0 |
| Get the name of this register unit pressure set. More... | |
| virtual unsigned | getRegPressureSetLimit (const MachineFunction &MF, unsigned Idx) const =0 |
| Get the register unit pressure limit for this dimension. More... | |
| virtual const int * | getRegClassPressureSets (const TargetRegisterClass *RC) const =0 |
| Get the dimensions of register pressure impacted by this register class. More... | |
| virtual const int * | getRegUnitPressureSets (unsigned RegUnit) const =0 |
| Get the dimensions of register pressure impacted by this register unit. More... | |
| virtual bool | getRegAllocationHints (unsigned VirtReg, ArrayRef< MCPhysReg > Order, SmallVectorImpl< MCPhysReg > &Hints, const MachineFunction &MF, const VirtRegMap *VRM=nullptr, const LiveRegMatrix *Matrix=nullptr) const |
| Get a list of 'hint' registers that the register allocator should try first when allocating a physical register for the virtual register VirtReg. More... | |
| virtual void | updateRegAllocHint (unsigned Reg, unsigned NewReg, MachineFunction &MF) const |
| A callback to allow target a chance to update register allocation hints when a register is "changed" (e.g. More... | |
| virtual bool | reverseLocalAssignment () const |
| Allow the target to reverse allocation order of local live ranges. More... | |
| virtual unsigned | getCSRFirstUseCost () const |
| Allow the target to override the cost of using a callee-saved register for the first time. More... | |
| virtual bool | requiresRegisterScavenging (const MachineFunction &MF) const |
| Returns true if the target requires (and can make use of) the register scavenger. More... | |
| virtual bool | useFPForScavengingIndex (const MachineFunction &MF) const |
| Returns true if the target wants to use frame pointer based accesses to spill to the scavenger emergency spill slot. More... | |
| virtual bool | requiresFrameIndexScavenging (const MachineFunction &MF) const |
| Returns true if the target requires post PEI scavenging of registers for materializing frame index constants. More... | |
| virtual bool | requiresFrameIndexReplacementScavenging (const MachineFunction &MF) const |
| Returns true if the target requires using the RegScavenger directly for frame elimination despite using requiresFrameIndexScavenging. More... | |
| virtual bool | requiresVirtualBaseRegisters (const MachineFunction &MF) const |
| Returns true if the target wants the LocalStackAllocation pass to be run and virtual base registers used for more efficient stack access. More... | |
| virtual bool | hasReservedSpillSlot (const MachineFunction &MF, unsigned Reg, int &FrameIdx) const |
| Return true if target has reserved a spill slot in the stack frame of the given function for the specified register. More... | |
| virtual bool | trackLivenessAfterRegAlloc (const MachineFunction &MF) const |
| Returns true if the live-ins should be tracked after register allocation. More... | |
| virtual bool | canRealignStack (const MachineFunction &MF) const |
| True if the stack can be realigned for the target. More... | |
| bool | needsStackRealignment (const MachineFunction &MF) const |
| True if storage within the function requires the stack pointer to be aligned more than the normal calling convention calls for. More... | |
| virtual int64_t | getFrameIndexInstrOffset (const MachineInstr *MI, int Idx) const |
| Get the offset from the referenced frame index in the instruction, if there is one. More... | |
| virtual bool | needsFrameBaseReg (MachineInstr *MI, int64_t Offset) const |
| Returns true if the instruction's frame index reference would be better served by a base register other than FP or SP. More... | |
| virtual void | materializeFrameBaseRegister (MachineBasicBlock *MBB, unsigned BaseReg, int FrameIdx, int64_t Offset) const |
| Insert defining instruction(s) for BaseReg to be a pointer to FrameIdx before insertion point I. More... | |
| virtual void | resolveFrameIndex (MachineInstr &MI, unsigned BaseReg, int64_t Offset) const |
| Resolve a frame index operand of an instruction to reference the indicated base register plus offset instead. More... | |
| virtual bool | isFrameOffsetLegal (const MachineInstr *MI, unsigned BaseReg, int64_t Offset) const |
| Determine whether a given base register plus offset immediate is encodable to resolve a frame index. More... | |
| virtual bool | saveScavengerRegister (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, MachineBasicBlock::iterator &UseMI, const TargetRegisterClass *RC, unsigned Reg) const |
| Spill the register so it can be used by the register scavenger. More... | |
| virtual void | eliminateFrameIndex (MachineBasicBlock::iterator MI, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const =0 |
| This method must be overriden to eliminate abstract frame indices from instructions which may use them. More... | |
| virtual StringRef | getRegAsmName (unsigned Reg) const |
Return the assembly name for Reg. More... | |
| virtual bool | shouldCoalesce (MachineInstr *MI, const TargetRegisterClass *SrcRC, unsigned SubReg, const TargetRegisterClass *DstRC, unsigned DstSubReg, const TargetRegisterClass *NewRC, LiveIntervals &LIS) const |
| Subtarget Hooks. More... | |
| virtual unsigned | getFrameRegister (const MachineFunction &MF) const =0 |
| Debug information queries. More... | |
| void | markSuperRegs (BitVector &RegisterSet, unsigned Reg) const |
| Mark a register and all its aliases as reserved in the given set. More... | |
| bool | checkAllSuperRegsMarked (const BitVector &RegisterSet, ArrayRef< MCPhysReg > Exceptions=ArrayRef< MCPhysReg >()) const |
| Returns true if for every register in the set all super registers are part of the set as well. More... | |
| virtual const TargetRegisterClass * | getConstrainedRegClassForOperand (const MachineOperand &MO, const MachineRegisterInfo &MRI) const |
| Public Member Functions inherited from llvm::MCRegisterInfo | |
| void | InitMCRegisterInfo (const MCRegisterDesc *D, unsigned NR, unsigned RA, unsigned PC, const MCRegisterClass *C, unsigned NC, const MCPhysReg(*RURoots)[2], unsigned NRU, const MCPhysReg *DL, const LaneBitmask *RUMS, const char *Strings, const char *ClassStrings, const uint16_t *SubIndices, unsigned NumIndices, const SubRegCoveredBits *SubIdxRanges, const uint16_t *RET) |
| Initialize MCRegisterInfo, called by TableGen auto-generated routines. More... | |
| void | mapLLVMRegsToDwarfRegs (const DwarfLLVMRegPair *Map, unsigned Size, bool isEH) |
| Used to initialize LLVM register to Dwarf register number mapping. More... | |
| void | mapDwarfRegsToLLVMRegs (const DwarfLLVMRegPair *Map, unsigned Size, bool isEH) |
| Used to initialize Dwarf register to LLVM register number mapping. More... | |
| void | mapLLVMRegToSEHReg (unsigned LLVMReg, int SEHReg) |
| mapLLVMRegToSEHReg - Used to initialize LLVM register to SEH register number mapping. More... | |
| void | mapLLVMRegToCVReg (unsigned LLVMReg, int CVReg) |
| unsigned | getRARegister () const |
| This method should return the register where the return address can be found. More... | |
| unsigned | getProgramCounter () const |
| Return the register which is the program counter. More... | |
| const MCRegisterDesc & | operator[] (unsigned RegNo) const |
| const MCRegisterDesc & | get (unsigned RegNo) const |
| Provide a get method, equivalent to [], but more useful with a pointer to this object. More... | |
| unsigned | getSubReg (unsigned Reg, unsigned Idx) const |
| Returns the physical register number of sub-register "Index" for physical register RegNo. More... | |
| unsigned | getMatchingSuperReg (unsigned Reg, unsigned SubIdx, const MCRegisterClass *RC) const |
| Return a super-register of the specified register Reg so its sub-register of index SubIdx is Reg. More... | |
| unsigned | getSubRegIndex (unsigned RegNo, unsigned SubRegNo) const |
| For a given register pair, return the sub-register index if the second register is a sub-register of the first. More... | |
| unsigned | getSubRegIdxSize (unsigned Idx) const |
| Get the size of the bit range covered by a sub-register index. More... | |
| unsigned | getSubRegIdxOffset (unsigned Idx) const |
| Get the offset of the bit range covered by a sub-register index. More... | |
| const char * | getName (unsigned RegNo) const |
| Return the human-readable symbolic target-specific name for the specified physical register. More... | |
| unsigned | getNumRegs () const |
| Return the number of registers this target has (useful for sizing arrays holding per register information) More... | |
| unsigned | getNumSubRegIndices () const |
| Return the number of sub-register indices understood by the target. More... | |
| unsigned | getNumRegUnits () const |
| Return the number of (native) register units in the target. More... | |
| int | getDwarfRegNum (unsigned RegNum, bool isEH) const |
| Map a target register to an equivalent dwarf register number. More... | |
| int | getLLVMRegNum (unsigned RegNum, bool isEH) const |
| Map a dwarf register back to a target register. More... | |
| int | getLLVMRegNumFromEH (unsigned RegNum) const |
| Map a DWARF EH register back to a target register (same as getLLVMRegNum(RegNum, true)) but return -1 if there is no mapping, rather than asserting that there must be one. More... | |
| int | getDwarfRegNumFromDwarfEHRegNum (unsigned RegNum) const |
| Map a target EH register number to an equivalent DWARF register number. More... | |
| int | getSEHRegNum (unsigned RegNum) const |
| Map a target register to an equivalent SEH register number. More... | |
| int | getCodeViewRegNum (unsigned RegNum) const |
| Map a target register to an equivalent CodeView register number. More... | |
| regclass_iterator | regclass_begin () const |
| regclass_iterator | regclass_end () const |
| iterator_range< regclass_iterator > | regclasses () const |
| unsigned | getNumRegClasses () const |
| const MCRegisterClass & | getRegClass (unsigned i) const |
| Returns the register class associated with the enumeration value. More... | |
| const char * | getRegClassName (const MCRegisterClass *Class) const |
| uint16_t | getEncodingValue (unsigned RegNo) const |
| Returns the encoding for RegNo. More... | |
| bool | isSubRegister (unsigned RegA, unsigned RegB) const |
| Returns true if RegB is a sub-register of RegA. More... | |
| bool | isSuperRegister (unsigned RegA, unsigned RegB) const |
| Returns true if RegB is a super-register of RegA. More... | |
| bool | isSubRegisterEq (unsigned RegA, unsigned RegB) const |
| Returns true if RegB is a sub-register of RegA or if RegB == RegA. More... | |
| bool | isSuperRegisterEq (unsigned RegA, unsigned RegB) const |
| Returns true if RegB is a super-register of RegA or if RegB == RegA. More... | |
| bool | isSuperOrSubRegisterEq (unsigned RegA, unsigned RegB) const |
| Returns true if RegB is a super-register or sub-register of RegA or if RegB == RegA. More... | |
Static Public Member Functions | |
| static bool | isStackSlot (unsigned Reg) |
| isStackSlot - Sometimes it is useful the be able to store a non-negative frame index in a variable that normally holds a register. More... | |
| static int | stackSlot2Index (unsigned Reg) |
| Compute the frame index from a register value representing a stack slot. More... | |
| static unsigned | index2StackSlot (int FI) |
| Convert a non-negative frame index to a stack slot register value. More... | |
| static bool | isPhysicalRegister (unsigned Reg) |
| Return true if the specified register number is in the physical register namespace. More... | |
| static bool | isVirtualRegister (unsigned Reg) |
| Return true if the specified register number is in the virtual register namespace. More... | |
| static unsigned | virtReg2Index (unsigned Reg) |
| Convert a virtual register number to a 0-based index. More... | |
| static unsigned | index2VirtReg (unsigned Index) |
| Convert a 0-based index to a virtual register number. More... | |
| static void | dumpReg (unsigned Reg, unsigned SubRegIndex=0, const TargetRegisterInfo *TRI=nullptr) |
| Debugging helper: dump register in human readable form to dbgs() stream. More... | |
Protected Member Functions | |
| TargetRegisterInfo (const TargetRegisterInfoDesc *ID, regclass_iterator RCB, regclass_iterator RCE, const char *const *SRINames, const LaneBitmask *SRILaneMasks, LaneBitmask CoveringLanes, const RegClassInfo *const RCIs, unsigned Mode=0) | |
| virtual | ~TargetRegisterInfo () |
| virtual unsigned | composeSubRegIndicesImpl (unsigned, unsigned) const |
| Overridden by TableGen in targets that have sub-registers. More... | |
| virtual LaneBitmask | composeSubRegIndexLaneMaskImpl (unsigned, LaneBitmask) const |
| Overridden by TableGen in targets that have sub-registers. More... | |
| virtual LaneBitmask | reverseComposeSubRegIndexLaneMaskImpl (unsigned, LaneBitmask) const |
| const RegClassInfo & | getRegClassInfo (const TargetRegisterClass &RC) const |
Detailed Description
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDesc objects that represent all of the machine registers that the target has.
As such, we simply have to track a pointer to this array so that we can turn register number into a register descriptor.
Definition at line 220 of file TargetRegisterInfo.h.
Member Typedef Documentation
◆ regclass_iterator
Definition at line 222 of file TargetRegisterInfo.h.
◆ vt_iterator
Definition at line 223 of file TargetRegisterInfo.h.
Constructor & Destructor Documentation
◆ TargetRegisterInfo()
|
protected |
Definition at line 43 of file TargetRegisterInfo.cpp.
References ~TargetRegisterInfo().
◆ ~TargetRegisterInfo()
|
protectedvirtualdefault |
Referenced by TargetRegisterInfo().
Member Function Documentation
◆ adjustStackMapLiveOutMask()
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inlinevirtual |
Prior to adding the live-out mask to a stackmap or patchpoint instruction, provide the target the opportunity to adjust it (mainly to remove pseudo-registers that should be ignored).
Definition at line 537 of file TargetRegisterInfo.h.
◆ canRealignStack()
|
virtual |
True if the stack can be realigned for the target.
Definition at line 437 of file TargetRegisterInfo.cpp.
References llvm::MachineFunction::getFunction(), and llvm::Function::hasFnAttribute().
Referenced by llvm::SparcRegisterInfo::canRealignStack(), llvm::MipsRegisterInfo::canRealignStack(), llvm::X86RegisterInfo::canRealignStack(), llvm::ARMBaseRegisterInfo::canRealignStack(), and needsStackRealignment().
◆ checkAllSuperRegsMarked()
| bool TargetRegisterInfo::checkAllSuperRegsMarked | ( | const BitVector & | RegisterSet, |
| ArrayRef< MCPhysReg > | Exceptions = ArrayRef<MCPhysReg>() |
||
| ) | const |
Returns true if for every register in the set all super registers are part of the set as well.
Definition at line 65 of file TargetRegisterInfo.cpp.
References llvm::dbgs(), llvm::MCRegisterInfo::getNumRegs(), llvm::is_contained(), llvm::MCRegisterInfo::DiffListIterator::isValid(), llvm::printReg(), Reg, llvm::BitVector::set(), and llvm::BitVector::set_bits().
◆ composeSubRegIndexLaneMask()
|
inline |
Transforms a LaneMask computed for one subregister to the lanemask that would have been computed when composing the subsubregisters with IdxA first.
- See also
- composeSubRegIndices()
Definition at line 604 of file TargetRegisterInfo.h.
References llvm::BitmaskEnumDetail::Mask().
Referenced by definesFullReg(), and llvm::rdf::PhysicalRegisterInfo::mapTo().
◆ composeSubRegIndexLaneMaskImpl()
|
inlineprotectedvirtual |
Overridden by TableGen in targets that have sub-registers.
Definition at line 637 of file TargetRegisterInfo.h.
References llvm_unreachable.
◆ composeSubRegIndices()
Return the subregister index you get from composing two subregister indices.
The special null sub-register index composes as the identity.
If R:a:b is the same register as R:c, then composeSubRegIndices(a, b) returns c. Note that composeSubRegIndices does not tell you about illegal compositions. If R does not have a subreg a, or R:a does not have a subreg b, composeSubRegIndices doesn't tell you.
The ARM register Q0 has two D subregs dsub_0:D0 and dsub_1:D1. It also has ssub_0:S0 - ssub_3:S3 subregs. If you compose subreg indices dsub_1, ssub_0 you get ssub_2.
Definition at line 595 of file TargetRegisterInfo.h.
Referenced by definesFullReg(), getCommonSuperRegClass(), getRegsUsedByPHIs(), llvm::CoalescerPair::isCoalescable(), isCrossCopy(), and llvm::MachineOperand::substVirtReg().
◆ composeSubRegIndicesImpl()
|
inlineprotectedvirtual |
Overridden by TableGen in targets that have sub-registers.
Definition at line 631 of file TargetRegisterInfo.h.
References llvm_unreachable.
◆ dumpReg()
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static |
Debugging helper: dump register in human readable form to dbgs() stream.
Definition at line 514 of file TargetRegisterInfo.cpp.
References llvm::dbgs(), and llvm::printReg().
◆ eliminateFrameIndex()
|
pure virtual |
This method must be overriden to eliminate abstract frame indices from instructions which may use them.
The instruction referenced by the iterator contains an MO_FrameIndex operand which must be eliminated by this method. This method may modify or replace the specified instruction, as long as it keeps the iterator pointing at the finished product. SPAdj is the SP adjustment due to call frame setup instruction. FIOperandNum is the FI operand number.
Referenced by AssignProtectedObjSet(), and llvm::createNVPTXPrologEpilogPass().
◆ getAllocatableClass()
| const TargetRegisterClass * TargetRegisterInfo::getAllocatableClass | ( | const TargetRegisterClass * | RC | ) | const |
Return the maximal subclass of the given register class that is allocatable or NULL.
getAllocatableClass - Return the maximal subclass of the given register class that is alloctable, or NULL.
Definition at line 175 of file TargetRegisterInfo.cpp.
References getRegClass(), llvm::TargetRegisterClass::getSubClassMask(), llvm::TargetRegisterClass::isAllocatable(), and llvm::BitMaskClassIterator::isValid().
Referenced by getAllocatableSet().
◆ getAllocatableSet()
| BitVector TargetRegisterInfo::getAllocatableSet | ( | const MachineFunction & | MF, |
| const TargetRegisterClass * | RC = nullptr |
||
| ) | const |
Returns a bitset indexed by register number indicating if a register is allocatable or not.
If a register class is specified, returns the subset for the class.
Definition at line 218 of file TargetRegisterInfo.cpp.
References C, llvm::BitVector::flip(), getAllocatableClass(), getAllocatableSetForRC(), llvm::MCRegisterInfo::getNumRegs(), getReservedRegs(), and regclasses().
Referenced by addLiveInRegs(), llvm::AggressiveAntiDepBreaker::AggressiveAntiDepBreaker(), llvm::PPCFrameLowering::assignCalleeSavedSpillSlots(), CriticalPathStep(), and findTemporariesForLR().
◆ getCalleeSavedRegs()
|
pure virtual |
Return a null-terminated list of all of the callee-saved registers on this target.
The register should be in the order of desired callee-save stack frame offset. The first register is closest to the incoming stack pointer if stack grows down, and vice versa. Notice: This function does not take into account disabled CSRs. In most cases you will want to use instead the function getCalleeSavedRegs that is implemented in MachineRegisterInfo.
Referenced by addLiveInRegs(), llvm::createRegUsageInfoCollector(), llvm::SystemZFrameLowering::determineCalleeSaves(), llvm::MachineRegisterInfo::disableCalleeSavedRegister(), doesModifyCalleeSavedReg(), llvm::MipsFrameLowering::estimateStackSize(), findTemporariesForLR(), llvm::MachineRegisterInfo::getCalleeSavedRegs(), and llvm::tryFoldSPUpdateIntoPushPop().
◆ getCallPreservedMask()
|
inlinevirtual |
Return a mask of call-preserved registers for the given calling convention on the current function.
The mask should include all call-preserved aliases. This is used by the register allocator to determine which registers can be live across a call.
The mask is an array containing (TRI::getNumRegs()+31)/32 entries. A set bit indicates that all bits of the corresponding register are preserved across the function call. The bit mask is expected to be sub-register complete, i.e. if A is preserved, so are all its sub-registers.
Bits are numbered from the LSB, so the bit for physical register Reg can be found as (Mask[Reg / 32] >> Reg % 32) & 1.
A NULL pointer means that no register mask will be used, and call instructions should use implicit-def operands to indicate call clobbered registers.
Definition at line 482 of file TargetRegisterInfo.h.
Referenced by llvm::analyzeArguments(), llvm::MipsTargetLowering::getOpndList(), llvm::ARCTargetLowering::getTargetNodeName(), llvm::MipsCallLowering::lowerCall(), llvm::SystemZTargetLowering::LowerCall(), PrepareCall(), and unpackF64OnRV32DSoftABI().
◆ getCommonSubClass()
| const TargetRegisterClass * TargetRegisterInfo::getCommonSubClass | ( | const TargetRegisterClass * | A, |
| const TargetRegisterClass * | B, | ||
| const MVT::SimpleValueType | SVT = MVT::SimpleValueType::Any |
||
| ) | const |
Find the largest common subclass of A and B.
Return NULL if there is no common subclass. The common subclass should contain simple value type SVT if it is not the Any type.
Definition at line 257 of file TargetRegisterInfo.cpp.
References firstCommonClass(), and llvm::TargetRegisterClass::getSubClassMask().
Referenced by constrainRegClass(), definesFullReg(), llvm::LiveStacks::getOrCreateInterval(), llvm::SystemZRegisterInfo::getRegAllocationHints(), llvm::MachineInstr::getRegClassConstraintEffect(), isCrossCopy(), numVectorEltsOrZero(), llvm::CoalescerPair::setRegisters(), and shareSameRegisterFile().
◆ getCommonSuperRegClass()
| const TargetRegisterClass * TargetRegisterInfo::getCommonSuperRegClass | ( | const TargetRegisterClass * | RCA, |
| unsigned | SubA, | ||
| const TargetRegisterClass * | RCB, | ||
| unsigned | SubB, | ||
| unsigned & | PreA, | ||
| unsigned & | PreB | ||
| ) | const |
Find a common super-register class if it exists.
Find a register class, SuperRC and two sub-register indices, PreA and PreB, such that:
- PreA + SubA == PreB + SubB (using composeSubRegIndices()), and
- For all Reg in SuperRC: Reg:PreA in RCA and Reg:PreB in RCB, and
- SuperRC->getSize() >= max(RCA->getSize(), RCB->getSize()).
SuperRC will be chosen such that no super-class of SuperRC satisfies the requirements, and there is no register class with a smaller spill size that satisfies the requirements.
SubA and SubB must not be 0. Use getMatchingSuperRegClass() instead.
Either of the PreA and PreB sub-register indices may be returned as 0. In that case, the returned register class will be a sub-class of the corresponding argument register class.
The function returns NULL if no register class can be found.
Definition at line 288 of file TargetRegisterInfo.cpp.
References assert(), composeSubRegIndices(), firstCommonClass(), getRegSizeInBits(), llvm::SuperRegClassIterator::isValid(), and std::swap().
Referenced by getMatchingSuperRegClass(), isCrossCopy(), llvm::CoalescerPair::setRegisters(), and shareSameRegisterFile().
◆ getConstrainedRegClassForOperand()
|
inlinevirtual |
Definition at line 1000 of file TargetRegisterInfo.h.
Referenced by llvm::constrainOperandRegClass().
◆ getCostPerUse()
Return the additional cost of using this register instead of other registers in its class.
Definition at line 370 of file TargetRegisterInfo.h.
References llvm::TargetRegisterInfoDesc::CostPerUse.
Referenced by llvm::createGreedyRegisterAllocator(), and llvm::RegisterClassInfo::runOnMachineFunction().
◆ getCoveringLanes()
|
inline |
The lane masks returned by getSubRegIndexLaneMask() above can only be used to determine if sub-registers overlap - they can't be used to determine if a set of sub-registers completely cover another sub-register.
The X86 general purpose registers have two lanes corresponding to the sub_8bit and sub_8bit_hi sub-registers. Both sub_32bit and sub_16bit have lane masks '3', but the sub_16bit sub-register doesn't fully cover the sub_32bit sub-register.
On the other hand, the ARM NEON lanes fully cover their registers: The dsub_0 sub-register is completely covered by the ssub_0 and ssub_1 lanes. This is related to the CoveredBySubRegs property on register definitions.
This function returns a bit mask of lanes that completely cover their sub-registers. More precisely, given:
Covering = getCoveringLanes(); MaskA = getSubRegIndexLaneMask(SubA); MaskB = getSubRegIndexLaneMask(SubB);
If (MaskA & ~(MaskB & Covering)) == 0, then SubA is completely covered by SubB.
Definition at line 419 of file TargetRegisterInfo.h.
◆ getCrossCopyRegClass()
|
inlinevirtual |
Returns a legal register class to copy a register in the specified class to or from.
If it is possible to copy the register directly without using a cross register class copy, return the specified RC. Returns NULL if it is not possible to copy between two registers of the specified class.
Definition at line 729 of file TargetRegisterInfo.h.
◆ getCSRFirstUseCost()
|
inlinevirtual |
Allow the target to override the cost of using a callee-saved register for the first time.
Default value of 0 means we will use a callee-saved register if it is available.
Definition at line 841 of file TargetRegisterInfo.h.
◆ getFrameIndexInstrOffset()
|
inlinevirtual |
Get the offset from the referenced frame index in the instruction, if there is one.
Definition at line 901 of file TargetRegisterInfo.h.
Referenced by lookupCandidateBaseReg().
◆ getFrameRegister()
|
pure virtual |
Debug information queries.
getFrameRegister - This method should return the register used as a base for values allocated in the current stack frame.
Referenced by llvm::X86FrameLowering::assignCalleeSavedSpillSlots(), llvm::DIEDwarfExpression::DIEDwarfExpression(), llvm::MipsAsmPrinter::emitFrameDirective(), llvm::ARMAsmPrinter::EmitJumpTableTBInst(), llvm::RISCVFrameLowering::getFrameIndexReference(), llvm::TargetFrameLowering::getFrameIndexReference(), llvm::SelectionDAGISel::runOnMachineFunction(), srcMgrDiagHandler(), and llvm::DwarfCompileUnit::updateSubprogramScopeDIE().
◆ getLargestLegalSuperClass()
|
inlinevirtual |
Returns the largest super class of RC that is legal to use in the current sub-target and has the same spill size.
The returned register class can be used to create virtual registers which means that all its registers can be copied and spilled.
The default implementation is very conservative and doesn't allow the register allocator to inflate register classes.
Definition at line 738 of file TargetRegisterInfo.h.
Referenced by llvm::PPCRegisterInfo::getLargestLegalSuperClass(), getNumAllocatableRegsForConstraints(), matchPair(), llvm::MachineRegisterInfo::recomputeRegClass(), and llvm::RegisterClassInfo::runOnMachineFunction().
◆ getMatchingSuperReg()
|
inline |
Return a super-register of the specified register Reg so its sub-register of index SubIdx is Reg.
Definition at line 541 of file TargetRegisterInfo.h.
References B, llvm::MCRegisterInfo::getMatchingSuperReg(), and llvm::TargetRegisterClass::MC.
Referenced by copyHint(), llvm::AArch64InstrInfo::copyPhysReg(), llvm::PPCInstrInfo::copyPhysReg(), llvm::X86InstrInfo::copyPhysReg(), emitAlignedDPRCS2Restores(), emitAlignedDPRCS2Spills(), expandNOVLXLoad(), expandNOVLXStore(), llvm::ARMBaseInstrInfo::expandPostRAPseudo(), llvm::X86InstrInfo::expandPostRAPseudo(), llvm::AArch64InstrInfo::foldMemoryOperandImpl(), getCorrespondingDRegAndLane(), llvm::ARMBaseInstrInfo::getPartialRegUpdateClearance(), llvm::PPCTargetLowering::getRegForInlineAsmConstraint(), and llvm::CoalescerPair::setRegisters().
◆ getMatchingSuperRegClass()
|
virtual |
Return a subclass of the specified register class A so that each register in it has a sub-register of the specified sub-register index which is in the specified register class B.
TableGen will synthesize missing A sub-classes.
Definition at line 272 of file TargetRegisterInfo.cpp.
References assert(), firstCommonClass(), getCommonSuperRegClass(), llvm::TargetRegisterClass::getSubClassMask(), and llvm::SuperRegClassIterator::isValid().
Referenced by definesFullReg(), llvm::MachineInstr::getRegClassConstraintEffect(), getRegsUsedByPHIs(), isCrossCopy(), matchPair(), llvm::CoalescerPair::setRegisters(), and shareSameRegisterFile().
◆ getMinimalPhysRegClass()
| const TargetRegisterClass * TargetRegisterInfo::getMinimalPhysRegClass | ( | unsigned | reg, |
| MVT | VT = MVT::Other |
||
| ) | const |
Returns the Register Class of a physical register of the given type, picking the most sub register class of the right type that contains this physreg.
getMinimalPhysRegClass - Returns the Register Class of a physical register of the given type, picking the most sub register class of the right type that contains this physreg.
Definition at line 192 of file TargetRegisterInfo.cpp.
References assert(), llvm::TargetRegisterClass::hasSubClass(), isPhysicalRegister(), isTypeLegalForClass(), llvm::MVT::Other, and regclasses().
Referenced by llvm::DwarfExpression::addMachineReg(), llvm::X86FrameLowering::assignCalleeSavedSpillSlots(), llvm::HexagonFrameLowering::assignCalleeSavedSpillSlots(), assignCalleeSavedSpillSlots(), CheckForPhysRegDependency(), CriticalPathStep(), llvm::MipsFrameLowering::estimateStackSize(), llvm::AArch64InstrInfo::foldMemoryOperandImpl(), getDwarfRegNum(), llvm::RegisterBankInfo::getMinimalPhysRegClass(), llvm::HexagonEvaluator::getPhysRegBitWidth(), llvm::BitTracker::MachineEvaluator::getPhysRegBitWidth(), getRegSizeInBits(), insertCSRRestores(), insertCSRSaves(), llvm::rdf::CopyPropagation::interpretAsCopy(), isNopCopy(), llvm::AVRFrameLowering::restoreCalleeSavedRegisters(), llvm::XCoreFrameLowering::restoreCalleeSavedRegisters(), llvm::X86FrameLowering::restoreCalleeSavedRegisters(), llvm::PPCFrameLowering::restoreCalleeSavedRegisters(), llvm::rdf::CopyPropagation::run(), llvm::AVRFrameLowering::spillCalleeSavedRegisters(), llvm::MipsSEFrameLowering::spillCalleeSavedRegisters(), llvm::XCoreFrameLowering::spillCalleeSavedRegisters(), llvm::X86FrameLowering::spillCalleeSavedRegisters(), and llvm::PPCFrameLowering::spillCalleeSavedRegisters().
◆ getNoPreservedMask()
Return a register mask that clobbers everything.
Definition at line 489 of file TargetRegisterInfo.h.
References llvm_unreachable.
Referenced by llvm::MachineBasicBlock::getBeginClobberMask(), and llvm::MachineBasicBlock::getEndClobberMask().
◆ getNumRegClasses()
|
inline |
Definition at line 690 of file TargetRegisterInfo.h.
Referenced by llvm::TargetLoweringBase::findRepresentativeClass(), firstCommonClass(), getOpenCLAlignment(), llvm::MIRParserImpl::initializeJumpTableInfo(), llvm::RegisterBank::print(), llvm::ResourcePriorityQueue::ResourcePriorityQueue(), and llvm::RegisterClassInfo::runOnMachineFunction().
◆ getNumRegPressureSets()
|
pure virtual |
Get the number of dimensions of register pressure.
Referenced by LoopIsOuterMostWithPredecessor(), llvm::RegisterClassInfo::runOnMachineFunction(), and llvm::SIScheduleBlockScheduler::SIScheduleBlockScheduler().
◆ getPointerRegClass()
|
inlinevirtual |
Returns a TargetRegisterClass used for pointer values.
If a target supports multiple different pointer register classes, kind specifies which one is indicated.
Definition at line 720 of file TargetRegisterInfo.h.
References llvm_unreachable.
Referenced by llvm::WebAssemblyRegisterInfo::eliminateFrameIndex(), getOffsetFromIndices(), llvm::TargetInstrInfo::getRegClass(), llvm::MachineInstr::getRegClassConstraint(), isOpcWithIntImmediate(), and lookupCandidateBaseReg().
◆ getRegAllocationHints()
|
virtual |
Get a list of 'hint' registers that the register allocator should try first when allocating a physical register for the virtual register VirtReg.
These registers are effectively moved to the front of the allocation order. If true is returned, regalloc will try to only use hints to the greatest extent possible even if it means spilling.
The Order argument is the allocation order for VirtReg's register class as returned from RegisterClassInfo::getOrder(). The hint registers must come from Order, and they must not be reserved.
The default implementation of this function will only add target independent register allocation hints. Targets that override this function should typically call this default implementation as well and expect to see generic copy hints added.
Definition at line 392 of file TargetRegisterInfo.cpp.
References llvm::VirtRegMap::getPhys(), llvm::MachineRegisterInfo::getRegAllocationHints(), llvm::MachineFunction::getRegInfo(), llvm::SmallSet< T, N, C >::insert(), llvm::is_contained(), isPhysicalRegister(), llvm::MachineRegisterInfo::isReserved(), isVirtualRegister(), MRI, llvm::SmallVectorTemplateBase< T, bool >::push_back(), and Reg.
Referenced by llvm::AllocationOrder::AllocationOrder(), llvm::SystemZRegisterInfo::getRegAllocationHints(), and llvm::ARMBaseRegisterInfo::getRegAllocationHints().
◆ getRegAsmName()
Return the assembly name for Reg.
Definition at line 961 of file TargetRegisterInfo.h.
References getName().
Referenced by llvm::SIRegisterInfo::getRegAsmName(), and llvm::TargetLowering::getRegForInlineAsmConstraint().
◆ getRegClass()
|
inline |
Returns the register class associated with the enumeration value.
See class MCOperandInfo.
Definition at line 696 of file TargetRegisterInfo.h.
References assert().
Referenced by llvm::AArch64RegisterBankInfo::AArch64RegisterBankInfo(), llvm::ARMRegisterBankInfo::ARMRegisterBankInfo(), llvm::InstructionSelector::executeMatchTable(), llvm::TargetLoweringBase::findRepresentativeClass(), findTemporariesForLR(), firstCommonClass(), getAllocatableClass(), getOpenCLAlignment(), llvm::TargetInstrInfo::getRegClass(), llvm::MachineInstr::getRegClassConstraint(), llvm::MipsTargetLowering::getTypeForExtReturn(), llvm::MIRParserImpl::initializeJumpTableInfo(), llvm::MachineInstr::print(), llvm::ARMAsmPrinter::PrintAsmOperand(), selectCopy(), and llvm::X86RegisterBankInfo::X86RegisterBankInfo().
◆ getRegClassInfo()
|
inlineprotected |
Definition at line 678 of file TargetRegisterInfo.h.
References llvm::TargetRegisterClass::getID().
◆ getRegClassName()
|
inline |
Returns the name of the register class.
Definition at line 702 of file TargetRegisterInfo.h.
References llvm::SystemZICMP::Any, llvm::MCRegisterInfo::getRegClassName(), and llvm::TargetRegisterClass::MC.
Referenced by llvm::RegAllocBase::allocatePhysRegs(), llvm::LiveRangeEdit::calculateRegClassAndHint(), CriticalPathStep(), INITIALIZE_PASS(), llvm::MIRParserImpl::initializeJumpTableInfo(), isImplicitOperandIn(), isTerminalReg(), llvm::HexagonEvaluator::mask(), matchPair(), llvm::LiveStacks::print(), llvm::VirtRegMap::print(), llvm::MachineInstr::print(), PrintNodeInfo(), llvm::printRegClassOrBank(), llvm::RegisterClassInfo::runOnMachineFunction(), and llvm::ExecutionDomainFix::runOnMachineFunction().
◆ getRegClassPressureSets()
|
pure virtual |
Get the dimensions of register pressure impacted by this register class.
Returns a -1 terminated array of pressure set IDs.
Referenced by llvm::RegisterClassInfo::computePSetLimit(), isOperandKill(), and llvm::PSetIterator::PSetIterator().
◆ getRegClassWeight()
|
pure virtual |
Get the weight in units of pressure for this register class.
Referenced by llvm::RegisterClassInfo::computePSetLimit(), isOperandKill(), llvm::PSetIterator::PSetIterator(), and llvm::ARMBaseRegisterInfo::shouldCoalesce().
◆ getRegMaskNames()
Referenced by llvm::MIPrinter::print().
◆ getRegMasks()
Return all the call-preserved register masks defined for this target.
Referenced by llvm::rdf::PhysicalRegisterInfo::PhysicalRegisterInfo().
◆ getRegPressureLimit()
|
inlinevirtual |
Return the register pressure "high water mark" for the specific register class.
The scheduler is in high register pressure mode (for the specific register class) if it goes over the limit.
Note: this is the old register pressure model that relies on a manually specified representative register class per value type.
Definition at line 751 of file TargetRegisterInfo.h.
Referenced by llvm::ResourcePriorityQueue::ResourcePriorityQueue().
◆ getRegPressureSetLimit()
|
pure virtual |
Get the register unit pressure limit for this dimension.
This limit must be adjusted dynamically for reserved registers.
Referenced by llvm::RegisterClassInfo::computePSetLimit(), and LoopIsOuterMostWithPredecessor().
◆ getRegPressureSetName()
|
pure virtual |
Get the name of this register unit pressure set.
Referenced by llvm::PressureDiff::dump(), and llvm::dumpRegSetPressure().
◆ getRegPressureSetScore()
|
inlinevirtual |
Return a heuristic for the machine scheduler to compare the profitability of increasing one register pressure set versus another.
The scheduler will prefer increasing the register pressure of the set which returns the largest value for this function.
Definition at line 760 of file TargetRegisterInfo.h.
References Matrix.
Referenced by llvm::tryPressure().
◆ getRegSizeInBits() [1/2]
|
inline |
Return the size in bits of a register from class RC.
Definition at line 314 of file TargetRegisterInfo.h.
Referenced by llvm::DwarfExpression::addMachineReg(), llvm::RegisterBankInfo::applyDefaultMapping(), llvm::X86InstrInfo::classifyLEAReg(), llvm::AArch64FrameLowering::determineCalleeSaves(), llvm::ARMAsmPrinter::EmitJumpTableTBInst(), llvm::AArch64InstrInfo::foldMemoryOperandImpl(), llvm::SystemZInstrInfo::foldMemoryOperandImpl(), llvm::X86InstrInfo::foldMemoryOperandImpl(), getCommonSuperRegClass(), llvm::SIInstrInfo::getMemOperandWithOffset(), llvm::HexagonEvaluator::getPhysRegBitWidth(), llvm::BitTracker::MachineEvaluator::getPhysRegBitWidth(), llvm::BitTracker::MachineEvaluator::getRegBitWidth(), getRegSizeInBits(), llvm::X86InstrInfo::insertSelect(), isNonFoldablePartialRegisterLoad(), llvm::RISCVInstrInfo::loadRegFromStackSlot(), llvm::X86CallLowering::lowerReturn(), MakeM0Inst(), matchPair(), llvm::X86InstrInfo::optimizeCompareInstr(), llvm::MipsAsmPrinter::printSavedRegsBitmask(), llvm::AVRFrameLowering::restoreCalleeSavedRegisters(), llvm::AVRFrameLowering::spillCalleeSavedRegisters(), llvm::RISCVInstrInfo::storeRegToStackSlot(), llvm::X86CallLowering::X86CallLowering(), and X86ChooseCmpImmediateOpcode().
◆ getRegSizeInBits() [2/2]
| unsigned TargetRegisterInfo::getRegSizeInBits | ( | unsigned | Reg, |
| const MachineRegisterInfo & | MRI | ||
| ) | const |
Returns size in bits of a phys/virtual/generic register.
Definition at line 467 of file TargetRegisterInfo.cpp.
References assert(), getMinimalPhysRegClass(), llvm::MachineRegisterInfo::getRegClass(), getRegSizeInBits(), llvm::LLT::getSizeInBits(), llvm::MachineRegisterInfo::getType(), isPhysicalRegister(), and llvm::LLT::isValid().
◆ getRegUnitPressureSets()
|
pure virtual |
Get the dimensions of register pressure impacted by this register unit.
Returns a -1 terminated array of pressure set IDs.
Referenced by llvm::PSetIterator::PSetIterator().
◆ getRegUnitWeight()
Get the weight in units of pressure for this register unit.
Referenced by llvm::PSetIterator::PSetIterator().
◆ getReservedRegs()
|
pure virtual |
Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times, e.g.
stack pointer, return address. A reserved register:
- is not allocatable
- is considered always live
- is ignored by liveness tracking It is often necessary to reserve the super registers of a reserved register as well, to avoid them getting allocated indirectly. You may use markSuperRegs() and checkAllSuperRegsMarked() in this case.
Referenced by llvm::HexagonFrameLowering::assignCalleeSavedSpillSlots(), llvm::MachineRegisterInfo::freezeReservedRegs(), getAllocatableSet(), and llvm::MachineFunction::verify().
◆ getSpillAlignment()
|
inline |
Return the minimum required alignment in bytes for a spill slot for a register of this class.
Definition at line 326 of file TargetRegisterInfo.h.
Referenced by llvm::PPCFrameLowering::addScavengingSpillSlot(), llvm::X86FrameLowering::assignCalleeSavedSpillSlots(), llvm::HexagonFrameLowering::assignCalleeSavedSpillSlots(), assignCalleeSavedSpillSlots(), llvm::VirtRegMap::assignVirt2Phys(), llvm::MipsFunctionInfo::createEhDataRegsFI(), llvm::XCoreFunctionInfo::createEHSpillSlot(), llvm::XCoreFunctionInfo::createFPSpillSlot(), llvm::MipsFunctionInfo::createISRRegFI(), llvm::XCoreFunctionInfo::createLRSpillSlot(), llvm::MipsSEFrameLowering::determineCalleeSaves(), llvm::ARMFrameLowering::determineCalleeSaves(), llvm::AArch64FrameLowering::determineCalleeSaves(), llvm::MipsFunctionInfo::getMoveF64ViaSpillFI(), INITIALIZE_PASS(), llvm::HexagonInstrInfo::loadRegFromStackSlot(), llvm::RISCVFrameLowering::processFunctionBeforeFrameFinalized(), llvm::XCoreFrameLowering::processFunctionBeforeFrameFinalized(), llvm::ARCFrameLowering::processFunctionBeforeFrameFinalized(), and llvm::HexagonInstrInfo::storeRegToStackSlot().
◆ getSpillSize()
|
inline |
Return the size in bytes of the stack slot allocated to hold a spilled copy of a register from class RC.
Definition at line 320 of file TargetRegisterInfo.h.
Referenced by llvm::PPCFrameLowering::addScavengingSpillSlot(), llvm::X86FrameLowering::assignCalleeSavedSpillSlots(), llvm::HexagonFrameLowering::assignCalleeSavedSpillSlots(), assignCalleeSavedSpillSlots(), llvm::VirtRegMap::assignVirt2Phys(), llvm::MipsFunctionInfo::createEhDataRegsFI(), llvm::XCoreFunctionInfo::createEHSpillSlot(), llvm::XCoreFunctionInfo::createFPSpillSlot(), llvm::MipsFunctionInfo::createISRRegFI(), llvm::XCoreFunctionInfo::createLRSpillSlot(), llvm::MipsSEFrameLowering::determineCalleeSaves(), llvm::ARMFrameLowering::determineCalleeSaves(), llvm::AArch64FrameLowering::determineCalleeSaves(), llvm::MipsFrameLowering::estimateStackSize(), llvm::TargetLoweringBase::findRepresentativeClass(), getDwarfRegNum(), llvm::MipsFunctionInfo::getMoveF64ViaSpillFI(), llvm::TargetInstrInfo::getStackSlotRange(), INITIALIZE_PASS(), llvm::HexagonInstrInfo::isValidOffset(), llvm::X86InstrInfo::loadRegFromAddr(), llvm::ARCInstrInfo::loadRegFromStackSlot(), llvm::AArch64InstrInfo::loadRegFromStackSlot(), llvm::ARMBaseInstrInfo::loadRegFromStackSlot(), llvm::SIInstrInfo::loadRegFromStackSlot(), llvm::X86InstrInfo::loadRegFromStackSlot(), llvm::RISCVFrameLowering::processFunctionBeforeFrameFinalized(), llvm::XCoreFrameLowering::processFunctionBeforeFrameFinalized(), llvm::ARCFrameLowering::processFunctionBeforeFrameFinalized(), llvm::X86InstrInfo::storeRegToAddr(), llvm::ARCInstrInfo::storeRegToStackSlot(), llvm::AArch64InstrInfo::storeRegToStackSlot(), llvm::ARMBaseInstrInfo::storeRegToStackSlot(), llvm::SIInstrInfo::storeRegToStackSlot(), llvm::X86InstrInfo::storeRegToStackSlot(), and llvm::X86InstrInfo::unfoldMemoryOperand().
◆ getSubClassWithSubReg()
|
inlinevirtual |
Returns the largest legal sub-class of RC that supports the sub-register index Idx.
If no such sub-class exists, return NULL. If all registers in RC already have an Idx sub-register, return RC.
TableGen generates a version of this function that is good enough in most cases. Targets can override if they have constraints that TableGen doesn't understand. For example, the x86 sub_8bit sub-register index is supported by the full GR32 register class in 64-bit mode, but only by the GR32_ABCD regiister class in 32-bit mode.
TableGen will synthesize missing RC sub-classes.
Definition at line 577 of file TargetRegisterInfo.h.
References assert().
Referenced by llvm::SplitEditor::dump(), llvm::FastISel::fastEmitInst_extractsubreg(), llvm::MachineInstr::getRegClassConstraintEffect(), and matchPair().
◆ getSubRegIndexLaneMask()
|
inline |
Return a bitmask representing the parts of a register that are covered by SubIdx.
- See also
- LaneBitmask.
SubIdx == 0 is allowed, it has the lane mask ~0u.
Definition at line 391 of file TargetRegisterInfo.h.
References assert().
Referenced by llvm::LiveIntervals::addKillFlags(), llvm::LivePhysRegs::available(), llvm::LiveRangeCalc::calculate(), llvm::LiveInterval::computeSubRangeUndefs(), llvm::LiveRangeCalc::createDeadDefs(), llvm::SplitEditor::dump(), llvm::LiveRangeEdit::eraseVirtReg(), findUseBetween(), llvm::rdf::PhysicalRegisterInfo::getAliasSet(), getDefRegMask(), llvm::ScheduleDAGInstrs::getLaneMaskForMO(), getLiveLanesAt(), getUsedRegMask(), llvm::HexagonBlockRanges::HexagonBlockRanges(), isVirtualRegisterOperand(), matchPair(), llvm::rdf::CopyPropagation::run(), llvm::LiveIntervals::shrinkToUses(), and llvm::LiveIntervals::HMEditor::updateAllRanges().
◆ getSubRegIndexName()
Return the human-readable symbolic target-specific name for the specified SubRegIndex.
Definition at line 381 of file TargetRegisterInfo.h.
References assert().
Referenced by llvm::MachineOperand::print(), llvm::printReg(), and llvm::MachineOperand::printSubRegIdx().
◆ hasRegUnit()
Returns true if Reg contains RegUnit.
Definition at line 440 of file TargetRegisterInfo.h.
References llvm::MCRegisterInfo::DiffListIterator::isValid(), and MRI.
Referenced by matchPair(), and llvm::LiveIntervals::HMEditor::updateAllRanges().
◆ hasReservedSpillSlot()
|
inlinevirtual |
Return true if target has reserved a spill slot in the stack frame of the given function for the specified register.
e.g. On x86, if the frame register is required, the first fixed stack object is reserved as its spill slot. This tells PEI not to create a new stack frame object for the given register. It should be called only after determineCalleeSaves().
Definition at line 880 of file TargetRegisterInfo.h.
Referenced by assignCalleeSavedSpillSlots().
◆ index2StackSlot()
|
inlinestatic |
Convert a non-negative frame index to a stack slot register value.
Definition at line 281 of file TargetRegisterInfo.h.
References assert().
Referenced by llvm::LiveStacks::getOrCreateInterval(), and llvm::rdf::PhysicalRegisterInfo::getRegMaskId().
◆ index2VirtReg()
Convert a 0-based index to a virtual register number.
This is the inverse operation of VirtReg2IndexFunctor below.
Definition at line 309 of file TargetRegisterInfo.h.
Referenced by llvm::LiveIntervals::addKillFlags(), llvm::LiveVariables::addNewBlock(), llvm::calculateSpillWeightsAndHints(), llvm::MachineRegisterInfo::clearVirtRegs(), computeWeight(), llvm::MIRPrinter::convert(), llvm::MachineRegisterInfo::createIncompleteVirtualRegister(), findStartOfTree(), llvm::getLiveRegs(), getOpenCLAlignment(), HasArgumentDef(), llvm::RegAllocBase::init(), INITIALIZE_PASS(), isCrossCopy(), isDebug(), isSSA(), matchPair(), llvm::VirtRegMap::print(), llvm::LiveIntervals::print(), llvm::GCNRPTracker::printLiveRegs(), llvm::printLivesAt(), llvm::LiveIntervals::releaseMemory(), llvm::InstructionSelect::runOnMachineFunction(), llvm::LiveVariables::runOnMachineFunction(), llvm::MachineBasicBlock::SplitCriticalEdge(), subRangeLiveAt(), usedAsAddr(), and llvm::MachineRegisterInfo::verifyUseLists().
◆ isAsmClobberable()
|
inlinevirtual |
Returns false if we can't guarantee that Physreg, specified as an IR asm clobber constraint, will be preserved across the statement.
Definition at line 515 of file TargetRegisterInfo.h.
Referenced by EmitGCCInlineAsmStr().
◆ isCallerPreservedPhysReg()
|
inlinevirtual |
Physical registers that may be modified within a function but are guaranteed to be restored before any uses.
This is useful for targets that have call sequences where a GOT register may be updated by the caller prior to a call and is guaranteed to be restored (also by the caller) after the call.
Definition at line 529 of file TargetRegisterInfo.h.
Referenced by isCallerPreservedOrConstPhysReg(), llvm::MachineRegisterInfo::isCallerPreservedOrConstPhysReg(), isCopyFeedingInvariantStore(), and isInvariantStore().
◆ isConstantPhysReg()
Returns true if PhysReg is unallocatable and constant throughout the function.
Used by MachineRegisterInfo::isConstantPhysReg().
Definition at line 522 of file TargetRegisterInfo.h.
Referenced by llvm::LiveRegUnits::accumulateUsedDefed(), and llvm::MachineRegisterInfo::isConstantPhysReg().
◆ isFrameOffsetLegal()
|
inlinevirtual |
Determine whether a given base register plus offset immediate is encodable to resolve a frame index.
Definition at line 932 of file TargetRegisterInfo.h.
References llvm_unreachable.
Referenced by lookupCandidateBaseReg().
◆ isInAllocatableClass()
Return true if the register is in the allocation of any register class.
Definition at line 375 of file TargetRegisterInfo.h.
References llvm::TargetRegisterInfoDesc::inAllocatableClass.
Referenced by llvm::MachineRegisterInfo::isAllocatable().
◆ isPhysicalRegister()
Return true if the specified register number is in the physical register namespace.
Definition at line 288 of file TargetRegisterInfo.h.
References assert().
Referenced by llvm::LiveRegUnits::accumulate(), llvm::LiveRegUnits::accumulateUsedDefed(), addDefsUsesToList(), llvm::ARMBaseInstrInfo::AddDReg(), llvm::MachineBasicBlock::addLiveIn(), llvm::DwarfExpression::addMachineReg(), addRegAndItsAliases(), llvm::MachineInstr::addRegisterDead(), llvm::MachineInstr::addRegisterDefined(), llvm::MachineInstr::addRegisterKilled(), llvm::ScheduleDAGInstrs::addSchedBarrierDeps(), addSegmentsWithValNo(), AddSubReg(), addToListsIfDependent(), llvm::LivePhysRegs::addUses(), llvm::AMDGPUInstructionSelector::AMDGPUInstructionSelector(), llvm::MachineOperandIteratorBase::analyzePhysReg(), llvm::LiveRangeEdit::anyRematerializable(), llvm::HexagonSubtarget::CallMutation::apply(), llvm::RegisterBankInfo::applyDefaultMapping(), llvm::VirtRegMap::assignVirt2Phys(), llvm::biasPhysReg(), llvm::ARMBaseInstrInfo::breakPartialRegDependency(), llvm::ScheduleDAGInstrs::buildSchedGraph(), llvm::calculateDbgEntityHistory(), canCompareBeNewValueJump(), canFoldCopy(), canFoldIntoMOVCC(), canFoldIntoSelect(), canMoveInstsAcrossMemOp(), llvm::X86InstrInfo::classifyLEAReg(), llvm::MachineInstr::clearRegisterKills(), llvm::TargetInstrInfo::commuteInstructionImpl(), llvm::constrainSelectedInstRegOperands(), ConvertDoubleToBytes(), llvm::SelectionDAGBuilder::CopyValueToVirtualRegister(), createBBSelectReg(), definesFullReg(), llvm::InstrEmitter::EmitDbgLabel(), llvm::RegScavenger::enterBasicBlockEnd(), llvm::LiveRangeEdit::eraseVirtReg(), llvm::HexagonEvaluator::evaluate(), llvm::InstructionSelector::executeMatchTable(), llvm::HexagonBlockRanges::expandToSubRegs(), llvm::finalizeBundle(), findHoistingInsertPosAndDeps(), findOnlyInterestingUse(), llvm::MachineInstr::findRegisterDefOperandIdx(), llvm::CoalescerPair::flip(), llvm::AArch64InstrInfo::foldMemoryOperandImpl(), llvm::X86InstrInfo::foldMemoryOperandImpl(), foldVGPRCopyIntoRegSequence(), llvm::RegScavenger::forward(), llvm::TargetInstrInfo::genAlternativeCodeSequence(), llvm::rdf::PhysicalRegisterInfo::getAliasSet(), llvm::RegBankSelect::getAnalysisUsage(), llvm::BitTracker::MachineEvaluator::getCell(), getConstant(), getDataDeps(), getDwarfRegNum(), llvm::AArch64RegisterBankInfo::getInstrMapping(), llvm::RegisterClassInfo::getLastCalleeSavedAlias(), getMappedReg(), getMinimalPhysRegClass(), llvm::RegisterBankInfo::getMinimalPhysRegClass(), getMopState(), getNewSource(), getNewValueJumpOpcode(), llvm::rdf::DataFlowGraph::getNextShadow(), llvm::HexagonEvaluator::getPhysRegBitWidth(), llvm::BitTracker::MachineEvaluator::getPhysRegBitWidth(), llvm::ARMBaseRegisterInfo::getRegAllocationHints(), getRegAllocationHints(), llvm::RegisterBankInfo::getRegBank(), llvm::BitTracker::MachineEvaluator::getRegBitWidth(), getRegisterName(), getRegSizeInBits(), llvm::getRegState(), getSubRegForIndex(), llvm::X86InstrInfo::getUndefRegClearance(), llvm::LiveVariables::HandleVirtRegDef(), llvm::VirtRegMap::hasKnownPreference(), hasRegisterDependency(), hasUseAfterLoop(), INITIALIZE_PASS(), instAccessReg(), InstructionStoresToFI(), llvm::rdf::CopyPropagation::interpretAsCopy(), llvm::PPCRegisterInfo::isCallerPreservedPhysReg(), llvm::CoalescerPair::isCoalescable(), llvm::MachineRegisterInfo::isConstantPhysReg(), isCopyFeedingInvariantStore(), isCopyToReg(), isCrossCopy(), llvm::HexagonInstrInfo::isDependent(), isEvenReg(), isIdenticalOp(), isKilled(), isLocalCopy(), llvm::MachineOperand::isRenamable(), IsSafeToMove(), isSubRegOf(), isTerminalReg(), llvm::isTriviallyDead(), isVirtualRegisterOperand(), llvm::SITargetLowering::legalizeTargetIndependentNode(), llvm::Thumb1InstrInfo::loadRegFromStackSlot(), llvm::Thumb2InstrInfo::loadRegFromStackSlot(), llvm::ARMBaseInstrInfo::loadRegFromStackSlot(), loadRegPairFromStackSlot(), llvm::rdf::DataFlowGraph::makeRegRef(), matchPair(), matchSwap(), MIIsInTerminatorSequence(), MoveAndTeeForMultiUse(), llvm::SIInstrInfo::moveToVALU(), performSink(), llvm::LiveIntervals::print(), llvm::MachineOperand::print(), llvm::ARMAsmPrinter::printOperand(), llvm::recomputeLivenessFlags(), llvm::LivePhysRegs::removeDefs(), removeExternalCFGEdges(), llvm::MachineRegisterInfo::replaceRegWith(), llvm::rdf::Liveness::resetKills(), llvm::SelectionDAGISel::runOnMachineFunction(), llvm::MachineOperand::setIsRenamable(), llvm::MachineInstr::setPhysRegsDeadExcept(), llvm::CoalescerPair::setRegisters(), llvm::MachineBasicBlock::SplitCriticalEdge(), llvm::LiveDebugVariables::splitRegister(), llvm::LiveRegUnits::stepBackward(), llvm::LivePhysRegs::stepForward(), storeRegPairToStackSlot(), llvm::Thumb1InstrInfo::storeRegToStackSlot(), llvm::MachineInstr::substituteRegister(), llvm::MachineOperand::substPhysReg(), llvm::LiveIntervals::HMEditor::updateAllRanges(), UpdateOperandRegClass(), updatePhysDepsDownwards(), updatePhysDepsUpwards(), llvm::DwarfCompileUnit::updateSubprogramScopeDIE(), llvm::SIInstrInfo::verifyInstruction(), and llvm::VirtRegAuxInfo::weightCalcHelper().
◆ isStackSlot()
isStackSlot - Sometimes it is useful the be able to store a non-negative frame index in a variable that normally holds a register.
isStackSlot() returns true if Reg is in the range used for stack slots.
Note that isVirtualRegister() and isPhysicalRegister() cannot handle stack slots, so if a variable may contains a stack slot, always check isStackSlot() first.
Definition at line 270 of file TargetRegisterInfo.h.
Referenced by isFullUndefDef(), llvm::rdf::PhysicalRegisterInfo::isRegMaskId(), and llvm::printReg().
◆ isTypeLegalForClass()
|
inline |
Return true if the given TargetRegisterClass has the ValueType T.
Definition at line 331 of file TargetRegisterInfo.h.
References I, and llvm::MVT::Other.
Referenced by firstCommonClass(), llvm::AVRRegisterInfo::getLargestLegalSuperClass(), getMinimalPhysRegClass(), llvm::X86TargetLowering::getRegForInlineAsmConstraint(), llvm::TargetLowering::getRegForInlineAsmConstraint(), GetRegistersForValue(), llvm::WebAssemblyAsmPrinter::getRegType(), getRetpolineSymbol(), llvm::MipsSEInstrInfo::loadRegFromStack(), llvm::AVRInstrInfo::loadRegFromStackSlot(), llvm::MipsSEInstrInfo::storeRegToStack(), and llvm::AVRInstrInfo::storeRegToStackSlot().
◆ isVirtualRegister()
Return true if the specified register number is in the virtual register namespace.
Definition at line 295 of file TargetRegisterInfo.h.
References assert().
Referenced by llvm::RegsForValue::AddInlineAsmOperands(), llvm::LiveVariables::addNewBlock(), llvm::MachineRegisterInfo::addRegAllocationHint(), llvm::ScheduleDAGInstrs::addSchedBarrierDeps(), addSegmentsWithValNo(), llvm::RegisterOperands::adjustLaneLiveness(), llvm::GCNDownwardRPTracker::advanceToNext(), llvm::RegAllocBase::allocatePhysRegs(), allPhiOperandsUndefined(), llvm::VirtRegMap::assignVirt2Phys(), llvm::VirtRegMap::assignVirt2StackSlot(), llvm::ScheduleDAGInstrs::buildSchedGraph(), llvm::calculateDbgEntityHistory(), canClobberPhysRegDefs(), canCombine(), canFoldCopy(), canFoldIntoCSel(), canFoldIntoMOVCC(), canFoldIntoSelect(), CheckForPhysRegDependency(), llvm::X86InstrInfo::classifyLEAReg(), llvm::VirtRegMap::clearVirt(), collectChangingRegs(), collectVirtualRegUses(), llvm::ScheduleDAGMILive::collectVRegUses(), computeBranchTargetAndInversion(), llvm::HexagonBlockRanges::computeDeadMap(), computeLiveOuts(), llvm::ScheduleDAGSDNodes::computeOperandLatency(), llvm::FunctionLoweringInfo::ComputePHILiveOutRegInfo(), llvm::LiveInterval::computeSubRangeUndefs(), llvm::constrainOperandRegClass(), llvm::FastISel::constrainOperandRegClass(), llvm::ARMBaseInstrInfo::convertToThreeAddress(), llvm::SystemZInstrInfo::convertToThreeAddress(), llvm::X86InstrInfo::convertToThreeAddress(), copyHint(), llvm::WebAssemblyInstrInfo::copyPhysReg(), createBBSelectReg(), llvm::createCopyConstrainDAGMutation(), llvm::createGreedyRegisterAllocator(), llvm::createR600ISelDag(), llvm::createSIWholeQuadModePass(), definesFullReg(), doCandidateWalk(), dumpMachineInstrRangeWithSlotIndex(), llvm::WebAssemblyRegisterInfo::eliminateFrameIndex(), llvm::R600TargetLowering::EmitInstrWithCustomInserter(), llvm::MachineInstr::eraseFromParentAndMarkDBGValuesForRemoval(), llvm::LiveRangeEdit::eraseVirtReg(), llvm::HexagonEvaluator::evaluate(), llvm::BitTracker::MachineEvaluator::evaluate(), llvm::HexagonBlockRanges::expandToSubRegs(), llvm::FastISel::fastEmitInst_extractsubreg(), findHoistingInsertPosAndDeps(), llvm::SIRegisterInfo::findReachingDef(), findSinkableLocalRegDef(), findSRegBaseAndIndex(), findSurvivorBackwards(), foldImmediates(), llvm::AArch64InstrInfo::foldMemoryOperandImpl(), llvm::TargetInstrInfo::genAlternativeCodeSequence(), genFusedMultiply(), genMaddR(), getCallTargetRegOpnd(), llvm::BitTracker::MachineEvaluator::getCell(), llvm::RegsForValue::getCopyFromRegs(), getCopyRegClasses(), getDefRegMask(), getDepthOfOptCmov(), llvm::NVPTXAsmPrinter::getFunctionFrameSymbol(), llvm::MachineInstrExpressionTrait::getHashValue(), getImmOrMaterializedImm(), llvm::R600InstrInfo::getIndirectIndexBegin(), getLanesWithProperty(), getLiveLanesAt(), getLiveRange(), getMappedReg(), llvm::MachineRegisterInfo::getMaxLaneMaskForVReg(), getMopState(), getNewSource(), getOModValue(), llvm::PPCInstrInfo::getOperandLatency(), llvm::SIInstrInfo::getOpRegClass(), llvm::ARMBaseInstrInfo::getPartialRegUpdateClearance(), llvm::X86InstrInfo::getPartialRegUpdateClearance(), llvm::VirtRegMap::getPhys(), llvm::SIRegisterInfo::getPhysRegClass(), llvm::MachineRegisterInfo::getRegAllocationHint(), llvm::MachineRegisterInfo::getRegAllocationHints(), getRegAllocationHints(), llvm::BitTracker::MachineEvaluator::getRegBitWidth(), llvm::SIRegisterInfo::getRegClassForReg(), llvm::RegScavenger::getRegsAvailable(), getRegsUsedByPHIs(), llvm::MachineRegisterInfo::getSimpleHint(), llvm::VirtRegMap::getStackSlot(), llvm::MachineRegisterInfo::getType(), getUnderlyingArgReg(), getUsedRegMask(), llvm::LiveVariables::getVarInfo(), GetVRegRenameMap(), llvm::getVRegSubRegDef(), llvm::LiveVariables::HandleVirtRegDef(), llvm::VirtRegMap::hasKnownPreference(), hasOnlyLiveInOpers(), hasOnlyLiveOutUses(), llvm::VirtRegMap::hasPreferredPhys(), llvm::TargetInstrInfo::hasReassociableOperands(), hasUseAfterLoop(), hasVGPROperands(), hoistAndMergeSGPRInits(), INITIALIZE_PASS(), llvm::RegPressureTracker::initLiveThru(), insertUndefLaneMask(), instAccessReg(), isCallerPreservedOrConstPhysReg(), llvm::WebAssembly::isChild(), isCopyFeedingInvariantStore(), isCrossCopy(), isCVTAToLocalCombinationCandidate(), isDebug(), isDefBetween(), isDefInSubRange(), isEqual(), isFPR64(), isFullCopyOf(), llvm::MachineInstr::isIdenticalTo(), isImplicitOperandIn(), isInvariantStore(), llvm::SIInstrInfo::isLegalRegOperand(), llvm::R600InstrInfo::isLegalToSplitMBBAt(), isNopCopy(), isOperandKill(), isPhysicalRegCopy(), llvm::R600RegisterInfo::isPhysRegLiveAcrossClauses(), isPlainlyKilled(), isRematerializable(), llvm::SIRegisterInfo::isSGPRReg(), llvm::PPCInstrInfo::isSignOrZeroExtended(), isUseSafeToFold(), isVirtualRegisterOperand(), llvm::SIInstrInfo::legalizeOperands(), llvm::Mips16InstrInfo::loadImmediate(), llvm::Thumb2InstrInfo::loadRegFromStackSlot(), llvm::AArch64InstrInfo::loadRegFromStackSlot(), llvm::SIInstrInfo::loadRegFromStackSlot(), lookThruCopyLike(), MatchingStackOffset(), matchPair(), matchSwap(), llvm::BitTracker::RegisterCell::meet(), llvm::SIInstrInfo::moveToVALU(), needsStackFrame(), OneUseDominatesOtherUses(), llvm::AArch64InstrInfo::optimizeCondBranch(), optimizeVcndVcmpPair(), llvm::SMSchedule::orderDependence(), populateCandidates(), llvm::MachineOperand::print(), printExtendedName(), llvm::printReg(), llvm::printVRegOrUnit(), llvm::ARMBaseInstrInfo::produceSameValue(), profitImm(), propagateLocalCopies(), llvm::PSetIterator::PSetIterator(), pushDepHeight(), llvm::BitTracker::MachineEvaluator::putCell(), llvm::R600InstrInfo::readsLDSSrcReg(), llvm::TargetInstrInfo::reassociateOps(), llvm::GCNUpwardRPTracker::recede(), llvm::RegPressureTracker::recede(), regIsPICBase(), llvm::WebAssemblyAsmPrinter::regToString(), llvm::R600SchedStrategy::releaseBottomNode(), removeCopies(), removePhis(), llvm::LiveVariables::removeVirtualRegistersKilled(), llvm::LiveIntervals::repairIntervalsInRange(), llvm::PPCInstrInfo::replaceInstrWithLI(), rescheduleCanonically(), runOnBasicBlock(), llvm::InstructionSelect::runOnMachineFunction(), llvm::SelectionDAGISel::runOnMachineFunction(), llvm::ThumbRegisterInfo::saveScavengerRegister(), scavengeFrameVirtualRegsInBlock(), llvm::RegScavenger::scavengeRegister(), llvm::AVRDAGToDAGISel::SelectInlineAsmMemoryOperand(), llvm::MachineRegisterInfo::setRegAllocationHint(), llvm::CoalescerPair::setRegisters(), llvm::MachineRegisterInfo::shouldTrackSubRegLiveness(), shrinkScalarLogicOp(), llvm::LiveIntervals::shrinkToUses(), llvm::SIScheduleBlockScheduler::SIScheduleBlockScheduler(), llvm::MachineBasicBlock::SplitCriticalEdge(), llvm::LiveDebugVariables::splitRegister(), llvm::Thumb2InstrInfo::storeRegToStackSlot(), llvm::AArch64InstrInfo::storeRegToStackSlot(), llvm::SIInstrInfo::storeRegToStackSlot(), llvm::MachineOperand::substVirtReg(), swapMIOperands(), tryChangeVGPRtoSGPRinCopy(), tryToElideArgumentCopy(), llvm::LiveIntervals::HMEditor::updateAllRanges(), updateOperand(), updateOperandRegConstraints(), updatePhysDepsDownwards(), llvm::ARMBaseRegisterInfo::updateRegAllocHint(), usedAsAddr(), llvm::SIInstrInfo::usesConstantBus(), llvm::MachineTraceMetrics::Ensemble::verify(), llvm::MachineFunction::verify(), llvm::SIInstrInfo::verifyInstruction(), VisitGlobalVariableForEmission(), and llvm::VirtRegAuxInfo::weightCalcHelper().
◆ legalclasstypes_begin()
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inline |
Loop over all of the value types that can be represented by values in the given register class.
Definition at line 340 of file TargetRegisterInfo.h.
Referenced by GetRegistersForValue(), getRegTy(), llvm::TargetLoweringBase::isLegalRC(), and llvm::X86InstrInfo::unfoldMemoryOperand().
◆ legalclasstypes_end()
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inline |
Definition at line 344 of file TargetRegisterInfo.h.
References getMinimalPhysRegClass(), I, llvm::MVT::Other, and Reg.
Referenced by getRegTy().
◆ lookThruCopyLike()
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virtual |
Returns the original SrcReg unless it is the target of a copy-like operation, in which case we chain backwards through all such operations to the ultimate source register.
If a physical register is encountered, we stop the search.
Definition at line 490 of file TargetRegisterInfo.cpp.
References assert(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineRegisterInfo::getVRegDef(), llvm::MachineInstr::isCopy(), llvm::MachineInstr::isCopyLike(), llvm::MachineInstr::isSubregToReg(), isVirtualRegister(), LLVM_DUMP_METHOD, and MI.
Referenced by isInvariantStore(), and llvm::PPCInstrInfo::replaceInstrWithLI().
◆ markSuperRegs()
Mark a register and all its aliases as reserved in the given set.
Definition at line 59 of file TargetRegisterInfo.cpp.
References llvm::MCRegisterInfo::DiffListIterator::isValid(), and llvm::BitVector::set().
◆ materializeFrameBaseRegister()
|
inlinevirtual |
Insert defining instruction(s) for BaseReg to be a pointer to FrameIdx before insertion point I.
Definition at line 916 of file TargetRegisterInfo.h.
References llvm_unreachable.
Referenced by lookupCandidateBaseReg().
◆ needsFrameBaseReg()
|
inlinevirtual |
Returns true if the instruction's frame index reference would be better served by a base register other than FP or SP.
Used by LocalStackFrameAllocation to determine which frame index references it should create new base registers for.
Definition at line 910 of file TargetRegisterInfo.h.
Referenced by lookupCandidateBaseReg().
◆ needsStackRealignment()
| bool TargetRegisterInfo::needsStackRealignment | ( | const MachineFunction & | MF | ) | const |
True if storage within the function requires the stack pointer to be aligned more than the normal calling convention calls for.
This cannot be overriden by the target, but canRealignStack can be overridden.
Definition at line 441 of file TargetRegisterInfo.cpp.
References canRealignStack(), llvm::dbgs(), F(), llvm::MachineFunction::getFrameInfo(), llvm::TargetSubtargetInfo::getFrameLowering(), llvm::MachineFunction::getFunction(), llvm::MachineFrameInfo::getMaxAlignment(), llvm::Value::getName(), llvm::TargetFrameLowering::getStackAlignment(), llvm::MachineFunction::getSubtarget(), llvm::Function::hasFnAttribute(), LLVM_DEBUG, and llvm::Attribute::StackAlignment.
Referenced by AdjustStackOffset(), AssignProtectedObjSet(), llvm::CodeViewDebug::beginFunctionImpl(), llvm::MachineFrameInfo::estimateStackSize(), getDwarfRegNum(), getMemcpyLoadsAndStores(), llvm::MipsFrameLowering::hasBP(), llvm::MipsFrameLowering::hasFP(), llvm::SparcFrameLowering::hasFP(), llvm::RISCVFrameLowering::hasFP(), llvm::ARMFrameLowering::hasFP(), llvm::ARCFrameLowering::hasFP(), llvm::AArch64FrameLowering::hasFP(), and INITIALIZE_PASS().
◆ regclass_begin()
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inline |
Register class iterators.
Definition at line 684 of file TargetRegisterInfo.h.
◆ regclass_end()
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inline |
Definition at line 685 of file TargetRegisterInfo.h.
◆ regclasses()
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inline |
Definition at line 686 of file TargetRegisterInfo.h.
References llvm::make_range().
Referenced by llvm::RegisterClassInfo::computePSetLimit(), llvm::createRegUsageInfoCollector(), getAllocatableSet(), getMinimalPhysRegClass(), llvm::TargetLowering::getRegForInlineAsmConstraint(), llvm::HexagonBlockRanges::HexagonBlockRanges(), llvm::rdf::PhysicalRegisterInfo::PhysicalRegisterInfo(), llvm::ResourcePriorityQueue::regPressureDelta(), and llvm::ResourcePriorityQueue::ResourcePriorityQueue().
◆ regmaskSubsetEqual()
| bool TargetRegisterInfo::regmaskSubsetEqual | ( | const uint32_t * | mask0, |
| const uint32_t * | mask1 | ||
| ) | const |
Return true if all bits that are set in mask mask0 are also set in mask1.
Definition at line 458 of file TargetRegisterInfo.cpp.
References llvm::MCRegisterInfo::getNumRegs(), I, and N.
◆ regsOverlap()
Returns true if the two registers are equal or alias each other.
The registers may be virtual registers.
Definition at line 423 of file TargetRegisterInfo.h.
References llvm::MCRegisterInfo::DiffListIterator::isValid().
Referenced by llvm::MachineOperandIteratorBase::analyzePhysReg(), AnyAliasLiveIn(), llvm::X86FrameLowering::assignCalleeSavedSpillSlots(), canClobberPhysRegDefs(), canClobberReachingPhysRegUse(), llvm::MachineInstr::clearRegisterKills(), llvm::MachineBasicBlock::computeRegisterLiveness(), llvm::ARMBaseInstrInfo::copyPhysReg(), CriticalPathStep(), llvm::MachineInstr::findRegisterDefOperandIdx(), llvm::MachineInstr::findRegisterUseOperandIdx(), isACalleeSavedRegister(), isNopCopy(), IsSafeAndProfitableToMove(), regOverlapsSet(), regsAreCompatible(), and llvm::MachineInstr::setPhysRegsDeadExcept().
◆ requiresFrameIndexReplacementScavenging()
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inlinevirtual |
Returns true if the target requires using the RegScavenger directly for frame elimination despite using requiresFrameIndexScavenging.
Definition at line 863 of file TargetRegisterInfo.h.
◆ requiresFrameIndexScavenging()
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inlinevirtual |
Returns true if the target requires post PEI scavenging of registers for materializing frame index constants.
Definition at line 857 of file TargetRegisterInfo.h.
◆ requiresRegisterScavenging()
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inlinevirtual |
Returns true if the target requires (and can make use of) the register scavenger.
Definition at line 845 of file TargetRegisterInfo.h.
◆ requiresVirtualBaseRegisters()
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inlinevirtual |
Returns true if the target wants the LocalStackAllocation pass to be run and virtual base registers used for more efficient stack access.
Definition at line 870 of file TargetRegisterInfo.h.
Referenced by INITIALIZE_PASS().
◆ resolveFrameIndex()
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inlinevirtual |
Resolve a frame index operand of an instruction to reference the indicated base register plus offset instead.
Definition at line 925 of file TargetRegisterInfo.h.
References llvm_unreachable.
Referenced by lookupCandidateBaseReg().
◆ reverseComposeSubRegIndexLaneMask()
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inline |
Transform a lanemask given for a virtual register to the corresponding lanemask before using subregister with index IdxA.
This is the reverse of composeSubRegIndexLaneMask(), assuming Mask is a valie lane mask (no invalid bits set) the following holds: X0 = composeSubRegIndexLaneMask(Idx, Mask) X1 = reverseComposeSubRegIndexLaneMask(Idx, X0) => X1 == Mask
Definition at line 618 of file TargetRegisterInfo.h.
References llvm::TargetRegisterClass::LaneMask, and TRI.
Referenced by llvm::rdf::PhysicalRegisterInfo::mapTo().
◆ reverseComposeSubRegIndexLaneMaskImpl()
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inlineprotectedvirtual |
Definition at line 641 of file TargetRegisterInfo.h.
References llvm_unreachable.
◆ reverseLocalAssignment()
|
inlinevirtual |
Allow the target to reverse allocation order of local live ranges.
This will generally allocate shorter local live ranges first. For targets with many registers, this could reduce regalloc compile time by a large factor. It is disabled by default for three reasons: (1) Top-down allocation is simpler and easier to debug for targets that don't benefit from reversing the order. (2) Bottom-up allocation could result in poor evicition decisions on some targets affecting the performance of compiled code. (3) Bottom-up allocation is no longer guaranteed to optimally color.
Definition at line 836 of file TargetRegisterInfo.h.
Referenced by llvm::createGreedyRegisterAllocator().
◆ saveScavengerRegister()
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inlinevirtual |
Spill the register so it can be used by the register scavenger.
Return true if the register was spilled, false otherwise. If this function does not spill the register, the scavenger will instead spill it to the emergency spill slot.
Definition at line 941 of file TargetRegisterInfo.h.
References MI.
◆ shouldCoalesce()
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inlinevirtual |
Subtarget Hooks.
SrcRC and DstRC will be morphed into NewRC if this returns true.
Definition at line 975 of file TargetRegisterInfo.h.
◆ shouldRewriteCopySrc()
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virtual |
Definition at line 382 of file TargetRegisterInfo.cpp.
References shareSameRegisterFile().
◆ stackSlot2Index()
|
inlinestatic |
Compute the frame index from a register value representing a stack slot.
Definition at line 275 of file TargetRegisterInfo.h.
References assert().
Referenced by llvm::rdf::PhysicalRegisterInfo::getMaskUnits(), llvm::rdf::PhysicalRegisterInfo::getRegMaskBits(), false::IntervalSorter::operator()(), and llvm::printReg().
◆ trackLivenessAfterRegAlloc()
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inlinevirtual |
Returns true if the live-ins should be tracked after register allocation.
Definition at line 886 of file TargetRegisterInfo.h.
Referenced by llvm::BranchFolder::OptimizeFunction().
◆ updateRegAllocHint()
|
inlinevirtual |
A callback to allow target a chance to update register allocation hints when a register is "changed" (e.g.
coalesced) to another register. e.g. On ARM, some virtual registers should target register pairs, if one of pair is coalesced to another register, the allocation hint of the other half of the pair should be changed to point to the new register.
Definition at line 822 of file TargetRegisterInfo.h.
◆ useFPForScavengingIndex()
|
inlinevirtual |
Returns true if the target wants to use frame pointer based accesses to spill to the scavenger emergency spill slot.
Definition at line 851 of file TargetRegisterInfo.h.
Referenced by AssignProtectedObjSet().
◆ virtReg2Index()
Convert a virtual register number to a 0-based index.
The first virtual register in a function will get the index 0.
Definition at line 302 of file TargetRegisterInfo.h.
References assert().
Referenced by computeWeight(), findStartOfTree(), llvm::VReg2SUnit::getSparseSetIndex(), llvm::WebAssemblyFunctionInfo::getWAReg(), INITIALIZE_PASS(), isCrossCopy(), isDebug(), llvm::WebAssemblyFunctionInfo::isVRegStackified(), llvm::VirtReg2IndexFunctor::operator()(), llvm::printReg(), llvm::printVRegOrUnit(), llvm::SelectionDAGISel::runOnMachineFunction(), scavengeFrameVirtualRegsInBlock(), llvm::WebAssemblyFunctionInfo::setWAReg(), and llvm::WebAssemblyFunctionInfo::stackifyVReg().
The documentation for this class was generated from the following files:
- include/llvm/CodeGen/TargetRegisterInfo.h
- lib/CodeGen/TargetRegisterInfo.cpp
