24 #define GET_INSTRINFO_CTOR_DTOR 25 #include "BPFGenInstrInfo.inc" 34 const DebugLoc &DL,
unsigned DestReg,
35 unsigned SrcReg,
bool KillSrc)
const {
36 if (BPF::GPRRegClass.
contains(DestReg, SrcReg))
37 BuildMI(MBB, I, DL,
get(BPF::MOV_rr), DestReg)
39 else if (BPF::GPR32RegClass.
contains(DestReg, SrcReg))
40 BuildMI(MBB, I, DL,
get(BPF::MOV_rr_32), DestReg)
47 unsigned DstReg = MI->getOperand(0).getReg();
48 unsigned SrcReg = MI->getOperand(1).getReg();
49 uint64_t CopyLen = MI->getOperand(2).getImm();
50 uint64_t Alignment = MI->getOperand(3).getImm();
51 unsigned ScratchReg = MI->getOperand(4).getReg();
54 unsigned LdOpc, StOpc;
77 unsigned IterationNum = CopyLen >>
Log2_64(Alignment);
78 for(
unsigned I = 0;
I < IterationNum; ++
I) {
79 BuildMI(*BB, MI, dl,
get(LdOpc))
82 BuildMI(*BB, MI, dl,
get(StOpc))
87 unsigned BytesLeft = CopyLen & (Alignment - 1);
88 unsigned Offset = IterationNum * Alignment;
89 bool Hanging4Byte = BytesLeft & 0x4;
90 bool Hanging2Byte = BytesLeft & 0x2;
91 bool Hanging1Byte = BytesLeft & 0x1;
93 BuildMI(*BB, MI, dl,
get(BPF::LDW))
95 BuildMI(*BB, MI, dl,
get(BPF::STW))
100 BuildMI(*BB, MI, dl,
get(BPF::LDH))
102 BuildMI(*BB, MI, dl,
get(BPF::STH))
107 BuildMI(*BB, MI, dl,
get(BPF::LDB))
109 BuildMI(*BB, MI, dl,
get(BPF::STB))
127 unsigned SrcReg,
bool IsKill,
int FI,
132 DL = I->getDebugLoc();
134 if (RC == &BPF::GPRRegClass)
135 BuildMI(MBB, I, DL,
get(BPF::STD))
139 else if (RC == &BPF::GPR32RegClass)
140 BuildMI(MBB, I, DL,
get(BPF::STW32))
150 unsigned DestReg,
int FI,
155 DL = I->getDebugLoc();
157 if (RC == &BPF::GPRRegClass)
159 else if (RC == &BPF::GPR32RegClass)
169 bool AllowModify)
const {
173 while (I != MBB.
begin()) {
175 if (I->isDebugInstr())
180 if (!isUnpredicatedTerminator(*I))
189 if (I->getOpcode() == BPF::JMP) {
191 TBB = I->getOperand(0).getMBB();
196 while (std::next(I) != MBB.
end())
197 std::next(I)->eraseFromParent();
204 I->eraseFromParent();
210 TBB = I->getOperand(0).getMBB();
225 int *BytesAdded)
const {
226 assert(!BytesAdded &&
"code size not handled");
229 assert(TBB &&
"insertBranch must not be told to insert a fallthrough");
233 assert(!FBB &&
"Unconditional branch with multiple successors!");
242 int *BytesRemoved)
const {
243 assert(!BytesRemoved &&
"code size not handled");
248 while (I != MBB.
begin()) {
250 if (I->isDebugInstr())
252 if (I->getOpcode() != BPF::JMP)
255 I->eraseFromParent();
This class represents lattice values for constants.
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
unsigned const TargetRegisterInfo * TRI
return AArch64::GPR64RegClass contains(Reg)
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
unsigned getKillRegState(bool B)
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
const MachineInstrBuilder & addFrameIndex(int Idx) const
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
bool isLayoutSuccessor(const MachineBasicBlock *MBB) const
Return true if the specified MBB will be emitted immediately after this block, such that if this bloc...
bool expandPostRAPseudo(MachineInstr &MI) const override
Representation of each machine instruction.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned char TargetFlags=0) const
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
unsigned Log2_64(uint64_t Value)
Return the floor log base 2 of the specified value, -1 if the value is zero.
bool empty() const
empty - Check if the array is empty.