59 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
87 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
111 "Can't handle non-64 bits locations");
115 unsigned alignment = (LocVT ==
MVT::f128) ? 16 : 8;
119 if (LocVT ==
MVT::i64 && Offset < 6*8)
121 Reg = SP::I0 + Offset/8;
122 else if (LocVT ==
MVT::f64 && Offset < 16*8)
124 Reg = SP::D0 + Offset/8;
125 else if (LocVT ==
MVT::f32 && Offset < 16*8)
127 Reg = SP::F1 + Offset/4;
128 else if (LocVT ==
MVT::f128 && Offset < 16*8)
130 Reg = SP::Q0 + Offset/16;
157 if (LocVT ==
MVT::f32 && Offset < 16*8) {
164 if (LocVT ==
MVT::i32 && Offset < 6*8) {
166 unsigned Reg = SP::I0 + Offset/8;
183 #include "SparcGenCallingConv.inc" 189 static_assert(SP::I0 + 7 == SP::I7 && SP::O0 + 7 == SP::O7,
191 if (Reg >= SP::I0 && Reg <= SP::I7)
192 return Reg - SP::I0 + SP::O0;
203 return LowerReturn_64(Chain, CallConv, IsVarArg, Outs, OutVals, DL, DAG);
204 return LowerReturn_32(Chain, CallConv, IsVarArg, Outs, OutVals, DL, DAG);
231 for (
unsigned i = 0, realRVLocIdx = 0;
233 ++i, ++realRVLocIdx) {
265 unsigned RetAddrOffset = 8;
316 for (
unsigned i = 0; i != RVLocs.
size(); ++i) {
345 if (i+1 < RVLocs.
size() && RVLocs[i+1].getLocReg() == VA.
getLocReg()) {
397 const unsigned StackOffset = 92;
401 for (
unsigned i = 0, e = ArgLocs.size(); i != e; ++i, ++InIdx) {
404 if (Ins[InIdx].Flags.isSRet()) {
435 &SP::IntRegsRegClass);
470 if (Offset % 8 == 0) {
537 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
539 unsigned NumAllocated = CCInfo.getFirstUnallocated(ArgRegs);
540 const MCPhysReg *CurArgReg = ArgRegs+NumAllocated, *ArgRegEnd = ArgRegs+6;
541 unsigned ArgOffset = CCInfo.getNextStackOffset();
542 if (NumAllocated == 6)
543 ArgOffset += StackOffset;
546 ArgOffset = 68+4*NumAllocated;
552 std::vector<SDValue> OutChains;
554 for (; CurArgReg != ArgRegEnd; ++CurArgReg) {
568 if (!OutChains.empty()) {
569 OutChains.push_back(Chain);
591 const unsigned ArgArea = 128;
593 for (
unsigned i = 0, e = ArgLocs.
size(); i != e; ++i) {
642 Offset += 8 - ValSize;
660 unsigned ArgOffset = CCInfo.getNextStackOffset();
670 for (; ArgOffset < 6*8; ArgOffset += 8) {
671 unsigned VReg = MF.
addLiveIn(SP::I0 + ArgOffset/8, &SP::I64RegsRegClass);
680 if (!OutChains.
empty())
703 dyn_cast<ExternalSymbolSDNode>(Callee)) {
706 const char *CalleeName =
E->getSymbol();
740 unsigned ArgsSize = CCInfo.getNextStackOffset();
743 ArgsSize = (ArgsSize+7) & ~7;
749 for (
unsigned i = 0, e = Outs.
size(); i != e; ++i) {
763 Chain = DAG.
getMemcpy(Chain, dl, FIPtr, Arg, SizeNode, Align,
781 const unsigned StackOffset = 92;
782 bool hasStructRetAttr =
false;
783 unsigned SRetArgSize = 0;
785 for (
unsigned i = 0, realArgIdx = 0, byvalArgIdx = 0, e = ArgLocs.
size();
795 Arg = ByValArgs[byvalArgIdx++];
827 hasStructRetAttr =
true;
829 assert(Outs[realArgIdx].OrigArgIndex == 0);
842 if (Offset % 8 == 0) {
925 if (!MemOpChains.
empty())
933 for (
unsigned i = 0, e = RegsToPass.
size(); i != e; ++i) {
955 if (hasStructRetAttr)
957 for (
unsigned i = 0, e = RegsToPass.
size(); i != e; ++i)
959 RegsToPass[i].
second.getValueType()));
967 assert(Mask &&
"Missing call preserved mask for calling convention");
988 for (
unsigned i = 0; i != RVLocs.
size(); ++i) {
992 Chain, dl,
toCallerWindow(RVLocs[i++].getLocReg()), MVT::i32, InFlag);
998 Chain, dl,
toCallerWindow(RVLocs[i].getLocReg()), MVT::i32, InFlag);
1007 RVLocs[i].getValVT(), InFlag)
1022 .Case(
"i0", SP::I0).
Case(
"i1", SP::I1).
Case(
"i2", SP::I2).
Case(
"i3", SP::I3)
1023 .
Case(
"i4", SP::I4).
Case(
"i5", SP::I5).
Case(
"i6", SP::I6).
Case(
"i7", SP::I7)
1024 .
Case(
"o0", SP::O0).
Case(
"o1", SP::O1).
Case(
"o2", SP::O2).
Case(
"o3", SP::O3)
1025 .
Case(
"o4", SP::O4).
Case(
"o5", SP::O5).
Case(
"o6", SP::O6).
Case(
"o7", SP::O7)
1026 .
Case(
"l0", SP::L0).
Case(
"l1", SP::L1).
Case(
"l2", SP::L2).
Case(
"l3", SP::L3)
1027 .
Case(
"l4", SP::L4).
Case(
"l5", SP::L5).
Case(
"l6", SP::L6).
Case(
"l7", SP::L7)
1028 .
Case(
"g0", SP::G0).
Case(
"g1", SP::G1).
Case(
"g2", SP::G2).
Case(
"g3", SP::G3)
1029 .
Case(
"g4", SP::G4).
Case(
"g5", SP::G5).
Case(
"g6", SP::G6).
Case(
"g7", SP::G7)
1048 for (
unsigned i = 0, e = ArgLocs.
size(); i != e; ++i) {
1063 unsigned firstReg = (ValTy ==
MVT::f64) ? SP::D0 : SP::Q0;
1064 unsigned argSize = (ValTy ==
MVT::f64) ? 8 : 16;
1066 assert(Offset < 16*8 &&
"Offset out of range, bad register enum?");
1070 unsigned IReg = SP::I0 + Offset/8;
1113 unsigned ArgsSize =
std::max(6*8u, CCInfo.getNextStackOffset());
1116 ArgsSize =
alignTo(ArgsSize, 16);
1137 for (
unsigned i = 0, e = ArgLocs.
size(); i != e; ++i) {
1200 if (i+1 < ArgLocs.
size() && ArgLocs[i+1].isRegLoc() &&
1201 ArgLocs[i+1].getLocReg() == VA.
getLocReg()) {
1228 if (!MemOpChains.
empty())
1236 for (
unsigned i = 0, e = RegsToPass.
size(); i != e; ++i) {
1238 RegsToPass[i].
first, RegsToPass[i].
second, InGlue);
1257 for (
unsigned i = 0, e = RegsToPass.
size(); i != e; ++i)
1259 RegsToPass[i].second.getValueType()));
1267 assert(Mask &&
"Missing call preserved mask for calling convention");
1296 CLI.
Ins[0].Flags.setInReg();
1298 RVInfo.AnalyzeCallResult(CLI.
Ins, RetCC_Sparc64);
1301 for (
unsigned i = 0; i != RVLocs.
size(); ++i) {
1314 if (!RV.getNode()) {
1315 RV = DAG.
getCopyFromReg(Chain, DL, Reg, RVLocs[i].getLocVT(), InGlue);
1579 if (Subtarget->
isV9())
1610 if (!Subtarget->
isV9()) {
1718 if (Subtarget->
isV9()) {
1858 const APInt &DemandedElts,
1860 unsigned Depth)
const {
1893 SPCC = cast<ConstantSDNode>(LHS.
getOperand(2))->getZExtValue();
1905 GA->getValueType(0),
1906 GA->getOffset(), TF);
1910 CP->getValueType(0),
1912 CP->getOffset(), TF);
1922 ES->getValueType(0), TF);
1930 unsigned HiTF,
unsigned LoTF,
2051 Chain = DAG.
getCopyToReg(Chain, DL, SP::O0, Argument, InFlag);
2059 assert(Mask &&
"Missing call preserved mask for calling convention");
2142 Args.push_back(Entry);
2148 const char *LibFuncName,
2149 unsigned numArgs)
const {
2158 Type *RetTyABI = RetTy;
2167 Entry.
Node = RetPtr;
2172 Args.push_back(Entry);
2177 for (
unsigned i = 0, e = numArgs; i != e; ++i) {
2181 CLI.setDebugLoc(
SDLoc(Op)).setChain(Chain)
2187 if (RetTyABI == RetTy)
2188 return CallInfo.first;
2192 Chain = CallInfo.second;
2200 unsigned &SPCC,
const SDLoc &DL,
2203 const char *
LibCall =
nullptr;
2207 case SPCC::FCC_E : LibCall = is64Bit?
"_Qp_feq" :
"_Q_feq";
break;
2208 case SPCC::FCC_NE : LibCall = is64Bit?
"_Qp_fne" :
"_Q_fne";
break;
2209 case SPCC::FCC_L : LibCall = is64Bit?
"_Qp_flt" :
"_Q_flt";
break;
2210 case SPCC::FCC_G : LibCall = is64Bit?
"_Qp_fgt" :
"_Q_fgt";
break;
2211 case SPCC::FCC_LE : LibCall = is64Bit?
"_Qp_fle" :
"_Q_fle";
break;
2212 case SPCC::FCC_GE : LibCall = is64Bit?
"_Qp_fge" :
"_Q_fge";
break;
2220 case SPCC::FCC_UE : LibCall = is64Bit?
"_Qp_cmp" :
"_Q_cmp";
break;
2238 SDValue Result = CallInfo.first;
2341 ? RTLIB::FPTOSINT_F128_I32
2342 : RTLIB::FPTOSINT_F128_I64);
2372 ? RTLIB::SINTTOFP_I32_F128
2373 : RTLIB::SINTTOFP_I64_F128);
2403 ? RTLIB::FPTOUINT_F128_I32
2404 : RTLIB::FPTOUINT_F128_I64),
2422 ? RTLIB::UINTTOFP_I32_F128
2423 : RTLIB::UINTTOFP_I64_F128),
2436 unsigned Opc, SPCC = ~0U;
2473 unsigned Opc, SPCC = ~0U;
2526 const Value *SV = cast<SrcValueSDNode>(Node->
getOperand(2))->getValue();
2547 unsigned Align = cast<ConstantSDNode>(Op.
getOperand(2))->getZExtValue();
2555 if (Align > StackAlign) {
2558 "over-aligned dynamic alloca not supported.");
2563 unsigned regSpillArea;
2593 unsigned SPReg = SP::O6;
2602 SDValue Ops[2] = { NewVal, Chain };
2616 bool AlwaysFlush =
false) {
2622 unsigned FrameReg = SP::I6;
2633 unsigned Offset = (Subtarget->
is64Bit()) ? (stackBias + 112) : 56;
2730 &&
"Unexpected node type");
2784 &&
"Unexpected node type");
2840 &&
"invalid opcode");
2855 SDValue Hi64 = DAG.getTargetExtractSubreg(SP::sub_even64, dl,
MVT::f64,
2857 SDValue Lo64 = DAG.getTargetExtractSubreg(SP::sub_odd64, dl,
MVT::f64,
2860 if (DAG.getDataLayout().isLittleEndian()) {
2872 SDValue DstReg128 =
SDValue(DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF,
2874 DstReg128 = DAG.getTargetInsertSubreg(SP::sub_even64, dl,
MVT::f128,
2876 DstReg128 = DAG.getTargetInsertSubreg(SP::sub_odd64, dl,
MVT::f128,
2900 bool hasChain =
false;
2926 SDValue Ops[2] = { Dst, Carry };
2955 RTLIB::MUL_I128, WideVT,
2956 Args, isSigned, dl).first;
2972 assert(MulResult->
use_empty() &&
"Illegally typed node still in use!");
2974 SDValue Ops[2] = { BottomHalf, TopHalf } ;
2989 unsigned IntNo = cast<ConstantSDNode>(Op.
getOperand(0))->getZExtValue();
3004 bool isV9 = Subtarget->
isV9();
3101 case SP::SELECT_CC_Int_ICC:
3102 case SP::SELECT_CC_FP_ICC:
3103 case SP::SELECT_CC_DFP_ICC:
3104 case SP::SELECT_CC_QFP_ICC:
3106 case SP::SELECT_CC_Int_FCC:
3107 case SP::SELECT_CC_FP_FCC:
3108 case SP::SELECT_CC_DFP_FCC:
3109 case SP::SELECT_CC_QFP_FCC:
3116 unsigned BROpcode)
const {
3139 F->
insert(It, IfFalseMBB);
3164 .addMBB(IfFalseMBB);
3178 if (Constraint.
size() == 1) {
3179 switch (Constraint[0]) {
3195 const char *constraint)
const {
3200 if (!CallOperandVal)
3204 switch (*constraint) {
3210 if (isInt<13>(
C->getSExtValue()))
3222 std::string &Constraint,
3223 std::vector<SDValue> &Ops,
3228 if (Constraint.length() > 1)
3231 char ConstraintLetter = Constraint[0];
3232 switch (ConstraintLetter) {
3236 if (isInt<13>(
C->getSExtValue())) {
3246 Ops.push_back(Result);
3252 std::pair<unsigned, const TargetRegisterClass *>
3256 if (Constraint.
size() == 1) {
3257 switch (Constraint[0]) {
3260 return std::make_pair(0U, &SP::IntPairRegClass);
3262 return std::make_pair(0U, &SP::IntRegsRegClass);
3265 return std::make_pair(0U, &SP::FPRegsRegClass);
3267 return std::make_pair(0U, &SP::LowDFPRegsRegClass);
3269 return std::make_pair(0U, &SP::LowQFPRegsRegClass);
3271 return std::make_pair(0U,
nullptr);
3274 return std::make_pair(0U, &SP::FPRegsRegClass);
3276 return std::make_pair(0U, &SP::DFPRegsRegClass);
3278 return std::make_pair(0U, &SP::QFPRegsRegClass);
3280 return std::make_pair(0U,
nullptr);
3282 }
else if (!Constraint.
empty() && Constraint.
size() <= 5
3283 && Constraint[0] ==
'{' && *(Constraint.
end()-1) ==
'}') {
3292 uint64_t intVal = 0;
3293 if (
name.substr(0, 1).equals(
"r")
3294 && !
name.substr(1).getAsInteger(10, intVal) && intVal <= 31) {
3295 const char regTypes[] = {
'g',
'o',
'l',
'i' };
3296 char regType = regTypes[intVal/8];
3297 char regIdx =
'0' + (intVal % 8);
3298 char tmp[] = {
'{', regType, regIdx,
'}', 0 };
3299 std::string newConstraint = std::string(tmp);
3303 if (
name.substr(0, 1).equals(
"f") &&
3304 !
name.substr(1).getAsInteger(10, intVal) && intVal <= 63) {
3305 std::string newConstraint;
3308 newConstraint =
"{f" +
utostr(intVal) +
"}";
3309 }
else if (VT ==
MVT::f64 && (intVal % 2 == 0)) {
3310 newConstraint =
"{d" +
utostr(intVal / 2) +
"}";
3311 }
else if (VT ==
MVT::f128 && (intVal % 4 == 0)) {
3312 newConstraint =
"{q" +
utostr(intVal / 4) +
"}";
3314 return std::make_pair(0U,
nullptr);
3340 llvm_unreachable(
"Do not know how to custom type legalize this operation!");
3349 ? RTLIB::FPTOSINT_F128_I64
3350 : RTLIB::FPTOUINT_F128_I64);
3375 ? RTLIB::SINTTOFP_I64_F128
3376 : RTLIB::UINTTOFP_I64_F128);
SDValue getStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, unsigned Alignment=0, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
Helper function to build ISD::STORE nodes.
void setFrameAddressIsTaken(bool T)
static SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, bool hasHardQuad)
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
X = FP_ROUND(Y, TRUNC) - Rounding 'Y' from a larger floating point type down to the precision of the ...
static MVT getIntegerVT(unsigned BitWidth)
void AnalyzeCallResult(const SmallVectorImpl< ISD::InputArg > &Ins, CCAssignFn Fn)
AnalyzeCallResult - Analyze the return values of a call, incorporating info about the passed values i...
BUILTIN_OP_END - This must be the last enum value in this list.
A parsed version of the target data layout string in and methods for querying it. ...
constexpr char Align[]
Key for Kernel::Arg::Metadata::mAlign.
virtual MVT getVectorIdxTy(const DataLayout &DL) const
Returns the type to be used for the index operand of: ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT...
EVT getValueType() const
Return the ValueType of the referenced return value.
void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified load with extension does not work with the specified type and indicate wh...
const SDValue & getOffset() const
C - The default llvm calling convention, compatible with C.
static CCValAssign getCustomReg(unsigned ValNo, MVT ValVT, unsigned RegNo, MVT LocVT, LocInfo HTP)
const GlobalValue * getGlobal() const
EXTRACT_ELEMENT - This is used to get the lower or upper (determined by a Constant, which is required to be operand #1) half of the integer or float value specified as operand #0.
GCNRegPressure max(const GCNRegPressure &P1, const GCNRegPressure &P2)
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
This class represents an incoming formal argument to a Function.
DiagnosticInfoOptimizationBase::Argument NV
SDValue getSetCC(const SDLoc &DL, EVT VT, SDValue LHS, SDValue RHS, ISD::CondCode Cond)
Helper function to make it easier to build SetCC's if you just have an ISD::CondCode instead of an SD...
bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override
Return true if folding a constant offset with the given GlobalAddress is legal.
SDValue getCALLSEQ_END(SDValue Chain, SDValue Op1, SDValue Op2, SDValue InGlue, const SDLoc &DL)
Return a new CALLSEQ_END node, which always must have a glue result (to ensure it's not CSE'd)...
static SPCC::CondCodes IntCondCCodeToICC(ISD::CondCode CC)
IntCondCCodeToICC - Convert a DAG integer condition code to a SPARC ICC condition.
BR_CC - Conditional branch.
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
This class represents lattice values for constants.
static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI)
static SDValue LowerATOMIC_LOAD_STORE(SDValue Op, SelectionDAG &DAG)
A Module instance is used to store all the information related to an LLVM module. ...
SDValue LowerCall_64(TargetLowering::CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals) const
void addLiveIn(unsigned Reg, unsigned vreg=0)
addLiveIn - Add the specified register as a live-in.
const SDValue & getBasePtr() const
Carry-setting nodes for multiple precision addition and subtraction.
EVT getValueType(unsigned ResNo) const
Return the type of a specified result.
void push_back(const T &Elt)
virtual void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const
Lower the specified operand into the Ops vector.
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
unsigned addLiveIn(unsigned PReg, const TargetRegisterClass *RC)
addLiveIn - Add the specified physical register as a live-in value and create a corresponding virtual...
void AnalyzeFormalArguments(const SmallVectorImpl< ISD::InputArg > &Ins, CCAssignFn Fn)
AnalyzeFormalArguments - Analyze an array of argument values, incorporating info about the formals in...
unsigned getReg() const
getReg - Returns the register number.
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE size_t size() const
size - Get the string size.
bool isFP128Ty() const
Return true if this is 'fp128'.
const SDValue & getValue() const
void transferSuccessorsAndUpdatePHIs(MachineBasicBlock *FromMBB)
Transfers all the successors, as in transferSuccessors, and update PHI operands in the successor bloc...
STACKRESTORE has two operands, an input chain and a pointer to restore to it returns an output chain...
Libcall
RTLIB::Libcall enum - This enum defines all of the runtime library calls the backend can emit...
AAMDNodes getAAInfo() const
Returns the AA info that describes the dereference.
const SDValue & getChain() const
Function Alias Analysis Results
unsigned getValNo() const
unsigned getAlignment() const
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
virtual std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const
Given a physical register constraint (e.g.
static bool CC_Sparc64_Full(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State)
void setBooleanVectorContents(BooleanContent Ty)
Specify how the target extends the result of a vector boolean value from a vector of i1 to a wider ty...
const uint32_t * getRTCallPreservedMask(CallingConv::ID CC) const
virtual const TargetRegisterClass * getRegClassFor(MVT VT) const
Return the register class that should be used for the specified value type.
unsigned const TargetRegisterInfo * TRI
MVT getSimpleValueType(unsigned ResNo) const
Return the type of a specified result as a simple type.
bool isInteger() const
Return true if this is an integer or a vector integer type.
CallLoweringInfo & setDebugLoc(const SDLoc &dl)
uint64_t alignTo(uint64_t Value, uint64_t Align, uint64_t Skew=0)
Returns the next integer (mod 2**64) that is greater than or equal to Value and is a multiple of Alig...
APInt zextOrTrunc(unsigned width) const
Zero extend or truncate to width.
an instruction that atomically reads a memory location, combines it with another value, and then stores the result back.
SDNode * getNode() const
get the SDNode which holds the desired result
SDValue getTargetExternalSymbol(const char *Sym, EVT VT, unsigned char TargetFlags=0)
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
AtomicExpansionKind
Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.
Value * CallOperandVal
If this is the result output operand or a clobber, this is null, otherwise it is the incoming operand...
const SparcInstrInfo * getInstrInfo() const override
MachineMemOperand * getMemOperand() const
Return a MachineMemOperand object describing the memory reference performed by operation.
virtual SDValue LowerToTLSEmulatedModel(const GlobalAddressSDNode *GA, SelectionDAG &DAG) const
Lower TLS global address SDNode for target independent emulated TLS model.
OUTCHAIN = ATOMIC_FENCE(INCHAIN, ordering, scope) This corresponds to the fence instruction.
SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const
int CreateStackObject(uint64_t Size, unsigned Alignment, bool isSpillSlot, const AllocaInst *Alloca=nullptr, uint8_t ID=0)
Create a new statically sized stack object, returning a nonnegative identifier to represent it...
Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE const char * data() const
data - Get a pointer to the start of the string (which may not be null terminated).
AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override
Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all...
bool useSoftFloat() const override
SDValue getExternalSymbol(const char *Sym, EVT VT)
void setTruncStoreAction(MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified truncating store does not work with the specified type and indicate what ...
ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &info, const char *constraint) const override
Examine constraint string and operand type and determine a weight value.
static SDValue getFRAMEADDR(uint64_t depth, SDValue Op, SelectionDAG &DAG, const SparcSubtarget *Subtarget, bool AlwaysFlush=false)
static bool CC_Sparc_Assign_SRet(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State)
bool hasStructRetAttr() const
Determine if the function returns a structure through first or second pointer argument.
SDIVREM/UDIVREM - Divide two integers and produce both a quotient and remainder result.
SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded integer shift operations...
SDValue getIntPtrConstant(uint64_t Val, const SDLoc &DL, bool isTarget=false)
bool isTargetLinux() const
static SDValue LowerF128_FPROUND(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI)
SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const
static SDValue LowerFNEGorFABS(SDValue Op, SelectionDAG &DAG, bool isV9)
void setMaxAtomicSizeInBitsSupported(unsigned SizeInBits)
Set the maximum atomic operation size supported by the backend.
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
static SDValue LowerF128_FPEXTEND(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI)
const HexagonInstrInfo * TII
static void fixupVariableFloatArgs(SmallVectorImpl< CCValAssign > &ArgLocs, ArrayRef< ISD::OutputArg > Outs)
Shift and rotation operations.
MachineBasicBlock * expandSelectCC(MachineInstr &MI, MachineBasicBlock *BB, unsigned BROpcode) const
Type * getTypeForEVT(LLVMContext &Context) const
This method returns an LLVM type corresponding to the specified EVT.
SDValue getTargetExtractSubreg(int SRIdx, const SDLoc &DL, EVT VT, SDValue Operand)
A convenience function for creating TargetInstrInfo::EXTRACT_SUBREG nodes.
MachineSDNode * getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT)
These are used for target selectors to create a new node with specified return type(s), MachineInstr opcode, and operands.
BinOp getOperation() const
CallLoweringInfo & setChain(SDValue InChain)
BUILD_PAIR - This is the opposite of EXTRACT_ELEMENT in some ways.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
void addLoc(const CCValAssign &V)
uint64_t getConstantOperandVal(unsigned i) const
ISD::LoadExtType getExtensionType() const
Return whether this is a plain node, or one of the varieties of value-extending loads.
virtual bool useLoadStackGuardNode() const
If this function returns true, SelectionDAGBuilder emits a LOAD_STACK_GUARD node when it is lowering ...
static SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, const SparcSubtarget *Subtarget)
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
Val, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amt) Val, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN, ptr, amt) For double-word atomic operations: ValLo, ValHi, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amtLo, amtHi) ValLo, ValHi, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN, ptr, amtLo, amtHi) These correspond to the atomicrmw instruction.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
SDValue getEntryNode() const
Return the token chain corresponding to the entry of the function.
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
Indicate that the specified operation does not work with the specified type and indicate what to do a...
const DataLayout & getDataLayout() const
SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
FRAMEADDR, RETURNADDR - These nodes represent llvm.frameaddress and llvm.returnaddress on the DAG...
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE R Default(T Value)
LocInfo getLocInfo() const
bool useSoftFloat() const
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
bool hasLeonCycleCounter() const
This represents a list of ValueType's that has been intern'd by a SelectionDAG.
SDValue getExtLoad(ISD::LoadExtType ExtType, const SDLoc &dl, EVT VT, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, EVT MemVT, unsigned Alignment=0, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
SmallVector< ISD::InputArg, 32 > Ins
STACKSAVE - STACKSAVE has one operand, an input chain.
SDValue getMergeValues(ArrayRef< SDValue > Ops, const SDLoc &dl)
Create a MERGE_VALUES node from the given operands.
unsigned getSizeInBits() const
static void LookThroughSetCC(SDValue &LHS, SDValue &RHS, ISD::CondCode CC, unsigned &SPCC)
static bool CC_Sparc_Assign_Split_64(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State)
bool fixAllFDIVSQRT() const
unsigned getSizeInBits() const
Return the size of the specified value type in bits.
Type * getType() const
All values are typed, get the type of this value.
MachineFunction & getMachineFunction() const
void computeRegisterProperties(const TargetRegisterInfo *TRI)
Once all of the register classes are added, this allows us to compute derived properties we expose...
[SU]INT_TO_FP - These operators convert integers (whose interpreted sign depends on the first letter)...
SDValue getRegisterMask(const uint32_t *RegMask)
static SDValue LowerUMULO_SMULO(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI)
const TargetMachine & getTarget() const
SDValue LowerReturn_32(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SDLoc &DL, SelectionDAG &DAG) const
void setSRetReturnReg(unsigned Reg)
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID CC) const override
This contains information for each constraint that we are lowering.
Simple integer binary arithmetic operators.
SDValue LowerF128Op(SDValue Op, SelectionDAG &DAG, const char *LibFuncName, unsigned numArgs) const
bool useSoftMulDiv() const
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE bool empty() const
empty - Check if the string is empty.
int64_t getStackPointerBias() const
The 64-bit ABI uses biased stack and frame pointers, so the stack frame of the current function is th...
SmallVector< ISD::OutputArg, 32 > Outs
SDValue LowerFormalArguments_32(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const
LowerFormalArguments32 - V8 uses a very simple ABI, where all values are passed in either one or two ...
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
bool isLittleEndian() const
Layout endianness...
SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower calls into the specified DAG.
TLSModel::Model getTLSModel(const GlobalValue *GV) const
Returns the TLS model which should be used for the given global variable.
static mvt_range integer_vector_valuetypes()
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out...
READCYCLECOUNTER - This corresponds to the readcyclecounter intrinsic.
SDValue getTargetConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isOpaque=false)
void setMinCmpXchgSizeInBits(unsigned SizeInBits)
Sets the minimum cmpxchg or ll/sc size supported by the backend.
bool useLoadStackGuardNode() const override
Override to support customized stack guard loading.
bool isStrongerThanMonotonic(AtomicOrdering ao)
RESULT = INTRINSIC_WO_CHAIN(INTRINSICID, arg1, arg2, ...) This node represents a target intrinsic fun...
amdgpu Simplify well known AMD library false Value * Callee
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *bb=nullptr)
CreateMachineBasicBlock - Allocate a new MachineBasicBlock.
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
Class to represent pointers.
unsigned getByValSize() const
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
UNDEF - An undefined node.
This class is used to represent ISD::STORE nodes.
FP_TO_[US]INT - Convert a floating point value to a signed or unsigned integer.
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
static CCValAssign getReg(unsigned ValNo, MVT ValVT, unsigned RegNo, MVT LocVT, LocInfo HTP)
Flag
These should be considered private to the implementation of the MCInstrDesc class.
BUILD_VECTOR(ELT0, ELT1, ELT2, ELT3,...) - Return a vector with the specified, possibly variable...
TargetInstrInfo - Interface to description of machine instruction set.
bool isOneConstant(SDValue V)
Returns true if V is a constant integer one.
MVT getSimpleValueType() const
Return the simple ValueType of the referenced return value.
bool useEmulatedTLS() const
Returns true if this target uses emulated TLS.
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
int getVarArgsFrameOffset() const
const SDValue & getBasePtr() const
static SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG)
A switch()-like statement whose cases are string literals.
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
static bool CC_Sparc64_Half(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State)
LLVM Basic Block Representation.
The instances of the Type class are immutable: once they are created, they are never changed...
This is an important class for using LLVM in a threaded context.
void addRegisterClass(MVT VT, const TargetRegisterClass *RC)
Add the specified register class as an available regclass for the specified value type...
virtual ConstraintType getConstraintType(StringRef Constraint) const
Given a constraint, return the type of constraint it is for this target.
Simple binary floating point operators.
void setTargetDAGCombine(ISD::NodeType NT)
Targets should invoke this method for each target independent node that they want to provide a custom...
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
SDValue makeAddress(SDValue Op, SelectionDAG &DAG) const
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
void resetAll()
Resets the known state of all bits.
VAEND, VASTART - VAEND and VASTART have three operands: an input chain, pointer, and a SRCVALUE...
const SDValue & getOperand(unsigned Num) const
static bool is64Bit(const char *name)
void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const override
LowerAsmOperandForConstraint - Lower the specified operand into the Ops vector.
INSERT_VECTOR_ELT(VECTOR, VAL, IDX) - Returns VECTOR with the element at IDX replaced with VAL...
bool hasFnAttr(Attribute::AttrKind Kind) const
Return true if this function has the given attribute.
SDValue LowerFormalArguments_64(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const
Carry-using nodes for multiple precision addition and subtraction.
SDValue getCALLSEQ_START(SDValue Chain, uint64_t InSize, uint64_t OutSize, const SDLoc &DL)
Return a new CALLSEQ_START node, that starts new call frame, in which InSize bytes are set up inside ...
void setBooleanContents(BooleanContent Ty)
Specify how the target extends the result of integer and floating point boolean values from i1 to a w...
SDValue withTargetFlags(SDValue Op, unsigned TF, SelectionDAG &DAG) const
const SDValue & getOffset() const
static mvt_range fp_valuetypes()
static SDValue LowerF128Store(SDValue Op, SelectionDAG &DAG)
static Type * getVoidTy(LLVMContext &C)
SDValue LowerReturn_64(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SDLoc &DL, SelectionDAG &DAG) const
virtual ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &info, const char *constraint) const
Examine constraint string and operand type and determine a weight value.
SDValue PerformBITCASTCombine(SDNode *N, DAGCombinerInfo &DCI) const
static SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG, const SparcSubtarget *Subtarget)
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
TRAP - Trapping instruction.
AssertSext, AssertZext - These nodes record if a register contains a value that has already been zero...
DEBUGTRAP - Trap intended to get the attention of a debugger.
static SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, bool hasHardQuad)
self_iterator getIterator()
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
This callback is invoked when a node result type is illegal for the target, and the operation was reg...
VAARG - VAARG has four operands: an input chain, a pointer, a SRCVALUE, and the alignment.
static SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG, const SparcSubtarget *Subtarget)
Val, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmp, swap) For double-word atomic operations: ValLo...
X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.
std::vector< ArgListEntry > ArgListTy
void setVarArgsFrameOffset(int Offset)
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
bool isPositionIndependent() const
This structure contains all information that is necessary for lowering calls.
const TargetMachine & getTargetMachine() const
This class contains a discriminated union of information about pointers in memory operands...
unsigned getNumOperands() const
Return the number of values used by this operation.
unsigned getStackAlignment() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower the incoming (formal) arguments, described by the Ins array...
SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const
APInt lshr(unsigned shiftAmt) const
Logical right-shift function.
SDValue getLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, unsigned Alignment=0, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
Loads are not normal binary operators: their result type is not determined by their operands...
const SparcRegisterInfo * getRegisterInfo() const override
unsigned getPointerSize(unsigned AS) const
Get the pointer size for this target.
const TargetFrameLowering * getFrameLowering() const override
bool use_empty() const
Return true if there are no uses of this node.
SDValue getTargetConstantPool(const Constant *C, EVT VT, unsigned Align=0, int Offset=0, unsigned char TargetFlags=0)
TokenFactor - This node takes multiple tokens as input and produces a single token result...
ConstraintType getConstraintType(StringRef Constraint) const override
getConstraintType - Given a constraint letter, return the type of constraint it is for this target...
Iterator for intrusive lists based on ilist_node.
CCState - This class holds information needed while lowering arguments and return values...
void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
static PointerType * getUnqual(Type *ElementType)
This constructs a pointer to an object of the specified type in the generic address space (address sp...
This is the shared class of boolean and integer constants.
auto size(R &&Range, typename std::enable_if< std::is_same< typename std::iterator_traits< decltype(Range.begin())>::iterator_category, std::random_access_iterator_tag >::value, void >::type *=nullptr) -> decltype(std::distance(Range.begin(), Range.end()))
Get the size of a range.
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override
getSetCCResultType - Return the ISD::SETCC ValueType
EXTRACT_VECTOR_ELT(VECTOR, IDX) - Returns a single element from VECTOR identified by the (potentially...
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
CallLoweringInfo & setCallee(CallingConv::ID CC, Type *ResultType, SDValue Target, ArgListTy &&ArgsList)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
Module.h This file contains the declarations for the Module class.
SDValue getBuildVector(EVT VT, const SDLoc &DL, ArrayRef< SDValue > Ops)
Return an ISD::BUILD_VECTOR node.
CCValAssign - Represent assignment of one arg/retval to a location.
SDValue getMemcpy(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, bool isVol, bool AlwaysInline, bool isTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo)
EVT changeVectorElementTypeToInteger() const
Return a vector with the same number of elements as this vector, but with the element type converted ...
BRCOND - Conditional branch.
void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth=0) const override
computeKnownBitsForTargetNode - Determine which of the bits specified in Mask are known to be either ...
Byte Swap and Counting operators.
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool IsImmutable, bool isAliased=false)
Create a new object at a fixed location on the stack.
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
std::string utostr(uint64_t X, bool isNeg=false)
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
SDValue getCopyToReg(SDValue Chain, const SDLoc &dl, unsigned Reg, SDValue N)
static SDValue getFLUSHW(SDValue Op, SelectionDAG &DAG)
const Function & getFunction() const
Return the LLVM function that this machine code represents.
static mvt_range integer_valuetypes()
Function * getFunction(StringRef Name) const
Look up the specified function in the module symbol table.
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
EVT getMemoryVT() const
Return the type of the in-memory value.
bool isTypeLegal(EVT VT) const
Return true if the target has native support for the specified value type.
Class for arbitrary precision integers.
unsigned getByValAlign() const
CodeModel::Model getCodeModel() const
Returns the code model.
SparcTargetLowering(const TargetMachine &TM, const SparcSubtarget &STI)
static SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG)
Select(COND, TRUEVAL, FALSEVAL).
void setMinFunctionAlignment(unsigned Align)
Set the target's minimum function alignment (in log2(bytes))
static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, bool hasHardQuad)
ZERO_EXTEND - Used for integer types, zeroing the new bits.
static SPCC::CondCodes FPCondCCodeToFCC(ISD::CondCode CC)
FPCondCCodeToFCC - Convert a DAG floatingp oint condition code to a SPARC FCC condition.
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
void AnalyzeCallOperands(const SmallVectorImpl< ISD::OutputArg > &Outs, CCAssignFn Fn)
AnalyzeCallOperands - Analyze the outgoing arguments to a call, incorporating info about the passed v...
ANY_EXTEND - Used for integer types. The high bits are undefined.
SDValue LowerF128_LibCallArg(SDValue Chain, ArgListTy &Args, SDValue Arg, const SDLoc &DL, SelectionDAG &DAG) const
LLVM_ATTRIBUTE_ALWAYS_INLINE StringSwitch & Case(StringLiteral S, T Value)
FCOPYSIGN(X, Y) - Return the value of X with the sign of Y.
SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SDLoc &dl, SelectionDAG &DAG) const override
This hook must be implemented to lower outgoing return values, described by the Outs array...
unsigned getSRetReturnReg() const
amdgpu Simplify well known AMD library false Value Value * Arg
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
std::pair< SDValue, SDValue > LowerCallTo(CallLoweringInfo &CLI) const
This function lowers an abstract call to a function into an actual call.
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
static SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, bool hasHardQuad)
uint64_t getTypeAllocSize(Type *Ty) const
Returns the offset in bytes between successive objects of the specified type, including alignment pad...
BR_JT - Jumptable branch.
SDValue LowerF128Compare(SDValue LHS, SDValue RHS, unsigned &SPCC, const SDLoc &DL, SelectionDAG &DAG) const
Representation of each machine instruction.
VACOPY - VACOPY has 5 operands: an input chain, a destination pointer, a source pointer, a SRCVALUE for the destination, and a SRCVALUE for the source.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
SDValue getTargetBlockAddress(const BlockAddress *BA, EVT VT, int64_t Offset=0, unsigned char TargetFlags=0)
SmallVector< SDValue, 32 > OutVals
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
bool isVector() const
Return true if this is a vector value type.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Bitwise operators - logical and, logical or, logical xor.
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
SDValue getCopyFromReg(SDValue Chain, const SDLoc &dl, unsigned Reg, EVT VT)
std::pair< SDValue, SDValue > makeLibCall(SelectionDAG &DAG, RTLIB::Libcall LC, EVT RetVT, ArrayRef< SDValue > Ops, bool isSigned, const SDLoc &dl, bool doesNotReturn=false, bool isReturnValueUsed=true) const
Returns a pair of (return value, chain).
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
static IntegerType * getInt32Ty(LLVMContext &C)
unsigned getLocMemOffset() const
SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing a signed/unsigned value of type i[2...
LLVM_NODISCARD bool empty() const
SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to sign extend a small value in ...
static CCValAssign getCustomMem(unsigned ValNo, MVT ValVT, unsigned Offset, MVT LocVT, LocInfo HTP)
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
LOAD and STORE have token chains as their first operand, then the same operands as an LLVM load/store...
Establish a view to a call site for examination.
void AnalyzeReturn(const SmallVectorImpl< ISD::OutputArg > &Outs, CCAssignFn Fn)
AnalyzeReturn - Analyze the returned values of a return, incorporating info about the result values i...
Flags getFlags() const
Return the raw flags of the source value,.
void setStackPointerRegisterToSaveRestore(unsigned R)
If set to a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save and restore.
SDValue bitcastConstantFPToInt(ConstantFPSDNode *C, const SDLoc &DL, SelectionDAG &DAG) const
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
void setLibcallName(RTLIB::Libcall Call, const char *Name)
Rename the default libcall routine name for the specified libcall.
LLVM_NODISCARD std::enable_if<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
static SDValue LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, bool hasHardQuad)
static CCValAssign getMem(unsigned ValNo, MVT ValVT, unsigned Offset, MVT LocVT, LocInfo HTP)
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
unsigned getOpcode() const
FSINCOS - Compute both fsin and fcos as a single operation.
SDValue getValue(unsigned R) const
CopyFromReg - This node indicates that the input value is a virtual or physical register that is defi...
const SDValue & getRoot() const
Return the root tag of the SelectionDAG.
SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
Create a ConstantSDNode wrapping a constant value.
const MachinePointerInfo & getPointerInfo() const
static bool hasReturnsTwiceAttr(SelectionDAG &DAG, SDValue Callee, ImmutableCallSite CS)
void insertSSPDeclarations(Module &M) const override
Inserts necessary declarations for SSP (stack protection) purpose.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
void insert(iterator MBBI, MachineBasicBlock *MBB)
SDValue getFrameIndex(int FI, EVT VT, bool isTarget=false)
void setReturnAddressIsTaken(bool s)
static MachinePointerInfo getGOT(MachineFunction &MF)
Return a MachinePointerInfo record that refers to a GOT entry.
unsigned getPrimitiveSizeInBits() const LLVM_READONLY
Return the basic size of this type if it is a primitive type.
Module * getParent()
Get the module that this global value is contained inside of...
LLVM Value Representation.
FMA - Perform a * b + c with no intermediate rounding step.
SDValue getRegister(unsigned Reg, EVT VT)
static bool CC_Sparc_Assign_Ret_Split_64(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State)
SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const
virtual void insertSSPDeclarations(Module &M) const
Inserts necessary declarations for SSP (stack protection) purpose.
bool isNullConstant(SDValue V)
Returns true if V is a constant integer zero.
static SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG)
SDValue getValueType(EVT)
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
static SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, bool hasHardQuad)
Primary interface to the complete machine description for the target machine.
PICLevel::Level getPICLevel() const
Returns the PIC level (small or large model)
const APFloat & getValueAPF() const
StringRef - Represent a constant reference to a string, i.e.
SetCC operator - This evaluates to a true value iff the condition is true.
APInt bitcastToAPInt() const
KnownBits computeKnownBits(SDValue Op, unsigned Depth=0) const
Determine which bits of Op are known to be either zero or one and return them in Known.
const SDValue & getOperand(unsigned i) const
bool verifyReturnAddressArgumentIsConstant(SDValue Op, SelectionDAG &DAG) const
OUTCHAIN = ATOMIC_STORE(INCHAIN, ptr, val) This corresponds to "store atomic" instruction.
unsigned getLocReg() const
static SDValue LowerF64Op(SDValue SrcReg64, const SDLoc &dl, SelectionDAG &DAG, unsigned opcode)
SDValue getTargetInsertSubreg(int SRIdx, const SDLoc &DL, EVT VT, SDValue Operand, SDValue Subreg)
A convenience function for creating TargetInstrInfo::INSERT_SUBREG nodes.
TRUNCATE - Completely drop the high bits.
SDValue LowerCall_32(TargetLowering::CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals) const
unsigned AllocateReg(unsigned Reg)
AllocateReg - Attempt to allocate one register.
const MachineOperand & getOperand(unsigned i) const
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
Perform various unary floating-point operations inspired by libm.
unsigned AllocateStack(unsigned Size, unsigned Align)
AllocateStack - Allocate a chunk of stack space with the specified size and alignment.
Val, OUTCHAIN = ATOMIC_LOAD(INCHAIN, ptr) This corresponds to "load atomic" instruction.
static unsigned toCallerWindow(unsigned Reg)
LLVMContext * getContext() const
constexpr char Args[]
Key for Kernel::Metadata::mArgs.
SDValue makeHiLoPair(SDValue Op, unsigned HiTF, unsigned LoTF, SelectionDAG &DAG) const
Type * getElementType() const
static SDValue LowerF128Load(SDValue Op, SelectionDAG &DAG)
unsigned createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
unsigned getRegisterByName(const char *RegName, EVT VT, SelectionDAG &DAG) const override
Return the register ID of the name passed in.
const char * getLibcallName(RTLIB::Libcall Call) const
Get the libcall routine name for the specified libcall.
SDValue getTargetGlobalAddress(const GlobalValue *GV, const SDLoc &DL, EVT VT, int64_t offset=0, unsigned char TargetFlags=0)
static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG)
MULHU/MULHS - Multiply high - Multiply two integers of type iN, producing an unsigned/signed value of...
SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const
This class is used to represent ISD::LOAD nodes.
DYNAMIC_STACKALLOC - Allocate some number of bytes on the stack aligned to a specified boundary...