TargetInstrInfo - Interface to description of machine instruction set. More...
#include "llvm/CodeGen/TargetInstrInfo.h"
Classes | |
| struct | MachineBranchPredicate |
| Represents a predicate at the MachineFunction level. More... | |
| struct | RegSubRegPair |
| A pair composed of a register and a sub-register index. More... | |
| struct | RegSubRegPairAndIdx |
| A pair composed of a pair of a register and a sub-register index, and another sub-register index. More... | |
Public Member Functions | |
| TargetInstrInfo (unsigned CFSetupOpcode=~0u, unsigned CFDestroyOpcode=~0u, unsigned CatchRetOpcode=~0u, unsigned ReturnOpcode=~0u) | |
| TargetInstrInfo (const TargetInstrInfo &)=delete | |
| TargetInstrInfo & | operator= (const TargetInstrInfo &)=delete |
| virtual | ~TargetInstrInfo () |
| const TargetRegisterClass * | getRegClass (const MCInstrDesc &MCID, unsigned OpNum, const TargetRegisterInfo *TRI, const MachineFunction &MF) const |
| Given a machine instruction descriptor, returns the register class constraint for OpNum, or NULL. More... | |
| bool | isTriviallyReMaterializable (const MachineInstr &MI, AliasAnalysis *AA=nullptr) const |
| Return true if the instruction is trivially rematerializable, meaning it has no side effects and requires no operands that aren't always available. More... | |
| unsigned | getCallFrameSetupOpcode () const |
| These methods return the opcode of the frame setup/destroy instructions if they exist (-1 otherwise). More... | |
| unsigned | getCallFrameDestroyOpcode () const |
| bool | isFrameInstr (const MachineInstr &I) const |
| Returns true if the argument is a frame pseudo instruction. More... | |
| bool | isFrameSetup (const MachineInstr &I) const |
| Returns true if the argument is a frame setup pseudo instruction. More... | |
| int64_t | getFrameSize (const MachineInstr &I) const |
| Returns size of the frame associated with the given frame instruction. More... | |
| int64_t | getFrameTotalSize (const MachineInstr &I) const |
| Returns the total frame size, which is made up of the space set up inside the pair of frame start-stop instructions and the space that is set up prior to the pair. More... | |
| unsigned | getCatchReturnOpcode () const |
| unsigned | getReturnOpcode () const |
| virtual int | getSPAdjust (const MachineInstr &MI) const |
| Returns the actual stack pointer adjustment made by an instruction as part of a call sequence. More... | |
| virtual bool | isCoalescableExtInstr (const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg, unsigned &SubIdx) const |
| Return true if the instruction is a "coalescable" extension instruction. More... | |
| virtual unsigned | isLoadFromStackSlot (const MachineInstr &MI, int &FrameIndex) const |
| If the specified machine instruction is a direct load from a stack slot, return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot. More... | |
| virtual unsigned | isLoadFromStackSlot (const MachineInstr &MI, int &FrameIndex, unsigned &MemBytes) const |
| Optional extension of isLoadFromStackSlot that returns the number of bytes loaded from the stack. More... | |
| virtual unsigned | isLoadFromStackSlotPostFE (const MachineInstr &MI, int &FrameIndex) const |
| Check for post-frame ptr elimination stack locations as well. More... | |
| virtual bool | hasLoadFromStackSlot (const MachineInstr &MI, SmallVectorImpl< const MachineMemOperand *> &Accesses) const |
| If the specified machine instruction has a load from a stack slot, return true along with the FrameIndices of the loaded stack slot and the machine mem operands containing the reference. More... | |
| virtual unsigned | isStoreToStackSlot (const MachineInstr &MI, int &FrameIndex) const |
| If the specified machine instruction is a direct store to a stack slot, return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot. More... | |
| virtual unsigned | isStoreToStackSlot (const MachineInstr &MI, int &FrameIndex, unsigned &MemBytes) const |
| Optional extension of isStoreToStackSlot that returns the number of bytes stored to the stack. More... | |
| virtual unsigned | isStoreToStackSlotPostFE (const MachineInstr &MI, int &FrameIndex) const |
| Check for post-frame ptr elimination stack locations as well. More... | |
| virtual bool | hasStoreToStackSlot (const MachineInstr &MI, SmallVectorImpl< const MachineMemOperand *> &Accesses) const |
| If the specified machine instruction has a store to a stack slot, return true along with the FrameIndices of the loaded stack slot and the machine mem operands containing the reference. More... | |
| virtual bool | isStackSlotCopy (const MachineInstr &MI, int &DestFrameIndex, int &SrcFrameIndex) const |
| Return true if the specified machine instruction is a copy of one stack slot to another and has no other effect. More... | |
| virtual bool | getStackSlotRange (const TargetRegisterClass *RC, unsigned SubIdx, unsigned &Size, unsigned &Offset, const MachineFunction &MF) const |
| Compute the size in bytes and offset within a stack slot of a spilled register or subregister. More... | |
| virtual unsigned | getInstSizeInBytes (const MachineInstr &MI) const |
| Returns the size in bytes of the specified MachineInstr, or ~0U when this function is not implemented by a target. More... | |
| virtual bool | isAsCheapAsAMove (const MachineInstr &MI) const |
| Return true if the instruction is as cheap as a move instruction. More... | |
| virtual bool | shouldSink (const MachineInstr &MI) const |
| Return true if the instruction should be sunk by MachineSink. More... | |
| virtual void | reMaterialize (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, unsigned SubIdx, const MachineInstr &Orig, const TargetRegisterInfo &TRI) const |
| Re-issue the specified 'original' instruction at the specific location targeting a new destination register. More... | |
| virtual MachineInstr & | duplicate (MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore, const MachineInstr &Orig) const |
Clones instruction or the whole instruction bundle Orig and insert into MBB before InsertBefore. More... | |
| virtual MachineInstr * | convertToThreeAddress (MachineFunction::iterator &MFI, MachineInstr &MI, LiveVariables *LV) const |
| This method must be implemented by targets that set the M_CONVERTIBLE_TO_3_ADDR flag. More... | |
| MachineInstr * | commuteInstruction (MachineInstr &MI, bool NewMI=false, unsigned OpIdx1=CommuteAnyOperandIndex, unsigned OpIdx2=CommuteAnyOperandIndex) const |
| This method commutes the operands of the given machine instruction MI. More... | |
| virtual bool | findCommutedOpIndices (MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const |
| Returns true iff the routine could find two commutable operands in the given machine instruction. More... | |
| bool | getRegSequenceInputs (const MachineInstr &MI, unsigned DefIdx, SmallVectorImpl< RegSubRegPairAndIdx > &InputRegs) const |
Build the equivalent inputs of a REG_SEQUENCE for the given MI and DefIdx. More... | |
| bool | getExtractSubregInputs (const MachineInstr &MI, unsigned DefIdx, RegSubRegPairAndIdx &InputReg) const |
Build the equivalent inputs of a EXTRACT_SUBREG for the given MI and DefIdx. More... | |
| bool | getInsertSubregInputs (const MachineInstr &MI, unsigned DefIdx, RegSubRegPair &BaseReg, RegSubRegPairAndIdx &InsertedReg) const |
Build the equivalent inputs of a INSERT_SUBREG for the given MI and DefIdx. More... | |
| virtual bool | produceSameValue (const MachineInstr &MI0, const MachineInstr &MI1, const MachineRegisterInfo *MRI=nullptr) const |
| Return true if two machine instructions would produce identical values. More... | |
| virtual bool | isBranchOffsetInRange (unsigned BranchOpc, int64_t BrOffset) const |
| virtual MachineBasicBlock * | getBranchDestBlock (const MachineInstr &MI) const |
| virtual unsigned | insertIndirectBranch (MachineBasicBlock &MBB, MachineBasicBlock &NewDestBB, const DebugLoc &DL, int64_t BrOffset=0, RegScavenger *RS=nullptr) const |
Insert an unconditional indirect branch at the end of MBB to NewDestBB. More... | |
| virtual bool | analyzeBranch (MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const |
| Analyze the branching code at the end of MBB, returning true if it cannot be understood (e.g. More... | |
| virtual bool | analyzeBranchPredicate (MachineBasicBlock &MBB, MachineBranchPredicate &MBP, bool AllowModify=false) const |
| Analyze the branching code at the end of MBB and parse it into the MachineBranchPredicate structure if possible. More... | |
| virtual unsigned | removeBranch (MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const |
| Remove the branching code at the end of the specific MBB. More... | |
| virtual unsigned | insertBranch (MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const |
| Insert branch code into the end of the specified MachineBasicBlock. More... | |
| unsigned | insertUnconditionalBranch (MachineBasicBlock &MBB, MachineBasicBlock *DestBB, const DebugLoc &DL, int *BytesAdded=nullptr) const |
| virtual bool | analyzeLoop (MachineLoop &L, MachineInstr *&IndVarInst, MachineInstr *&CmpInst) const |
| Analyze the loop code, return true if it cannot be understoo. More... | |
| virtual unsigned | reduceLoopCount (MachineBasicBlock &MBB, MachineInstr *IndVar, MachineInstr &Cmp, SmallVectorImpl< MachineOperand > &Cond, SmallVectorImpl< MachineInstr *> &PrevInsts, unsigned Iter, unsigned MaxIter) const |
| Generate code to reduce the loop iteration by one and check if the loop is finished. More... | |
| virtual void | ReplaceTailWithBranchTo (MachineBasicBlock::iterator Tail, MachineBasicBlock *NewDest) const |
| Delete the instruction OldInst and everything after it, replacing it with an unconditional branch to NewDest. More... | |
| virtual bool | isLegalToSplitMBBAt (MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) const |
| Return true if it's legal to split the given basic block at the specified instruction (i.e. More... | |
| virtual bool | isProfitableToIfCvt (MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, BranchProbability Probability) const |
| Return true if it's profitable to predicate instructions with accumulated instruction latency of "NumCycles" of the specified basic block, where the probability of the instructions being executed is given by Probability, and Confidence is a measure of our confidence that it will be properly predicted. More... | |
| virtual bool | isProfitableToIfCvt (MachineBasicBlock &TMBB, unsigned NumTCycles, unsigned ExtraTCycles, MachineBasicBlock &FMBB, unsigned NumFCycles, unsigned ExtraFCycles, BranchProbability Probability) const |
| Second variant of isProfitableToIfCvt. More... | |
| virtual bool | isProfitableToDupForIfCvt (MachineBasicBlock &MBB, unsigned NumCycles, BranchProbability Probability) const |
| Return true if it's profitable for if-converter to duplicate instructions of specified accumulated instruction latencies in the specified MBB to enable if-conversion. More... | |
| virtual bool | isProfitableToUnpredicate (MachineBasicBlock &TMBB, MachineBasicBlock &FMBB) const |
| Return true if it's profitable to unpredicate one side of a 'diamond', i.e. More... | |
| virtual bool | canInsertSelect (const MachineBasicBlock &MBB, ArrayRef< MachineOperand > Cond, unsigned TrueReg, unsigned FalseReg, int &CondCycles, int &TrueCycles, int &FalseCycles) const |
| Return true if it is possible to insert a select instruction that chooses between TrueReg and FalseReg based on the condition code in Cond. More... | |
| virtual void | insertSelect (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, unsigned DstReg, ArrayRef< MachineOperand > Cond, unsigned TrueReg, unsigned FalseReg) const |
| Insert a select instruction into MBB before I that will copy TrueReg to DstReg when Cond is true, and FalseReg to DstReg when Cond is false. More... | |
| virtual bool | analyzeSelect (const MachineInstr &MI, SmallVectorImpl< MachineOperand > &Cond, unsigned &TrueOp, unsigned &FalseOp, bool &Optimizable) const |
| Analyze the given select instruction, returning true if it cannot be understood. More... | |
| virtual MachineInstr * | optimizeSelect (MachineInstr &MI, SmallPtrSetImpl< MachineInstr *> &NewMIs, bool PreferFalse=false) const |
| Given a select instruction that was understood by analyzeSelect and returned Optimizable = true, attempt to optimize MI by merging it with one of its operands. More... | |
| virtual void | copyPhysReg (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const |
| Emit instructions to copy a pair of physical registers. More... | |
| bool | isCopyInstr (const MachineInstr &MI, const MachineOperand *&Source, const MachineOperand *&Destination) const |
| If the specific machine instruction is a instruction that moves/copies value from one register to another register return true along with machine operand and machine operand. More... | |
| virtual void | storeRegToStackSlot (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const |
| Store the specified register of the given register class to the specified stack frame index. More... | |
| virtual void | loadRegFromStackSlot (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const |
| Load the specified register of the given register class from the specified stack frame index. More... | |
| virtual bool | expandPostRAPseudo (MachineInstr &MI) const |
| This function is called for all pseudo instructions that remain after register allocation. More... | |
| virtual bool | isSubregFoldable () const |
| Check whether the target can fold a load that feeds a subreg operand (or a subreg operand that feeds a store). More... | |
| MachineInstr * | foldMemoryOperand (MachineInstr &MI, ArrayRef< unsigned > Ops, int FI, LiveIntervals *LIS=nullptr) const |
| Attempt to fold a load or store of the specified stack slot into the specified machine instruction for the specified operand(s). More... | |
| MachineInstr * | foldMemoryOperand (MachineInstr &MI, ArrayRef< unsigned > Ops, MachineInstr &LoadMI, LiveIntervals *LIS=nullptr) const |
| Same as the previous version except it allows folding of any load and store from / to any address, not just from a specific stack slot. More... | |
| virtual bool | getMachineCombinerPatterns (MachineInstr &Root, SmallVectorImpl< MachineCombinerPattern > &Patterns) const |
Return true when there is potentially a faster code sequence for an instruction chain ending in Root. More... | |
| virtual bool | isThroughputPattern (MachineCombinerPattern Pattern) const |
| Return true when a code sequence can improve throughput. More... | |
| bool | isReassociationCandidate (const MachineInstr &Inst, bool &Commuted) const |
| Return true if the input Inst is part of a chain of dependent ops that are suitable for reassociation, otherwise return false. More... | |
| virtual bool | isAssociativeAndCommutative (const MachineInstr &Inst) const |
| Return true when Inst is both associative and commutative. More... | |
| virtual bool | hasReassociableOperands (const MachineInstr &Inst, const MachineBasicBlock *MBB) const |
| Return true when Inst has reassociable operands in the same MBB. More... | |
| bool | hasReassociableSibling (const MachineInstr &Inst, bool &Commuted) const |
| Return true when Inst has reassociable sibling. More... | |
| virtual void | genAlternativeCodeSequence (MachineInstr &Root, MachineCombinerPattern Pattern, SmallVectorImpl< MachineInstr *> &InsInstrs, SmallVectorImpl< MachineInstr *> &DelInstrs, DenseMap< unsigned, unsigned > &InstIdxForVirtReg) const |
| When getMachineCombinerPatterns() finds patterns, this function generates the instructions that could replace the original code sequence. More... | |
| void | reassociateOps (MachineInstr &Root, MachineInstr &Prev, MachineCombinerPattern Pattern, SmallVectorImpl< MachineInstr *> &InsInstrs, SmallVectorImpl< MachineInstr *> &DelInstrs, DenseMap< unsigned, unsigned > &InstrIdxForVirtReg) const |
| Attempt to reassociate Root and Prev according to Pattern to reduce critical path length. More... | |
| virtual void | setSpecialOperandAttr (MachineInstr &OldMI1, MachineInstr &OldMI2, MachineInstr &NewMI1, MachineInstr &NewMI2) const |
| This is an architecture-specific helper function of reassociateOps. More... | |
| virtual bool | useMachineCombiner () const |
| Return true when a target supports MachineCombiner. More... | |
| virtual bool | canCopyGluedNodeDuringSchedule (SDNode *N) const |
| Return true if the given SDNode can be copied during scheduling even if it has glue. More... | |
| virtual unsigned | getAddressSpaceForPseudoSourceKind (unsigned Kind) const |
| getAddressSpaceForPseudoSourceKind - Given the kind of memory (e.g. More... | |
| virtual bool | unfoldMemoryOperand (MachineFunction &MF, MachineInstr &MI, unsigned Reg, bool UnfoldLoad, bool UnfoldStore, SmallVectorImpl< MachineInstr *> &NewMIs) const |
| unfoldMemoryOperand - Separate a single instruction which folded a load or a store or a load and a store into two or more instruction. More... | |
| virtual bool | unfoldMemoryOperand (SelectionDAG &DAG, SDNode *N, SmallVectorImpl< SDNode *> &NewNodes) const |
| virtual unsigned | getOpcodeAfterMemoryUnfold (unsigned Opc, bool UnfoldLoad, bool UnfoldStore, unsigned *LoadRegIndex=nullptr) const |
| Returns the opcode of the would be new instruction after load / store are unfolded from an instruction of the specified opcode. More... | |
| virtual bool | areLoadsFromSameBasePtr (SDNode *Load1, SDNode *Load2, int64_t &Offset1, int64_t &Offset2) const |
| This is used by the pre-regalloc scheduler to determine if two loads are loading from the same base address. More... | |
| virtual bool | shouldScheduleLoadsNear (SDNode *Load1, SDNode *Load2, int64_t Offset1, int64_t Offset2, unsigned NumLoads) const |
| This is a used by the pre-regalloc scheduler to determine (in conjunction with areLoadsFromSameBasePtr) if two loads should be scheduled together. More... | |
| virtual bool | getMemOperandWithOffset (MachineInstr &MI, MachineOperand *&BaseOp, int64_t &Offset, const TargetRegisterInfo *TRI) const |
| Get the base operand and byte offset of an instruction that reads/writes memory. More... | |
| virtual bool | getBaseAndOffsetPosition (const MachineInstr &MI, unsigned &BasePos, unsigned &OffsetPos) const |
| Return true if the instruction contains a base register and offset. More... | |
| virtual bool | getIncrementValue (const MachineInstr &MI, int &Value) const |
| If the instruction is an increment of a constant value, return the amount. More... | |
| virtual bool | shouldClusterMemOps (MachineOperand &BaseOp1, MachineOperand &BaseOp2, unsigned NumLoads) const |
| Returns true if the two given memory operations should be scheduled adjacent. More... | |
| virtual bool | reverseBranchCondition (SmallVectorImpl< MachineOperand > &Cond) const |
| Reverses the branch condition of the specified condition list, returning false on success and true if it cannot be reversed. More... | |
| virtual void | insertNoop (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const |
| Insert a noop into the instruction stream at the specified point. More... | |
| virtual void | getNoop (MCInst &NopInst) const |
| Return the noop instruction to use for a noop. More... | |
| virtual bool | isPostIncrement (const MachineInstr &MI) const |
| Return true for post-incremented instructions. More... | |
| virtual bool | isPredicated (const MachineInstr &MI) const |
| Returns true if the instruction is already predicated. More... | |
| virtual bool | isUnpredicatedTerminator (const MachineInstr &MI) const |
| Returns true if the instruction is a terminator instruction that has not been predicated. More... | |
| virtual bool | isUnconditionalTailCall (const MachineInstr &MI) const |
| Returns true if MI is an unconditional tail call. More... | |
| virtual bool | canMakeTailCallConditional (SmallVectorImpl< MachineOperand > &Cond, const MachineInstr &TailCall) const |
| Returns true if the tail call can be made conditional on BranchCond. More... | |
| virtual void | replaceBranchWithTailCall (MachineBasicBlock &MBB, SmallVectorImpl< MachineOperand > &Cond, const MachineInstr &TailCall) const |
| Replace the conditional branch in MBB with a conditional tail call. More... | |
| virtual bool | PredicateInstruction (MachineInstr &MI, ArrayRef< MachineOperand > Pred) const |
| Convert the instruction into a predicated instruction. More... | |
| virtual bool | SubsumesPredicate (ArrayRef< MachineOperand > Pred1, ArrayRef< MachineOperand > Pred2) const |
| Returns true if the first specified predicate subsumes the second, e.g. More... | |
| virtual bool | DefinesPredicate (MachineInstr &MI, std::vector< MachineOperand > &Pred) const |
| If the specified instruction defines any predicate or condition code register(s) used for predication, returns true as well as the definition predicate(s) by reference. More... | |
| virtual bool | isPredicable (const MachineInstr &MI) const |
| Return true if the specified instruction can be predicated. More... | |
| virtual bool | isSafeToMoveRegClassDefs (const TargetRegisterClass *RC) const |
| Return true if it's safe to move a machine instruction that defines the specified register class. More... | |
| virtual bool | isSchedulingBoundary (const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const |
| Test if the given instruction should be considered a scheduling boundary. More... | |
| virtual unsigned | getInlineAsmLength (const char *Str, const MCAsmInfo &MAI) const |
| Measure the specified inline asm to determine an approximation of its length. More... | |
| virtual ScheduleHazardRecognizer * | CreateTargetHazardRecognizer (const TargetSubtargetInfo *STI, const ScheduleDAG *DAG) const |
| Allocate and return a hazard recognizer to use for this target when scheduling the machine instructions before register allocation. More... | |
| virtual ScheduleHazardRecognizer * | CreateTargetMIHazardRecognizer (const InstrItineraryData *, const ScheduleDAG *DAG) const |
| Allocate and return a hazard recognizer to use for this target when scheduling the machine instructions before register allocation. More... | |
| virtual ScheduleHazardRecognizer * | CreateTargetPostRAHazardRecognizer (const InstrItineraryData *, const ScheduleDAG *DAG) const |
| Allocate and return a hazard recognizer to use for this target when scheduling the machine instructions after register allocation. More... | |
| virtual ScheduleHazardRecognizer * | CreateTargetPostRAHazardRecognizer (const MachineFunction &MF) const |
| Allocate and return a hazard recognizer to use for by non-scheduling passes. More... | |
| bool | usePreRAHazardRecognizer () const |
| Provide a global flag for disabling the PreRA hazard recognizer that targets may choose to honor. More... | |
| virtual bool | analyzeCompare (const MachineInstr &MI, unsigned &SrcReg, unsigned &SrcReg2, int &Mask, int &Value) const |
| For a comparison instruction, return the source registers in SrcReg and SrcReg2 if having two register operands, and the value it compares against in CmpValue. More... | |
| virtual bool | optimizeCompareInstr (MachineInstr &CmpInstr, unsigned SrcReg, unsigned SrcReg2, int Mask, int Value, const MachineRegisterInfo *MRI) const |
| See if the comparison instruction can be converted into something more efficient. More... | |
| virtual bool | optimizeCondBranch (MachineInstr &MI) const |
| virtual MachineInstr * | optimizeLoadInstr (MachineInstr &MI, const MachineRegisterInfo *MRI, unsigned &FoldAsLoadDefReg, MachineInstr *&DefMI) const |
| Try to remove the load by folding it to a register operand at the use. More... | |
| virtual bool | FoldImmediate (MachineInstr &UseMI, MachineInstr &DefMI, unsigned Reg, MachineRegisterInfo *MRI) const |
| 'Reg' is known to be defined by a move immediate instruction, try to fold the immediate into the use instruction. More... | |
| virtual unsigned | getNumMicroOps (const InstrItineraryData *ItinData, const MachineInstr &MI) const |
| Return the number of u-operations the given machine instruction will be decoded to on the target cpu. More... | |
| bool | isZeroCost (unsigned Opcode) const |
| Return true for pseudo instructions that don't consume any machine resources in their current form. More... | |
| virtual int | getOperandLatency (const InstrItineraryData *ItinData, SDNode *DefNode, unsigned DefIdx, SDNode *UseNode, unsigned UseIdx) const |
| virtual int | getOperandLatency (const InstrItineraryData *ItinData, const MachineInstr &DefMI, unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const |
| Compute and return the use operand latency of a given pair of def and use. More... | |
| virtual unsigned | getInstrLatency (const InstrItineraryData *ItinData, const MachineInstr &MI, unsigned *PredCost=nullptr) const |
| Compute the instruction latency of a given instruction. More... | |
| virtual unsigned | getPredicationCost (const MachineInstr &MI) const |
| virtual int | getInstrLatency (const InstrItineraryData *ItinData, SDNode *Node) const |
| unsigned | defaultDefLatency (const MCSchedModel &SchedModel, const MachineInstr &DefMI) const |
| Return the default expected latency for a def based on its opcode. More... | |
| int | computeDefOperandLatency (const InstrItineraryData *ItinData, const MachineInstr &DefMI) const |
| If we can determine the operand latency from the def only, without itinerary lookup, do so. More... | |
| virtual bool | isHighLatencyDef (int opc) const |
| Return true if this opcode has high latency to its result. More... | |
| virtual bool | hasHighOperandLatency (const TargetSchedModel &SchedModel, const MachineRegisterInfo *MRI, const MachineInstr &DefMI, unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const |
| Compute operand latency between a def of 'Reg' and a use in the current loop. More... | |
| virtual bool | hasLowDefLatency (const TargetSchedModel &SchedModel, const MachineInstr &DefMI, unsigned DefIdx) const |
| Compute operand latency of a def of 'Reg'. More... | |
| virtual bool | verifyInstruction (const MachineInstr &MI, StringRef &ErrInfo) const |
| Perform target-specific instruction verification. More... | |
| virtual std::pair< uint16_t, uint16_t > | getExecutionDomain (const MachineInstr &MI) const |
| Return the current execution domain and bit mask of possible domains for instruction. More... | |
| virtual void | setExecutionDomain (MachineInstr &MI, unsigned Domain) const |
| Change the opcode of MI to execute in Domain. More... | |
| virtual unsigned | getPartialRegUpdateClearance (const MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) const |
| Returns the preferred minimum clearance before an instruction with an unwanted partial register update. More... | |
| virtual unsigned | getUndefRegClearance (const MachineInstr &MI, unsigned &OpNum, const TargetRegisterInfo *TRI) const |
| Return the minimum clearance before an instruction that reads an unused register. More... | |
| virtual void | breakPartialRegDependency (MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) const |
| Insert a dependency-breaking instruction before MI to eliminate an unwanted dependency on OpNum. More... | |
| virtual DFAPacketizer * | CreateTargetScheduleState (const TargetSubtargetInfo &) const |
| Create machine specific model for scheduling. More... | |
| virtual bool | areMemAccessesTriviallyDisjoint (MachineInstr &MIa, MachineInstr &MIb, AliasAnalysis *AA=nullptr) const |
| Sometimes, it is possible for the target to tell, even without aliasing information, that two MIs access different memory addresses. More... | |
| virtual unsigned | getMachineCSELookAheadLimit () const |
| Return the value to use for the MachineCSE's LookAheadLimit, which is a heuristic used for CSE'ing phys reg defs. More... | |
| virtual ArrayRef< std::pair< int, const char * > > | getSerializableTargetIndices () const |
| Return an array that contains the ids of the target indices (used for the TargetIndex machine operand) and their names. More... | |
| virtual std::pair< unsigned, unsigned > | decomposeMachineOperandsTargetFlags (unsigned) const |
| Decompose the machine operand's target flags into two values - the direct target flag value and any of bit flags that are applied. More... | |
| virtual ArrayRef< std::pair< unsigned, const char * > > | getSerializableDirectMachineOperandTargetFlags () const |
| Return an array that contains the direct target flag values and their names. More... | |
| virtual ArrayRef< std::pair< unsigned, const char * > > | getSerializableBitmaskMachineOperandTargetFlags () const |
| Return an array that contains the bitmask target flag values and their names. More... | |
| virtual ArrayRef< std::pair< MachineMemOperand::Flags, const char * > > | getSerializableMachineMemOperandTargetFlags () const |
| Return an array that contains the MMO target flag values and their names. More... | |
| virtual bool | isTailCall (const MachineInstr &Inst) const |
Determines whether Inst is a tail call instruction. More... | |
| virtual bool | isBasicBlockPrologue (const MachineInstr &MI) const |
| True if the instruction is bound to the top of its basic block and no other instructions shall be inserted before it. More... | |
| virtual outliner::OutlinedFunction | getOutliningCandidateInfo (std::vector< outliner::Candidate > &RepeatedSequenceLocs) const |
Returns a outliner::OutlinedFunction struct containing target-specific information for a set of outlining candidates. More... | |
| virtual outliner::InstrType | getOutliningType (MachineBasicBlock::iterator &MIT, unsigned Flags) const |
Returns how or if MI should be outlined. More... | |
| virtual bool | isMBBSafeToOutlineFrom (MachineBasicBlock &MBB, unsigned &Flags) const |
Optional target hook that returns true if MBB is safe to outline from, and returns any target-specific information in Flags. More... | |
| virtual void | buildOutlinedFrame (MachineBasicBlock &MBB, MachineFunction &MF, const outliner::OutlinedFunction &OF) const |
| Insert a custom frame for outlined functions. More... | |
| virtual MachineBasicBlock::iterator | insertOutlinedCall (Module &M, MachineBasicBlock &MBB, MachineBasicBlock::iterator &It, MachineFunction &MF, const outliner::Candidate &C) const |
| Insert a call to an outlined function into the program. More... | |
| virtual bool | isFunctionSafeToOutlineFrom (MachineFunction &MF, bool OutlineFromLinkOnceODRs) const |
| Return true if the function can safely be outlined from. More... | |
| virtual bool | shouldOutlineFromFunctionByDefault (MachineFunction &MF) const |
| Return true if the function should be outlined from by default. More... | |
 Public Member Functions inherited from llvm::MCInstrInfo | |
| void | InitMCInstrInfo (const MCInstrDesc *D, const unsigned *NI, const char *ND, unsigned NO) |
| Initialize MCInstrInfo, called by TableGen auto-generated routines. More... | |
| unsigned | getNumOpcodes () const |
| const MCInstrDesc & | get (unsigned Opcode) const |
| Return the machine instruction descriptor that corresponds to the specified instruction opcode. More... | |
| StringRef | getName (unsigned Opcode) const |
| Returns the name for the instructions with the given opcode. More... | |
Static Public Member Functions | |
| static bool | isGenericOpcode (unsigned Opc) |
Static Public Attributes | |
| static const unsigned | CommuteAnyOperandIndex = ~0U |
Protected Member Functions | |
| virtual bool | isReallyTriviallyReMaterializable (const MachineInstr &MI, AliasAnalysis *AA) const |
| For instructions with opcodes for which the M_REMATERIALIZABLE flag is set, this hook lets the target specify whether the instruction is actually trivially rematerializable, taking into consideration its operands. More... | |
| virtual MachineInstr * | commuteInstructionImpl (MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const |
| This method commutes the operands of the given machine instruction MI. More... | |
| virtual bool | isCopyInstrImpl (const MachineInstr &MI, const MachineOperand *&Source, const MachineOperand *&Destination) const |
| Target-dependent implemenation for IsCopyInstr. More... | |
| virtual MachineInstr * | foldMemoryOperandImpl (MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex, LiveIntervals *LIS=nullptr) const |
| Target-dependent implementation for foldMemoryOperand. More... | |
| virtual MachineInstr * | foldMemoryOperandImpl (MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI, LiveIntervals *LIS=nullptr) const |
| Target-dependent implementation for foldMemoryOperand. More... | |
| virtual bool | getRegSequenceLikeInputs (const MachineInstr &MI, unsigned DefIdx, SmallVectorImpl< RegSubRegPairAndIdx > &InputRegs) const |
| Target-dependent implementation of getRegSequenceInputs. More... | |
| virtual bool | getExtractSubregLikeInputs (const MachineInstr &MI, unsigned DefIdx, RegSubRegPairAndIdx &InputReg) const |
| Target-dependent implementation of getExtractSubregInputs. More... | |
| virtual bool | getInsertSubregLikeInputs (const MachineInstr &MI, unsigned DefIdx, RegSubRegPair &BaseReg, RegSubRegPairAndIdx &InsertedReg) const |
| Target-dependent implementation of getInsertSubregInputs. More... | |
Static Protected Member Functions | |
| static bool | fixCommutedOpIndices (unsigned &ResultIdx1, unsigned &ResultIdx2, unsigned CommutableOpIdx1, unsigned CommutableOpIdx2) |
| Assigns the (CommutableOpIdx1, CommutableOpIdx2) pair of commutable operand indices to (ResultIdx1, ResultIdx2). More... | |
Detailed Description
TargetInstrInfo - Interface to description of machine instruction set.
Definition at line 67 of file TargetInstrInfo.h.
Constructor & Destructor Documentation
◆ TargetInstrInfo() [1/2]
|
inline |
Definition at line 69 of file TargetInstrInfo.h.
References operator=(), and ~TargetInstrInfo().
◆ TargetInstrInfo() [2/2]
|
delete |
◆ ~TargetInstrInfo()
|
virtual |
Definition at line 41 of file TargetInstrInfo.cpp.
Referenced by TargetInstrInfo().
Member Function Documentation
◆ analyzeBranch()
|
inlinevirtual |
Analyze the branching code at the end of MBB, returning true if it cannot be understood (e.g.
it's a switch dispatch or isn't implemented for a target). Upon success, this returns false and returns with the following information in various cases:
- If this block ends with no branches (it just falls through to its succ) just return false, leaving TBB/FBB null.
- If this block ends with only an unconditional branch, it sets TBB to be the destination block.
- If this block ends with a conditional branch and it falls through to a successor block, it sets TBB to be the branch destination block and a list of operands that evaluate the condition. These operands can be passed to other TargetInstrInfo methods to create new branches.
- If this block ends with a conditional branch followed by an unconditional branch, it returns the 'true' destination in TBB, the 'false' destination in FBB, and a list of operands that evaluate the condition. These operands can be passed to other TargetInstrInfo methods to create new branches.
Note that removeBranch and insertBranch must be implemented to support cases where this method returns success.
If AllowModify is true, then this routine is allowed to modify the basic block (e.g. delete instructions after the unconditional branch).
The CFG information in MBB.Predecessors and MBB.Successors must be valid before calling this function.
Definition at line 567 of file TargetInstrInfo.h.
Referenced by bothUsedInPHI(), llvm::MachineBasicBlock::canSplitCriticalEdge(), llvm::TailDuplicator::canTailDuplicate(), findHoistingInsertPosAndDeps(), FixTail(), getBBFallenThrough(), llvm::MachineBasicBlock::getFallThrough(), getLayoutSuccessorProbThreshold(), isIntersect(), isOperandKill(), matchPair(), mergeOperations(), llvm::BranchFolder::OptimizeFunction(), parseCond(), llvm::MachinePipeliner::runOnMachineFunction(), salvageDebugInfoFromEmptyBlock(), llvm::TailDuplicator::shouldTailDuplicate(), llvm::MachineBasicBlock::updateTerminator(), and verifySameBranchInstructions().
◆ analyzeBranchPredicate()
|
inlinevirtual |
Analyze the branching code at the end of MBB and parse it into the MachineBranchPredicate structure if possible.
Returns false on success and true on failure.
If AllowModify is true, then this routine is allowed to modify the basic block (e.g. delete instructions after the unconditional branch).
Definition at line 609 of file TargetInstrInfo.h.
Referenced by AnyAliasLiveIn(), and SinkingPreventsImplicitNullCheck().
◆ analyzeCompare()
|
inlinevirtual |
For a comparison instruction, return the source registers in SrcReg and SrcReg2 if having two register operands, and the value it compares against in CmpValue.
Return true if the comparison instruction can be analyzed.
Definition at line 1292 of file TargetInstrInfo.h.
◆ analyzeLoop()
|
inlinevirtual |
Analyze the loop code, return true if it cannot be understoo.
Upon success, this function returns false and returns information about the induction variable and compare instruction used at the end.
Definition at line 657 of file TargetInstrInfo.h.
Referenced by llvm::MachinePipeliner::runOnMachineFunction().
◆ analyzeSelect()
|
inlinevirtual |
Analyze the given select instruction, returning true if it cannot be understood.
It is assumed that MI->isSelect() is true.
When successful, return the controlling condition and the operands that determine the true and false result values.
Result = SELECT Cond, TrueOp, FalseOp
Some targets can optimize select instructions, for example by predicating the instruction defining one of the operands. Such targets should set Optimizable.
- Parameters
-
MI Select instruction to analyze. Cond Condition controlling the select. TrueOp Operand number of the value selected when Cond is true. FalseOp Operand number of the value selected when Cond is false. Optimizable Returned as true if MI is optimizable.
- Returns
- False on success.
Definition at line 804 of file TargetInstrInfo.h.
References assert(), llvm::MachineInstr::getDesc(), and llvm::MCInstrDesc::isSelect().
◆ areLoadsFromSameBasePtr()
|
inlinevirtual |
This is used by the pre-regalloc scheduler to determine if two loads are loading from the same base address.
It should only return true if the base pointers are the same and the only differences between the two addresses are the offset. It also returns the offsets by reference.
Definition at line 1119 of file TargetInstrInfo.h.
◆ areMemAccessesTriviallyDisjoint()
|
inlinevirtual |
Sometimes, it is possible for the target to tell, even without aliasing information, that two MIs access different memory addresses.
This function returns true if two MIs access different memory addresses and false otherwise.
Assumes any physical registers used to compute addresses have the same value for both instructions. (This is the most useful assumption for post-RA scheduling.)
See also MachineInstr::mayAlias, which is implemented on top of this function.
Definition at line 1545 of file TargetInstrInfo.h.
References assert(), llvm::MachineInstr::mayLoad(), and llvm::MachineInstr::mayStore().
Referenced by getUnderlyingObjects(), llvm::MachineInstr::mayAlias(), and removePhis().
◆ breakPartialRegDependency()
|
inlinevirtual |
Insert a dependency-breaking instruction before MI to eliminate an unwanted dependency on OpNum.
If it wasn't possible to avoid a def in the last N instructions before MI (see getPartialRegUpdateClearance), this hook will be called to break the unwanted dependency.
On x86, an xorps instruction can be used as a dependency breaker:
addps xmm1, xmm0 movaps xmm0, (rax) xorps xmm0, xmm0 cvtsi2ss rbx, xmm0
An <imp-kill> operand should be added to MI if an instruction was inserted. This ties the instructions together in the post-ra scheduler.
Definition at line 1524 of file TargetInstrInfo.h.
Referenced by llvm::createBreakFalseDeps().
◆ buildOutlinedFrame()
|
inlinevirtual |
Insert a custom frame for outlined functions.
Definition at line 1646 of file TargetInstrInfo.h.
References llvm_unreachable.
Referenced by INITIALIZE_PASS().
◆ canCopyGluedNodeDuringSchedule()
|
inlinevirtual |
Return true if the given SDNode can be copied during scheduling even if it has glue.
Definition at line 1009 of file TargetInstrInfo.h.
◆ canInsertSelect()
|
inlinevirtual |
Return true if it is possible to insert a select instruction that chooses between TrueReg and FalseReg based on the condition code in Cond.
When successful, also return the latency in cycles from TrueReg, FalseReg, and Cond to the destination register. In most cases, a select instruction will be 1 cycle, so CondCycles = TrueCycles = FalseCycles = 1
Some x86 implementations have 2-cycle cmov instructions.
- Parameters
-
MBB Block where select instruction would be inserted. Cond Condition returned by AnalyzeBranch. TrueReg Virtual register to select when Cond is true. FalseReg Virtual register to select when Cond is false. CondCycles Latency from Cond+Branch to select output. TrueCycles Latency from TrueReg to select output. FalseCycles Latency from FalseReg to select output.
Definition at line 757 of file TargetInstrInfo.h.
◆ canMakeTailCallConditional()
|
inlinevirtual |
Returns true if the tail call can be made conditional on BranchCond.
Definition at line 1203 of file TargetInstrInfo.h.
Referenced by salvageDebugInfoFromEmptyBlock().
◆ commuteInstruction()
| MachineInstr * TargetInstrInfo::commuteInstruction | ( | MachineInstr & | MI, |
| bool | NewMI = false, |
||
| unsigned | OpIdx1 = CommuteAnyOperandIndex, |
||
| unsigned | OpIdx2 = CommuteAnyOperandIndex |
||
| ) | const |
This method commutes the operands of the given machine instruction MI.
The operands to be commuted are specified by their indices OpIdx1 and OpIdx2. OpIdx1 and OpIdx2 arguments may be set to a special value 'CommuteAnyOperandIndex', which means that the method is free to choose any arbitrarily chosen commutable operand. If both arguments are set to 'CommuteAnyOperandIndex' then the method looks for 2 different commutable operands; then commutes them if such operands could be found.
If NewMI is false, MI is modified in place and returned; otherwise, a new machine instruction is created and returned.
Do not call this method for a non-commutable instruction or for non-commuable operands. Even though the instruction is commutable, the method may still fail to commute the operands, null pointer is returned in such cases.
Definition at line 231 of file TargetInstrInfo.cpp.
References assert(), CommuteAnyOperandIndex, commuteInstructionImpl(), findCommutedOpIndices(), and llvm::MachineInstr::isCommutable().
Referenced by addSegmentsWithValNo(), isCallerPreservedOrConstPhysReg(), isVirtualRegisterOperand(), and regOverlapsSet().
◆ commuteInstructionImpl()
|
protectedvirtual |
This method commutes the operands of the given machine instruction MI.
The operands to be commuted are specified by their indices OpIdx1 and OpIdx2.
If a target has any instructions that are commutable but require converting to different instructions or making non-trivial changes to commute them, this method can be overloaded to do that. The default implementation simply swaps the commutable operands.
If NewMI is false, MI is modified in place and returned; otherwise, a new machine instruction is created and returned.
Do not call this method for a non-commutable instruction. Even though the instruction is commutable, the method may still fail to commute the operands, null pointer is returned in such cases.
Definition at line 148 of file TargetInstrInfo.cpp.
References assert(), llvm::MachineFunction::CloneMachineInstr(), findCommutedOpIndices(), llvm::MachineInstr::getDesc(), llvm::MachineInstr::getMF(), llvm::MCInstrDesc::getNumDefs(), llvm::MachineInstr::getOperand(), llvm::MCInstrDesc::getOperandConstraint(), llvm::MachineOperand::getReg(), llvm::MachineOperand::getSubReg(), llvm::MachineOperand::isInternalRead(), llvm::MachineOperand::isKill(), llvm::TargetRegisterInfo::isPhysicalRegister(), llvm::MachineOperand::isReg(), llvm::MachineOperand::isRenamable(), llvm::MachineOperand::isUndef(), MI, llvm::MachineOperand::setIsInternalRead(), llvm::MachineOperand::setIsKill(), llvm::MachineOperand::setIsRenamable(), llvm::MachineOperand::setIsUndef(), llvm::MachineOperand::setReg(), llvm::MachineOperand::setSubReg(), and llvm::MCOI::TIED_TO.
Referenced by commuteInstruction(), llvm::WebAssemblyInstrInfo::commuteInstructionImpl(), llvm::ARMBaseInstrInfo::commuteInstructionImpl(), llvm::SIInstrInfo::commuteInstructionImpl(), llvm::PPCInstrInfo::commuteInstructionImpl(), llvm::SystemZInstrInfo::commuteInstructionImpl(), llvm::X86InstrInfo::commuteInstructionImpl(), and isReallyTriviallyReMaterializable().
◆ computeDefOperandLatency()
| int TargetInstrInfo::computeDefOperandLatency | ( | const InstrItineraryData * | ItinData, |
| const MachineInstr & | DefMI | ||
| ) | const |
If we can determine the operand latency from the def only, without itinerary lookup, do so.
Otherwise return -1.
Definition at line 1128 of file TargetInstrInfo.cpp.
References defaultDefLatency(), getInstrLatency(), llvm::InstrItineraryData::isEmpty(), and llvm::InstrItineraryData::SchedModel.
◆ convertToThreeAddress()
|
inlinevirtual |
This method must be implemented by targets that set the M_CONVERTIBLE_TO_3_ADDR flag.
When this flag is set, the target may be able to convert a two-address instruction into one or more true three-address instructions on demand. This allows the X86 target (for example) to convert ADD and SHL instructions into LEA instructions if they would require register copies due to two-addressness.
This method returns a null pointer if the transformation cannot be performed, otherwise it returns the last new instruction.
Definition at line 371 of file TargetInstrInfo.h.
Referenced by regOverlapsSet().
◆ copyPhysReg()
|
inlinevirtual |
Emit instructions to copy a pair of physical registers.
This function should support copies within any legal register class as well as any cross-class copies created during instruction selection.
The source and destination registers may overlap, which may require a careful implementation when multiple copy instructions are required for large registers. See for example the ARM target.
Definition at line 842 of file TargetInstrInfo.h.
References llvm_unreachable.
Referenced by llvm::Mips16RegisterInfo::saveScavengerRegister().
◆ CreateTargetHazardRecognizer()
|
virtual |
Allocate and return a hazard recognizer to use for this target when scheduling the machine instructions before register allocation.
Definition at line 1002 of file TargetInstrInfo.cpp.
References CreateTargetMIHazardRecognizer().
Referenced by llvm::ARMBaseInstrInfo::CreateTargetHazardRecognizer(), llvm::PPCInstrInfo::CreateTargetHazardRecognizer(), isSafeToMoveRegClassDefs(), and usePreRAHazardRecognizer().
◆ CreateTargetMIHazardRecognizer()
|
virtual |
Allocate and return a hazard recognizer to use for this target when scheduling the machine instructions before register allocation.
Definition at line 1010 of file TargetInstrInfo.cpp.
References CreateTargetPostRAHazardRecognizer().
Referenced by CreateTargetHazardRecognizer(), llvm::ConvergingVLIWScheduler::initialize(), llvm::PostGenericScheduler::initialize(), and isSafeToMoveRegClassDefs().
◆ CreateTargetPostRAHazardRecognizer() [1/2]
|
virtual |
Allocate and return a hazard recognizer to use for this target when scheduling the machine instructions after register allocation.
Definition at line 1018 of file TargetInstrInfo.cpp.
Referenced by CreateTargetMIHazardRecognizer(), llvm::ARMBaseInstrInfo::CreateTargetPostRAHazardRecognizer(), llvm::HexagonInstrInfo::CreateTargetPostRAHazardRecognizer(), INITIALIZE_PASS(), and isSafeToMoveRegClassDefs().
◆ CreateTargetPostRAHazardRecognizer() [2/2]
|
inlinevirtual |
Allocate and return a hazard recognizer to use for by non-scheduling passes.
Definition at line 1280 of file TargetInstrInfo.h.
References usePreRAHazardRecognizer().
◆ CreateTargetScheduleState()
|
inlinevirtual |
Create machine specific model for scheduling.
Definition at line 1529 of file TargetInstrInfo.h.
Referenced by getUnderlyingObjects(), llvm::ResourcePriorityQueue::ResourcePriorityQueue(), llvm::VLIWPacketizerList::VLIWPacketizerList(), and llvm::VLIWResourceModel::VLIWResourceModel().
◆ decomposeMachineOperandsTargetFlags()
|
inlinevirtual |
Decompose the machine operand's target flags into two values - the direct target flag value and any of bit flags that are applied.
Definition at line 1575 of file TargetInstrInfo.h.
◆ defaultDefLatency()
| unsigned TargetInstrInfo::defaultDefLatency | ( | const MCSchedModel & | SchedModel, |
| const MachineInstr & | DefMI | ||
| ) | const |
Return the default expected latency for a def based on its opcode.
Return the default expected latency for a def based on it's opcode.
Definition at line 1076 of file TargetInstrInfo.cpp.
References llvm::MachineInstr::getOpcode(), llvm::MCSchedModel::HighLatency, if(), isHighLatencyDef(), llvm::MachineInstr::isTransient(), llvm::MCSchedModel::LoadLatency, and llvm::MachineInstr::mayLoad().
Referenced by computeDefOperandLatency(), llvm::TargetSchedModel::computeInstrLatency(), and llvm::TargetSchedModel::computeOperandLatency().
◆ DefinesPredicate()
|
inlinevirtual |
If the specified instruction defines any predicate or condition code register(s) used for predication, returns true as well as the definition predicate(s) by reference.
Definition at line 1230 of file TargetInstrInfo.h.
Referenced by getNextBlock().
◆ duplicate()
|
virtual |
Clones instruction or the whole instruction bundle Orig and insert into MBB before InsertBefore.
The target may update operands that are required to be unique.
Orig must not return true for MachineInstr::isNotDuplicable().
Definition at line 416 of file TargetInstrInfo.cpp.
References assert(), llvm::MachineFunction::CloneMachineInstrBundle(), llvm::MachineBasicBlock::getParent(), and llvm::MachineInstr::isNotDuplicable().
Referenced by copyDebugInfoToPredecessor(), copyDebugInfoToSuccessor(), llvm::ARMBaseInstrInfo::duplicate(), getRegsUsedByPHIs(), and shouldSink().
◆ expandPostRAPseudo()
|
inlinevirtual |
This function is called for all pseudo instructions that remain after register allocation.
Many pseudo instructions are created to help register allocation. This is the place to convert them into real instructions. The target can edit MI in place, or it can insert new instructions and erase MI. The function should return true if anything was changed.
Definition at line 907 of file TargetInstrInfo.h.
Referenced by llvm::SIInstrInfo::expandPostRAPseudo().
◆ findCommutedOpIndices()
|
virtual |
Returns true iff the routine could find two commutable operands in the given machine instruction.
The 'SrcOpIdx1' and 'SrcOpIdx2' are INPUT and OUTPUT arguments. If any of the INPUT values is set to the special value 'CommuteAnyOperandIndex' then the method arbitrarily picks a commutable operand, then returns its index in the corresponding argument. If both of INPUT values are set to 'CommuteAnyOperandIndex' then method looks for 2 commutable operands. If INPUT values refer to some operands of MI, then the method simply returns true if the corresponding operands are commutable and returns false otherwise.
For example, calling this method this way: unsigned Op1 = 1, Op2 = CommuteAnyOperandIndex; findCommutedOpIndices(MI, Op1, Op2); can be interpreted as a query asking to find an operand that would be commutable with the operand#1.
Definition at line 277 of file TargetInstrInfo.cpp.
References assert(), fixCommutedOpIndices(), llvm::MachineInstr::getDesc(), llvm::MCInstrDesc::getNumDefs(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::isBundle(), and llvm::MachineOperand::isReg().
Referenced by addSegmentsWithValNo(), commuteInstruction(), commuteInstructionImpl(), llvm::MipsInstrInfo::findCommutedOpIndices(), llvm::PPCInstrInfo::findCommutedOpIndices(), llvm::X86InstrInfo::findCommutedOpIndices(), and isVirtualRegisterOperand().
◆ fixCommutedOpIndices()
|
staticprotected |
Assigns the (CommutableOpIdx1, CommutableOpIdx2) pair of commutable operand indices to (ResultIdx1, ResultIdx2).
One or both input values of the pair: (ResultIdx1, ResultIdx2) may be predefined to some indices or be undefined (designated by the special value 'CommuteAnyOperandIndex'). The predefined result indices cannot be re-defined. The function returns true iff after the result pair redefinition the fixed result pair is equal to or equivalent to the source pair of indices: (CommutableOpIdx1, CommutableOpIdx2). It is assumed here that the pairs (x,y) and (y,x) are equivalent.
Definition at line 246 of file TargetInstrInfo.cpp.
References CommuteAnyOperandIndex.
Referenced by findCommutedOpIndices(), and isReallyTriviallyReMaterializable().
◆ FoldImmediate()
|
inlinevirtual |
'Reg' is known to be defined by a move immediate instruction, try to fold the immediate into the use instruction.
If MRI->hasOneNonDBGUse(Reg) is true, and this function returns true, then the caller may assume that DefMI has been erased from its parent block. The caller may assume that it will not be erased by this function otherwise.
Definition at line 1327 of file TargetInstrInfo.h.
References getNumMicroOps().
Referenced by getNewSource().
◆ foldMemoryOperand() [1/2]
| MachineInstr * TargetInstrInfo::foldMemoryOperand | ( | MachineInstr & | MI, |
| ArrayRef< unsigned > | Ops, | ||
| int | FI, | ||
| LiveIntervals * | LIS = nullptr |
||
| ) | const |
Attempt to fold a load or store of the specified stack slot into the specified machine instruction for the specified operand(s).
If this is possible, a new instruction is returned with the specified operand folded, otherwise NULL is returned. The new instruction is inserted before MI, and the client is responsible for removing the old instruction.
Definition at line 524 of file TargetInstrInfo.cpp.
References llvm::MachineInstr::addMemOperand(), assert(), canFoldCopy(), foldMemoryOperandImpl(), foldPatchpoint(), llvm::MachinePointerInfo::getFixedStack(), llvm::MachineFunction::getFrameInfo(), llvm::MachineFunction::getMachineMemOperand(), llvm::MachineFrameInfo::getObjectAlignment(), llvm::MachineFrameInfo::getObjectOffset(), llvm::MachineFrameInfo::getObjectSize(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), llvm::TargetSubtargetInfo::getRegisterInfo(), llvm::MachineOperand::getSubReg(), llvm::MCRegisterInfo::getSubRegIdxSize(), llvm::MachineFunction::getSubtarget(), llvm::MachineBasicBlock::insert(), llvm::MachineInstr::isCopy(), llvm::MachineOperand::isDef(), llvm::MachineOperand::isKill(), loadRegFromStackSlot(), llvm::max(), llvm::MachineInstr::mayLoad(), llvm::MachineInstr::mayStore(), llvm::MachineInstr::memoperands(), MI, llvm::MachineMemOperand::MOLoad, llvm::MachineMemOperand::MONone, llvm::MachineMemOperand::MOStore, llvm::MachineInstr::setMemRefs(), storeRegToStackSlot(), SubReg, and TRI.
Referenced by isSubregFoldable().
◆ foldMemoryOperand() [2/2]
| MachineInstr * TargetInstrInfo::foldMemoryOperand | ( | MachineInstr & | MI, |
| ArrayRef< unsigned > | Ops, | ||
| MachineInstr & | LoadMI, | ||
| LiveIntervals * | LIS = nullptr |
||
| ) | const |
Same as the previous version except it allows folding of any load and store from / to any address, not just from a specific stack slot.
Definition at line 611 of file TargetInstrInfo.cpp.
References llvm::MachineInstr::addMemOperand(), assert(), llvm::MachineInstr::canFoldAsLoad(), E, foldMemoryOperandImpl(), foldPatchpoint(), llvm::ISD::FrameIndex, llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), I, isLoadFromStackSlot(), llvm::MachineOperand::isUse(), llvm::MachineInstr::memoperands(), llvm::MachineInstr::memoperands_begin(), llvm::MachineInstr::memoperands_empty(), llvm::MachineInstr::memoperands_end(), and llvm::MachineInstr::setMemRefs().
◆ foldMemoryOperandImpl() [1/2]
|
inlineprotectedvirtual |
Target-dependent implementation for foldMemoryOperand.
Target-independent code in foldMemoryOperand will take care of adding a MachineMemOperand to the newly created instruction. The instruction and any auxiliary instructions necessary will be inserted at InsertPt.
Definition at line 1018 of file TargetInstrInfo.h.
Referenced by foldMemoryOperand(), and llvm::AArch64InstrInfo::isSubregFoldable().
◆ foldMemoryOperandImpl() [2/2]
|
inlineprotectedvirtual |
Target-dependent implementation for foldMemoryOperand.
Target-independent code in foldMemoryOperand will take care of adding a MachineMemOperand to the newly created instruction. The instruction and any auxiliary instructions necessary will be inserted at InsertPt.
Definition at line 1030 of file TargetInstrInfo.h.
◆ genAlternativeCodeSequence()
|
virtual |
When getMachineCombinerPatterns() finds patterns, this function generates the instructions that could replace the original code sequence.
The client has to decide whether the actual replacement is beneficial or not.
- Parameters
-
Root - Instruction that could be combined with one of its operands Pattern - Combination pattern for Root InsInstrs - Vector of new instructions that implement P DelInstrs - Old instructions, including Root, that could be replaced by InsInstr InstIdxForVirtReg - map of virtual register to instruction in InsInstr that defines it
Definition at line 847 of file TargetInstrInfo.cpp.
References assert(), llvm::MachineFunction::getFrameInfo(), llvm::MachineInstr::getMF(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), llvm::MachineOperand::getSubReg(), llvm::MachineRegisterInfo::getUniqueVRegDef(), llvm::MachineInstr::hasUnmodeledSideEffects(), llvm::MachineRegisterInfo::isConstantPhysReg(), llvm::MachineOperand::isDef(), llvm::MachineInstr::isDereferenceableInvariantLoad(), llvm::MachineFrameInfo::isImmutableObjectIndex(), llvm::MachineInstr::isInlineAsm(), isLoadFromStackSlot(), llvm::MachineInstr::isNotDuplicable(), llvm::TargetRegisterInfo::isPhysicalRegister(), llvm::MachineOperand::isReg(), llvm::MachineOperand::isUse(), llvm::TargetRegisterInfo::isVirtualRegister(), llvm::MachineInstr::mayLoad(), llvm::MachineInstr::mayStore(), MI, MRI, llvm::MachineInstr::readsVirtualRegister(), llvm::REASSOC_AX_BY, llvm::REASSOC_AX_YB, llvm::REASSOC_XA_BY, llvm::REASSOC_XA_YB, reassociateOps(), and Reg.
Referenced by llvm::AArch64InstrInfo::genAlternativeCodeSequence(), and isAssociativeAndCommutative().
◆ getAddressSpaceForPseudoSourceKind()
|
inlinevirtual |
getAddressSpaceForPseudoSourceKind - Given the kind of memory (e.g.
stack) the target returns the corresponding address space.
Definition at line 1084 of file TargetInstrInfo.h.
Referenced by llvm::PseudoSourceValue::PseudoSourceValue().
◆ getBaseAndOffsetPosition()
|
inlinevirtual |
Return true if the instruction contains a base register and offset.
If true, the function also sets the operand position in the instruction for the base register and offset.
Definition at line 1150 of file TargetInstrInfo.h.
Referenced by llvm::SwingSchedulerDAG::applyInstrChange(), llvm::SwingSchedulerDAG::fixupRegisterOverlaps(), and removePhis().
◆ getBranchDestBlock()
|
inlinevirtual |
- Returns
- The block that branch instruction
MIjumps to.
Definition at line 523 of file TargetInstrInfo.h.
References llvm_unreachable.
◆ getCallFrameDestroyOpcode()
|
inline |
Definition at line 162 of file TargetInstrInfo.h.
Referenced by llvm::MachineFrameInfo::computeMaxCallFrameSize(), createPHIsForCMOVsInSinkBB(), FindCallSeqStart(), getComparePred(), getSPAdjust(), IsChainDependent(), isFrameInstr(), and matchPair().
◆ getCallFrameSetupOpcode()
|
inline |
These methods return the opcode of the frame setup/destroy instructions if they exist (-1 otherwise).
Some targets use pseudo instructions in order to abstract away the difference between operating with a frame pointer and operating without, through the use of these two instructions.
Definition at line 161 of file TargetInstrInfo.h.
Referenced by llvm::MachineFrameInfo::computeMaxCallFrameSize(), createPHIsForCMOVsInSinkBB(), FindCallSeqStart(), getComparePred(), getSPAdjust(), IsChainDependent(), isFrameInstr(), isFrameSetup(), and matchPair().
◆ getCatchReturnOpcode()
|
inline |
Definition at line 201 of file TargetInstrInfo.h.
Referenced by llvm::getEHScopeMembership().
◆ getExecutionDomain()
|
inlinevirtual |
Return the current execution domain and bit mask of possible domains for instruction.
Some micro-architectures have multiple execution domains, and multiple opcodes that perform the same operation in different domains. For example, the x86 architecture provides the por, orps, and orpd instructions that all do the same thing. There is a latency penalty if a register is written in one domain and read in another.
This function returns a pair (domain, mask) containing the execution domain of MI, and a bit mask of possible domains. The setExecutionDomain function can be used to change the opcode to one of the domains in the bit mask. Instructions whose execution domain can't be changed should return a 0 mask.
The execution domain numbers don't have any special meaning except domain 0 is used for instructions that are not associated with any interesting execution domain.
Definition at line 1431 of file TargetInstrInfo.h.
◆ getExtractSubregInputs()
| bool TargetInstrInfo::getExtractSubregInputs | ( | const MachineInstr & | MI, |
| unsigned | DefIdx, | ||
| RegSubRegPairAndIdx & | InputReg | ||
| ) | const |
Build the equivalent inputs of a EXTRACT_SUBREG for the given MI and DefIdx.
[out] InputReg of the equivalent EXTRACT_SUBREG. E.g., EXTRACT_SUBREG %1:sub1, sub0, sub1 would produce:
- %1:sub1, sub0
- Returns
- true if it is possible to build such an input sequence with the pair
MI,DefIdxand the operand has no undef flag set. False otherwise.
- Precondition
- MI.isExtractSubreg() or MI.isExtractSubregLike().
- Note
- The generic implementation does not provide any support for MI.isExtractSubregLike(). In other words, one has to override getExtractSubregLikeInputs for target specific instructions.
Definition at line 1169 of file TargetInstrInfo.cpp.
References assert(), getExtractSubregLikeInputs(), llvm::MachineOperand::getImm(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::getSubReg(), llvm::MachineInstr::isExtractSubreg(), llvm::MachineInstr::isExtractSubregLike(), llvm::MachineOperand::isImm(), llvm::MachineOperand::isUndef(), llvm::TargetInstrInfo::RegSubRegPair::Reg, llvm::TargetInstrInfo::RegSubRegPairAndIdx::SubIdx, and llvm::TargetInstrInfo::RegSubRegPair::SubReg.
Referenced by isVirtualRegisterOperand(), and llvm::TargetInstrInfo::RegSubRegPairAndIdx::RegSubRegPairAndIdx().
◆ getExtractSubregLikeInputs()
|
inlineprotectedvirtual |
Target-dependent implementation of getExtractSubregInputs.
- Returns
- true if it is possible to build the equivalent EXTRACT_SUBREG inputs with the pair
MI,DefIdx. False otherwise.
- Precondition
- MI.isExtractSubregLike().
Definition at line 1059 of file TargetInstrInfo.h.
Referenced by getExtractSubregInputs().
◆ getFrameSize()
|
inline |
Returns size of the frame associated with the given frame instruction.
For frame setup instruction this is frame that is set up space set up after the instruction. For frame destroy instruction this is the frame freed by the caller. Note, in some cases a call frame (or a part of it) may be prepared prior to the frame setup instruction. It occurs in the calls that involve inalloca arguments. This function reports only the size of the frame part that is set up between the frame setup and destroy pseudo instructions.
Definition at line 183 of file TargetInstrInfo.h.
References assert(), llvm::MachineOperand::getImm(), llvm::MachineInstr::getOperand(), and isFrameInstr().
Referenced by llvm::MachineFrameInfo::computeMaxCallFrameSize(), getFrameTotalSize(), and getSPAdjust().
◆ getFrameTotalSize()
|
inline |
Returns the total frame size, which is made up of the space set up inside the pair of frame start-stop instructions and the space that is set up prior to the pair.
Definition at line 192 of file TargetInstrInfo.h.
References assert(), getFrameSize(), llvm::MachineOperand::getImm(), llvm::MachineInstr::getOperand(), and isFrameSetup().
Referenced by matchPair().
◆ getIncrementValue()
|
inlinevirtual |
If the instruction is an increment of a constant value, return the amount.
Definition at line 1157 of file TargetInstrInfo.h.
Referenced by llvm::SwingSchedulerDAG::isLoopCarriedDep(), and removePhis().
◆ getInlineAsmLength()
|
virtual |
Measure the specified inline asm to determine an approximation of its length.
Comments (which run till the next SeparatorString or newline) do not count as an instruction. Any other non-whitespace text is considered an instruction, with multiple instructions separated by SeparatorString or newlines. Variable-length instructions are not handled here; this function may be overloaded in the target code to do that. We implement a special case of the .space directive which takes only a single integer argument in base 10 that is the size in bytes. This is a restricted form of the GAS directive in that we only interpret simple–i.e. not a logical or arithmetic expression–size values without the optional fill value. This is primarily used for creating arbitrary sized inline asm blocks for testing purposes.
Definition at line 89 of file TargetInstrInfo.cpp.
References llvm::MCAsmInfo::getMaxInstLength(), llvm::MCAsmInfo::getSeparatorString(), and isAsmComment().
Referenced by llvm::MSP430InstrInfo::getInstSizeInBytes(), and isSafeToMoveRegClassDefs().
◆ getInsertSubregInputs()
| bool TargetInstrInfo::getInsertSubregInputs | ( | const MachineInstr & | MI, |
| unsigned | DefIdx, | ||
| RegSubRegPair & | BaseReg, | ||
| RegSubRegPairAndIdx & | InsertedReg | ||
| ) | const |
Build the equivalent inputs of a INSERT_SUBREG for the given MI and DefIdx.
[out] BaseReg and [out] InsertedReg contain the equivalent inputs of INSERT_SUBREG. E.g., INSERT_SUBREG %0:sub0, %1:sub1, sub3 would produce:
- BaseReg: %0:sub0
- InsertedReg: %1:sub1, sub3
- Returns
- true if it is possible to build such an input sequence with the pair
MI,DefIdxand the operand has no undef flag set. False otherwise.
- Precondition
- MI.isInsertSubreg() or MI.isInsertSubregLike().
- Note
- The generic implementation does not provide any support for MI.isInsertSubregLike(). In other words, one has to override getInsertSubregLikeInputs for target specific instructions.
Definition at line 1194 of file TargetInstrInfo.cpp.
References assert(), llvm::MachineOperand::getImm(), getInsertSubregLikeInputs(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::getSubReg(), llvm::MachineOperand::isImm(), llvm::MachineInstr::isInsertSubreg(), llvm::MachineInstr::isInsertSubregLike(), llvm::MachineOperand::isUndef(), llvm::TargetInstrInfo::RegSubRegPair::Reg, llvm::TargetInstrInfo::RegSubRegPairAndIdx::SubIdx, and llvm::TargetInstrInfo::RegSubRegPair::SubReg.
Referenced by isVirtualRegisterOperand(), and llvm::TargetInstrInfo::RegSubRegPairAndIdx::RegSubRegPairAndIdx().
◆ getInsertSubregLikeInputs()
|
inlineprotectedvirtual |
Target-dependent implementation of getInsertSubregInputs.
- Returns
- true if it is possible to build the equivalent INSERT_SUBREG inputs with the pair
MI,DefIdx. False otherwise.
- Precondition
- MI.isInsertSubregLike().
Definition at line 1074 of file TargetInstrInfo.h.
Referenced by getInsertSubregInputs().
◆ getInstrLatency() [1/2]
|
virtual |
Compute the instruction latency of a given instruction.
If the instruction has higher cost when predicated, it's returned via PredCost.
Definition at line 1091 of file TargetInstrInfo.cpp.
References llvm::MachineInstr::getDesc(), llvm::MCInstrDesc::getSchedClass(), llvm::InstrItineraryData::getStageLatency(), and llvm::MachineInstr::mayLoad().
Referenced by computeDefOperandLatency(), llvm::TargetSchedModel::computeInstrLatency(), llvm::ScheduleDAGSDNodes::computeLatency(), llvm::TargetSchedModel::computeOperandLatency(), isZeroCost(), and regOverlapsSet().
◆ getInstrLatency() [2/2]
|
virtual |
Definition at line 1045 of file TargetInstrInfo.cpp.
References llvm::SDNode::getMachineOpcode(), llvm::InstrItineraryData::getStageLatency(), llvm::InstrItineraryData::isEmpty(), and llvm::SDNode::isMachineOpcode().
◆ getInstSizeInBytes()
|
inlinevirtual |
Returns the size in bytes of the specified MachineInstr, or ~0U when this function is not implemented by a target.
Definition at line 323 of file TargetInstrInfo.h.
Referenced by INITIALIZE_PASS().
◆ getMachineCombinerPatterns()
|
virtual |
Return true when there is potentially a faster code sequence for an instruction chain ending in Root.
All potential patterns are returned in the Pattern vector. Pattern should be sorted in priority order since the pattern evaluator stops checking as soon as it finds a faster sequence.
- Parameters
-
Root - Instruction that could be combined with one of its operands Patterns - Vector of possible combination patterns
Definition at line 733 of file TargetInstrInfo.cpp.
References isReassociationCandidate(), llvm::SmallVectorTemplateBase< T >::push_back(), llvm::REASSOC_AX_BY, llvm::REASSOC_AX_YB, llvm::REASSOC_XA_BY, and llvm::REASSOC_XA_YB.
Referenced by llvm::AArch64InstrInfo::getMachineCombinerPatterns(), llvm::PPCInstrInfo::getMachineCombinerPatterns(), and isSubregFoldable().
◆ getMachineCSELookAheadLimit()
|
inlinevirtual |
Return the value to use for the MachineCSE's LookAheadLimit, which is a heuristic used for CSE'ing phys reg defs.
Definition at line 1556 of file TargetInstrInfo.h.
◆ getMemOperandWithOffset()
|
inlinevirtual |
Get the base operand and byte offset of an instruction that reads/writes memory.
Definition at line 1141 of file TargetInstrInfo.h.
Referenced by AnyAliasLiveIn(), getUnderlyingObjects(), llvm::SwingSchedulerDAG::isLoopCarriedDep(), removePhis(), and SinkingPreventsImplicitNullCheck().
◆ getNoop()
|
virtual |
Return the noop instruction to use for a noop.
Definition at line 457 of file TargetInstrInfo.cpp.
References llvm_unreachable.
Referenced by reverseBranchCondition().
◆ getNumMicroOps()
|
virtual |
Return the number of u-operations the given machine instruction will be decoded to on the target cpu.
The itinerary's IssueWidth is the number of microops that can be dispatched each cycle. An instruction with zero microops takes no dispatch resources.
Definition at line 1060 of file TargetInstrInfo.cpp.
References llvm::MachineInstr::getDesc(), llvm::MCInstrDesc::getSchedClass(), llvm::InstrItineraryData::isEmpty(), llvm::InstrItineraryData::Itineraries, and llvm::InstrItinerary::NumMicroOps.
Referenced by FoldImmediate(), and llvm::TargetSchedModel::getNumMicroOps().
◆ getOpcodeAfterMemoryUnfold()
|
inlinevirtual |
Returns the opcode of the would be new instruction after load / store are unfolded from an instruction of the specified opcode.
It returns zero if the specified unfolding is not possible. If LoadRegIndex is non-null, it is filled in with the operand index of the operand which will hold the register holding the loaded value.
Definition at line 1110 of file TargetInstrInfo.h.
Referenced by isCopyFeedingInvariantStore().
◆ getOperandLatency() [1/2]
|
virtual |
Definition at line 1029 of file TargetInstrInfo.cpp.
References llvm::SDNode::getMachineOpcode(), llvm::InstrItineraryData::getOperandCycle(), llvm::InstrItineraryData::getOperandLatency(), llvm::InstrItineraryData::isEmpty(), and llvm::SDNode::isMachineOpcode().
Referenced by llvm::ScheduleDAGSDNodes::computeOperandLatency(), llvm::TargetSchedModel::computeOperandLatency(), llvm::HexagonInstrInfo::getOperandLatency(), and isZeroCost().
◆ getOperandLatency() [2/2]
|
virtual |
Compute and return the use operand latency of a given pair of def and use.
Both DefMI and UseMI must be valid.
In most cases, the static scheduling itinerary was enough to determine the operand latency. But it may not be possible for instructions with variable number of defs / uses.
This is a raw interface to the itinerary that may be directly overridden by a target. Use computeOperandLatency to get the best estimate of latency.
By default, call directly to the itinerary. This may be overriden by the target.
Definition at line 1116 of file TargetInstrInfo.cpp.
References llvm::MachineInstr::getDesc(), llvm::InstrItineraryData::getOperandLatency(), and llvm::MCInstrDesc::getSchedClass().
◆ getOutliningCandidateInfo()
|
inlinevirtual |
Returns a outliner::OutlinedFunction struct containing target-specific information for a set of outlining candidates.
Definition at line 1625 of file TargetInstrInfo.h.
References llvm_unreachable.
Referenced by INITIALIZE_PASS().
◆ getOutliningType()
|
inlinevirtual |
Returns how or if MI should be outlined.
Definition at line 1633 of file TargetInstrInfo.h.
References llvm_unreachable.
◆ getPartialRegUpdateClearance()
|
inlinevirtual |
Returns the preferred minimum clearance before an instruction with an unwanted partial register update.
Some instructions only write part of a register, and implicitly need to read the other parts of the register. This may cause unwanted stalls preventing otherwise unrelated instructions from executing in parallel in an out-of-order CPU.
For example, the x86 instruction cvtsi2ss writes its result to bits [31:0] of the destination xmm register. Bits [127:32] are unaffected, so the instruction needs to wait for the old value of the register to become available:
addps xmm1, xmm0 movaps xmm0, (rax) cvtsi2ss rbx, xmm0
In the code above, the cvtsi2ss instruction needs to wait for the addps instruction before it can issue, even though the high bits of xmm0 probably aren't needed.
This hook returns the preferred clearance before MI, measured in instructions. Other defs of MI's operand OpNum are avoided in the last N instructions before MI. It should only return a positive value for unwanted dependencies. If the old bits of the defined register have useful values, or if MI is determined to otherwise read the dependency, the hook should return 0.
The unwanted dependency may be handled by:
- Allocating the same register for an MI def and use. That makes the unwanted dependency identical to a required dependency.
- Allocating a register for the def that has no defs in the previous N instructions.
- Calling breakPartialRegDependency() with the same arguments. This allows the target to insert a dependency breaking instruction.
Definition at line 1481 of file TargetInstrInfo.h.
Referenced by llvm::createBreakFalseDeps().
◆ getPredicationCost()
|
virtual |
Definition at line 1087 of file TargetInstrInfo.cpp.
Referenced by isZeroCost(), and MaySpeculate().
◆ getRegClass()
| const TargetRegisterClass * TargetInstrInfo::getRegClass | ( | const MCInstrDesc & | MCID, |
| unsigned | OpNum, | ||
| const TargetRegisterInfo * | TRI, | ||
| const MachineFunction & | MF | ||
| ) | const |
Given a machine instruction descriptor, returns the register class constraint for OpNum, or NULL.
Definition at line 45 of file TargetInstrInfo.cpp.
References llvm::MCInstrDesc::getNumOperands(), llvm::TargetRegisterInfo::getPointerRegClass(), llvm::TargetRegisterInfo::getRegClass(), llvm::MCOperandInfo::isLookupPtrRegClass(), llvm::MCInstrDesc::OpInfo, and llvm::MCOperandInfo::RegClass.
Referenced by llvm::constrainOperandRegClass(), llvm::FastISel::constrainOperandRegClass(), llvm::createBreakFalseDeps(), CriticalPathStep(), definesFullReg(), llvm::MachineInstr::getRegClassConstraint(), isCopyFeedingInvariantStore(), isGenericOpcode(), matchPair(), llvm::ARMBaseRegisterInfo::materializeFrameBaseRegister(), parseCond(), and updateOperandRegConstraints().
◆ getRegSequenceInputs()
| bool TargetInstrInfo::getRegSequenceInputs | ( | const MachineInstr & | MI, |
| unsigned | DefIdx, | ||
| SmallVectorImpl< RegSubRegPairAndIdx > & | InputRegs | ||
| ) | const |
Build the equivalent inputs of a REG_SEQUENCE for the given MI and DefIdx.
[out] InputRegs of the equivalent REG_SEQUENCE. Each element of the list is modeled as <Reg:SubReg, SubIdx>. Operands with the undef flag are not added to this list. E.g., REG_SEQUENCE %1:sub1, sub0, %2, sub1 would produce two elements:
- %1:sub1, sub0
- %2<:0>, sub1
- Returns
- true if it is possible to build such an input sequence with the pair
MI,DefIdx. False otherwise.
- Precondition
- MI.isRegSequence() or MI.isRegSequenceLike().
- Note
- The generic implementation does not provide any support for MI.isRegSequenceLike(). In other words, one has to override getRegSequenceLikeInputs for target specific instructions.
Definition at line 1142 of file TargetInstrInfo.cpp.
References assert(), llvm::MachineOperand::getImm(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), getRegSequenceLikeInputs(), llvm::MachineOperand::getSubReg(), llvm::MachineOperand::isImm(), llvm::MachineInstr::isRegSequence(), llvm::MachineInstr::isRegSequenceLike(), llvm::MachineOperand::isUndef(), and llvm::SmallVectorTemplateBase< T >::push_back().
Referenced by isVirtualRegisterOperand(), and llvm::TargetInstrInfo::RegSubRegPairAndIdx::RegSubRegPairAndIdx().
◆ getRegSequenceLikeInputs()
|
inlineprotectedvirtual |
Target-dependent implementation of getRegSequenceInputs.
- Returns
- true if it is possible to build the equivalent REG_SEQUENCE inputs with the pair
MI,DefIdx. False otherwise.
- Precondition
- MI.isRegSequenceLike().
Definition at line 1045 of file TargetInstrInfo.h.
Referenced by getRegSequenceInputs().
◆ getReturnOpcode()
|
inline |
Definition at line 202 of file TargetInstrInfo.h.
References getSPAdjust().
◆ getSerializableBitmaskMachineOperandTargetFlags()
|
inlinevirtual |
Return an array that contains the bitmask target flag values and their names.
MIR Serialization is able to serialize only the target flags that are defined by this method.
Definition at line 1595 of file TargetInstrInfo.h.
References llvm::None.
◆ getSerializableDirectMachineOperandTargetFlags()
|
inlinevirtual |
Return an array that contains the direct target flag values and their names.
MIR Serialization is able to serialize only the target flags that are defined by this method.
Definition at line 1585 of file TargetInstrInfo.h.
References llvm::None.
Referenced by getTargetFlagName().
◆ getSerializableMachineMemOperandTargetFlags()
|
inlinevirtual |
Return an array that contains the MMO target flag values and their names.
MIR Serialization is able to serialize only the MMO target flags that are defined by this method.
Definition at line 1605 of file TargetInstrInfo.h.
References llvm::None.
Referenced by getTargetMMOFlagName().
◆ getSerializableTargetIndices()
|
inlinevirtual |
Return an array that contains the ids of the target indices (used for the TargetIndex machine operand) and their names.
MIR Serialization is able to serialize only the target indices that are defined by this method.
Definition at line 1568 of file TargetInstrInfo.h.
References llvm::None.
◆ getSPAdjust()
|
virtual |
Returns the actual stack pointer adjustment made by an instruction as part of a call sequence.
By default, only call frame setup/destroy instructions adjust the stack, but targets may want to override this to enable more fine-grained adjustment, or adjust by a different value.
Definition at line 953 of file TargetInstrInfo.cpp.
References llvm::TargetFrameLowering::alignSPAdjust(), getCallFrameDestroyOpcode(), getCallFrameSetupOpcode(), llvm::TargetSubtargetInfo::getFrameLowering(), getFrameSize(), llvm::MachineInstr::getMF(), llvm::MachineInstr::getOpcode(), llvm::TargetFrameLowering::getStackGrowthDirection(), llvm::MachineFunction::getSubtarget(), isFrameInstr(), and llvm::TargetFrameLowering::StackGrowsDown.
Referenced by getReturnOpcode().
◆ getStackSlotRange()
|
virtual |
Compute the size in bytes and offset within a stack slot of a spilled register or subregister.
- Parameters
-
[out] Size in bytes of the spilled value. [out] Offset in bytes within the stack slot.
- Returns
- true if both Size and Offset are successfully computed.
Not all subregisters have computable spill slots. For example, subregisters registers may not be byte-sized, and a pair of discontiguous subregisters has no single offset.
Targets with nontrivial bigendian implementations may need to override this, particularly to support spilled vector registers.
Definition at line 370 of file TargetInstrInfo.cpp.
References assert(), llvm::MachineFunction::getDataLayout(), llvm::TargetSubtargetInfo::getRegisterInfo(), llvm::TargetRegisterInfo::getSpillSize(), llvm::MCRegisterInfo::getSubRegIdxOffset(), llvm::MCRegisterInfo::getSubRegIdxSize(), llvm::MachineFunction::getSubtarget(), llvm::DataLayout::isLittleEndian(), Size, and TRI.
Referenced by foldPatchpoint(), isStackSlotCopy(), and llvm::LiveDebugVariables::splitRegister().
◆ getUndefRegClearance()
|
inlinevirtual |
Return the minimum clearance before an instruction that reads an unused register.
For example, AVX instructions may copy part of a register operand into the unused high bits of the destination register.
vcvtsi2sdq rax, undef xmm0, xmm14
In the code above, vcvtsi2sdq copies xmm0[127:64] into xmm14 creating a false dependence on any previous write to xmm0.
This hook works similarly to getPartialRegUpdateClearance, except that it does not take an operand index. Instead sets OpNum to the index of the unused register.
Definition at line 1501 of file TargetInstrInfo.h.
Referenced by llvm::createBreakFalseDeps().
◆ hasHighOperandLatency()
|
inlinevirtual |
Compute operand latency between a def of 'Reg' and a use in the current loop.
Return true if the target considered it 'high'. This is used by optimization passes such as machine LICM to determine whether it makes sense to hoist an instruction out even in a high register pressure situation.
Definition at line 1391 of file TargetInstrInfo.h.
References hasLowDefLatency().
Referenced by isCopyFeedingInvariantStore().
◆ hasLoadFromStackSlot()
|
virtual |
If the specified machine instruction has a load from a stack slot, return true along with the FrameIndices of the loaded stack slot and the machine mem operands containing the reference.
If not, return false. Unlike isLoadFromStackSlot, this returns true for any instructions that loads from the stack. This is just a hint, as some cases may be missed.
Definition at line 342 of file TargetInstrInfo.cpp.
References llvm::MachineInstr::memoperands_begin(), llvm::MachineInstr::memoperands_end(), llvm::SmallVectorTemplateBase< T >::push_back(), and llvm::SmallVectorBase::size().
Referenced by emitComments(), llvm::HexagonInstrInfo::hasLoadFromStackSlot(), and isLoadFromStackSlotPostFE().
◆ hasLowDefLatency()
|
virtual |
Compute operand latency of a def of 'Reg'.
Return true if the target considered it 'low'.
Definition at line 1102 of file TargetInstrInfo.cpp.
References llvm::MachineInstr::getDesc(), llvm::TargetSchedModel::getInstrItineraries(), llvm::InstrItineraryData::getOperandCycle(), llvm::MCInstrDesc::getSchedClass(), and llvm::InstrItineraryData::isEmpty().
Referenced by hasHighOperandLatency(), and isCopyFeedingInvariantStore().
◆ hasReassociableOperands()
|
virtual |
Return true when Inst has reassociable operands in the same MBB.
Definition at line 659 of file TargetInstrInfo.cpp.
References llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), llvm::MachineRegisterInfo::getUniqueVRegDef(), llvm::MachineOperand::isReg(), llvm::TargetRegisterInfo::isVirtualRegister(), and MRI.
Referenced by llvm::X86InstrInfo::hasReassociableOperands(), hasReassociableSibling(), isAssociativeAndCommutative(), and isReassociationCandidate().
◆ hasReassociableSibling()
| bool TargetInstrInfo::hasReassociableSibling | ( | const MachineInstr & | Inst, |
| bool & | Commuted | ||
| ) | const |
Return true when Inst has reassociable sibling.
Definition at line 678 of file TargetInstrInfo.cpp.
References llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), llvm::MachineRegisterInfo::getUniqueVRegDef(), llvm::MachineRegisterInfo::hasOneNonDBGUse(), hasReassociableOperands(), MRI, and std::swap().
Referenced by isAssociativeAndCommutative(), and isReassociationCandidate().
◆ hasStoreToStackSlot()
|
virtual |
If the specified machine instruction has a store to a stack slot, return true along with the FrameIndices of the loaded stack slot and the machine mem operands containing the reference.
If not, return false. Unlike isStoreToStackSlot, this returns true for any instructions that stores to the stack. This is just a hint, as some cases may be missed.
Definition at line 356 of file TargetInstrInfo.cpp.
References llvm::MachineInstr::memoperands_begin(), llvm::MachineInstr::memoperands_end(), llvm::SmallVectorTemplateBase< T >::push_back(), and llvm::SmallVectorBase::size().
Referenced by emitComments(), llvm::HexagonInstrInfo::hasStoreToStackSlot(), and isStoreToStackSlotPostFE().
◆ insertBranch()
|
inlinevirtual |
Insert branch code into the end of the specified MachineBasicBlock.
The operands to this method are the same as those returned by AnalyzeBranch. This is only invoked in cases where AnalyzeBranch returns success. It returns the number of instructions inserted. If BytesAdded is non-null, report the change in code size from the added instructions.
It is also invoked by tail merging to add unconditional branches in cases where AnalyzeBranch doesn't apply because there was no original branch to analyze. At least this much must be implemented, else tail merging needs to be disabled.
The CFG information in MBB.Predecessors and MBB.Successors must be valid before calling this function.
Definition at line 638 of file TargetInstrInfo.h.
References llvm_unreachable.
Referenced by AnyAliasLiveIn(), bothUsedInPHI(), findFalseBlock(), FixTail(), getLayoutSuccessorProbThreshold(), InsertUncondBranch(), insertUnconditionalBranch(), isIntersect(), mergeOperations(), removePhis(), ReplaceTailWithBranchTo(), salvageDebugInfoFromEmptyBlock(), llvm::MachineBasicBlock::SplitCriticalEdge(), UpdatePredRedefs(), and llvm::MachineBasicBlock::updateTerminator().
◆ insertIndirectBranch()
|
inlinevirtual |
Insert an unconditional indirect branch at the end of MBB to NewDestBB.
BrOffset indicates the offset of NewDestBB relative to the offset of the position to insert the new branch.
- Returns
- The number of bytes added to the block.
Definition at line 532 of file TargetInstrInfo.h.
References llvm_unreachable.
◆ insertNoop()
|
virtual |
Insert a noop into the instruction stream at the specified point.
insertNoop - Insert a noop into the instruction stream at the specified point.
Definition at line 65 of file TargetInstrInfo.cpp.
References llvm_unreachable.
Referenced by llvm::ScheduleDAGSDNodes::EmitSchedule(), INITIALIZE_PASS(), and reverseBranchCondition().
◆ insertOutlinedCall()
|
inlinevirtual |
Insert a call to an outlined function into the program.
Returns an iterator to the spot where we inserted the call. This must be implemented by the target.
Definition at line 1656 of file TargetInstrInfo.h.
References llvm_unreachable.
Referenced by INITIALIZE_PASS().
◆ insertSelect()
|
inlinevirtual |
Insert a select instruction into MBB before I that will copy TrueReg to DstReg when Cond is true, and FalseReg to DstReg when Cond is false.
This function can only be called after canInsertSelect() returned true. The condition in Cond comes from AnalyzeBranch, and it can be assumed that the same flags or registers required by Cond are available at the insertion point.
- Parameters
-
MBB Block where select instruction should be inserted. I Insertion point. DL Source location for debugging. DstReg Virtual register to be defined by select instruction. Cond Condition as computed by AnalyzeBranch. TrueReg Virtual register to copy when Cond is true. FalseReg Virtual register to copy when Cons is false.
Definition at line 779 of file TargetInstrInfo.h.
References llvm_unreachable.
Referenced by llvm::PPCTargetLowering::EmitInstrWithCustomInserter().
◆ insertUnconditionalBranch()
|
inline |
Definition at line 646 of file TargetInstrInfo.h.
References insertBranch().
◆ isAsCheapAsAMove()
|
inlinevirtual |
Return true if the instruction is as cheap as a move instruction.
Targets for different archs need to override this, and different micro-architectures can also be finely tuned inside.
Definition at line 331 of file TargetInstrInfo.h.
References llvm::MachineInstr::isAsCheapAsAMove().
Referenced by definesFullReg(), isCallerPreservedOrConstPhysReg(), and isCopyFeedingInvariantStore().
◆ isAssociativeAndCommutative()
|
inlinevirtual |
Return true when Inst is both associative and commutative.
Definition at line 963 of file TargetInstrInfo.h.
References genAlternativeCodeSequence(), hasReassociableOperands(), hasReassociableSibling(), and reassociateOps().
Referenced by isReassociationCandidate().
◆ isBasicBlockPrologue()
|
inlinevirtual |
True if the instruction is bound to the top of its basic block and no other instructions shall be inserted before it.
This can be implemented to prevent register allocator to insert spills before such instructions.
Definition at line 1619 of file TargetInstrInfo.h.
Referenced by llvm::MachineBasicBlock::SkipPHIsAndLabels(), and llvm::MachineBasicBlock::SkipPHIsLabelsAndDebug().
◆ isBranchOffsetInRange()
|
inlinevirtual |
- Returns
- true if a branch from an instruction with opcode
BranchOpcbytes is capable of jumping to a positionBrOffsetbytes away.
Definition at line 517 of file TargetInstrInfo.h.
References llvm_unreachable.
◆ isCoalescableExtInstr()
|
inlinevirtual |
Return true if the instruction is a "coalescable" extension instruction.
That is, it's like a copy where it's legal for the source to overlap the destination. e.g. X86::MOVSX64rr32. If this returns true, then it's expected the pre-extension value is available as a subreg of the result register. This also returns the sub-register index in SubIdx.
Definition at line 215 of file TargetInstrInfo.h.
◆ isCopyInstr()
|
inline |
If the specific machine instruction is a instruction that moves/copies value from one register to another register return true along with machine operand and machine operand.
For COPY-instruction the method naturally returns true, for all other instructions the method calls target-dependent implementation.
Definition at line 866 of file TargetInstrInfo.h.
References llvm::MachineInstr::getOperand(), llvm::MachineInstr::isCopy(), and isCopyInstrImpl().
◆ isCopyInstrImpl()
|
inlineprotectedvirtual |
Target-dependent implemenation for IsCopyInstr.
If the specific machine instruction is a instruction that moves/copies value from one register to another register return true along with machine operand and machine operand.
Definition at line 854 of file TargetInstrInfo.h.
Referenced by isCopyInstr().
◆ isFrameInstr()
|
inline |
Returns true if the argument is a frame pseudo instruction.
Definition at line 165 of file TargetInstrInfo.h.
References getCallFrameDestroyOpcode(), getCallFrameSetupOpcode(), and llvm::MachineInstr::getOpcode().
Referenced by getFrameSize(), and getSPAdjust().
◆ isFrameSetup()
|
inline |
Returns true if the argument is a frame setup pseudo instruction.
Definition at line 171 of file TargetInstrInfo.h.
References getCallFrameSetupOpcode(), and llvm::MachineInstr::getOpcode().
Referenced by getFrameTotalSize().
◆ isFunctionSafeToOutlineFrom()
|
inlinevirtual |
Return true if the function can safely be outlined from.
A function MF is considered safe for outlining if an outlined function produced from instructions in F will produce a program which produces the same output for any set of given inputs.
Definition at line 1667 of file TargetInstrInfo.h.
References llvm_unreachable.
Referenced by INITIALIZE_PASS().
◆ isGenericOpcode()
Definition at line 78 of file TargetInstrInfo.h.
References getRegClass(), and TRI.
◆ isHighLatencyDef()
|
inlinevirtual |
Return true if this opcode has high latency to its result.
Definition at line 1384 of file TargetInstrInfo.h.
Referenced by llvm::ScheduleDAGSDNodes::computeLatency(), and defaultDefLatency().
◆ isLegalToSplitMBBAt()
|
inlinevirtual |
Return true if it's legal to split the given basic block at the specified instruction (i.e.
instruction would be the start of a new basic block).
Definition at line 682 of file TargetInstrInfo.h.
Referenced by ComputeCommonTailLength().
◆ isLoadFromStackSlot() [1/2]
|
inlinevirtual |
If the specified machine instruction is a direct load from a stack slot, return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot.
If not, return 0. This predicate must return 0 if the instruction has any side effects other than loading from the stack slot.
Definition at line 225 of file TargetInstrInfo.h.
Referenced by foldMemoryOperand(), genAlternativeCodeSequence(), InstructionStoresToFI(), isLoadFromStackSlot(), MatchingStackOffset(), and false::IntervalSorter::operator()().
◆ isLoadFromStackSlot() [2/2]
|
inlinevirtual |
Optional extension of isLoadFromStackSlot that returns the number of bytes loaded from the stack.
This must be implemented if a backend supports partial stack slot spills/loads to further disambiguate what the load does.
Definition at line 234 of file TargetInstrInfo.h.
References isLoadFromStackSlot().
◆ isLoadFromStackSlotPostFE()
|
inlinevirtual |
Check for post-frame ptr elimination stack locations as well.
This uses a heuristic so it isn't reliable for correctness.
Definition at line 243 of file TargetInstrInfo.h.
References hasLoadFromStackSlot().
Referenced by emitComments().
◆ isMBBSafeToOutlineFrom()
|
inlinevirtual |
Optional target hook that returns true if MBB is safe to outline from, and returns any target-specific information in Flags.
Definition at line 1640 of file TargetInstrInfo.h.
◆ isPostIncrement()
|
inlinevirtual |
Return true for post-incremented instructions.
Definition at line 1188 of file TargetInstrInfo.h.
Referenced by removePhis().
◆ isPredicable()
|
inlinevirtual |
Return true if the specified instruction can be predicated.
By default, this returns true for every instruction with a PredicateOperand.
Definition at line 1238 of file TargetInstrInfo.h.
References llvm::MachineInstr::getDesc(), and llvm::MCInstrDesc::isPredicable().
Referenced by llvm::R600InstrInfo::isPredicable().
◆ isPredicated()
|
inlinevirtual |
Returns true if the instruction is already predicated.
Definition at line 1191 of file TargetInstrInfo.h.
References isUnpredicatedTerminator().
Referenced by llvm::TargetSchedModel::computeOutputLatency(), CriticalPathStep(), findHoistingInsertPosAndDeps(), llvm::MachineBasicBlock::getFallThrough(), isUnpredicatedTerminator(), matchPair(), MaySpeculate(), and UpdatePredRedefs().
◆ isProfitableToDupForIfCvt()
|
inlinevirtual |
Return true if it's profitable for if-converter to duplicate instructions of specified accumulated instruction latencies in the specified MBB to enable if-conversion.
The probability of the instructions being executed is given by Probability, and Confidence is a measure of our confidence that it will be properly predicted.
Definition at line 718 of file TargetInstrInfo.h.
Referenced by getNextBlock().
◆ isProfitableToIfCvt() [1/2]
|
inlinevirtual |
Return true if it's profitable to predicate instructions with accumulated instruction latency of "NumCycles" of the specified basic block, where the probability of the instructions being executed is given by Probability, and Confidence is a measure of our confidence that it will be properly predicted.
Definition at line 692 of file TargetInstrInfo.h.
◆ isProfitableToIfCvt() [2/2]
|
inlinevirtual |
Second variant of isProfitableToIfCvt.
This one checks for the case where two basic blocks from true and false path of a if-then-else (diamond) are predicated on mutally exclusive predicates, where the probability of the true path being taken is given by Probability, and Confidence is a measure of our confidence that it will be properly predicted.
Definition at line 704 of file TargetInstrInfo.h.
◆ isProfitableToUnpredicate()
|
inlinevirtual |
Return true if it's profitable to unpredicate one side of a 'diamond', i.e.
two sides of if-else predicated on mutually exclusive predicates. e.g. subeq r0, r1, #1 addne r0, r1, #1 => sub r0, r1, #1 addne r0, r1, #1
This may be profitable is conditional instructions are always executed.
Definition at line 735 of file TargetInstrInfo.h.
Referenced by UpdatePredRedefs().
◆ isReallyTriviallyReMaterializable()
|
inlineprotectedvirtual |
For instructions with opcodes for which the M_REMATERIALIZABLE flag is set, this hook lets the target specify whether the instruction is actually trivially rematerializable, taking into consideration its operands.
This predicate must return false if the instruction has any side effects other than producing a value, or if it requres any address registers that are not always available. Requirements must be check as stated in isTriviallyReMaterializable() .
Definition at line 109 of file TargetInstrInfo.h.
References commuteInstructionImpl(), fixCommutedOpIndices(), and MI.
Referenced by isTriviallyReMaterializable().
◆ isReassociationCandidate()
| bool TargetInstrInfo::isReassociationCandidate | ( | const MachineInstr & | Inst, |
| bool & | Commuted | ||
| ) | const |
Return true if the input Inst is part of a chain of dependent ops that are suitable for reassociation, otherwise return false.
If the instruction's operands must be commuted to have a previous instruction of the same type define the first source operand, Commuted will be set to true.
Definition at line 705 of file TargetInstrInfo.cpp.
References llvm::MachineInstr::getParent(), hasReassociableOperands(), hasReassociableSibling(), and isAssociativeAndCommutative().
Referenced by getMachineCombinerPatterns(), and isSubregFoldable().
◆ isSafeToMoveRegClassDefs()
|
inlinevirtual |
Return true if it's safe to move a machine instruction that defines the specified register class.
Definition at line 1244 of file TargetInstrInfo.h.
References CreateTargetHazardRecognizer(), CreateTargetMIHazardRecognizer(), CreateTargetPostRAHazardRecognizer(), getInlineAsmLength(), and isSchedulingBoundary().
◆ isSchedulingBoundary()
|
virtual |
Test if the given instruction should be considered a scheduling boundary.
isSchedulingBoundary - Test if the given instruction should be considered a scheduling boundary.
This primarily includes labels and terminators.
Definition at line 977 of file TargetInstrInfo.cpp.
References llvm::TargetSubtargetInfo::getRegisterInfo(), llvm::TargetLoweringBase::getStackPointerRegisterToSaveRestore(), llvm::MachineFunction::getSubtarget(), llvm::TargetSubtargetInfo::getTargetLowering(), llvm::MachineInstr::isPosition(), llvm::MachineInstr::isTerminator(), llvm::MachineInstr::modifiesRegister(), and TRI.
Referenced by isSafeToMoveRegClassDefs(), isSchedBoundary(), llvm::AArch64InstrInfo::isSchedulingBoundary(), and llvm::SIInstrInfo::isSchedulingBoundary().
◆ isStackSlotCopy()
|
inlinevirtual |
Return true if the specified machine instruction is a copy of one stack slot to another and has no other effect.
Provide the identity of the two frame indices.
Definition at line 299 of file TargetInstrInfo.h.
References getStackSlotRange(), and Size.
Referenced by false::IntervalSorter::operator()().
◆ isStoreToStackSlot() [1/2]
|
inlinevirtual |
If the specified machine instruction is a direct store to a stack slot, return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot.
If not, return 0. This predicate must return 0 if the instruction has any side effects other than storing to the stack slot.
Definition at line 263 of file TargetInstrInfo.h.
Referenced by isStoreToStackSlot(), and false::IntervalSorter::operator()().
◆ isStoreToStackSlot() [2/2]
|
inlinevirtual |
Optional extension of isStoreToStackSlot that returns the number of bytes stored to the stack.
This must be implemented if a backend supports partial stack slot spills/loads to further disambiguate what the store does.
Definition at line 272 of file TargetInstrInfo.h.
References isStoreToStackSlot().
◆ isStoreToStackSlotPostFE()
|
inlinevirtual |
Check for post-frame ptr elimination stack locations as well.
This uses a heuristic, so it isn't reliable for correctness.
Definition at line 281 of file TargetInstrInfo.h.
References hasStoreToStackSlot().
Referenced by emitComments().
◆ isSubregFoldable()
|
inlinevirtual |
Check whether the target can fold a load that feeds a subreg operand (or a subreg operand that feeds a store).
For example, X86 may want to return true if it can fold movl (esp), eax subb, al, ... Into: subb (esp), ...
Ideally, we'd like the target implementation of foldMemoryOperand() to reject subregs - but since this behavior used to be enforced in the target-independent code, moving this responsibility to the targets has the potential of causing nasty silent breakage in out-of-tree targets.
Definition at line 921 of file TargetInstrInfo.h.
References foldMemoryOperand(), getMachineCombinerPatterns(), isReassociationCandidate(), and isThroughputPattern().
◆ isTailCall()
|
inlinevirtual |
Determines whether Inst is a tail call instruction.
Override this method on targets that do not properly set MCID::Return and MCID::Call on tail call instructions."
Definition at line 1612 of file TargetInstrInfo.h.
References llvm::MachineInstr::isCall(), and llvm::MachineInstr::isReturn().
Referenced by llvm::DwarfDebug::shareAcrossDWOCUs().
◆ isThroughputPattern()
|
virtual |
Return true when a code sequence can improve throughput.
Return true when a code sequence can improve loop throughput.
It should be called only for instructions in loops.
- Parameters
-
Pattern - combiner pattern
Definition at line 757 of file TargetInstrInfo.cpp.
Referenced by isSubregFoldable().
◆ isTriviallyReMaterializable()
|
inline |
Return true if the instruction is trivially rematerializable, meaning it has no side effects and requires no operands that aren't always available.
This means the only allowed uses are constants and unallocatable physical registers so that the instructions result is independent of the place in the function.
Definition at line 93 of file TargetInstrInfo.h.
References llvm::MachineInstr::getDesc(), llvm::MachineInstr::getOpcode(), isReallyTriviallyReMaterializable(), and llvm::MCInstrDesc::isRematerializable().
Referenced by definesFullReg(), isCopyFeedingInvariantStore(), and isRematerializable().
◆ isUnconditionalTailCall()
|
inlinevirtual |
Returns true if MI is an unconditional tail call.
Definition at line 1198 of file TargetInstrInfo.h.
Referenced by salvageDebugInfoFromEmptyBlock().
◆ isUnpredicatedTerminator()
|
virtual |
Returns true if the instruction is a terminator instruction that has not been predicated.
Definition at line 301 of file TargetInstrInfo.cpp.
References llvm::MachineInstr::isBarrier(), llvm::MachineInstr::isBranch(), llvm::MachineInstr::isPredicable(), isPredicated(), and llvm::MachineInstr::isTerminator().
Referenced by findHoistingInsertPosAndDeps(), and isPredicated().
◆ isZeroCost()
Return true for pseudo instructions that don't consume any machine resources in their current form.
These are common cases that the scheduler should consider free, rather than conservatively handling them as instructions with no itinerary.
Definition at line 1343 of file TargetInstrInfo.h.
References DefMI, getInstrLatency(), getOperandLatency(), getPredicationCost(), and UseMI.
Referenced by llvm::ScoreboardHazardRecognizer::EmitInstruction(), and getUnderlyingObjects().
◆ loadRegFromStackSlot()
|
inlinevirtual |
Load the specified register of the given register class from the specified stack frame index.
The load instruction is to be added to the given machine basic block before the specified machine instruction.
Definition at line 892 of file TargetInstrInfo.h.
References llvm_unreachable.
Referenced by emitBuildPairF64Pseudo(), foldMemoryOperand(), INITIALIZE_PASS(), insertCSRRestores(), llvm::SystemZFrameLowering::restoreCalleeSavedRegisters(), and llvm::XCoreFrameLowering::restoreCalleeSavedRegisters().
◆ operator=()
|
delete |
Referenced by TargetInstrInfo().
◆ optimizeCompareInstr()
|
inlinevirtual |
See if the comparison instruction can be converted into something more efficient.
E.g., on ARM most instructions can set the flags register, obviating the need for a separate CMP.
Definition at line 1300 of file TargetInstrInfo.h.
◆ optimizeCondBranch()
|
inlinevirtual |
Definition at line 1305 of file TargetInstrInfo.h.
◆ optimizeLoadInstr()
|
inlinevirtual |
Try to remove the load by folding it to a register operand at the use.
We fold the load instructions if and only if the def and use are in the same BB. We only look at one load and see whether it can be folded into MI. FoldAsLoadDefReg is the virtual register defined by the load we are trying to fold. DefMI returns the machine instruction that defines FoldAsLoadDefReg, and the function returns the machine instruction generated due to folding.
Definition at line 1314 of file TargetInstrInfo.h.
Referenced by isVirtualRegisterOperand().
◆ optimizeSelect()
|
inlinevirtual |
Given a select instruction that was understood by analyzeSelect and returned Optimizable = true, attempt to optimize MI by merging it with one of its operands.
Returns NULL on failure.
When successful, returns the new select instruction. The client is responsible for deleting MI.
If both sides of the select can be optimized, PreferFalse is used to pick a side.
- Parameters
-
MI Optimizable select instruction. NewMIs Set that record all MIs in the basic block up to MI. Has to be updated with any newly created MI or deleted ones.PreferFalse Try to optimize FalseOp instead of TrueOp.
- Returns
- Optimized instruction or NULL.
Definition at line 827 of file TargetInstrInfo.h.
References llvm_unreachable.
◆ PredicateInstruction()
|
virtual |
Convert the instruction into a predicated instruction.
It returns true if the operation was successful.
Definition at line 312 of file TargetInstrInfo.cpp.
References assert(), llvm::MachineInstr::getDesc(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOperand(), getReg(), llvm::MachineInstr::isBundle(), llvm::MachineOperand::isImm(), llvm::MachineOperand::isMBB(), llvm::MachineInstr::isPredicable(), llvm::MachineOperand::isReg(), llvm::MachineOperand::setImm(), llvm::MachineOperand::setMBB(), and llvm::MachineOperand::setReg().
Referenced by MaySpeculate(), and replaceBranchWithTailCall().
◆ produceSameValue()
|
virtual |
Return true if two machine instructions would produce identical values.
By default, this is only true when the two instructions are deemed identical except for defs. If this function is called when the IR is still in SSA form, the caller can pass the MachineRegisterInfo for aggressive checks.
Definition at line 410 of file TargetInstrInfo.cpp.
References llvm::MachineInstr::IgnoreVRegDefs, and llvm::MachineInstr::isIdenticalTo().
Referenced by isCopyFeedingInvariantStore(), and llvm::TargetInstrInfo::RegSubRegPairAndIdx::RegSubRegPairAndIdx().
◆ reassociateOps()
| void TargetInstrInfo::reassociateOps | ( | MachineInstr & | Root, |
| MachineInstr & | Prev, | ||
| MachineCombinerPattern | Pattern, | ||
| SmallVectorImpl< MachineInstr *> & | InsInstrs, | ||
| SmallVectorImpl< MachineInstr *> & | DelInstrs, | ||
| DenseMap< unsigned, unsigned > & | InstrIdxForVirtReg | ||
| ) | const |
Attempt to reassociate Root and Prev according to Pattern to reduce critical path length.
Attempt the reassociation transformation to reduce critical path length.
See the above comments before getMachineCombinerPatterns().
Definition at line 763 of file TargetInstrInfo.cpp.
References llvm::BuildMI(), llvm::MachineRegisterInfo::constrainRegClass(), llvm::MachineRegisterInfo::createVirtualRegister(), llvm::MCInstrInfo::get(), llvm::MachineInstr::getDebugLoc(), llvm::TargetSubtargetInfo::getInstrInfo(), llvm::getKillRegState(), llvm::MachineInstr::getMF(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineInstr::getRegClassConstraint(), llvm::MachineFunction::getRegInfo(), llvm::TargetSubtargetInfo::getRegisterInfo(), llvm::MachineFunction::getSubtarget(), llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::insert(), llvm::MachineOperand::isKill(), llvm::TargetRegisterInfo::isVirtualRegister(), llvm_unreachable, MRI, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::REASSOC_AX_BY, llvm::REASSOC_AX_YB, llvm::REASSOC_XA_BY, llvm::REASSOC_XA_YB, setSpecialOperandAttr(), TII, and TRI.
Referenced by genAlternativeCodeSequence(), and isAssociativeAndCommutative().
◆ reduceLoopCount()
|
inlinevirtual |
Generate code to reduce the loop iteration by one and check if the loop is finished.
Return the value/register of the new loop count. We need this function when peeling off one or more iterations of a loop. This function assumes the nth iteration is peeled first.
Definition at line 666 of file TargetInstrInfo.h.
References llvm_unreachable, and ReplaceTailWithBranchTo().
Referenced by removePhis().
◆ reMaterialize()
|
virtual |
Re-issue the specified 'original' instruction at the specific location targeting a new destination register.
The register in Orig->getOperand(0).getReg() will be substituted by DestReg:SubIdx. Any existing subreg index is preserved or composed with SubIdx.
Definition at line 400 of file TargetInstrInfo.cpp.
References llvm::MachineFunction::CloneMachineInstr(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getReg(), llvm::MachineBasicBlock::insert(), MI, llvm::MachineInstr::substituteRegister(), and TRI.
Referenced by definesFullReg(), and shouldSink().
◆ removeBranch()
|
inlinevirtual |
Remove the branching code at the end of the specific MBB.
This is only invoked in cases where AnalyzeBranch returns success. It returns the number of instructions that were removed. If BytesRemoved is non-null, report the change in code size from the removed instructions.
Definition at line 620 of file TargetInstrInfo.h.
References llvm_unreachable.
Referenced by AnyAliasLiveIn(), bothUsedInPHI(), llvm::TailDuplicator::canTailDuplicate(), findFalseBlock(), FixTail(), getLayoutSuccessorProbThreshold(), isIntersect(), mergeOperations(), parseCond(), salvageDebugInfoFromEmptyBlock(), UpdatePredRedefs(), and llvm::MachineBasicBlock::updateTerminator().
◆ replaceBranchWithTailCall()
|
inlinevirtual |
Replace the conditional branch in MBB with a conditional tail call.
Definition at line 1209 of file TargetInstrInfo.h.
References llvm_unreachable, and PredicateInstruction().
Referenced by salvageDebugInfoFromEmptyBlock().
◆ ReplaceTailWithBranchTo()
|
virtual |
Delete the instruction OldInst and everything after it, replacing it with an unconditional branch to NewDest.
ReplaceTailWithBranchTo - Delete the instruction OldInst and everything after it, replacing it with an unconditional branch to NewDest.
This is used by the tail merging pass.
Definition at line 128 of file TargetInstrInfo.cpp.
References llvm::MachineBasicBlock::addSuccessor(), llvm::MachineBasicBlock::end(), llvm::MachineBasicBlock::erase(), insertBranch(), llvm::MachineBasicBlock::removeSuccessor(), llvm::MachineBasicBlock::succ_begin(), and llvm::MachineBasicBlock::succ_empty().
Referenced by ComputeCommonTailLength(), reduceLoopCount(), and llvm::Thumb2InstrInfo::ReplaceTailWithBranchTo().
◆ reverseBranchCondition()
|
inlinevirtual |
Reverses the branch condition of the specified condition list, returning false on success and true if it cannot be reversed.
Definition at line 1176 of file TargetInstrInfo.h.
References getNoop(), and insertNoop().
Referenced by findFalseBlock(), FixTail(), getLayoutSuccessorProbThreshold(), mergeOperations(), salvageDebugInfoFromEmptyBlock(), UpdatePredRedefs(), llvm::MachineBasicBlock::updateTerminator(), and verifySameBranchInstructions().
◆ setExecutionDomain()
|
inlinevirtual |
Change the opcode of MI to execute in Domain.
The bit (1 << Domain) must be set in the mask returned from getExecutionDomain(MI).
Definition at line 1439 of file TargetInstrInfo.h.
◆ setSpecialOperandAttr()
|
inlinevirtual |
This is an architecture-specific helper function of reassociateOps.
Set special operand attributes for new instructions after reassociation.
Definition at line 1000 of file TargetInstrInfo.h.
Referenced by reassociateOps().
◆ shouldClusterMemOps()
|
inlinevirtual |
Returns true if the two given memory operations should be scheduled adjacent.
Note that you have to add: DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI)); or DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI)); to TargetPassConfig::createMachineScheduler() to have an effect.
Definition at line 1167 of file TargetInstrInfo.h.
References llvm_unreachable.
◆ shouldOutlineFromFunctionByDefault()
|
inlinevirtual |
Return true if the function should be outlined from by default.
Definition at line 1674 of file TargetInstrInfo.h.
Referenced by INITIALIZE_PASS().
◆ shouldScheduleLoadsNear()
|
inlinevirtual |
This is a used by the pre-regalloc scheduler to determine (in conjunction with areLoadsFromSameBasePtr) if two loads should be scheduled together.
On some targets if two loads are loading from addresses in the same cache line, it's better if they are scheduled together. This function takes two integers that represent the load offsets from the common base address. It returns true if it decides it's desirable to schedule the two loads together. "NumLoads" is the number of loads that have already been scheduled after Load1.
Definition at line 1133 of file TargetInstrInfo.h.
◆ shouldSink()
|
inlinevirtual |
Return true if the instruction should be sunk by MachineSink.
MachineSink determines on its own whether the instruction is safe to sink; this gives the target a hook to override the default behavior with regards to which instructions should be sunk.
Definition at line 340 of file TargetInstrInfo.h.
References duplicate(), and reMaterialize().
Referenced by performSink().
◆ storeRegToStackSlot()
|
inlinevirtual |
Store the specified register of the given register class to the specified stack frame index.
The store instruction is to be added to the given machine basic block before the specified machine instruction. If isKill is true, the register operand is the last use and must be marked kill.
Definition at line 880 of file TargetInstrInfo.h.
References llvm_unreachable.
Referenced by emitSplitF64Pseudo(), foldMemoryOperand(), INITIALIZE_PASS(), insertCSRSaves(), llvm::SystemZFrameLowering::spillCalleeSavedRegisters(), llvm::MipsSEFrameLowering::spillCalleeSavedRegisters(), and llvm::XCoreFrameLowering::spillCalleeSavedRegisters().
◆ SubsumesPredicate()
|
inlinevirtual |
Returns true if the first specified predicate subsumes the second, e.g.
GE subsumes GT.
Definition at line 1222 of file TargetInstrInfo.h.
◆ unfoldMemoryOperand() [1/2]
|
inlinevirtual |
unfoldMemoryOperand - Separate a single instruction which folded a load or a store or a load and a store into two or more instruction.
If this is possible, returns true as well as the new instructions by reference.
Definition at line 1092 of file TargetInstrInfo.h.
Referenced by isCopyFeedingInvariantStore().
◆ unfoldMemoryOperand() [2/2]
|
inlinevirtual |
Definition at line 1098 of file TargetInstrInfo.h.
◆ useMachineCombiner()
|
inlinevirtual |
Return true when a target supports MachineCombiner.
Definition at line 1005 of file TargetInstrInfo.h.
◆ usePreRAHazardRecognizer()
| bool TargetInstrInfo::usePreRAHazardRecognizer | ( | ) | const |
Provide a global flag for disabling the PreRA hazard recognizer that targets may choose to honor.
Definition at line 996 of file TargetInstrInfo.cpp.
References CreateTargetHazardRecognizer(), and DisableHazardRecognizer.
Referenced by CreateTargetPostRAHazardRecognizer().
◆ verifyInstruction()
|
inlinevirtual |
Perform target-specific instruction verification.
Definition at line 1406 of file TargetInstrInfo.h.
Referenced by matchPair().
Member Data Documentation
◆ CommuteAnyOperandIndex
Definition at line 381 of file TargetInstrInfo.h.
Referenced by addSegmentsWithValNo(), commuteInstruction(), fixCommutedOpIndices(), isVirtualRegisterOperand(), MoveAndTeeForMultiUse(), stripExtractLoElt(), tryAddToFoldList(), and VerifyLowRegs().
The documentation for this class was generated from the following files:
- include/llvm/CodeGen/TargetInstrInfo.h
- lib/CodeGen/TargetInstrInfo.cpp
