32 #define DEBUG_TYPE "dwarfdebug" 50 auto &Ranges = VarInstrRanges[Var];
51 if (!Ranges.empty() && Ranges.back().second ==
nullptr &&
52 Ranges.back().first->isIdenticalTo(MI)) {
54 <<
"\t" << Ranges.back().first <<
"\t" << MI <<
"\n");
57 Ranges.push_back(std::make_pair(&MI,
nullptr));
62 auto &Ranges = VarInstrRanges[Var];
64 assert(!Ranges.empty() && Ranges.back().second ==
nullptr);
68 Ranges.back().second = &
MI;
72 const auto &
I = VarInstrRanges.
find(Var);
73 if (
I == VarInstrRanges.
end())
75 const auto &Ranges =
I->second;
76 if (Ranges.empty() || Ranges.back().second !=
nullptr)
83 LabelInstr[Label] = &
MI;
90 using RegDescribedVarsMap = std::map<unsigned, SmallVector<InlinedEntity, 1>>;
97 const auto &
I = RegVars.find(RegNo);
98 assert(RegNo != 0U &&
I != RegVars.end());
99 auto &VarSet =
I->second;
101 assert(VarPos != VarSet.end());
102 VarSet.erase(VarPos);
112 auto &VarSet = RegVars[RegNo];
114 VarSet.push_back(Var);
120 RegDescribedVarsMap::iterator
I,
125 for (
const auto &Var : I->second)
135 const auto &
I = RegVars.find(RegNo);
136 if (
I == RegVars.end())
145 if (LastMI == MBB.
end() || !LastMI->isReturn())
149 DebugLoc LastLoc = LastMI->getDebugLoc();
154 if (
I->getDebugLoc() != LastLoc)
160 return &*MBB.
begin();
168 for (
const auto &MBB : *MF) {
171 for (
const auto &
MI : MBB) {
173 if (&
MI == FirstEpilogueInst)
182 if (MO.isReg() && MO.isDef() && MO.getReg() &&
187 }
else if (MO.isRegMask()) {
204 RegDescribedVarsMap RegVars;
205 for (
const auto &MBB : *MF) {
206 for (
const auto &
MI : MBB) {
207 if (!
MI.isDebugInstr()) {
211 if (MO.isReg() && MO.isDef() && MO.getReg()) {
214 if (
MI.isCall() && MO.getReg() == SP)
225 if (ChangingRegs.test(*AI))
228 }
else if (MO.isRegMask()) {
231 for (
unsigned I : ChangingRegs.set_bits()) {
234 MO.clobbersPhysReg(
I)) {
243 if (
MI.isDebugValue()) {
244 assert(
MI.getNumOperands() > 1 &&
"Invalid DBG_VALUE instruction!");
249 assert(RawVar->isValidLocationForIntrinsic(
MI.getDebugLoc()) &&
250 "Expected inlined-at fields to agree");
260 }
else if (
MI.isDebugLabel()) {
261 assert(
MI.getNumOperands() == 1 &&
"Invalid DBG_LABEL instruction!");
262 const DILabel *RawLabel =
MI.getDebugLabel();
263 assert(RawLabel->isValidLocationForIntrinsic(
MI.getDebugLoc()) &&
264 "Expected inlined-at fields to agree");
276 if (!MBB.empty() && &MBB != &MF->back()) {
277 for (
auto I = RegVars.begin(),
E = RegVars.end();
I !=
E;) {
280 ChangingRegs.test(CurElem->first))
287 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) 289 dbgs() <<
"DbgValueHistoryMap:\n";
290 for (
const auto &VarRangePair : *
this) {
300 dbgs() << Location->getFilename() <<
":" << Location->getLine() <<
":" 301 << Location->getColumn();
303 dbgs() <<
"<unknown location>";
308 dbgs() <<
" Begin: " << *Range.first;
310 dbgs() <<
" End : " << *Range.second;
For each inlined instance of a source-level label, keep the corresponding DBG_LABEL instruction...
bool isDebugLabel() const
static void dropRegDescribedVar(RegDescribedVarsMap &RegVars, unsigned RegNo, InlinedEntity Var)
This class represents lattice values for constants.
static const MachineInstr * getFirstEpilogueInst(const MachineBasicBlock &MBB)
unsigned getReg() const
getReg - Returns the register number.
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
virtual const TargetLowering * getTargetLowering() const
void setBitsNotInMask(const uint32_t *Mask, unsigned MaskWords=~0u)
setBitsNotInMask - Add a bit to this vector for every '0' bit in Mask.
unsigned const TargetRegisterInfo * TRI
unsigned getRegisterForVar(InlinedEntity Var) const
void calculateDbgEntityHistory(const MachineFunction *MF, const TargetRegisterInfo *TRI, DbgValueHistoryMap &DbgValues, DbgLabelInstrMap &DbgLabels)
std::pair< const DINode *, const DILocation * > InlinedEntity
StringRef getName() const
unsigned getNumOperands() const
Retuns the total number of operands.
MachineBasicBlock iterator that automatically skips over MIs that are inside bundles (i...
static void addRegDescribedVar(RegDescribedVarsMap &RegVars, unsigned RegNo, InlinedEntity Var)
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
iterator getLastNonDebugInstr()
Returns an iterator to the last non-debug instruction in the basic block, or end().
iterator find(const KeyT &Key)
unsigned getNumRegs() const
Return the number of registers this target has (useful for sizing arrays holding per register informa...
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
MCRegAliasIterator enumerates all registers aliasing Reg.
static void clobberRegisterUses(RegDescribedVarsMap &RegVars, RegDescribedVarsMap::iterator I, DbgValueHistoryMap &HistMap, const MachineInstr &ClobberingInstr)
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
auto find(R &&Range, const T &Val) -> decltype(adl_begin(Range))
Provide wrappers to std::find which take ranges instead of having to pass begin/end explicitly...
static unsigned isDescribedByReg(const MachineInstr &MI)
std::pair< const DINode *, const DILocation * > InlinedEntity
void addInstr(InlinedEntity Label, const MachineInstr &MI)
bool isDebugValue() const
MachineOperand class - Representation of each machine instruction operand.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
void startInstrRange(InlinedEntity Var, const MachineInstr &MI)
const MachineBasicBlock * getParent() const
Representation of each machine instruction.
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
void endInstrRange(InlinedEntity Var, const MachineInstr &MI)
std::pair< const MachineInstr *, const MachineInstr * > InstrRange
bool isReg() const
isReg - Tests if this is a MO_Register operand.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
unsigned getStackPointerRegisterToSaveRestore() const
If a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save...
static void collectChangingRegs(const MachineFunction *MF, const TargetRegisterInfo *TRI, BitVector &Regs)
const MachineOperand & getOperand(unsigned i) const
LLVM_DUMP_METHOD void dump() const
This file describes how to lower LLVM code to machine code.
bool is_contained(R &&Range, const E &Element)
Wrapper function around std::find to detect if an element exists in a container.