30 #define DEBUG_TYPE "calcspillweights" 38 LLVM_DEBUG(
dbgs() <<
"********** Compute Spill Weights **********\n" 39 <<
"********** Function: " << MF.
getName() <<
'\n');
43 for (
unsigned i = 0, e = MRI.getNumVirtRegs(); i != e; ++i) {
45 if (MRI.reg_nodbg_empty(Reg))
55 unsigned sub, hreg, hsub;
70 return sub == hsub ? hreg : 0;
73 unsigned CopiedPReg = (hsub ? tri.
getSubReg(hreg, hsub) : hreg);
90 unsigned Original = VRM ? VRM->
getOriginal(Reg) : 0;
100 assert(MI &&
"Dead valno in interval");
124 assert(VNI &&
"Copy from non-existing value");
128 assert(MI &&
"Dead valno in interval");
157 bool isExiting =
false;
158 float totalWeight = 0;
159 unsigned numInstr = 0;
167 bool localSplitArtifact = start &&
end;
170 bool updateLI = !localSplitArtifact;
172 if (localSplitArtifact) {
175 "start and end are expected to be in the same basic block");
193 CopyHint(
unsigned R,
float W,
bool P) :
194 Reg(R), Weight(W), IsPhys(P) {}
195 bool operator<(
const CopyHint &rhs)
const {
197 if (IsPhys != rhs.IsPhys)
198 return (IsPhys && !rhs.IsPhys);
199 if (Weight != rhs.Weight)
200 return (Weight > rhs.Weight);
201 return Reg < rhs.Reg;
204 std::set<CopyHint> CopyHints;
213 SlotIndex si = LIS.getInstructionIndex(*mi);
214 if (localSplitArtifact && ((si < *start) || (si > *end)))
220 if (!visited.
insert(mi).second)
228 loop =
Loops.getLoopFor(mbb);
238 if (writes && isExiting && LIS.isLiveOutOfMBB(li, mbb))
241 totalWeight += weight;
254 volatile float hweight = Hint[hint] += weight;
262 if (updateLI && CopyHints.size()) {
264 if (TargetHint.first == 0 && TargetHint.second)
267 std::set<unsigned> HintedRegs;
268 for (
auto &Hint : CopyHints) {
269 if (!HintedRegs.insert(Hint.Reg).second ||
270 (TargetHint.first != 0 && Hint.Reg == TargetHint.second))
277 totalWeight *= 1.01F;
287 if (updateLI && li.
isZeroLength(LIS.getSlotIndexes()) &&
300 if (localSplitArtifact)
301 return normalize(totalWeight, start->
distance(*end), numInstr);
302 return normalize(totalWeight, li.
getSize(), numInstr);
bool isPHIDef() const
Returns true if this value is defined by a PHI instruction (or was, PHI instructions may have been el...
const_iterator end(StringRef path)
Get end iterator over path.
Calculate auxiliary information for a virtual register such as its spill weight and allocation hint...
bool contains(unsigned Reg) const
Return true if the specified register is included in this register class.
const TargetRegisterClass * getRegClass(unsigned Reg) const
Return the register class of the specified virtual register.
SlotIndex def
The index of the defining instruction.
static float getSpillWeight(bool isDef, bool isUse, const MachineBlockFrequencyInfo *MBFI, const MachineInstr &MI)
Calculate the spill weight to assign to a single instruction.
bool isAllocatable(unsigned PhysReg) const
isAllocatable - Returns true when PhysReg belongs to an allocatable register class and it hasn't been...
This class represents lattice values for constants.
static unsigned index2VirtReg(unsigned Index)
Convert a 0-based index to a virtual register number.
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
LiveInterval - This class represents the liveness of a register, or stack slot.
unsigned getReg() const
getReg - Returns the register number.
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
unsigned getSubReg() const
bool isLiveAtIndexes(ArrayRef< SlotIndex > Slots) const
MachineBlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate machine basic b...
VNInfo - Value Number Information.
bool isUnused() const
Returns true if this value is unused.
const HexagonInstrInfo * TII
Result of a LiveRange query.
static reg_instr_iterator reg_instr_end()
defusechain_iterator - This class provides iterator support for machine operands in the function that...
MachineInstr * getInstructionFromIndex(SlotIndex index) const
Returns the instruction associated with the given index.
static bool isRematerializable(const LiveInterval &LI, const LiveIntervals &LIS, VirtRegMap *VRM, const TargetInstrInfo &TII)
bool isIdentityCopy() const
Return true is the instruction is an identity copy.
AliasAnalysis * getAliasAnalysis() const
bool isZeroLength(SlotIndexes *Indexes) const
Returns true if the live range is zero length, i.e.
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
float futureWeight(LiveInterval &li, SlotIndex start, SlotIndex end)
Compute future expected spill weight of a split artifact of li that will span between start and end s...
VNInfo * valueIn() const
Return the value that is live-in to the instruction.
LiveQueryResult Query(SlotIndex Idx) const
Query Liveness at Idx.
static unsigned copyHint(const MachineInstr *mi, unsigned reg, const TargetRegisterInfo &tri, const MachineRegisterInfo &mri)
TargetInstrInfo - Interface to description of machine instruction set.
unsigned const MachineRegisterInfo * MRI
VNInfoList::const_iterator const_vni_iterator
bool isLoopExiting(const BlockT *BB) const
True if terminator in the block can branch to another block that is outside of the current loop...
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
std::pair< iterator, bool > insert(PtrType Ptr)
Inserts Ptr if and only if there is no element in the container equal to Ptr.
unsigned getSubReg(unsigned Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo...
std::pair< bool, bool > readsWritesVirtualRegister(unsigned Reg, SmallVectorImpl< unsigned > *Ops=nullptr) const
Return a pair of bools (reads, writes) indicating if this instruction reads or writes Reg...
MachineBasicBlock * getMBBFromIndex(SlotIndex index) const
bool isImplicitDef() const
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
bool isDebugInstr() const
float weightCalcHelper(LiveInterval &li, SlotIndex *start=nullptr, SlotIndex *end=nullptr)
Helper function for weight calculations.
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements...
void calculateSpillWeightsAndHints(LiveIntervals &LIS, MachineFunction &MF, VirtRegMap *VRM, const MachineLoopInfo &MLI, const MachineBlockFrequencyInfo &MBFI, VirtRegAuxInfo::NormalizingFn norm=normalizeSpillWeight)
Compute spill weights and allocation hints for all virtual register live intervals.
void calculateSpillWeightAndHint(LiveInterval &li)
(re)compute li's spill weight and allocation hint.
void clearSimpleHint(unsigned VReg)
void markNotSpillable()
markNotSpillable - Mark interval as not spillable
LiveInterval & getInterval(unsigned Reg)
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
unsigned getSize() const
getSize - Returns the sum of sizes of all the LiveRange's.
const MachineBasicBlock * getParent() const
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
std::pair< unsigned, unsigned > getRegAllocationHint(unsigned VReg) const
getRegAllocationHint - Return the register allocation hint for the specified virtual register...
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx, const TargetRegisterClass *RC) const
Return a super-register of the specified register Reg so its sub-register of index SubIdx is Reg...
int distance(SlotIndex other) const
Return the distance from this index to the given one.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool operator<(int64_t V1, const APSInt &V2)
void addRegAllocationHint(unsigned VReg, unsigned PrefReg)
addRegAllocationHint - Add a register allocation hint to the hints vector for VReg.
bool isSpillable() const
isSpillable - Can this interval be spilled?
float(*)(float, unsigned, unsigned) NormalizingFn
const MachineOperand & getOperand(unsigned i) const
SlotIndex - An opaque wrapper around machine indexes.
bool isTriviallyReMaterializable(const MachineInstr &MI, AliasAnalysis *AA=nullptr) const
Return true if the instruction is trivially rematerializable, meaning it has no side effects and requ...
unsigned getOriginal(unsigned VirtReg) const
getOriginal - Return the original virtual register that VirtReg descends from through splitting...
reg_instr_iterator reg_instr_begin(unsigned RegNo) const