Describe properties that are true of each instruction in the target description file. More...
#include "llvm/MC/MCInstrDesc.h"
Public Types | |
| using | const_opInfo_iterator = const MCOperandInfo * |
Public Member Functions | |
| int | getOperandConstraint (unsigned OpNum, MCOI::OperandConstraint Constraint) const |
| Returns the value of the specific constraint if it is set. More... | |
| bool | getDeprecatedInfo (MCInst &MI, const MCSubtargetInfo &STI, std::string &Info) const |
Returns true if a certain instruction is deprecated and if so returns the reason in Info. More... | |
| unsigned | getOpcode () const |
| Return the opcode number for this descriptor. More... | |
| unsigned | getNumOperands () const |
| Return the number of declared MachineOperands for this MachineInstruction. More... | |
| const_opInfo_iterator | opInfo_begin () const |
| const_opInfo_iterator | opInfo_end () const |
| iterator_range< const_opInfo_iterator > | operands () const |
| unsigned | getNumDefs () const |
| Return the number of MachineOperands that are register definitions. More... | |
| uint64_t | getFlags () const |
| Return flags of this instruction. More... | |
| bool | isVariadic () const |
| Return true if this instruction can have a variable number of operands. More... | |
| bool | hasOptionalDef () const |
| Set if this instruction has an optional definition, e.g. More... | |
| bool | isPseudo () const |
| Return true if this is a pseudo instruction that doesn't correspond to a real machine instruction. More... | |
| bool | isReturn () const |
| Return true if the instruction is a return. More... | |
| bool | isAdd () const |
| Return true if the instruction is an add instruction. More... | |
| bool | isTrap () const |
| Return true if this instruction is a trap. More... | |
| bool | isMoveReg () const |
| Return true if the instruction is a register to register move. More... | |
| bool | isCall () const |
| Return true if the instruction is a call. More... | |
| bool | isBarrier () const |
| Returns true if the specified instruction stops control flow from executing the instruction immediately following it. More... | |
| bool | isTerminator () const |
| Returns true if this instruction part of the terminator for a basic block. More... | |
| bool | isBranch () const |
| Returns true if this is a conditional, unconditional, or indirect branch. More... | |
| bool | isIndirectBranch () const |
| Return true if this is an indirect branch, such as a branch through a register. More... | |
| bool | isConditionalBranch () const |
| Return true if this is a branch which may fall through to the next instruction or may transfer control flow to some other block. More... | |
| bool | isUnconditionalBranch () const |
| Return true if this is a branch which always transfers control flow to some other block. More... | |
| bool | mayAffectControlFlow (const MCInst &MI, const MCRegisterInfo &RI) const |
| Return true if this is a branch or an instruction which directly writes to the program counter. More... | |
| bool | isPredicable () const |
| Return true if this instruction has a predicate operand that controls execution. More... | |
| bool | isCompare () const |
| Return true if this instruction is a comparison. More... | |
| bool | isMoveImmediate () const |
| Return true if this instruction is a move immediate (including conditional moves) instruction. More... | |
| bool | isBitcast () const |
| Return true if this instruction is a bitcast instruction. More... | |
| bool | isSelect () const |
| Return true if this is a select instruction. More... | |
| bool | isNotDuplicable () const |
| Return true if this instruction cannot be safely duplicated. More... | |
| bool | hasDelaySlot () const |
| Returns true if the specified instruction has a delay slot which must be filled by the code generator. More... | |
| bool | canFoldAsLoad () const |
| Return true for instructions that can be folded as memory operands in other instructions. More... | |
| bool | isRegSequenceLike () const |
| Return true if this instruction behaves the same way as the generic REG_SEQUENCE instructions. More... | |
| bool | isExtractSubregLike () const |
| Return true if this instruction behaves the same way as the generic EXTRACT_SUBREG instructions. More... | |
| bool | isInsertSubregLike () const |
| Return true if this instruction behaves the same way as the generic INSERT_SUBREG instructions. More... | |
| bool | isConvergent () const |
| Return true if this instruction is convergent. More... | |
| bool | variadicOpsAreDefs () const |
| Return true if variadic operands of this instruction are definitions. More... | |
| bool | mayLoad () const |
| Return true if this instruction could possibly read memory. More... | |
| bool | mayStore () const |
| Return true if this instruction could possibly modify memory. More... | |
| bool | hasUnmodeledSideEffects () const |
| Return true if this instruction has side effects that are not modeled by other flags. More... | |
| bool | isCommutable () const |
| Return true if this may be a 2- or 3-address instruction (of the form "X = op Y, Z, ..."), which produces the same result if Y and Z are exchanged. More... | |
| bool | isConvertibleTo3Addr () const |
| Return true if this is a 2-address instruction which can be changed into a 3-address instruction if needed. More... | |
| bool | usesCustomInsertionHook () const |
| Return true if this instruction requires custom insertion support when the DAG scheduler is inserting it into a machine basic block. More... | |
| bool | hasPostISelHook () const |
| Return true if this instruction requires adjustment after instruction selection by calling a target hook. More... | |
| bool | isRematerializable () const |
| Returns true if this instruction is a candidate for remat. More... | |
| bool | isAsCheapAsAMove () const |
| Returns true if this instruction has the same cost (or less) than a move instruction. More... | |
| bool | hasExtraSrcRegAllocReq () const |
| Returns true if this instruction source operands have special register allocation requirements that are not captured by the operand register classes. More... | |
| bool | hasExtraDefRegAllocReq () const |
| Returns true if this instruction def operands have special register allocation requirements that are not captured by the operand register classes. More... | |
| const MCPhysReg * | getImplicitUses () const |
| Return a list of registers that are potentially read by any instance of this machine instruction. More... | |
| unsigned | getNumImplicitUses () const |
| Return the number of implicit uses this instruction has. More... | |
| const MCPhysReg * | getImplicitDefs () const |
| Return a list of registers that are potentially written by any instance of this machine instruction. More... | |
| unsigned | getNumImplicitDefs () const |
| Return the number of implicit defs this instruct has. More... | |
| bool | hasImplicitUseOfPhysReg (unsigned Reg) const |
| Return true if this instruction implicitly uses the specified physical register. More... | |
| bool | hasImplicitDefOfPhysReg (unsigned Reg, const MCRegisterInfo *MRI=nullptr) const |
| Return true if this instruction implicitly defines the specified physical register. More... | |
| unsigned | getSchedClass () const |
| Return the scheduling class for this instruction. More... | |
| unsigned | getSize () const |
| Return the number of bytes in the encoding of this instruction, or zero if the encoding size cannot be known from the opcode. More... | |
| int | findFirstPredOperandIdx () const |
| Find the index of the first operand in the operand list that is used to represent the predicate. More... | |
| bool | hasDefOfPhysReg (const MCInst &MI, unsigned Reg, const MCRegisterInfo &RI) const |
| Return true if this instruction defines the specified physical register, either explicitly or implicitly. More... | |
Public Attributes | |
| unsigned short | Opcode |
| unsigned short | NumOperands |
| unsigned char | NumDefs |
| unsigned char | Size |
| unsigned short | SchedClass |
| uint64_t | Flags |
| uint64_t | TSFlags |
| const MCPhysReg * | ImplicitUses |
| const MCPhysReg * | ImplicitDefs |
| const MCOperandInfo * | OpInfo |
| int64_t | DeprecatedFeature |
| bool(* | ComplexDeprecationInfo )(MCInst &, const MCSubtargetInfo &, std::string &) |
Detailed Description
Describe properties that are true of each instruction in the target description file.
This captures information about side effects, register use and many other things. There is one instance of this struct for each target instruction class, and the MachineInstr class points to this struct directly to describe itself.
Definition at line 164 of file MCInstrDesc.h.
Member Typedef Documentation
◆ const_opInfo_iterator
Definition at line 213 of file MCInstrDesc.h.
Member Function Documentation
◆ canFoldAsLoad()
|
inline |
Return true for instructions that can be folded as memory operands in other instructions.
The most common use for this is instructions that are simple loads from memory that don't modify the loaded value in any way, but it can also be used for instructions that can be expressed as constant-pool loads, such as V_SETALLONES on x86, to allow them to be folded when it is beneficial. This should only be set on instructions that return a value in their only virtual register definition.
Definition at line 339 of file MCInstrDesc.h.
References llvm::MCID::FoldableAsLoad.
◆ findFirstPredOperandIdx()
|
inline |
Find the index of the first operand in the operand list that is used to represent the predicate.
It returns -1 if none is found.
Definition at line 586 of file MCInstrDesc.h.
Referenced by instIsBreakpoint(), and llvm::IsCPSRDead< MCInst >().
◆ getDeprecatedInfo()
| bool MCInstrDesc::getDeprecatedInfo | ( | MCInst & | MI, |
| const MCSubtargetInfo & | STI, | ||
| std::string & | Info | ||
| ) | const |
Returns true if a certain instruction is deprecated and if so returns the reason in Info.
Definition at line 22 of file MCInstrDesc.cpp.
References ComplexDeprecationInfo, DeprecatedFeature, and llvm::MCSubtargetInfo::getFeatureBits().
◆ getFlags()
|
inline |
Return flags of this instruction.
Definition at line 229 of file MCInstrDesc.h.
Referenced by llvm::MachineInstr::hasProperty().
◆ getImplicitDefs()
Return a list of registers that are potentially written by any instance of this machine instruction.
For example, on X86, many instructions implicitly set the flags register. In this case, they are marked as setting the FLAGS. Likewise, many instructions always deposit their result in a physical register. For example, the X86 divide instruction always deposits the quotient and remainder in the EAX/EDX registers. For that instruction, this will return a list containing the EAX/EDX/EFLAGS registers.
This method returns null if the instruction has no implicit defs.
Definition at line 546 of file MCInstrDesc.h.
Referenced by llvm::MachineInstr::addImplicitDefUseOperands(), llvm::X86_MC::X86MCInstrAnalysis::clearsSuperRegisters(), llvm::InstrEmitter::EmitDbgLabel(), getPhysicalRegisterVT(), HasImplicitCPSRDef(), llvm::rdf::TargetOperandInfo::isFixedReg(), isImplicitOperandIn(), llvm::PPCInstrInfo::optimizeCompareInstr(), and llvm::mca::verifyOperands().
◆ getImplicitUses()
Return a list of registers that are potentially read by any instance of this machine instruction.
For example, on X86, the "adc" instruction adds two register operands and adds the carry bit in from the flags register. In this case, the instruction is marked as implicitly reading the flags. Likewise, the variable shift instruction on X86 is marked as implicitly reading the 'CL' register, which it always does.
This method returns null if the instruction has no implicit uses.
Definition at line 524 of file MCInstrDesc.h.
Referenced by llvm::MachineInstr::addImplicitDefUseOperands(), llvm::InstrEmitter::EmitDbgLabel(), llvm::rdf::TargetOperandInfo::isFixedReg(), isImplicitOperandIn(), llvm::PPCInstrInfo::optimizeCompareInstr(), and llvm::mca::verifyOperands().
◆ getNumDefs()
|
inline |
Return the number of MachineOperands that are register definitions.
Register definitions always occur at the start of the machine operand list. This is the number of "outs" in the .td file, and does not include implicit defs.
Definition at line 226 of file MCInstrDesc.h.
Referenced by AnyAliasLiveIn(), llvm::ARMBaseInstrInfo::breakPartialRegDependency(), canEnableCoalescing(), CC_MipsO32_FP64(), CheckForPhysRegDependency(), llvm::X86_MC::X86MCInstrAnalysis::clearsSuperRegisters(), llvm::TargetInstrInfo::commuteInstructionImpl(), computeBytesPoppedByCalleeForSRet(), llvm::createBreakFalseDeps(), llvm::createR600ISelDag(), definesFullReg(), llvm::InstrEmitter::EmitDbgLabel(), encodeBitmaskPerm(), llvm::LiveRangeEdit::eraseVirtReg(), llvm::FastISel::fastEmitInst_f(), llvm::FastISel::fastEmitInst_i(), llvm::FastISel::fastEmitInst_r(), llvm::FastISel::fastEmitInst_ri(), llvm::FastISel::fastEmitInst_rii(), llvm::FastISel::fastEmitInst_rr(), llvm::FastISel::fastEmitInst_rri(), llvm::FastISel::fastEmitInst_rrr(), llvm::X86InstrInfo::findCommutedOpIndices(), llvm::TargetInstrInfo::findCommutedOpIndices(), findStartOfTree(), llvm::X86InstrInfo::foldMemoryOperandImpl(), getCompareCC(), llvm::ARMBaseInstrInfo::getExtractSubregLikeInputs(), llvm::ARMBaseInstrInfo::getInsertSubregLikeInputs(), llvm::ARMBaseInstrInfo::getLDMVariableDefsSize(), getNewSource(), llvm::MachineInstr::getNumExplicitDefs(), llvm::X86II::getOperandBias(), getPhysicalRegisterVT(), llvm::ARMBaseInstrInfo::getRegSequenceLikeInputs(), llvm::ARMTargetLowering::getSchedulingPreference(), INITIALIZE_PASS(), llvm::ResourcePriorityQueue::initNumRegDefsLeft(), insertPHI(), isCopyFeedingInvariantStore(), isCrossCopy(), llvm::HexagonInstrInfo::isDependent(), isMulPowOf2(), isRegOrImmWithInputMods(), isSExtLoad(), isVirtualRegisterOperand(), matchPair(), OneUseDominatesOtherUses(), llvm::HexagonMCInstrInfo::predicateInfo(), printMasking(), llvm::HexagonMCChecker::reportBranchErrors(), llvm::SystemZHazardRecognizer::Reset(), rewritesSort(), llvm::Localizer::runOnMachineFunction(), stripExtractLoElt(), llvm::X86InstrInfo::unfoldMemoryOperand(), and llvm::mca::verifyOperands().
◆ getNumImplicitDefs()
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inline |
Return the number of implicit defs this instruct has.
Definition at line 549 of file MCInstrDesc.h.
Referenced by llvm::MachineInstr::addImplicitDefUseOperands(), llvm::X86_MC::X86MCInstrAnalysis::clearsSuperRegisters(), copyExtraImplicitOps(), llvm::InstrEmitter::EmitDbgLabel(), llvm::MachineInstr::getNumDefs(), stripExtraCopyOperands(), and llvm::mca::verifyOperands().
◆ getNumImplicitUses()
|
inline |
Return the number of implicit uses this instruction has.
Definition at line 527 of file MCInstrDesc.h.
Referenced by llvm::MachineInstr::addImplicitDefUseOperands(), copyExtraImplicitOps(), llvm::InstrEmitter::EmitDbgLabel(), llvm::SIInstrInfo::expandPostRAPseudo(), getSpecialRegForName(), llvm::SIInstrInfo::isFoldableCopy(), stripExtraCopyOperands(), llvm::SIInstrInfo::verifyInstruction(), and llvm::mca::verifyOperands().
◆ getNumOperands()
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inline |
Return the number of declared MachineOperands for this MachineInstruction.
Note that variadic (isVariadic() returns true) instructions may have additional operands at the end of the list, and note that the machine instruction may include implicit register def/uses as well.
Definition at line 211 of file MCInstrDesc.h.
Referenced by llvm::MachineInstr::addImplicitDefUseOperands(), addLiveInRegs(), llvm::MachineInstr::addOperand(), llvm::ScheduleDAGInstrs::addPhysRegDataDeps(), canEnableCoalescing(), llvm::ARMBaseInstrInfo::convertToThreeAddress(), copyExtraImplicitOps(), llvm::MachineInstr::copyImplicitOps(), llvm::PPCInstrInfo::copyPhysReg(), countMCSymbolRefExpr(), llvm::createLanaiDelaySlotFillerPass(), llvm::createR600ISelDag(), CriticalPathStep(), definesFullReg(), llvm::InstrEmitter::EmitDbgLabel(), emitDirectiveRelocJalr(), Expand2AddrKreg(), Expand2AddrUndef(), llvm::SIInstrInfo::expandPostRAPseudo(), llvm::ARMBaseInstrInfo::FoldImmediate(), llvm::PPCInstrInfo::FoldImmediate(), llvm::X86InstrInfo::foldMemoryOperandImpl(), FuseTwoAddrInst(), llvm::LegalizerInfo::getAction(), GetDSubRegs(), llvm::X86InstrInfo::getExecutionDomainCustom(), llvm::ARMBaseInstrInfo::getLDMVariableDefsSize(), getLit64Encoding(), getLSMultipleTransferSize(), getMemoryOpOffset(), getNewSource(), llvm::MachineInstr::getNumExplicitOperands(), llvm::ARMBaseInstrInfo::getNumMicroOps(), llvm::X86II::getOperandBias(), llvm::SIInstrInfo::getOpRegClass(), llvm::TargetInstrInfo::getRegClass(), getTargetMBB(), HasSecRelSymbolRef(), INITIALIZE_PASS(), isCopy(), isCopyFeedingInvariantStore(), llvm::SIInstrInfo::isFoldableCopy(), llvm::AArch64InstrInfo::isFPRCopy(), llvm::AArch64InstrInfo::isGPRCopy(), llvm::AArch64InstrInfo::isGPRZero(), isOperandKill(), isOperandOf(), matchPair(), llvm::HexagonMCInstrInfo::predicateInfo(), llvm::WebAssemblyInstPrinter::printInst(), registerDefinedBetween(), llvm::SystemZHazardRecognizer::Reset(), llvm::ARMBaseInstrInfo::setExecutionDomain(), llvm::X86InstrInfo::setExecutionDomainCustom(), stripExtraCopyOperands(), llvm::SIInstrInfo::verifyInstruction(), VerifyLowRegs(), and llvm::mca::verifyOperands().
◆ getOpcode()
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inline |
Return the opcode number for this descriptor.
Definition at line 204 of file MCInstrDesc.h.
Referenced by adjustDefLatency(), llvm::AVRInstrInfo::analyzeBranch(), llvm::constrainOperandRegClass(), llvm::createRISCVMCCodeEmitter(), llvm::MipsSEInstrInfo::expandPostRAPseudo(), llvm::Mips16InstrInfo::expandPostRAPseudo(), llvm::SIInstrInfo::findCommutedOpIndices(), llvm::AArch64InstrInfo::getInstSizeInBytes(), llvm::MSP430InstrInfo::getInstSizeInBytes(), llvm::ARMBaseInstrInfo::getLDMVariableDefsSize(), llvm::ARMBaseInstrInfo::getNumMicroOps(), llvm::ARMBaseInstrInfo::getOperandLatency(), hasRAWHazard(), INITIALIZE_PASS(), llvm::HexagonInstrInfo::isComplex(), isFpMulInstruction(), isPCRel(), matchPair(), raise_relocation_error(), llvm::SIInstrInfo::verifyInstruction(), and VerifyLowRegs().
◆ getOperandConstraint()
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inline |
Returns the value of the specific constraint if it is set.
Returns -1 if it is not set.
Definition at line 188 of file MCInstrDesc.h.
References llvm::MCOperandInfo::Constraints, Info, and MI.
Referenced by llvm::MachineInstr::addOperand(), canEnableCoalescing(), llvm::TargetInstrInfo::commuteInstructionImpl(), llvm::PPCInstrInfo::commuteInstructionImpl(), llvm::constrainSelectedInstRegOperands(), llvm::X86InstrInfo::findCommutedOpIndices(), llvm::X86InstrInfo::foldMemoryOperandImpl(), llvm::X86II::getOperandBias(), getSpecialRegForName(), llvm::MachineInstr::hasComplexRegisterTies(), INITIALIZE_PASS(), isMatchingOrAlias(), isOperandOf(), isRegOrImmWithInputMods(), matchPair(), printMasking(), llvm::SystemZHazardRecognizer::Reset(), and tieOpsIfNeeded().
◆ getSchedClass()
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inline |
Return the scheduling class for this instruction.
The scheduling class is an index into the InstrItineraryData table. This returns zero if there is no known scheduling information for the instruction.
Definition at line 577 of file MCInstrDesc.h.
Referenced by llvm::DFAPacketizer::canReserveResources(), llvm::TargetSchedModel::computeInstrLatency(), llvm::TargetSchedModel::computeOperandLatency(), llvm::TargetSchedModel::computeReciprocalThroughput(), llvm::ScoreboardHazardRecognizer::EmitInstruction(), llvm::HexagonInstrInfo::genAllInsnTimingClasses(), llvm::ScoreboardHazardRecognizer::getHazardType(), llvm::PPCInstrInfo::getInstrLatency(), llvm::TargetInstrInfo::getInstrLatency(), llvm::HexagonInstrInfo::getInstrTimingClassLatency(), getItineraryLatency(), getLatency(), llvm::ARMBaseInstrInfo::getLDMVariableDefsSize(), llvm::TargetSchedModel::getNumMicroOps(), llvm::ARMBaseInstrInfo::getNumMicroOps(), llvm::TargetInstrInfo::getNumMicroOps(), getNumMicroOpsSwiftLdSt(), llvm::ARMBaseInstrInfo::getOperandLatency(), llvm::TargetInstrInfo::getOperandLatency(), llvm::HexagonMCInstrInfo::getOtherReservedSlots(), llvm::ARMTargetLowering::getSchedulingPreference(), getUnderlyingObjects(), llvm::HexagonMCInstrInfo::getUnits(), llvm::HexagonInstrInfo::getUnits(), llvm::TargetInstrInfo::hasLowDefLatency(), llvm::HexagonPacketizerList::ignorePseudoInstruction(), llvm::HexagonInstrInfo::isEarlySourceInstr(), llvm::HexagonInstrInfo::isLateResultInstr(), llvm::HexagonInstrInfo::isTC1(), llvm::HexagonInstrInfo::isTC2(), llvm::HexagonInstrInfo::isTC2Early(), llvm::HexagonInstrInfo::isTC4x(), llvm::DFAPacketizer::reserveResources(), llvm::TargetSchedModel::resolveSchedClass(), and llvm::mca::verifyOperands().
◆ getSize()
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inline |
Return the number of bytes in the encoding of this instruction, or zero if the encoding size cannot be known from the opcode.
Definition at line 581 of file MCInstrDesc.h.
References Size.
Referenced by llvm::createRISCVMCCodeEmitter(), llvm::MipsMCCodeEmitter::encodeInstruction(), llvm::MSP430MCCodeEmitter::encodeInstruction(), llvm::ARCInstrInfo::getInstSizeInBytes(), llvm::MSP430InstrInfo::getInstSizeInBytes(), llvm::AVRInstrInfo::getInstSizeInBytes(), llvm::PPCMCCodeEmitter::getInstSizeInBytes(), llvm::MipsInstrInfo::getInstSizeInBytes(), llvm::ARMBaseInstrInfo::getInstSizeInBytes(), llvm::SystemZInstrInfo::getInstSizeInBytes(), llvm::SIInstrInfo::getInstSizeInBytes(), getLit64Encoding(), llvm::HexagonInstrInfo::getSize(), HasConditionalBranch(), and needsPCRel().
◆ hasDefOfPhysReg()
| bool MCInstrDesc::hasDefOfPhysReg | ( | const MCInst & | MI, |
| unsigned | Reg, | ||
| const MCRegisterInfo & | RI | ||
| ) | const |
Return true if this instruction defines the specified physical register, either explicitly or implicitly.
Definition at line 54 of file MCInstrDesc.cpp.
References llvm::MCInst::getNumOperands(), llvm::MCInst::getOperand(), llvm::MCOperand::getReg(), hasImplicitDefOfPhysReg(), llvm::MCOperand::isReg(), llvm::MCRegisterInfo::isSubRegisterEq(), NumDefs, NumOperands, and variadicOpsAreDefs().
Referenced by llvm::IsCPSRDead< MCInst >(), and mayAffectControlFlow().
◆ hasDelaySlot()
|
inline |
Returns true if the specified instruction has a delay slot which must be filled by the code generator.
Definition at line 330 of file MCInstrDesc.h.
References llvm::MCID::DelaySlot.
Referenced by countMCSymbolRefExpr(), and nextReg().
◆ hasExtraDefRegAllocReq()
|
inline |
Returns true if this instruction def operands have special register allocation requirements that are not captured by the operand register classes.
e.g. ARM::LDRD's two def registers must be an even / odd pair, ARM::LDM registers have to be in ascending order. Post-register allocation passes should not attempt to change allocations for definitions of instructions with this flag.
Definition at line 512 of file MCInstrDesc.h.
References llvm::MCID::ExtraDefRegAllocReq.
◆ hasExtraSrcRegAllocReq()
|
inline |
Returns true if this instruction source operands have special register allocation requirements that are not captured by the operand register classes.
e.g. ARM::STRD's two source registers must be an even / odd pair, ARM::STM registers have to be in ascending order. Post-register allocation passes should not attempt to change allocations for sources of instructions with this flag.
Definition at line 502 of file MCInstrDesc.h.
References llvm::MCID::ExtraSrcRegAllocReq.
◆ hasImplicitDefOfPhysReg()
| bool MCInstrDesc::hasImplicitDefOfPhysReg | ( | unsigned | Reg, |
| const MCRegisterInfo * | MRI = nullptr |
||
| ) | const |
Return true if this instruction implicitly defines the specified physical register.
Definition at line 45 of file MCInstrDesc.cpp.
References ImplicitDefs, and llvm::MCRegisterInfo::isSubRegister().
Referenced by llvm::ScheduleDAGInstrs::addPhysRegDataDeps(), llvm::ARMBaseInstrInfo::getOperandLatency(), llvm::X86InstrInfo::getOutliningType(), and hasDefOfPhysReg().
◆ hasImplicitUseOfPhysReg()
Return true if this instruction implicitly uses the specified physical register.
Definition at line 560 of file MCInstrDesc.h.
Referenced by llvm::ScheduleDAGInstrs::addPhysRegDataDeps(), and llvm::X86InstrInfo::getOutliningType().
◆ hasOptionalDef()
|
inline |
Set if this instruction has an optional definition, e.g.
ARM instructions which can set condition code if 's' bit is set.
Definition at line 239 of file MCInstrDesc.h.
References llvm::MCID::HasOptionalDef.
Referenced by llvm::ARMBaseInstrInfo::FoldImmediate(), getRealVLDOpcode(), VerifyLowRegs(), and llvm::mca::verifyOperands().
◆ hasPostISelHook()
|
inline |
Return true if this instruction requires adjustment after instruction selection by calling a target hook.
For example, this can be used to fill in ARM 's' optional operand depending on whether the conditional flag register is used.
Definition at line 473 of file MCInstrDesc.h.
References llvm::MCID::HasPostISelHook.
◆ hasUnmodeledSideEffects()
|
inline |
Return true if this instruction has side effects that are not modeled by other flags.
This does not return true for instructions whose effects are captured by:
- Their operand list and implicit definition/use list. Register use/def info is explicit for instructions.
- Memory accesses. Use mayLoad/mayStore.
- Calling, branching, returning: use isCall/isReturn/isBranch.
Examples of side effects would be modifying 'invisible' machine state like a control register, flushing a cache, modifying a register invisible to LLVM, etc.
Definition at line 419 of file MCInstrDesc.h.
References llvm::MCID::UnmodeledSideEffects.
Referenced by llvm::mca::verifyOperands().
◆ isAdd()
|
inline |
Return true if the instruction is an add instruction.
Definition at line 249 of file MCInstrDesc.h.
References llvm::MCID::Add.
Referenced by llvm::createHexagonHardwareLoops(), and isImmValidForOpcode().
◆ isAsCheapAsAMove()
|
inline |
Returns true if this instruction has the same cost (or less) than a move instruction.
This is useful during certain types of optimizations (e.g., remat during two-address conversion or machine licm) where we would like to remat or hoist the instruction, but not if it costs more than moving the instruction into the appropriate register. Note, we are not marking copies from and to the same register class with this flag.
This method could be called by interface TargetInstrInfo::isAsCheapAsAMove for different subtargets.
Definition at line 494 of file MCInstrDesc.h.
References llvm::MCID::CheapAsAMove.
◆ isBarrier()
|
inline |
Returns true if the specified instruction stops control flow from executing the instruction immediately following it.
Examples include unconditional branches and return instructions.
Definition at line 263 of file MCInstrDesc.h.
References llvm::MCID::Barrier.
◆ isBitcast()
|
inline |
Return true if this instruction is a bitcast instruction.
Definition at line 318 of file MCInstrDesc.h.
References llvm::MCID::Bitcast.
◆ isBranch()
|
inline |
Returns true if this is a conditional, unconditional, or indirect branch.
Predicates below can be used to discriminate between these cases, and the TargetInstrInfo::AnalyzeBranch method can be used to get more information.
Definition at line 277 of file MCInstrDesc.h.
References llvm::MCID::Branch.
Referenced by countMCSymbolRefExpr(), llvm::PPCDispatchGroupSBHazardRecognizer::EmitInstruction(), llvm::RISCVInstrInfo::getBranchDestBlock(), llvm::HexagonMCInstrInfo::isConstExtended(), llvm::IsCPSRDead< MCInst >(), isPCRel(), mayAffectControlFlow(), raise_relocation_error(), and llvm::HexagonMCChecker::reportBranchErrors().
◆ isCall()
|
inline |
Return true if the instruction is a call.
Definition at line 258 of file MCInstrDesc.h.
References llvm::MCID::Call.
Referenced by llvm::mca::computeMaxLatency(), countMCSymbolRefExpr(), findPotentialBlockers(), llvm::ARMBaseInstrInfo::getOperandLatency(), isControlFlow(), llvm::IsCPSRDead< MCInst >(), isImplicitOperandIn(), mayAffectControlFlow(), raise_relocation_error(), llvm::HexagonMCChecker::reportBranchErrors(), llvm::SelectionDAGISel::runOnMachineFunction(), llvm::ResourcePriorityQueue::SUSchedulingCost(), and llvm::mca::verifyOperands().
◆ isCommutable()
|
inline |
Return true if this may be a 2- or 3-address instruction (of the form "X = op Y, Z, ..."), which produces the same result if Y and Z are exchanged.
If this flag is set, then the TargetInstrInfo::commuteInstruction method may be used to hack on the instruction.
Note that this flag may be set on instructions that are only commutable sometimes. In these cases, the call to commuteInstruction will fail. Also note that some instructions require non-trivial modification to commute them.
Definition at line 437 of file MCInstrDesc.h.
References llvm::MCID::Commutable.
Referenced by llvm::SIInstrInfo::findCommutedOpIndices(), llvm::X86InstrInfo::findCommutedOpIndices(), isOperandOf(), and stripExtractLoElt().
◆ isCompare()
|
inline |
Return true if this instruction is a comparison.
Definition at line 311 of file MCInstrDesc.h.
References llvm::MCID::Compare.
Referenced by getNewValueJumpOpcode().
◆ isConditionalBranch()
|
inline |
Return true if this is a branch which may fall through to the next instruction or may transfer control flow to some other block.
The TargetInstrInfo::AnalyzeBranch method can be used to get more information about this branch.
Definition at line 287 of file MCInstrDesc.h.
References isBranch().
Referenced by parseCondBranch().
◆ isConvergent()
|
inline |
Return true if this instruction is convergent.
Convergent instructions may not be made control-dependent on any additional values.
Definition at line 385 of file MCInstrDesc.h.
References llvm::MCID::Convergent.
◆ isConvertibleTo3Addr()
|
inline |
Return true if this is a 2-address instruction which can be changed into a 3-address instruction if needed.
Doing this transformation can be profitable in the register allocator, because it means that the instruction can use a 2-address form if possible, but degrade into a less efficient form if the source and dest register cannot be assigned to the same register. For example, this allows the x86 backend to turn a "shl reg, 3" instruction into an LEA instruction, which is the same speed as the shift but has bigger code size.
If this returns true, then the target must implement the TargetInstrInfo::convertToThreeAddress method for this instruction, which is allowed to fail if the transformation isn't valid for this specific instruction (e.g. shl reg, 4 on x86).
Definition at line 453 of file MCInstrDesc.h.
References llvm::MCID::ConvertibleTo3Addr.
◆ isExtractSubregLike()
|
inline |
Return true if this instruction behaves the same way as the generic EXTRACT_SUBREG instructions.
E.g., on ARM, rX, rY VMOVRRD dZ is equivalent to two EXTRACT_SUBREG: rX = EXTRACT_SUBREG dZ, ssub_0 rY = EXTRACT_SUBREG dZ, ssub_1
Note that for the optimizers to be able to take advantage of this property, TargetInstrInfo::getExtractSubregLikeInputs has to be override accordingly.
Definition at line 364 of file MCInstrDesc.h.
References llvm::MCID::ExtractSubreg.
◆ isIndirectBranch()
|
inline |
Return true if this is an indirect branch, such as a branch through a register.
Definition at line 281 of file MCInstrDesc.h.
References llvm::MCID::IndirectBranch.
Referenced by llvm::IsCPSRDead< MCInst >(), and mayAffectControlFlow().
◆ isInsertSubregLike()
|
inline |
Return true if this instruction behaves the same way as the generic INSERT_SUBREG instructions.
E.g., on ARM, dX = VSETLNi32 dY, rZ, Imm is equivalent to a INSERT_SUBREG: dX = INSERT_SUBREG dY, rZ, translateImmToSubIdx(Imm)
Note that for the optimizers to be able to take advantage of this property, TargetInstrInfo::getInsertSubregLikeInputs has to be override accordingly.
Definition at line 378 of file MCInstrDesc.h.
References llvm::MCID::InsertSubreg.
◆ isMoveImmediate()
|
inline |
Return true if this instruction is a move immediate (including conditional moves) instruction.
Definition at line 315 of file MCInstrDesc.h.
References llvm::MCID::MoveImm.
◆ isMoveReg()
|
inline |
Return true if the instruction is a register to register move.
Definition at line 255 of file MCInstrDesc.h.
References llvm::MCID::MoveReg.
◆ isNotDuplicable()
|
inline |
Return true if this instruction cannot be safely duplicated.
For example, if the instruction has a unique labels attached to it, duplicating it would cause multiple definition errors.
Definition at line 326 of file MCInstrDesc.h.
References llvm::MCID::NotDuplicable.
◆ isPredicable()
|
inline |
Return true if this instruction has a predicate operand that controls execution.
It may be set to 'always', or may be set to other values. There are various methods in TargetInstrInfo that can be used to control and modify the predicate in this instruction.
Definition at line 308 of file MCInstrDesc.h.
References llvm::MCID::Predicable.
Referenced by llvm::MachineInstr::findFirstPredOperandIdx(), instIsBreakpoint(), llvm::IsCPSRDead< MCInst >(), llvm::HexagonInstrInfo::isPredicable(), llvm::TargetInstrInfo::isPredicable(), and VerifyLowRegs().
◆ isPseudo()
|
inline |
Return true if this is a pseudo instruction that doesn't correspond to a real machine instruction.
Definition at line 243 of file MCInstrDesc.h.
References llvm::MCID::Pseudo.
Referenced by llvm::PPCInstrInfo::FoldImmediate(), llvm::HexagonMCInstrInfo::isCanon(), and makeCombineInst().
◆ isRegSequenceLike()
|
inline |
Return true if this instruction behaves the same way as the generic REG_SEQUENCE instructions.
E.g., on ARM, dX VMOVDRR rY, rZ is equivalent to dX = REG_SEQUENCE rY, ssub_0, rZ, ssub_1.
Note that for the optimizers to be able to take advantage of this property, TargetInstrInfo::getRegSequenceLikeInputs has to be override accordingly.
Definition at line 351 of file MCInstrDesc.h.
References llvm::MCID::RegSequence.
◆ isRematerializable()
|
inline |
Returns true if this instruction is a candidate for remat.
This flag is only used in TargetInstrInfo method isTriviallyRematerializable.
If this flag is set, the isReallyTriviallyReMaterializable() or isReallyTriviallyReMaterializableGeneric methods are called to verify the instruction is really rematable.
Definition at line 481 of file MCInstrDesc.h.
References llvm::MCID::Rematerializable.
Referenced by llvm::TargetInstrInfo::isTriviallyReMaterializable().
◆ isReturn()
|
inline |
Return true if the instruction is a return.
Definition at line 246 of file MCInstrDesc.h.
References llvm::MCID::Return.
Referenced by llvm::HexagonShuffler::check(), llvm::IsCPSRDead< MCInst >(), mayAffectControlFlow(), llvm::HexagonMCChecker::reportBranchErrors(), llvm::SelectionDAGISel::runOnMachineFunction(), and llvm::mca::verifyOperands().
◆ isSelect()
|
inline |
Return true if this is a select instruction.
Definition at line 321 of file MCInstrDesc.h.
References llvm::MCID::Select.
Referenced by llvm::TargetInstrInfo::analyzeSelect().
◆ isTerminator()
|
inline |
Returns true if this instruction part of the terminator for a basic block.
Typically this is things like return and branch instructions.
Various passes use this to insert code into the bottom of a basic block, but before control flow occurs.
Definition at line 271 of file MCInstrDesc.h.
References llvm::MCID::Terminator.
Referenced by isControlFlow(), llvm::IsCPSRDead< MCInst >(), and llvm::HexagonInstrInfo::isSchedulingBoundary().
◆ isTrap()
|
inline |
Return true if this instruction is a trap.
Definition at line 252 of file MCInstrDesc.h.
References llvm::MCID::Trap.
◆ isUnconditionalBranch()
|
inline |
Return true if this is a branch which always transfers control flow to some other block.
The TargetInstrInfo::AnalyzeBranch method can be used to get more information about this branch.
Definition at line 295 of file MCInstrDesc.h.
References isBranch().
◆ isVariadic()
|
inline |
Return true if this instruction can have a variable number of operands.
In this case, the variable operands will be after the normal operands but before the implicit definitions and uses (if any are present).
Definition at line 235 of file MCInstrDesc.h.
References llvm::MCID::Variadic.
Referenced by llvm::MachineInstr::addOperand(), llvm::InstrEmitter::EmitDbgLabel(), llvm::MachineInstr::getNumExplicitDefs(), llvm::MachineInstr::getNumExplicitOperands(), isUseSafeToFold(), llvm::WebAssemblyInstPrinter::printInst(), and llvm::SIInstrInfo::verifyInstruction().
◆ mayAffectControlFlow()
| bool MCInstrDesc::mayAffectControlFlow | ( | const MCInst & | MI, |
| const MCRegisterInfo & | RI | ||
| ) | const |
Return true if this is a branch or an instruction which directly writes to the program counter.
Considered 'may' affect rather than 'does' affect as things like predication are not taken into account.
Definition at line 33 of file MCInstrDesc.cpp.
References llvm::MCRegisterInfo::getProgramCounter(), hasDefOfPhysReg(), isBranch(), isCall(), isIndirectBranch(), and isReturn().
◆ mayLoad()
|
inline |
Return true if this instruction could possibly read memory.
Instructions with this flag set are not necessarily simple load instructions, they may load a value and modify it, for example.
Definition at line 399 of file MCInstrDesc.h.
References llvm::MCID::MayLoad.
Referenced by llvm::addFrameReference(), llvm::HexagonShuffler::check(), countMCSymbolRefExpr(), llvm::HexagonInstrInfo::getNonExtOpcode(), llvm::ARMBaseInstrInfo::getNumMicroOps(), llvm::ARMBaseInstrInfo::getOperandLatency(), getSpecialRegForName(), llvm::HexagonInstrInfo::hasNonExtEquivalent(), llvm::HexagonInstrInfo::isComplex(), llvm::PPCHazardRecognizer970::PPCHazardRecognizer970(), llvm::HexagonMCChecker::reportBranchErrors(), llvm::SelectionDAGISel::SelectCodeCommon(), and llvm::mca::verifyOperands().
◆ mayStore()
|
inline |
Return true if this instruction could possibly modify memory.
Instructions with this flag set are not necessarily simple store instructions, they may store a modified value based on their operands, or may not actually modify anything, for example.
Definition at line 405 of file MCInstrDesc.h.
References llvm::MCID::MayStore.
Referenced by llvm::addFrameReference(), buildMUBUFOffsetLoadStore(), llvm::HexagonShuffler::check(), countMCSymbolRefExpr(), llvm::HexagonInstrInfo::getNonExtOpcode(), llvm::ARMBaseInstrInfo::getNumMicroOps(), getPostIncrementOperand(), getSpecialRegForName(), llvm::HexagonInstrInfo::hasNonExtEquivalent(), llvm::HexagonInstrInfo::isComplex(), llvm::PPCHazardRecognizer970::PPCHazardRecognizer970(), llvm::HexagonMCChecker::reportBranchErrors(), rewritesSort(), llvm::SelectionDAGISel::SelectCodeCommon(), and llvm::mca::verifyOperands().
◆ operands()
|
inline |
Definition at line 218 of file MCInstrDesc.h.
References llvm::make_range().
◆ opInfo_begin()
|
inline |
Definition at line 215 of file MCInstrDesc.h.
Referenced by llvm::LegalizerInfo::verify().
◆ opInfo_end()
|
inline |
Definition at line 216 of file MCInstrDesc.h.
Referenced by llvm::LegalizerInfo::verify().
◆ usesCustomInsertionHook()
|
inline |
Return true if this instruction requires custom insertion support when the DAG scheduler is inserting it into a machine basic block.
If this is true for the instruction, it basically means that it is a pseudo instruction used at SelectionDAG time that is expanded out into magic code by the target when MachineInstrs are formed.
If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method is used to insert this into the MachineBasicBlock.
Definition at line 465 of file MCInstrDesc.h.
References llvm::MCID::UsesCustomInserter.
◆ variadicOpsAreDefs()
|
inline |
Return true if variadic operands of this instruction are definitions.
Definition at line 388 of file MCInstrDesc.h.
References llvm::MCID::VariadicOpsAreDefs.
Referenced by hasDefOfPhysReg().
Member Data Documentation
◆ ComplexDeprecationInfo
| bool(* llvm::MCInstrDesc::ComplexDeprecationInfo) (MCInst &, const MCSubtargetInfo &, std::string &) |
Definition at line 183 of file MCInstrDesc.h.
Referenced by getDeprecatedInfo().
◆ DeprecatedFeature
| int64_t llvm::MCInstrDesc::DeprecatedFeature |
Definition at line 179 of file MCInstrDesc.h.
Referenced by getDeprecatedInfo().
◆ Flags
| uint64_t llvm::MCInstrDesc::Flags |
Definition at line 171 of file MCInstrDesc.h.
◆ ImplicitDefs
Definition at line 174 of file MCInstrDesc.h.
Referenced by llvm::MachineInstr::addImplicitDefUseOperands(), CheckForPhysRegDependency(), computeBytesPoppedByCalleeForSRet(), llvm::FastISel::fastEmitInst_f(), llvm::FastISel::fastEmitInst_i(), llvm::FastISel::fastEmitInst_r(), llvm::FastISel::fastEmitInst_ri(), llvm::FastISel::fastEmitInst_rii(), llvm::FastISel::fastEmitInst_rr(), llvm::FastISel::fastEmitInst_rri(), llvm::FastISel::fastEmitInst_rrr(), getPhysicalRegisterVT(), hasImplicitDefOfPhysReg(), INITIALIZE_PASS(), isImplicitOperandIn(), and llvm::PPCInstrInfo::optimizeCompareInstr().
◆ ImplicitUses
Definition at line 173 of file MCInstrDesc.h.
Referenced by llvm::MachineInstr::addImplicitDefUseOperands(), getSpecialRegForName(), INITIALIZE_PASS(), isImplicitOperandIn(), and llvm::PPCInstrInfo::optimizeCompareInstr().
◆ NumDefs
Definition at line 168 of file MCInstrDesc.h.
Referenced by hasDefOfPhysReg(), and llvm::X86InstrInfo::unfoldMemoryOperand().
◆ NumOperands
| unsigned short llvm::MCInstrDesc::NumOperands |
Definition at line 167 of file MCInstrDesc.h.
Referenced by AddThumb1SBit(), getRealVLDOpcode(), llvm::AMDGPU::getRegOperandSize(), hasDefOfPhysReg(), llvm::SIInstrInfo::isInlineConstant(), isRegOrImmWithInputMods(), llvm::AMDGPU::isSISrcFPOperand(), llvm::AMDGPU::isSISrcInlinableOperand(), llvm::AMDGPU::isSISrcOperand(), llvm::MipsSEInstrInfo::loadImmediate(), llvm::WebAssemblyMCInstLower::Lower(), and llvm::WebAssemblyInstPrinter::printInst().
◆ Opcode
| unsigned short llvm::MCInstrDesc::Opcode |
Definition at line 166 of file MCInstrDesc.h.
Referenced by llvm::ScoreboardHazardRecognizer::EmitInstruction(), llvm::MachineInstr::getOpcode(), and llvm::ARMBaseInstrInfo::getOperandLatency().
◆ OpInfo
| const MCOperandInfo* llvm::MCInstrDesc::OpInfo |
Definition at line 175 of file MCInstrDesc.h.
Referenced by addRegsToSet(), AddThumb1SBit(), llvm::TargetSchedModel::computeOperandLatency(), countMCSymbolRefExpr(), llvm::createR600ISelDag(), llvm::X86AsmPrinter::EmitInstruction(), llvm::MachineInstr::findFirstPredOperandIdx(), findSingleRegDef(), llvm::PPCInstrInfo::FoldImmediate(), llvm::LegalizerInfo::getAction(), llvm::SIInstrInfo::getInstSizeInBytes(), getLit64Encoding(), llvm::AMDGPU::getOperandSize(), llvm::SIInstrInfo::getOpRegClass(), getRealVLDOpcode(), llvm::TargetInstrInfo::getRegClass(), llvm::AMDGPU::getRegOperandSize(), getSpecialRegForName(), llvm::MachineInstr::getTypeToPrint(), llvm::SIInstrInfo::isBufferSMRD(), llvm::SIInstrInfo::isInlineConstant(), isInlineConstantIfFolded(), llvm::SIInstrInfo::isOperandLegal(), isRegOrImmWithInputMods(), llvm::AMDGPU::isSISrcFPOperand(), llvm::AMDGPU::isSISrcInlinableOperand(), llvm::AMDGPU::isSISrcOperand(), isUseSafeToFold(), llvm::SIInstrInfo::legalizeOperandsVOP2(), llvm::WebAssemblyMCInstLower::Lower(), matchPair(), llvm::SIInstrInfo::moveToVALU(), needsPCRel(), nextReg(), llvm::HexagonMCInstrInfo::predicateInfo(), llvm::WebAssemblyInstPrinter::printInst(), llvm::WebAssemblyInstPrinter::printOperand(), llvm::AMDGPUInstPrinter::printRegOperand(), llvm::HexagonMCChecker::reportBranchErrors(), RewriteP2Align(), llvm::SIInstrInfo::verifyInstruction(), and VerifyLowRegs().
◆ SchedClass
| unsigned short llvm::MCInstrDesc::SchedClass |
Definition at line 170 of file MCInstrDesc.h.
◆ Size
Definition at line 169 of file MCInstrDesc.h.
◆ TSFlags
| uint64_t llvm::MCInstrDesc::TSFlags |
Definition at line 172 of file MCInstrDesc.h.
Referenced by llvm::X86_MC::X86MCInstrAnalysis::clearsSuperRegisters(), llvm::X86InstrInfo::commuteInstructionImpl(), commuteVPTERNLOG(), llvm::ARMBaseInstrInfo::convertToThreeAddress(), countMCSymbolRefExpr(), llvm::createR600MCCodeEmitter(), llvm::createRISCVMCCodeEmitter(), llvm::createX86OptimizeLEAs(), llvm::ARMBaseRegisterInfo::eliminateFrameIndex(), llvm::X86InstrInfo::findCommutedOpIndices(), llvm::SystemZInstrInfo::foldMemoryOperandImpl(), llvm::HexagonMCInstrInfo::getAddrMode(), llvm::HexagonInstrInfo::getAddrMode(), getAddrOffset(), llvm::HexagonInstrInfo::getCExtOpNum(), llvm::SIInstrInfo::getClampMask(), getCompareSourceReg(), llvm::ARMBaseInstrInfo::getExecutionDomain(), llvm::X86InstrInfo::getExecutionDomain(), llvm::HexagonMCInstrInfo::getExtendableOp(), llvm::HexagonMCInstrInfo::getExtentAlignment(), llvm::HexagonMCInstrInfo::getExtentBits(), llvm::X86InstrInfo::getFMA3OpcodeToCommuteOperands(), getFPReg(), llvm::ARMBaseRegisterInfo::getFrameIndexInstrOffset(), llvm::ARMHazardRecognizer::getHazardType(), llvm::HexagonInstrInfo::getMaxValue(), llvm::HexagonMCInstrInfo::getMemAccessSize(), llvm::HexagonInstrInfo::getMemAccessSize(), llvm::X86InstrInfo::getMemOperandWithOffset(), llvm::HexagonInstrInfo::getMinValue(), llvm::HexagonMCInstrInfo::getNewValueOp(), llvm::HexagonMCInstrInfo::getNewValueOp2(), llvm::SystemZInstrInfo::getOpcodeForOffset(), getRealVLDOpcode(), llvm::PPCInstrInfo::getRegNumForOperand(), getSpecialRegForName(), getTruncatedShiftCount(), llvm::HexagonInstrInfo::getType(), HasConditionalBranch(), llvm::MipsInstrInfo::HasForbiddenSlot(), llvm::SIInstrInfo::hasFPClamp(), llvm::SIInstrInfo::hasIntClamp(), llvm::HexagonMCInstrInfo::hasNewValue(), llvm::HexagonMCInstrInfo::hasNewValue2(), hasRAWHazard(), HasSecRelSymbolRef(), llvm::HexagonMCInstrInfo::hasTmpDst(), llvm::HexagonMCInstrInfo::isAccumulator(), llvm::HexagonInstrInfo::isAccumulator(), llvm::HexagonInstrInfo::isAddrModeWithOffset(), llvm::HexagonMCInstrInfo::isCofMax1(), llvm::HexagonMCInstrInfo::isCofRelax1(), llvm::HexagonMCInstrInfo::isCofRelax2(), llvm::HexagonInstrInfo::isConstExtended(), llvm::HexagonMCInstrInfo::isCVINew(), llvm::SIInstrInfo::isDisableWQM(), llvm::SIInstrInfo::isDPP(), llvm::SIInstrInfo::isDS(), isEFLAGSLive(), llvm::SIInstrInfo::isEXP(), llvm::HexagonMCInstrInfo::isExtendable(), llvm::HexagonInstrInfo::isExtendable(), llvm::HexagonMCInstrInfo::isExtended(), llvm::HexagonInstrInfo::isExtended(), llvm::HexagonMCInstrInfo::isExtentSigned(), llvm::SIInstrInfo::isFixedSize(), llvm::SIInstrInfo::isFLAT(), llvm::HexagonMCInstrInfo::isFloat(), isFpMulInstruction(), llvm::ARMBaseRegisterInfo::isFrameOffsetLegal(), llvm::SIInstrInfo::isGather4(), isLEASimpleIncOrDec(), isMatchingOrAlias(), llvm::SIInstrInfo::isMIMG(), llvm::SIInstrInfo::isMTBUF(), llvm::SIInstrInfo::isMUBUF(), llvm::HexagonMCInstrInfo::isNewValue(), llvm::HexagonInstrInfo::isNewValue(), llvm::HexagonInstrInfo::isNewValueStore(), llvm::HexagonInstrInfo::isOperandExtended(), llvm::ARMBaseInstrInfo::isPredicable(), llvm::HexagonInstrInfo::isPredicated(), llvm::HexagonMCInstrInfo::isPredicated(), llvm::HexagonMCInstrInfo::isPredicatedNew(), llvm::HexagonInstrInfo::isPredicatedNew(), llvm::HexagonMCInstrInfo::isPredicatedTrue(), llvm::HexagonInstrInfo::isPredicatedTrue(), llvm::HexagonMCInstrInfo::isPredicateLate(), isRegOrImmWithInputMods(), llvm::HexagonMCInstrInfo::isRestrictNoSlot1Store(), llvm::HexagonMCInstrInfo::isRestrictSlot1AOK(), llvm::SIInstrInfo::isSALU(), llvm::SIInstrInfo::isScalarStore(), llvm::SIInstrInfo::isScalarUnit(), llvm::SIInstrInfo::isSDWA(), llvm::SIInstrInfo::isSegmentSpecificFLAT(), llvm::SIInstrInfo::isSGPRSpill(), isSimpleBD12Move(), isSimpleMove(), llvm::SIInstrInfo::isSMRD(), llvm::HexagonInstrInfo::isSolo(), llvm::HexagonMCInstrInfo::isSoloAX(), llvm::SIInstrInfo::isSOP1(), llvm::SIInstrInfo::isSOP2(), llvm::SIInstrInfo::isSOPC(), llvm::SIInstrInfo::isSOPK(), llvm::SIInstrInfo::isSOPP(), llvm::SIInstrInfo::isVALU(), llvm::SIInstrInfo::isVGPRSpill(), llvm::SIInstrInfo::isVINTRP(), llvm::SIInstrInfo::isVOP1(), llvm::SIInstrInfo::isVOP2(), llvm::SIInstrInfo::isVOP3(), llvm::SIInstrInfo::isVOP3P(), llvm::SIInstrInfo::isVOPC(), llvm::SIInstrInfo::isWQM(), llvm::HexagonInstrInfo::mayBeCurLoad(), llvm::HexagonInstrInfo::mayBeNewStore(), performCustomAdjustments(), llvm::PPCHazardRecognizer970::PPCHazardRecognizer970(), llvm::HexagonMCInstrInfo::prefersSlot3(), llvm::X86InstPrinterCommon::printInstFlags(), printMasking(), llvm::rewriteARMFrameIndex(), llvm::ThumbRegisterInfo::rewriteFrameIndex(), llvm::rewriteT2FrameIndex(), llvm::MipsInstrInfo::SafeInForbiddenSlot(), llvm::X86InstrInfo::setExecutionDomain(), llvm::X86InstrInfo::setExecutionDomainCustom(), llvm::SIInstrInfo::sopkIsZext(), updateOperand(), usedAsAddr(), llvm::SIInstrInfo::usesFPDPRounding(), llvm::SIInstrInfo::usesLGKM_CNT(), llvm::SIInstrInfo::usesVM_CNT(), and VisitGlobalVariableForEmission().
The documentation for this class was generated from the following files:
- include/llvm/MC/MCInstrDesc.h
- lib/MC/MCInstrDesc.cpp
