38 #define GET_REGINFO_TARGET_DESC 39 #include "X86GenRegisterInfo.inc" 43 cl::desc(
"Enable use of a base pointer for complex stack frames"));
49 (TT.isArch64Bit() ? X86::RIP : X86::EIP)) {
65 StackPtr = Use64BitReg ? X86::RSP :
X86::ESP;
66 FramePtr = Use64BitReg ? X86::RBP : X86::EBP;
67 BasePtr = Use64BitReg ? X86::RBX :
X86::EBX;
84 return getEncodingValue(i);
92 if (!Is64Bit && Idx == X86::sub_8bit)
93 Idx = X86::sub_8bit_hi;
96 return X86GenRegisterInfo::getSubClassWithSubReg(RC, Idx);
102 unsigned SubIdx)
const {
104 if (!Is64Bit && SubIdx == X86::sub_8bit) {
105 A = X86GenRegisterInfo::getSubClassWithSubReg(A, X86::sub_8bit_hi);
109 return X86GenRegisterInfo::getMatchingSuperRegClass(A, B, SubIdx);
123 if (RC == &X86::GR8_NOREXRegClass)
131 switch (Super->getID()) {
132 case X86::FR32RegClassID:
133 case X86::FR64RegClassID:
136 getRegSizeInBits(*Super) == getRegSizeInBits(*RC))
139 case X86::VR128RegClassID:
140 case X86::VR256RegClassID:
142 if (!Subtarget.
hasVLX() &&
143 getRegSizeInBits(*Super) == getRegSizeInBits(*RC))
146 case X86::VR128XRegClassID:
147 case X86::VR256XRegClassID:
150 getRegSizeInBits(*Super) == getRegSizeInBits(*RC))
153 case X86::FR32XRegClassID:
154 case X86::FR64XRegClassID:
157 getRegSizeInBits(*Super) == getRegSizeInBits(*RC))
160 case X86::GR8RegClassID:
161 case X86::GR16RegClassID:
162 case X86::GR32RegClassID:
163 case X86::GR64RegClassID:
164 case X86::RFP32RegClassID:
165 case X86::RFP64RegClassID:
166 case X86::RFP80RegClassID:
167 case X86::VR512RegClassID:
170 if (getRegSizeInBits(*Super) == getRegSizeInBits(*RC))
180 unsigned Kind)
const {
186 return &X86::GR64RegClass;
196 ? &X86::LOW32_ADDR_ACCESS_RBPRegClass
197 : &X86::LOW32_ADDR_ACCESSRegClass;
199 return &X86::GR32RegClass;
202 return &X86::GR64_NOSPRegClass;
204 return &X86::GR32_NOSPRegClass;
207 return &X86::GR64_NOREXRegClass;
208 return &X86::GR32_NOREXRegClass;
211 return &X86::GR64_NOREX_NOSPRegClass;
213 return &X86::GR32_NOREX_NOSPRegClass;
223 return &X86::GR64_TCW64RegClass;
225 return &X86::GR64_TCRegClass;
229 return &X86::GR32RegClass;
230 return &X86::GR32_TCRegClass;
235 if (RC == &X86::CCRRegClass) {
237 return &X86::GR64RegClass;
239 return &X86::GR32RegClass;
249 unsigned FPDiff = TFI->
hasFP(MF) ? 1 : 0;
250 switch (RC->
getID()) {
253 case X86::GR32RegClassID:
255 case X86::GR64RegClassID:
257 case X86::VR128RegClassID:
258 return Is64Bit ? 10 : 4;
259 case X86::VR64RegClassID:
266 assert(MF &&
"MachineFunction required");
270 bool HasSSE = Subtarget.
hasSSE1();
271 bool HasAVX = Subtarget.
hasAVX();
285 return CSR_NoRegs_SaveList;
288 return CSR_64_AllRegs_AVX_SaveList;
289 return CSR_64_AllRegs_SaveList;
291 return CSR_64_RT_MostRegs_SaveList;
294 return CSR_64_RT_AllRegs_AVX_SaveList;
295 return CSR_64_RT_AllRegs_SaveList;
299 CSR_64_CXX_TLS_Darwin_PE_SaveList : CSR_64_TLS_Darwin_SaveList;
302 if (HasAVX512 && IsWin64)
303 return CSR_Win64_Intel_OCL_BI_AVX512_SaveList;
304 if (HasAVX512 && Is64Bit)
305 return CSR_64_Intel_OCL_BI_AVX512_SaveList;
306 if (HasAVX && IsWin64)
307 return CSR_Win64_Intel_OCL_BI_AVX_SaveList;
308 if (HasAVX && Is64Bit)
309 return CSR_64_Intel_OCL_BI_AVX_SaveList;
310 if (!HasAVX && !IsWin64 && Is64Bit)
311 return CSR_64_Intel_OCL_BI_SaveList;
315 return CSR_64_HHVM_SaveList;
319 return (HasSSE ? CSR_Win64_RegCall_SaveList :
320 CSR_Win64_RegCall_NoSSE_SaveList);
322 return (HasSSE ? CSR_SysV64_RegCall_SaveList :
323 CSR_SysV64_RegCall_NoSSE_SaveList);
326 return (HasSSE ? CSR_32_RegCall_SaveList :
327 CSR_32_RegCall_NoSSE_SaveList);
331 return CSR_64_MostRegs_SaveList;
335 return CSR_Win64_NoSSE_SaveList;
336 return CSR_Win64_SaveList;
339 return CSR_64EHRet_SaveList;
340 return CSR_64_SaveList;
344 return CSR_64_AllRegs_AVX512_SaveList;
346 return CSR_64_AllRegs_AVX_SaveList;
348 return CSR_64_AllRegs_SaveList;
349 return CSR_64_AllRegs_NoSSE_SaveList;
352 return CSR_32_AllRegs_AVX512_SaveList;
354 return CSR_32_AllRegs_AVX_SaveList;
356 return CSR_32_AllRegs_SSE_SaveList;
357 return CSR_32_AllRegs_SaveList;
367 return IsWin64 ? CSR_Win64_SwiftError_SaveList
368 : CSR_64_SwiftError_SaveList;
371 return HasSSE ? CSR_Win64_SaveList : CSR_Win64_NoSSE_SaveList;
373 return CSR_64EHRet_SaveList;
374 return CSR_64_SaveList;
377 return CallsEHReturn ? CSR_32EHRet_SaveList : CSR_32_SaveList;
382 assert(MF &&
"Invalid MachineFunction pointer.");
385 return CSR_64_CXX_TLS_Darwin_ViaCopy_SaveList;
393 bool HasSSE = Subtarget.
hasSSE1();
394 bool HasAVX = Subtarget.
hasAVX();
400 return CSR_NoRegs_RegMask;
403 return CSR_64_AllRegs_AVX_RegMask;
404 return CSR_64_AllRegs_RegMask;
406 return CSR_64_RT_MostRegs_RegMask;
409 return CSR_64_RT_AllRegs_AVX_RegMask;
410 return CSR_64_RT_AllRegs_RegMask;
413 return CSR_64_TLS_Darwin_RegMask;
416 if (HasAVX512 && IsWin64)
417 return CSR_Win64_Intel_OCL_BI_AVX512_RegMask;
418 if (HasAVX512 && Is64Bit)
419 return CSR_64_Intel_OCL_BI_AVX512_RegMask;
420 if (HasAVX && IsWin64)
421 return CSR_Win64_Intel_OCL_BI_AVX_RegMask;
422 if (HasAVX && Is64Bit)
423 return CSR_64_Intel_OCL_BI_AVX_RegMask;
424 if (!HasAVX && !IsWin64 && Is64Bit)
425 return CSR_64_Intel_OCL_BI_RegMask;
429 return CSR_64_HHVM_RegMask;
433 return (HasSSE ? CSR_Win64_RegCall_RegMask :
434 CSR_Win64_RegCall_NoSSE_RegMask);
436 return (HasSSE ? CSR_SysV64_RegCall_RegMask :
437 CSR_SysV64_RegCall_NoSSE_RegMask);
440 return (HasSSE ? CSR_32_RegCall_RegMask :
441 CSR_32_RegCall_NoSSE_RegMask);
445 return CSR_64_MostRegs_RegMask;
448 return CSR_Win64_RegMask;
450 return CSR_64_RegMask;
454 return CSR_64_AllRegs_AVX512_RegMask;
456 return CSR_64_AllRegs_AVX_RegMask;
458 return CSR_64_AllRegs_RegMask;
459 return CSR_64_AllRegs_NoSSE_RegMask;
462 return CSR_32_AllRegs_AVX512_RegMask;
464 return CSR_32_AllRegs_AVX_RegMask;
466 return CSR_32_AllRegs_SSE_RegMask;
467 return CSR_32_AllRegs_RegMask;
480 return IsWin64 ? CSR_Win64_SwiftError_RegMask : CSR_64_SwiftError_RegMask;
481 return IsWin64 ? CSR_Win64_RegMask : CSR_64_RegMask;
484 return CSR_32_RegMask;
489 return CSR_NoRegs_RegMask;
493 return CSR_64_TLS_Darwin_RegMask;
501 Reserved.
set(X86::FPCW);
509 Reserved.
set(X86::SSP);
517 if (TFI->
hasFP(MF)) {
529 "Stack realignment in presence of dynamic allocas is not supported with" 530 "this calling convention.");
539 Reserved.
set(X86::CS);
540 Reserved.
set(X86::SS);
542 Reserved.
set(X86::ES);
543 Reserved.
set(X86::FS);
544 Reserved.
set(X86::GS);
547 for (
unsigned n = 0; n != 8; ++n)
548 Reserved.
set(X86::ST0 + n);
554 Reserved.
set(X86::SIL);
555 Reserved.
set(X86::DIL);
556 Reserved.
set(X86::BPL);
557 Reserved.
set(X86::SPL);
558 Reserved.
set(X86::SIH);
559 Reserved.
set(X86::DIH);
560 Reserved.
set(X86::BPH);
561 Reserved.
set(X86::SPH);
563 for (
unsigned n = 0; n != 8; ++n) {
574 for (
unsigned n = 16; n != 32; ++n) {
580 assert(checkAllSuperRegsMarked(Reserved,
581 {X86::SIL, X86::DIL, X86::BPL, X86::SPL,
582 X86::SIH, X86::DIH, X86::BPH, X86::SPH}));
594 assert(!(Mask[X86::EFLAGS / 32] & (1U << (X86::EFLAGS % 32))) &&
595 "EFLAGS are not live-out from a patchpoint.");
598 for (
auto Reg : {X86::EFLAGS, X86::RIP, X86::EIP, X86::IP})
599 Mask[
Reg / 32] &= ~(1U << (
Reg % 32));
621 bool CantUseFP = needsStackRealignment(MF);
645 unsigned Reg,
int &FrameIdx)
const {
657 unsigned Opc = II->getOpcode();
659 if ((Opc != X86::LEA32r && Opc != X86::LEA64r && Opc != X86::LEA64_32r) ||
669 if (Opc == X86::LEA64_32r)
682 int SPAdj,
unsigned FIOperandNum,
693 assert((!needsStackRealignment(MF) ||
695 "Return instruction can only reference SP relative frame objects");
707 if (Opc == TargetOpcode::LOCAL_ESCAPE) {
717 unsigned MachineBasePtr = BasePtr;
718 if (Opc == X86::LEA64_32r && X86::GR32RegClass.
contains(BasePtr))
725 if (BasePtr == StackPtr)
730 if (Opc == TargetOpcode::STACKMAP || Opc == TargetOpcode::PATCHPOINT) {
731 assert(BasePtr == FramePtr &&
"Expected the FP as base register");
740 int Offset = FIOffset + Imm;
742 "Requesting 64-bit offset in 32-bit immediate!");
747 uint64_t
Offset = FIOffset +
755 return TFI->
hasFP(MF) ? FramePtr : StackPtr;
const TargetRegisterClass * getMatchingSuperRegClass(const TargetRegisterClass *A, const TargetRegisterClass *B, unsigned Idx) const override
getMatchingSuperRegClass - Return a subclass of the specified register class A so that each register ...
bool hasBasePointer(const MachineFunction &MF) const
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
This class represents lattice values for constants.
unsigned getRegPressureLimit(const TargetRegisterClass *RC, MachineFunction &MF) const override
static bool tryOptimizeLEAtoMOV(MachineBasicBlock::iterator II)
void ChangeToRegister(unsigned Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isDebug=false)
ChangeToRegister - Replace this operand with a new register operand of the specified value...
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
bool hasOpaqueSPAdjustment() const
Returns true if the function contains opaque dynamic stack adjustments.
unsigned getReg() const
getReg - Returns the register number.
const TargetRegisterClass * getGPRsForTailCall(const MachineFunction &MF) const
getGPRsForTailCall - Returns a register class with registers that can be used in forming tail calls...
Register calling convention used for parameters transfer optimization.
The C convention as implemented on Windows/x86-64 and AArch64.
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
unsigned getPtrSizedFrameRegister(const MachineFunction &MF) const
block Block Frequency true
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
unsigned getDwarfRegFlavour(const Triple &TT, bool isEH)
return AArch64::GPR64RegClass contains(Reg)
X86MachineFunctionInfo - This class is derived from MachineFunction and contains private X86 target-s...
bool Uses64BitFramePtr
True if the 64-bit frame or stack pointer should be used.
X86RegisterInfo(const Triple &TT)
const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const override
getPointerRegClass - Returns a TargetRegisterClass used for pointer values.
bool supportSwiftError() const override
Return true if the target supports swifterror attribute.
const HexagonInstrInfo * TII
bool isTarget64BitLP64() const
Is this x86_64 with the LP64 programming model (standard AMD64, no x32)?
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
virtual bool canRealignStack(const MachineFunction &MF) const
True if the stack can be realigned for the target.
const MCPhysReg * getCalleeSavedRegsViaCopy(const MachineFunction *MF) const
const TargetRegisterClass *const * sc_iterator
unsigned getID() const
Return the register class ID number.
unsigned getBaseRegister() const
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register...
static cl::opt< bool > EnableBasePointer("x86-use-base-pointer", cl::Hidden, cl::init(true), cl::desc("Enable use of a base pointer for complex stack frames"))
bool canReserveReg(unsigned PhysReg) const
canReserveReg - Returns true if PhysReg can be used as a reserved register.
AttributeList getAttributes() const
Return the attribute list for this Function.
BitVector getReservedRegs(const MachineFunction &MF) const override
getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a ...
void adjustStackMapLiveOutMask(uint32_t *Mask) const override
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
void ChangeToImmediate(int64_t ImmVal)
ChangeToImmediate - Replace this operand with a new immediate operand of the specified value...
bool isReturn(QueryType Type=AnyInBundle) const
bool isOSWindows() const
Tests whether the OS is Windows.
const X86TargetLowering * getTargetLowering() const override
bool hasAttrSomewhere(Attribute::AttrKind Kind, unsigned *Index=nullptr) const
Return true if the specified attribute is set for at least one parameter or for the return value...
const TargetRegisterClass * getLargestLegalSuperClass(const TargetRegisterClass *RC, const MachineFunction &MF) const override
bool hasReservedSpillSlot(const MachineFunction &MF, unsigned Reg, int &FrameIdx) const override
sc_iterator getSuperClasses() const
Returns a NULL-terminated list of super-classes.
initializer< Ty > init(const Ty &Val)
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
unsigned const MachineRegisterInfo * MRI
bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override
Code Generation virtual methods...
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
const uint32_t * getNoPreservedMask() const override
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
This file contains the declarations for the subclasses of Constant, which represent the different fla...
bool isFixedObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a fixed stack object.
MCRegAliasIterator enumerates all registers aliasing Reg.
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const override
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
The C convention as specified in the x86-64 supplement to the System V ABI, used on most non-Windows ...
int getSEHRegNum(unsigned i) const
void setOffset(int64_t Offset)
MCSubRegIterator enumerates all sub-registers of Reg.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Triple - Helper class for working with autoconf configuration names.
void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override
constexpr bool isInt< 32 >(int64_t x)
void initLLVMToSEHAndCVRegMapping(MCRegisterInfo *MRI)
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
MachineOperand class - Representation of each machine instruction operand.
EnvironmentType getEnvironment() const
getEnvironment - Get the parsed environment type of this triple.
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
getCalleeSavedRegs - Return a null-terminated list of all of the callee-save registers on this target...
const TargetRegisterClass * getCrossCopyRegClass(const TargetRegisterClass *RC) const override
getCrossCopyRegClass - Returns a legal register class to copy a register in the specified class to or...
const Function & getFunction() const
Return the LLVM function that this machine code represents.
bool isTarget64BitILP32() const
Is this x86_64 with the ILP32 programming model (x32 ABI)?
bool callsEHReturn() const
unsigned getX86SubSuperRegister(unsigned, unsigned, bool High=false)
Returns the sub or super register of a specific X86 register.
const uint32_t * getDarwinTLSCallPreservedMask() const
static bool clobbersPhysReg(const uint32_t *RegMask, unsigned PhysReg)
clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
const MachineBasicBlock * getParent() const
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
int getFrameIndexReferenceSP(const MachineFunction &MF, int FI, unsigned &SPReg, int Adjustment) const
Representation of each machine instruction.
Intel_OCL_BI - Calling conventions for Intel OpenCL built-ins.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
bool isArch64Bit() const
Test whether the architecture is 64-bit.
int64_t getOffset() const
Return the offset from the symbol in this operand.
const TargetRegisterClass * getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const override
Calling convention used by HipHop Virtual Machine (HHVM) to perform calls to and from translation cac...
X86_INTR - x86 hardware interrupt context.
bool canRealignStack(const MachineFunction &MF) const override
static bool CantUseSP(const MachineFrameInfo &MFI)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
int getFrameIndexReference(const MachineFunction &MF, int FI, unsigned &FrameReg) const override
getFrameIndexReference - This method should return the base register and offset used to reference a f...
unsigned getFrameRegister(const MachineFunction &MF) const override
const MachineOperand & getOperand(unsigned i) const