LLVM  8.0.1
ARMExpandPseudoInsts.cpp
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1 //===-- ARMExpandPseudoInsts.cpp - Expand pseudo instructions -------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains a pass that expands pseudo instructions into target
11 // instructions to allow proper scheduling, if-conversion, and other late
12 // optimizations. This pass should be run after register allocation but before
13 // the post-regalloc scheduling pass.
14 //
15 //===----------------------------------------------------------------------===//
16 
17 #include "ARM.h"
18 #include "ARMBaseInstrInfo.h"
19 #include "ARMBaseRegisterInfo.h"
20 #include "ARMConstantPoolValue.h"
21 #include "ARMMachineFunctionInfo.h"
22 #include "ARMSubtarget.h"
23 #include "MCTargetDesc/ARMAddressingModes.h"
24 #include "llvm/CodeGen/LivePhysRegs.h"
25 #include "llvm/CodeGen/MachineFrameInfo.h"
26 #include "llvm/CodeGen/MachineFunctionPass.h"
27 
28 using namespace llvm;
29 
30 #define DEBUG_TYPE "arm-pseudo"
31 
32 static cl::opt<bool>
33 VerifyARMPseudo("verify-arm-pseudo-expand", cl::Hidden,
34  cl::desc("Verify machine code after expanding ARM pseudos"));
35 
36 #define ARM_EXPAND_PSEUDO_NAME "ARM pseudo instruction expansion pass"
37 
38 namespace {
39  class ARMExpandPseudo : public MachineFunctionPass {
40  public:
41  static char ID;
42  ARMExpandPseudo() : MachineFunctionPass(ID) {}
43 
44  const ARMBaseInstrInfo *TII;
45  const TargetRegisterInfo *TRI;
46  const ARMSubtarget *STI;
47  ARMFunctionInfo *AFI;
48 
49  bool runOnMachineFunction(MachineFunction &Fn) override;
50 
51  MachineFunctionProperties getRequiredProperties() const override {
52  return MachineFunctionProperties().set(
53  MachineFunctionProperties::Property::NoVRegs);
54  }
55 
56  StringRef getPassName() const override {
57  return ARM_EXPAND_PSEUDO_NAME;
58  }
59 
60  private:
61  void TransferImpOps(MachineInstr &OldMI,
62  MachineInstrBuilder &UseMI, MachineInstrBuilder &DefMI);
63  bool ExpandMI(MachineBasicBlock &MBB,
64  MachineBasicBlock::iterator MBBI,
65  MachineBasicBlock::iterator &NextMBBI);
66  bool ExpandMBB(MachineBasicBlock &MBB);
67  void ExpandVLD(MachineBasicBlock::iterator &MBBI);
68  void ExpandVST(MachineBasicBlock::iterator &MBBI);
69  void ExpandLaneOp(MachineBasicBlock::iterator &MBBI);
70  void ExpandVTBL(MachineBasicBlock::iterator &MBBI,
71  unsigned Opc, bool IsExt);
72  void ExpandMOV32BitImm(MachineBasicBlock &MBB,
73  MachineBasicBlock::iterator &MBBI);
74  bool ExpandCMP_SWAP(MachineBasicBlock &MBB,
75  MachineBasicBlock::iterator MBBI, unsigned LdrexOp,
76  unsigned StrexOp, unsigned UxtOp,
77  MachineBasicBlock::iterator &NextMBBI);
78 
79  bool ExpandCMP_SWAP_64(MachineBasicBlock &MBB,
80  MachineBasicBlock::iterator MBBI,
81  MachineBasicBlock::iterator &NextMBBI);
82  };
83  char ARMExpandPseudo::ID = 0;
84 }
85 
86 INITIALIZE_PASS(ARMExpandPseudo, DEBUG_TYPE, ARM_EXPAND_PSEUDO_NAME, false,
87  false)
88 
89 /// TransferImpOps - Transfer implicit operands on the pseudo instruction to
90 /// the instructions created from the expansion.
91 void ARMExpandPseudo::TransferImpOps(MachineInstr &OldMI,
92  MachineInstrBuilder &UseMI,
93  MachineInstrBuilder &DefMI) {
94  const MCInstrDesc &Desc = OldMI.getDesc();
95  for (unsigned i = Desc.getNumOperands(), e = OldMI.getNumOperands();
96  i != e; ++i) {
97  const MachineOperand &MO = OldMI.getOperand(i);
98  assert(MO.isReg() && MO.getReg());
99  if (MO.isUse())
100  UseMI.add(MO);
101  else
102  DefMI.add(MO);
103  }
104 }
105 
106 namespace {
107  // Constants for register spacing in NEON load/store instructions.
108  // For quad-register load-lane and store-lane pseudo instructors, the
109  // spacing is initially assumed to be EvenDblSpc, and that is changed to
110  // OddDblSpc depending on the lane number operand.
111  enum NEONRegSpacing {
112  SingleSpc,
113  SingleLowSpc , // Single spacing, low registers, three and four vectors.
114  SingleHighQSpc, // Single spacing, high registers, four vectors.
115  SingleHighTSpc, // Single spacing, high registers, three vectors.
116  EvenDblSpc,
117  OddDblSpc
118  };
119 
120  // Entries for NEON load/store information table. The table is sorted by
121  // PseudoOpc for fast binary-search lookups.
122  struct NEONLdStTableEntry {
123  uint16_t PseudoOpc;
124  uint16_t RealOpc;
125  bool IsLoad;
126  bool isUpdating;
127  bool hasWritebackOperand;
128  uint8_t RegSpacing; // One of type NEONRegSpacing
129  uint8_t NumRegs; // D registers loaded or stored
130  uint8_t RegElts; // elements per D register; used for lane ops
131  // FIXME: Temporary flag to denote whether the real instruction takes
132  // a single register (like the encoding) or all of the registers in
133  // the list (like the asm syntax and the isel DAG). When all definitions
134  // are converted to take only the single encoded register, this will
135  // go away.
136  bool copyAllListRegs;
137 
138  // Comparison methods for binary search of the table.
139  bool operator<(const NEONLdStTableEntry &TE) const {
140  return PseudoOpc < TE.PseudoOpc;
141  }
142  friend bool operator<(const NEONLdStTableEntry &TE, unsigned PseudoOpc) {
143  return TE.PseudoOpc < PseudoOpc;
144  }
145  friend bool LLVM_ATTRIBUTE_UNUSED operator<(unsigned PseudoOpc,
146  const NEONLdStTableEntry &TE) {
147  return PseudoOpc < TE.PseudoOpc;
148  }
149  };
150 }
151 
152 static const NEONLdStTableEntry NEONLdStTable[] = {
153 { ARM::VLD1LNq16Pseudo, ARM::VLD1LNd16, true, false, false, EvenDblSpc, 1, 4 ,true},
154 { ARM::VLD1LNq16Pseudo_UPD, ARM::VLD1LNd16_UPD, true, true, true, EvenDblSpc, 1, 4 ,true},
155 { ARM::VLD1LNq32Pseudo, ARM::VLD1LNd32, true, false, false, EvenDblSpc, 1, 2 ,true},
156 { ARM::VLD1LNq32Pseudo_UPD, ARM::VLD1LNd32_UPD, true, true, true, EvenDblSpc, 1, 2 ,true},
157 { ARM::VLD1LNq8Pseudo, ARM::VLD1LNd8, true, false, false, EvenDblSpc, 1, 8 ,true},
158 { ARM::VLD1LNq8Pseudo_UPD, ARM::VLD1LNd8_UPD, true, true, true, EvenDblSpc, 1, 8 ,true},
159 
160 { ARM::VLD1d16QPseudo, ARM::VLD1d16Q, true, false, false, SingleSpc, 4, 4 ,false},
161 { ARM::VLD1d16TPseudo, ARM::VLD1d16T, true, false, false, SingleSpc, 3, 4 ,false},
162 { ARM::VLD1d32QPseudo, ARM::VLD1d32Q, true, false, false, SingleSpc, 4, 2 ,false},
163 { ARM::VLD1d32TPseudo, ARM::VLD1d32T, true, false, false, SingleSpc, 3, 2 ,false},
164 { ARM::VLD1d64QPseudo, ARM::VLD1d64Q, true, false, false, SingleSpc, 4, 1 ,false},
165 { ARM::VLD1d64QPseudoWB_fixed, ARM::VLD1d64Qwb_fixed, true, true, false, SingleSpc, 4, 1 ,false},
166 { ARM::VLD1d64QPseudoWB_register, ARM::VLD1d64Qwb_register, true, true, true, SingleSpc, 4, 1 ,false},
167 { ARM::VLD1d64TPseudo, ARM::VLD1d64T, true, false, false, SingleSpc, 3, 1 ,false},
168 { ARM::VLD1d64TPseudoWB_fixed, ARM::VLD1d64Twb_fixed, true, true, false, SingleSpc, 3, 1 ,false},
169 { ARM::VLD1d64TPseudoWB_register, ARM::VLD1d64Twb_register, true, true, true, SingleSpc, 3, 1 ,false},
170 { ARM::VLD1d8QPseudo, ARM::VLD1d8Q, true, false, false, SingleSpc, 4, 8 ,false},
171 { ARM::VLD1d8TPseudo, ARM::VLD1d8T, true, false, false, SingleSpc, 3, 8 ,false},
172 { ARM::VLD1q16HighQPseudo, ARM::VLD1d16Q, true, false, false, SingleHighQSpc, 4, 4 ,false},
173 { ARM::VLD1q16HighTPseudo, ARM::VLD1d16T, true, false, false, SingleHighTSpc, 3, 4 ,false},
174 { ARM::VLD1q16LowQPseudo_UPD, ARM::VLD1d16Qwb_fixed, true, true, true, SingleLowSpc, 4, 4 ,false},
175 { ARM::VLD1q16LowTPseudo_UPD, ARM::VLD1d16Twb_fixed, true, true, true, SingleLowSpc, 3, 4 ,false},
176 { ARM::VLD1q32HighQPseudo, ARM::VLD1d32Q, true, false, false, SingleHighQSpc, 4, 2 ,false},
177 { ARM::VLD1q32HighTPseudo, ARM::VLD1d32T, true, false, false, SingleHighTSpc, 3, 2 ,false},
178 { ARM::VLD1q32LowQPseudo_UPD, ARM::VLD1d32Qwb_fixed, true, true, true, SingleLowSpc, 4, 2 ,false},
179 { ARM::VLD1q32LowTPseudo_UPD, ARM::VLD1d32Twb_fixed, true, true, true, SingleLowSpc, 3, 2 ,false},
180 { ARM::VLD1q64HighQPseudo, ARM::VLD1d64Q, true, false, false, SingleHighQSpc, 4, 1 ,false},
181 { ARM::VLD1q64HighTPseudo, ARM::VLD1d64T, true, false, false, SingleHighTSpc, 3, 1 ,false},
182 { ARM::VLD1q64LowQPseudo_UPD, ARM::VLD1d64Qwb_fixed, true, true, true, SingleLowSpc, 4, 1 ,false},
183 { ARM::VLD1q64LowTPseudo_UPD, ARM::VLD1d64Twb_fixed, true, true, true, SingleLowSpc, 3, 1 ,false},
184 { ARM::VLD1q8HighQPseudo, ARM::VLD1d8Q, true, false, false, SingleHighQSpc, 4, 8 ,false},
185 { ARM::VLD1q8HighTPseudo, ARM::VLD1d8T, true, false, false, SingleHighTSpc, 3, 8 ,false},
186 { ARM::VLD1q8LowQPseudo_UPD, ARM::VLD1d8Qwb_fixed, true, true, true, SingleLowSpc, 4, 8 ,false},
187 { ARM::VLD1q8LowTPseudo_UPD, ARM::VLD1d8Twb_fixed, true, true, true, SingleLowSpc, 3, 8 ,false},
188 
189 { ARM::VLD2DUPq16EvenPseudo, ARM::VLD2DUPd16x2, true, false, false, EvenDblSpc, 2, 4 ,false},
190 { ARM::VLD2DUPq16OddPseudo, ARM::VLD2DUPd16x2, true, false, false, OddDblSpc, 2, 4 ,false},
191 { ARM::VLD2DUPq32EvenPseudo, ARM::VLD2DUPd32x2, true, false, false, EvenDblSpc, 2, 2 ,false},
192 { ARM::VLD2DUPq32OddPseudo, ARM::VLD2DUPd32x2, true, false, false, OddDblSpc, 2, 2 ,false},
193 { ARM::VLD2DUPq8EvenPseudo, ARM::VLD2DUPd8x2, true, false, false, EvenDblSpc, 2, 8 ,false},
194 { ARM::VLD2DUPq8OddPseudo, ARM::VLD2DUPd8x2, true, false, false, OddDblSpc, 2, 8 ,false},
195 
196 { ARM::VLD2LNd16Pseudo, ARM::VLD2LNd16, true, false, false, SingleSpc, 2, 4 ,true},
197 { ARM::VLD2LNd16Pseudo_UPD, ARM::VLD2LNd16_UPD, true, true, true, SingleSpc, 2, 4 ,true},
198 { ARM::VLD2LNd32Pseudo, ARM::VLD2LNd32, true, false, false, SingleSpc, 2, 2 ,true},
199 { ARM::VLD2LNd32Pseudo_UPD, ARM::VLD2LNd32_UPD, true, true, true, SingleSpc, 2, 2 ,true},
200 { ARM::VLD2LNd8Pseudo, ARM::VLD2LNd8, true, false, false, SingleSpc, 2, 8 ,true},
201 { ARM::VLD2LNd8Pseudo_UPD, ARM::VLD2LNd8_UPD, true, true, true, SingleSpc, 2, 8 ,true},
202 { ARM::VLD2LNq16Pseudo, ARM::VLD2LNq16, true, false, false, EvenDblSpc, 2, 4 ,true},
203 { ARM::VLD2LNq16Pseudo_UPD, ARM::VLD2LNq16_UPD, true, true, true, EvenDblSpc, 2, 4 ,true},
204 { ARM::VLD2LNq32Pseudo, ARM::VLD2LNq32, true, false, false, EvenDblSpc, 2, 2 ,true},
205 { ARM::VLD2LNq32Pseudo_UPD, ARM::VLD2LNq32_UPD, true, true, true, EvenDblSpc, 2, 2 ,true},
206 
207 { ARM::VLD2q16Pseudo, ARM::VLD2q16, true, false, false, SingleSpc, 4, 4 ,false},
208 { ARM::VLD2q16PseudoWB_fixed, ARM::VLD2q16wb_fixed, true, true, false, SingleSpc, 4, 4 ,false},
209 { ARM::VLD2q16PseudoWB_register, ARM::VLD2q16wb_register, true, true, true, SingleSpc, 4, 4 ,false},
210 { ARM::VLD2q32Pseudo, ARM::VLD2q32, true, false, false, SingleSpc, 4, 2 ,false},
211 { ARM::VLD2q32PseudoWB_fixed, ARM::VLD2q32wb_fixed, true, true, false, SingleSpc, 4, 2 ,false},
212 { ARM::VLD2q32PseudoWB_register, ARM::VLD2q32wb_register, true, true, true, SingleSpc, 4, 2 ,false},
213 { ARM::VLD2q8Pseudo, ARM::VLD2q8, true, false, false, SingleSpc, 4, 8 ,false},
214 { ARM::VLD2q8PseudoWB_fixed, ARM::VLD2q8wb_fixed, true, true, false, SingleSpc, 4, 8 ,false},
215 { ARM::VLD2q8PseudoWB_register, ARM::VLD2q8wb_register, true, true, true, SingleSpc, 4, 8 ,false},
216 
217 { ARM::VLD3DUPd16Pseudo, ARM::VLD3DUPd16, true, false, false, SingleSpc, 3, 4,true},
218 { ARM::VLD3DUPd16Pseudo_UPD, ARM::VLD3DUPd16_UPD, true, true, true, SingleSpc, 3, 4,true},
219 { ARM::VLD3DUPd32Pseudo, ARM::VLD3DUPd32, true, false, false, SingleSpc, 3, 2,true},
220 { ARM::VLD3DUPd32Pseudo_UPD, ARM::VLD3DUPd32_UPD, true, true, true, SingleSpc, 3, 2,true},
221 { ARM::VLD3DUPd8Pseudo, ARM::VLD3DUPd8, true, false, false, SingleSpc, 3, 8,true},
222 { ARM::VLD3DUPd8Pseudo_UPD, ARM::VLD3DUPd8_UPD, true, true, true, SingleSpc, 3, 8,true},
223 { ARM::VLD3DUPq16EvenPseudo, ARM::VLD3DUPq16, true, false, false, EvenDblSpc, 3, 4 ,true},
224 { ARM::VLD3DUPq16OddPseudo, ARM::VLD3DUPq16, true, false, false, OddDblSpc, 3, 4 ,true},
225 { ARM::VLD3DUPq32EvenPseudo, ARM::VLD3DUPq32, true, false, false, EvenDblSpc, 3, 2 ,true},
226 { ARM::VLD3DUPq32OddPseudo, ARM::VLD3DUPq32, true, false, false, OddDblSpc, 3, 2 ,true},
227 { ARM::VLD3DUPq8EvenPseudo, ARM::VLD3DUPq8, true, false, false, EvenDblSpc, 3, 8 ,true},
228 { ARM::VLD3DUPq8OddPseudo, ARM::VLD3DUPq8, true, false, false, OddDblSpc, 3, 8 ,true},
229 
230 { ARM::VLD3LNd16Pseudo, ARM::VLD3LNd16, true, false, false, SingleSpc, 3, 4 ,true},
231 { ARM::VLD3LNd16Pseudo_UPD, ARM::VLD3LNd16_UPD, true, true, true, SingleSpc, 3, 4 ,true},
232 { ARM::VLD3LNd32Pseudo, ARM::VLD3LNd32, true, false, false, SingleSpc, 3, 2 ,true},
233 { ARM::VLD3LNd32Pseudo_UPD, ARM::VLD3LNd32_UPD, true, true, true, SingleSpc, 3, 2 ,true},
234 { ARM::VLD3LNd8Pseudo, ARM::VLD3LNd8, true, false, false, SingleSpc, 3, 8 ,true},
235 { ARM::VLD3LNd8Pseudo_UPD, ARM::VLD3LNd8_UPD, true, true, true, SingleSpc, 3, 8 ,true},
236 { ARM::VLD3LNq16Pseudo, ARM::VLD3LNq16, true, false, false, EvenDblSpc, 3, 4 ,true},
237 { ARM::VLD3LNq16Pseudo_UPD, ARM::VLD3LNq16_UPD, true, true, true, EvenDblSpc, 3, 4 ,true},
238 { ARM::VLD3LNq32Pseudo, ARM::VLD3LNq32, true, false, false, EvenDblSpc, 3, 2 ,true},
239 { ARM::VLD3LNq32Pseudo_UPD, ARM::VLD3LNq32_UPD, true, true, true, EvenDblSpc, 3, 2 ,true},
240 
241 { ARM::VLD3d16Pseudo, ARM::VLD3d16, true, false, false, SingleSpc, 3, 4 ,true},
242 { ARM::VLD3d16Pseudo_UPD, ARM::VLD3d16_UPD, true, true, true, SingleSpc, 3, 4 ,true},
243 { ARM::VLD3d32Pseudo, ARM::VLD3d32, true, false, false, SingleSpc, 3, 2 ,true},
244 { ARM::VLD3d32Pseudo_UPD, ARM::VLD3d32_UPD, true, true, true, SingleSpc, 3, 2 ,true},
245 { ARM::VLD3d8Pseudo, ARM::VLD3d8, true, false, false, SingleSpc, 3, 8 ,true},
246 { ARM::VLD3d8Pseudo_UPD, ARM::VLD3d8_UPD, true, true, true, SingleSpc, 3, 8 ,true},
247 
248 { ARM::VLD3q16Pseudo_UPD, ARM::VLD3q16_UPD, true, true, true, EvenDblSpc, 3, 4 ,true},
249 { ARM::VLD3q16oddPseudo, ARM::VLD3q16, true, false, false, OddDblSpc, 3, 4 ,true},
250 { ARM::VLD3q16oddPseudo_UPD, ARM::VLD3q16_UPD, true, true, true, OddDblSpc, 3, 4 ,true},
251 { ARM::VLD3q32Pseudo_UPD, ARM::VLD3q32_UPD, true, true, true, EvenDblSpc, 3, 2 ,true},
252 { ARM::VLD3q32oddPseudo, ARM::VLD3q32, true, false, false, OddDblSpc, 3, 2 ,true},
253 { ARM::VLD3q32oddPseudo_UPD, ARM::VLD3q32_UPD, true, true, true, OddDblSpc, 3, 2 ,true},
254 { ARM::VLD3q8Pseudo_UPD, ARM::VLD3q8_UPD, true, true, true, EvenDblSpc, 3, 8 ,true},
255 { ARM::VLD3q8oddPseudo, ARM::VLD3q8, true, false, false, OddDblSpc, 3, 8 ,true},
256 { ARM::VLD3q8oddPseudo_UPD, ARM::VLD3q8_UPD, true, true, true, OddDblSpc, 3, 8 ,true},
257 
258 { ARM::VLD4DUPd16Pseudo, ARM::VLD4DUPd16, true, false, false, SingleSpc, 4, 4,true},
259 { ARM::VLD4DUPd16Pseudo_UPD, ARM::VLD4DUPd16_UPD, true, true, true, SingleSpc, 4, 4,true},
260 { ARM::VLD4DUPd32Pseudo, ARM::VLD4DUPd32, true, false, false, SingleSpc, 4, 2,true},
261 { ARM::VLD4DUPd32Pseudo_UPD, ARM::VLD4DUPd32_UPD, true, true, true, SingleSpc, 4, 2,true},
262 { ARM::VLD4DUPd8Pseudo, ARM::VLD4DUPd8, true, false, false, SingleSpc, 4, 8,true},
263 { ARM::VLD4DUPd8Pseudo_UPD, ARM::VLD4DUPd8_UPD, true, true, true, SingleSpc, 4, 8,true},
264 { ARM::VLD4DUPq16EvenPseudo, ARM::VLD4DUPq16, true, false, false, EvenDblSpc, 4, 4 ,true},
265 { ARM::VLD4DUPq16OddPseudo, ARM::VLD4DUPq16, true, false, false, OddDblSpc, 4, 4 ,true},
266 { ARM::VLD4DUPq32EvenPseudo, ARM::VLD4DUPq32, true, false, false, EvenDblSpc, 4, 2 ,true},
267 { ARM::VLD4DUPq32OddPseudo, ARM::VLD4DUPq32, true, false, false, OddDblSpc, 4, 2 ,true},
268 { ARM::VLD4DUPq8EvenPseudo, ARM::VLD4DUPq8, true, false, false, EvenDblSpc, 4, 8 ,true},
269 { ARM::VLD4DUPq8OddPseudo, ARM::VLD4DUPq8, true, false, false, OddDblSpc, 4, 8 ,true},
270 
271 { ARM::VLD4LNd16Pseudo, ARM::VLD4LNd16, true, false, false, SingleSpc, 4, 4 ,true},
272 { ARM::VLD4LNd16Pseudo_UPD, ARM::VLD4LNd16_UPD, true, true, true, SingleSpc, 4, 4 ,true},
273 { ARM::VLD4LNd32Pseudo, ARM::VLD4LNd32, true, false, false, SingleSpc, 4, 2 ,true},
274 { ARM::VLD4LNd32Pseudo_UPD, ARM::VLD4LNd32_UPD, true, true, true, SingleSpc, 4, 2 ,true},
275 { ARM::VLD4LNd8Pseudo, ARM::VLD4LNd8, true, false, false, SingleSpc, 4, 8 ,true},
276 { ARM::VLD4LNd8Pseudo_UPD, ARM::VLD4LNd8_UPD, true, true, true, SingleSpc, 4, 8 ,true},
277 { ARM::VLD4LNq16Pseudo, ARM::VLD4LNq16, true, false, false, EvenDblSpc, 4, 4 ,true},
278 { ARM::VLD4LNq16Pseudo_UPD, ARM::VLD4LNq16_UPD, true, true, true, EvenDblSpc, 4, 4 ,true},
279 { ARM::VLD4LNq32Pseudo, ARM::VLD4LNq32, true, false, false, EvenDblSpc, 4, 2 ,true},
280 { ARM::VLD4LNq32Pseudo_UPD, ARM::VLD4LNq32_UPD, true, true, true, EvenDblSpc, 4, 2 ,true},
281 
282 { ARM::VLD4d16Pseudo, ARM::VLD4d16, true, false, false, SingleSpc, 4, 4 ,true},
283 { ARM::VLD4d16Pseudo_UPD, ARM::VLD4d16_UPD, true, true, true, SingleSpc, 4, 4 ,true},
284 { ARM::VLD4d32Pseudo, ARM::VLD4d32, true, false, false, SingleSpc, 4, 2 ,true},
285 { ARM::VLD4d32Pseudo_UPD, ARM::VLD4d32_UPD, true, true, true, SingleSpc, 4, 2 ,true},
286 { ARM::VLD4d8Pseudo, ARM::VLD4d8, true, false, false, SingleSpc, 4, 8 ,true},
287 { ARM::VLD4d8Pseudo_UPD, ARM::VLD4d8_UPD, true, true, true, SingleSpc, 4, 8 ,true},
288 
289 { ARM::VLD4q16Pseudo_UPD, ARM::VLD4q16_UPD, true, true, true, EvenDblSpc, 4, 4 ,true},
290 { ARM::VLD4q16oddPseudo, ARM::VLD4q16, true, false, false, OddDblSpc, 4, 4 ,true},
291 { ARM::VLD4q16oddPseudo_UPD, ARM::VLD4q16_UPD, true, true, true, OddDblSpc, 4, 4 ,true},
292 { ARM::VLD4q32Pseudo_UPD, ARM::VLD4q32_UPD, true, true, true, EvenDblSpc, 4, 2 ,true},
293 { ARM::VLD4q32oddPseudo, ARM::VLD4q32, true, false, false, OddDblSpc, 4, 2 ,true},
294 { ARM::VLD4q32oddPseudo_UPD, ARM::VLD4q32_UPD, true, true, true, OddDblSpc, 4, 2 ,true},
295 { ARM::VLD4q8Pseudo_UPD, ARM::VLD4q8_UPD, true, true, true, EvenDblSpc, 4, 8 ,true},
296 { ARM::VLD4q8oddPseudo, ARM::VLD4q8, true, false, false, OddDblSpc, 4, 8 ,true},
297 { ARM::VLD4q8oddPseudo_UPD, ARM::VLD4q8_UPD, true, true, true, OddDblSpc, 4, 8 ,true},
298 
299 { ARM::VST1LNq16Pseudo, ARM::VST1LNd16, false, false, false, EvenDblSpc, 1, 4 ,true},
300 { ARM::VST1LNq16Pseudo_UPD, ARM::VST1LNd16_UPD, false, true, true, EvenDblSpc, 1, 4 ,true},
301 { ARM::VST1LNq32Pseudo, ARM::VST1LNd32, false, false, false, EvenDblSpc, 1, 2 ,true},
302 { ARM::VST1LNq32Pseudo_UPD, ARM::VST1LNd32_UPD, false, true, true, EvenDblSpc, 1, 2 ,true},
303 { ARM::VST1LNq8Pseudo, ARM::VST1LNd8, false, false, false, EvenDblSpc, 1, 8 ,true},
304 { ARM::VST1LNq8Pseudo_UPD, ARM::VST1LNd8_UPD, false, true, true, EvenDblSpc, 1, 8 ,true},
305 
306 { ARM::VST1d16QPseudo, ARM::VST1d16Q, false, false, false, SingleSpc, 4, 4 ,false},
307 { ARM::VST1d16TPseudo, ARM::VST1d16T, false, false, false, SingleSpc, 3, 4 ,false},
308 { ARM::VST1d32QPseudo, ARM::VST1d32Q, false, false, false, SingleSpc, 4, 2 ,false},
309 { ARM::VST1d32TPseudo, ARM::VST1d32T, false, false, false, SingleSpc, 3, 2 ,false},
310 { ARM::VST1d64QPseudo, ARM::VST1d64Q, false, false, false, SingleSpc, 4, 1 ,false},
311 { ARM::VST1d64QPseudoWB_fixed, ARM::VST1d64Qwb_fixed, false, true, false, SingleSpc, 4, 1 ,false},
312 { ARM::VST1d64QPseudoWB_register, ARM::VST1d64Qwb_register, false, true, true, SingleSpc, 4, 1 ,false},
313 { ARM::VST1d64TPseudo, ARM::VST1d64T, false, false, false, SingleSpc, 3, 1 ,false},
314 { ARM::VST1d64TPseudoWB_fixed, ARM::VST1d64Twb_fixed, false, true, false, SingleSpc, 3, 1 ,false},
315 { ARM::VST1d64TPseudoWB_register, ARM::VST1d64Twb_register, false, true, true, SingleSpc, 3, 1 ,false},
316 { ARM::VST1d8QPseudo, ARM::VST1d8Q, false, false, false, SingleSpc, 4, 8 ,false},
317 { ARM::VST1d8TPseudo, ARM::VST1d8T, false, false, false, SingleSpc, 3, 8 ,false},
318 { ARM::VST1q16HighQPseudo, ARM::VST1d16Q, false, false, false, SingleHighQSpc, 4, 4 ,false},
319 { ARM::VST1q16HighTPseudo, ARM::VST1d16T, false, false, false, SingleHighTSpc, 3, 4 ,false},
320 { ARM::VST1q16LowQPseudo_UPD, ARM::VST1d16Qwb_fixed, false, true, true, SingleLowSpc, 4, 4 ,false},
321 { ARM::VST1q16LowTPseudo_UPD, ARM::VST1d16Twb_fixed, false, true, true, SingleLowSpc, 3, 4 ,false},
322 { ARM::VST1q32HighQPseudo, ARM::VST1d32Q, false, false, false, SingleHighQSpc, 4, 2 ,false},
323 { ARM::VST1q32HighTPseudo, ARM::VST1d32T, false, false, false, SingleHighTSpc, 3, 2 ,false},
324 { ARM::VST1q32LowQPseudo_UPD, ARM::VST1d32Qwb_fixed, false, true, true, SingleLowSpc, 4, 2 ,false},
325 { ARM::VST1q32LowTPseudo_UPD, ARM::VST1d32Twb_fixed, false, true, true, SingleLowSpc, 3, 2 ,false},
326 { ARM::VST1q64HighQPseudo, ARM::VST1d64Q, false, false, false, SingleHighQSpc, 4, 1 ,false},
327 { ARM::VST1q64HighTPseudo, ARM::VST1d64T, false, false, false, SingleHighTSpc, 3, 1 ,false},
328 { ARM::VST1q64LowQPseudo_UPD, ARM::VST1d64Qwb_fixed, false, true, true, SingleLowSpc, 4, 1 ,false},
329 { ARM::VST1q64LowTPseudo_UPD, ARM::VST1d64Twb_fixed, false, true, true, SingleLowSpc, 3, 1 ,false},
330 { ARM::VST1q8HighQPseudo, ARM::VST1d8Q, false, false, false, SingleHighQSpc, 4, 8 ,false},
331 { ARM::VST1q8HighTPseudo, ARM::VST1d8T, false, false, false, SingleHighTSpc, 3, 8 ,false},
332 { ARM::VST1q8LowQPseudo_UPD, ARM::VST1d8Qwb_fixed, false, true, true, SingleLowSpc, 4, 8 ,false},
333 { ARM::VST1q8LowTPseudo_UPD, ARM::VST1d8Twb_fixed, false, true, true, SingleLowSpc, 3, 8 ,false},
334 
335 { ARM::VST2LNd16Pseudo, ARM::VST2LNd16, false, false, false, SingleSpc, 2, 4 ,true},
336 { ARM::VST2LNd16Pseudo_UPD, ARM::VST2LNd16_UPD, false, true, true, SingleSpc, 2, 4 ,true},
337 { ARM::VST2LNd32Pseudo, ARM::VST2LNd32, false, false, false, SingleSpc, 2, 2 ,true},
338 { ARM::VST2LNd32Pseudo_UPD, ARM::VST2LNd32_UPD, false, true, true, SingleSpc, 2, 2 ,true},
339 { ARM::VST2LNd8Pseudo, ARM::VST2LNd8, false, false, false, SingleSpc, 2, 8 ,true},
340 { ARM::VST2LNd8Pseudo_UPD, ARM::VST2LNd8_UPD, false, true, true, SingleSpc, 2, 8 ,true},
341 { ARM::VST2LNq16Pseudo, ARM::VST2LNq16, false, false, false, EvenDblSpc, 2, 4,true},
342 { ARM::VST2LNq16Pseudo_UPD, ARM::VST2LNq16_UPD, false, true, true, EvenDblSpc, 2, 4,true},
343 { ARM::VST2LNq32Pseudo, ARM::VST2LNq32, false, false, false, EvenDblSpc, 2, 2,true},
344 { ARM::VST2LNq32Pseudo_UPD, ARM::VST2LNq32_UPD, false, true, true, EvenDblSpc, 2, 2,true},
345 
346 { ARM::VST2q16Pseudo, ARM::VST2q16, false, false, false, SingleSpc, 4, 4 ,false},
347 { ARM::VST2q16PseudoWB_fixed, ARM::VST2q16wb_fixed, false, true, false, SingleSpc, 4, 4 ,false},
348 { ARM::VST2q16PseudoWB_register, ARM::VST2q16wb_register, false, true, true, SingleSpc, 4, 4 ,false},
349 { ARM::VST2q32Pseudo, ARM::VST2q32, false, false, false, SingleSpc, 4, 2 ,false},
350 { ARM::VST2q32PseudoWB_fixed, ARM::VST2q32wb_fixed, false, true, false, SingleSpc, 4, 2 ,false},
351 { ARM::VST2q32PseudoWB_register, ARM::VST2q32wb_register, false, true, true, SingleSpc, 4, 2 ,false},
352 { ARM::VST2q8Pseudo, ARM::VST2q8, false, false, false, SingleSpc, 4, 8 ,false},
353 { ARM::VST2q8PseudoWB_fixed, ARM::VST2q8wb_fixed, false, true, false, SingleSpc, 4, 8 ,false},
354 { ARM::VST2q8PseudoWB_register, ARM::VST2q8wb_register, false, true, true, SingleSpc, 4, 8 ,false},
355 
356 { ARM::VST3LNd16Pseudo, ARM::VST3LNd16, false, false, false, SingleSpc, 3, 4 ,true},
357 { ARM::VST3LNd16Pseudo_UPD, ARM::VST3LNd16_UPD, false, true, true, SingleSpc, 3, 4 ,true},
358 { ARM::VST3LNd32Pseudo, ARM::VST3LNd32, false, false, false, SingleSpc, 3, 2 ,true},
359 { ARM::VST3LNd32Pseudo_UPD, ARM::VST3LNd32_UPD, false, true, true, SingleSpc, 3, 2 ,true},
360 { ARM::VST3LNd8Pseudo, ARM::VST3LNd8, false, false, false, SingleSpc, 3, 8 ,true},
361 { ARM::VST3LNd8Pseudo_UPD, ARM::VST3LNd8_UPD, false, true, true, SingleSpc, 3, 8 ,true},
362 { ARM::VST3LNq16Pseudo, ARM::VST3LNq16, false, false, false, EvenDblSpc, 3, 4,true},
363 { ARM::VST3LNq16Pseudo_UPD, ARM::VST3LNq16_UPD, false, true, true, EvenDblSpc, 3, 4,true},
364 { ARM::VST3LNq32Pseudo, ARM::VST3LNq32, false, false, false, EvenDblSpc, 3, 2,true},
365 { ARM::VST3LNq32Pseudo_UPD, ARM::VST3LNq32_UPD, false, true, true, EvenDblSpc, 3, 2,true},
366 
367 { ARM::VST3d16Pseudo, ARM::VST3d16, false, false, false, SingleSpc, 3, 4 ,true},
368 { ARM::VST3d16Pseudo_UPD, ARM::VST3d16_UPD, false, true, true, SingleSpc, 3, 4 ,true},
369 { ARM::VST3d32Pseudo, ARM::VST3d32, false, false, false, SingleSpc, 3, 2 ,true},
370 { ARM::VST3d32Pseudo_UPD, ARM::VST3d32_UPD, false, true, true, SingleSpc, 3, 2 ,true},
371 { ARM::VST3d8Pseudo, ARM::VST3d8, false, false, false, SingleSpc, 3, 8 ,true},
372 { ARM::VST3d8Pseudo_UPD, ARM::VST3d8_UPD, false, true, true, SingleSpc, 3, 8 ,true},
373 
374 { ARM::VST3q16Pseudo_UPD, ARM::VST3q16_UPD, false, true, true, EvenDblSpc, 3, 4 ,true},
375 { ARM::VST3q16oddPseudo, ARM::VST3q16, false, false, false, OddDblSpc, 3, 4 ,true},
376 { ARM::VST3q16oddPseudo_UPD, ARM::VST3q16_UPD, false, true, true, OddDblSpc, 3, 4 ,true},
377 { ARM::VST3q32Pseudo_UPD, ARM::VST3q32_UPD, false, true, true, EvenDblSpc, 3, 2 ,true},
378 { ARM::VST3q32oddPseudo, ARM::VST3q32, false, false, false, OddDblSpc, 3, 2 ,true},
379 { ARM::VST3q32oddPseudo_UPD, ARM::VST3q32_UPD, false, true, true, OddDblSpc, 3, 2 ,true},
380 { ARM::VST3q8Pseudo_UPD, ARM::VST3q8_UPD, false, true, true, EvenDblSpc, 3, 8 ,true},
381 { ARM::VST3q8oddPseudo, ARM::VST3q8, false, false, false, OddDblSpc, 3, 8 ,true},
382 { ARM::VST3q8oddPseudo_UPD, ARM::VST3q8_UPD, false, true, true, OddDblSpc, 3, 8 ,true},
383 
384 { ARM::VST4LNd16Pseudo, ARM::VST4LNd16, false, false, false, SingleSpc, 4, 4 ,true},
385 { ARM::VST4LNd16Pseudo_UPD, ARM::VST4LNd16_UPD, false, true, true, SingleSpc, 4, 4 ,true},
386 { ARM::VST4LNd32Pseudo, ARM::VST4LNd32, false, false, false, SingleSpc, 4, 2 ,true},
387 { ARM::VST4LNd32Pseudo_UPD, ARM::VST4LNd32_UPD, false, true, true, SingleSpc, 4, 2 ,true},
388 { ARM::VST4LNd8Pseudo, ARM::VST4LNd8, false, false, false, SingleSpc, 4, 8 ,true},
389 { ARM::VST4LNd8Pseudo_UPD, ARM::VST4LNd8_UPD, false, true, true, SingleSpc, 4, 8 ,true},
390 { ARM::VST4LNq16Pseudo, ARM::VST4LNq16, false, false, false, EvenDblSpc, 4, 4,true},
391 { ARM::VST4LNq16Pseudo_UPD, ARM::VST4LNq16_UPD, false, true, true, EvenDblSpc, 4, 4,true},
392 { ARM::VST4LNq32Pseudo, ARM::VST4LNq32, false, false, false, EvenDblSpc, 4, 2,true},
393 { ARM::VST4LNq32Pseudo_UPD, ARM::VST4LNq32_UPD, false, true, true, EvenDblSpc, 4, 2,true},
394 
395 { ARM::VST4d16Pseudo, ARM::VST4d16, false, false, false, SingleSpc, 4, 4 ,true},
396 { ARM::VST4d16Pseudo_UPD, ARM::VST4d16_UPD, false, true, true, SingleSpc, 4, 4 ,true},
397 { ARM::VST4d32Pseudo, ARM::VST4d32, false, false, false, SingleSpc, 4, 2 ,true},
398 { ARM::VST4d32Pseudo_UPD, ARM::VST4d32_UPD, false, true, true, SingleSpc, 4, 2 ,true},
399 { ARM::VST4d8Pseudo, ARM::VST4d8, false, false, false, SingleSpc, 4, 8 ,true},
400 { ARM::VST4d8Pseudo_UPD, ARM::VST4d8_UPD, false, true, true, SingleSpc, 4, 8 ,true},
401 
402 { ARM::VST4q16Pseudo_UPD, ARM::VST4q16_UPD, false, true, true, EvenDblSpc, 4, 4 ,true},
403 { ARM::VST4q16oddPseudo, ARM::VST4q16, false, false, false, OddDblSpc, 4, 4 ,true},
404 { ARM::VST4q16oddPseudo_UPD, ARM::VST4q16_UPD, false, true, true, OddDblSpc, 4, 4 ,true},
405 { ARM::VST4q32Pseudo_UPD, ARM::VST4q32_UPD, false, true, true, EvenDblSpc, 4, 2 ,true},
406 { ARM::VST4q32oddPseudo, ARM::VST4q32, false, false, false, OddDblSpc, 4, 2 ,true},
407 { ARM::VST4q32oddPseudo_UPD, ARM::VST4q32_UPD, false, true, true, OddDblSpc, 4, 2 ,true},
408 { ARM::VST4q8Pseudo_UPD, ARM::VST4q8_UPD, false, true, true, EvenDblSpc, 4, 8 ,true},
409 { ARM::VST4q8oddPseudo, ARM::VST4q8, false, false, false, OddDblSpc, 4, 8 ,true},
410 { ARM::VST4q8oddPseudo_UPD, ARM::VST4q8_UPD, false, true, true, OddDblSpc, 4, 8 ,true}
411 };
412 
413 /// LookupNEONLdSt - Search the NEONLdStTable for information about a NEON
414 /// load or store pseudo instruction.
415 static const NEONLdStTableEntry *LookupNEONLdSt(unsigned Opcode) {
416 #ifndef NDEBUG
417  // Make sure the table is sorted.
418  static std::atomic<bool> TableChecked(false);
419  if (!TableChecked.load(std::memory_order_relaxed)) {
420  assert(std::is_sorted(std::begin(NEONLdStTable), std::end(NEONLdStTable)) &&
421  "NEONLdStTable is not sorted!");
422  TableChecked.store(true, std::memory_order_relaxed);
423  }
424 #endif
425 
426  auto I = std::lower_bound(std::begin(NEONLdStTable),
427  std::end(NEONLdStTable), Opcode);
428  if (I != std::end(NEONLdStTable) && I->PseudoOpc == Opcode)
429  return I;
430  return nullptr;
431 }
432 
433 /// GetDSubRegs - Get 4 D subregisters of a Q, QQ, or QQQQ register,
434 /// corresponding to the specified register spacing. Not all of the results
435 /// are necessarily valid, e.g., a Q register only has 2 D subregisters.
436 static void GetDSubRegs(unsigned Reg, NEONRegSpacing RegSpc,
437  const TargetRegisterInfo *TRI, unsigned &D0,
438  unsigned &D1, unsigned &D2, unsigned &D3) {
439  if (RegSpc == SingleSpc || RegSpc == SingleLowSpc) {
440  D0 = TRI->getSubReg(Reg, ARM::dsub_0);
441  D1 = TRI->getSubReg(Reg, ARM::dsub_1);
442  D2 = TRI->getSubReg(Reg, ARM::dsub_2);
443  D3 = TRI->getSubReg(Reg, ARM::dsub_3);
444  } else if (RegSpc == SingleHighQSpc) {
445  D0 = TRI->getSubReg(Reg, ARM::dsub_4);
446  D1 = TRI->getSubReg(Reg, ARM::dsub_5);
447  D2 = TRI->getSubReg(Reg, ARM::dsub_6);
448  D3 = TRI->getSubReg(Reg, ARM::dsub_7);
449  } else if (RegSpc == SingleHighTSpc) {
450  D0 = TRI->getSubReg(Reg, ARM::dsub_3);
451  D1 = TRI->getSubReg(Reg, ARM::dsub_4);
452  D2 = TRI->getSubReg(Reg, ARM::dsub_5);
453  D3 = TRI->getSubReg(Reg, ARM::dsub_6);
454  } else if (RegSpc == EvenDblSpc) {
455  D0 = TRI->getSubReg(Reg, ARM::dsub_0);
456  D1 = TRI->getSubReg(Reg, ARM::dsub_2);
457  D2 = TRI->getSubReg(Reg, ARM::dsub_4);
458  D3 = TRI->getSubReg(Reg, ARM::dsub_6);
459  } else {
460  assert(RegSpc == OddDblSpc && "unknown register spacing");
461  D0 = TRI->getSubReg(Reg, ARM::dsub_1);
462  D1 = TRI->getSubReg(Reg, ARM::dsub_3);
463  D2 = TRI->getSubReg(Reg, ARM::dsub_5);
464  D3 = TRI->getSubReg(Reg, ARM::dsub_7);
465  }
466 }
467 
468 /// ExpandVLD - Translate VLD pseudo instructions with Q, QQ or QQQQ register
469 /// operands to real VLD instructions with D register operands.
470 void ARMExpandPseudo::ExpandVLD(MachineBasicBlock::iterator &MBBI) {
471  MachineInstr &MI = *MBBI;
472  MachineBasicBlock &MBB = *MI.getParent();
473 
474  const NEONLdStTableEntry *TableEntry = LookupNEONLdSt(MI.getOpcode());
475  assert(TableEntry && TableEntry->IsLoad && "NEONLdStTable lookup failed");
476  NEONRegSpacing RegSpc = (NEONRegSpacing)TableEntry->RegSpacing;
477  unsigned NumRegs = TableEntry->NumRegs;
478 
479  MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
480  TII->get(TableEntry->RealOpc));
481  unsigned OpIdx = 0;
482 
483  bool DstIsDead = MI.getOperand(OpIdx).isDead();
484  unsigned DstReg = MI.getOperand(OpIdx++).getReg();
485  if(TableEntry->RealOpc == ARM::VLD2DUPd8x2 ||
486  TableEntry->RealOpc == ARM::VLD2DUPd16x2 ||
487  TableEntry->RealOpc == ARM::VLD2DUPd32x2) {
488  unsigned SubRegIndex;
489  if (RegSpc == EvenDblSpc) {
490  SubRegIndex = ARM::dsub_0;
491  } else {
492  assert(RegSpc == OddDblSpc && "Unexpected spacing!");
493  SubRegIndex = ARM::dsub_1;
494  }
495  unsigned SubReg = TRI->getSubReg(DstReg, SubRegIndex);
496  unsigned DstRegPair = TRI->getMatchingSuperReg(SubReg, ARM::dsub_0,
497  &ARM::DPairSpcRegClass);
498  MIB.addReg(DstRegPair, RegState::Define | getDeadRegState(DstIsDead));
499  } else {
500  unsigned D0, D1, D2, D3;
501  GetDSubRegs(DstReg, RegSpc, TRI, D0, D1, D2, D3);
502  MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead));
503  if (NumRegs > 1 && TableEntry->copyAllListRegs)
504  MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead));
505  if (NumRegs > 2 && TableEntry->copyAllListRegs)
506  MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead));
507  if (NumRegs > 3 && TableEntry->copyAllListRegs)
508  MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead));
509  }
510 
511  if (TableEntry->isUpdating)
512  MIB.add(MI.getOperand(OpIdx++));
513 
514  // Copy the addrmode6 operands.
515  MIB.add(MI.getOperand(OpIdx++));
516  MIB.add(MI.getOperand(OpIdx++));
517 
518  // Copy the am6offset operand.
519  if (TableEntry->hasWritebackOperand) {
520  // TODO: The writing-back pseudo instructions we translate here are all
521  // defined to take am6offset nodes that are capable to represent both fixed
522  // and register forms. Some real instructions, however, do not rely on
523  // am6offset and have separate definitions for such forms. When this is the
524  // case, fixed forms do not take any offset nodes, so here we skip them for
525  // such instructions. Once all real and pseudo writing-back instructions are
526  // rewritten without use of am6offset nodes, this code will go away.
527  const MachineOperand &AM6Offset = MI.getOperand(OpIdx++);
528  if (TableEntry->RealOpc == ARM::VLD1d8Qwb_fixed ||
529  TableEntry->RealOpc == ARM::VLD1d16Qwb_fixed ||
530  TableEntry->RealOpc == ARM::VLD1d32Qwb_fixed ||
531  TableEntry->RealOpc == ARM::VLD1d64Qwb_fixed ||
532  TableEntry->RealOpc == ARM::VLD1d8Twb_fixed ||
533  TableEntry->RealOpc == ARM::VLD1d16Twb_fixed ||
534  TableEntry->RealOpc == ARM::VLD1d32Twb_fixed ||
535  TableEntry->RealOpc == ARM::VLD1d64Twb_fixed) {
536  assert(AM6Offset.getReg() == 0 &&
537  "A fixed writing-back pseudo instruction provides an offset "
538  "register!");
539  } else {
540  MIB.add(AM6Offset);
541  }
542  }
543 
544  // For an instruction writing double-spaced subregs, the pseudo instruction
545  // has an extra operand that is a use of the super-register. Record the
546  // operand index and skip over it.
547  unsigned SrcOpIdx = 0;
548  if(TableEntry->RealOpc != ARM::VLD2DUPd8x2 &&
549  TableEntry->RealOpc != ARM::VLD2DUPd16x2 &&
550  TableEntry->RealOpc != ARM::VLD2DUPd32x2) {
551  if (RegSpc == EvenDblSpc || RegSpc == OddDblSpc ||
552  RegSpc == SingleLowSpc || RegSpc == SingleHighQSpc ||
553  RegSpc == SingleHighTSpc)
554  SrcOpIdx = OpIdx++;
555  }
556 
557  // Copy the predicate operands.
558  MIB.add(MI.getOperand(OpIdx++));
559  MIB.add(MI.getOperand(OpIdx++));
560 
561  // Copy the super-register source operand used for double-spaced subregs over
562  // to the new instruction as an implicit operand.
563  if (SrcOpIdx != 0) {
564  MachineOperand MO = MI.getOperand(SrcOpIdx);
565  MO.setImplicit(true);
566  MIB.add(MO);
567  }
568  // Add an implicit def for the super-register.
569  MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));
570  TransferImpOps(MI, MIB, MIB);
571 
572  // Transfer memoperands.
573  MIB.cloneMemRefs(MI);
574 
575  MI.eraseFromParent();
576 }
577 
578 /// ExpandVST - Translate VST pseudo instructions with Q, QQ or QQQQ register
579 /// operands to real VST instructions with D register operands.
580 void ARMExpandPseudo::ExpandVST(MachineBasicBlock::iterator &MBBI) {
581  MachineInstr &MI = *MBBI;
582  MachineBasicBlock &MBB = *MI.getParent();
583 
584  const NEONLdStTableEntry *TableEntry = LookupNEONLdSt(MI.getOpcode());
585  assert(TableEntry && !TableEntry->IsLoad && "NEONLdStTable lookup failed");
586  NEONRegSpacing RegSpc = (NEONRegSpacing)TableEntry->RegSpacing;
587  unsigned NumRegs = TableEntry->NumRegs;
588 
589  MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
590  TII->get(TableEntry->RealOpc));
591  unsigned OpIdx = 0;
592  if (TableEntry->isUpdating)
593  MIB.add(MI.getOperand(OpIdx++));
594 
595  // Copy the addrmode6 operands.
596  MIB.add(MI.getOperand(OpIdx++));
597  MIB.add(MI.getOperand(OpIdx++));
598 
599  if (TableEntry->hasWritebackOperand) {
600  // TODO: The writing-back pseudo instructions we translate here are all
601  // defined to take am6offset nodes that are capable to represent both fixed
602  // and register forms. Some real instructions, however, do not rely on
603  // am6offset and have separate definitions for such forms. When this is the
604  // case, fixed forms do not take any offset nodes, so here we skip them for
605  // such instructions. Once all real and pseudo writing-back instructions are
606  // rewritten without use of am6offset nodes, this code will go away.
607  const MachineOperand &AM6Offset = MI.getOperand(OpIdx++);
608  if (TableEntry->RealOpc == ARM::VST1d8Qwb_fixed ||
609  TableEntry->RealOpc == ARM::VST1d16Qwb_fixed ||
610  TableEntry->RealOpc == ARM::VST1d32Qwb_fixed ||
611  TableEntry->RealOpc == ARM::VST1d64Qwb_fixed ||
612  TableEntry->RealOpc == ARM::VST1d8Twb_fixed ||
613  TableEntry->RealOpc == ARM::VST1d16Twb_fixed ||
614  TableEntry->RealOpc == ARM::VST1d32Twb_fixed ||
615  TableEntry->RealOpc == ARM::VST1d64Twb_fixed) {
616  assert(AM6Offset.getReg() == 0 &&
617  "A fixed writing-back pseudo instruction provides an offset "
618  "register!");
619  } else {
620  MIB.add(AM6Offset);
621  }
622  }
623 
624  bool SrcIsKill = MI.getOperand(OpIdx).isKill();
625  bool SrcIsUndef = MI.getOperand(OpIdx).isUndef();
626  unsigned SrcReg = MI.getOperand(OpIdx++).getReg();
627  unsigned D0, D1, D2, D3;
628  GetDSubRegs(SrcReg, RegSpc, TRI, D0, D1, D2, D3);
629  MIB.addReg(D0, getUndefRegState(SrcIsUndef));
630  if (NumRegs > 1 && TableEntry->copyAllListRegs)
631  MIB.addReg(D1, getUndefRegState(SrcIsUndef));
632  if (NumRegs > 2 && TableEntry->copyAllListRegs)
633  MIB.addReg(D2, getUndefRegState(SrcIsUndef));
634  if (NumRegs > 3 && TableEntry->copyAllListRegs)
635  MIB.addReg(D3, getUndefRegState(SrcIsUndef));
636 
637  // Copy the predicate operands.
638  MIB.add(MI.getOperand(OpIdx++));
639  MIB.add(MI.getOperand(OpIdx++));
640 
641  if (SrcIsKill && !SrcIsUndef) // Add an implicit kill for the super-reg.
642  MIB->addRegisterKilled(SrcReg, TRI, true);
643  else if (!SrcIsUndef)
644  MIB.addReg(SrcReg, RegState::Implicit); // Add implicit uses for src reg.
645  TransferImpOps(MI, MIB, MIB);
646 
647  // Transfer memoperands.
648  MIB.cloneMemRefs(MI);
649 
650  MI.eraseFromParent();
651 }
652 
653 /// ExpandLaneOp - Translate VLD*LN and VST*LN instructions with Q, QQ or QQQQ
654 /// register operands to real instructions with D register operands.
655 void ARMExpandPseudo::ExpandLaneOp(MachineBasicBlock::iterator &MBBI) {
656  MachineInstr &MI = *MBBI;
657  MachineBasicBlock &MBB = *MI.getParent();
658 
659  const NEONLdStTableEntry *TableEntry = LookupNEONLdSt(MI.getOpcode());
660  assert(TableEntry && "NEONLdStTable lookup failed");
661  NEONRegSpacing RegSpc = (NEONRegSpacing)TableEntry->RegSpacing;
662  unsigned NumRegs = TableEntry->NumRegs;
663  unsigned RegElts = TableEntry->RegElts;
664 
665  MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
666  TII->get(TableEntry->RealOpc));
667  unsigned OpIdx = 0;
668  // The lane operand is always the 3rd from last operand, before the 2
669  // predicate operands.
670  unsigned Lane = MI.getOperand(MI.getDesc().getNumOperands() - 3).getImm();
671 
672  // Adjust the lane and spacing as needed for Q registers.
673  assert(RegSpc != OddDblSpc && "unexpected register spacing for VLD/VST-lane");
674  if (RegSpc == EvenDblSpc && Lane >= RegElts) {
675  RegSpc = OddDblSpc;
676  Lane -= RegElts;
677  }
678  assert(Lane < RegElts && "out of range lane for VLD/VST-lane");
679 
680  unsigned D0 = 0, D1 = 0, D2 = 0, D3 = 0;
681  unsigned DstReg = 0;
682  bool DstIsDead = false;
683  if (TableEntry->IsLoad) {
684  DstIsDead = MI.getOperand(OpIdx).isDead();
685  DstReg = MI.getOperand(OpIdx++).getReg();
686  GetDSubRegs(DstReg, RegSpc, TRI, D0, D1, D2, D3);
687  MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead));
688  if (NumRegs > 1)
689  MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead));
690  if (NumRegs > 2)
691  MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead));
692  if (NumRegs > 3)
693  MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead));
694  }
695 
696  if (TableEntry->isUpdating)
697  MIB.add(MI.getOperand(OpIdx++));
698 
699  // Copy the addrmode6 operands.
700  MIB.add(MI.getOperand(OpIdx++));
701  MIB.add(MI.getOperand(OpIdx++));
702  // Copy the am6offset operand.
703  if (TableEntry->hasWritebackOperand)
704  MIB.add(MI.getOperand(OpIdx++));
705 
706  // Grab the super-register source.
707  MachineOperand MO = MI.getOperand(OpIdx++);
708  if (!TableEntry->IsLoad)
709  GetDSubRegs(MO.getReg(), RegSpc, TRI, D0, D1, D2, D3);
710 
711  // Add the subregs as sources of the new instruction.
712  unsigned SrcFlags = (getUndefRegState(MO.isUndef()) |
713  getKillRegState(MO.isKill()));
714  MIB.addReg(D0, SrcFlags);
715  if (NumRegs > 1)
716  MIB.addReg(D1, SrcFlags);
717  if (NumRegs > 2)
718  MIB.addReg(D2, SrcFlags);
719  if (NumRegs > 3)
720  MIB.addReg(D3, SrcFlags);
721 
722  // Add the lane number operand.
723  MIB.addImm(Lane);
724  OpIdx += 1;
725 
726  // Copy the predicate operands.
727  MIB.add(MI.getOperand(OpIdx++));
728  MIB.add(MI.getOperand(OpIdx++));
729 
730  // Copy the super-register source to be an implicit source.
731  MO.setImplicit(true);
732  MIB.add(MO);
733  if (TableEntry->IsLoad)
734  // Add an implicit def for the super-register.
735  MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));
736  TransferImpOps(MI, MIB, MIB);
737  // Transfer memoperands.
738  MIB.cloneMemRefs(MI);
739  MI.eraseFromParent();
740 }
741 
742 /// ExpandVTBL - Translate VTBL and VTBX pseudo instructions with Q or QQ
743 /// register operands to real instructions with D register operands.
744 void ARMExpandPseudo::ExpandVTBL(MachineBasicBlock::iterator &MBBI,
745  unsigned Opc, bool IsExt) {
746  MachineInstr &MI = *MBBI;
747  MachineBasicBlock &MBB = *MI.getParent();
748 
749  MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc));
750  unsigned OpIdx = 0;
751 
752  // Transfer the destination register operand.
753  MIB.add(MI.getOperand(OpIdx++));
754  if (IsExt) {
755  MachineOperand VdSrc(MI.getOperand(OpIdx++));
756  MIB.add(VdSrc);
757  }
758 
759  bool SrcIsKill = MI.getOperand(OpIdx).isKill();
760  unsigned SrcReg = MI.getOperand(OpIdx++).getReg();
761  unsigned D0, D1, D2, D3;
762  GetDSubRegs(SrcReg, SingleSpc, TRI, D0, D1, D2, D3);
763  MIB.addReg(D0);
764 
765  // Copy the other source register operand.
766  MachineOperand VmSrc(MI.getOperand(OpIdx++));
767  MIB.add(VmSrc);
768 
769  // Copy the predicate operands.
770  MIB.add(MI.getOperand(OpIdx++));
771  MIB.add(MI.getOperand(OpIdx++));
772 
773  // Add an implicit kill and use for the super-reg.
774  MIB.addReg(SrcReg, RegState::Implicit | getKillRegState(SrcIsKill));
775  TransferImpOps(MI, MIB, MIB);
776  MI.eraseFromParent();
777 }
778 
779 static bool IsAnAddressOperand(const MachineOperand &MO) {
780  // This check is overly conservative. Unless we are certain that the machine
781  // operand is not a symbol reference, we return that it is a symbol reference.
782  // This is important as the load pair may not be split up Windows.
783  switch (MO.getType()) {
784  case MachineOperand::MO_Register:
785  case MachineOperand::MO_Immediate:
786  case MachineOperand::MO_CImmediate:
787  case MachineOperand::MO_FPImmediate:
788  return false;
789  case MachineOperand::MO_MachineBasicBlock:
790  return true;
791  case MachineOperand::MO_FrameIndex:
792  return false;
793  case MachineOperand::MO_ConstantPoolIndex:
794  case MachineOperand::MO_TargetIndex:
795  case MachineOperand::MO_JumpTableIndex:
796  case MachineOperand::MO_ExternalSymbol:
797  case MachineOperand::MO_GlobalAddress:
798  case MachineOperand::MO_BlockAddress:
799  return true;
800  case MachineOperand::MO_RegisterMask:
801  case MachineOperand::MO_RegisterLiveOut:
802  return false;
803  case MachineOperand::MO_Metadata:
804  case MachineOperand::MO_MCSymbol:
805  return true;
806  case MachineOperand::MO_CFIIndex:
807  return false;
808  case MachineOperand::MO_IntrinsicID:
809  case MachineOperand::MO_Predicate:
810  llvm_unreachable("should not exist post-isel");
811  }
812  llvm_unreachable("unhandled machine operand type");
813 }
814 
815 static MachineOperand makeImplicit(const MachineOperand &MO) {
816  MachineOperand NewMO = MO;
817  NewMO.setImplicit();
818  return NewMO;
819 }
820 
821 void ARMExpandPseudo::ExpandMOV32BitImm(MachineBasicBlock &MBB,
822  MachineBasicBlock::iterator &MBBI) {
823  MachineInstr &MI = *MBBI;
824  unsigned Opcode = MI.getOpcode();
825  unsigned PredReg = 0;
826  ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg);
827  unsigned DstReg = MI.getOperand(0).getReg();
828  bool DstIsDead = MI.getOperand(0).isDead();
829  bool isCC = Opcode == ARM::MOVCCi32imm || Opcode == ARM::t2MOVCCi32imm;
830  const MachineOperand &MO = MI.getOperand(isCC ? 2 : 1);
831  bool RequiresBundling = STI->isTargetWindows() && IsAnAddressOperand(MO);
832  MachineInstrBuilder LO16, HI16;
833 
834  if (!STI->hasV6T2Ops() &&
835  (Opcode == ARM::MOVi32imm || Opcode == ARM::MOVCCi32imm)) {
836  // FIXME Windows CE supports older ARM CPUs
837  assert(!STI->isTargetWindows() && "Windows on ARM requires ARMv7+");
838 
839  // Expand into a movi + orr.
840  LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVi), DstReg);
841  HI16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::ORRri))
842  .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
843  .addReg(DstReg);
844 
845  assert (MO.isImm() && "MOVi32imm w/ non-immediate source operand!");
846  unsigned ImmVal = (unsigned)MO.getImm();
847  unsigned SOImmValV1 = ARM_AM::getSOImmTwoPartFirst(ImmVal);
848  unsigned SOImmValV2 = ARM_AM::getSOImmTwoPartSecond(ImmVal);
849  LO16 = LO16.addImm(SOImmValV1);
850  HI16 = HI16.addImm(SOImmValV2);
851  LO16.cloneMemRefs(MI);
852  HI16.cloneMemRefs(MI);
853  LO16.addImm(Pred).addReg(PredReg).add(condCodeOp());
854  HI16.addImm(Pred).addReg(PredReg).add(condCodeOp());
855  if (isCC)
856  LO16.add(makeImplicit(MI.getOperand(1)));
857  TransferImpOps(MI, LO16, HI16);
858  MI.eraseFromParent();
859  return;
860  }
861 
862  unsigned LO16Opc = 0;
863  unsigned HI16Opc = 0;
864  if (Opcode == ARM::t2MOVi32imm || Opcode == ARM::t2MOVCCi32imm) {
865  LO16Opc = ARM::t2MOVi16;
866  HI16Opc = ARM::t2MOVTi16;
867  } else {
868  LO16Opc = ARM::MOVi16;
869  HI16Opc = ARM::MOVTi16;
870  }
871 
872  LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(LO16Opc), DstReg);
873  HI16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(HI16Opc))
874  .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
875  .addReg(DstReg);
876 
877  switch (MO.getType()) {
878  case MachineOperand::MO_Immediate: {
879  unsigned Imm = MO.getImm();
880  unsigned Lo16 = Imm & 0xffff;
881  unsigned Hi16 = (Imm >> 16) & 0xffff;
882  LO16 = LO16.addImm(Lo16);
883  HI16 = HI16.addImm(Hi16);
884  break;
885  }
886  case MachineOperand::MO_ExternalSymbol: {
887  const char *ES = MO.getSymbolName();
888  unsigned TF = MO.getTargetFlags();
889  LO16 = LO16.addExternalSymbol(ES, TF | ARMII::MO_LO16);
890  HI16 = HI16.addExternalSymbol(ES, TF | ARMII::MO_HI16);
891  break;
892  }
893  default: {
894  const GlobalValue *GV = MO.getGlobal();
895  unsigned TF = MO.getTargetFlags();
896  LO16 = LO16.addGlobalAddress(GV, MO.getOffset(), TF | ARMII::MO_LO16);
897  HI16 = HI16.addGlobalAddress(GV, MO.getOffset(), TF | ARMII::MO_HI16);
898  break;
899  }
900  }
901 
902  LO16.cloneMemRefs(MI);
903  HI16.cloneMemRefs(MI);
904  LO16.addImm(Pred).addReg(PredReg);
905  HI16.addImm(Pred).addReg(PredReg);
906 
907  if (RequiresBundling)
908  finalizeBundle(MBB, LO16->getIterator(), MBBI->getIterator());
909 
910  if (isCC)
911  LO16.add(makeImplicit(MI.getOperand(1)));
912  TransferImpOps(MI, LO16, HI16);
913  MI.eraseFromParent();
914 }
915 
916 /// Expand a CMP_SWAP pseudo-inst to an ldrex/strex loop as simply as
917 /// possible. This only gets used at -O0 so we don't care about efficiency of
918 /// the generated code.
919 bool ARMExpandPseudo::ExpandCMP_SWAP(MachineBasicBlock &MBB,
920  MachineBasicBlock::iterator MBBI,
921  unsigned LdrexOp, unsigned StrexOp,
922  unsigned UxtOp,
923  MachineBasicBlock::iterator &NextMBBI) {
924  bool IsThumb = STI->isThumb();
925  MachineInstr &MI = *MBBI;
926  DebugLoc DL = MI.getDebugLoc();
927  const MachineOperand &Dest = MI.getOperand(0);
928  unsigned TempReg = MI.getOperand(1).getReg();
929  // Duplicating undef operands into 2 instructions does not guarantee the same
930  // value on both; However undef should be replaced by xzr anyway.
931  assert(!MI.getOperand(2).isUndef() && "cannot handle undef");
932  unsigned AddrReg = MI.getOperand(2).getReg();
933  unsigned DesiredReg = MI.getOperand(3).getReg();
934  unsigned NewReg = MI.getOperand(4).getReg();
935 
936  MachineFunction *MF = MBB.getParent();
937  auto LoadCmpBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
938  auto StoreBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
939  auto DoneBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
940 
941  MF->insert(++MBB.getIterator(), LoadCmpBB);
942  MF->insert(++LoadCmpBB->getIterator(), StoreBB);
943  MF->insert(++StoreBB->getIterator(), DoneBB);
944 
945  if (UxtOp) {
946  MachineInstrBuilder MIB =
947  BuildMI(MBB, MBBI, DL, TII->get(UxtOp), DesiredReg)
948  .addReg(DesiredReg, RegState::Kill);
949  if (!IsThumb)
950  MIB.addImm(0);
951  MIB.add(predOps(ARMCC::AL));
952  }
953 
954  // .Lloadcmp:
955  // ldrex rDest, [rAddr]
956  // cmp rDest, rDesired
957  // bne .Ldone
958 
959  MachineInstrBuilder MIB;
960  MIB = BuildMI(LoadCmpBB, DL, TII->get(LdrexOp), Dest.getReg());
961  MIB.addReg(AddrReg);
962  if (LdrexOp == ARM::t2LDREX)
963  MIB.addImm(0); // a 32-bit Thumb ldrex (only) allows an offset.
964  MIB.add(predOps(ARMCC::AL));
965 
966  unsigned CMPrr = IsThumb ? ARM::tCMPhir : ARM::CMPrr;
967  BuildMI(LoadCmpBB, DL, TII->get(CMPrr))
968  .addReg(Dest.getReg(), getKillRegState(Dest.isDead()))
969  .addReg(DesiredReg)
970  .add(predOps(ARMCC::AL));
971  unsigned Bcc = IsThumb ? ARM::tBcc : ARM::Bcc;
972  BuildMI(LoadCmpBB, DL, TII->get(Bcc))
973  .addMBB(DoneBB)
974  .addImm(ARMCC::NE)
975  .addReg(ARM::CPSR, RegState::Kill);
976  LoadCmpBB->addSuccessor(DoneBB);
977  LoadCmpBB->addSuccessor(StoreBB);
978 
979  // .Lstore:
980  // strex rTempReg, rNew, [rAddr]
981  // cmp rTempReg, #0
982  // bne .Lloadcmp
983  MIB = BuildMI(StoreBB, DL, TII->get(StrexOp), TempReg)
984  .addReg(NewReg)
985  .addReg(AddrReg);
986  if (StrexOp == ARM::t2STREX)
987  MIB.addImm(0); // a 32-bit Thumb strex (only) allows an offset.
988  MIB.add(predOps(ARMCC::AL));
989 
990  unsigned CMPri = IsThumb ? ARM::t2CMPri : ARM::CMPri;
991  BuildMI(StoreBB, DL, TII->get(CMPri))
992  .addReg(TempReg, RegState::Kill)
993  .addImm(0)
994  .add(predOps(ARMCC::AL));
995  BuildMI(StoreBB, DL, TII->get(Bcc))
996  .addMBB(LoadCmpBB)
997  .addImm(ARMCC::NE)
998  .addReg(ARM::CPSR, RegState::Kill);
999  StoreBB->addSuccessor(LoadCmpBB);
1000  StoreBB->addSuccessor(DoneBB);
1001 
1002  DoneBB->splice(DoneBB->end(), &MBB, MI, MBB.end());
1003  DoneBB->transferSuccessors(&MBB);
1004 
1005  MBB.addSuccessor(LoadCmpBB);
1006 
1007  NextMBBI = MBB.end();
1008  MI.eraseFromParent();
1009 
1010  // Recompute livein lists.
1011  LivePhysRegs LiveRegs;
1012  computeAndAddLiveIns(LiveRegs, *DoneBB);
1013  computeAndAddLiveIns(LiveRegs, *StoreBB);
1014  computeAndAddLiveIns(LiveRegs, *LoadCmpBB);
1015  // Do an extra pass around the loop to get loop carried registers right.
1016  StoreBB->clearLiveIns();
1017  computeAndAddLiveIns(LiveRegs, *StoreBB);
1018  LoadCmpBB->clearLiveIns();
1019  computeAndAddLiveIns(LiveRegs, *LoadCmpBB);
1020 
1021  return true;
1022 }
1023 
1024 /// ARM's ldrexd/strexd take a consecutive register pair (represented as a
1025 /// single GPRPair register), Thumb's take two separate registers so we need to
1026 /// extract the subregs from the pair.
1027 static void addExclusiveRegPair(MachineInstrBuilder &MIB, MachineOperand &Reg,
1028  unsigned Flags, bool IsThumb,
1029  const TargetRegisterInfo *TRI) {
1030  if (IsThumb) {
1031  unsigned RegLo = TRI->getSubReg(Reg.getReg(), ARM::gsub_0);
1032  unsigned RegHi = TRI->getSubReg(Reg.getReg(), ARM::gsub_1);
1033  MIB.addReg(RegLo, Flags);
1034  MIB.addReg(RegHi, Flags);
1035  } else
1036  MIB.addReg(Reg.getReg(), Flags);
1037 }
1038 
1039 /// Expand a 64-bit CMP_SWAP to an ldrexd/strexd loop.
1040 bool ARMExpandPseudo::ExpandCMP_SWAP_64(MachineBasicBlock &MBB,
1041  MachineBasicBlock::iterator MBBI,
1042  MachineBasicBlock::iterator &NextMBBI) {
1043  bool IsThumb = STI->isThumb();
1044  MachineInstr &MI = *MBBI;
1045  DebugLoc DL = MI.getDebugLoc();
1046  MachineOperand &Dest = MI.getOperand(0);
1047  unsigned TempReg = MI.getOperand(1).getReg();
1048  // Duplicating undef operands into 2 instructions does not guarantee the same
1049  // value on both; However undef should be replaced by xzr anyway.
1050  assert(!MI.getOperand(2).isUndef() && "cannot handle undef");
1051  unsigned AddrReg = MI.getOperand(2).getReg();
1052  unsigned DesiredReg = MI.getOperand(3).getReg();
1053  MachineOperand New = MI.getOperand(4);
1054  New.setIsKill(false);
1055 
1056  unsigned DestLo = TRI->getSubReg(Dest.getReg(), ARM::gsub_0);
1057  unsigned DestHi = TRI->getSubReg(Dest.getReg(), ARM::gsub_1);
1058  unsigned DesiredLo = TRI->getSubReg(DesiredReg, ARM::gsub_0);
1059  unsigned DesiredHi = TRI->getSubReg(DesiredReg, ARM::gsub_1);
1060 
1061  MachineFunction *MF = MBB.getParent();
1062  auto LoadCmpBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
1063  auto StoreBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
1064  auto DoneBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
1065 
1066  MF->insert(++MBB.getIterator(), LoadCmpBB);
1067  MF->insert(++LoadCmpBB->getIterator(), StoreBB);
1068  MF->insert(++StoreBB->getIterator(), DoneBB);
1069 
1070  // .Lloadcmp:
1071  // ldrexd rDestLo, rDestHi, [rAddr]
1072  // cmp rDestLo, rDesiredLo
1073  // sbcs dead rTempReg, rDestHi, rDesiredHi
1074  // bne .Ldone
1075  unsigned LDREXD = IsThumb ? ARM::t2LDREXD : ARM::LDREXD;
1076  MachineInstrBuilder MIB;
1077  MIB = BuildMI(LoadCmpBB, DL, TII->get(LDREXD));
1078  addExclusiveRegPair(MIB, Dest, RegState::Define, IsThumb, TRI);
1079  MIB.addReg(AddrReg).add(predOps(ARMCC::AL));
1080 
1081  unsigned CMPrr = IsThumb ? ARM::tCMPhir : ARM::CMPrr;
1082  BuildMI(LoadCmpBB, DL, TII->get(CMPrr))
1083  .addReg(DestLo, getKillRegState(Dest.isDead()))
1084  .addReg(DesiredLo)
1085  .add(predOps(ARMCC::AL));
1086 
1087  BuildMI(LoadCmpBB, DL, TII->get(CMPrr))
1088  .addReg(DestHi, getKillRegState(Dest.isDead()))
1089  .addReg(DesiredHi)
1090  .addImm(ARMCC::EQ).addReg(ARM::CPSR, RegState::Kill);
1091 
1092  unsigned Bcc = IsThumb ? ARM::tBcc : ARM::Bcc;
1093  BuildMI(LoadCmpBB, DL, TII->get(Bcc))
1094  .addMBB(DoneBB)
1095  .addImm(ARMCC::NE)
1096  .addReg(ARM::CPSR, RegState::Kill);
1097  LoadCmpBB->addSuccessor(DoneBB);
1098  LoadCmpBB->addSuccessor(StoreBB);
1099 
1100  // .Lstore:
1101  // strexd rTempReg, rNewLo, rNewHi, [rAddr]
1102  // cmp rTempReg, #0
1103  // bne .Lloadcmp
1104  unsigned STREXD = IsThumb ? ARM::t2STREXD : ARM::STREXD;
1105  MIB = BuildMI(StoreBB, DL, TII->get(STREXD), TempReg);
1106  unsigned Flags = getKillRegState(New.isDead());
1107  addExclusiveRegPair(MIB, New, Flags, IsThumb, TRI);
1108  MIB.addReg(AddrReg).add(predOps(ARMCC::AL));
1109 
1110  unsigned CMPri = IsThumb ? ARM::t2CMPri : ARM::CMPri;
1111  BuildMI(StoreBB, DL, TII->get(CMPri))
1112  .addReg(TempReg, RegState::Kill)
1113  .addImm(0)
1114  .add(predOps(ARMCC::AL));
1115  BuildMI(StoreBB, DL, TII->get(Bcc))
1116  .addMBB(LoadCmpBB)
1117  .addImm(ARMCC::NE)
1118  .addReg(ARM::CPSR, RegState::Kill);
1119  StoreBB->addSuccessor(LoadCmpBB);
1120  StoreBB->addSuccessor(DoneBB);
1121 
1122  DoneBB->splice(DoneBB->end(), &MBB, MI, MBB.end());
1123  DoneBB->transferSuccessors(&MBB);
1124 
1125  MBB.addSuccessor(LoadCmpBB);
1126 
1127  NextMBBI = MBB.end();
1128  MI.eraseFromParent();
1129 
1130  // Recompute livein lists.
1131  LivePhysRegs LiveRegs;
1132  computeAndAddLiveIns(LiveRegs, *DoneBB);
1133  computeAndAddLiveIns(LiveRegs, *StoreBB);
1134  computeAndAddLiveIns(LiveRegs, *LoadCmpBB);
1135  // Do an extra pass around the loop to get loop carried registers right.
1136  StoreBB->clearLiveIns();
1137  computeAndAddLiveIns(LiveRegs, *StoreBB);
1138  LoadCmpBB->clearLiveIns();
1139  computeAndAddLiveIns(LiveRegs, *LoadCmpBB);
1140 
1141  return true;
1142 }
1143 
1144 
1145 bool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB,
1146  MachineBasicBlock::iterator MBBI,
1147  MachineBasicBlock::iterator &NextMBBI) {
1148  MachineInstr &MI = *MBBI;
1149  unsigned Opcode = MI.getOpcode();
1150  switch (Opcode) {
1151  default:
1152  return false;
1153 
1154  case ARM::TCRETURNdi:
1155  case ARM::TCRETURNri: {
1156  MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
1157  assert(MBBI->isReturn() &&
1158  "Can only insert epilog into returning blocks");
1159  unsigned RetOpcode = MBBI->getOpcode();
1160  DebugLoc dl = MBBI->getDebugLoc();
1161  const ARMBaseInstrInfo &TII = *static_cast<const ARMBaseInstrInfo *>(
1162  MBB.getParent()->getSubtarget().getInstrInfo());
1163 
1164  // Tail call return: adjust the stack pointer and jump to callee.
1165  MBBI = MBB.getLastNonDebugInstr();
1166  MachineOperand &JumpTarget = MBBI->getOperand(0);
1167 
1168  // Jump to label or value in register.
1169  if (RetOpcode == ARM::TCRETURNdi) {
1170  unsigned TCOpcode =
1171  STI->isThumb()
1172  ? (STI->isTargetMachO() ? ARM::tTAILJMPd : ARM::tTAILJMPdND)
1173  : ARM::TAILJMPd;
1174  MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(TCOpcode));
1175  if (JumpTarget.isGlobal())
1176  MIB.addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(),
1177  JumpTarget.getTargetFlags());
1178  else {
1179  assert(JumpTarget.isSymbol());
1180  MIB.addExternalSymbol(JumpTarget.getSymbolName(),
1181  JumpTarget.getTargetFlags());
1182  }
1183 
1184  // Add the default predicate in Thumb mode.
1185  if (STI->isThumb())
1186  MIB.add(predOps(ARMCC::AL));
1187  } else if (RetOpcode == ARM::TCRETURNri) {
1188  unsigned Opcode =
1189  STI->isThumb() ? ARM::tTAILJMPr
1190  : (STI->hasV4TOps() ? ARM::TAILJMPr : ARM::TAILJMPr4);
1191  BuildMI(MBB, MBBI, dl,
1192  TII.get(Opcode))
1193  .addReg(JumpTarget.getReg(), RegState::Kill);
1194  }
1195 
1196  auto NewMI = std::prev(MBBI);
1197  for (unsigned i = 1, e = MBBI->getNumOperands(); i != e; ++i)
1198  NewMI->addOperand(MBBI->getOperand(i));
1199 
1200  // Delete the pseudo instruction TCRETURN.
1201  MBB.erase(MBBI);
1202  MBBI = NewMI;
1203  return true;
1204  }
1205  case ARM::VMOVScc:
1206  case ARM::VMOVDcc: {
1207  unsigned newOpc = Opcode == ARM::VMOVScc ? ARM::VMOVS : ARM::VMOVD;
1208  BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(newOpc),
1209  MI.getOperand(1).getReg())
1210  .add(MI.getOperand(2))
1211  .addImm(MI.getOperand(3).getImm()) // 'pred'
1212  .add(MI.getOperand(4))
1213  .add(makeImplicit(MI.getOperand(1)));
1214 
1215  MI.eraseFromParent();
1216  return true;
1217  }
1218  case ARM::t2MOVCCr:
1219  case ARM::MOVCCr: {
1220  unsigned Opc = AFI->isThumbFunction() ? ARM::t2MOVr : ARM::MOVr;
1221  BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc),
1222  MI.getOperand(1).getReg())
1223  .add(MI.getOperand(2))
1224  .addImm(MI.getOperand(3).getImm()) // 'pred'
1225  .add(MI.getOperand(4))
1226  .add(condCodeOp()) // 's' bit
1227  .add(makeImplicit(MI.getOperand(1)));
1228 
1229  MI.eraseFromParent();
1230  return true;
1231  }
1232  case ARM::MOVCCsi: {
1233  BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsi),
1234  (MI.getOperand(1).getReg()))
1235  .add(MI.getOperand(2))
1236  .addImm(MI.getOperand(3).getImm())
1237  .addImm(MI.getOperand(4).getImm()) // 'pred'
1238  .add(MI.getOperand(5))
1239  .add(condCodeOp()) // 's' bit
1240  .add(makeImplicit(MI.getOperand(1)));
1241 
1242  MI.eraseFromParent();
1243  return true;
1244  }
1245  case ARM::MOVCCsr: {
1246  BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsr),
1247  (MI.getOperand(1).getReg()))
1248  .add(MI.getOperand(2))
1249  .add(MI.getOperand(3))
1250  .addImm(MI.getOperand(4).getImm())
1251  .addImm(MI.getOperand(5).getImm()) // 'pred'
1252  .add(MI.getOperand(6))
1253  .add(condCodeOp()) // 's' bit
1254  .add(makeImplicit(MI.getOperand(1)));
1255 
1256  MI.eraseFromParent();
1257  return true;
1258  }
1259  case ARM::t2MOVCCi16:
1260  case ARM::MOVCCi16: {
1261  unsigned NewOpc = AFI->isThumbFunction() ? ARM::t2MOVi16 : ARM::MOVi16;
1262  BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc),
1263  MI.getOperand(1).getReg())
1264  .addImm(MI.getOperand(2).getImm())
1265  .addImm(MI.getOperand(3).getImm()) // 'pred'
1266  .add(MI.getOperand(4))
1267  .add(makeImplicit(MI.getOperand(1)));
1268  MI.eraseFromParent();
1269  return true;
1270  }
1271  case ARM::t2MOVCCi:
1272  case ARM::MOVCCi: {
1273  unsigned Opc = AFI->isThumbFunction() ? ARM::t2MOVi : ARM::MOVi;
1274  BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc),
1275  MI.getOperand(1).getReg())
1276  .addImm(MI.getOperand(2).getImm())
1277  .addImm(MI.getOperand(3).getImm()) // 'pred'
1278  .add(MI.getOperand(4))
1279  .add(condCodeOp()) // 's' bit
1280  .add(makeImplicit(MI.getOperand(1)));
1281 
1282  MI.eraseFromParent();
1283  return true;
1284  }
1285  case ARM::t2MVNCCi:
1286  case ARM::MVNCCi: {
1287  unsigned Opc = AFI->isThumbFunction() ? ARM::t2MVNi : ARM::MVNi;
1288  BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc),
1289  MI.getOperand(1).getReg())
1290  .addImm(MI.getOperand(2).getImm())
1291  .addImm(MI.getOperand(3).getImm()) // 'pred'
1292  .add(MI.getOperand(4))
1293  .add(condCodeOp()) // 's' bit
1294  .add(makeImplicit(MI.getOperand(1)));
1295 
1296  MI.eraseFromParent();
1297  return true;
1298  }
1299  case ARM::t2MOVCClsl:
1300  case ARM::t2MOVCClsr:
1301  case ARM::t2MOVCCasr:
1302  case ARM::t2MOVCCror: {
1303  unsigned NewOpc;
1304  switch (Opcode) {
1305  case ARM::t2MOVCClsl: NewOpc = ARM::t2LSLri; break;
1306  case ARM::t2MOVCClsr: NewOpc = ARM::t2LSRri; break;
1307  case ARM::t2MOVCCasr: NewOpc = ARM::t2ASRri; break;
1308  case ARM::t2MOVCCror: NewOpc = ARM::t2RORri; break;
1309  default: llvm_unreachable("unexpeced conditional move");
1310  }
1311  BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc),
1312  MI.getOperand(1).getReg())
1313  .add(MI.getOperand(2))
1314  .addImm(MI.getOperand(3).getImm())
1315  .addImm(MI.getOperand(4).getImm()) // 'pred'
1316  .add(MI.getOperand(5))
1317  .add(condCodeOp()) // 's' bit
1318  .add(makeImplicit(MI.getOperand(1)));
1319  MI.eraseFromParent();
1320  return true;
1321  }
1322  case ARM::Int_eh_sjlj_dispatchsetup: {
1323  MachineFunction &MF = *MI.getParent()->getParent();
1324  const ARMBaseInstrInfo *AII =
1325  static_cast<const ARMBaseInstrInfo*>(TII);
1326  const ARMBaseRegisterInfo &RI = AII->getRegisterInfo();
1327  // For functions using a base pointer, we rematerialize it (via the frame
1328  // pointer) here since eh.sjlj.setjmp and eh.sjlj.longjmp don't do it
1329  // for us. Otherwise, expand to nothing.
1330  if (RI.hasBasePointer(MF)) {
1331  int32_t NumBytes = AFI->getFramePtrSpillOffset();
1332  unsigned FramePtr = RI.getFrameRegister(MF);
1333  assert(MF.getSubtarget().getFrameLowering()->hasFP(MF) &&
1334  "base pointer without frame pointer?");
1335 
1336  if (AFI->isThumb2Function()) {
1337  emitT2RegPlusImmediate(MBB, MBBI, MI.getDebugLoc(), ARM::R6,
1338  FramePtr, -NumBytes, ARMCC::AL, 0, *TII);
1339  } else if (AFI->isThumbFunction()) {
1340  emitThumbRegPlusImmediate(MBB, MBBI, MI.getDebugLoc(), ARM::R6,
1341  FramePtr, -NumBytes, *TII, RI);
1342  } else {
1343  emitARMRegPlusImmediate(MBB, MBBI, MI.getDebugLoc(), ARM::R6,
1344  FramePtr, -NumBytes, ARMCC::AL, 0,
1345  *TII);
1346  }
1347  // If there's dynamic realignment, adjust for it.
1348  if (RI.needsStackRealignment(MF)) {
1349  MachineFrameInfo &MFI = MF.getFrameInfo();
1350  unsigned MaxAlign = MFI.getMaxAlignment();
1351  assert (!AFI->isThumb1OnlyFunction());
1352  // Emit bic r6, r6, MaxAlign
1353  assert(MaxAlign <= 256 && "The BIC instruction cannot encode "
1354  "immediates larger than 256 with all lower "
1355  "bits set.");
1356  unsigned bicOpc = AFI->isThumbFunction() ?
1357  ARM::t2BICri : ARM::BICri;
1358  BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(bicOpc), ARM::R6)
1359  .addReg(ARM::R6, RegState::Kill)
1360  .addImm(MaxAlign - 1)
1361  .add(predOps(ARMCC::AL))
1362  .add(condCodeOp());
1363  }
1364 
1365  }
1366  MI.eraseFromParent();
1367  return true;
1368  }
1369 
1370  case ARM::MOVsrl_flag:
1371  case ARM::MOVsra_flag: {
1372  // These are just fancy MOVs instructions.
1373  BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsi),
1374  MI.getOperand(0).getReg())
1375  .add(MI.getOperand(1))
1376  .addImm(ARM_AM::getSORegOpc(
1377  (Opcode == ARM::MOVsrl_flag ? ARM_AM::lsr : ARM_AM::asr), 1))
1378  .add(predOps(ARMCC::AL))
1379  .addReg(ARM::CPSR, RegState::Define);
1380  MI.eraseFromParent();
1381  return true;
1382  }
1383  case ARM::RRX: {
1384  // This encodes as "MOVs Rd, Rm, rrx
1385  MachineInstrBuilder MIB =
1386  BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsi),
1387  MI.getOperand(0).getReg())
1388  .add(MI.getOperand(1))
1389  .addImm(ARM_AM::getSORegOpc(ARM_AM::rrx, 0))
1390  .add(predOps(ARMCC::AL))
1391  .add(condCodeOp());
1392  TransferImpOps(MI, MIB, MIB);
1393  MI.eraseFromParent();
1394  return true;
1395  }
1396  case ARM::tTPsoft:
1397  case ARM::TPsoft: {
1398  const bool Thumb = Opcode == ARM::tTPsoft;
1399 
1400  MachineInstrBuilder MIB;
1401  if (STI->genLongCalls()) {
1402  MachineFunction *MF = MBB.getParent();
1403  MachineConstantPool *MCP = MF->getConstantPool();
1404  unsigned PCLabelID = AFI->createPICLabelUId();
1405  MachineConstantPoolValue *CPV =
1406  ARMConstantPoolSymbol::Create(MF->getFunction().getContext(),
1407  "__aeabi_read_tp", PCLabelID, 0);
1408  unsigned Reg = MI.getOperand(0).getReg();
1409  MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
1410  TII->get(Thumb ? ARM::tLDRpci : ARM::LDRi12), Reg)
1411  .addConstantPoolIndex(MCP->getConstantPoolIndex(CPV, 4));
1412  if (!Thumb)
1413  MIB.addImm(0);
1414  MIB.add(predOps(ARMCC::AL));
1415 
1416  MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
1417  TII->get(Thumb ? ARM::tBLXr : ARM::BLX));
1418  if (Thumb)
1419  MIB.add(predOps(ARMCC::AL));
1420  MIB.addReg(Reg, RegState::Kill);
1421  } else {
1422  MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
1423  TII->get(Thumb ? ARM::tBL : ARM::BL));
1424  if (Thumb)
1425  MIB.add(predOps(ARMCC::AL));
1426  MIB.addExternalSymbol("__aeabi_read_tp", 0);
1427  }
1428 
1429  MIB.cloneMemRefs(MI);
1430  TransferImpOps(MI, MIB, MIB);
1431  MI.eraseFromParent();
1432  return true;
1433  }
1434  case ARM::tLDRpci_pic:
1435  case ARM::t2LDRpci_pic: {
1436  unsigned NewLdOpc = (Opcode == ARM::tLDRpci_pic)
1437  ? ARM::tLDRpci : ARM::t2LDRpci;
1438  unsigned DstReg = MI.getOperand(0).getReg();
1439  bool DstIsDead = MI.getOperand(0).isDead();
1440  MachineInstrBuilder MIB1 =
1441  BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewLdOpc), DstReg)
1442  .add(MI.getOperand(1))
1443  .add(predOps(ARMCC::AL));
1444  MIB1.cloneMemRefs(MI);
1445  MachineInstrBuilder MIB2 =
1446  BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::tPICADD))
1447  .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
1448  .addReg(DstReg)
1449  .add(MI.getOperand(2));
1450  TransferImpOps(MI, MIB1, MIB2);
1451  MI.eraseFromParent();
1452  return true;
1453  }
1454 
1455  case ARM::LDRLIT_ga_abs:
1456  case ARM::LDRLIT_ga_pcrel:
1457  case ARM::LDRLIT_ga_pcrel_ldr:
1458  case ARM::tLDRLIT_ga_abs:
1459  case ARM::tLDRLIT_ga_pcrel: {
1460  unsigned DstReg = MI.getOperand(0).getReg();
1461  bool DstIsDead = MI.getOperand(0).isDead();
1462  const MachineOperand &MO1 = MI.getOperand(1);
1463  auto Flags = MO1.getTargetFlags();
1464  const GlobalValue *GV = MO1.getGlobal();
1465  bool IsARM =
1466  Opcode != ARM::tLDRLIT_ga_pcrel && Opcode != ARM::tLDRLIT_ga_abs;
1467  bool IsPIC =
1468  Opcode != ARM::LDRLIT_ga_abs && Opcode != ARM::tLDRLIT_ga_abs;
1469  unsigned LDRLITOpc = IsARM ? ARM::LDRi12 : ARM::tLDRpci;
1470  unsigned PICAddOpc =
1471  IsARM
1472  ? (Opcode == ARM::LDRLIT_ga_pcrel_ldr ? ARM::PICLDR : ARM::PICADD)
1473  : ARM::tPICADD;
1474 
1475  // We need a new const-pool entry to load from.
1476  MachineConstantPool *MCP = MBB.getParent()->getConstantPool();
1477  unsigned ARMPCLabelIndex = 0;
1478  MachineConstantPoolValue *CPV;
1479 
1480  if (IsPIC) {
1481  unsigned PCAdj = IsARM ? 8 : 4;
1482  auto Modifier = (Flags & ARMII::MO_GOT)
1483  ? ARMCP::GOT_PREL
1484  : ARMCP::no_modifier;
1485  ARMPCLabelIndex = AFI->createPICLabelUId();
1486  CPV = ARMConstantPoolConstant::Create(
1487  GV, ARMPCLabelIndex, ARMCP::CPValue, PCAdj, Modifier,
1488  /*AddCurrentAddr*/ Modifier == ARMCP::GOT_PREL);
1489  } else
1490  CPV = ARMConstantPoolConstant::Create(GV, ARMCP::no_modifier);
1491 
1492  MachineInstrBuilder MIB =
1493  BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(LDRLITOpc), DstReg)
1494  .addConstantPoolIndex(MCP->getConstantPoolIndex(CPV, 4));
1495  if (IsARM)
1496  MIB.addImm(0);
1497  MIB.add(predOps(ARMCC::AL));
1498 
1499  if (IsPIC) {
1500  MachineInstrBuilder MIB =
1501  BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(PICAddOpc))
1502  .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
1503  .addReg(DstReg)
1504  .addImm(ARMPCLabelIndex);
1505 
1506  if (IsARM)
1507  MIB.add(predOps(ARMCC::AL));
1508  }
1509 
1510  MI.eraseFromParent();
1511  return true;
1512  }
1513  case ARM::MOV_ga_pcrel:
1514  case ARM::MOV_ga_pcrel_ldr:
1515  case ARM::t2MOV_ga_pcrel: {
1516  // Expand into movw + movw. Also "add pc" / ldr [pc] in PIC mode.
1517  unsigned LabelId = AFI->createPICLabelUId();
1518  unsigned DstReg = MI.getOperand(0).getReg();
1519  bool DstIsDead = MI.getOperand(0).isDead();
1520  const MachineOperand &MO1 = MI.getOperand(1);
1521  const GlobalValue *GV = MO1.getGlobal();
1522  unsigned TF = MO1.getTargetFlags();
1523  bool isARM = Opcode != ARM::t2MOV_ga_pcrel;
1524  unsigned LO16Opc = isARM ? ARM::MOVi16_ga_pcrel : ARM::t2MOVi16_ga_pcrel;
1525  unsigned HI16Opc = isARM ? ARM::MOVTi16_ga_pcrel :ARM::t2MOVTi16_ga_pcrel;
1526  unsigned LO16TF = TF | ARMII::MO_LO16;
1527  unsigned HI16TF = TF | ARMII::MO_HI16;
1528  unsigned PICAddOpc = isARM
1529  ? (Opcode == ARM::MOV_ga_pcrel_ldr ? ARM::PICLDR : ARM::PICADD)
1530  : ARM::tPICADD;
1531  MachineInstrBuilder MIB1 = BuildMI(MBB, MBBI, MI.getDebugLoc(),
1532  TII->get(LO16Opc), DstReg)
1533  .addGlobalAddress(GV, MO1.getOffset(), TF | LO16TF)
1534  .addImm(LabelId);
1535 
1536  BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(HI16Opc), DstReg)
1537  .addReg(DstReg)
1538  .addGlobalAddress(GV, MO1.getOffset(), TF | HI16TF)
1539  .addImm(LabelId);
1540 
1541  MachineInstrBuilder MIB3 = BuildMI(MBB, MBBI, MI.getDebugLoc(),
1542  TII->get(PICAddOpc))
1543  .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
1544  .addReg(DstReg).addImm(LabelId);
1545  if (isARM) {
1546  MIB3.add(predOps(ARMCC::AL));
1547  if (Opcode == ARM::MOV_ga_pcrel_ldr)
1548  MIB3.cloneMemRefs(MI);
1549  }
1550  TransferImpOps(MI, MIB1, MIB3);
1551  MI.eraseFromParent();
1552  return true;
1553  }
1554 
1555  case ARM::MOVi32imm:
1556  case ARM::MOVCCi32imm:
1557  case ARM::t2MOVi32imm:
1558  case ARM::t2MOVCCi32imm:
1559  ExpandMOV32BitImm(MBB, MBBI);
1560  return true;
1561 
1562  case ARM::SUBS_PC_LR: {
1563  MachineInstrBuilder MIB =
1564  BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::SUBri), ARM::PC)
1565  .addReg(ARM::LR)
1566  .add(MI.getOperand(0))
1567  .add(MI.getOperand(1))
1568  .add(MI.getOperand(2))
1569  .addReg(ARM::CPSR, RegState::Undef);
1570  TransferImpOps(MI, MIB, MIB);
1571  MI.eraseFromParent();
1572  return true;
1573  }
1574  case ARM::VLDMQIA: {
1575  unsigned NewOpc = ARM::VLDMDIA;
1576  MachineInstrBuilder MIB =
1577  BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc));
1578  unsigned OpIdx = 0;
1579 
1580  // Grab the Q register destination.
1581  bool DstIsDead = MI.getOperand(OpIdx).isDead();
1582  unsigned DstReg = MI.getOperand(OpIdx++).getReg();
1583 
1584  // Copy the source register.
1585  MIB.add(MI.getOperand(OpIdx++));
1586 
1587  // Copy the predicate operands.
1588  MIB.add(MI.getOperand(OpIdx++));
1589  MIB.add(MI.getOperand(OpIdx++));
1590 
1591  // Add the destination operands (D subregs).
1592  unsigned D0 = TRI->getSubReg(DstReg, ARM::dsub_0);
1593  unsigned D1 = TRI->getSubReg(DstReg, ARM::dsub_1);
1594  MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead))
1595  .addReg(D1, RegState::Define | getDeadRegState(DstIsDead));
1596 
1597  // Add an implicit def for the super-register.
1598  MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));
1599  TransferImpOps(MI, MIB, MIB);
1600  MIB.cloneMemRefs(MI);
1601  MI.eraseFromParent();
1602  return true;
1603  }
1604 
1605  case ARM::VSTMQIA: {
1606  unsigned NewOpc = ARM::VSTMDIA;
1607  MachineInstrBuilder MIB =
1608  BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc));
1609  unsigned OpIdx = 0;
1610 
1611  // Grab the Q register source.
1612  bool SrcIsKill = MI.getOperand(OpIdx).isKill();
1613  unsigned SrcReg = MI.getOperand(OpIdx++).getReg();
1614 
1615  // Copy the destination register.
1616  MachineOperand Dst(MI.getOperand(OpIdx++));
1617  MIB.add(Dst);
1618 
1619  // Copy the predicate operands.
1620  MIB.add(MI.getOperand(OpIdx++));
1621  MIB.add(MI.getOperand(OpIdx++));
1622 
1623  // Add the source operands (D subregs).
1624  unsigned D0 = TRI->getSubReg(SrcReg, ARM::dsub_0);
1625  unsigned D1 = TRI->getSubReg(SrcReg, ARM::dsub_1);
1626  MIB.addReg(D0, SrcIsKill ? RegState::Kill : 0)
1627  .addReg(D1, SrcIsKill ? RegState::Kill : 0);
1628 
1629  if (SrcIsKill) // Add an implicit kill for the Q register.
1630  MIB->addRegisterKilled(SrcReg, TRI, true);
1631 
1632  TransferImpOps(MI, MIB, MIB);
1633  MIB.cloneMemRefs(MI);
1634  MI.eraseFromParent();
1635  return true;
1636  }
1637 
1638  case ARM::VLD2q8Pseudo:
1639  case ARM::VLD2q16Pseudo:
1640  case ARM::VLD2q32Pseudo:
1641  case ARM::VLD2q8PseudoWB_fixed:
1642  case ARM::VLD2q16PseudoWB_fixed:
1643  case ARM::VLD2q32PseudoWB_fixed:
1644  case ARM::VLD2q8PseudoWB_register:
1645  case ARM::VLD2q16PseudoWB_register:
1646  case ARM::VLD2q32PseudoWB_register:
1647  case ARM::VLD3d8Pseudo:
1648  case ARM::VLD3d16Pseudo:
1649  case ARM::VLD3d32Pseudo:
1650  case ARM::VLD1d8TPseudo:
1651  case ARM::VLD1d16TPseudo:
1652  case ARM::VLD1d32TPseudo:
1653  case ARM::VLD1d64TPseudo:
1654  case ARM::VLD1d64TPseudoWB_fixed:
1655  case ARM::VLD1d64TPseudoWB_register:
1656  case ARM::VLD3d8Pseudo_UPD:
1657  case ARM::VLD3d16Pseudo_UPD:
1658  case ARM::VLD3d32Pseudo_UPD:
1659  case ARM::VLD3q8Pseudo_UPD:
1660  case ARM::VLD3q16Pseudo_UPD:
1661  case ARM::VLD3q32Pseudo_UPD:
1662  case ARM::VLD3q8oddPseudo:
1663  case ARM::VLD3q16oddPseudo:
1664  case ARM::VLD3q32oddPseudo:
1665  case ARM::VLD3q8oddPseudo_UPD:
1666  case ARM::VLD3q16oddPseudo_UPD:
1667  case ARM::VLD3q32oddPseudo_UPD:
1668  case ARM::VLD4d8Pseudo:
1669  case ARM::VLD4d16Pseudo:
1670  case ARM::VLD4d32Pseudo:
1671  case ARM::VLD1d8QPseudo:
1672  case ARM::VLD1d16QPseudo:
1673  case ARM::VLD1d32QPseudo:
1674  case ARM::VLD1d64QPseudo:
1675  case ARM::VLD1d64QPseudoWB_fixed:
1676  case ARM::VLD1d64QPseudoWB_register:
1677  case ARM::VLD1q8HighQPseudo:
1678  case ARM::VLD1q8LowQPseudo_UPD:
1679  case ARM::VLD1q8HighTPseudo:
1680  case ARM::VLD1q8LowTPseudo_UPD:
1681  case ARM::VLD1q16HighQPseudo:
1682  case ARM::VLD1q16LowQPseudo_UPD:
1683  case ARM::VLD1q16HighTPseudo:
1684  case ARM::VLD1q16LowTPseudo_UPD:
1685  case ARM::VLD1q32HighQPseudo:
1686  case ARM::VLD1q32LowQPseudo_UPD:
1687  case ARM::VLD1q32HighTPseudo:
1688  case ARM::VLD1q32LowTPseudo_UPD:
1689  case ARM::VLD1q64HighQPseudo:
1690  case ARM::VLD1q64LowQPseudo_UPD:
1691  case ARM::VLD1q64HighTPseudo:
1692  case ARM::VLD1q64LowTPseudo_UPD:
1693  case ARM::VLD4d8Pseudo_UPD:
1694  case ARM::VLD4d16Pseudo_UPD:
1695  case ARM::VLD4d32Pseudo_UPD:
1696  case ARM::VLD4q8Pseudo_UPD:
1697  case ARM::VLD4q16Pseudo_UPD:
1698  case ARM::VLD4q32Pseudo_UPD:
1699  case ARM::VLD4q8oddPseudo:
1700  case ARM::VLD4q16oddPseudo:
1701  case ARM::VLD4q32oddPseudo:
1702  case ARM::VLD4q8oddPseudo_UPD:
1703  case ARM::VLD4q16oddPseudo_UPD:
1704  case ARM::VLD4q32oddPseudo_UPD:
1705  case ARM::VLD3DUPd8Pseudo:
1706  case ARM::VLD3DUPd16Pseudo:
1707  case ARM::VLD3DUPd32Pseudo:
1708  case ARM::VLD3DUPd8Pseudo_UPD:
1709  case ARM::VLD3DUPd16Pseudo_UPD:
1710  case ARM::VLD3DUPd32Pseudo_UPD:
1711  case ARM::VLD4DUPd8Pseudo:
1712  case ARM::VLD4DUPd16Pseudo:
1713  case ARM::VLD4DUPd32Pseudo:
1714  case ARM::VLD4DUPd8Pseudo_UPD:
1715  case ARM::VLD4DUPd16Pseudo_UPD:
1716  case ARM::VLD4DUPd32Pseudo_UPD:
1717  case ARM::VLD2DUPq8EvenPseudo:
1718  case ARM::VLD2DUPq8OddPseudo:
1719  case ARM::VLD2DUPq16EvenPseudo:
1720  case ARM::VLD2DUPq16OddPseudo:
1721  case ARM::VLD2DUPq32EvenPseudo:
1722  case ARM::VLD2DUPq32OddPseudo:
1723  case ARM::VLD3DUPq8EvenPseudo:
1724  case ARM::VLD3DUPq8OddPseudo:
1725  case ARM::VLD3DUPq16EvenPseudo:
1726  case ARM::VLD3DUPq16OddPseudo:
1727  case ARM::VLD3DUPq32EvenPseudo:
1728  case ARM::VLD3DUPq32OddPseudo:
1729  case ARM::VLD4DUPq8EvenPseudo:
1730  case ARM::VLD4DUPq8OddPseudo:
1731  case ARM::VLD4DUPq16EvenPseudo:
1732  case ARM::VLD4DUPq16OddPseudo:
1733  case ARM::VLD4DUPq32EvenPseudo:
1734  case ARM::VLD4DUPq32OddPseudo:
1735  ExpandVLD(MBBI);
1736  return true;
1737 
1738  case ARM::VST2q8Pseudo:
1739  case ARM::VST2q16Pseudo:
1740  case ARM::VST2q32Pseudo:
1741  case ARM::VST2q8PseudoWB_fixed:
1742  case ARM::VST2q16PseudoWB_fixed:
1743  case ARM::VST2q32PseudoWB_fixed:
1744  case ARM::VST2q8PseudoWB_register:
1745  case ARM::VST2q16PseudoWB_register:
1746  case ARM::VST2q32PseudoWB_register:
1747  case ARM::VST3d8Pseudo:
1748  case ARM::VST3d16Pseudo:
1749  case ARM::VST3d32Pseudo:
1750  case ARM::VST1d8TPseudo:
1751  case ARM::VST1d16TPseudo:
1752  case ARM::VST1d32TPseudo:
1753  case ARM::VST1d64TPseudo:
1754  case ARM::VST3d8Pseudo_UPD:
1755  case ARM::VST3d16Pseudo_UPD:
1756  case ARM::VST3d32Pseudo_UPD:
1757  case ARM::VST1d64TPseudoWB_fixed:
1758  case ARM::VST1d64TPseudoWB_register:
1759  case ARM::VST3q8Pseudo_UPD:
1760  case ARM::VST3q16Pseudo_UPD:
1761  case ARM::VST3q32Pseudo_UPD:
1762  case ARM::VST3q8oddPseudo:
1763  case ARM::VST3q16oddPseudo:
1764  case ARM::VST3q32oddPseudo:
1765  case ARM::VST3q8oddPseudo_UPD:
1766  case ARM::VST3q16oddPseudo_UPD:
1767  case ARM::VST3q32oddPseudo_UPD:
1768  case ARM::VST4d8Pseudo:
1769  case ARM::VST4d16Pseudo:
1770  case ARM::VST4d32Pseudo:
1771  case ARM::VST1d8QPseudo:
1772  case ARM::VST1d16QPseudo:
1773  case ARM::VST1d32QPseudo:
1774  case ARM::VST1d64QPseudo:
1775  case ARM::VST4d8Pseudo_UPD:
1776  case ARM::VST4d16Pseudo_UPD:
1777  case ARM::VST4d32Pseudo_UPD:
1778  case ARM::VST1d64QPseudoWB_fixed:
1779  case ARM::VST1d64QPseudoWB_register:
1780  case ARM::VST1q8HighQPseudo:
1781  case ARM::VST1q8LowQPseudo_UPD:
1782  case ARM::VST1q8HighTPseudo:
1783  case ARM::VST1q8LowTPseudo_UPD:
1784  case ARM::VST1q16HighQPseudo:
1785  case ARM::VST1q16LowQPseudo_UPD:
1786  case ARM::VST1q16HighTPseudo:
1787  case ARM::VST1q16LowTPseudo_UPD:
1788  case ARM::VST1q32HighQPseudo:
1789  case ARM::VST1q32LowQPseudo_UPD:
1790  case ARM::VST1q32HighTPseudo:
1791  case ARM::VST1q32LowTPseudo_UPD:
1792  case ARM::VST1q64HighQPseudo:
1793  case ARM::VST1q64LowQPseudo_UPD:
1794  case ARM::VST1q64HighTPseudo:
1795  case ARM::VST1q64LowTPseudo_UPD:
1796  case ARM::VST4q8Pseudo_UPD:
1797  case ARM::VST4q16Pseudo_UPD:
1798  case ARM::VST4q32Pseudo_UPD:
1799  case ARM::VST4q8oddPseudo:
1800  case ARM::VST4q16oddPseudo:
1801  case ARM::VST4q32oddPseudo:
1802  case ARM::VST4q8oddPseudo_UPD:
1803  case ARM::VST4q16oddPseudo_UPD:
1804  case ARM::VST4q32oddPseudo_UPD:
1805  ExpandVST(MBBI);
1806  return true;
1807 
1808  case ARM::VLD1LNq8Pseudo:
1809  case ARM::VLD1LNq16Pseudo:
1810  case ARM::VLD1LNq32Pseudo:
1811  case ARM::VLD1LNq8Pseudo_UPD:
1812  case ARM::VLD1LNq16Pseudo_UPD:
1813  case ARM::VLD1LNq32Pseudo_UPD:
1814  case ARM::VLD2LNd8Pseudo:
1815  case ARM::VLD2LNd16Pseudo:
1816  case ARM::VLD2LNd32Pseudo:
1817  case ARM::VLD2LNq16Pseudo:
1818  case ARM::VLD2LNq32Pseudo:
1819  case ARM::VLD2LNd8Pseudo_UPD:
1820  case ARM::VLD2LNd16Pseudo_UPD:
1821  case ARM::VLD2LNd32Pseudo_UPD:
1822  case ARM::VLD2LNq16Pseudo_UPD:
1823  case ARM::VLD2LNq32Pseudo_UPD:
1824  case ARM::VLD3LNd8Pseudo:
1825  case ARM::VLD3LNd16Pseudo:
1826  case ARM::VLD3LNd32Pseudo:
1827  case ARM::VLD3LNq16Pseudo:
1828  case ARM::VLD3LNq32Pseudo:
1829  case ARM::VLD3LNd8Pseudo_UPD:
1830  case ARM::VLD3LNd16Pseudo_UPD:
1831  case ARM::VLD3LNd32Pseudo_UPD:
1832  case ARM::VLD3LNq16Pseudo_UPD:
1833  case ARM::VLD3LNq32Pseudo_UPD:
1834  case ARM::VLD4LNd8Pseudo:
1835  case ARM::VLD4LNd16Pseudo:
1836  case ARM::VLD4LNd32Pseudo:
1837  case ARM::VLD4LNq16Pseudo:
1838  case ARM::VLD4LNq32Pseudo:
1839  case ARM::VLD4LNd8Pseudo_UPD:
1840  case ARM::VLD4LNd16Pseudo_UPD:
1841  case ARM::VLD4LNd32Pseudo_UPD:
1842  case ARM::VLD4LNq16Pseudo_UPD:
1843  case ARM::VLD4LNq32Pseudo_UPD:
1844  case ARM::VST1LNq8Pseudo:
1845  case ARM::VST1LNq16Pseudo:
1846  case ARM::VST1LNq32Pseudo:
1847  case ARM::VST1LNq8Pseudo_UPD:
1848  case ARM::VST1LNq16Pseudo_UPD:
1849  case ARM::VST1LNq32Pseudo_UPD:
1850  case ARM::VST2LNd8Pseudo:
1851  case ARM::VST2LNd16Pseudo:
1852  case ARM::VST2LNd32Pseudo:
1853  case ARM::VST2LNq16Pseudo:
1854  case ARM::VST2LNq32Pseudo:
1855  case ARM::VST2LNd8Pseudo_UPD:
1856  case ARM::VST2LNd16Pseudo_UPD:
1857  case ARM::VST2LNd32Pseudo_UPD:
1858  case ARM::VST2LNq16Pseudo_UPD:
1859  case ARM::VST2LNq32Pseudo_UPD:
1860  case ARM::VST3LNd8Pseudo:
1861  case ARM::VST3LNd16Pseudo:
1862  case ARM::VST3LNd32Pseudo:
1863  case ARM::VST3LNq16Pseudo:
1864  case ARM::VST3LNq32Pseudo:
1865  case ARM::VST3LNd8Pseudo_UPD:
1866  case ARM::VST3LNd16Pseudo_UPD:
1867  case ARM::VST3LNd32Pseudo_UPD:
1868  case ARM::VST3LNq16Pseudo_UPD:
1869  case ARM::VST3LNq32Pseudo_UPD:
1870  case ARM::VST4LNd8Pseudo:
1871  case ARM::VST4LNd16Pseudo:
1872  case ARM::VST4LNd32Pseudo:
1873  case ARM::VST4LNq16Pseudo:
1874  case ARM::VST4LNq32Pseudo:
1875  case ARM::VST4LNd8Pseudo_UPD:
1876  case ARM::VST4LNd16Pseudo_UPD:
1877  case ARM::VST4LNd32Pseudo_UPD:
1878  case ARM::VST4LNq16Pseudo_UPD:
1879  case ARM::VST4LNq32Pseudo_UPD:
1880  ExpandLaneOp(MBBI);
1881  return true;
1882 
1883  case ARM::VTBL3Pseudo: ExpandVTBL(MBBI, ARM::VTBL3, false); return true;
1884  case ARM::VTBL4Pseudo: ExpandVTBL(MBBI, ARM::VTBL4, false); return true;
1885  case ARM::VTBX3Pseudo: ExpandVTBL(MBBI, ARM::VTBX3, true); return true;
1886  case ARM::VTBX4Pseudo: ExpandVTBL(MBBI, ARM::VTBX4, true); return true;
1887 
1888  case ARM::CMP_SWAP_8:
1889  if (STI->isThumb())
1890  return ExpandCMP_SWAP(MBB, MBBI, ARM::t2LDREXB, ARM::t2STREXB,
1891  ARM::tUXTB, NextMBBI);
1892  else
1893  return ExpandCMP_SWAP(MBB, MBBI, ARM::LDREXB, ARM::STREXB,
1894  ARM::UXTB, NextMBBI);
1895  case ARM::CMP_SWAP_16:
1896  if (STI->isThumb())
1897  return ExpandCMP_SWAP(MBB, MBBI, ARM::t2LDREXH, ARM::t2STREXH,
1898  ARM::tUXTH, NextMBBI);
1899  else
1900  return ExpandCMP_SWAP(MBB, MBBI, ARM::LDREXH, ARM::STREXH,
1901  ARM::UXTH, NextMBBI);
1902  case ARM::CMP_SWAP_32:
1903  if (STI->isThumb())
1904  return ExpandCMP_SWAP(MBB, MBBI, ARM::t2LDREX, ARM::t2STREX, 0,
1905  NextMBBI);
1906  else
1907  return ExpandCMP_SWAP(MBB, MBBI, ARM::LDREX, ARM::STREX, 0, NextMBBI);
1908 
1909  case ARM::CMP_SWAP_64:
1910  return ExpandCMP_SWAP_64(MBB, MBBI, NextMBBI);
1911  }
1912 }
1913 
1914 bool ARMExpandPseudo::ExpandMBB(MachineBasicBlock &MBB) {
1915  bool Modified = false;
1916 
1917  MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
1918  while (MBBI != E) {
1919  MachineBasicBlock::iterator NMBBI = std::next(MBBI);
1920  Modified |= ExpandMI(MBB, MBBI, NMBBI);
1921  MBBI = NMBBI;
1922  }
1923 
1924  return Modified;
1925 }
1926 
1927 bool ARMExpandPseudo::runOnMachineFunction(MachineFunction &MF) {
1928  STI = &static_cast<const ARMSubtarget &>(MF.getSubtarget());
1929  TII = STI->getInstrInfo();
1930  TRI = STI->getRegisterInfo();
1931  AFI = MF.getInfo<ARMFunctionInfo>();
1932 
1933  bool Modified = false;
1934  for (MachineBasicBlock &MBB : MF)
1935  Modified |= ExpandMBB(MBB);
1936  if (VerifyARMPseudo)
1937  MF.verify(this, "After expanding ARM pseudo instructions.");
1938  return Modified;
1939 }
1940 
1941 /// createARMExpandPseudoPass - returns an instance of the pseudo instruction
1942 /// expansion pass.
1943 FunctionPass *llvm::createARMExpandPseudoPass() {
1944  return new ARMExpandPseudo();
1945 }
llvm::MachineOperand::getTargetFlags
unsigned getTargetFlags() const
Definition: MachineOperand.h:215
llvm::MachineInstrBuilder::add
const MachineInstrBuilder & add(const MachineOperand &MO) const
Definition: MachineInstrBuilder.h:211
llvm::sys::path::end
const_iterator end(StringRef path)
Get end iterator over path.
Definition: Path.cpp:259
llvm::MachineConstantPool
The MachineConstantPool class keeps track of constants referenced by a function which must be spilled...
Definition: MachineConstantPool.h:121
llvm::sys::path::begin
const_iterator begin(StringRef path, Style style=Style::native)
Get begin iterator over path.
Definition: Path.cpp:250
llvm::ARMConstantPoolSymbol::Create
static ARMConstantPoolSymbol * Create(LLVMContext &C, StringRef s, unsigned ID, unsigned char PCAdj)
Definition: ARMConstantPoolValue.cpp:233
llvm
This class represents lattice values for constants.
Definition: AllocatorList.h:24
VerifyARMPseudo
static cl::opt< bool > VerifyARMPseudo("verify-arm-pseudo-expand", cl::Hidden, cl::desc("Verify machine code after expanding ARM pseudos"))
LookupNEONLdSt
static const NEONLdStTableEntry * LookupNEONLdSt(unsigned Opcode)
LookupNEONLdSt - Search the NEONLdStTable for information about a NEON load or store pseudo instructi...
Definition: ARMExpandPseudoInsts.cpp:415
llvm::MachineInstr::getDebugLoc
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:383
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:164
llvm::MachineOperand::getReg
unsigned getReg() const
getReg - Returns the register number.
Definition: MachineOperand.h:349
llvm::ARM_AM::add
Definition: ARMAddressingModes.h:39
llvm::MachineOperand::MO_JumpTableIndex
Address of indexed Jump Table for switch.
Definition: MachineOperand.h:60
Reg
unsigned Reg
Definition: MachineSink.cpp:979
llvm::createARMExpandPseudoPass
FunctionPass * createARMExpandPseudoPass()
createARMExpandPseudoPass - returns an instance of the pseudo instruction expansion pass...
Definition: ARMExpandPseudoInsts.cpp:1943
llvm::AArch64_AM::UXTB
Definition: AArch64AddressingModes.h:41
llvm::ARMII::MO_GOT
MO_GOT - On a symbol operand, this represents a GOT relative relocation.
Definition: ARMBaseInfo.h:257
llvm::MachineOperand::MO_MachineBasicBlock
MachineBasicBlock reference.
Definition: MachineOperand.h:56
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:980
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:34
llvm::MachineInstrBuilder::addGlobalAddress
const MachineInstrBuilder & addGlobalAddress(const GlobalValue *GV, int64_t Offset=0, unsigned char TargetFlags=0) const
Definition: MachineInstrBuilder.h:164
llvm::MachineOperand::MO_RegisterLiveOut
Mask of live-out registers.
Definition: MachineOperand.h:65
llvm::ARM_AM::getSOImmTwoPartSecond
unsigned getSOImmTwoPartSecond(unsigned V)
getSOImmTwoPartSecond - If V is a value that satisfies isSOImmTwoPartVal, return the second chunk of ...
Definition: ARMAddressingModes.h:198
llvm::MachineOperand::isImm
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
Definition: MachineOperand.h:313
llvm::MachineOperand::MO_RegisterMask
Mask of preserved registers.
Definition: MachineOperand.h:64
llvm::MachineBasicBlock::erase
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
Definition: MachineBasicBlock.cpp:1156
NEONLdStTable
static const NEONLdStTableEntry NEONLdStTable[]
Definition: ARMExpandPseudoInsts.cpp:152
llvm::MachineFunctionPass
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
Definition: MachineFunctionPass.h:31
llvm::MCInstrDesc::getNumOperands
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
Definition: MCInstrDesc.h:211
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:128
DEBUG_TYPE
#define DEBUG_TYPE
Definition: ARMExpandPseudoInsts.cpp:30
llvm::MachineOperand::MO_CFIIndex
MCCFIInstruction index.
Definition: MachineOperand.h:68
llvm::TargetFrameLowering::hasFP
virtual bool hasFP(const MachineFunction &MF) const =0
hasFP - Return true if the specified function should have a dedicated frame pointer register...
llvm::MachineOperand::MO_TargetIndex
Target-dependent index+offset operand.
Definition: MachineOperand.h:59
llvm::ARMBaseRegisterInfo::getFrameRegister
unsigned getFrameRegister(const MachineFunction &MF) const override
Definition: ARMBaseRegisterInfo.cpp:429
llvm::MachineOperand::setImplicit
void setImplicit(bool Val=true)
Definition: MachineOperand.h:484
llvm::MachineInstr::eraseFromParent
void eraseFromParent()
Unlink &#39;this&#39; from the containing basic block and delete it.
Definition: MachineInstr.cpp:658
llvm::emitT2RegPlusImmediate
void emitT2RegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, unsigned DestReg, unsigned BaseReg, int NumBytes, ARMCC::CondCodes Pred, unsigned PredReg, const ARMBaseInstrInfo &TII, unsigned MIFlags=0)
Definition: Thumb2InstrInfo.cpp:232
SubReg
unsigned SubReg
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::MachineOperand::MO_ExternalSymbol
Name of external global symbol.
Definition: MachineOperand.h:61
llvm::MachineFrameInfo
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
Definition: MachineFrameInfo.h:106
llvm::MachineInstr::getOpcode
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:409
llvm::MachineOperand::getSymbolName
const char * getSymbolName() const
Definition: MachineOperand.h:592
llvm::MachineInstr::getDesc
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:406
llvm::predOps
static std::array< MachineOperand, 2 > predOps(ARMCC::CondCodes Pred, unsigned PredReg=0)
Get the operands corresponding to the given Pred value.
Definition: ARMBaseInstrInfo.h:455
llvm::MachineOperand::MO_CImmediate
Immediate >64bit operand.
Definition: MachineOperand.h:54
llvm::lower_bound
auto lower_bound(R &&Range, ForwardIt I) -> decltype(adl_begin(Range))
Provide wrappers to std::lower_bound which take ranges instead of having to pass begin/end explicitly...
Definition: STLExtras.h:1282
llvm::MachineBasicBlock::getLastNonDebugInstr
iterator getLastNonDebugInstr()
Returns an iterator to the last non-debug instruction in the basic block, or end().
Definition: MachineBasicBlock.cpp:214
llvm::TargetSubtargetInfo::getInstrInfo
virtual const TargetInstrInfo * getInstrInfo() const
Definition: TargetSubtargetInfo.h:96
llvm::getUndefRegState
unsigned getUndefRegState(bool B)
Definition: MachineInstrBuilder.h:470
llvm::MachineFunction::CreateMachineBasicBlock
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *bb=nullptr)
CreateMachineBasicBlock - Allocate a new MachineBasicBlock.
Definition: MachineFunction.cpp:373
llvm::getKillRegState
unsigned getKillRegState(bool B)
Definition: MachineInstrBuilder.h:464
llvm::getDeadRegState
unsigned getDeadRegState(bool B)
Definition: MachineInstrBuilder.h:467
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition: MachineInstrBuilder.h:304
llvm::MachineOperand::MO_GlobalAddress
Address of a global value.
Definition: MachineOperand.h:62
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:446
llvm::MachineFunction::getFrameInfo
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Definition: MachineFunction.h:463
UseMI
MachineInstrBuilder & UseMI
Definition: AArch64ExpandPseudoInsts.cpp:93
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
llvm::MachineOperand::getGlobal
const GlobalValue * getGlobal() const
Definition: MachineOperand.h:552
llvm::MCRegisterInfo::getSubReg
unsigned getSubReg(unsigned Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo...
Definition: MCRegisterInfo.cpp:32
llvm::MachineFrameInfo::getMaxAlignment
unsigned getMaxAlignment() const
Return the alignment in bytes that this function must be aligned to, which is greater than the defaul...
Definition: MachineFrameInfo.h:562
llvm::MachineOperand::MO_BlockAddress
Address of a basic block.
Definition: MachineOperand.h:63
llvm::MachineFunction::getInfo
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Definition: MachineFunction.h:541
llvm::ARMBaseRegisterInfo::hasBasePointer
bool hasBasePointer(const MachineFunction &MF) const
Definition: ARMBaseRegisterInfo.cpp:367
llvm::FunctionPass
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:285
llvm::ARMCP::GOT_PREL
Thread Local Storage (General Dynamic Mode)
Definition: ARMConstantPoolValue.h:50
llvm::ilist_node_impl::getIterator
self_iterator getIterator()
Definition: ilist_node.h:82
llvm::MachineFunction::getConstantPool
MachineConstantPool * getConstantPool()
getConstantPool - Return the constant pool object for the current function.
Definition: MachineFunction.h:479
llvm::Function::getContext
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function. ...
Definition: Function.cpp:193
llvm::emitARMRegPlusImmediate
void emitARMRegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, unsigned DestReg, unsigned BaseReg, int NumBytes, ARMCC::CondCodes Pred, unsigned PredReg, const ARMBaseInstrInfo &TII, unsigned MIFlags=0)
emitARMRegPlusImmediate / emitT2RegPlusImmediate - Emits a series of instructions to materializea des...
Definition: ARMBaseInstrInfo.cpp:2223
llvm::getInstrPredicate
ARMCC::CondCodes getInstrPredicate(const MachineInstr &MI, unsigned &PredReg)
getInstrPredicate - If instruction is predicated, returns its predicate condition, otherwise returns AL.
Definition: ARMBaseInstrInfo.cpp:1992
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:220
LivePhysRegs.h
This file implements the LivePhysRegs utility for tracking liveness of physical registers.
llvm::MachineConstantPoolValue
Abstract base class for all machine specific constantpool value subclasses.
Definition: MachineConstantPool.h:35
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:136
llvm::ARMII::MO_LO16
MO_LO16 - On a symbol operand, this represents a relocation containing lower 16 bit of the address...
Definition: ARMBaseInfo.h:241
llvm::MachineOperand::setIsKill
void setIsKill(bool Val=true)
Definition: MachineOperand.h:489
llvm::ARM_AM::asr
Definition: ARMAddressingModes.h:30
llvm::MachineBasicBlock::addSuccessor
void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
Definition: MachineBasicBlock.cpp:646
R6
#define R6(n)
llvm::MachineOperand::isGlobal
bool isGlobal() const
isGlobal - Tests if this is a MO_GlobalAddress operand.
Definition: MachineOperand.h:329
llvm::MachineOperand::MO_Predicate
Generic predicate for ISel.
Definition: MachineOperand.h:70
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:49
DefMI
MachineInstrBuilder MachineInstrBuilder & DefMI
Definition: AArch64ExpandPseudoInsts.cpp:94
addExclusiveRegPair
static void addExclusiveRegPair(MachineInstrBuilder &MIB, MachineOperand &Reg, unsigned Flags, bool IsThumb, const TargetRegisterInfo *TRI)
ARM&#39;s ldrexd/strexd take a consecutive register pair (represented as a single GPRPair register)...
Definition: ARMExpandPseudoInsts.cpp:1027
llvm::ARM_AM::getSORegOpc
unsigned getSORegOpc(ShiftOpc ShOp, unsigned Imm)
Definition: ARMAddressingModes.h:111
llvm::MachineOperand::getImm
int64_t getImm() const
Definition: MachineOperand.h:526
llvm::MachineFunction::getFunction
const Function & getFunction() const
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:433
llvm::MachineOperand::MO_MCSymbol
MCSymbol reference (for debug/eh info)
Definition: MachineOperand.h:67
llvm::ARM_AM::rrx
Definition: ARMAddressingModes.h:34
llvm::computeAndAddLiveIns
void computeAndAddLiveIns(LivePhysRegs &LiveRegs, MachineBasicBlock &MBB)
Convenience function combining computeLiveIns() and addLiveIns().
Definition: LivePhysRegs.cpp:327
llvm::MachineInstr::getParent
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:254
llvm::MachineFunctionProperties::set
MachineFunctionProperties & set(Property P)
Definition: MachineFunction.h:165
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
llvm::MachineBasicBlock::getParent
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
Definition: MachineBasicBlock.h:163
llvm::MachineInstrBuilder::addImm
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Definition: MachineInstrBuilder.h:118
llvm::AArch64_AM::UXTH
Definition: AArch64AddressingModes.h:42
llvm::condCodeOp
static MachineOperand condCodeOp(unsigned CCReg=0)
Get the operand corresponding to the conditional code result.
Definition: ARMBaseInstrInfo.h:463
llvm::LivePhysRegs
A set of physical registers with utility functions to track liveness when walking backward/forward th...
Definition: LivePhysRegs.h:49
GetDSubRegs
static void GetDSubRegs(unsigned Reg, NEONRegSpacing RegSpc, const TargetRegisterInfo *TRI, unsigned &D0, unsigned &D1, unsigned &D2, unsigned &D3)
GetDSubRegs - Get 4 D subregisters of a Q, QQ, or QQQQ register, corresponding to the specified regis...
Definition: ARMExpandPseudoInsts.cpp:436
llvm::ARM_AM::lsr
Definition: ARMAddressingModes.h:32
llvm::ARMFunctionInfo
ARMFunctionInfo - This class is derived from MachineFunctionInfo and contains private ARM-specific in...
Definition: ARMMachineFunctionInfo.h:27
llvm::MachineOperand::getOffset
int64_t getOffset() const
Return the offset from the symbol in this operand.
Definition: MachineOperand.h:584
llvm::MachineInstrBuilder::addExternalSymbol
const MachineInstrBuilder & addExternalSymbol(const char *FnName, unsigned char TargetFlags=0) const
Definition: MachineInstrBuilder.h:171
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::MachineInstrBuilder::cloneMemRefs
const MachineInstrBuilder & cloneMemRefs(const MachineInstr &OtherMI) const
Definition: MachineInstrBuilder.h:200
llvm::TargetSubtargetInfo::getFrameLowering
virtual const TargetFrameLowering * getFrameLowering() const
Definition: TargetSubtargetInfo.h:97
llvm::emitThumbRegPlusImmediate
void emitThumbRegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, unsigned DestReg, unsigned BaseReg, int NumBytes, const TargetInstrInfo &TII, const ARMBaseRegisterInfo &MRI, unsigned MIFlags=0)
emitThumbRegPlusImmediate - Emits a series of instructions to materialize a destreg = basereg + immed...
Definition: ThumbRegisterInfo.cpp:186
llvm::MachineBasicBlock::getBasicBlock
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
Definition: MachineBasicBlock.h:147
ARM_EXPAND_PSEUDO_NAME
#define ARM_EXPAND_PSEUDO_NAME
Definition: ARMExpandPseudoInsts.cpp:36
llvm::MachineInstrBuilder::addReg
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Definition: MachineInstrBuilder.h:84
llvm::MachineOperand::MO_FrameIndex
Abstract Stack Frame Index.
Definition: MachineOperand.h:57
llvm::MachineOperand::isSymbol
bool isSymbol() const
isSymbol - Tests if this is a MO_ExternalSymbol operand.
Definition: MachineOperand.h:331
llvm::MachineOperand::isReg
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Definition: MachineOperand.h:311
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::MachineFunction::insert
void insert(iterator MBBI, MachineBasicBlock *MBB)
Definition: MachineFunction.h:640
llvm::operator<
bool operator<(int64_t V1, const APSInt &V2)
Definition: APSInt.h:326
llvm::ARMBaseInstrInfo::getRegisterInfo
virtual const ARMBaseRegisterInfo & getRegisterInfo() const =0
llvm::MachineOperand::MO_FPImmediate
Floating-point immediate operand.
Definition: MachineOperand.h:55
INITIALIZE_PASS
INITIALIZE_PASS(ARMExpandPseudo, DEBUG_TYPE, ARM_EXPAND_PSEUDO_NAME, false, false) void ARMExpandPseudo
TransferImpOps - Transfer implicit operands on the pseudo instruction to the instructions created fro...
Definition: ARMExpandPseudoInsts.cpp:86
IsAnAddressOperand
static bool IsAnAddressOperand(const MachineOperand &MO)
Definition: ARMExpandPseudoInsts.cpp:779
llvm::MachineInstr::addRegisterKilled
bool addRegisterKilled(unsigned IncomingReg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)
We have determined MI kills a register.
Definition: MachineInstr.cpp:1757
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:89
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
llvm::MachineOperand::MO_ConstantPoolIndex
Address of indexed Constant in Constant Pool.
Definition: MachineOperand.h:58
LLVM_ATTRIBUTE_UNUSED
#define LLVM_ATTRIBUTE_UNUSED
Definition: Compiler.h:160
llvm::MachineInstr::getOperand
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:414
llvm::finalizeBundle
void finalizeBundle(MachineBasicBlock &MBB, MachineBasicBlock::instr_iterator FirstMI, MachineBasicBlock::instr_iterator LastMI)
finalizeBundle - Finalize a machine instruction bundle which includes a sequence of instructions star...
Definition: MachineInstrBundle.cpp:125
llvm::MachineOperand::getType
MachineOperandType getType() const
getType - Returns the MachineOperandType for this operand.
Definition: MachineOperand.h:213
llvm::ARM_AM::getSOImmTwoPartFirst
unsigned getSOImmTwoPartFirst(unsigned V)
getSOImmTwoPartFirst - If V is a value that satisfies isSOImmTwoPartVal, return the first chunk of it...
Definition: ARMAddressingModes.h:192
llvm::ARMConstantPoolConstant::Create
static ARMConstantPoolConstant * Create(const Constant *C, unsigned ID)
Definition: ARMConstantPoolValue.cpp:148
llvm::MachineConstantPool::getConstantPoolIndex
unsigned getConstantPoolIndex(const Constant *C, unsigned Alignment)
getConstantPoolIndex - Create a new entry in the constant pool or return an existing one...
Definition: MachineFunction.cpp:1005
makeImplicit
static MachineOperand makeImplicit(const MachineOperand &MO)
Definition: ARMExpandPseudoInsts.cpp:815
llvm::ARMII::MO_HI16
MO_HI16 - On a symbol operand, this represents a relocation containing higher 16 bit of the address...
Definition: ARMBaseInfo.h:245
llvm::MachineFunctionProperties
Properties which a MachineFunction may have at a given point in time.
Definition: MachineFunction.h:113
llvm::MachineOperand::MO_Metadata
Metadata reference (for debug info)
Definition: MachineOperand.h:66
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