45 #define GET_INSTRINFO_CTOR_DTOR 46 #define GET_INSTRMAP_INFO 47 #include "SystemZGenInstrInfo.inc" 49 #define DEBUG_TYPE "systemz-II" 50 STATISTIC(LOCRMuxJumps,
"Number of LOCRMux jump-sequences (lower is better)");
53 static uint64_t
allOnes(
unsigned int Count) {
54 return Count == 0 ? 0 : (uint64_t(1) << (Count - 1) << 1) - 1;
60 if (SystemZ::GRH32BitRegClass.
contains(Reg))
67 void SystemZInstrInfo::anchor() {}
77 unsigned NewOpcode)
const {
84 MBB->
insert(MI, EarlierMI);
89 unsigned Reg128 = LowRegOp.
getReg();
92 HighRegOp.
setReg(RI.getSubReg(HighRegOp.
getReg(), SystemZ::subreg_h64));
93 LowRegOp.
setReg(RI.getSubReg(LowRegOp.
getReg(), SystemZ::subreg_l64));
120 assert(HighOpcode && LowOpcode &&
"Both offsets should be in range");
122 EarlierMI->
setDesc(
get(HighOpcode));
123 MI->setDesc(
get(LowOpcode));
137 assert(NewOpcode &&
"No support for huge argument lists yet");
138 MI->setDesc(
get(NewOpcode));
148 void SystemZInstrInfo::expandRIPseudo(
MachineInstr &MI,
unsigned LowOpcode,
150 bool ConvertHigh)
const {
153 MI.
setDesc(
get(IsHigh ? HighOpcode : LowOpcode));
154 if (IsHigh && ConvertHigh)
162 void SystemZInstrInfo::expandRIEPseudo(
MachineInstr &MI,
unsigned LowOpcode,
164 unsigned HighOpcode)
const {
169 if (!DestIsHigh && !SrcIsHigh)
175 MI.
setDesc(
get(DestIsHigh ? HighOpcode : LowOpcode));
184 void SystemZInstrInfo::expandRXYPseudo(
MachineInstr &MI,
unsigned LowOpcode,
185 unsigned HighOpcode)
const {
195 void SystemZInstrInfo::expandLOCPseudo(
MachineInstr &MI,
unsigned LowOpcode,
196 unsigned HighOpcode)
const {
198 unsigned Opcode =
isHighReg(Reg) ? HighOpcode : LowOpcode;
205 void SystemZInstrInfo::expandLOCRPseudo(
MachineInstr &MI,
unsigned LowOpcode,
206 unsigned HighOpcode)
const {
212 if (!DestIsHigh && !SrcIsHigh)
214 else if (DestIsHigh && SrcIsHigh)
228 void SystemZInstrInfo::expandZExtPseudo(
MachineInstr &MI,
unsigned LowOpcode,
229 unsigned Size)
const {
242 void SystemZInstrInfo::expandLoadStackGuard(
MachineInstr *MI)
const {
246 const unsigned Reg32 = RI.getSubReg(Reg64, SystemZ::subreg_l32);
279 const DebugLoc &DL,
unsigned DestReg,
280 unsigned SrcReg,
unsigned LowLowOpcode,
281 unsigned Size,
bool KillSrc,
282 bool UndefSrc)
const {
286 if (DestIsHigh && SrcIsHigh)
287 Opcode = SystemZ::RISBHH;
288 else if (DestIsHigh && !SrcIsHigh)
289 Opcode = SystemZ::RISBHL;
290 else if (!DestIsHigh && SrcIsHigh)
291 Opcode = SystemZ::RISBLH;
293 return BuildMI(MBB, MBBI, DL,
get(LowLowOpcode), DestReg)
296 unsigned Rotate = (DestIsHigh != SrcIsHigh ? 32 : 0);
297 return BuildMI(MBB, MBBI, DL,
get(Opcode), DestReg)
306 unsigned OpIdx2)
const {
314 case SystemZ::LOCRMux:
315 case SystemZ::LOCFHR:
317 case SystemZ::LOCGR: {
318 auto &WorkingMI = cloneIfNew(MI);
320 unsigned CCValid = WorkingMI.getOperand(3).getImm();
321 unsigned CCMask = WorkingMI.getOperand(4).getImm();
322 WorkingMI.getOperand(4).setImm(CCMask ^ CCValid);
359 int &SrcFrameIndex)
const {
375 DestFrameIndex = FI1;
384 bool AllowModify)
const {
390 while (I != MBB.
begin()) {
392 if (I->isDebugInstr())
397 if (!isUnpredicatedTerminator(*I))
422 while (std::next(I) != MBB.
end())
431 I->eraseFromParent();
452 assert(Cond.
size() == 2 && TBB &&
"Should have seen a conditional branch");
460 unsigned OldCCValid = Cond[0].getImm();
461 unsigned OldCCMask = Cond[1].getImm();
462 if (OldCCValid == Branch.
CCValid && OldCCMask == Branch.
CCMask)
473 int *BytesRemoved)
const {
474 assert(!BytesRemoved &&
"code size not handled");
480 while (I != MBB.
begin()) {
482 if (I->isDebugInstr())
489 I->eraseFromParent();
499 assert(Cond.
size() == 2 &&
"Invalid condition");
500 Cond[1].setImm(Cond[1].getImm() ^ Cond[0].getImm());
509 int *BytesAdded)
const {
515 assert(TBB &&
"insertBranch must not be told to insert a fallthrough");
517 "SystemZ branch conditions have one component!");
518 assert(!BytesAdded &&
"code size not handled");
522 assert(!FBB &&
"Unconditional branch with multiple successors!");
529 unsigned CCValid = Cond[0].getImm();
530 unsigned CCMask = Cond[1].getImm();
531 BuildMI(&MBB, DL,
get(SystemZ::BRC))
544 unsigned &SrcReg2,
int &
Mask,
546 assert(MI.
isCompare() &&
"Caller should have checked for a comparison");
562 unsigned TrueReg,
unsigned FalseReg,
563 int &CondCycles,
int &TrueCycles,
564 int &FalseCycles)
const {
568 if (Pred.
size() != 2)
580 SystemZ::GRX32BitRegClass.hasSubClassEq(RC)) ||
581 SystemZ::GR32BitRegClass.hasSubClassEq(RC) ||
582 SystemZ::GR64BitRegClass.hasSubClassEq(RC)) {
595 const DebugLoc &DL,
unsigned DstReg,
598 unsigned FalseReg)
const {
602 assert(Pred.
size() == 2 &&
"Invalid condition");
603 unsigned CCValid = Pred[0].getImm();
604 unsigned CCMask = Pred[1].getImm();
607 if (SystemZ::GRX32BitRegClass.hasSubClassEq(RC)) {
609 Opc = SystemZ::LOCRMux;
615 BuildMI(MBB, I, DL,
get(TargetOpcode::COPY), TReg).
addReg(TrueReg);
616 BuildMI(MBB, I, DL,
get(TargetOpcode::COPY), FReg).
addReg(FalseReg);
620 }
else if (SystemZ::GR64BitRegClass.hasSubClassEq(RC))
621 Opc = SystemZ::LOCGR;
625 BuildMI(MBB, I, DL,
get(Opc), DstReg)
634 if (DefOpc != SystemZ::LHIMux && DefOpc != SystemZ::LHI &&
635 DefOpc != SystemZ::LGHI)
646 case SystemZ::LOCRMux:
649 NewUseOpc = SystemZ::LOCHIMux;
653 UseIdx = 2, CommuteIdx = 1;
660 NewUseOpc = SystemZ::LOCGHI;
664 UseIdx = 2, CommuteIdx = 1;
672 if (CommuteIdx != -1)
673 if (!commuteInstruction(UseMI,
false, CommuteIdx, UseIdx))
688 Opcode == SystemZ::Trap ||
689 Opcode == SystemZ::CallJG ||
690 Opcode == SystemZ::CallBR)
697 unsigned NumCycles,
unsigned ExtraPredCycles,
711 return NumCycles == 1;
716 unsigned NumCyclesT,
unsigned ExtraPredCyclesT,
718 unsigned NumCyclesF,
unsigned ExtraPredCyclesF,
728 return NumCycles == 1;
733 assert(Pred.
size() == 2 &&
"Invalid condition");
734 unsigned CCValid = Pred[0].getImm();
735 unsigned CCMask = Pred[1].getImm();
736 assert(CCMask > 0 && CCMask < 15 &&
"Invalid predicate");
738 if (Opcode == SystemZ::Trap) {
739 MI.
setDesc(
get(SystemZ::CondTrap));
741 .addImm(CCValid).
addImm(CCMask)
746 MI.
setDesc(
get(SystemZ::CondReturn));
748 .addImm(CCValid).
addImm(CCMask)
752 if (Opcode == SystemZ::CallJG) {
757 MI.
setDesc(
get(SystemZ::CallBRCL));
766 if (Opcode == SystemZ::CallBR) {
769 MI.
setDesc(
get(SystemZ::CallBCR));
771 .addImm(CCValid).
addImm(CCMask)
781 const DebugLoc &DL,
unsigned DestReg,
782 unsigned SrcReg,
bool KillSrc)
const {
786 if (SystemZ::GR128BitRegClass.
contains(DestReg, SrcReg)) {
787 copyPhysReg(MBB, MBBI, DL, RI.getSubReg(DestReg, SystemZ::subreg_h64),
788 RI.getSubReg(SrcReg, SystemZ::subreg_h64), KillSrc);
791 copyPhysReg(MBB, MBBI, DL, RI.getSubReg(DestReg, SystemZ::subreg_l64),
792 RI.getSubReg(SrcReg, SystemZ::subreg_l64), KillSrc);
793 MachineInstrBuilder(*MBB.
getParent(), std::prev(MBBI))
798 if (SystemZ::GRX32BitRegClass.
contains(DestReg, SrcReg)) {
799 emitGRX32Move(MBB, MBBI, DL, DestReg, SrcReg, SystemZ::LR, 32, KillSrc,
805 if (SystemZ::VR128BitRegClass.
contains(DestReg) &&
806 SystemZ::FP128BitRegClass.
contains(SrcReg)) {
808 RI.getMatchingSuperReg(RI.getSubReg(SrcReg, SystemZ::subreg_h64),
809 SystemZ::subreg_h64, &SystemZ::VR128BitRegClass);
811 RI.getMatchingSuperReg(RI.getSubReg(SrcReg, SystemZ::subreg_l64),
812 SystemZ::subreg_h64, &SystemZ::VR128BitRegClass);
814 BuildMI(MBB, MBBI, DL,
get(SystemZ::VMRHG), DestReg)
819 if (SystemZ::FP128BitRegClass.
contains(DestReg) &&
820 SystemZ::VR128BitRegClass.
contains(SrcReg)) {
822 RI.getMatchingSuperReg(RI.getSubReg(DestReg, SystemZ::subreg_h64),
823 SystemZ::subreg_h64, &SystemZ::VR128BitRegClass);
825 RI.getMatchingSuperReg(RI.getSubReg(DestReg, SystemZ::subreg_l64),
826 SystemZ::subreg_h64, &SystemZ::VR128BitRegClass);
828 if (DestRegHi != SrcReg)
829 copyPhysReg(MBB, MBBI, DL, DestRegHi, SrcReg,
false);
830 BuildMI(MBB, MBBI, DL,
get(SystemZ::VREPG), DestRegLo)
836 if (SrcReg == SystemZ::CC) {
841 MIB->addRegisterKilled(SrcReg, TRI);
845 if (DestReg == SystemZ::CC) {
846 BuildMI(MBB, MBBI, DL,
get(SystemZ::TMLH))
854 if (SystemZ::GR64BitRegClass.
contains(DestReg, SrcReg))
855 Opcode = SystemZ::LGR;
856 else if (SystemZ::FP32BitRegClass.
contains(DestReg, SrcReg))
858 Opcode = STI.
hasVector() ? SystemZ::LDR32 : SystemZ::LER;
859 else if (SystemZ::FP64BitRegClass.
contains(DestReg, SrcReg))
861 else if (SystemZ::FP128BitRegClass.
contains(DestReg, SrcReg))
862 Opcode = SystemZ::LXR;
863 else if (SystemZ::VR32BitRegClass.
contains(DestReg, SrcReg))
864 Opcode = SystemZ::VLR32;
865 else if (SystemZ::VR64BitRegClass.
contains(DestReg, SrcReg))
866 Opcode = SystemZ::VLR64;
867 else if (SystemZ::VR128BitRegClass.
contains(DestReg, SrcReg))
868 Opcode = SystemZ::VLR;
869 else if (SystemZ::AR32BitRegClass.
contains(DestReg, SrcReg))
870 Opcode = SystemZ::CPYA;
871 else if (SystemZ::AR32BitRegClass.
contains(DestReg) &&
872 SystemZ::GR32BitRegClass.
contains(SrcReg))
873 Opcode = SystemZ::SAR;
874 else if (SystemZ::GR32BitRegClass.
contains(DestReg) &&
875 SystemZ::AR32BitRegClass.
contains(SrcReg))
876 Opcode = SystemZ::EAR;
880 BuildMI(MBB, MBBI, DL,
get(Opcode), DestReg)
892 unsigned LoadOpcode, StoreOpcode;
907 unsigned LoadOpcode, StoreOpcode;
917 return ((MCID.
TSFlags & Flag) &&
926 LogicOp(
unsigned regSize,
unsigned immLSB,
unsigned immSize)
927 : RegSize(regSize), ImmLSB(immLSB), ImmSize(immSize) {}
929 explicit operator bool()
const {
return RegSize; }
931 unsigned RegSize = 0;
933 unsigned ImmSize = 0;
940 case SystemZ::NILMux:
return LogicOp(32, 0, 16);
941 case SystemZ::NIHMux:
return LogicOp(32, 16, 16);
942 case SystemZ::NILL64:
return LogicOp(64, 0, 16);
943 case SystemZ::NILH64:
return LogicOp(64, 16, 16);
944 case SystemZ::NIHL64:
return LogicOp(64, 32, 16);
945 case SystemZ::NIHH64:
return LogicOp(64, 48, 16);
946 case SystemZ::NIFMux:
return LogicOp(32, 0, 32);
947 case SystemZ::NILF64:
return LogicOp(64, 0, 32);
948 case SystemZ::NIHF64:
return LogicOp(64, 32, 32);
949 default:
return LogicOp();
956 if (CCDef !=
nullptr)
968 for (
unsigned I = 1;
I < NumOps; ++
I) {
991 if (STI.hasDistinctOps()) {
994 unsigned DestReg = Dest.
getReg();
995 unsigned SrcReg = Src.
getReg();
999 if (Opcode == SystemZ::AHIMux &&
1007 int ThreeOperandOpcode = SystemZ::getThreeOperandOpcode(Opcode);
1008 if (ThreeOperandOpcode >= 0) {
1019 for (
unsigned I = 2;
I < NumOps; ++
I)
1030 Imm |=
allOnes(And.RegSize) & ~(
allOnes(And.ImmSize) << And.ImmLSB);
1031 unsigned Start, End;
1034 if (And.RegSize == 64) {
1035 NewOpcode = SystemZ::RISBG;
1037 if (STI.hasMiscellaneousExtensions())
1038 NewOpcode = SystemZ::RISBGN;
1040 NewOpcode = SystemZ::RISBMux;
1070 if (Ops.
size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
1071 if (LIS !=
nullptr && (Opcode == SystemZ::LA || Opcode == SystemZ::LAY) &&
1082 if (!CCLiveRange.
liveAt(MISlot)) {
1098 if (Ops.
size() != 1)
1101 unsigned OpNum = Ops[0];
1105 "Invalid size combination");
1107 if ((Opcode == SystemZ::AHI || Opcode == SystemZ::AGHI) && OpNum == 0 &&
1110 Opcode = (Opcode == SystemZ::AHI ? SystemZ::ASI : SystemZ::AGSI);
1120 if ((Opcode == SystemZ::ALFI && OpNum == 0 &&
1122 (Opcode == SystemZ::ALGFI && OpNum == 0 &&
1125 Opcode = (Opcode == SystemZ::ALFI ? SystemZ::ALSI : SystemZ::ALGSI);
1135 if ((Opcode == SystemZ::SLFI && OpNum == 0 &&
1137 (Opcode == SystemZ::SLGFI && OpNum == 0 &&
1140 Opcode = (Opcode == SystemZ::SLFI ? SystemZ::ALSI : SystemZ::ALGSI);
1150 if (Opcode == SystemZ::LGDR || Opcode == SystemZ::LDGR) {
1151 bool Op0IsGPR = (Opcode == SystemZ::LGDR);
1152 bool Op1IsGPR = (Opcode == SystemZ::LDGR);
1156 unsigned StoreOpcode = Op1IsGPR ? SystemZ::STG : SystemZ::STD;
1160 .addFrameIndex(FrameIndex)
1167 unsigned LoadOpcode = Op0IsGPR ? SystemZ::LG :
SystemZ::LD;
1171 .addFrameIndex(FrameIndex)
1202 .addMemOperand(MMO);
1220 int MemOpcode = SystemZ::getMemOpcode(Opcode);
1221 if (MemOpcode >= 0) {
1223 if (OpNum == NumOps - 1) {
1226 assert(AccessBytes != 0 &&
"Size of access should be known");
1227 assert(AccessBytes <= Size &&
"Access outside the frame index");
1228 uint64_t
Offset = Size - AccessBytes;
1231 for (
unsigned I = 0;
I < OpNum; ++
I)
1254 splitMove(MI, SystemZ::LG);
1257 case SystemZ::ST128:
1258 splitMove(MI, SystemZ::STG);
1266 splitMove(MI, SystemZ::STD);
1269 case SystemZ::LBMux:
1270 expandRXYPseudo(MI, SystemZ::LB, SystemZ::LBH);
1273 case SystemZ::LHMux:
1274 expandRXYPseudo(MI, SystemZ::LH, SystemZ::LHH);
1277 case SystemZ::LLCRMux:
1278 expandZExtPseudo(MI, SystemZ::LLCR, 8);
1281 case SystemZ::LLHRMux:
1282 expandZExtPseudo(MI, SystemZ::LLHR, 16);
1285 case SystemZ::LLCMux:
1286 expandRXYPseudo(MI, SystemZ::LLC, SystemZ::LLCH);
1289 case SystemZ::LLHMux:
1290 expandRXYPseudo(MI, SystemZ::LLH, SystemZ::LLHH);
1294 expandRXYPseudo(MI, SystemZ::L, SystemZ::LFH);
1297 case SystemZ::LOCMux:
1298 expandLOCPseudo(MI, SystemZ::LOC, SystemZ::LOCFH);
1301 case SystemZ::LOCHIMux:
1302 expandLOCPseudo(MI, SystemZ::LOCHI, SystemZ::LOCHHI);
1305 case SystemZ::LOCRMux:
1306 expandLOCRPseudo(MI, SystemZ::LOCR, SystemZ::LOCFHR);
1309 case SystemZ::STCMux:
1310 expandRXYPseudo(MI, SystemZ::STC, SystemZ::STCH);
1313 case SystemZ::STHMux:
1314 expandRXYPseudo(MI, SystemZ::STH, SystemZ::STHH);
1317 case SystemZ::STMux:
1321 case SystemZ::STOCMux:
1322 expandLOCPseudo(MI, SystemZ::STOC, SystemZ::STOCFH);
1325 case SystemZ::LHIMux:
1326 expandRIPseudo(MI, SystemZ::LHI, SystemZ::IIHF,
true);
1329 case SystemZ::IIFMux:
1330 expandRIPseudo(MI, SystemZ::IILF, SystemZ::IIHF,
false);
1333 case SystemZ::IILMux:
1334 expandRIPseudo(MI, SystemZ::IILL, SystemZ::IIHL,
false);
1337 case SystemZ::IIHMux:
1338 expandRIPseudo(MI, SystemZ::IILH, SystemZ::IIHH,
false);
1341 case SystemZ::NIFMux:
1342 expandRIPseudo(MI, SystemZ::NILF, SystemZ::NIHF,
false);
1345 case SystemZ::NILMux:
1346 expandRIPseudo(MI, SystemZ::NILL, SystemZ::NIHL,
false);
1349 case SystemZ::NIHMux:
1350 expandRIPseudo(MI, SystemZ::NILH, SystemZ::NIHH,
false);
1353 case SystemZ::OIFMux:
1354 expandRIPseudo(MI, SystemZ::OILF, SystemZ::OIHF,
false);
1357 case SystemZ::OILMux:
1358 expandRIPseudo(MI, SystemZ::OILL, SystemZ::OIHL,
false);
1361 case SystemZ::OIHMux:
1362 expandRIPseudo(MI, SystemZ::OILH, SystemZ::OIHH,
false);
1365 case SystemZ::XIFMux:
1366 expandRIPseudo(MI, SystemZ::XILF, SystemZ::XIHF,
false);
1369 case SystemZ::TMLMux:
1370 expandRIPseudo(MI, SystemZ::TMLL, SystemZ::TMHL,
false);
1373 case SystemZ::TMHMux:
1374 expandRIPseudo(MI, SystemZ::TMLH, SystemZ::TMHH,
false);
1377 case SystemZ::AHIMux:
1378 expandRIPseudo(MI, SystemZ::AHI, SystemZ::AIH,
false);
1381 case SystemZ::AHIMuxK:
1382 expandRIEPseudo(MI, SystemZ::AHI, SystemZ::AHIK, SystemZ::AIH);
1385 case SystemZ::AFIMux:
1386 expandRIPseudo(MI, SystemZ::AFI, SystemZ::AIH,
false);
1389 case SystemZ::CHIMux:
1390 expandRIPseudo(MI, SystemZ::CHI, SystemZ::CIH,
false);
1393 case SystemZ::CFIMux:
1394 expandRIPseudo(MI, SystemZ::CFI, SystemZ::CIH,
false);
1397 case SystemZ::CLFIMux:
1398 expandRIPseudo(MI, SystemZ::CLFI, SystemZ::CLIH,
false);
1402 expandRXYPseudo(MI,
SystemZ::C, SystemZ::CHF);
1405 case SystemZ::CLMux:
1406 expandRXYPseudo(MI, SystemZ::CL, SystemZ::CLHF);
1409 case SystemZ::RISBMux: {
1412 if (SrcIsHigh == DestIsHigh)
1413 MI.
setDesc(
get(DestIsHigh ? SystemZ::RISBHH : SystemZ::RISBLL));
1415 MI.
setDesc(
get(DestIsHigh ? SystemZ::RISBHL : SystemZ::RISBLH));
1422 splitAdjDynAlloc(MI);
1425 case TargetOpcode::LOAD_STACK_GUARD:
1426 expandLoadStackGuard(&MI);
1459 case SystemZ::BRCTH:
1463 case SystemZ::BRCTG:
1482 case SystemZ::CLGIJ:
1483 case SystemZ::CLGRJ:
1493 unsigned &LoadOpcode,
1494 unsigned &StoreOpcode)
const {
1495 if (RC == &SystemZ::GR32BitRegClass || RC == &SystemZ::ADDR32BitRegClass) {
1496 LoadOpcode = SystemZ::L;
1498 }
else if (RC == &SystemZ::GRH32BitRegClass) {
1499 LoadOpcode = SystemZ::LFH;
1500 StoreOpcode = SystemZ::STFH;
1501 }
else if (RC == &SystemZ::GRX32BitRegClass) {
1502 LoadOpcode = SystemZ::LMux;
1503 StoreOpcode = SystemZ::STMux;
1504 }
else if (RC == &SystemZ::GR64BitRegClass ||
1505 RC == &SystemZ::ADDR64BitRegClass) {
1506 LoadOpcode = SystemZ::LG;
1507 StoreOpcode = SystemZ::STG;
1508 }
else if (RC == &SystemZ::GR128BitRegClass ||
1509 RC == &SystemZ::ADDR128BitRegClass) {
1510 LoadOpcode = SystemZ::L128;
1511 StoreOpcode = SystemZ::ST128;
1512 }
else if (RC == &SystemZ::FP32BitRegClass) {
1514 StoreOpcode = SystemZ::STE;
1515 }
else if (RC == &SystemZ::FP64BitRegClass) {
1517 StoreOpcode = SystemZ::STD;
1518 }
else if (RC == &SystemZ::FP128BitRegClass) {
1519 LoadOpcode = SystemZ::LX;
1520 StoreOpcode = SystemZ::STX;
1521 }
else if (RC == &SystemZ::VR32BitRegClass) {
1522 LoadOpcode = SystemZ::VL32;
1523 StoreOpcode = SystemZ::VST32;
1524 }
else if (RC == &SystemZ::VR64BitRegClass) {
1525 LoadOpcode = SystemZ::VL64;
1526 StoreOpcode = SystemZ::VST64;
1527 }
else if (RC == &SystemZ::VF128BitRegClass ||
1528 RC == &SystemZ::VR128BitRegClass) {
1529 LoadOpcode = SystemZ::VL;
1530 StoreOpcode = SystemZ::VST;
1539 if (isUInt<12>(Offset) && isUInt<12>(Offset2)) {
1541 int Disp12Opcode = SystemZ::getDisp12Opcode(Opcode);
1542 if (Disp12Opcode >= 0)
1543 return Disp12Opcode;
1549 if (isInt<20>(Offset) && isInt<20>(Offset2)) {
1551 int Disp20Opcode = SystemZ::getDisp20Opcode(Opcode);
1552 if (Disp20Opcode >= 0)
1553 return Disp20Opcode;
1566 case SystemZ::LG:
return SystemZ::LTG;
1567 case SystemZ::LGF:
return SystemZ::LTGF;
1568 case SystemZ::LR:
return SystemZ::LTR;
1569 case SystemZ::LGFR:
return SystemZ::LTGFR;
1570 case SystemZ::LGR:
return SystemZ::LTGR;
1571 case SystemZ::LER:
return SystemZ::LTEBR;
1573 case SystemZ::LXR:
return SystemZ::LTXBR;
1574 case SystemZ::LCDFR:
return SystemZ::LCDBR;
1575 case SystemZ::LPDFR:
return SystemZ::LPDBR;
1576 case SystemZ::LNDFR:
return SystemZ::LNDBR;
1577 case SystemZ::LCDFR_32:
return SystemZ::LCEBR;
1578 case SystemZ::LPDFR_32:
return SystemZ::LPEBR;
1579 case SystemZ::LNDFR_32:
return SystemZ::LNEBR;
1584 case SystemZ::RISBGN:
return SystemZ::RISBG;
1594 uint64_t Top = (Mask >> First) + 1;
1595 if ((Top & -Top) == Top) {
1604 unsigned &Start,
unsigned &End)
const {
1612 unsigned LSB, Length;
1614 Start = 63 - (LSB + Length - 1);
1622 assert(LSB > 0 &&
"Bottom bit must be set");
1623 assert(LSB + Length < BitSize &&
"Top bit must be set");
1624 Start = 63 - (LSB - 1);
1625 End = 63 - (LSB + Length);
1642 case SystemZ::CLGFI:
1648 if (!STI.hasMiscellaneousExtensions())
1658 return SystemZ::CRJ;
1660 return SystemZ::CGRJ;
1662 return SystemZ::CIJ;
1664 return SystemZ::CGIJ;
1666 return SystemZ::CLRJ;
1668 return SystemZ::CLGRJ;
1670 return SystemZ::CLIJ;
1671 case SystemZ::CLGFI:
1672 return SystemZ::CLGIJ;
1679 return SystemZ::CRBReturn;
1681 return SystemZ::CGRBReturn;
1683 return SystemZ::CIBReturn;
1685 return SystemZ::CGIBReturn;
1687 return SystemZ::CLRBReturn;
1689 return SystemZ::CLGRBReturn;
1691 return SystemZ::CLIBReturn;
1692 case SystemZ::CLGFI:
1693 return SystemZ::CLGIBReturn;
1700 return SystemZ::CRBCall;
1702 return SystemZ::CGRBCall;
1704 return SystemZ::CIBCall;
1706 return SystemZ::CGIBCall;
1708 return SystemZ::CLRBCall;
1710 return SystemZ::CLGRBCall;
1712 return SystemZ::CLIBCall;
1713 case SystemZ::CLGFI:
1714 return SystemZ::CLGIBCall;
1721 return SystemZ::CRT;
1723 return SystemZ::CGRT;
1725 return SystemZ::CIT;
1727 return SystemZ::CGIT;
1729 return SystemZ::CLRT;
1731 return SystemZ::CLGRT;
1733 return SystemZ::CLFIT;
1734 case SystemZ::CLGFI:
1735 return SystemZ::CLGIT;
1737 return SystemZ::CLT;
1739 return SystemZ::CLGT;
1748 if (!STI.hasLoadAndTrap())
1753 return SystemZ::LAT;
1755 return SystemZ::LGAT;
1757 return SystemZ::LFHAT;
1759 return SystemZ::LLGFAT;
1761 return SystemZ::LLGTAT;
1768 unsigned Reg, uint64_t
Value)
const {
1772 Opcode = SystemZ::LGHI;
1774 Opcode = SystemZ::LLILL;
1776 Opcode = SystemZ::LLILH;
1780 Opcode = SystemZ::LGFI;
1800 bool SameVal = (VALa && VALb && (VALa == VALb));
1804 if (PSVa && PSVb && (PSVa == PSVb))
1810 int LowOffset = OffsetA < OffsetB ? OffsetA : OffsetB;
1811 int HighOffset = OffsetA < OffsetB ? OffsetB : OffsetA;
1812 int LowWidth = (LowOffset == OffsetA) ? WidthA : WidthB;
1813 if (LowOffset + LowWidth <= HighOffset)
void loadImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned Reg, uint64_t Value) const
const MachineInstrBuilder & add(const MachineOperand &MO) const
void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, unsigned DstReg, ArrayRef< MachineOperand > Cond, unsigned TrueReg, unsigned FalseReg) const override
bool expandPostRAPseudo(MachineInstr &MBBI) const override
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
bool contains(unsigned Reg) const
Return true if the specified register is included in this register class.
MachineBasicBlock * getMBB() const
const int64_t CallFrameSize
const TargetRegisterClass * getRegClass(unsigned Reg) const
Return the register class of the specified virtual register.
SystemZInstrInfo(SystemZSubtarget &STI)
This class represents lattice values for constants.
MachineOperand * findRegisterDefOperand(unsigned Reg, bool isDead=false, const TargetRegisterInfo *TRI=nullptr)
Wrapper for findRegisterDefOperandIdx, it returns a pointer to the MachineOperand rather than an inde...
MachineInstr * foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex, LiveIntervals *LIS=nullptr) const override
bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg, unsigned &SrcReg2, int &Mask, int &Value) const override
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
void push_back(const T &Elt)
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Describe properties that are true of each instruction in the target description file.
unsigned getReg() const
getReg - Returns the register number.
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
unsigned getSubReg() const
bool hasLoadStoreOnCond() const
constexpr bool isInt< 8 >(int64_t x)
uint64_t getSize() const
Return the size in bytes of the memory reference.
bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, BranchProbability Probability) const override
constexpr bool isInt< 16 >(int64_t x)
STATISTIC(NumFunctions, "Total number of functions")
unsigned const TargetRegisterInfo * TRI
void setIsDead(bool Val=true)
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
MachineInstr * CreateMachineInstr(const MCInstrDesc &MCID, const DebugLoc &DL, bool NoImp=false)
CreateMachineInstr - Allocate a new MachineInstr.
const unsigned CCMASK_ICMP
bool PredicateInstruction(MachineInstr &MI, ArrayRef< MachineOperand > Pred) const override
bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, unsigned Reg, MachineRegisterInfo *MRI) const override
return AArch64::GPR64RegClass contains(Reg)
static uint64_t allOnes(unsigned int Count)
This class represents the liveness of a register, stack slot, etc.
bool areMemAccessesTriviallyDisjoint(MachineInstr &MIa, MachineInstr &MIb, AliasAnalysis *AA=nullptr) const override
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
void eraseFromParent()
This method unlinks 'this' from the containing function and deletes it.
A description of a memory reference used in the backend.
unsigned getNumOperands() const
Retuns the total number of operands.
VNInfo::Allocator & getVNInfoAllocator()
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
SlotIndex getInstructionIndex(const MachineInstr &MI) const
Returns the base index for the given instruction.
unsigned getLoadAndTest(unsigned Opcode) const
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
const char * getSymbolName() const
unsigned getLoadAndTrap(unsigned Opcode) const
INLINEASM - Represents an inline asm block.
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
static LogicOp interpretAndImmediate(unsigned Opcode)
SlotIndex getRegSlot(bool EC=false) const
Returns the register use/def slot in the current instruction for a normal or early-clobber def...
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
bool isPredicable(const MachineInstr &MI) const override
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
const MachineOperand * Target
iterator getLastNonDebugInstr()
Returns an iterator to the last non-debug instruction in the basic block, or end().
const unsigned CCMASK_ANY
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
unsigned getUndefRegState(bool B)
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
bool isStackSlotCopy(const MachineInstr &MI, int &DestFrameIndex, int &SrcFrameIndex) const override
VNInfo * createDeadDef(SlotIndex Def, VNInfo::Allocator &VNIAlloc)
createDeadDef - Make sure the range has a value defined at Def.
const TargetRegisterClass * constrainRegClass(unsigned Reg, const TargetRegisterClass *RC, unsigned MinNumRegs=0)
constrainRegClass - Constrain the register class of the specified virtual register to be a common sub...
BasicBlockListType::iterator iterator
unsigned getKillRegState(bool B)
void ChangeToImmediate(int64_t ImmVal)
ChangeToImmediate - Replace this operand with a new immediate operand of the specified value...
Flag
These should be considered private to the implementation of the MCInstrDesc class.
const Value * getValue() const
Return the base address of the memory access.
MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned CommuteOpIdx1, unsigned CommuteOpIdx2) const override
Commutes the operands in the given instruction by changing the operands order and/or changing the ins...
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
virtual MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const
This method commutes the operands of the given machine instruction MI.
static void transferDeadCC(MachineInstr *OldMI, MachineInstr *NewMI)
Control flow instructions. These all have token chains.
constexpr bool isUInt< 8 >(uint64_t x)
unsigned const MachineRegisterInfo * MRI
The instances of the Type class are immutable: once they are created, they are never changed...
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
static unsigned getAccessSize(unsigned int Flags)
bool isCompare(QueryType Type=IgnoreBundle) const
Return true if this instruction is a comparison.
bool liveAt(SlotIndex index) const
bool registerDefIsDead(unsigned Reg, const TargetRegisterInfo *TRI=nullptr) const
Returns true if the register is dead in this machine instruction.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
MachineInstrBuilder & UseMI
size_t size() const
size - Get the array size.
unsigned getOpcodeForOffset(unsigned Opcode, int64_t Offset) const
const MCAsmInfo * getMCAsmInfo() const
Return target specific asm information.
bool hasOneMemOperand() const
Return true if this instruction has exactly one MachineMemOperand.
const MachineInstrBuilder & addRegMask(const uint32_t *Mask) const
bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, BranchProbability Probability) const override
const PseudoSourceValue * getPseudoValue() const
void setImm(int64_t immVal)
const MachineInstrBuilder & addFrameIndex(int Idx) const
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIdx, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
static bool isImmLH(uint64_t Val)
T findFirstSet(T Val, ZeroBehavior ZB=ZB_Max)
Get the index of the first set bit starting from the least significant bit.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
unsigned getNumExplicitOperands() const
Returns the number of non-implicit operands.
void setIsKill(bool Val=true)
static const MachineInstrBuilder & addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset=0, bool mem=true)
addFrameReference - This function is used to add a reference to the base of an abstract object on the...
static bool isHighReg(unsigned int Reg)
void replaceKillInstruction(unsigned Reg, MachineInstr &OldMI, MachineInstr &NewMI)
replaceKillInstruction - Update register kill info by replacing a kill instruction with a new one...
void setDesc(const MCInstrDesc &tid)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one...
constexpr bool isInt< 32 >(int64_t x)
unsigned getMaxCallFrameSize() const
Return the maximum size of a call frame that must be allocated for an outgoing function call...
mmo_iterator memoperands_begin() const
Access to memory operands of the instruction.
MachineInstr * CloneMachineInstr(const MachineInstr *Orig)
Create a new MachineInstr which is a copy of Orig, identical in all ways except the instruction has n...
MachineOperand class - Representation of each machine instruction operand.
MachineInstrBuilder MachineInstrBuilder & DefMI
static bool isStringOfOnes(uint64_t Mask, unsigned &LSB, unsigned &Length)
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
const unsigned CCMASK_CMP_NE
MachineInstr * convertToThreeAddress(MachineFunction::iterator &MFI, MachineInstr &MI, LiveVariables *LV) const override
bool isLayoutSuccessor(const MachineBasicBlock *MBB) const
Return true if the specified MBB will be emitted immediately after this block, such that if this bloc...
const uint32_t * getRegMask() const
getRegMask - Returns a bit mask of registers preserved by this RegMask operand.
Special value supplied for machine level alias analysis.
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
static MachineInstr * finishConvertToThreeAddress(MachineInstr *OldMI, MachineInstr *NewMI, LiveVariables *LV)
static int isSimpleMove(const MachineInstr &MI, int &FrameIndex, unsigned Flag)
bool canInsertSelect(const MachineBasicBlock &, ArrayRef< MachineOperand > Cond, unsigned, unsigned, int &, int &, int &) const override
const MachineBasicBlock * getParent() const
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
void getLoadStoreOpcodes(const TargetRegisterClass *RC, unsigned &LoadOpcode, unsigned &StoreOpcode) const
Representation of each machine instruction.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
unsigned getInstSizeInBytes(const MachineInstr &MI) const override
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
LLVM_NODISCARD bool empty() const
unsigned getFusedCompare(unsigned Opcode, SystemZII::FusedCompareType Type, const MachineInstr *MI=nullptr) const
void setReg(unsigned Reg)
Change the register this operand corresponds to.
static MachineOperand CreateImm(int64_t Val)
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
static bool isSimpleBD12Move(const MachineInstr *MI, unsigned Flag)
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
bool hasOneNonDBGUse(unsigned RegNo) const
hasOneNonDBGUse - Return true if there is exactly one non-Debug instruction using the specified regis...
SlotIndexes * getSlotIndexes() const
bool isReg() const
isReg - Tests if this is a MO_Register operand.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
SystemZII::Branch getBranchInfo(const MachineInstr &MI) const
int64_t getOffset() const
For normal values, this is a byte offset added to the base address.
LLVM Value Representation.
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
static bool isImmLL(uint64_t Val)
bool isRxSBGMask(uint64_t Mask, unsigned BitSize, unsigned &Start, unsigned &End) const
bool isMBB() const
isMBB - Tests if this is a MO_MachineBasicBlock operand.
void RemoveOperand(unsigned OpNo)
Erase an operand from an instruction, leaving it with one fewer operand than it started with...
unsigned getRegSizeInBits(const TargetRegisterClass &RC) const
Return the size in bits of a register from class RC.
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned char TargetFlags=0) const
bool hasLoadStoreOnCond2() const
const MachineOperand & getOperand(unsigned i) const
unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
SlotIndex - An opaque wrapper around machine indexes.
LiveRange & getRegUnit(unsigned Unit)
Return the live range for register unit Unit.
unsigned createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
bool empty() const
empty - Check if the array is empty.
unsigned getSize() const
Return the number of bytes in the encoding of this instruction, or zero if the encoding size cannot b...
void tieOperands(unsigned DefIdx, unsigned UseIdx)
Add a tie between the register operands at DefIdx and UseIdx.