15 #define DEBUG_TYPE "cseinfo" 20 "Analysis containing CSE Info",
false,
true)
36 case TargetOpcode::G_ADD:
37 case TargetOpcode::G_AND:
38 case TargetOpcode::G_ASHR:
39 case TargetOpcode::G_LSHR:
40 case TargetOpcode::G_MUL:
41 case TargetOpcode::G_OR:
42 case TargetOpcode::G_SHL:
43 case TargetOpcode::G_SUB:
44 case TargetOpcode::G_XOR:
45 case TargetOpcode::G_UDIV:
46 case TargetOpcode::G_SDIV:
47 case TargetOpcode::G_UREM:
48 case TargetOpcode::G_SREM:
49 case TargetOpcode::G_CONSTANT:
50 case TargetOpcode::G_FCONSTANT:
51 case TargetOpcode::G_ZEXT:
52 case TargetOpcode::G_SEXT:
53 case TargetOpcode::G_ANYEXT:
54 case TargetOpcode::G_UNMERGE_VALUES:
55 case TargetOpcode::G_TRUNC:
62 return Opc == TargetOpcode::G_CONSTANT;
74 bool GISelCSEInfo::isUniqueMachineInstValid(
84 bool Removed = CSEMap.RemoveNode(UMI);
86 assert(Removed &&
"Invalidation called on invalid UMI");
93 auto *Node = CSEMap.FindNodeOrInsertPos(ID, InsertPos);
95 if (!isUniqueMachineInstValid(*Node)) {
96 invalidateUniqueMachineInstr(Node);
100 if (Node->MI->getParent() != MBB)
107 handleRecordedInsts();
111 CSEMap.InsertNode(UMI, InsertPos);
113 MaybeNewNode = CSEMap.GetOrInsertNode(UMI);
114 if (MaybeNewNode != UMI) {
118 assert(InstrMapping.count(UMI->MI) == 0 &&
119 "This instruction should not be in the map");
120 InstrMapping[UMI->MI] = MaybeNewNode;
124 assert(shouldCSE(MI->
getOpcode()) &&
"Trying to CSE an unsupported Node");
129 void GISelCSEInfo::insertInstr(
MachineInstr *MI,
void *InsertPos) {
132 TemporaryInsts.remove(MI);
133 auto *Node = getUniqueInstrForMI(MI);
134 insertNode(Node, InsertPos);
140 handleRecordedInsts();
141 if (
auto *Inst = getNodeIfExists(ID, MBB, InsertPos)) {
142 LLVM_DEBUG(
dbgs() <<
"CSEInfo: Found Instr " << *Inst->MI <<
"\n";);
150 if (OpcodeHitTable.count(Opc))
151 OpcodeHitTable[Opc] += 1;
153 OpcodeHitTable[Opc] = 1;
160 TemporaryInsts.insert(MI);
161 LLVM_DEBUG(
dbgs() <<
"CSEInfo: Recording new MI" << *MI <<
"\n";);
167 auto *UMI = InstrMapping.lookup(MI);
168 LLVM_DEBUG(
dbgs() <<
"CSEInfo: Handling recorded MI" << *MI <<
"\n";);
171 invalidateUniqueMachineInstr(UMI);
172 InstrMapping.erase(MI);
179 insertNode(UMI,
nullptr);
188 if (
auto *UMI = InstrMapping.lookup(MI)) {
189 invalidateUniqueMachineInstr(UMI);
190 InstrMapping.erase(MI);
192 TemporaryInsts.remove(MI);
196 while (!TemporaryInsts.empty()) {
197 auto *MI = TemporaryInsts.pop_back_val();
198 handleRecordedInst(MI);
206 assert(CSEOpt.get() &&
"CSEConfig not set");
207 return CSEOpt->shouldCSEOpc(Opc);
221 for (
auto &MBB : MF) {
236 InstrMapping.clear();
237 UniqueInstrAllocator.Reset();
238 TemporaryInsts.clear();
243 OpcodeHitTable.clear();
249 for (
auto &It : OpcodeHitTable) {
250 dbgs() <<
"CSE Count for Opc " << It.first <<
" : " << It.second <<
"\n";
261 addNodeIDMachineOperand(
Op);
274 uint64_t Val = Ty.getUniqueRAWLLTData();
327 addNodeIDRegNum(Reg);
328 LLT Ty =
MRI.getType(Reg);
330 addNodeIDRegType(Ty);
331 auto *RB =
MRI.getRegBankOrNull(Reg);
333 addNodeIDRegType(RB);
334 auto *RC =
MRI.getRegClassOrNull(Reg);
336 addNodeIDRegType(RC);
338 }
else if (MO.
isImm())
354 if (!AlreadyComputed || Recompute) {
355 Info.setCSEConfig(std::move(CSEOpt));
357 AlreadyComputed =
true;
void changedInstr(MachineInstr &MI) override
This instruction was mutated in some way.
void AddPointer(const void *Ptr)
Add* - Add various data types to Bit data.
This class represents lattice values for constants.
bool runOnMachineFunction(MachineFunction &MF) override
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
unsigned getReg() const
getReg - Returns the register number.
const GISelInstProfileBuilder & addNodeIDImmediate(int64_t Imm) const
The actual analysis pass wrapper.
block Block Frequency true
void setMF(MachineFunction &MF)
iterator_range< mop_iterator > operands()
const GISelInstProfileBuilder & addNodeIDRegNum(unsigned Reg) const
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
static MachineOperand CreateReg(unsigned Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)
const GISelInstProfileBuilder & addNodeIDFlag(unsigned Flag) const
void changingInstr(MachineInstr &MI) override
This instruction is about to be mutated in some way.
amdgpu aa AMDGPU Address space based Alias Analysis Wrapper
GISelCSEInfo & get(std::unique_ptr< CSEConfig > CSEOpt, bool ReCompute=false)
Takes a CSEConfig object that defines what opcodes get CSEd.
const GISelInstProfileBuilder & addNodeIDOpcode(unsigned Opc) const
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - This function should be overriden by passes that need analysis information to do t...
const ConstantFP * getFPImm() const
separate const offset from Split GEPs to a variadic base and a constant offset for better CSE
void AddInteger(signed I)
virtual bool shouldCSEOpc(unsigned Opc) override
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
const GISelInstProfileBuilder & addNodeIDRegType(const LLT &Ty) const
void erasingInstr(MachineInstr &MI) override
An instruction is about to be erased.
bool isFPImm() const
isFPImm - Tests if this is a MO_FPImmediate operand.
bool shouldCSE(unsigned Opc) const
void handleRemoveInst(MachineInstr *MI)
Remove this inst from the CSE map.
Analysis containing CSE Info
Flag
These should be considered private to the implementation of the MCInstrDesc class.
FoldingSetNodeID - This class is used to gather all the unique data bits of a node.
INITIALIZE_PASS_BEGIN(GISelCSEAnalysisWrapperPass, DEBUG_TYPE, "Analysis containing CSE Info", false, true) INITIALIZE_PASS_END(GISelCSEAnalysisWrapperPass
unsigned const MachineRegisterInfo * MRI
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
bool isCImm() const
isCImm - Test if this is a MO_CImmediate operand.
const GISelInstProfileBuilder & addNodeID(const MachineInstr *MI) const
Represent the analysis usage information of a pass.
void countOpcodeHit(unsigned Opc)
INITIALIZE_PASS_END(RegBankSelect, DEBUG_TYPE, "Assign register bank of generic virtual registers", false, false) RegBankSelect
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
void handleRecordedInst(MachineInstr *MI)
Use this callback to inform CSE about a newly fully created instruction.
void recordNewInstruction(MachineInstr *MI)
Records a newly created inst in a list and lazily insert it to the CSEMap.
MachineOperand class - Representation of each machine instruction operand.
void analyze(MachineFunction &MF)
This class implements the register bank concept.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
void setPreservesAll()
Set by analyses that do not transform their input at all.
const MachineBasicBlock * getParent() const
Representation of each machine instruction.
block Block Frequency Analysis
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
const GISelInstProfileBuilder & addNodeIDMBB(const MachineBasicBlock *MBB) const
virtual bool shouldCSEOpc(unsigned Opc)
bool isReg() const
isReg - Tests if this is a MO_Register operand.
uint16_t getFlags() const
Return the MI flags bitvector.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool isPreISelGenericOpcode(unsigned Opcode)
Check whether the given Opcode is a generic opcode that is not supposed to appear after ISel...
const GISelInstProfileBuilder & addNodeIDMachineOperand(const MachineOperand &MO) const
void createdInstr(MachineInstr &MI) override
An instruction was created and inserted into the function.
A class that wraps MachineInstrs and derives from FoldingSetNode in order to be uniqued in a CSEMap...
void handleRecordedInsts()
Use this callback to insert all the recorded instructions.
const ConstantInt * getCImm() const
unsigned getPredicate() const