88 : MF(MF), SM(&SM), IRSlots(IRSlots), Names2RegClasses(Names2RegClasses),
89 Names2RegBanks(Names2RegBanks) {
93 auto I =
VRegInfos.insert(std::make_pair(Num,
nullptr));
98 I.first->second =
Info;
100 return *
I.first->second;
104 assert(RegName !=
"" &&
"Expected named reg.");
110 I.first->second =
Info;
112 return *
I.first->second;
119 struct ParsedMachineOperand {
127 : Operand(Operand), Begin(Begin), End(End), TiedDefIdx(TiedDefIdx) {
130 "Only used register operands can be tied");
167 void lex(
unsigned SkipChar = 0);
181 bool parseBasicBlocks();
184 bool parseStandaloneNamedRegister(
unsigned &
Reg);
186 bool parseStandaloneRegister(
unsigned &Reg);
187 bool parseStandaloneStackObject(
int &FI);
188 bool parseStandaloneMDNode(
MDNode *&Node);
197 bool parseNamedRegister(
unsigned &Reg);
198 bool parseVirtualRegister(
VRegInfo *&Info);
199 bool parseNamedVirtualRegister(
VRegInfo *&Info);
201 bool parseRegisterFlag(
unsigned &Flags);
202 bool parseRegisterClassOrBank(VRegInfo &RegInfo);
203 bool parseSubRegisterIndex(
unsigned &
SubReg);
204 bool parseRegisterTiedDefIndex(
unsigned &TiedDefIdx);
216 bool parseStackFrameIndex(
int &FI);
218 bool parseFixedStackFrameIndex(
int &FI);
228 bool parseDIExpression(
MDNode *&Expr);
229 bool parseDILocation(
MDNode *&Expr);
231 bool parseCFIOffset(
int &
Offset);
232 bool parseCFIRegister(
unsigned &Reg);
233 bool parseCFIEscapeValues(std::string& Values);
246 bool parseOffset(int64_t &Offset);
247 bool parseAlignment(
unsigned &Alignment);
248 bool parseAddrspace(
unsigned &Addrspace);
250 bool parseIRValue(
const Value *&V);
263 bool getUnsigned(
unsigned &Result);
268 bool getUint64(uint64_t &Result);
274 bool getHexUint(
APInt &Result);
284 void initNames2InstrOpCodes();
288 bool parseInstrName(
StringRef InstrName,
unsigned &OpCode);
290 bool parseInstruction(
unsigned &OpCode,
unsigned &Flags);
298 void initNames2Regs();
302 bool getRegisterByName(
StringRef RegName,
unsigned &Reg);
304 void initNames2RegMasks();
311 void initNames2SubRegIndices();
321 const Value *getIRValue(
unsigned Slot);
323 void initNames2TargetIndices();
330 void initNames2DirectTargetFlags();
338 void initNames2BitmaskTargetFlags();
344 bool getBitmaskTargetFlag(
StringRef Name,
unsigned &Flag);
346 void initNames2MMOTargetFlags();
359 bool parseStringConstant(std::string &Result);
366 :
MF(PFS.
MF),
Error(Error),
Source(Source), CurrentSource(Source), PFS(PFS)
369 void MIParser::lex(
unsigned SkipChar) {
371 CurrentSource.data() + SkipChar, Token,
407 return "<unknown token>";
412 if (Token.isNot(TokenKind))
419 if (Token.isNot(TokenKind))
425 bool MIParser::parseBasicBlockDefinition(
431 auto Loc = Token.location();
432 auto Name = Token.stringValue();
434 bool HasAddressTaken =
false;
435 bool IsLandingPad =
false;
436 unsigned Alignment = 0;
441 switch (Token.kind()) {
443 HasAddressTaken =
true;
451 if (parseAlignment(Alignment))
471 BB = dyn_cast_or_null<BasicBlock>(
475 "' is not defined in the function '" +
480 bool WasInserted = MBBSlots.
insert(std::make_pair(ID, MBB)).second;
482 return error(Loc,
Twine(
"redefinition of machine basic block with id #") +
485 MBB->setAlignment(Alignment);
487 MBB->setHasAddressTaken();
488 MBB->setIsEHPad(IsLandingPad);
492 bool MIParser::parseBasicBlockDefinitions(
498 if (Token.isErrorOrEOF())
499 return Token.isError();
501 return error(
"expected a basic block definition before instructions");
502 unsigned BraceDepth = 0;
504 if (parseBasicBlockDefinition(MBBSlots))
506 bool IsAfterNewline =
false;
510 Token.isErrorOrEOF())
513 return error(
"basic block definition should be located at the start of " 516 IsAfterNewline =
true;
519 IsAfterNewline =
false;
524 return error(
"extraneous closing brace ('}')");
530 if (!Token.isError() && BraceDepth)
531 return error(
"expected '}'");
532 }
while (!Token.isErrorOrEOF());
533 return Token.isError();
541 if (Token.isNewlineOrEOF())
545 return error(
"expected a named register");
547 if (parseNamedRegister(Reg))
555 return error(
"expected a lane mask");
557 "Use correct get-function for lane mask");
560 return error(
"invalid lane mask value");
574 if (Token.isNewlineOrEOF())
578 return error(
"expected a machine basic block reference");
587 return error(
"expected an integer literal after '('");
588 if (getUnsigned(Weight))
621 bool ExplicitSuccessors =
false;
624 if (parseBasicBlockSuccessors(MBB))
626 ExplicitSuccessors =
true;
628 if (parseBasicBlockLiveins(MBB))
634 if (!Token.isNewlineOrEOF())
635 return error(
"expected line break at the end of a list");
640 bool IsInBundle =
false;
664 return error(
"nested instruction bundles are not allowed");
673 assert(Token.isNewlineOrEOF() &&
"MI is not fully parsed");
678 if (!ExplicitSuccessors) {
686 AddFalthroughFrom = &MBB;
695 bool MIParser::parseBasicBlocks() {
700 if (Token.isErrorOrEOF())
701 return Token.isError();
710 if (AddFalthroughFrom) {
711 if (!AddFalthroughFrom->isSuccessor(MBB))
713 AddFalthroughFrom->normalizeSuccProbs();
714 AddFalthroughFrom =
nullptr;
716 if (parseBasicBlock(*MBB, AddFalthroughFrom))
729 while (Token.isRegister() || Token.isRegisterFlag()) {
730 auto Loc = Token.location();
732 if (parseRegisterOperand(MO, TiedDefIdx,
true))
735 ParsedMachineOperand(MO, Loc, Token.location(), TiedDefIdx));
743 unsigned OpCode, Flags = 0;
744 if (Token.isError() || parseInstruction(OpCode, Flags))
752 auto Loc = Token.location();
754 if (parseMachineOperandAndTargetFlags(MO, TiedDefIdx))
756 if (OpCode == TargetOpcode::DBG_VALUE && MO.
isReg())
759 ParsedMachineOperand(MO, Loc, Token.location(), TiedDefIdx));
764 return error(
"expected ',' before the next machine operand");
770 if (parsePreOrPostInstrSymbol(PreInstrSymbol))
772 MCSymbol *PostInstrSymbol =
nullptr;
774 if (parsePreOrPostInstrSymbol(PostInstrSymbol))
785 if (parseDILocation(Node))
788 return error(
"expected a metadata node after 'debug-location'");
789 if (!isa<DILocation>(Node))
790 return error(
"referenced metadata is not a DILocation");
798 while (!Token.isNewlineOrEOF()) {
800 if (parseMachineMemoryOperand(MemOp))
803 if (Token.isNewlineOrEOF())
806 return error(
"expected ',' before the next machine memory operand");
812 if (!MCID.isVariadic()) {
814 if (verifyImplicitOperands(Operands, MCID))
821 for (
const auto &Operand : Operands)
823 if (assignRegisterTies(*MI, Operands))
829 if (!MemOperands.
empty())
837 return error(
"expected a machine basic block reference");
843 "expected end of string after the machine basic block reference");
847 bool MIParser::parseStandaloneNamedRegister(
unsigned &
Reg) {
850 return error(
"expected a named register");
851 if (parseNamedRegister(Reg))
855 return error(
"expected end of string after the register reference");
859 bool MIParser::parseStandaloneVirtualRegister(
VRegInfo *&
Info) {
862 return error(
"expected a virtual register");
863 if (parseVirtualRegister(Info))
867 return error(
"expected end of string after the register reference");
871 bool MIParser::parseStandaloneRegister(
unsigned &Reg) {
875 return error(
"expected either a named or virtual register");
878 if (parseRegister(Reg, Info))
883 return error(
"expected end of string after the register reference");
887 bool MIParser::parseStandaloneStackObject(
int &FI) {
890 return error(
"expected a stack object");
891 if (parseStackFrameIndex(FI))
894 return error(
"expected end of string after the stack object reference");
898 bool MIParser::parseStandaloneMDNode(
MDNode *&Node) {
904 if (parseDIExpression(Node))
907 if (parseDILocation(Node))
910 return error(
"expected a metadata node");
912 return error(
"expected end of string after the metadata node");
918 return MO.
isDef() ?
"implicit-def" :
"implicit";
930 for (
const auto &
I : Operands) {
956 assert(
TRI &&
"Expected target register info");
957 for (
const auto &
I : ImplicitOperands) {
960 return error(Operands.
empty() ? Token.location() : Operands.
back().End,
961 Twine(
"missing implicit register operand '") +
968 bool MIParser::parseInstruction(
unsigned &OpCode,
unsigned &Flags) {
1011 return error(
"expected a machine instruction");
1012 StringRef InstrName = Token.stringValue();
1013 if (parseInstrName(InstrName, OpCode))
1014 return error(
Twine(
"unknown machine instruction name '") + InstrName +
"'");
1019 bool MIParser::parseNamedRegister(
unsigned &Reg) {
1022 if (getRegisterByName(Name, Reg))
1023 return error(
Twine(
"unknown register name '") + Name +
"'");
1027 bool MIParser::parseNamedVirtualRegister(
VRegInfo *&Info) {
1036 bool MIParser::parseVirtualRegister(
VRegInfo *&Info) {
1038 return parseNamedVirtualRegister(Info);
1041 if (getUnsigned(ID))
1047 bool MIParser::parseRegister(
unsigned &Reg,
VRegInfo *&Info) {
1048 switch (Token.kind()) {
1053 return parseNamedRegister(Reg);
1056 if (parseVirtualRegister(Info))
1066 bool MIParser::parseRegisterClassOrBank(
VRegInfo &RegInfo) {
1068 return error(
"expected '_', register class, or register bank name");
1078 switch (RegInfo.
Kind) {
1084 return error(Loc,
Twine(
"conflicting register classes, previously: ") +
1093 return error(Loc,
"register class specification on generic register");
1103 return error(Loc,
"expected '_', register class, or register bank name");
1104 RegBank = RBNameI->getValue();
1109 switch (RegInfo.
Kind) {
1115 return error(Loc,
"conflicting generic register banks");
1121 return error(Loc,
"register bank specification on normal register");
1126 bool MIParser::parseRegisterFlag(
unsigned &Flags) {
1127 const unsigned OldFlags = Flags;
1128 switch (Token.kind()) {
1162 if (OldFlags == Flags)
1165 return error(
"duplicate '" + Token.stringValue() +
"' register flag");
1170 bool MIParser::parseSubRegisterIndex(
unsigned &
SubReg) {
1174 return error(
"expected a subregister index after '.'");
1175 auto Name = Token.stringValue();
1176 SubReg = getSubRegIndex(
Name);
1178 return error(
Twine(
"use of unknown subregister index '") +
Name +
"'");
1183 bool MIParser::parseRegisterTiedDefIndex(
unsigned &TiedDefIdx) {
1187 return error(
"expected an integer literal after 'tied-def'");
1188 if (getUnsigned(TiedDefIdx))
1199 for (
unsigned I = 0,
E = Operands.
size();
I !=
E; ++
I) {
1200 if (!Operands[
I].TiedDefIdx)
1204 unsigned DefIdx = Operands[
I].TiedDefIdx.getValue();
1206 return error(Operands[
I].Begin,
1207 Twine(
"use of invalid tied-def operand index '" +
1208 Twine(DefIdx) +
"'; instruction has only ") +
1210 const auto &DefOperand = Operands[DefIdx].Operand;
1211 if (!DefOperand.isReg() || !DefOperand.isDef())
1213 return error(Operands[
I].Begin,
1214 Twine(
"use of invalid tied-def operand index '") +
1215 Twine(DefIdx) +
"'; the operand #" +
Twine(DefIdx) +
1216 " isn't a defined register");
1218 for (
const auto &TiedPair : TiedRegisterPairs) {
1219 if (TiedPair.first == DefIdx)
1220 return error(Operands[
I].Begin,
1221 Twine(
"the tied-def operand #") +
Twine(DefIdx) +
1222 " is already tied with another register operand");
1224 TiedRegisterPairs.push_back(std::make_pair(DefIdx,
I));
1228 for (
const auto &TiedPair : TiedRegisterPairs)
1237 while (Token.isRegisterFlag()) {
1238 if (parseRegisterFlag(Flags))
1241 if (!Token.isRegister())
1242 return error(
"expected a register after register flags");
1245 if (parseRegister(Reg, RegInfo))
1248 unsigned SubReg = 0;
1250 if (parseSubRegisterIndex(SubReg))
1253 return error(
"subregister index expects a virtual register");
1257 return error(
"register class specification expects a virtual register");
1259 if (parseRegisterClassOrBank(*RegInfo))
1266 if (!parseRegisterTiedDefIndex(Idx))
1271 if (parseLowLevelType(Token.location(), Ty))
1272 return error(
"expected tied-def or low-level type after '('");
1278 return error(
"inconsistent type for generic virtual register");
1286 return error(
"unexpected type on physical register");
1289 if (parseLowLevelType(Token.location(), Ty))
1296 return error(
"inconsistent type for generic virtual register");
1305 return error(
"generic virtual registers must have a type");
1318 const APSInt &Int = Token.integerValue();
1319 if (Int.getMinSignedBits() > 64)
1320 return error(
"integer literal is too large to be an immediate operand");
1328 auto Source = StringValue.
str();
1338 if (parseIRConstant(Loc,
StringRef(Loc, Token.range().end() - Loc), C))
1345 if (Token.range().front() ==
's' || Token.range().front() ==
'p') {
1348 return error(
"expected integers after 's'/'p' type character");
1351 if (Token.range().front() ==
's') {
1355 }
else if (Token.range().front() ==
'p') {
1357 unsigned AS =
APSInt(Token.range().drop_front()).getZExtValue();
1366 "expected sN, pA, <M x sN>, or <M x pA> for GlobalISel type");
1370 return error(Loc,
"expected <M x sN> or <M x pA> for vector type");
1371 uint64_t NumElements = Token.integerValue().getZExtValue();
1375 return error(Loc,
"expected <M x sN> or <M x pA> for vector type");
1378 if (Token.range().front() !=
's' && Token.range().front() !=
'p')
1379 return error(Loc,
"expected <M x sN> or <M x pA> for vector type");
1382 return error(
"expected integers after 's'/'p' type character");
1384 if (Token.range().front() ==
's')
1386 else if (Token.range().front() ==
'p') {
1388 unsigned AS =
APSInt(Token.range().drop_front()).getZExtValue();
1391 return error(Loc,
"expected <M x sN> or <M x pA> for vector type");
1395 return error(Loc,
"expected <M x sN> or <M x pA> for vector type");
1402 bool MIParser::parseTypedImmediateOperand(
MachineOperand &Dest) {
1405 if (TypeStr.front() !=
'i' && TypeStr.front() !=
's' &&
1406 TypeStr.front() !=
'p')
1408 "a typed immediate operand should start with one of 'i', 's', or 'p'");
1411 return error(
"expected integers after 'i'/'s'/'p' type character");
1413 auto Loc = Token.location();
1417 !(Token.range() ==
"true" || Token.range() ==
"false"))
1418 return error(
"expected an integer literal");
1421 if (parseIRConstant(Loc, C))
1428 auto Loc = Token.location();
1432 return error(
"expected a floating point literal");
1434 if (parseIRConstant(Loc, C))
1440 bool MIParser::getUnsigned(
unsigned &Result) {
1441 if (Token.hasIntegerValue()) {
1443 uint64_t Val64 = Token.integerValue().getLimitedValue(Limit);
1445 return error(
"expected 32-bit integer (too large)");
1454 return error(
"expected 32-bit integer (too large)");
1465 if (getUnsigned(Number))
1467 auto MBBInfo = PFS.
MBBSlots.find(Number);
1469 return error(
Twine(
"use of undefined machine basic block #") +
1471 MBB = MBBInfo->second;
1474 if (!Token.stringValue().empty() && Token.stringValue() != MBB->
getName())
1475 return error(
Twine(
"the name of machine basic block #") +
Twine(Number) +
1476 " isn't '" + Token.stringValue() +
"'");
1489 bool MIParser::parseStackFrameIndex(
int &FI) {
1492 if (getUnsigned(ID))
1496 return error(
Twine(
"use of undefined stack object '%stack.") +
Twine(ID) +
1499 if (
const auto *Alloca =
1501 Name = Alloca->getName();
1502 if (!Token.stringValue().empty() && Token.stringValue() !=
Name)
1503 return error(
Twine(
"the name of the stack object '%stack.") +
Twine(ID) +
1504 "' isn't '" + Token.stringValue() +
"'");
1506 FI = ObjectInfo->second;
1512 if (parseStackFrameIndex(FI))
1518 bool MIParser::parseFixedStackFrameIndex(
int &FI) {
1521 if (getUnsigned(ID))
1525 return error(
Twine(
"use of undefined fixed stack object '%fixed-stack.") +
1528 FI = ObjectInfo->second;
1532 bool MIParser::parseFixedStackObjectOperand(
MachineOperand &Dest) {
1534 if (parseFixedStackFrameIndex(FI))
1540 bool MIParser::parseGlobalValue(
GlobalValue *&GV) {
1541 switch (Token.kind()) {
1546 return error(
Twine(
"use of undefined global value '") + Token.range() +
1552 if (getUnsigned(GVIdx))
1555 return error(
Twine(
"use of undefined global value '@") +
Twine(GVIdx) +
1568 if (parseGlobalValue(GV))
1572 if (parseOperandsOffset(Dest))
1577 bool MIParser::parseConstantPoolIndexOperand(
MachineOperand &Dest) {
1580 if (getUnsigned(ID))
1584 return error(
"use of undefined constant '%const." +
Twine(ID) +
"'");
1587 if (parseOperandsOffset(Dest))
1592 bool MIParser::parseJumpTableIndexOperand(
MachineOperand &Dest) {
1595 if (getUnsigned(ID))
1599 return error(
"use of undefined jump table '%jump-table." +
Twine(ID) +
"'");
1605 bool MIParser::parseExternalSymbolOperand(
MachineOperand &Dest) {
1610 if (parseOperandsOffset(Dest))
1620 if (parseOperandsOffset(Dest))
1625 bool MIParser::parseSubRegisterIndexOperand(
MachineOperand &Dest) {
1628 unsigned SubRegIndex = getSubRegIndex(Token.stringValue());
1629 if (SubRegIndex == 0)
1630 return error(
Twine(
"unknown subregister index '") + Name +
"'");
1639 auto Loc = Token.location();
1642 return error(
"expected metadata id after '!'");
1644 if (getUnsigned(ID))
1648 return error(Loc,
"use of undefined metadata '!" +
Twine(ID) +
"'");
1650 Node = NodeInfo->second.
get();
1654 bool MIParser::parseDIExpression(
MDNode *&Expr) {
1672 return error(
Twine(
"invalid DWARF op '") + Token.stringValue() +
"'");
1676 Token.integerValue().isSigned())
1677 return error(
"expected unsigned integer");
1679 auto &U = Token.integerValue();
1695 bool MIParser::parseDILocation(
MDNode *&Loc) {
1699 bool HaveLine =
false;
1701 unsigned Column = 0;
1703 MDNode *InlinedAt =
nullptr;
1704 bool ImplicitCode =
false;
1712 if (Token.stringValue() ==
"line") {
1717 Token.integerValue().isSigned())
1718 return error(
"expected unsigned integer");
1719 Line = Token.integerValue().getZExtValue();
1724 if (Token.stringValue() ==
"column") {
1729 Token.integerValue().isSigned())
1730 return error(
"expected unsigned integer");
1731 Column = Token.integerValue().getZExtValue();
1735 if (Token.stringValue() ==
"scope") {
1740 return error(
"expected metadata node");
1741 if (!isa<DIScope>(Scope))
1742 return error(
"expected DIScope node");
1745 if (Token.stringValue() ==
"inlinedAt") {
1753 if (parseDILocation(InlinedAt))
1756 return error(
"expected metadata node");
1757 if (!isa<DILocation>(InlinedAt))
1758 return error(
"expected DILocation node");
1761 if (Token.stringValue() ==
"isImplicitCode") {
1766 return error(
"expected true/false");
1770 if (Token.stringValue() ==
"true")
1771 ImplicitCode =
true;
1772 else if (Token.stringValue() ==
"false")
1773 ImplicitCode =
false;
1775 return error(
"expected true/false");
1780 return error(
Twine(
"invalid DILocation argument '") +
1781 Token.stringValue() +
"'");
1789 return error(
"DILocation requires line number");
1791 return error(
"DILocation requires a scope");
1794 InlinedAt, ImplicitCode);
1804 if (parseDIExpression(Node))
1811 bool MIParser::parseCFIOffset(
int &
Offset) {
1813 return error(
"expected a cfi offset");
1814 if (Token.integerValue().getMinSignedBits() > 32)
1815 return error(
"expected a 32 bit integer (the cfi offset is too large)");
1816 Offset = (int)Token.integerValue().getExtValue();
1821 bool MIParser::parseCFIRegister(
unsigned &Reg) {
1823 return error(
"expected a cfi register");
1825 if (parseNamedRegister(LLVMReg))
1828 assert(
TRI &&
"Expected target register info");
1829 int DwarfReg =
TRI->getDwarfRegNum(LLVMReg,
true);
1831 return error(
"invalid DWARF register");
1837 bool MIParser::parseCFIEscapeValues(std::string &Values) {
1840 return error(
"expected a hexadecimal literal");
1842 if (getUnsigned(Value))
1844 if (Value > UINT8_MAX)
1845 return error(
"expected a 8-bit integer (too large)");
1846 Values.push_back(static_cast<uint8_t>(Value));
1853 auto Kind = Token.kind();
1860 if (parseCFIRegister(Reg))
1866 parseCFIOffset(Offset))
1873 parseCFIOffset(Offset))
1879 if (parseCFIRegister(Reg))
1885 if (parseCFIOffset(Offset))
1892 if (parseCFIOffset(Offset))
1899 parseCFIOffset(Offset))
1909 if (parseCFIRegister(Reg))
1917 if (parseCFIRegister(Reg))
1924 parseCFIRegister(Reg2))
1939 if (parseCFIEscapeValues(Values))
1953 switch (Token.kind()) {
1955 BB = dyn_cast_or_null<BasicBlock>(
1958 return error(
Twine(
"use of undefined IR block '") + Token.range() +
"'");
1962 unsigned SlotNumber = 0;
1963 if (getUnsigned(SlotNumber))
1965 BB =
const_cast<BasicBlock *
>(getIRBlock(SlotNumber, F));
1967 return error(
Twine(
"use of undefined IR block '%ir-block.") +
1968 Twine(SlotNumber) +
"'");
1984 return error(
"expected a global value");
1986 if (parseGlobalValue(GV))
1990 return error(
"expected an IR function reference");
1996 return error(
"expected an IR block reference");
1997 if (parseIRBlock(BB, *F))
2003 if (parseOperandsOffset(Dest))
2012 return error(
"expected syntax intrinsic(@llvm.whatever)");
2015 return error(
"expected syntax intrinsic(@llvm.whatever)");
2017 std::string
Name = Token.stringValue();
2021 return error(
"expected ')' to terminate intrinsic name");
2031 return error(
"unknown intrinsic name");
2043 return error(
"expected syntax intpred(whatever) or floatpred(whatever");
2046 return error(
"whatever");
2069 return error(
"invalid floating-point predicate");
2084 return error(
"invalid integer predicate");
2090 return error(
"predicate should be terminated by ')'.");
2101 return error(
"expected the name of the target index");
2103 if (getTargetIndex(Token.stringValue(),
Index))
2104 return error(
"use of undefined target index '" + Token.stringValue() +
"'");
2109 if (parseOperandsOffset(Dest))
2114 bool MIParser::parseCustomRegisterMaskOperand(
MachineOperand &Dest) {
2115 assert(Token.stringValue() ==
"CustomRegMask" &&
"Expected a custom RegMask");
2123 return error(
"expected a named register");
2125 if (parseNamedRegister(Reg))
2128 Mask[Reg / 32] |= 1U << (Reg % 32);
2141 bool MIParser::parseLiveoutRegisterMaskOperand(
MachineOperand &Dest) {
2149 return error(
"expected a named register");
2151 if (parseNamedRegister(Reg))
2154 Mask[Reg / 32] |= 1U << (Reg % 32);
2168 switch (Token.kind()) {
2183 return parseRegisterOperand(Dest, TiedDefIdx);
2185 return parseImmediateOperand(Dest);
2192 return parseFPImmediateOperand(Dest);
2194 return parseMBBOperand(Dest);
2196 return parseStackObjectOperand(Dest);
2198 return parseFixedStackObjectOperand(Dest);
2201 return parseGlobalAddressOperand(Dest);
2203 return parseConstantPoolIndexOperand(Dest);
2205 return parseJumpTableIndexOperand(Dest);
2207 return parseExternalSymbolOperand(Dest);
2209 return parseMCSymbolOperand(Dest);
2211 return parseSubRegisterIndexOperand(Dest);
2214 return parseMetadataOperand(Dest);
2230 return parseCFIOperand(Dest);
2232 return parseBlockAddressOperand(Dest);
2234 return parseIntrinsicOperand(Dest);
2236 return parseTargetIndexOperand(Dest);
2238 return parseLiveoutRegisterMaskOperand(Dest);
2241 return parsePredicateOperand(Dest);
2245 if (
const auto *RegMask = getRegMask(Token.stringValue())) {
2249 }
else if (Token.stringValue() ==
"CustomRegMask") {
2250 return parseCustomRegisterMaskOperand(Dest);
2252 return parseTypedImmediateOperand(Dest);
2255 return error(
"expected a machine operand");
2260 bool MIParser::parseMachineOperandAndTargetFlags(
2263 bool HasTargetFlags =
false;
2265 HasTargetFlags =
true;
2270 return error(
"expected the name of the target flag");
2271 if (getDirectTargetFlag(Token.stringValue(), TF)) {
2272 if (getBitmaskTargetFlag(Token.stringValue(), TF))
2273 return error(
"use of undefined target flag '" + Token.stringValue() +
2280 return error(
"expected the name of the target flag");
2281 unsigned BitFlag = 0;
2282 if (getBitmaskTargetFlag(Token.stringValue(), BitFlag))
2283 return error(
"use of undefined target flag '" + Token.stringValue() +
2292 auto Loc = Token.location();
2293 if (parseMachineOperand(Dest, TiedDefIdx))
2295 if (!HasTargetFlags)
2298 return error(Loc,
"register operands can't have target flags");
2303 bool MIParser::parseOffset(int64_t &
Offset) {
2310 return error(
"expected an integer literal after '" + Sign +
"'");
2311 if (Token.integerValue().getMinSignedBits() > 64)
2312 return error(
"expected 64-bit integer (too large)");
2313 Offset = Token.integerValue().getExtValue();
2320 bool MIParser::parseAlignment(
unsigned &Alignment) {
2324 return error(
"expected an integer literal after 'align'");
2325 if (getUnsigned(Alignment))
2331 bool MIParser::parseAddrspace(
unsigned &Addrspace) {
2335 return error(
"expected an integer literal after 'addrspace'");
2336 if (getUnsigned(Addrspace))
2344 if (parseOffset(Offset))
2350 bool MIParser::parseIRValue(
const Value *&V) {
2351 switch (Token.kind()) {
2357 unsigned SlotNumber = 0;
2358 if (getUnsigned(SlotNumber))
2360 V = getIRValue(SlotNumber);
2366 if (parseGlobalValue(GV))
2373 if (parseIRConstant(Token.location(), Token.stringValue(),
C))
2382 return error(
Twine(
"use of undefined IR value '") + Token.range() +
"'");
2386 bool MIParser::getUint64(uint64_t &Result) {
2387 if (Token.hasIntegerValue()) {
2388 if (Token.integerValue().getActiveBits() > 64)
2389 return error(
"expected 64-bit integer (too large)");
2390 Result = Token.integerValue().getZExtValue();
2398 return error(
"expected 64-bit integer (too large)");
2405 bool MIParser::getHexUint(
APInt &Result) {
2408 assert(S[0] ==
'0' && tolower(S[1]) ==
'x');
2410 if (!isxdigit(S[2]))
2417 unsigned NumBits = (A == 0) ? 32 : A.getActiveBits();
2423 const auto OldFlags = Flags;
2424 switch (Token.kind()) {
2439 if (getMMOTargetFlag(Token.stringValue(), TF))
2440 return error(
"use of undefined target MMO flag '" + Token.stringValue() +
2448 if (OldFlags == Flags)
2451 return error(
"duplicate '" + Token.stringValue() +
"' memory operand flag");
2457 switch (Token.kind()) {
2472 if (parseFixedStackFrameIndex(FI))
2480 if (parseStackFrameIndex(FI))
2488 switch (Token.kind()) {
2492 if (parseGlobalValue(GV))
2503 "expected a global value or an external symbol after 'call-entry'");
2519 if (parseMemoryPseudoSourceValue(PSV))
2522 if (parseOffset(Offset))
2531 return error(
"expected an IR value reference");
2532 const Value *V =
nullptr;
2533 if (parseIRValue(V))
2536 return error(
"expected a pointer IR value");
2539 if (parseOffset(Offset))
2551 return error(
"expected '(' in syncscope");
2554 if (parseStringConstant(SSN))
2559 return error(
"expected ')' in syncscope");
2565 bool MIParser::parseOptionalAtomicOrdering(
AtomicOrdering &Order) {
2584 return error(
"expected an atomic scope, ordering or a size specification");
2591 while (Token.isMemoryOperandFlag()) {
2592 if (parseMemoryOperandFlag(Flags))
2596 (Token.stringValue() !=
"load" && Token.stringValue() !=
"store"))
2597 return error(
"expected 'load' or 'store' memory operation");
2598 if (Token.stringValue() ==
"load")
2617 if (parseOptionalAtomicOrdering(Order))
2620 if (parseOptionalAtomicOrdering(FailureOrder))
2625 return error(
"expected the size integer literal or 'unknown-size' after " 2626 "memory operation");
2629 if (getUint64(Size))
2643 if (Token.stringValue() !=
Word)
2644 return error(
Twine(
"expected '") + Word +
"'");
2647 if (parseMachinePointerInfo(Ptr))
2654 switch (Token.kind()) {
2656 if (parseAlignment(BaseAlignment))
2685 return error(
"expected 'align' or '!tbaa' or '!alias.scope' or " 2686 "'!noalias' or '!range'");
2692 SSID, Order, FailureOrder);
2699 "Invalid token for a pre- post-instruction symbol!");
2702 return error(
"expected a symbol after 'pre-instr-symbol'");
2703 Symbol = getOrCreateMCSymbol(Token.stringValue());
2709 return error(
"expected ',' before the next machine operand");
2714 void MIParser::initNames2InstrOpCodes() {
2715 if (!Names2InstrOpCodes.empty())
2718 assert(
TII &&
"Expected target instruction info");
2719 for (
unsigned I = 0,
E =
TII->getNumOpcodes();
I <
E; ++
I)
2720 Names2InstrOpCodes.insert(std::make_pair(
StringRef(
TII->getName(
I)),
I));
2723 bool MIParser::parseInstrName(
StringRef InstrName,
unsigned &OpCode) {
2724 initNames2InstrOpCodes();
2725 auto InstrInfo = Names2InstrOpCodes.find(InstrName);
2726 if (InstrInfo == Names2InstrOpCodes.end())
2728 OpCode = InstrInfo->getValue();
2732 void MIParser::initNames2Regs() {
2733 if (!Names2Regs.empty())
2736 Names2Regs.insert(std::make_pair(
"noreg", 0));
2738 assert(
TRI &&
"Expected target register info");
2739 for (
unsigned I = 0,
E =
TRI->getNumRegs();
I <
E; ++
I) {
2741 Names2Regs.insert(std::make_pair(
StringRef(
TRI->getName(
I)).lower(),
I))
2744 assert(WasInserted &&
"Expected registers to be unique case-insensitively");
2748 bool MIParser::getRegisterByName(
StringRef RegName,
unsigned &Reg) {
2750 auto RegInfo = Names2Regs.find(RegName);
2751 if (RegInfo == Names2Regs.end())
2753 Reg = RegInfo->getValue();
2757 void MIParser::initNames2RegMasks() {
2758 if (!Names2RegMasks.empty())
2761 assert(
TRI &&
"Expected target register info");
2765 for (
size_t I = 0,
E = RegMasks.
size();
I <
E; ++
I)
2766 Names2RegMasks.insert(
2767 std::make_pair(
StringRef(RegMaskNames[
I]).lower(), RegMasks[I]));
2771 initNames2RegMasks();
2772 auto RegMaskInfo = Names2RegMasks.find(Identifier);
2773 if (RegMaskInfo == Names2RegMasks.end())
2775 return RegMaskInfo->getValue();
2778 void MIParser::initNames2SubRegIndices() {
2779 if (!Names2SubRegIndices.empty())
2783 Names2SubRegIndices.insert(
2788 initNames2SubRegIndices();
2789 auto SubRegInfo = Names2SubRegIndices.find(Name);
2790 if (SubRegInfo == Names2SubRegIndices.end())
2792 return SubRegInfo->getValue();
2800 for (
auto &BB : F) {
2803 int Slot = MST.getLocalSlot(&BB);
2806 Slots2BasicBlocks.
insert(std::make_pair(
unsigned(Slot), &BB));
2813 auto BlockInfo = Slots2BasicBlocks.
find(Slot);
2814 if (BlockInfo == Slots2BasicBlocks.
end())
2816 return BlockInfo->second;
2819 const BasicBlock *MIParser::getIRBlock(
unsigned Slot) {
2820 if (Slots2BasicBlocks.empty())
2827 return getIRBlock(Slot);
2838 Slots2Values.
insert(std::make_pair(
unsigned(Slot), V));
2846 for (
const auto &
Arg : F.
args())
2848 for (
const auto &BB : F) {
2850 for (
const auto &
I : BB)
2855 const Value *MIParser::getIRValue(
unsigned Slot) {
2856 if (Slots2Values.empty())
2858 auto ValueInfo = Slots2Values.find(Slot);
2864 void MIParser::initNames2TargetIndices() {
2865 if (!Names2TargetIndices.empty())
2868 assert(
TII &&
"Expected target instruction info");
2869 auto Indices =
TII->getSerializableTargetIndices();
2870 for (
const auto &
I : Indices)
2871 Names2TargetIndices.insert(std::make_pair(
StringRef(
I.second),
I.first));
2875 initNames2TargetIndices();
2876 auto IndexInfo = Names2TargetIndices.find(Name);
2877 if (IndexInfo == Names2TargetIndices.end())
2879 Index = IndexInfo->second;
2883 void MIParser::initNames2DirectTargetFlags() {
2884 if (!Names2DirectTargetFlags.empty())
2887 assert(
TII &&
"Expected target instruction info");
2889 for (
const auto &
I : Flags)
2890 Names2DirectTargetFlags.insert(
2894 bool MIParser::getDirectTargetFlag(
StringRef Name,
unsigned &
Flag) {
2895 initNames2DirectTargetFlags();
2896 auto FlagInfo = Names2DirectTargetFlags.find(Name);
2897 if (FlagInfo == Names2DirectTargetFlags.end())
2899 Flag = FlagInfo->second;
2903 void MIParser::initNames2BitmaskTargetFlags() {
2904 if (!Names2BitmaskTargetFlags.empty())
2907 assert(
TII &&
"Expected target instruction info");
2909 for (
const auto &
I : Flags)
2910 Names2BitmaskTargetFlags.insert(
2914 bool MIParser::getBitmaskTargetFlag(
StringRef Name,
unsigned &Flag) {
2915 initNames2BitmaskTargetFlags();
2916 auto FlagInfo = Names2BitmaskTargetFlags.find(Name);
2917 if (FlagInfo == Names2BitmaskTargetFlags.end())
2919 Flag = FlagInfo->second;
2923 void MIParser::initNames2MMOTargetFlags() {
2924 if (!Names2MMOTargetFlags.empty())
2927 assert(
TII &&
"Expected target instruction info");
2928 auto Flags =
TII->getSerializableMachineMemOperandTargetFlags();
2929 for (
const auto &
I : Flags)
2930 Names2MMOTargetFlags.insert(
2934 bool MIParser::getMMOTargetFlag(
StringRef Name,
2936 initNames2MMOTargetFlags();
2937 auto FlagInfo = Names2MMOTargetFlags.find(Name);
2938 if (FlagInfo == Names2MMOTargetFlags.end())
2940 Flag = FlagInfo->second;
2953 bool MIParser::parseStringConstant(std::string &Result) {
2955 return error(
"expected string constant");
2956 Result = Token.stringValue();
2964 return MIParser(PFS, Error, Src).parseBasicBlockDefinitions(PFS.
MBBSlots);
2969 return MIParser(PFS, Error, Src).parseBasicBlocks();
2975 return MIParser(PFS, Error, Src).parseStandaloneMBB(MBB);
2981 return MIParser(PFS, Error, Src).parseStandaloneRegister(Reg);
2987 return MIParser(PFS, Error, Src).parseStandaloneNamedRegister(Reg);
2993 return MIParser(PFS, Error, Src).parseStandaloneVirtualRegister(Info);
2999 return MIParser(PFS, Error, Src).parseStandaloneStackObject(FI);
3004 return MIParser(PFS, Error, Src).parseStandaloneMDNode(Node);
bool isFPPredicate() const
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override
Return an array that contains the direct target flag values and their names.
virtual StringRef getBufferIdentifier() const
Return an identifier for this buffer, typically the filename it was read from.
A parsed version of the target data layout string in and methods for querying it. ...
bool parseMachineBasicBlockDefinitions(PerFunctionMIParsingState &PFS, StringRef Src, SMDiagnostic &Error)
Parse the machine basic block definitions, and skip the machine instructions.
static void initSlots2BasicBlocks(const Function &F, DenseMap< unsigned, const BasicBlock *> &Slots2BasicBlocks)
A common definition of LaneBitmask for use in TableGen and CodeGen.
uint64_t getZExtValue() const
Get zero extended value.
static MachineOperand CreateCImm(const ConstantInt *CI)
GCNRegPressure max(const GCNRegPressure &P1, const GCNRegPressure &P2)
DenseMap< unsigned, unsigned > JumpTableSlots
LLVM_NODISCARD std::string str() const
str - Get the contents as an std::string.
const T & back() const
back - Get the last element.
MDNode * Scope
The tag for alias scope specification (used with noalias).
Atomic ordering constants.
DenseMap< unsigned, unsigned > ConstantPoolSlots
This class represents lattice values for constants.
MDNode * TBAA
The tag for type-based alias analysis.
Constant * parseConstantValue(StringRef Asm, SMDiagnostic &Err, const Module &M, const SlotMapping *Slots=nullptr)
Parse a type and a constant value in the given string.
static MachineOperand CreateMCSymbol(MCSymbol *Sym, unsigned char TargetFlags=0)
void setTargetFlags(unsigned F)
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
A Module instance is used to store all the information related to an LLVM module. ...
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
static BranchProbability getRaw(uint32_t N)
static MCCFIInstruction createRememberState(MCSymbol *L)
.cfi_remember_state Save all current rules for all registers.
void push_back(const T &Elt)
const MCPhysReg * getImplicitUses() const
Return a list of registers that are potentially read by any instance of this machine instruction...
static MachineOperand CreateJTI(unsigned Idx, unsigned char TargetFlags=0)
Describe properties that are true of each instruction in the target description file.
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE size_t size() const
size - Get the string size.
static MCCFIInstruction createOffset(MCSymbol *L, unsigned Register, int Offset)
.cfi_offset Previous value of Register is saved at offset Offset from CFA.
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
SyncScope::ID getOrInsertSyncScopeID(StringRef SSN)
getOrInsertSyncScopeID - Maps synchronization scope name to synchronization scope ID...
int getLocalSlot(const Value *V)
Return the slot number of the specified local value.
0 1 0 0 True if ordered and less than
ArrayRef< std::pair< unsigned, const char * > > getSerializableBitmaskMachineOperandTargetFlags() const override
Return an array that contains the bitmask target flag values and their names.
iterator find(StringRef Key)
DenseMap< unsigned, int > StackObjectSlots
LLT getType(unsigned Reg) const
Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register...
1 1 1 0 True if unordered or not equal
bool all_of(R &&range, UnaryPredicate P)
Provide wrappers to std::all_of which take ranges instead of having to pass begin/end explicitly...
unsigned getPointerSizeInBits(unsigned AS=0) const
Layout pointer size, in bits FIXME: The defaults need to be removed once all of the backends/clients ...
unsigned const TargetRegisterInfo * TRI
DenseMap< unsigned, VRegInfo * > VRegInfos
Manage lifetime of a slot tracker for printing IR.
bool parseMBBReference(PerFunctionMIParsingState &PFS, MachineBasicBlock *&MBB, StringRef Src, SMDiagnostic &Error)
const TargetRegisterClass * RC
static MCCFIInstruction createDefCfaOffset(MCSymbol *L, int Offset)
.cfi_def_cfa_offset modifies a rule for computing CFA.
MachineInstr * CreateMachineInstr(const MCInstrDesc &MCID, const DebugLoc &DL, bool NoImp=false)
CreateMachineInstr - Allocate a new MachineInstr.
StringRef lexMIToken(StringRef Source, MIToken &Token, function_ref< void(StringRef::iterator, const Twine &)> ErrorCallback)
Consume a single machine instruction token in the given source and return the remaining source string...
static MCCFIInstruction createAdjustCfaOffset(MCSymbol *L, int Adjustment)
.cfi_adjust_cfa_offset Same as .cfi_def_cfa_offset, but Offset is a relative value that is added/subt...
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE const char * data() const
data - Get a pointer to the start of the string (which may not be null terminated).
static MachineOperand CreateIntrinsicID(Intrinsic::ID ID)
unsigned getBitWidth() const
Return the number of bits in the APInt.
static MachineOperand CreateReg(unsigned Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)
static MCCFIInstruction createUndefined(MCSymbol *L, unsigned Register)
.cfi_undefined From now on the previous value of Register can't be restored anymore.
std::pair< iterator, bool > insert(const std::pair< KeyT, ValueT > &KV)
const char * getRegClassName(const TargetRegisterClass *Class) const
Returns the name of the register class.
1 0 0 1 True if unordered or equal
void guessSuccessors(const MachineBasicBlock &MBB, SmallVectorImpl< MachineBasicBlock *> &Result, bool &IsFallthrough)
Determine a possible list of successors of a basic block based on the basic block machine operand bei...
1 0 0 0 True if unordered: isnan(X) | isnan(Y)
std::map< unsigned, TrackingMDNodeRef > MetadataNodes
A description of a memory reference used in the backend.
amdgpu Simplify well known AMD library false Value Value const Twine & Name
std::string toString(Error E)
Write all error messages (if any) in E to a string.
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
const HexagonInstrInfo * TII
static const BasicBlock * getIRBlockFromSlot(unsigned Slot, const DenseMap< unsigned, const BasicBlock *> &Slots2BasicBlocks)
VRegInfo & getVRegInfoNamed(StringRef RegName)
union llvm::VRegInfo::@347 D
support::ulittle32_t Word
static constexpr LaneBitmask getAll()
0 1 0 1 True if ordered and less than or equal
const Name2RegBankMap & Names2RegBanks
The memory access is dereferenceable (i.e., doesn't trap).
static MachineOperand CreateRegMask(const uint32_t *Mask)
CreateRegMask - Creates a register mask operand referencing Mask.
static MachineOperand CreateRegLiveOut(const uint32_t *Mask)
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE R Default(T Value)
LLVM_NODISCARD unsigned addFrameInst(const MCCFIInstruction &Inst)
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, unsigned base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
This file implements a class to represent arbitrary precision integral constant values and operations...
AtomicOrdering
Atomic ordering for LLVM's memory model.
DenseMap< unsigned, int > FixedStackObjectSlots
static std::string getRegisterName(const TargetRegisterInfo *TRI, unsigned Reg)
const MemoryBuffer * getMemoryBuffer(unsigned i) const
Type * getType() const
All values are typed, get the type of this value.
PseudoSourceValueManager & getPSVManager() const
virtual unsigned lookupName(const char *Name, unsigned Len) const =0
Look up target intrinsic by name.
GlobalValue * getNamedValue(StringRef Name) const
Return the global value in the module with the specified name, of arbitrary type. ...
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
const char * getSubRegIndexName(unsigned SubIdx) const
Return the human-readable symbolic target-specific name for the specified SubRegIndex.
void setPostInstrSymbol(MachineFunction &MF, MCSymbol *Symbol)
Set a symbol that will be emitted just after the instruction itself.
virtual const TargetInstrInfo * getInstrInfo() const
static LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
bool parseVirtualRegisterReference(PerFunctionMIParsingState &PFS, VRegInfo *&Info, StringRef Src, SMDiagnostic &Error)
static MachineOperand CreatePredicate(unsigned Pred)
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *bb=nullptr)
CreateMachineBasicBlock - Allocate a new MachineBasicBlock.
const PseudoSourceValue * getFixedStack(int FI)
Return a pseudo source value referencing a fixed stack frame entry, e.g., a spill slot...
Analysis containing CSE Info
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
void normalizeSuccProbs()
Normalize probabilities of all successors so that the sum of them becomes one.
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
const char * getName(unsigned RegNo) const
Return the human-readable symbolic target-specific name for the specified physical register...
Flag
These should be considered private to the implementation of the MCInstrDesc class.
iterator find(const_arg_type_t< KeyT > Val)
unsigned getMainFileID() const
bool isIdenticalTo(const MachineOperand &Other) const
Returns true if this operand is identical to the specified operand except for liveness related flags ...
MCContext & getContext() const
The memory access is volatile.
static MCCFIInstruction createSameValue(MCSymbol *L, unsigned Register)
.cfi_same_value Current value of Register is the same as in the previous frame.
static MDTuple * get(LLVMContext &Context, ArrayRef< Metadata *> MDs)
A switch()-like statement whose cases are string literals.
bool parseStackObjectReference(PerFunctionMIParsingState &PFS, int &FI, StringRef Src, SMDiagnostic &Error)
static MCCFIInstruction createNegateRAState(MCSymbol *L)
.cfi_negate_ra_state AArch64 negate RA state.
const MCPhysReg * getImplicitDefs() const
Return a list of registers that are potentially written by any instance of this machine instruction...
void addLiveIn(MCPhysReg PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
unsigned const MachineRegisterInfo * MRI
StringRef getName() const
Return the name of the corresponding LLVM basic block, or an empty string.
static const char * printImplicitRegisterFlag(const MachineOperand &MO)
static MCCFIInstruction createDefCfa(MCSymbol *L, unsigned Register, int Offset)
.cfi_def_cfa defines a rule for computing CFA as: take address from Register and add Offset to it...
static Intrinsic::ID lookupIntrinsicID(StringRef Name)
This does the actual lookup of an intrinsic ID which matches the given function name.
static MachineOperand CreateCPI(unsigned Idx, int Offset, unsigned char TargetFlags=0)
LLVM Basic Block Representation.
const PseudoSourceValue * getExternalSymbolCallEntry(const char *ES)
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
This is an important class for using LLVM in a threaded context.
static MCCFIInstruction createDefCfaRegister(MCSymbol *L, unsigned Register)
.cfi_def_cfa_register modifies a rule for computing CFA.
static BlockAddress * get(Function *F, BasicBlock *BB)
Return a BlockAddress for the specified function and basic block.
static MachineOperand CreateFPImm(const ConstantFP *CFP)
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
size_t size() const
size - Get the array size.
static MCCFIInstruction createWindowSave(MCSymbol *L)
.cfi_window_save SPARC register window is saved.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
This is an important base class in LLVM.
This file contains the declarations for the subclasses of Constant, which represent the different fla...
bool isPointerTy() const
True if this is an instance of PointerType.
StringMap< VRegInfo * > VRegInfosNamed
unsigned getOperationEncoding(StringRef OperationEncodingString)
const MCPhysReg * ImplicitDefs
void setType(unsigned VReg, LLT Ty)
Set the low-level type of VReg to Ty.
BumpPtrAllocator Allocator
static MachineOperand CreateBA(const BlockAddress *BA, int64_t Offset, unsigned char TargetFlags=0)
bool parseNamedRegisterReference(PerFunctionMIParsingState &PFS, unsigned &Reg, StringRef Src, SMDiagnostic &Error)
void setFlag(MIFlag Flag)
Set a MI flag.
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
static MCCFIInstruction createRelOffset(MCSymbol *L, unsigned Register, int Offset)
.cfi_rel_offset Previous value of Register is saved at offset Offset from the current CFA register...
static MachineOperand CreateGA(const GlobalValue *GV, int64_t Offset, unsigned char TargetFlags=0)
static MachineOperand CreateTargetIndex(unsigned Idx, int64_t Offset, unsigned char TargetFlags=0)
static MCCFIInstruction createRestore(MCSymbol *L, unsigned Register)
.cfi_restore says that the rule for Register is now the same as it was at the beginning of the functi...
0 1 1 1 True if ordered (no nans)
The memory access is non-temporal.
llvm::Expected< Value > parse(llvm::StringRef JSON)
Parses the provided JSON source, or returns a ParseError.
std::vector< GlobalValue * > GlobalValues
This owns the files read by a parser, handles include stacks, and handles diagnostic wrangling...
void setOffset(int64_t Offset)
1 1 1 1 Always true (always folded)
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function. ...
void incorporateFunction(const Function &F)
Incorporate the given function.
const SlotMapping & IRSlots
static MCCFIInstruction createRestoreState(MCSymbol *L)
.cfi_restore_state Restore the previously saved state.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This class contains a discriminated union of information about pointers in memory operands...
const char * createExternalSymbolName(StringRef Name)
Allocate a string and populate it with the given external symbol name.
1 1 0 1 True if unordered, less than, or equal
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
SMDiagnostic GetMessage(SMLoc Loc, DiagKind Kind, const Twine &Msg, ArrayRef< SMRange > Ranges=None, ArrayRef< SMFixIt > FixIts=None) const
Return an SMDiagnostic at the specified location with the specified string.
bool parseMachineInstructions(PerFunctionMIParsingState &PFS, StringRef Src, SMDiagnostic &Error)
Parse the machine instructions.
TargetIntrinsicInfo - Interface to description of machine instruction set.
Struct that holds a reference to a particular GUID in a global value summary.
The memory access writes data.
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE StringRef drop_front(size_t N=1) const
Return a StringRef equal to 'this' but with the first N elements dropped.
0 0 1 0 True if ordered and greater than
const Name2RegClassMap & Names2RegClasses
unsigned createIncompleteVirtualRegister(StringRef Name="")
Creates a new virtual register that has no register class, register bank or size assigned yet...
static MachineOperand CreateMetadata(const MDNode *Meta)
void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
void addOperand(MachineFunction &MF, const MachineOperand &Op)
Add the specified operand to the instruction.
void setFlags(unsigned flags)
enum llvm::VRegInfo::uint8_t Kind
MachineOperand class - Representation of each machine instruction operand.
1 1 0 0 True if unordered or less than
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
Module.h This file contains the declarations for the Module class.
static bool isImplicitOperandIn(const MachineOperand &ImplicitOperand, ArrayRef< ParsedMachineOperand > Operands)
Return true if the parsed machine operands contain a given machine operand.
StringRef getMessage() const
A collection of metadata nodes that might be associated with a memory access used by the alias-analys...
MDNode * NoAlias
The tag specifying the noalias scope.
uint32_t * allocateRegMask()
Allocate and initialize a register mask with NumRegister bits.
This class implements the register bank concept.
const Function & getFunction() const
Return the LLVM function that this machine code represents.
This interface provides simple read-only access to a block of memory, and provides simple methods for...
ValueSymbolTable * getValueSymbolTable()
getSymbolTable() - Return the symbol table if any, otherwise nullptr.
bool isIntPredicate() const
StringMap - This is an unconventional map that is specialized for handling keys that are "strings"...
Class for arbitrary precision integers.
Special value supplied for machine level alias analysis.
const PseudoSourceValue * getJumpTable()
Return a pseudo source value referencing a jump table.
const PseudoSourceValue * getGlobalValueCallEntry(const GlobalValue *GV)
static MachineOperand CreateES(const char *SymName, unsigned char TargetFlags=0)
const PseudoSourceValue * getGOT()
Return a pseudo source value referencing the global offset table (or something the like)...
LLVM_ATTRIBUTE_ALWAYS_INLINE StringSwitch & Case(StringLiteral S, T Value)
This struct contains the mappings from the slot numbers to unnamed metadata nodes, global values and types.
bool parseMDNode(PerFunctionMIParsingState &PFS, MDNode *&Node, StringRef Src, SMDiagnostic &Error)
static SMLoc getFromPointer(const char *Ptr)
Flags
Flags values. These may be or'd together.
amdgpu Simplify well known AMD library false Value Value * Arg
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
The memory access reads data.
bool Explicit
VReg was explicitly specified in the .mir file.
Representation of each machine instruction.
const AllocaInst * getObjectAllocation(int ObjectIdx) const
Return the underlying Alloca of the specified stack object if it exists.
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
const char * getBufferEnd() const
static MachineOperand CreateMBB(MachineBasicBlock *MBB, unsigned char TargetFlags=0)
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
void setPreInstrSymbol(MachineFunction &MF, MCSymbol *Symbol)
Set a symbol that will be emitted just prior to the instruction itself.
MCSymbol * getOrCreateSymbol(const Twine &Name)
Lookup the symbol inside with the specified Name.
LLVM_NODISCARD bool empty() const
unsigned greater or equal
This file provides utility analysis objects describing memory locations.
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
virtual const TargetIntrinsicInfo * getIntrinsicInfo() const
If intrinsic information is available, return it. If not, return null.
static MachineOperand CreateCFIIndex(unsigned CFIIndex)
static MachineOperand CreateImm(int64_t Val)
VRegInfo & getVRegInfo(unsigned Num)
The memory access always returns the same value (or traps).
bool isCall() const
Return true if the instruction is a call.
0 1 1 0 True if ordered and operands are unequal
DenseMap< unsigned, MachineBasicBlock * > MBBSlots
LLVM_NODISCARD std::enable_if<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
unsigned getNumSubRegIndices() const
Return the number of sub-register indices understood by the target.
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
1 0 1 0 True if unordered or greater than
const char * getBufferStart() const
Value * lookup(StringRef Name) const
This method finds the value with the given Name in the the symbol table.
std::string str() const
Return the twine contents as a std::string.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
const PseudoSourceValue * getStack()
Return a pseudo source value referencing the area below the stack frame of a function, e.g., the argument space.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
void insert(iterator MBBI, MachineBasicBlock *MBB)
void setMemRefs(MachineFunction &MF, ArrayRef< MachineMemOperand *> MemRefs)
Assign this MachineInstr's memory reference descriptor list.
0 0 0 1 True if ordered and equal
Module * getParent()
Get the module that this global value is contained inside of...
LLVM Value Representation.
static LLT pointer(uint16_t AddressSpace, unsigned SizeInBits)
Get a low-level pointer in the given address space (defaulting to 0).
A token produced by the machine instruction lexer.
1 0 1 1 True if unordered, greater than, or equal
Synchronized with respect to all concurrently executing threads.
Lightweight error class with error context and mandatory checking.
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
StringRef - Represent a constant reference to a string, i.e.
static LLT vector(uint16_t NumElements, unsigned ScalarSizeInBits)
Get a low-level vector of some number of elements and element width.
const RegisterBank * RegBank
Represents a location in source code.
void setIsDebug(bool Val=true)
static MCCFIInstruction createEscape(MCSymbol *L, StringRef Vals)
.cfi_escape Allows the user to add arbitrary bytes to the unwind info.
bool parseRegisterReference(PerFunctionMIParsingState &PFS, unsigned &Reg, StringRef Src, SMDiagnostic &Error)
0 0 1 1 True if ordered and greater than or equal
static void mapValueToSlot(const Value *V, ModuleSlotTracker &MST, DenseMap< unsigned, const Value *> &Slots2Values)
static void initSlots2Values(const Function &F, DenseMap< unsigned, const Value *> &Slots2Values)
Creates the mapping from slot numbers to function's unnamed IR values.
static MachineOperand CreateFI(int Idx)
const PseudoSourceValue * getConstantPool()
Return a pseudo source value referencing the constant pool.
static MCCFIInstruction createRegister(MCSymbol *L, unsigned Register1, unsigned Register2)
.cfi_register Previous value of Register1 is saved in register Register2.
iterator_range< arg_iterator > args()
0 0 0 0 Always false (always folded)
bool empty() const
empty - Check if the array is empty.
const MCPhysReg * ImplicitUses
Instances of this class encapsulate one diagnostic report, allowing printing to a raw_ostream as a ca...
PerFunctionMIParsingState(MachineFunction &MF, SourceMgr &SM, const SlotMapping &IRSlots, const Name2RegClassMap &Names2RegClasses, const Name2RegBankMap &Names2RegBanks)
void tieOperands(unsigned DefIdx, unsigned UseIdx)
Add a tie between the register operands at DefIdx and UseIdx.