27 #define DEBUG_TYPE "regalloc" 34 : Pos(0), HardHints(
false) {
45 for (
unsigned I = 0,
E = Hints.
size();
I !=
E; ++
I)
51 for (
unsigned I = 0,
E = Hints.
size();
I !=
E; ++
I)
53 "Target hint is outside allocation order.");
virtual bool getRegAllocationHints(unsigned VirtReg, ArrayRef< MCPhysReg > Order, SmallVectorImpl< MCPhysReg > &Hints, const MachineFunction &MF, const VirtRegMap *VRM=nullptr, const LiveRegMatrix *Matrix=nullptr) const
Get a list of 'hint' registers that the register allocator should try first when allocating a physica...
ArrayRef< MCPhysReg > getOrder(const TargetRegisterClass *RC) const
getOrder - Returns the preferred allocation order for RC.
const TargetRegisterClass * getRegClass(unsigned Reg) const
Return the register class of the specified virtual register.
void rewind()
Start over from the beginning.
This class represents lattice values for constants.
unsigned const TargetRegisterInfo * TRI
const TargetRegisterInfo & getTargetRegInfo() const
AllocationOrder(unsigned VirtReg, const VirtRegMap &VRM, const RegisterClassInfo &RegClassInfo, const LiveRegMatrix *Matrix)
Create a new AllocationOrder for VirtReg.
MachineFunction & getMachineFunction() const
Printable printReg(unsigned Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
LLVM_NODISCARD bool empty() const
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool is_contained(R &&Range, const E &Element)
Wrapper function around std::find to detect if an element exists in a container.