LLVM  8.0.1
MipsCallLowering.cpp
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1 //===- MipsCallLowering.cpp -------------------------------------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 /// This file implements the lowering of LLVM calls to machine code calls for
12 /// GlobalISel.
13 //
14 //===----------------------------------------------------------------------===//
15 
16 #include "MipsCallLowering.h"
17 #include "MipsCCState.h"
18 #include "MipsTargetMachine.h"
19 #include "llvm/CodeGen/Analysis.h"
21 
22 using namespace llvm;
23 
25  : CallLowering(&TLI) {}
26 
27 bool MipsCallLowering::MipsHandler::assign(unsigned VReg,
28  const CCValAssign &VA) {
29  if (VA.isRegLoc()) {
30  assignValueToReg(VReg, VA);
31  } else if (VA.isMemLoc()) {
32  assignValueToAddress(VReg, VA);
33  } else {
34  return false;
35  }
36  return true;
37 }
38 
40  ArrayRef<CCValAssign> ArgLocs,
41  unsigned ArgLocsStartIndex) {
42  for (unsigned i = 0; i < VRegs.size(); ++i)
43  if (!assign(VRegs[i], ArgLocs[ArgLocsStartIndex + i]))
44  return false;
45  return true;
46 }
47 
50  if (!MIRBuilder.getMF().getDataLayout().isLittleEndian())
51  std::reverse(VRegs.begin(), VRegs.end());
52 }
53 
57  unsigned SplitLength;
58  const Function &F = MIRBuilder.getMF().getFunction();
59  const DataLayout &DL = F.getParent()->getDataLayout();
60  const MipsTargetLowering &TLI = *static_cast<const MipsTargetLowering *>(
61  MIRBuilder.getMF().getSubtarget().getTargetLowering());
62 
63  for (unsigned ArgsIndex = 0, ArgLocsIndex = 0; ArgsIndex < Args.size();
64  ++ArgsIndex, ArgLocsIndex += SplitLength) {
65  EVT VT = TLI.getValueType(DL, Args[ArgsIndex].Ty);
66  SplitLength = TLI.getNumRegistersForCallingConv(F.getContext(),
67  F.getCallingConv(), VT);
68  if (SplitLength > 1) {
69  VRegs.clear();
70  MVT RegisterVT = TLI.getRegisterTypeForCallingConv(
71  F.getContext(), F.getCallingConv(), VT);
72  for (unsigned i = 0; i < SplitLength; ++i)
73  VRegs.push_back(MRI.createGenericVirtualRegister(LLT{RegisterVT}));
74 
75  if (!handleSplit(VRegs, ArgLocs, ArgLocsIndex, Args[ArgsIndex].Reg))
76  return false;
77  } else {
78  if (!assign(Args[ArgsIndex].Reg, ArgLocs[ArgLocsIndex]))
79  return false;
80  }
81  }
82  return true;
83 }
84 
85 namespace {
86 class IncomingValueHandler : public MipsCallLowering::MipsHandler {
87 public:
88  IncomingValueHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI)
89  : MipsHandler(MIRBuilder, MRI) {}
90 
91 private:
92  void assignValueToReg(unsigned ValVReg, const CCValAssign &VA) override;
93 
94  unsigned getStackAddress(const CCValAssign &VA,
95  MachineMemOperand *&MMO) override;
96 
97  void assignValueToAddress(unsigned ValVReg, const CCValAssign &VA) override;
98 
99  bool handleSplit(SmallVectorImpl<unsigned> &VRegs,
100  ArrayRef<CCValAssign> ArgLocs, unsigned ArgLocsStartIndex,
101  unsigned ArgsReg) override;
102 
103  virtual void markPhysRegUsed(unsigned PhysReg) {
104  MIRBuilder.getMBB().addLiveIn(PhysReg);
105  }
106 
107  void buildLoad(unsigned Val, const CCValAssign &VA) {
108  MachineMemOperand *MMO;
109  unsigned Addr = getStackAddress(VA, MMO);
110  MIRBuilder.buildLoad(Val, Addr, *MMO);
111  }
112 };
113 
114 class CallReturnHandler : public IncomingValueHandler {
115 public:
116  CallReturnHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
117  MachineInstrBuilder &MIB)
118  : IncomingValueHandler(MIRBuilder, MRI), MIB(MIB) {}
119 
120 private:
121  void markPhysRegUsed(unsigned PhysReg) override {
122  MIB.addDef(PhysReg, RegState::Implicit);
123  }
124 
125  MachineInstrBuilder &MIB;
126 };
127 
128 } // end anonymous namespace
129 
130 void IncomingValueHandler::assignValueToReg(unsigned ValVReg,
131  const CCValAssign &VA) {
132  unsigned PhysReg = VA.getLocReg();
133  switch (VA.getLocInfo()) {
134  case CCValAssign::LocInfo::SExt:
135  case CCValAssign::LocInfo::ZExt:
136  case CCValAssign::LocInfo::AExt: {
137  auto Copy = MIRBuilder.buildCopy(LLT{VA.getLocVT()}, PhysReg);
138  MIRBuilder.buildTrunc(ValVReg, Copy);
139  break;
140  }
141  default:
142  MIRBuilder.buildCopy(ValVReg, PhysReg);
143  break;
144  }
145  markPhysRegUsed(PhysReg);
146 }
147 
148 unsigned IncomingValueHandler::getStackAddress(const CCValAssign &VA,
149  MachineMemOperand *&MMO) {
150  unsigned Size = alignTo(VA.getValVT().getSizeInBits(), 8) / 8;
151  unsigned Offset = VA.getLocMemOffset();
152  MachineFrameInfo &MFI = MIRBuilder.getMF().getFrameInfo();
153 
154  int FI = MFI.CreateFixedObject(Size, Offset, true);
155  MachinePointerInfo MPO =
156  MachinePointerInfo::getFixedStack(MIRBuilder.getMF(), FI);
157  MMO = MIRBuilder.getMF().getMachineMemOperand(MPO, MachineMemOperand::MOLoad,
158  Size, /* Alignment */ 0);
159 
160  unsigned AddrReg = MRI.createGenericVirtualRegister(LLT::pointer(0, 32));
161  MIRBuilder.buildFrameIndex(AddrReg, FI);
162 
163  return AddrReg;
164 }
165 
166 void IncomingValueHandler::assignValueToAddress(unsigned ValVReg,
167  const CCValAssign &VA) {
168  if (VA.getLocInfo() == CCValAssign::SExt ||
169  VA.getLocInfo() == CCValAssign::ZExt ||
170  VA.getLocInfo() == CCValAssign::AExt) {
171  unsigned LoadReg = MRI.createGenericVirtualRegister(LLT::scalar(32));
172  buildLoad(LoadReg, VA);
173  MIRBuilder.buildTrunc(ValVReg, LoadReg);
174  } else
175  buildLoad(ValVReg, VA);
176 }
177 
178 bool IncomingValueHandler::handleSplit(SmallVectorImpl<unsigned> &VRegs,
179  ArrayRef<CCValAssign> ArgLocs,
180  unsigned ArgLocsStartIndex,
181  unsigned ArgsReg) {
182  if (!assignVRegs(VRegs, ArgLocs, ArgLocsStartIndex))
183  return false;
184  setLeastSignificantFirst(VRegs);
185  MIRBuilder.buildMerge(ArgsReg, VRegs);
186  return true;
187 }
188 
189 namespace {
190 class OutgoingValueHandler : public MipsCallLowering::MipsHandler {
191 public:
192  OutgoingValueHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
193  MachineInstrBuilder &MIB)
194  : MipsHandler(MIRBuilder, MRI), MIB(MIB) {}
195 
196 private:
197  void assignValueToReg(unsigned ValVReg, const CCValAssign &VA) override;
198 
199  unsigned getStackAddress(const CCValAssign &VA,
200  MachineMemOperand *&MMO) override;
201 
202  void assignValueToAddress(unsigned ValVReg, const CCValAssign &VA) override;
203 
204  bool handleSplit(SmallVectorImpl<unsigned> &VRegs,
205  ArrayRef<CCValAssign> ArgLocs, unsigned ArgLocsStartIndex,
206  unsigned ArgsReg) override;
207 
208  unsigned extendRegister(unsigned ValReg, const CCValAssign &VA);
209 
210  MachineInstrBuilder &MIB;
211 };
212 } // end anonymous namespace
213 
214 void OutgoingValueHandler::assignValueToReg(unsigned ValVReg,
215  const CCValAssign &VA) {
216  unsigned PhysReg = VA.getLocReg();
217  unsigned ExtReg = extendRegister(ValVReg, VA);
218  MIRBuilder.buildCopy(PhysReg, ExtReg);
219  MIB.addUse(PhysReg, RegState::Implicit);
220 }
221 
222 unsigned OutgoingValueHandler::getStackAddress(const CCValAssign &VA,
223  MachineMemOperand *&MMO) {
224  LLT p0 = LLT::pointer(0, 32);
225  LLT s32 = LLT::scalar(32);
226  unsigned SPReg = MRI.createGenericVirtualRegister(p0);
227  MIRBuilder.buildCopy(SPReg, Mips::SP);
228 
229  unsigned OffsetReg = MRI.createGenericVirtualRegister(s32);
230  unsigned Offset = VA.getLocMemOffset();
231  MIRBuilder.buildConstant(OffsetReg, Offset);
232 
233  unsigned AddrReg = MRI.createGenericVirtualRegister(p0);
234  MIRBuilder.buildGEP(AddrReg, SPReg, OffsetReg);
235 
236  MachinePointerInfo MPO =
237  MachinePointerInfo::getStack(MIRBuilder.getMF(), Offset);
238  unsigned Size = alignTo(VA.getValVT().getSizeInBits(), 8) / 8;
239  MMO = MIRBuilder.getMF().getMachineMemOperand(MPO, MachineMemOperand::MOStore,
240  Size, /* Alignment */ 0);
241 
242  return AddrReg;
243 }
244 
245 void OutgoingValueHandler::assignValueToAddress(unsigned ValVReg,
246  const CCValAssign &VA) {
247  MachineMemOperand *MMO;
248  unsigned Addr = getStackAddress(VA, MMO);
249  unsigned ExtReg = extendRegister(ValVReg, VA);
250  MIRBuilder.buildStore(ExtReg, Addr, *MMO);
251 }
252 
253 unsigned OutgoingValueHandler::extendRegister(unsigned ValReg,
254  const CCValAssign &VA) {
255  LLT LocTy{VA.getLocVT()};
256  switch (VA.getLocInfo()) {
257  case CCValAssign::SExt: {
258  unsigned ExtReg = MRI.createGenericVirtualRegister(LocTy);
259  MIRBuilder.buildSExt(ExtReg, ValReg);
260  return ExtReg;
261  }
262  case CCValAssign::ZExt: {
263  unsigned ExtReg = MRI.createGenericVirtualRegister(LocTy);
264  MIRBuilder.buildZExt(ExtReg, ValReg);
265  return ExtReg;
266  }
267  case CCValAssign::AExt: {
268  unsigned ExtReg = MRI.createGenericVirtualRegister(LocTy);
269  MIRBuilder.buildAnyExt(ExtReg, ValReg);
270  return ExtReg;
271  }
272  // TODO : handle upper extends
273  case CCValAssign::Full:
274  return ValReg;
275  default:
276  break;
277  }
278  llvm_unreachable("unable to extend register");
279 }
280 
281 bool OutgoingValueHandler::handleSplit(SmallVectorImpl<unsigned> &VRegs,
282  ArrayRef<CCValAssign> ArgLocs,
283  unsigned ArgLocsStartIndex,
284  unsigned ArgsReg) {
285  MIRBuilder.buildUnmerge(VRegs, ArgsReg);
286  setLeastSignificantFirst(VRegs);
287  if (!assignVRegs(VRegs, ArgLocs, ArgLocsStartIndex))
288  return false;
289 
290  return true;
291 }
292 
293 static bool isSupportedType(Type *T) {
294  if (T->isIntegerTy())
295  return true;
296  if (T->isPointerTy())
297  return true;
298  return false;
299 }
300 
301 static CCValAssign::LocInfo determineLocInfo(const MVT RegisterVT, const EVT VT,
302  const ISD::ArgFlagsTy &Flags) {
303  // > does not mean loss of information as type RegisterVT can't hold type VT,
304  // it means that type VT is split into multiple registers of type RegisterVT
305  if (VT.getSizeInBits() >= RegisterVT.getSizeInBits())
307  if (Flags.isSExt())
308  return CCValAssign::LocInfo::SExt;
309  if (Flags.isZExt())
310  return CCValAssign::LocInfo::ZExt;
311  return CCValAssign::LocInfo::AExt;
312 }
313 
314 template <typename T>
316  const SmallVectorImpl<T> &Arguments) {
317  for (unsigned i = 0; i < ArgLocs.size(); ++i) {
318  const CCValAssign &VA = ArgLocs[i];
320  Arguments[i].VT, Arguments[i].ArgVT, Arguments[i].Flags);
321  if (VA.isMemLoc())
322  ArgLocs[i] =
324  VA.getLocMemOffset(), VA.getLocVT(), LocInfo);
325  else
326  ArgLocs[i] = CCValAssign::getReg(VA.getValNo(), VA.getValVT(),
327  VA.getLocReg(), VA.getLocVT(), LocInfo);
328  }
329 }
330 
332  const Value *Val,
333  ArrayRef<unsigned> VRegs) const {
334 
335  MachineInstrBuilder Ret = MIRBuilder.buildInstrNoInsert(Mips::RetRA);
336 
337  if (Val != nullptr && !isSupportedType(Val->getType()))
338  return false;
339 
340  if (!VRegs.empty()) {
341  MachineFunction &MF = MIRBuilder.getMF();
342  const Function &F = MF.getFunction();
343  const DataLayout &DL = MF.getDataLayout();
344  const MipsTargetLowering &TLI = *getTLI<MipsTargetLowering>();
345  LLVMContext &Ctx = Val->getType()->getContext();
346 
347  SmallVector<EVT, 4> SplitEVTs;
348  ComputeValueVTs(TLI, DL, Val->getType(), SplitEVTs);
349  assert(VRegs.size() == SplitEVTs.size() &&
350  "For each split Type there should be exactly one VReg.");
351 
352  SmallVector<ArgInfo, 8> RetInfos;
353  SmallVector<unsigned, 8> OrigArgIndices;
354 
355  for (unsigned i = 0; i < SplitEVTs.size(); ++i) {
356  ArgInfo CurArgInfo = ArgInfo{VRegs[i], SplitEVTs[i].getTypeForEVT(Ctx)};
357  setArgFlags(CurArgInfo, AttributeList::ReturnIndex, DL, F);
358  splitToValueTypes(CurArgInfo, 0, RetInfos, OrigArgIndices);
359  }
360 
362  subTargetRegTypeForCallingConv(F, RetInfos, OrigArgIndices, Outs);
363 
365  MipsCCState CCInfo(F.getCallingConv(), F.isVarArg(), MF, ArgLocs,
366  F.getContext());
367  CCInfo.AnalyzeReturn(Outs, TLI.CCAssignFnForReturn());
368  setLocInfo(ArgLocs, Outs);
369 
370  OutgoingValueHandler RetHandler(MIRBuilder, MF.getRegInfo(), Ret);
371  if (!RetHandler.handle(ArgLocs, RetInfos)) {
372  return false;
373  }
374  }
375  MIRBuilder.insertInstr(Ret);
376  return true;
377 }
378 
380  const Function &F,
381  ArrayRef<unsigned> VRegs) const {
382 
383  // Quick exit if there aren't any args.
384  if (F.arg_empty())
385  return true;
386 
387  if (F.isVarArg()) {
388  return false;
389  }
390 
391  for (auto &Arg : F.args()) {
392  if (!isSupportedType(Arg.getType()))
393  return false;
394  }
395 
396  MachineFunction &MF = MIRBuilder.getMF();
397  const DataLayout &DL = MF.getDataLayout();
398  const MipsTargetLowering &TLI = *getTLI<MipsTargetLowering>();
399 
400  SmallVector<ArgInfo, 8> ArgInfos;
401  SmallVector<unsigned, 8> OrigArgIndices;
402  unsigned i = 0;
403  for (auto &Arg : F.args()) {
404  ArgInfo AInfo(VRegs[i], Arg.getType());
405  setArgFlags(AInfo, i + AttributeList::FirstArgIndex, DL, F);
406  splitToValueTypes(AInfo, i, ArgInfos, OrigArgIndices);
407  ++i;
408  }
409 
411  subTargetRegTypeForCallingConv(F, ArgInfos, OrigArgIndices, Ins);
412 
414  MipsCCState CCInfo(F.getCallingConv(), F.isVarArg(), MF, ArgLocs,
415  F.getContext());
416 
417  const MipsTargetMachine &TM =
418  static_cast<const MipsTargetMachine &>(MF.getTarget());
419  const MipsABIInfo &ABI = TM.getABI();
420  CCInfo.AllocateStack(ABI.GetCalleeAllocdArgSizeInBytes(F.getCallingConv()),
421  1);
422  CCInfo.AnalyzeFormalArguments(Ins, TLI.CCAssignFnForCall());
423  setLocInfo(ArgLocs, Ins);
424 
425  IncomingValueHandler Handler(MIRBuilder, MF.getRegInfo());
426  if (!Handler.handle(ArgLocs, ArgInfos))
427  return false;
428 
429  return true;
430 }
431 
433  CallingConv::ID CallConv,
434  const MachineOperand &Callee,
435  const ArgInfo &OrigRet,
436  ArrayRef<ArgInfo> OrigArgs) const {
437 
438  if (CallConv != CallingConv::C)
439  return false;
440 
441  for (auto &Arg : OrigArgs) {
442  if (!isSupportedType(Arg.Ty))
443  return false;
444  if (Arg.Flags.isByVal() || Arg.Flags.isSRet())
445  return false;
446  }
447  if (OrigRet.Reg && !isSupportedType(OrigRet.Ty))
448  return false;
449 
450  MachineFunction &MF = MIRBuilder.getMF();
451  const Function &F = MF.getFunction();
452  const MipsTargetLowering &TLI = *getTLI<MipsTargetLowering>();
453  const MipsTargetMachine &TM =
454  static_cast<const MipsTargetMachine &>(MF.getTarget());
455  const MipsABIInfo &ABI = TM.getABI();
456 
457  MachineInstrBuilder CallSeqStart =
458  MIRBuilder.buildInstr(Mips::ADJCALLSTACKDOWN);
459 
460  // FIXME: Add support for pic calling sequences, long call sequences for O32,
461  // N32 and N64. First handle the case when Callee.isReg().
462  if (Callee.isReg())
463  return false;
464 
465  MachineInstrBuilder MIB = MIRBuilder.buildInstrNoInsert(Mips::JAL);
466  MIB.addDef(Mips::SP, RegState::Implicit);
467  MIB.add(Callee);
470 
471  TargetLowering::ArgListTy FuncOrigArgs;
472  FuncOrigArgs.reserve(OrigArgs.size());
473 
474  SmallVector<ArgInfo, 8> ArgInfos;
475  SmallVector<unsigned, 8> OrigArgIndices;
476  unsigned i = 0;
477  for (auto &Arg : OrigArgs) {
478 
480  Entry.Ty = Arg.Ty;
481  FuncOrigArgs.push_back(Entry);
482 
483  splitToValueTypes(Arg, i, ArgInfos, OrigArgIndices);
484  ++i;
485  }
486 
488  subTargetRegTypeForCallingConv(F, ArgInfos, OrigArgIndices, Outs);
489 
491  MipsCCState CCInfo(F.getCallingConv(), F.isVarArg(), MF, ArgLocs,
492  F.getContext());
493 
494  CCInfo.AllocateStack(ABI.GetCalleeAllocdArgSizeInBytes(CallConv), 1);
495  const char *Call = Callee.isSymbol() ? Callee.getSymbolName() : nullptr;
496  CCInfo.AnalyzeCallOperands(Outs, TLI.CCAssignFnForCall(), FuncOrigArgs, Call);
497  setLocInfo(ArgLocs, Outs);
498 
499  OutgoingValueHandler RetHandler(MIRBuilder, MF.getRegInfo(), MIB);
500  if (!RetHandler.handle(ArgLocs, ArgInfos)) {
501  return false;
502  }
503 
504  unsigned NextStackOffset = CCInfo.getNextStackOffset();
506  unsigned StackAlignment = TFL->getStackAlignment();
507  NextStackOffset = alignTo(NextStackOffset, StackAlignment);
508  CallSeqStart.addImm(NextStackOffset).addImm(0);
509 
510  MIRBuilder.insertInstr(MIB);
511 
512  if (OrigRet.Reg) {
513 
514  ArgInfos.clear();
515  SmallVector<unsigned, 8> OrigRetIndices;
516 
517  splitToValueTypes(OrigRet, 0, ArgInfos, OrigRetIndices);
518 
520  subTargetRegTypeForCallingConv(F, ArgInfos, OrigRetIndices, Ins);
521 
523  MipsCCState CCInfo(F.getCallingConv(), F.isVarArg(), MF, ArgLocs,
524  F.getContext());
525 
526  CCInfo.AnalyzeCallResult(Ins, TLI.CCAssignFnForReturn(), OrigRet.Ty, Call);
527  setLocInfo(ArgLocs, Ins);
528 
529  CallReturnHandler Handler(MIRBuilder, MF.getRegInfo(), MIB);
530  if (!Handler.handle(ArgLocs, ArgInfos))
531  return false;
532  }
533 
534  MIRBuilder.buildInstr(Mips::ADJCALLSTACKUP).addImm(NextStackOffset).addImm(0);
535 
536  return true;
537 }
538 
539 template <typename T>
540 void MipsCallLowering::subTargetRegTypeForCallingConv(
542  ArrayRef<unsigned> OrigArgIndices, SmallVectorImpl<T> &ISDArgs) const {
543  const DataLayout &DL = F.getParent()->getDataLayout();
544  const MipsTargetLowering &TLI = *getTLI<MipsTargetLowering>();
545 
546  unsigned ArgNo = 0;
547  for (auto &Arg : Args) {
548 
549  EVT VT = TLI.getValueType(DL, Arg.Ty);
550  MVT RegisterVT = TLI.getRegisterTypeForCallingConv(F.getContext(),
551  F.getCallingConv(), VT);
552  unsigned NumRegs = TLI.getNumRegistersForCallingConv(
553  F.getContext(), F.getCallingConv(), VT);
554 
555  for (unsigned i = 0; i < NumRegs; ++i) {
556  ISD::ArgFlagsTy Flags = Arg.Flags;
557 
558  if (i == 0)
560  else
561  Flags.setOrigAlign(1);
562 
563  ISDArgs.emplace_back(Flags, RegisterVT, VT, true, OrigArgIndices[ArgNo],
564  0);
565  }
566  ++ArgNo;
567  }
568 }
569 
570 void MipsCallLowering::splitToValueTypes(
571  const ArgInfo &OrigArg, unsigned OriginalIndex,
572  SmallVectorImpl<ArgInfo> &SplitArgs,
573  SmallVectorImpl<unsigned> &SplitArgsOrigIndices) const {
574 
575  // TODO : perform structure and array split. For now we only deal with
576  // types that pass isSupportedType check.
577  SplitArgs.push_back(OrigArg);
578  SplitArgsOrigIndices.push_back(OriginalIndex);
579 }
bool isVarArg() const
isVarArg - Return true if this function takes a variable number of arguments.
Definition: Function.h:177
const MachineInstrBuilder & add(const MachineOperand &MO) const
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:111
C - The default llvm calling convention, compatible with C.
Definition: CallingConv.h:35
This class represents lattice values for constants.
Definition: AllocatorList.h:24
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
void push_back(const T &Elt)
Definition: SmallVector.h:218
unsigned Reg
unsigned getValNo() const
unsigned const TargetRegisterInfo * TRI
F(f)
uint64_t alignTo(uint64_t Value, uint64_t Align, uint64_t Skew=0)
Returns the next integer (mod 2**64) that is greater than or equal to Value and is a multiple of Alig...
Definition: MathExtras.h:685
LLVMContext & getContext() const
Return the LLVMContext in which this type was uniqued.
Definition: Type.h:130
bool isMemLoc() const
A description of a memory reference used in the backend.
const DataLayout & getDataLayout() const
Get the data layout for the module&#39;s target platform.
Definition: Module.cpp:371
CCAssignFn * CCAssignFnForCall() const
bool isIntegerTy() const
True if this is an instance of IntegerType.
Definition: Type.h:197
unsigned GetCalleeAllocdArgSizeInBytes(CallingConv::ID CC) const
Obtain the size of the area allocated by the callee for arguments.
Definition: MipsABIInfo.cpp:49
MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const override
Return the register type for a given MVT, ensuring vectors are treated as a series of gpr sized integ...
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
bool assignVRegs(ArrayRef< unsigned > VRegs, ArrayRef< CCValAssign > ArgLocs, unsigned Index)
const char * getSymbolName() const
LocInfo getLocInfo() const
unsigned getSizeInBits() const
auto reverse(ContainerTy &&C, typename std::enable_if< has_rbegin< ContainerTy >::value >::type *=nullptr) -> decltype(make_range(C.rbegin(), C.rend()))
Definition: STLExtras.h:267
unsigned getSizeInBits() const
Return the size of the specified value type in bits.
Definition: ValueTypes.h:292
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:245
unsigned getABIAlignmentForCallingConv(Type *ArgTy, DataLayout DL) const override
Return the correct alignment for the current calling convention.
bool arg_empty() const
Definition: Function.h:699
MachineInstrBuilder buildInstrNoInsert(unsigned Opcode)
Build but don&#39;t insert <empty> = Opcode <empty>.
MachineFunction & getMF()
Getter for the function we currently build.
void AnalyzeCallResult(const SmallVectorImpl< ISD::InputArg > &Ins, CCAssignFn Fn, const Type *RetTy, const char *Func)
Definition: MipsCCState.h:120
static LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
MipsCallLowering(const MipsTargetLowering &TLI)
void setOrigAlign(unsigned A)
void ComputeValueVTs(const TargetLowering &TLI, const DataLayout &DL, Type *Ty, SmallVectorImpl< EVT > &ValueVTs, SmallVectorImpl< uint64_t > *Offsets=nullptr, uint64_t StartingOffset=0)
ComputeValueVTs - Given an LLVM IR type, compute a sequence of EVTs that represent all the individual...
Definition: Analysis.cpp:84
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
static CCValAssign getReg(unsigned ValNo, MVT ValVT, unsigned RegNo, MVT LocVT, LocInfo HTP)
virtual const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const
Return a mask of call-preserved registers for the given calling convention on the current function...
void addLiveIn(MCPhysReg PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
unsigned const MachineRegisterInfo * MRI
Machine Value Type.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:46
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:69
MachineInstrBuilder buildInstr(unsigned Opcode)
Build and insert <empty> = Opcode <empty>.
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:149
LLVM_ATTRIBUTE_ALWAYS_INLINE iterator begin()
Definition: SmallVector.h:129
bool lowerFormalArguments(MachineIRBuilder &MIRBuilder, const Function &F, ArrayRef< unsigned > VRegs) const override
This hook must be implemented to lower the incoming (formal) arguments, described by Args...
bool isPointerTy() const
True if this is an instance of PointerType.
Definition: Type.h:224
Helper class to build MachineInstr.
AMDGPU Lower Kernel Arguments
void setLeastSignificantFirst(SmallVectorImpl< unsigned > &VRegs)
const MachineInstrBuilder & addRegMask(const uint32_t *Mask) const
static void setLocInfo(SmallVectorImpl< CCValAssign > &ArgLocs, const SmallVectorImpl< T > &Arguments)
void setArgFlags(ArgInfo &Arg, unsigned OpIdx, const DataLayout &DL, const FuncInfoTy &FuncInfo) const
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function. ...
Definition: Function.cpp:193
std::vector< ArgListEntry > ArgListTy
Extended Value Type.
Definition: ValueTypes.h:34
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
size_t size() const
Definition: SmallVector.h:53
This class contains a discriminated union of information about pointers in memory operands...
unsigned getStackAlignment() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
EVT getValueType(const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const
Return the EVT corresponding to this LLVM type.
The memory access writes data.
unsigned getNumRegistersForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const override
Return the number of registers for a given MVT, ensuring vectors are treated as a series of gpr sized...
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:213
MachineOperand class - Representation of each machine instruction operand.
CCValAssign - Represent assignment of one arg/retval to a location.
Information about stack frame layout on the target.
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool IsImmutable, bool isAliased=false)
Create a new object at a fixed location on the stack.
const Function & getFunction() const
Return the LLVM function that this machine code represents.
This file declares the MachineIRBuilder class.
amdgpu Simplify well known AMD library false Value Value * Arg
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
The memory access reads data.
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
void AnalyzeReturn(const SmallVectorImpl< ISD::OutputArg > &Outs, CCAssignFn Fn)
Definition: MipsCCState.h:131
LLVM_ATTRIBUTE_ALWAYS_INLINE iterator end()
Definition: SmallVector.h:133
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
bool lowerReturn(MachineIRBuilder &MIRBuilder, const Value *Val, ArrayRef< unsigned > VRegs) const override
This hook must be implemented to lower outgoing return values, described by Val, into the specified v...
void emplace_back(ArgTypes &&... Args)
Definition: SmallVector.h:652
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
unsigned getLocMemOffset() const
const MachineBasicBlock & getMBB() const
Getter for the basic block we currently build.
virtual const TargetFrameLowering * getFrameLowering() const
uint32_t Size
Definition: Profile.cpp:47
static CCValAssign getMem(unsigned ValNo, MVT ValVT, unsigned Offset, MVT LocVT, LocInfo HTP)
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
bool isSymbol() const
isSymbol - Tests if this is a MO_ExternalSymbol operand.
This file describes how to lower LLVM calls to machine code calls.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
bool isRegLoc() const
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static bool isSupportedType(Type *T)
MachineInstrBuilder insertInstr(MachineInstrBuilder MIB)
Insert an existing instruction at the insertion point.
Module * getParent()
Get the module that this global value is contained inside of...
Definition: GlobalValue.h:566
LLVM Value Representation.
Definition: Value.h:73
static LLT pointer(uint16_t AddressSpace, unsigned SizeInBits)
Get a low-level pointer in the given address space (defaulting to 0).
bool lowerCall(MachineIRBuilder &MIRBuilder, CallingConv::ID CallConv, const MachineOperand &Callee, const ArgInfo &OrigRet, ArrayRef< ArgInfo > OrigArgs) const override
This hook must be implemented to lower the given call instruction, including argument and return valu...
MachineInstrBuilder buildLoad(unsigned Res, unsigned Addr, MachineMemOperand &MMO)
Build and insert Res = G_LOAD Addr, MMO.
CCAssignFn * CCAssignFnForReturn() const
static MachinePointerInfo getStack(MachineFunction &MF, int64_t Offset, uint8_t ID=0)
Stack pointer relative access.
static CCValAssign::LocInfo determineLocInfo(const MVT RegisterVT, const EVT VT, const ISD::ArgFlagsTy &Flags)
const MachineInstrBuilder & addDef(unsigned RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register definition operand.
unsigned getLocReg() const
unsigned AllocateStack(unsigned Size, unsigned Align)
AllocateStack - Allocate a chunk of stack space with the specified size and alignment.
constexpr char Args[]
Key for Kernel::Metadata::mArgs.
bool handle(ArrayRef< CCValAssign > ArgLocs, ArrayRef< CallLowering::ArgInfo > Args)
iterator_range< arg_iterator > args()
Definition: Function.h:689
bool empty() const
empty - Check if the array is empty.
Definition: ArrayRef.h:144