This pass removes redundant S_OR_B64 instructions enabling lanes in the exec. More...
#include "AMDGPU.h"#include "AMDGPUSubtarget.h"#include "SIInstrInfo.h"#include "MCTargetDesc/AMDGPUMCTargetDesc.h"#include "llvm/CodeGen/LiveIntervals.h"#include "llvm/CodeGen/MachineFunctionPass.h"
Go to the source code of this file.
Macros | |
| #define | DEBUG_TYPE "si-optimize-exec-masking-pre-ra" |
Functions | |
| INITIALIZE_PASS_BEGIN (SIOptimizeExecMaskingPreRA, DEBUG_TYPE, "SI optimize exec mask operations pre-RA", false, false) INITIALIZE_PASS_END(SIOptimizeExecMaskingPreRA | |
| static bool | isEndCF (const MachineInstr &MI, const SIRegisterInfo *TRI) |
| static bool | isFullExecCopy (const MachineInstr &MI) |
| static unsigned | getOrNonExecReg (const MachineInstr &MI, const SIInstrInfo &TII) |
| static MachineInstr * | getOrExecSource (const MachineInstr &MI, const SIInstrInfo &TII, const MachineRegisterInfo &MRI) |
| static unsigned | optimizeVcndVcmpPair (MachineBasicBlock &MBB, const GCNSubtarget &ST, MachineRegisterInfo &MRI, LiveIntervals *LIS) |
Variables | |
| DEBUG_TYPE | |
| SI optimize exec mask operations pre | RA |
| SI optimize exec mask operations pre | false |
Detailed Description
This pass removes redundant S_OR_B64 instructions enabling lanes in the exec.
If two SI_END_CF (lowered as S_OR_B64) come together without any vector instructions between them we can only keep outer SI_END_CF, given that CFG is structured and exec bits of the outer end statement are always not less than exec bit of the inner one.
This needs to be done before the RA to eliminate saved exec bits registers but after register coalescer to have no vector registers copies in between of different end cf statements.
Definition in file SIOptimizeExecMaskingPreRA.cpp.
Macro Definition Documentation
◆ DEBUG_TYPE
| #define DEBUG_TYPE "si-optimize-exec-masking-pre-ra" |
Definition at line 32 of file SIOptimizeExecMaskingPreRA.cpp.
Function Documentation
◆ getOrExecSource()
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static |
Definition at line 94 of file SIOptimizeExecMaskingPreRA.cpp.
References getOrNonExecReg(), llvm::MachineRegisterInfo::getUniqueVRegDef(), and isFullExecCopy().
Referenced by optimizeVcndVcmpPair().
◆ getOrNonExecReg()
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static |
Definition at line 83 of file SIOptimizeExecMaskingPreRA.cpp.
References llvm::SIInstrInfo::getNamedOperand().
Referenced by getOrExecSource(), and optimizeVcndVcmpPair().
◆ INITIALIZE_PASS_BEGIN()
| INITIALIZE_PASS_BEGIN | ( | SIOptimizeExecMaskingPreRA | , |
| DEBUG_TYPE | , | ||
| "SI optimize exec mask operations pre-RA" | , | ||
| false | , | ||
| false | |||
| ) |
◆ isEndCF()
|
static |
Definition at line 74 of file SIOptimizeExecMaskingPreRA.cpp.
References llvm::MachineInstr::getOpcode(), and llvm::MachineInstr::modifiesRegister().
Referenced by optimizeVcndVcmpPair().
◆ isFullExecCopy()
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static |
Definition at line 79 of file SIOptimizeExecMaskingPreRA.cpp.
References llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), and llvm::MachineInstr::isFullCopy().
Referenced by getOrExecSource().
◆ optimizeVcndVcmpPair()
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static |
Definition at line 122 of file SIOptimizeExecMaskingPreRA.cpp.
References llvm::MachineInstrBuilder::addReg(), llvm::MachineBasicBlock::begin(), llvm::BuildMI(), llvm::LiveIntervals::createAndComputeVirtRegInterval(), llvm::dbgs(), E, llvm::MachineBasicBlock::end(), llvm::MachineInstr::eraseFromParent(), llvm::find_if(), llvm::SIRegisterInfo::findReachingDef(), llvm::MachineFunction::getFunction(), llvm::MachineOperand::getImm(), llvm::GCNSubtarget::getInstrInfo(), llvm::ilist_node_impl< OptionsT >::getIterator(), llvm::SIInstrInfo::getNamedOperand(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOpcode(), getOrExecSource(), getOrNonExecReg(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), llvm::GCNSubtarget::getRegisterInfo(), llvm::MachineOperand::getSubReg(), llvm::MachineFunction::getSubtarget(), I, llvm::detail::DenseSetImpl< ValueT, MapTy, ValueInfoT >::insert(), llvm::LiveIntervals::InsertMachineInstrInMaps(), isEndCF(), llvm::MachineOperand::isImm(), llvm::MachineOperand::isReg(), llvm::SIInstrInfo::isSALU(), llvm::MCRegisterInfo::DiffListIterator::isValid(), llvm::TargetRegisterInfo::isVirtualRegister(), LLVM_DEBUG, MI, MRI, llvm::none_of(), llvm::SmallVectorImpl< T >::pop_back_val(), Reg, llvm::MachineRegisterInfo::reg_empty(), llvm::LiveIntervals::removeInterval(), llvm::LiveIntervals::RemoveMachineInstrFromMaps(), llvm::LiveIntervals::removeRegUnit(), llvm::MachineRegisterInfo::replaceRegWith(), llvm::ARM_MB::ST, llvm::MachineBasicBlock::succ_begin(), std::swap(), llvm::MachineBasicBlock::terminators(), TII, TRI, and llvm::MachineRegisterInfo::use_nodbg_instructions().
Variable Documentation
◆ DEBUG_TYPE
| DEBUG_TYPE |
Definition at line 63 of file SIOptimizeExecMaskingPreRA.cpp.
◆ false
| SI optimize exec mask operations pre false |
Definition at line 63 of file SIOptimizeExecMaskingPreRA.cpp.
◆ RA
| SI optimize exec mask operations pre RA |
Definition at line 63 of file SIOptimizeExecMaskingPreRA.cpp.
Referenced by addLiveInRegs(), addSaveRestoreRegs(), BrPHIToSelect(), llvm::rdf::DataFlowGraph::build(), CC_MipsO32_FP64(), CheckXWPInstr(), llvm::FunctionComparator::cmpConstants(), llvm::FunctionComparator::cmpMem(), llvm::rdf::DeadCodeElimination::collect(), CompareSCEVComplexity(), CompareValueComplexity(), llvm::SelectionDAG::computeKnownBits(), computeKnownBitsFromOperator(), llvm::rdf::Liveness::computeLiveIns(), ConsecutiveRegisters(), countMCSymbolRefExpr(), createMipsMCRegisterInfo(), createPPCMCRegisterInfo(), createX86MCRegisterInfo(), DecodeRegListOperand(), DecodeRegListOperand16(), llvm::MipsAsmPrinter::EmitStartOfAsmFile(), llvm::rdf::DeadCodeElimination::erase(), llvm::rdf::PhysicalRegisterInfo::getAliasSet(), getExactSDiv(), llvm::rdf::RefNode::getNextRef(), llvm::rdf::DataFlowGraph::getNextRelated(), llvm::rdf::DataFlowGraph::getNextShadow(), getRegisterForMxtrC0(), getRegisterForMxtrFP(), llvm::MipsRegisterInfo::getReservedRegs(), getRetComponentType(), llvm::rdf::PhysicalRegisterInfo::getTRI(), llvm::rdf::DataFlowGraph::id(), INITIALIZE_PASS(), llvm::MCRegisterInfo::InitMCRegisterInfo(), llvm::rdf::CopyPropagation::interpretAsCopy(), llvm::MipsSEInstrInfo::loadImmediate(), lowerFCOPYSIGN64(), nextReg(), DeadCodeElimination::SetQueue< T >::push_back(), RefineErrorLoc(), ShrinkDemandedConstant(), llvm::ScalarEvolution::SimplifyICmpOperands(), llvm::Mips16FrameLowering::spillCalleeSavedRegisters(), llvm::MipsSEFrameLowering::spillCalleeSavedRegisters(), and llvm::rdf::DataFlowGraph::unpack().
