10 #ifndef LLVM_LIB_TARGET_HEXAGON_RDFREGISTERS_H 11 #define LLVM_LIB_TARGET_HEXAGON_RDFREGISTERS_H 25 class MachineFunction;
36 template <
typename T,
unsigned N = 32>
42 assert(Idx != 0 && !Map.empty() && Idx-1 < Map.size());
50 return F - Map.begin() + 1;
58 return F - Map.begin() + 1;
78 : Reg(R), Mask(R != 0 ? M :
LaneBitmask::getNone()) {}
81 return Reg != 0 && Mask.
any();
85 return Reg == RR.
Reg && Mask == RR.
Mask;
93 return Reg < RR.
Reg || (Reg == RR.
Reg && Mask < RR.
Mask);
117 if (!isRegMaskId(RA.
Reg))
118 return !isRegMaskId(RB.
Reg) ? aliasRR(RA, RB) : aliasRM(RA, RB);
119 return !isRegMaskId(RB.
Reg) ? aliasRM(RB, RA) : aliasMM(RA, RB);
122 std::set<RegisterId> getAliasSet(
RegisterId Reg)
const;
125 return RegisterRef(UnitInfos[U].Reg, UnitInfos[U].Mask);
149 std::vector<RegInfo> RegInfos;
150 std::vector<UnitInfo> UnitInfos;
151 std::vector<MaskInfo> MaskInfos;
160 : Units(pri.getTRI().getNumRegUnits()), PRI(pri) {}
163 bool empty()
const {
return Units.none(); }
186 using MapType = std::map<RegisterId, LaneBitmask>;
190 MapType::iterator Pos;
210 return Index == I.Index;
214 return !(*
this ==
I);
241 #endif // LLVM_LIB_TARGET_HEXAGON_RDFREGISTERS_H bool hasCoverOf(RegisterRef RR) const
raw_ostream & operator<<(raw_ostream &OS, const PrintLaneMaskOpt &P)
A common definition of LaneBitmask for use in TableGen and CodeGen.
PrintLaneMaskOpt(LaneBitmask M)
This class represents lattice values for constants.
bool operator!=(const rr_iterator &I) const
unsigned const TargetRegisterInfo * TRI
RegisterRef(RegisterId R, LaneBitmask M=LaneBitmask::getAll())
rr_iterator rr_begin() const
SI optimize exec mask operations pre RA
static int stackSlot2Index(unsigned Reg)
Compute the frame index from a register value representing a stack slot.
const BitVector & getMaskUnits(RegisterId MaskId) const
static constexpr LaneBitmask getAll()
static constexpr LaneBitmask getNone()
uint32_t find(T Val) const
const_iterator end() const
std::map< RegisterId, LaneBitmask > MapType
const TargetRegisterInfo & getTRI() const
rr_iterator rr_end() const
static void print(raw_ostream &Out, object::Archive::Kind Kind, T Val)
RegisterRef getRefForUnit(uint32_t U) const
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
auto find(R &&Range, const T &Val) -> decltype(adl_begin(Range))
Provide wrappers to std::find which take ranges instead of having to pass begin/end explicitly...
static bool isStackSlot(unsigned Reg)
isStackSlot - Sometimes it is useful the be able to store a non-negative frame index in a variable th...
RegisterAggr & insert(RegisterRef RR)
RegisterAggr(const PhysicalRegisterInfo &pri)
RegisterRef operator*() const
rr_iterator & operator++()
bool operator==(const rr_iterator &I) const
static void clear(coro::Shape &Shape)
bool operator!=(uint64_t V1, const APInt &V2)
static ValueLatticeElement intersect(const ValueLatticeElement &A, const ValueLatticeElement &B)
Combine two sets of facts about the same value into a single set of facts.
RegisterId getRegMaskId(const uint32_t *RM) const
constexpr bool any() const
typename std::vector< const uint32_t * >::const_iterator const_iterator
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool alias(RegisterRef RA, RegisterRef RB) const
static bool isRegMaskId(RegisterId R)
static bool isCoverOf(RegisterRef RA, RegisterRef RB, const PhysicalRegisterInfo &PRI)
bool operator<(int64_t V1, const APSInt &V2)
const uint32_t * getRegMaskBits(RegisterId R) const
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
This class implements an extremely fast bulk output stream that can only output to a stream...
bool operator==(uint64_t V1, const APInt &V2)
static unsigned index2StackSlot(int FI)
Convert a non-negative frame index to a stack slot register value.
const_iterator begin() const