LLVM  8.0.1
RDFRegisters.h
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1 //===- RDFRegisters.h -------------------------------------------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
10 #ifndef LLVM_LIB_TARGET_HEXAGON_RDFREGISTERS_H
11 #define LLVM_LIB_TARGET_HEXAGON_RDFREGISTERS_H
12 
13 #include "llvm/ADT/BitVector.h"
14 #include "llvm/ADT/STLExtras.h"
16 #include "llvm/MC/LaneBitmask.h"
17 #include <cassert>
18 #include <cstdint>
19 #include <map>
20 #include <set>
21 #include <vector>
22 
23 namespace llvm {
24 
25 class MachineFunction;
26 class raw_ostream;
27 
28 namespace rdf {
29 
31 
32  // Template class for a map translating uint32_t into arbitrary types.
33  // The map will act like an indexed set: upon insertion of a new object,
34  // it will automatically assign a new index to it. Index of 0 is treated
35  // as invalid and is never allocated.
36  template <typename T, unsigned N = 32>
37  struct IndexedSet {
38  IndexedSet() { Map.reserve(N); }
39 
40  T get(uint32_t Idx) const {
41  // Index Idx corresponds to Map[Idx-1].
42  assert(Idx != 0 && !Map.empty() && Idx-1 < Map.size());
43  return Map[Idx-1];
44  }
45 
46  uint32_t insert(T Val) {
47  // Linear search.
48  auto F = llvm::find(Map, Val);
49  if (F != Map.end())
50  return F - Map.begin() + 1;
51  Map.push_back(Val);
52  return Map.size(); // Return actual_index + 1.
53  }
54 
55  uint32_t find(T Val) const {
56  auto F = llvm::find(Map, Val);
57  assert(F != Map.end());
58  return F - Map.begin() + 1;
59  }
60 
61  uint32_t size() const { return Map.size(); }
62 
63  using const_iterator = typename std::vector<T>::const_iterator;
64 
65  const_iterator begin() const { return Map.begin(); }
66  const_iterator end() const { return Map.end(); }
67 
68  private:
69  std::vector<T> Map;
70  };
71 
72  struct RegisterRef {
75 
76  RegisterRef() = default;
78  : Reg(R), Mask(R != 0 ? M : LaneBitmask::getNone()) {}
79 
80  operator bool() const {
81  return Reg != 0 && Mask.any();
82  }
83 
84  bool operator== (const RegisterRef &RR) const {
85  return Reg == RR.Reg && Mask == RR.Mask;
86  }
87 
88  bool operator!= (const RegisterRef &RR) const {
89  return !operator==(RR);
90  }
91 
92  bool operator< (const RegisterRef &RR) const {
93  return Reg < RR.Reg || (Reg == RR.Reg && Mask < RR.Mask);
94  }
95  };
96 
97 
100  const MachineFunction &mf);
101 
102  static bool isRegMaskId(RegisterId R) {
104  }
105 
107  return TargetRegisterInfo::index2StackSlot(RegMasks.find(RM));
108  }
109 
111  return RegMasks.get(TargetRegisterInfo::stackSlot2Index(R));
112  }
113 
114  RegisterRef normalize(RegisterRef RR) const;
115 
116  bool alias(RegisterRef RA, RegisterRef RB) const {
117  if (!isRegMaskId(RA.Reg))
118  return !isRegMaskId(RB.Reg) ? aliasRR(RA, RB) : aliasRM(RA, RB);
119  return !isRegMaskId(RB.Reg) ? aliasRM(RB, RA) : aliasMM(RA, RB);
120  }
121 
122  std::set<RegisterId> getAliasSet(RegisterId Reg) const;
123 
125  return RegisterRef(UnitInfos[U].Reg, UnitInfos[U].Mask);
126  }
127 
128  const BitVector &getMaskUnits(RegisterId MaskId) const {
129  return MaskInfos[TargetRegisterInfo::stackSlot2Index(MaskId)].Units;
130  }
131 
132  RegisterRef mapTo(RegisterRef RR, unsigned R) const;
133  const TargetRegisterInfo &getTRI() const { return TRI; }
134 
135  private:
136  struct RegInfo {
137  const TargetRegisterClass *RegClass = nullptr;
138  };
139  struct UnitInfo {
140  RegisterId Reg = 0;
142  };
143  struct MaskInfo {
144  BitVector Units;
145  };
146 
147  const TargetRegisterInfo &TRI;
149  std::vector<RegInfo> RegInfos;
150  std::vector<UnitInfo> UnitInfos;
151  std::vector<MaskInfo> MaskInfos;
152 
153  bool aliasRR(RegisterRef RA, RegisterRef RB) const;
154  bool aliasRM(RegisterRef RR, RegisterRef RM) const;
155  bool aliasMM(RegisterRef RM, RegisterRef RN) const;
156  };
157 
158  struct RegisterAggr {
160  : Units(pri.getTRI().getNumRegUnits()), PRI(pri) {}
161  RegisterAggr(const RegisterAggr &RG) = default;
162 
163  bool empty() const { return Units.none(); }
164  bool hasAliasOf(RegisterRef RR) const;
165  bool hasCoverOf(RegisterRef RR) const;
166 
168  const PhysicalRegisterInfo &PRI) {
169  return RegisterAggr(PRI).insert(RA).hasCoverOf(RB);
170  }
171 
173  RegisterAggr &insert(const RegisterAggr &RG);
175  RegisterAggr &intersect(const RegisterAggr &RG);
177  RegisterAggr &clear(const RegisterAggr &RG);
178 
179  RegisterRef intersectWith(RegisterRef RR) const;
180  RegisterRef clearIn(RegisterRef RR) const;
181  RegisterRef makeRegRef() const;
182 
183  void print(raw_ostream &OS) const;
184 
185  struct rr_iterator {
186  using MapType = std::map<RegisterId, LaneBitmask>;
187 
188  private:
189  MapType Masks;
190  MapType::iterator Pos;
191  unsigned Index;
192  const RegisterAggr *Owner;
193 
194  public:
195  rr_iterator(const RegisterAggr &RG, bool End);
196 
198  return RegisterRef(Pos->first, Pos->second);
199  }
200 
202  ++Pos;
203  ++Index;
204  return *this;
205  }
206 
207  bool operator==(const rr_iterator &I) const {
208  assert(Owner == I.Owner);
209  (void)Owner;
210  return Index == I.Index;
211  }
212 
213  bool operator!=(const rr_iterator &I) const {
214  return !(*this == I);
215  }
216  };
217 
219  return rr_iterator(*this, false);
220  }
221  rr_iterator rr_end() const {
222  return rr_iterator(*this, true);
223  }
224 
225  private:
226  BitVector Units;
227  const PhysicalRegisterInfo &PRI;
228  };
229 
230  // Optionally print the lane mask, if it is not ~0.
234  };
236 
237 } // end namespace rdf
238 
239 } // end namespace llvm
240 
241 #endif // LLVM_LIB_TARGET_HEXAGON_RDFREGISTERS_H
bool hasCoverOf(RegisterRef RR) const
raw_ostream & operator<<(raw_ostream &OS, const PrintLaneMaskOpt &P)
Definition: RDFGraph.cpp:52
A common definition of LaneBitmask for use in TableGen and CodeGen.
PrintLaneMaskOpt(LaneBitmask M)
Definition: RDFRegisters.h:232
This class represents lattice values for constants.
Definition: AllocatorList.h:24
unsigned Reg
bool operator!=(const rr_iterator &I) const
Definition: RDFRegisters.h:213
unsigned const TargetRegisterInfo * TRI
F(f)
RegisterRef(RegisterId R, LaneBitmask M=LaneBitmask::getAll())
Definition: RDFRegisters.h:77
rr_iterator rr_begin() const
Definition: RDFRegisters.h:218
SI optimize exec mask operations pre RA
static int stackSlot2Index(unsigned Reg)
Compute the frame index from a register value representing a stack slot.
const BitVector & getMaskUnits(RegisterId MaskId) const
Definition: RDFRegisters.h:128
static constexpr LaneBitmask getAll()
Definition: LaneBitmask.h:84
static constexpr LaneBitmask getNone()
Definition: LaneBitmask.h:83
uint32_t find(T Val) const
Definition: RDFRegisters.h:55
uint32_t size() const
Definition: RDFRegisters.h:61
const_iterator end() const
Definition: RDFRegisters.h:66
uint32_t insert(T Val)
Definition: RDFRegisters.h:46
std::map< RegisterId, LaneBitmask > MapType
Definition: RDFRegisters.h:186
#define P(N)
const TargetRegisterInfo & getTRI() const
Definition: RDFRegisters.h:133
rr_iterator rr_end() const
Definition: RDFRegisters.h:221
static void print(raw_ostream &Out, object::Archive::Kind Kind, T Val)
RegisterRef getRefForUnit(uint32_t U) const
Definition: RDFRegisters.h:124
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
auto find(R &&Range, const T &Val) -> decltype(adl_begin(Range))
Provide wrappers to std::find which take ranges instead of having to pass begin/end explicitly...
Definition: STLExtras.h:1207
static bool isStackSlot(unsigned Reg)
isStackSlot - Sometimes it is useful the be able to store a non-negative frame index in a variable th...
RegisterAggr & insert(RegisterRef RR)
RegisterAggr(const PhysicalRegisterInfo &pri)
Definition: RDFRegisters.h:159
bool operator==(const rr_iterator &I) const
Definition: RDFRegisters.h:207
static void clear(coro::Shape &Shape)
Definition: Coroutines.cpp:212
bool operator!=(uint64_t V1, const APInt &V2)
Definition: APInt.h:1969
static ValueLatticeElement intersect(const ValueLatticeElement &A, const ValueLatticeElement &B)
Combine two sets of facts about the same value into a single set of facts.
RegisterId getRegMaskId(const uint32_t *RM) const
Definition: RDFRegisters.h:106
#define I(x, y, z)
Definition: MD5.cpp:58
#define N
constexpr bool any() const
Definition: LaneBitmask.h:53
typename std::vector< const uint32_t * >::const_iterator const_iterator
Definition: RDFRegisters.h:63
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool alias(RegisterRef RA, RegisterRef RB) const
Definition: RDFRegisters.h:116
static bool isRegMaskId(RegisterId R)
Definition: RDFRegisters.h:102
static bool isCoverOf(RegisterRef RA, RegisterRef RB, const PhysicalRegisterInfo &PRI)
Definition: RDFRegisters.h:167
bool operator<(int64_t V1, const APSInt &V2)
Definition: APSInt.h:326
const uint32_t * getRegMaskBits(RegisterId R) const
Definition: RDFRegisters.h:110
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:81
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:46
bool operator==(uint64_t V1, const APInt &V2)
Definition: APInt.h:1967
static unsigned index2StackSlot(int FI)
Convert a non-negative frame index to a stack slot register value.
const_iterator begin() const
Definition: RDFRegisters.h:65