#include "Target/X86/X86ISelLowering.h"
Public Member Functions | |
| X86TargetLowering (const X86TargetMachine &TM, const X86Subtarget &STI) | |
| unsigned | getJumpTableEncoding () const override |
| Return the entry encoding for a jump table in the current function. More... | |
| bool | useSoftFloat () const override |
| void | markLibCallAttributes (MachineFunction *MF, unsigned CC, ArgListTy &Args) const override |
| MVT | getScalarShiftAmountTy (const DataLayout &, EVT VT) const override |
| EVT is not used in-tree, but is used by out-of-tree target. More... | |
| const MCExpr * | LowerCustomJumpTableEntry (const MachineJumpTableInfo *MJTI, const MachineBasicBlock *MBB, unsigned uid, MCContext &Ctx) const override |
| SDValue | getPICJumpTableRelocBase (SDValue Table, SelectionDAG &DAG) const override |
| Returns relocation base for the given PIC jumptable. More... | |
| const MCExpr * | getPICJumpTableRelocBaseExpr (const MachineFunction *MF, unsigned JTI, MCContext &Ctx) const override |
| This returns the relocation base for the given PIC jumptable, the same as getPICJumpTableRelocBase, but as an MCExpr. More... | |
| unsigned | getByValTypeAlignment (Type *Ty, const DataLayout &DL) const override |
| Return the desired alignment for ByVal aggregate function arguments in the caller parameter area. More... | |
| EVT | getOptimalMemOpType (uint64_t Size, unsigned DstAlign, unsigned SrcAlign, bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc, MachineFunction &MF) const override |
| Returns the target specific optimal type for load and store operations as a result of memset, memcpy, and memmove lowering. More... | |
| bool | isSafeMemOpType (MVT VT) const override |
| Returns true if it's safe to use load / store of the specified type to expand memcpy / memset inline. More... | |
| bool | allowsMisalignedMemoryAccesses (EVT VT, unsigned AS, unsigned Align, bool *Fast) const override |
| Returns true if the target allows unaligned memory accesses of the specified type. More... | |
| SDValue | LowerOperation (SDValue Op, SelectionDAG &DAG) const override |
| Provide custom lowering hooks for some operations. More... | |
| void | LowerOperationWrapper (SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override |
| Places new result values for the node in Results (their number and types must exactly match those of the original return values of the node), or leaves Results empty, which indicates that the node is not to be custom lowered after all. More... | |
| void | ReplaceNodeResults (SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override |
| Replace the results of node with an illegal result type with new values built out of custom code. More... | |
| SDValue | PerformDAGCombine (SDNode *N, DAGCombinerInfo &DCI) const override |
| This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for. More... | |
| bool | isDesirableToCombineBuildVectorToShuffleTruncate (ArrayRef< int > ShuffleMask, EVT SrcVT, EVT TruncVT) const override |
| bool | isTypeDesirableForOp (unsigned Opc, EVT VT) const override |
| Return true if the target has native support for the specified value type and it is 'desirable' to use the type for the given node type. More... | |
| bool | IsDesirableToPromoteOp (SDValue Op, EVT &PVT) const override |
| Return true if the target has native support for the specified value type and it is 'desirable' to use the type. More... | |
| MachineBasicBlock * | EmitInstrWithCustomInserter (MachineInstr &MI, MachineBasicBlock *MBB) const override |
| This method should be implemented by targets that mark instructions with the 'usesCustomInserter' flag. More... | |
| const char * | getTargetNodeName (unsigned Opcode) const override |
| This method returns the name of a target specific DAG node. More... | |
| bool | mergeStoresAfterLegalization () const override |
| Allow store merging after legalization in addition to before legalization. More... | |
| bool | canMergeStoresTo (unsigned AddressSpace, EVT MemVT, const SelectionDAG &DAG) const override |
| Returns if it's reasonable to merge stores to MemVT size. More... | |
| bool | isCheapToSpeculateCttz () const override |
| Return true if it is cheap to speculate a call to intrinsic cttz. More... | |
| bool | isCheapToSpeculateCtlz () const override |
| Return true if it is cheap to speculate a call to intrinsic ctlz. More... | |
| bool | isCtlzFast () const override |
| Return true if ctlz instruction is fast. More... | |
| bool | hasBitPreservingFPLogic (EVT VT) const override |
| Return true if it is safe to transform an integer-domain bitwise operation into the equivalent floating-point operation. More... | |
| bool | isMultiStoresCheaperThanBitsMerge (EVT LTy, EVT HTy) const override |
| Return true if it is cheaper to split the store of a merged int val from a pair of smaller values into multiple stores. More... | |
| bool | isMaskAndCmp0FoldingBeneficial (const Instruction &AndI) const override |
| Return if the target supports combining a chain like: More... | |
| bool | hasAndNotCompare (SDValue Y) const override |
| Return true if the target should transform: (X & Y) == Y —> (~X & Y) == 0 (X & Y) != Y —> (~X & Y) != 0. More... | |
| bool | hasAndNot (SDValue Y) const override |
| Return true if the target has a bitwise and-not operation: X = ~A & B This can be used to simplify select or other instructions. More... | |
| bool | preferShiftsToClearExtremeBits (SDValue Y) const override |
| There are two ways to clear extreme bits (either low or high): Mask: x & (-1 << y) (the instcombine canonical form) Shifts: x >> y << y Return true if the variant with 2 shifts is preferred. More... | |
| bool | shouldTransformSignedTruncationCheck (EVT XVT, unsigned KeptBits) const override |
| Should we tranform the IR-optimal check for whether given truncation down into KeptBits would be truncating or not: (add x, (1 << (KeptBits-1))) srccond (1 << KeptBits) Into it's more traditional form: ((x << C) a>> C) dstcond x Return true if we should transform. More... | |
| bool | shouldSplatInsEltVarIndex (EVT VT) const override |
| Return true if inserting a scalar into a variable element of an undef vector is more efficiently handled by splatting the scalar instead. More... | |
| bool | convertSetCCLogicToBitwiseLogic (EVT VT) const override |
| Use bitwise logic to make pairs of compares more efficient. More... | |
| MVT | hasFastEqualityCompare (unsigned NumBits) const override |
| Vector-sized comparisons are fast using PCMPEQ + PMOVMSK or PTEST. More... | |
| unsigned | getMemcmpEqZeroLoadsPerBlock () const override |
| Allow multiple load pairs per block for smaller and faster code. More... | |
| EVT | getSetCCResultType (const DataLayout &DL, LLVMContext &Context, EVT VT) const override |
| Return the value type to use for ISD::SETCC. More... | |
| bool | targetShrinkDemandedConstant (SDValue Op, const APInt &Demanded, TargetLoweringOpt &TLO) const override |
| void | computeKnownBitsForTargetNode (const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth=0) const override |
| Determine which of the bits specified in Mask are known to be either zero or one and return them in the KnownZero/KnownOne bitsets. More... | |
| unsigned | ComputeNumSignBitsForTargetNode (SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth) const override |
| Determine the number of bits in the operation that are sign bits. More... | |
| bool | SimplifyDemandedVectorEltsForTargetNode (SDValue Op, const APInt &DemandedElts, APInt &KnownUndef, APInt &KnownZero, TargetLoweringOpt &TLO, unsigned Depth) const override |
| Attempt to simplify any target nodes based on the demanded vector elements, returning true on success. More... | |
| bool | SimplifyDemandedBitsForTargetNode (SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, KnownBits &Known, TargetLoweringOpt &TLO, unsigned Depth) const override |
| Attempt to simplify any target nodes based on the demanded bits/elts, returning true on success. More... | |
| SDValue | unwrapAddress (SDValue N) const override |
| SDValue | getReturnAddressFrameIndex (SelectionDAG &DAG) const |
| bool | ExpandInlineAsm (CallInst *CI) const override |
| This hook allows the target to expand an inline asm call to be explicit llvm code if it wants to. More... | |
| ConstraintType | getConstraintType (StringRef Constraint) const override |
| Given a constraint letter, return the type of constraint for this target. More... | |
| ConstraintWeight | getSingleConstraintMatchWeight (AsmOperandInfo &info, const char *constraint) const override |
| Examine constraint string and operand type and determine a weight value. More... | |
| const char * | LowerXConstraint (EVT ConstraintVT) const override |
| Try to replace an X constraint, which matches anything, with another that has more specific requirements based on the type of the corresponding operand. More... | |
| void | LowerAsmOperandForConstraint (SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const override |
| Lower the specified operand into the Ops vector. More... | |
| unsigned | getInlineAsmMemConstraint (StringRef ConstraintCode) const override |
| std::pair< unsigned, const TargetRegisterClass * > | getRegForInlineAsmConstraint (const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override |
| Given a physical register constraint (e.g. More... | |
| bool | isLegalAddressingMode (const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS, Instruction *I=nullptr) const override |
| Return true if the addressing mode represented by AM is legal for this target, for a load/store of the specified type. More... | |
| bool | isLegalICmpImmediate (int64_t Imm) const override |
| Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructions which can compare a register against the immediate without having to materialize the immediate into a register. More... | |
| bool | isLegalAddImmediate (int64_t Imm) const override |
| Return true if the specified immediate is legal add immediate, that is the target has add instructions which can add a register and the immediate without having to materialize the immediate into a register. More... | |
| bool | isLegalStoreImmediate (int64_t Imm) const override |
| Return true if the specified immediate is legal for the value input of a store instruction. More... | |
| int | getScalingFactorCost (const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS) const override |
| Return the cost of the scaling factor used in the addressing mode represented by AM for this target, for a load/store of the specified type. More... | |
| bool | isVectorShiftByScalarCheap (Type *Ty) const override |
| Return true if it's significantly cheaper to shift a vector by a uniform scalar than by an amount which will vary across each lane. More... | |
| bool | isTruncateFree (Type *Ty1, Type *Ty2) const override |
| Return true if it's free to truncate a value of type Ty1 to type Ty2. More... | |
| bool | isTruncateFree (EVT VT1, EVT VT2) const override |
| bool | allowTruncateForTailCall (Type *Ty1, Type *Ty2) const override |
| Return true if a truncation from FromTy to ToTy is permitted when deciding whether a call is in tail position. More... | |
| bool | isZExtFree (Type *Ty1, Type *Ty2) const override |
| Return true if any actual instruction that defines a value of type Ty1 implicit zero-extends the value to Ty2 in the result register. More... | |
| bool | isZExtFree (EVT VT1, EVT VT2) const override |
| bool | isZExtFree (SDValue Val, EVT VT2) const override |
| Return true if zero-extending the specific node Val to type VT2 is free (either because it's implicitly zero-extended such as ARM ldrb / ldrh or because it's folded such as X86 zero-extending loads). More... | |
| bool | isVectorLoadExtDesirable (SDValue) const override |
| Return true if folding a vector load into ExtVal (a sign, zero, or any extend node) is profitable. More... | |
| bool | isFMAFasterThanFMulAndFAdd (EVT VT) const override |
| Return true if an FMA operation is faster than a pair of fmul and fadd instructions. More... | |
| bool | isNarrowingProfitable (EVT VT1, EVT VT2) const override |
| Return true if it's profitable to narrow operations of type VT1 to VT2. More... | |
| bool | getTgtMemIntrinsic (IntrinsicInfo &Info, const CallInst &I, MachineFunction &MF, unsigned Intrinsic) const override |
| Given an intrinsic, checks if on the target the intrinsic will need to map to a MemIntrinsicNode (touches memory). More... | |
| bool | isFPImmLegal (const APFloat &Imm, EVT VT) const override |
| Returns true if the target can instruction select the specified FP immediate natively. More... | |
| bool | isShuffleMaskLegal (ArrayRef< int > Mask, EVT VT) const override |
| Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations, those with specific masks. More... | |
| bool | isVectorClearMaskLegal (ArrayRef< int > Mask, EVT VT) const override |
| Similar to isShuffleMaskLegal. More... | |
| bool | areJTsAllowed (const Function *Fn) const override |
| Returns true if lowering to a jump table is allowed. More... | |
| bool | ShouldShrinkFPConstant (EVT VT) const override |
| If true, then instruction selection should seek to shrink the FP constant of the specified type to a smaller type in order to save space and / or reduce runtime. More... | |
| bool | shouldReduceLoadWidth (SDNode *Load, ISD::LoadExtType ExtTy, EVT NewVT) const override |
| Return true if we believe it is correct and profitable to reduce the load node to a smaller type. More... | |
| bool | isScalarFPTypeInSSEReg (EVT VT) const |
| Return true if the specified scalar FP type is computed in an SSE register, not on the X87 floating point stack. More... | |
| bool | shouldConvertConstantLoadToIntImm (const APInt &Imm, Type *Ty) const override |
| Returns true if it is beneficial to convert a load of a constant to just the constant itself. More... | |
| bool | reduceSelectOfFPConstantLoads (bool IsFPSetCC) const override |
| Return true if it is profitable to convert a select of FP constants into a constant pool load whose address depends on the select condition. More... | |
| bool | convertSelectOfConstantsToMath (EVT VT) const override |
| Return true if a select of constants (select Cond, C1, C2) should be transformed into simple math ops with the condition value. More... | |
| bool | decomposeMulByConstant (EVT VT, SDValue C) const override |
| Return true if it is profitable to transform an integer multiplication-by-constant into simpler operations like shifts and adds. More... | |
| bool | shouldUseStrictFP_TO_INT (EVT FpVT, EVT IntVT, bool IsSigned) const override |
| Return true if it is more correct/profitable to use strict FP_TO_INT conversion operations - canonicalizing the FP source value instead of converting all cases and then selecting based on value. More... | |
| bool | isExtractSubvectorCheap (EVT ResVT, EVT SrcVT, unsigned Index) const override |
| Return true if EXTRACT_SUBVECTOR is cheap for this result type with this index. More... | |
| bool | shouldScalarizeBinop (SDValue) const override |
| Scalar ops always have equal or better analysis/performance/power than the vector equivalent, so this always makes sense if the scalar op is supported. More... | |
| bool | storeOfVectorConstantIsCheap (EVT MemVT, unsigned NumElem, unsigned AddrSpace) const override |
| Return true if it is expected to be cheaper to do a store of a non-zero vector constant with the given size and type for the address space than to store the individual scalar element constants. More... | |
| bool | isLoadBitCastBeneficial (EVT LoadVT, EVT BitcastVT) const override |
| Return true if the following transform is beneficial: fold (conv (load x)) -> (load (conv*)x) On architectures that don't natively support some vector loads efficiently, casting the load to a smaller vector of larger types and loading is more efficient, however, this can be undone by optimizations in dag combiner. More... | |
| const char * | getClearCacheBuiltinName () const override |
| Intel processors have a unified instruction and data cache. More... | |
| unsigned | getRegisterByName (const char *RegName, EVT VT, SelectionDAG &DAG) const override |
| Return the register ID of the name passed in. More... | |
| unsigned | getExceptionPointerRegister (const Constant *PersonalityFn) const override |
| If a physical register, this returns the register that receives the exception address on entry to an EH pad. More... | |
| unsigned | getExceptionSelectorRegister (const Constant *PersonalityFn) const override |
| If a physical register, this returns the register that receives the exception typeid on entry to a landing pad. More... | |
| virtual bool | needsFixedCatchObjects () const override |
| FastISel * | createFastISel (FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo) const override |
| This method returns a target specific FastISel object, or null if the target does not support "fast" ISel. More... | |
| Value * | getIRStackGuard (IRBuilder<> &IRB) const override |
| If the target has a standard location for the stack protector cookie, returns the address of that location. More... | |
| bool | useLoadStackGuardNode () const override |
| If this function returns true, SelectionDAGBuilder emits a LOAD_STACK_GUARD node when it is lowering Intrinsic::stackprotector. More... | |
| bool | useStackGuardXorFP () const override |
| If this function returns true, stack protection checks should XOR the frame pointer (or whichever pointer is used to address locals) into the stack guard value before checking it. More... | |
| void | insertSSPDeclarations (Module &M) const override |
| Inserts necessary declarations for SSP (stack protection) purpose. More... | |
| Value * | getSDagStackGuard (const Module &M) const override |
| Return the variable that's previously inserted by insertSSPDeclarations, if any, otherwise return nullptr. More... | |
| Value * | getSSPStackGuardCheck (const Module &M) const override |
| If the target has a standard stack protection check function that performs validation and error handling, returns the function. More... | |
| SDValue | emitStackGuardXorFP (SelectionDAG &DAG, SDValue Val, const SDLoc &DL) const override |
| Value * | getSafeStackPointerLocation (IRBuilder<> &IRB) const override |
| Return true if the target stores SafeStack pointer at a fixed offset in some non-standard address space, and populates the address space and offset as appropriate. More... | |
| SDValue | BuildFILD (SDValue Op, EVT SrcVT, SDValue Chain, SDValue StackSlot, SelectionDAG &DAG) const |
| bool | isNoopAddrSpaceCast (unsigned SrcAS, unsigned DestAS) const override |
| Returns true if a cast between SrcAS and DestAS is a noop. More... | |
| LegalizeTypeAction | getPreferredVectorAction (MVT VT) const override |
| Customize the preferred legalization strategy for certain types. More... | |
| MVT | getRegisterTypeForCallingConv (LLVMContext &Context, CallingConv::ID CC, EVT VT) const override |
| Certain combinations of ABIs, Targets and features require that types are legal for some operations and not for other operations. More... | |
| unsigned | getNumRegistersForCallingConv (LLVMContext &Context, CallingConv::ID CC, EVT VT) const override |
| Certain targets require unusual breakdowns of certain types. More... | |
| bool | isIntDivCheap (EVT VT, AttributeList Attr) const override |
| Return true if integer divide is usually cheaper than a sequence of several shifts, adds, and multiplies for this target. More... | |
| bool | supportSwiftError () const override |
| Return true if the target supports swifterror attribute. More... | |
| StringRef | getStackProbeSymbolName (MachineFunction &MF) const override |
| Returns the name of the symbol used to emit stack probes or the empty string if not applicable. More... | |
| bool | hasVectorBlend () const override |
| Return true if the target has a vector blend instruction. More... | |
| unsigned | getMaxSupportedInterleaveFactor () const override |
| Get the maximum supported factor for interleaved memory accesses. More... | |
| bool | lowerInterleavedLoad (LoadInst *LI, ArrayRef< ShuffleVectorInst *> Shuffles, ArrayRef< unsigned > Indices, unsigned Factor) const override |
| Lower interleaved load(s) into target specific instructions/intrinsics. More... | |
| bool | lowerInterleavedStore (StoreInst *SI, ShuffleVectorInst *SVI, unsigned Factor) const override |
| Lower interleaved store(s) into target specific instructions/intrinsics. More... | |
| SDValue | expandIndirectJTBranch (const SDLoc &dl, SDValue Value, SDValue Addr, SelectionDAG &DAG) const override |
| Expands target specific indirect branch for the case of JumpTable expanasion. More... | |
 Public Member Functions inherited from llvm::TargetLowering | |
| TargetLowering (const TargetLowering &)=delete | |
| TargetLowering & | operator= (const TargetLowering &)=delete |
| TargetLowering (const TargetMachine &TM) | |
| NOTE: The TargetMachine owns TLOF. More... | |
| bool | isPositionIndependent () const |
| virtual bool | isSDNodeSourceOfDivergence (const SDNode *N, FunctionLoweringInfo *FLI, LegacyDivergenceAnalysis *DA) const |
| virtual bool | isSDNodeAlwaysUniform (const SDNode *N) const |
| virtual bool | getPreIndexedAddressParts (SDNode *, SDValue &, SDValue &, ISD::MemIndexedMode &, SelectionDAG &) const |
| Returns true by value, base pointer and offset pointer and addressing mode by reference if the node's address can be legally represented as pre-indexed load / store address. More... | |
| virtual bool | getPostIndexedAddressParts (SDNode *, SDNode *, SDValue &, SDValue &, ISD::MemIndexedMode &, SelectionDAG &) const |
| Returns true by value, base pointer and offset pointer and addressing mode by reference if this node can be combined with a load / store to form a post-indexed load / store. More... | |
| virtual bool | isOffsetFoldingLegal (const GlobalAddressSDNode *GA) const |
| Return true if folding a constant offset with the given GlobalAddress is legal. More... | |
| bool | isInTailCallPosition (SelectionDAG &DAG, SDNode *Node, SDValue &Chain) const |
| Check whether a given call node is in tail position within its function. More... | |
| void | softenSetCCOperands (SelectionDAG &DAG, EVT VT, SDValue &NewLHS, SDValue &NewRHS, ISD::CondCode &CCCode, const SDLoc &DL) const |
| Soften the operands of a comparison. More... | |
| std::pair< SDValue, SDValue > | makeLibCall (SelectionDAG &DAG, RTLIB::Libcall LC, EVT RetVT, ArrayRef< SDValue > Ops, bool isSigned, const SDLoc &dl, bool doesNotReturn=false, bool isReturnValueUsed=true) const |
| Returns a pair of (return value, chain). More... | |
| bool | parametersInCSRMatch (const MachineRegisterInfo &MRI, const uint32_t *CallerPreservedMask, const SmallVectorImpl< CCValAssign > &ArgLocs, const SmallVectorImpl< SDValue > &OutVals) const |
| Check whether parameters to a call that are passed in callee saved registers are the same as from the calling function. More... | |
| bool | ShrinkDemandedConstant (SDValue Op, const APInt &Demanded, TargetLoweringOpt &TLO) const |
| Check to see if the specified operand of the specified instruction is a constant integer. More... | |
| bool | ShrinkDemandedOp (SDValue Op, unsigned BitWidth, const APInt &Demanded, TargetLoweringOpt &TLO) const |
| Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the casts are free. More... | |
| bool | SimplifyDemandedBits (SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, KnownBits &Known, TargetLoweringOpt &TLO, unsigned Depth=0, bool AssumeSingleUse=false) const |
| Look at Op. More... | |
| bool | SimplifyDemandedBits (SDValue Op, const APInt &DemandedBits, KnownBits &Known, TargetLoweringOpt &TLO, unsigned Depth=0, bool AssumeSingleUse=false) const |
| Helper wrapper around SimplifyDemandedBits, demanding all elements. More... | |
| bool | SimplifyDemandedBits (SDValue Op, const APInt &DemandedMask, DAGCombinerInfo &DCI) const |
| Helper wrapper around SimplifyDemandedBits. More... | |
| bool | SimplifyDemandedVectorElts (SDValue Op, const APInt &DemandedEltMask, APInt &KnownUndef, APInt &KnownZero, TargetLoweringOpt &TLO, unsigned Depth=0, bool AssumeSingleUse=false) const |
| Look at Vector Op. More... | |
| bool | SimplifyDemandedVectorElts (SDValue Op, const APInt &DemandedElts, APInt &KnownUndef, APInt &KnownZero, DAGCombinerInfo &DCI) const |
| Helper wrapper around SimplifyDemandedVectorElts. More... | |
| virtual void | computeKnownBitsForFrameIndex (const SDValue FIOp, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth=0) const |
Determine which of the bits of FrameIndex FIOp are known to be 0. More... | |
| virtual bool | isKnownNeverNaNForTargetNode (SDValue Op, const SelectionDAG &DAG, bool SNaN=false, unsigned Depth=0) const |
If SNaN is false,. More... | |
| bool | isConstTrueVal (const SDNode *N) const |
| Return if the N is a constant or constant vector equal to the true value from getBooleanContents(). More... | |
| bool | isConstFalseVal (const SDNode *N) const |
| Return if the N is a constant or constant vector equal to the false value from getBooleanContents(). More... | |
| bool | isExtendedTrueVal (const ConstantSDNode *N, EVT VT, bool SExt) const |
Return if N is a True value when extended to VT. More... | |
| SDValue | SimplifySetCC (EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, bool foldBooleans, DAGCombinerInfo &DCI, const SDLoc &dl) const |
| Try to simplify a setcc built with the specified operands and cc. More... | |
| virtual bool | isGAPlusOffset (SDNode *N, const GlobalValue *&GA, int64_t &Offset) const |
| Returns true (and the GlobalValue and the offset) if the node is a GlobalAddress + offset. More... | |
| virtual bool | isDesirableToCommuteWithShift (const SDNode *N, CombineLevel Level) const |
| Return true if it is profitable to move this shift by a constant amount though its operand, adjusting any immediate operands as necessary to preserve semantics. More... | |
| virtual bool | shouldFoldShiftPairToMask (const SDNode *N, CombineLevel Level) const |
| Return true if it is profitable to fold a pair of shifts into a mask. More... | |
| virtual bool | isDesirableToTransformToIntegerOp (unsigned, EVT) const |
| Return true if it is profitable for dag combiner to transform a floating point op of specified opcode to a equivalent op of an integer type. More... | |
| std::pair< SDValue, SDValue > | LowerCallTo (CallLoweringInfo &CLI) const |
| This function lowers an abstract call to a function into an actual call. More... | |
| virtual void | HandleByVal (CCState *, unsigned &, unsigned) const |
| Target-specific cleanup for formal ByVal parameters. More... | |
| virtual bool | functionArgumentNeedsConsecutiveRegisters (Type *Ty, CallingConv::ID CallConv, bool isVarArg) const |
| For some targets, an LLVM struct type must be broken down into multiple simple types, but the calling convention specifies that the entire struct must be passed in a block of consecutive registers. More... | |
| virtual SDValue | prepareVolatileOrAtomicLoad (SDValue Chain, const SDLoc &DL, SelectionDAG &DAG) const |
| This callback is used to prepare for a volatile or atomic load. More... | |
| virtual MachineMemOperand::Flags | getMMOFlags (const Instruction &I) const |
| This callback is used to inspect load/store instructions and add target-specific MachineMemOperand flags to them. More... | |
| bool | verifyReturnAddressArgumentIsConstant (SDValue Op, SelectionDAG &DAG) const |
| virtual AsmOperandInfoVector | ParseConstraints (const DataLayout &DL, const TargetRegisterInfo *TRI, ImmutableCallSite CS) const |
| Split up the constraint string from the inline assembly value into the specific constraints and their prefixes, and also tie in the associated operand values. More... | |
| virtual ConstraintWeight | getMultipleConstraintMatchWeight (AsmOperandInfo &info, int maIndex) const |
| Examine constraint type and operand type and determine a weight value. More... | |
| virtual void | ComputeConstraintToUse (AsmOperandInfo &OpInfo, SDValue Op, SelectionDAG *DAG=nullptr) const |
| Determines the constraint code and constraint type to use for the specific AsmOperandInfo, setting OpInfo.ConstraintCode and OpInfo.ConstraintType. More... | |
| SDValue | BuildSDIV (SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization, SmallVectorImpl< SDNode *> &Created) const |
| Given an ISD::SDIV node expressing a divide by constant, return a DAG expression to select that will generate the same value by multiplying by a magic number. More... | |
| SDValue | BuildUDIV (SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization, SmallVectorImpl< SDNode *> &Created) const |
| Given an ISD::UDIV node expressing a divide by constant, return a DAG expression to select that will generate the same value by multiplying by a magic number. More... | |
| virtual SDValue | BuildSDIVPow2 (SDNode *N, const APInt &Divisor, SelectionDAG &DAG, SmallVectorImpl< SDNode *> &Created) const |
| Targets may override this function to provide custom SDIV lowering for power-of-2 denominators. More... | |
| bool | expandMUL_LOHI (unsigned Opcode, EVT VT, SDLoc dl, SDValue LHS, SDValue RHS, SmallVectorImpl< SDValue > &Result, EVT HiLoVT, SelectionDAG &DAG, MulExpansionKind Kind, SDValue LL=SDValue(), SDValue LH=SDValue(), SDValue RL=SDValue(), SDValue RH=SDValue()) const |
| Expand a MUL or [US]MUL_LOHI of n-bit values into two or four nodes, respectively, each computing an n/2-bit part of the result. More... | |
| bool | expandMUL (SDNode *N, SDValue &Lo, SDValue &Hi, EVT HiLoVT, SelectionDAG &DAG, MulExpansionKind Kind, SDValue LL=SDValue(), SDValue LH=SDValue(), SDValue RL=SDValue(), SDValue RH=SDValue()) const |
| Expand a MUL into two nodes. More... | |
| bool | expandFunnelShift (SDNode *N, SDValue &Result, SelectionDAG &DAG) const |
| Expand funnel shift. More... | |
| bool | expandROT (SDNode *N, SDValue &Result, SelectionDAG &DAG) const |
| Expand rotations. More... | |
| bool | expandFP_TO_SINT (SDNode *N, SDValue &Result, SelectionDAG &DAG) const |
| Expand float(f32) to SINT(i64) conversion. More... | |
| bool | expandFP_TO_UINT (SDNode *N, SDValue &Result, SelectionDAG &DAG) const |
| Expand float to UINT conversion. More... | |
| bool | expandUINT_TO_FP (SDNode *N, SDValue &Result, SelectionDAG &DAG) const |
| Expand UINT(i64) to double(f64) conversion. More... | |
| SDValue | expandFMINNUM_FMAXNUM (SDNode *N, SelectionDAG &DAG) const |
| Expand fminnum/fmaxnum into fminnum_ieee/fmaxnum_ieee with quieted inputs. More... | |
| bool | expandCTPOP (SDNode *N, SDValue &Result, SelectionDAG &DAG) const |
| Expand CTPOP nodes. More... | |
| bool | expandCTLZ (SDNode *N, SDValue &Result, SelectionDAG &DAG) const |
| Expand CTLZ/CTLZ_ZERO_UNDEF nodes. More... | |
| bool | expandCTTZ (SDNode *N, SDValue &Result, SelectionDAG &DAG) const |
| Expand CTTZ/CTTZ_ZERO_UNDEF nodes. More... | |
| bool | expandABS (SDNode *N, SDValue &Result, SelectionDAG &DAG) const |
| Expand ABS nodes. More... | |
| SDValue | scalarizeVectorLoad (LoadSDNode *LD, SelectionDAG &DAG) const |
| Turn load of vector type into a load of the individual elements. More... | |
| SDValue | scalarizeVectorStore (StoreSDNode *ST, SelectionDAG &DAG) const |
| std::pair< SDValue, SDValue > | expandUnalignedLoad (LoadSDNode *LD, SelectionDAG &DAG) const |
| Expands an unaligned load to 2 half-size loads for an integer, and possibly more for vectors. More... | |
| SDValue | expandUnalignedStore (StoreSDNode *ST, SelectionDAG &DAG) const |
| Expands an unaligned store to 2 half-size stores for integer values, and possibly more for vectors. More... | |
| SDValue | IncrementMemoryAddress (SDValue Addr, SDValue Mask, const SDLoc &DL, EVT DataVT, SelectionDAG &DAG, bool IsCompressedMemory) const |
Increments memory address Addr according to the type of the value DataVT that should be stored. More... | |
| SDValue | getVectorElementPointer (SelectionDAG &DAG, SDValue VecPtr, EVT VecVT, SDValue Index) const |
Get a pointer to vector element Idx located in memory for a vector of type VecVT starting at a base address of VecPtr. More... | |
| SDValue | expandAddSubSat (SDNode *Node, SelectionDAG &DAG) const |
| Method for building the DAG expansion of ISD::[US][ADD|SUB]SAT. More... | |
| SDValue | getExpandedFixedPointMultiplication (SDNode *Node, SelectionDAG &DAG) const |
| Method for building the DAG expansion of ISD::SMULFIX. More... | |
| virtual void | AdjustInstrPostInstrSelection (MachineInstr &MI, SDNode *Node) const |
| This method should be implemented by targets that mark instructions with the 'hasPostISelHook' flag. More... | |
| virtual SDValue | LowerToTLSEmulatedModel (const GlobalAddressSDNode *GA, SelectionDAG &DAG) const |
| Lower TLS global address SDNode for target independent emulated TLS model. More... | |
| SDValue | lowerCmpEqZeroToCtlzSrl (SDValue Op, SelectionDAG &DAG) const |
| Public Member Functions inherited from llvm::TargetLoweringBase | |
| TargetLoweringBase (const TargetMachine &TM) | |
| NOTE: The TargetMachine owns TLOF. More... | |
| TargetLoweringBase (const TargetLoweringBase &)=delete | |
| TargetLoweringBase & | operator= (const TargetLoweringBase &)=delete |
| virtual | ~TargetLoweringBase ()=default |
| const TargetMachine & | getTargetMachine () const |
| MVT | getPointerTy (const DataLayout &DL, uint32_t AS=0) const |
| Return the pointer type for the given address space, defaults to the pointer type from the data layout. More... | |
| MVT | getFrameIndexTy (const DataLayout &DL) const |
| Return the type for frame index, which is determined by the alloca address space specified through the data layout. More... | |
| virtual MVT | getFenceOperandTy (const DataLayout &DL) const |
| Return the type for operands of fence. More... | |
| EVT | getShiftAmountTy (EVT LHSTy, const DataLayout &DL, bool LegalTypes=true) const |
| virtual MVT | getVectorIdxTy (const DataLayout &DL) const |
| Returns the type to be used for the index operand of: ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT, ISD::INSERT_SUBVECTOR, and ISD::EXTRACT_SUBVECTOR. More... | |
| virtual bool | isSelectSupported (SelectSupportKind) const |
| bool | hasMultipleConditionRegisters () const |
| Return true if multiple condition registers are available. More... | |
| bool | hasExtractBitsInsn () const |
| Return true if the target has BitExtract instructions. More... | |
| virtual bool | shouldExpandBuildVectorWithShuffles (EVT, unsigned DefinedValues) const |
| virtual bool | hasStandaloneRem (EVT VT) const |
| Return true if the target can handle a standalone remainder operation. More... | |
| int | getRecipEstimateSqrtEnabled (EVT VT, MachineFunction &MF) const |
| Return a ReciprocalEstimate enum value for a square root of the given type based on the function's attributes. More... | |
| int | getRecipEstimateDivEnabled (EVT VT, MachineFunction &MF) const |
| Return a ReciprocalEstimate enum value for a division of the given type based on the function's attributes. More... | |
| int | getSqrtRefinementSteps (EVT VT, MachineFunction &MF) const |
| Return the refinement step count for a square root of the given type based on the function's attributes. More... | |
| int | getDivRefinementSteps (EVT VT, MachineFunction &MF) const |
| Return the refinement step count for a division of the given type based on the function's attributes. More... | |
| bool | isSlowDivBypassed () const |
| Returns true if target has indicated at least one type should be bypassed. More... | |
| const DenseMap< unsigned int, unsigned int > & | getBypassSlowDivWidths () const |
| Returns map of slow types for division or remainder with corresponding fast types. More... | |
| bool | isJumpExpensive () const |
| Return true if Flow Control is an expensive operation that should be avoided. More... | |
| bool | isPredictableSelectExpensive () const |
| Return true if selects are only cheaper than branches if the branch is unlikely to be predicted right. More... | |
| virtual BranchProbability | getPredictableBranchThreshold () const |
| If a branch or a select condition is skewed in one direction by more than this factor, it is very likely to be predicted correctly. More... | |
| virtual bool | isStoreBitCastBeneficial (EVT StoreVT, EVT BitcastVT) const |
| Return true if the following transform is beneficial: (store (y (conv x)), y*)) -> (store x, (x*)) More... | |
| bool | enableExtLdPromotion () const |
| Return true if the target wants to use the optimization that turns ext(promotableInst1(...(promotableInstN(load)))) into promotedInst1(...(promotedInstN(ext(load)))). More... | |
| virtual bool | canCombineStoreAndExtract (Type *VectorTy, Value *Idx, unsigned &Cost) const |
| Return true if the target can combine store(extractelement VectorTy, Idx). More... | |
| bool | hasFloatingPointExceptions () const |
| Return true if target supports floating point exceptions. More... | |
| virtual bool | enableAggressiveFMAFusion (EVT VT) const |
| Return true if target always beneficiates from combining into FMA for a given value type. More... | |
| virtual MVT::SimpleValueType | getCmpLibcallReturnType () const |
| Return the ValueType for comparison libcalls. More... | |
| BooleanContent | getBooleanContents (bool isVec, bool isFloat) const |
| For targets without i1 registers, this gives the nature of the high-bits of boolean values held in types wider than i1. More... | |
| BooleanContent | getBooleanContents (EVT Type) const |
| Sched::Preference | getSchedulingPreference () const |
| Return target scheduling preference. More... | |
| virtual Sched::Preference | getSchedulingPreference (SDNode *) const |
| Some scheduler, e.g. More... | |
| virtual const TargetRegisterClass * | getRegClassFor (MVT VT) const |
| Return the register class that should be used for the specified value type. More... | |
| virtual const TargetRegisterClass * | getRepRegClassFor (MVT VT) const |
| Return the 'representative' register class for the specified value type. More... | |
| virtual uint8_t | getRepRegClassCostFor (MVT VT) const |
| Return the cost of the 'representative' register class for the specified value type. More... | |
| bool | isTypeLegal (EVT VT) const |
| Return true if the target has native support for the specified value type. More... | |
| const ValueTypeActionImpl & | getValueTypeActions () const |
| LegalizeTypeAction | getTypeAction (LLVMContext &Context, EVT VT) const |
| Return how we should legalize values of this type, either it is already legal (return 'Legal') or we need to promote it to a larger type (return 'Promote'), or we need to expand it into multiple registers of smaller integer type (return 'Expand'). More... | |
| LegalizeTypeAction | getTypeAction (MVT VT) const |
| EVT | getTypeToTransformTo (LLVMContext &Context, EVT VT) const |
| For types supported by the target, this is an identity function. More... | |
| EVT | getTypeToExpandTo (LLVMContext &Context, EVT VT) const |
| For types supported by the target, this is an identity function. More... | |
| unsigned | getVectorTypeBreakdown (LLVMContext &Context, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const |
| Vector types are broken down into some number of legal first class types. More... | |
| virtual unsigned | getVectorTypeBreakdownForCallingConv (LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const |
| Certain targets such as MIPS require that some types such as vectors are always broken down into scalars in some contexts. More... | |
| virtual bool | canOpTrap (unsigned Op, EVT VT) const |
| Returns true if the operation can trap for the value type. More... | |
| LegalizeAction | getOperationAction (unsigned Op, EVT VT) const |
| Return how this operation should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it. More... | |
| virtual bool | isSupportedFixedPointOperation (unsigned Op, EVT VT, unsigned Scale) const |
| Custom method defined by each target to indicate if an operation which may require a scale is supported natively by the target. More... | |
| LegalizeAction | getFixedPointOperationAction (unsigned Op, EVT VT, unsigned Scale) const |
| Some fixed point operations may be natively supported by the target but only for specific scales. More... | |
| LegalizeAction | getStrictFPOperationAction (unsigned Op, EVT VT) const |
| bool | isOperationLegalOrCustom (unsigned Op, EVT VT) const |
| Return true if the specified operation is legal on this target or can be made legal with custom lowering. More... | |
| bool | isOperationLegalOrPromote (unsigned Op, EVT VT) const |
| Return true if the specified operation is legal on this target or can be made legal using promotion. More... | |
| bool | isOperationLegalOrCustomOrPromote (unsigned Op, EVT VT) const |
| Return true if the specified operation is legal on this target or can be made legal with custom lowering or using promotion. More... | |
| bool | isOperationCustom (unsigned Op, EVT VT) const |
| Return true if the operation uses custom lowering, regardless of whether the type is legal or not. More... | |
| bool | rangeFitsInWord (const APInt &Low, const APInt &High, const DataLayout &DL) const |
| Check whether the range [Low,High] fits in a machine word. More... | |
| virtual bool | isSuitableForJumpTable (const SwitchInst *SI, uint64_t NumCases, uint64_t Range) const |
Return true if lowering to a jump table is suitable for a set of case clusters which may contain NumCases cases, Range range of values. More... | |
| bool | isSuitableForBitTests (unsigned NumDests, unsigned NumCmps, const APInt &Low, const APInt &High, const DataLayout &DL) const |
Return true if lowering to a bit test is suitable for a set of case clusters which contains NumDests unique destinations, Low and High as its lowest and highest case values, and expects NumCmps case value comparisons. More... | |
| bool | isOperationExpand (unsigned Op, EVT VT) const |
| Return true if the specified operation is illegal on this target or unlikely to be made legal with custom lowering. More... | |
| bool | isOperationLegal (unsigned Op, EVT VT) const |
| Return true if the specified operation is legal on this target. More... | |
| LegalizeAction | getLoadExtAction (unsigned ExtType, EVT ValVT, EVT MemVT) const |
| Return how this load with extension should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it. More... | |
| bool | isLoadExtLegal (unsigned ExtType, EVT ValVT, EVT MemVT) const |
| Return true if the specified load with extension is legal on this target. More... | |
| bool | isLoadExtLegalOrCustom (unsigned ExtType, EVT ValVT, EVT MemVT) const |
| Return true if the specified load with extension is legal or custom on this target. More... | |
| LegalizeAction | getTruncStoreAction (EVT ValVT, EVT MemVT) const |
| Return how this store with truncation should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it. More... | |
| bool | isTruncStoreLegal (EVT ValVT, EVT MemVT) const |
| Return true if the specified store with truncation is legal on this target. More... | |
| bool | isTruncStoreLegalOrCustom (EVT ValVT, EVT MemVT) const |
| Return true if the specified store with truncation has solution on this target. More... | |
| LegalizeAction | getIndexedLoadAction (unsigned IdxMode, MVT VT) const |
| Return how the indexed load should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it. More... | |
| bool | isIndexedLoadLegal (unsigned IdxMode, EVT VT) const |
| Return true if the specified indexed load is legal on this target. More... | |
| LegalizeAction | getIndexedStoreAction (unsigned IdxMode, MVT VT) const |
| Return how the indexed store should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it. More... | |
| bool | isIndexedStoreLegal (unsigned IdxMode, EVT VT) const |
| Return true if the specified indexed load is legal on this target. More... | |
| LegalizeAction | getCondCodeAction (ISD::CondCode CC, MVT VT) const |
| Return how the condition code should be treated: either it is legal, needs to be expanded to some other code sequence, or the target has a custom expander for it. More... | |
| bool | isCondCodeLegal (ISD::CondCode CC, MVT VT) const |
| Return true if the specified condition code is legal on this target. More... | |
| bool | isCondCodeLegalOrCustom (ISD::CondCode CC, MVT VT) const |
| Return true if the specified condition code is legal or custom on this target. More... | |
| MVT | getTypeToPromoteTo (unsigned Op, MVT VT) const |
| If the action for this operation is to promote, this method returns the ValueType to promote to. More... | |
| EVT | getValueType (const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const |
| Return the EVT corresponding to this LLVM type. More... | |
| MVT | getSimpleValueType (const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const |
| Return the MVT corresponding to this LLVM type. See getValueType. More... | |
| MVT | getRegisterType (MVT VT) const |
| Return the type of registers that this ValueType will eventually require. More... | |
| MVT | getRegisterType (LLVMContext &Context, EVT VT) const |
| Return the type of registers that this ValueType will eventually require. More... | |
| unsigned | getNumRegisters (LLVMContext &Context, EVT VT) const |
| Return the number of registers that this ValueType will eventually require. More... | |
| virtual unsigned | getABIAlignmentForCallingConv (Type *ArgTy, DataLayout DL) const |
| Certain targets have context senstive alignment requirements, where one type has the alignment requirement of another type. More... | |
| bool | hasBigEndianPartOrdering (EVT VT, const DataLayout &DL) const |
| When splitting a value of the specified type into parts, does the Lo or Hi part come first? This usually follows the endianness, except for ppcf128, where the Hi part always comes first. More... | |
| bool | hasTargetDAGCombine (ISD::NodeType NT) const |
| If true, the target has custom DAG combine transformations that it can perform for the specified node. More... | |
| unsigned | getGatherAllAliasesMaxDepth () const |
| virtual unsigned | getVaListSizeInBits (const DataLayout &DL) const |
| Returns the size of the platform's va_list object. More... | |
| unsigned | getMaxStoresPerMemset (bool OptSize) const |
| Get maximum # of store operations permitted for llvm.memset. More... | |
| unsigned | getMaxStoresPerMemcpy (bool OptSize) const |
| Get maximum # of store operations permitted for llvm.memcpy. More... | |
| virtual unsigned | getMaxGluedStoresPerMemcpy () const |
| Get maximum # of store operations to be glued together. More... | |
| unsigned | getMaxExpandSizeMemcmp (bool OptSize) const |
| Get maximum # of load operations permitted for memcmp. More... | |
| unsigned | getMaxStoresPerMemmove (bool OptSize) const |
| Get maximum # of store operations permitted for llvm.memmove. More... | |
| bool | allowsMemoryAccess (LLVMContext &Context, const DataLayout &DL, EVT VT, unsigned AddrSpace=0, unsigned Alignment=1, bool *Fast=nullptr) const |
| Return true if the target supports a memory access of this type for the given address space and alignment. More... | |
| bool | usesUnderscoreSetJmp () const |
| Determine if we should use _setjmp or setjmp to implement llvm.setjmp. More... | |
| bool | usesUnderscoreLongJmp () const |
| Determine if we should use _longjmp or longjmp to implement llvm.longjmp. More... | |
| virtual unsigned | getMinimumJumpTableEntries () const |
| Return lower limit for number of blocks in a jump table. More... | |
| unsigned | getMinimumJumpTableDensity (bool OptForSize) const |
| Return lower limit of the density in a jump table. More... | |
| unsigned | getMaximumJumpTableSize () const |
| Return upper limit for number of entries in a jump table. More... | |
| virtual bool | isJumpTableRelative () const |
| unsigned | getStackPointerRegisterToSaveRestore () const |
| If a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save and restore. More... | |
| unsigned | getJumpBufSize () const |
| Returns the target's jmp_buf size in bytes (if never set, the default is 200) More... | |
| unsigned | getJumpBufAlignment () const |
| Returns the target's jmp_buf alignment in bytes (if never set, the default is 0) More... | |
| unsigned | getMinStackArgumentAlignment () const |
| Return the minimum stack alignment of an argument. More... | |
| unsigned | getMinFunctionAlignment () const |
| Return the minimum function alignment. More... | |
| unsigned | getPrefFunctionAlignment () const |
| Return the preferred function alignment. More... | |
| virtual unsigned | getPrefLoopAlignment (MachineLoop *ML=nullptr) const |
| Return the preferred loop alignment. More... | |
| virtual bool | alignLoopsWithOptSize () const |
| Should loops be aligned even when the function is marked OptSize (but not MinSize). More... | |
| virtual bool | isCheapAddrSpaceCast (unsigned SrcAS, unsigned DestAS) const |
| Returns true if a cast from SrcAS to DestAS is "cheap", such that e.g. More... | |
| virtual bool | shouldAlignPointerArgs (CallInst *, unsigned &, unsigned &) const |
| Return true if the pointer arguments to CI should be aligned by aligning the object whose address is being passed. More... | |
| virtual void | emitAtomicCmpXchgNoStoreLLBalance (IRBuilder<> &Builder) const |
| virtual bool | shouldSignExtendTypeInLibCall (EVT Type, bool IsSigned) const |
| Returns true if arguments should be sign-extended in lib calls. More... | |
| virtual AtomicExpansionKind | shouldExpandAtomicCmpXchgInIR (AtomicCmpXchgInst *AI) const |
| Returns how the given atomic cmpxchg should be expanded by the IR-level AtomicExpand pass. More... | |
| virtual ISD::NodeType | getExtendForAtomicOps () const |
| Returns how the platform's atomic operations are extended (ZERO_EXTEND, SIGN_EXTEND, or ANY_EXTEND). More... | |
| virtual bool | shouldNormalizeToSelectSequence (LLVMContext &Context, EVT VT) const |
| Returns true if we should normalize select(N0&N1, X, Y) => select(N0, select(N1, X, Y), Y) and select(N0|N1, X, Y) => select(N0, select(N1, X, Y, Y)) if it is likely that it saves us from materializing N0 and N1 in an integer register. More... | |
| virtual bool | getAddrModeArguments (IntrinsicInst *, SmallVectorImpl< Value *> &, Type *&) const |
| CodeGenPrepare sinks address calculations into the same BB as Load/Store instructions reading the address. More... | |
| virtual bool | isCommutativeBinOp (unsigned Opcode) const |
| Returns true if the opcode is a commutative binary operation. More... | |
| virtual bool | isProfitableToHoist (Instruction *I) const |
| bool | isExtFree (const Instruction *I) const |
Return true if the extension represented by I is free. More... | |
| bool | isExtLoad (const LoadInst *Load, const Instruction *Ext, const DataLayout &DL) const |
Return true if Load and Ext can form an ExtLoad. More... | |
| virtual bool | isSExtCheaperThanZExt (EVT FromTy, EVT ToTy) const |
| Return true if sign-extension from FromTy to ToTy is cheaper than zero-extension. More... | |
| virtual bool | hasPairedLoad (EVT, unsigned &) const |
| Return true if the target supplies and combines to a paired load two loaded values of type LoadedType next to each other in memory. More... | |
| virtual bool | isFPExtFree (EVT DestVT, EVT SrcVT) const |
| Return true if an fpext operation is free (for instance, because single-precision floating-point numbers are implicitly extended to double-precision). More... | |
| virtual bool | isFPExtFoldable (unsigned Opcode, EVT DestVT, EVT SrcVT) const |
Return true if an fpext operation input to an Opcode operation is free (for instance, because half-precision floating-point numbers are implicitly extended to float-precision) for an FMA instruction. More... | |
| virtual bool | isFNegFree (EVT VT) const |
| Return true if an fneg operation is free to the point where it is never worthwhile to replace it with a bitwise operation. More... | |
| virtual bool | isFAbsFree (EVT VT) const |
| Return true if an fabs operation is free to the point where it is never worthwhile to replace it with a bitwise operation. More... | |
| virtual bool | aggressivelyPreferBuildVectorSources (EVT VecVT) const |
| virtual bool | shouldConsiderGEPOffsetSplit () const |
| void | setLibcallName (RTLIB::Libcall Call, const char *Name) |
| Rename the default libcall routine name for the specified libcall. More... | |
| const char * | getLibcallName (RTLIB::Libcall Call) const |
| Get the libcall routine name for the specified libcall. More... | |
| void | setCmpLibcallCC (RTLIB::Libcall Call, ISD::CondCode CC) |
| Override the default CondCode to be used to test the result of the comparison libcall against zero. More... | |
| ISD::CondCode | getCmpLibcallCC (RTLIB::Libcall Call) const |
| Get the CondCode that's to be used to test the result of the comparison libcall against zero. More... | |
| void | setLibcallCallingConv (RTLIB::Libcall Call, CallingConv::ID CC) |
| Set the CallingConv that should be used for the specified libcall. More... | |
| CallingConv::ID | getLibcallCallingConv (RTLIB::Libcall Call) const |
| Get the CallingConv that should be used for the specified libcall. More... | |
| virtual void | finalizeLowering (MachineFunction &MF) const |
| Execute target specific actions to finalize target lowering. More... | |
| int | InstructionOpcodeToISD (unsigned Opcode) const |
| Get the ISD node that corresponds to the Instruction class opcode. More... | |
| std::pair< int, MVT > | getTypeLegalizationCost (const DataLayout &DL, Type *Ty) const |
| Estimate the cost of type-legalization and the legalized type. More... | |
| unsigned | getMaxAtomicSizeInBitsSupported () const |
| Returns the maximum atomic operation size (in bits) supported by the backend. More... | |
| unsigned | getMinCmpXchgSizeInBits () const |
| Returns the size of the smallest cmpxchg or ll/sc instruction the backend supports. More... | |
| bool | supportsUnalignedAtomics () const |
| Whether the target supports unaligned atomic operations. More... | |
| virtual bool | shouldInsertFencesForAtomic (const Instruction *I) const |
| Whether AtomicExpandPass should automatically insert fences and reduce ordering for this atomic. More... | |
| virtual Value * | emitLoadLinked (IRBuilder<> &Builder, Value *Addr, AtomicOrdering Ord) const |
| Perform a load-linked operation on Addr, returning a "Value *" with the corresponding pointee type. More... | |
| virtual Value * | emitStoreConditional (IRBuilder<> &Builder, Value *Val, Value *Addr, AtomicOrdering Ord) const |
| Perform a store-conditional operation to Addr. More... | |
| virtual Value * | emitMaskedAtomicRMWIntrinsic (IRBuilder<> &Builder, AtomicRMWInst *AI, Value *AlignedAddr, Value *Incr, Value *Mask, Value *ShiftAmt, AtomicOrdering Ord) const |
| Perform a masked atomicrmw using a target-specific intrinsic. More... | |
| virtual Value * | emitMaskedAtomicCmpXchgIntrinsic (IRBuilder<> &Builder, AtomicCmpXchgInst *CI, Value *AlignedAddr, Value *CmpVal, Value *NewVal, Value *Mask, AtomicOrdering Ord) const |
| Perform a masked cmpxchg using a target-specific intrinsic. More... | |
| virtual Instruction * | emitLeadingFence (IRBuilder<> &Builder, Instruction *Inst, AtomicOrdering Ord) const |
| Inserts in the IR a target-specific intrinsic specifying a fence. More... | |
| virtual Instruction * | emitTrailingFence (IRBuilder<> &Builder, Instruction *Inst, AtomicOrdering Ord) const |
Protected Member Functions | |
| std::pair< const TargetRegisterClass *, uint8_t > | findRepresentativeClass (const TargetRegisterInfo *TRI, MVT VT) const override |
| Return the largest legal super-reg register class of the register class for the specified type and its associated "cost". More... | |
| Protected Member Functions inherited from llvm::TargetLoweringBase | |
| void | initActions () |
| Initialize all of the actions to default values. More... | |
| Value * | getDefaultSafeStackPointerLocation (IRBuilder<> &IRB, bool UseTLS) const |
| void | setBooleanContents (BooleanContent Ty) |
| Specify how the target extends the result of integer and floating point boolean values from i1 to a wider type. More... | |
| void | setBooleanContents (BooleanContent IntTy, BooleanContent FloatTy) |
| Specify how the target extends the result of integer and floating point boolean values from i1 to a wider type. More... | |
| void | setBooleanVectorContents (BooleanContent Ty) |
| Specify how the target extends the result of a vector boolean value from a vector of i1 to a wider type. More... | |
| void | setSchedulingPreference (Sched::Preference Pref) |
| Specify the target scheduling preference. More... | |
| void | setUseUnderscoreSetJmp (bool Val) |
| Indicate whether this target prefers to use _setjmp to implement llvm.setjmp or the version without _. More... | |
| void | setUseUnderscoreLongJmp (bool Val) |
| Indicate whether this target prefers to use _longjmp to implement llvm.longjmp or the version without _. More... | |
| void | setMinimumJumpTableEntries (unsigned Val) |
| Indicate the minimum number of blocks to generate jump tables. More... | |
| void | setMaximumJumpTableSize (unsigned) |
| Indicate the maximum number of entries in jump tables. More... | |
| void | setStackPointerRegisterToSaveRestore (unsigned R) |
| If set to a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save and restore. More... | |
| void | setHasMultipleConditionRegisters (bool hasManyRegs=true) |
| Tells the code generator that the target has multiple (allocatable) condition registers that can be used to store the results of comparisons for use by selects and conditional branches. More... | |
| void | setHasExtractBitsInsn (bool hasExtractInsn=true) |
| Tells the code generator that the target has BitExtract instructions. More... | |
| void | setJumpIsExpensive (bool isExpensive=true) |
| Tells the code generator not to expand logic operations on comparison predicates into separate sequences that increase the amount of flow control. More... | |
| void | setHasFloatingPointExceptions (bool FPExceptions=true) |
| Tells the code generator that this target supports floating point exceptions and cares about preserving floating point exception behavior. More... | |
| void | addBypassSlowDiv (unsigned int SlowBitWidth, unsigned int FastBitWidth) |
| Tells the code generator which bitwidths to bypass. More... | |
| void | addRegisterClass (MVT VT, const TargetRegisterClass *RC) |
| Add the specified register class as an available regclass for the specified value type. More... | |
| void | computeRegisterProperties (const TargetRegisterInfo *TRI) |
| Once all of the register classes are added, this allows us to compute derived properties we expose. More... | |
| void | setOperationAction (unsigned Op, MVT VT, LegalizeAction Action) |
| Indicate that the specified operation does not work with the specified type and indicate what to do about it. More... | |
| void | setLoadExtAction (unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action) |
| Indicate that the specified load with extension does not work with the specified type and indicate what to do about it. More... | |
| void | setTruncStoreAction (MVT ValVT, MVT MemVT, LegalizeAction Action) |
| Indicate that the specified truncating store does not work with the specified type and indicate what to do about it. More... | |
| void | setIndexedLoadAction (unsigned IdxMode, MVT VT, LegalizeAction Action) |
| Indicate that the specified indexed load does or does not work with the specified type and indicate what to do abort it. More... | |
| void | setIndexedStoreAction (unsigned IdxMode, MVT VT, LegalizeAction Action) |
| Indicate that the specified indexed store does or does not work with the specified type and indicate what to do about it. More... | |
| void | setCondCodeAction (ISD::CondCode CC, MVT VT, LegalizeAction Action) |
| Indicate that the specified condition code is or isn't supported on the target and indicate what to do about it. More... | |
| void | AddPromotedToType (unsigned Opc, MVT OrigVT, MVT DestVT) |
| If Opc/OrigVT is specified as being promoted, the promotion code defaults to trying a larger integer/fp until it can find one that works. More... | |
| void | setOperationPromotedToType (unsigned Opc, MVT OrigVT, MVT DestVT) |
| Convenience method to set an operation to Promote and specify the type in a single call. More... | |
| void | setTargetDAGCombine (ISD::NodeType NT) |
| Targets should invoke this method for each target independent node that they want to provide a custom DAG combiner for by implementing the PerformDAGCombine virtual method. More... | |
| void | setJumpBufSize (unsigned Size) |
| Set the target's required jmp_buf buffer size (in bytes); default is 200. More... | |
| void | setJumpBufAlignment (unsigned Align) |
| Set the target's required jmp_buf buffer alignment (in bytes); default is 0. More... | |
| void | setMinFunctionAlignment (unsigned Align) |
| Set the target's minimum function alignment (in log2(bytes)) More... | |
| void | setPrefFunctionAlignment (unsigned Align) |
| Set the target's preferred function alignment. More... | |
| void | setPrefLoopAlignment (unsigned Align) |
| Set the target's preferred loop alignment. More... | |
| void | setMinStackArgumentAlignment (unsigned Align) |
| Set the minimum stack alignment of an argument (in log2(bytes)). More... | |
| void | setMaxAtomicSizeInBitsSupported (unsigned SizeInBits) |
| Set the maximum atomic operation size supported by the backend. More... | |
| void | setMinCmpXchgSizeInBits (unsigned SizeInBits) |
| Sets the minimum cmpxchg or ll/sc size supported by the backend. More... | |
| void | setSupportsUnalignedAtomics (bool UnalignedSupported) |
| Sets whether unaligned atomic operations are supported. More... | |
| virtual bool | isExtFreeImpl (const Instruction *I) const |
Return true if the extension represented by I is free. More... | |
| bool | isLegalRC (const TargetRegisterInfo &TRI, const TargetRegisterClass &RC) const |
| Return true if the value types that can be represented by the specified register class are all legal. More... | |
| MachineBasicBlock * | emitPatchPoint (MachineInstr &MI, MachineBasicBlock *MBB) const |
| Replace/modify any TargetFrameIndex operands with a targte-dependent sequence of memory operands that is recognized by PrologEpilogInserter. More... | |
| MachineBasicBlock * | emitXRayCustomEvent (MachineInstr &MI, MachineBasicBlock *MBB) const |
| Replace/modify the XRay custom event operands with target-dependent details. More... | |
| MachineBasicBlock * | emitXRayTypedEvent (MachineInstr &MI, MachineBasicBlock *MBB) const |
| Replace/modify the XRay typed event operands with target-dependent details. More... | |
Additional Inherited Members | |
| Public Types inherited from llvm::TargetLowering | |
| enum | ConstraintType { C_Register, C_RegisterClass, C_Memory, C_Other, C_Unknown } |
| enum | ConstraintWeight { CW_Invalid = -1, CW_Okay = 0, CW_Good = 1, CW_Better = 2, CW_Best = 3, CW_SpecificReg = CW_Okay, CW_Register = CW_Good, CW_Memory = CW_Better, CW_Constant = CW_Best, CW_Default = CW_Okay } |
| using | AsmOperandInfoVector = std::vector< AsmOperandInfo > |
| Public Types inherited from llvm::TargetLoweringBase | |
| enum | LegalizeAction : uint8_t { Legal, Promote, Expand, LibCall, Custom } |
| This enum indicates whether operations are valid for a target, and if not, what action should be used to make them valid. More... | |
| enum | LegalizeTypeAction : uint8_t { TypeLegal, TypePromoteInteger, TypeExpandInteger, TypeSoftenFloat, TypeExpandFloat, TypeScalarizeVector, TypeSplitVector, TypeWidenVector, TypePromoteFloat } |
| This enum indicates whether a types are legal for a target, and if not, what action should be used to make them valid. More... | |
| enum | BooleanContent { UndefinedBooleanContent, ZeroOrOneBooleanContent, ZeroOrNegativeOneBooleanContent } |
| Enum that describes how the target represents true/false values. More... | |
| enum | SelectSupportKind { ScalarValSelect, ScalarCondVectorVal, VectorMaskSelect } |
| Enum that describes what type of support for selects the target has. More... | |
| enum | AtomicExpansionKind { AtomicExpansionKind::None, AtomicExpansionKind::LLSC, AtomicExpansionKind::LLOnly, AtomicExpansionKind::CmpXChg, AtomicExpansionKind::MaskedIntrinsic } |
| Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all. More... | |
| enum | MulExpansionKind { MulExpansionKind::Always, MulExpansionKind::OnlyLegalOrCustom } |
| Enum that specifies when a multiplication should be expanded. More... | |
| enum | ReciprocalEstimate : int { Unspecified = -1, Disabled = 0, Enabled = 1 } |
| Reciprocal estimate status values used by the functions below. More... | |
| using | LegalizeKind = std::pair< LegalizeTypeAction, EVT > |
| LegalizeKind holds the legalization kind that needs to happen to EVT in order to type-legalize it. More... | |
| using | ArgListTy = std::vector< ArgListEntry > |
| Static Public Member Functions inherited from llvm::TargetLoweringBase | |
| static ISD::NodeType | getExtendForContent (BooleanContent Content) |
| Protected Attributes inherited from llvm::TargetLoweringBase | |
| ValueTypeActionImpl | ValueTypeActions |
| unsigned | GatherAllAliasesMaxDepth |
| Depth that GatherAllAliases should should continue looking for chain dependencies when trying to find a more preferable chain. More... | |
| unsigned | MaxStoresPerMemset |
| Specify maximum number of store instructions per memset call. More... | |
| unsigned | MaxStoresPerMemsetOptSize |
| Maximum number of stores operations that may be substituted for the call to memset, used for functions with OptSize attribute. More... | |
| unsigned | MaxStoresPerMemcpy |
| Specify maximum bytes of store instructions per memcpy call. More... | |
| unsigned | MaxGluedStoresPerMemcpy = 0 |
| Specify max number of store instructions to glue in inlined memcpy. More... | |
| unsigned | MaxStoresPerMemcpyOptSize |
| Maximum number of store operations that may be substituted for a call to memcpy, used for functions with OptSize attribute. More... | |
| unsigned | MaxLoadsPerMemcmp |
| unsigned | MaxLoadsPerMemcmpOptSize |
| unsigned | MaxStoresPerMemmove |
| Specify maximum bytes of store instructions per memmove call. More... | |
| unsigned | MaxStoresPerMemmoveOptSize |
| Maximum number of store instructions that may be substituted for a call to memmove, used for functions with OptSize attribute. More... | |
| bool | PredictableSelectIsExpensive |
| Tells the code generator that select is more expensive than a branch if the branch is usually predicted right. More... | |
| bool | EnableExtLdPromotion |
Detailed Description
Definition at line 662 of file X86ISelLowering.h.
Constructor & Destructor Documentation
◆ X86TargetLowering()
|
explicit |
Definition at line 99 of file X86ISelLowering.cpp.
References llvm::ISD::ABS, llvm::ISD::ADD, llvm::TargetLoweringBase::addBypassSlowDiv(), llvm::ISD::ADDCARRY, llvm::TargetLoweringBase::addRegisterClass(), llvm::ISD::ADJUST_TRAMPOLINE, llvm::ISD::AND, llvm::ISD::ANY_EXTEND, llvm::lltok::APFloat, assert(), llvm::ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, llvm::ISD::ATOMIC_FENCE, llvm::ISD::ATOMIC_LOAD_ADD, llvm::ISD::ATOMIC_LOAD_AND, llvm::ISD::ATOMIC_LOAD_OR, llvm::ISD::ATOMIC_LOAD_SUB, llvm::ISD::ATOMIC_LOAD_XOR, llvm::ISD::ATOMIC_STORE, llvm::ISD::BITCAST, llvm::ISD::BITREVERSE, llvm::ISD::BlockAddress, llvm::ISD::BR_CC, llvm::ISD::BR_JT, llvm::ISD::BRCOND, llvm::ISD::BSWAP, llvm::ISD::BUILD_VECTOR, llvm::APFloat::changeSign(), llvm::TargetLoweringBase::computeRegisterProperties(), llvm::ISD::CONCAT_VECTORS, llvm::ISD::ConstantPool, llvm::APFloat::convert(), llvm::ISD::CTLZ, llvm::ISD::CTLZ_ZERO_UNDEF, llvm::ISD::CTPOP, llvm::ISD::CTTZ, llvm::ISD::CTTZ_ZERO_UNDEF, llvm::TargetLoweringBase::Custom, llvm::ISD::DEBUGTRAP, llvm::CodeGenOpt::Default, llvm::ISD::DYNAMIC_STACKALLOC, llvm::ISD::EH_LABEL, llvm::ISD::EH_RETURN, llvm::ISD::EH_SJLJ_LONGJMP, llvm::ISD::EH_SJLJ_SETJMP, llvm::ISD::EH_SJLJ_SETUP_DISPATCH, llvm::TargetLoweringBase::EnableExtLdPromotion, llvm::TargetOptions::ExceptionModel, llvm::TargetLoweringBase::Expand, ExperimentalPrefLoopAlignment, ExperimentalVectorWideningLegalization, llvm::ISD::ExternalSymbol, llvm::ISD::EXTLOAD, llvm::ISD::EXTRACT_SUBVECTOR, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::MVT::f128, llvm::MVT::f16, llvm::MVT::f32, llvm::MVT::f64, llvm::MVT::f80, llvm::ISD::FABS, llvm::ISD::FADD, llvm::ISD::FCEIL, llvm::ISD::FCOPYSIGN, llvm::ISD::FCOS, llvm::ISD::FEXP, llvm::ISD::FEXP2, llvm::ISD::FFLOOR, llvm::ISD::FGETSIGN, llvm::ISD::FLOG, llvm::ISD::FLOG10, llvm::ISD::FLOG2, llvm::ISD::FLT_ROUNDS_, llvm::ISD::FMA, llvm::ISD::FMAXNUM, llvm::ISD::FMINNUM, llvm::ISD::FNEARBYINT, llvm::ISD::FNEG, llvm::ISD::FP16_TO_FP, llvm::ISD::FP_EXTEND, llvm::ISD::FP_ROUND, llvm::ISD::FP_ROUND_INREG, llvm::ISD::FP_TO_FP16, llvm::ISD::FP_TO_SINT, llvm::ISD::FP_TO_UINT, llvm::MVT::fp_vector_valuetypes(), llvm::ISD::FPOW, llvm::ISD::FRAME_TO_ARGS_OFFSET, llvm::ISD::FREM, llvm::ISD::FRINT, llvm::ISD::FSHL, llvm::ISD::FSHR, llvm::ISD::FSIN, llvm::ISD::FSINCOS, llvm::ISD::FSUB, llvm::ISD::FTRUNC, llvm::ISD::GC_TRANSITION_END, llvm::ISD::GC_TRANSITION_START, llvm::MVT::getIntegerVT(), llvm::TargetLoweringBase::getLibcallName(), llvm::TargetMachine::getOptLevel(), llvm::TargetMachine::getPointerSizeInBits(), llvm::TargetLoweringBase::getRegClassFor(), llvm::X86Subtarget::getRegisterInfo(), llvm::X86RegisterInfo::getStackRegister(), llvm::APFloat::getZero(), llvm::ISD::GlobalAddress, llvm::ISD::GlobalTLSAddress, llvm::X86Subtarget::has3DNow(), llvm::X86Subtarget::hasAnyFMA(), llvm::X86Subtarget::hasAVX(), llvm::X86Subtarget::hasAVX512(), llvm::X86Subtarget::hasBITALG(), llvm::X86Subtarget::hasBMI(), llvm::X86Subtarget::hasBWI(), llvm::X86Subtarget::hasCDI(), llvm::X86Subtarget::hasCMov(), llvm::X86Subtarget::hasCmpxchg16b(), llvm::X86Subtarget::hasDQI(), llvm::X86Subtarget::hasF16C(), llvm::X86Subtarget::hasInt256(), llvm::X86Subtarget::hasLZCNT(), llvm::X86Subtarget::hasMMX(), llvm::X86Subtarget::hasMOVBE(), llvm::X86Subtarget::hasPOPCNT(), llvm::X86Subtarget::hasSlowDivide32(), llvm::X86Subtarget::hasSlowDivide64(), llvm::X86Subtarget::hasSSE1(), llvm::X86Subtarget::hasSSE2(), llvm::X86Subtarget::hasSSE3(), llvm::X86Subtarget::hasSSE41(), llvm::X86Subtarget::hasSSEPrefetch(), llvm::X86Subtarget::hasSSSE3(), llvm::X86Subtarget::hasVBMI2(), llvm::X86Subtarget::hasVLX(), llvm::X86Subtarget::hasVPOPCNTDQ(), llvm::X86Subtarget::hasX87(), llvm::X86Subtarget::hasXOP(), llvm::MVT::i1, llvm::MVT::i128, llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i64, llvm::MVT::i8, llvm::Sched::ILP, llvm::ISD::INIT_TRAMPOLINE, llvm::ISD::INSERT_SUBVECTOR, llvm::ISD::INSERT_VECTOR_ELT, llvm::MVT::integer_valuetypes(), llvm::MVT::integer_vector_valuetypes(), llvm::ISD::INTRINSIC_VOID, llvm::ISD::INTRINSIC_W_CHAIN, llvm::ISD::INTRINSIC_WO_CHAIN, llvm::X86Subtarget::is32Bit(), llvm::X86Subtarget::is64Bit(), llvm::X86Subtarget::isAtom(), llvm::TargetLoweringBase::isOperationCustom(), llvm::TargetLoweringBase::isOperationExpand(), llvm::X86Subtarget::isTargetCygMing(), llvm::X86Subtarget::isTargetDarwin(), llvm::X86Subtarget::isTargetELF(), llvm::X86Subtarget::isTargetKnownWindowsMSVC(), llvm::X86Subtarget::isTargetWin64(), llvm::X86Subtarget::isTargetWindowsGNU(), llvm::X86Subtarget::isTargetWindowsItanium(), llvm::TargetLoweringBase::isTypeLegal(), llvm::ISD::JumpTable, llvm::TargetLoweringBase::Legal, llvm::ISD::LOAD, llvm::TargetLoweringBase::MaxLoadsPerMemcmp, llvm::TargetLoweringBase::MaxLoadsPerMemcmpOptSize, llvm::TargetLoweringBase::MaxStoresPerMemcpy, llvm::TargetLoweringBase::MaxStoresPerMemcpyOptSize, llvm::TargetLoweringBase::MaxStoresPerMemmove, llvm::TargetLoweringBase::MaxStoresPerMemmoveOptSize, llvm::TargetLoweringBase::MaxStoresPerMemset, llvm::TargetLoweringBase::MaxStoresPerMemsetOptSize, llvm::ISD::MGATHER, llvm::ISD::MLOAD, llvm::ISD::MSCATTER, llvm::ISD::MSTORE, llvm::ISD::MUL, llvm::ISD::MULHS, llvm::ISD::MULHU, llvm::TargetMachine::Options, llvm::ISD::OR, llvm::MVT::Other, llvm::TargetLoweringBase::PredictableSelectIsExpensive, llvm::ISD::PREFETCH, llvm::TargetLoweringBase::Promote, llvm::ISD::READCYCLECOUNTER, llvm::Sched::RegPressure, llvm::APFloatBase::rmNearestTiesToEven, llvm::ISD::ROTL, llvm::ISD::ROTR, llvm::ISD::SADDO, llvm::ISD::SADDSAT, llvm::ISD::SCALAR_TO_VECTOR, llvm::ISD::SDIV, llvm::ISD::SDIVREM, llvm::ISD::SELECT, llvm::ISD::SELECT_CC, llvm::TargetLoweringBase::setBooleanContents(), llvm::TargetLoweringBase::setBooleanVectorContents(), llvm::ISD::SETCC, llvm::ISD::SETCCCARRY, llvm::TargetLoweringBase::setCondCodeAction(), llvm::ISD::SETLE, llvm::TargetLoweringBase::setLibcallCallingConv(), llvm::TargetLoweringBase::setLibcallName(), llvm::TargetLoweringBase::setLoadExtAction(), llvm::ISD::SETLT, llvm::ISD::SETOEQ, llvm::TargetLoweringBase::setOperationAction(), llvm::TargetLoweringBase::setOperationPromotedToType(), llvm::TargetLoweringBase::setPrefFunctionAlignment(), llvm::TargetLoweringBase::setPrefLoopAlignment(), llvm::TargetLoweringBase::setSchedulingPreference(), llvm::TargetLoweringBase::setStackPointerRegisterToSaveRestore(), llvm::TargetLoweringBase::setTargetDAGCombine(), llvm::TargetLoweringBase::setTruncStoreAction(), llvm::TargetLoweringBase::ValueTypeActionImpl::setTypeAction(), llvm::ISD::SETUNE, llvm::TargetLoweringBase::setUseUnderscoreLongJmp(), llvm::TargetLoweringBase::setUseUnderscoreSetJmp(), llvm::ISD::SEXTLOAD, llvm::ISD::SHL, llvm::ISD::SHL_PARTS, llvm::ISD::SIGN_EXTEND, llvm::ISD::SIGN_EXTEND_INREG, llvm::ISD::SIGN_EXTEND_VECTOR_INREG, llvm::ISD::SINT_TO_FP, llvm::SjLj, llvm::ISD::SMAX, llvm::ISD::SMIN, llvm::ISD::SMUL_LOHI, llvm::ISD::SMULO, llvm::ISD::SRA, llvm::ISD::SRA_PARTS, llvm::ISD::SREM, llvm::ISD::SRL, llvm::ISD::SRL_PARTS, llvm::ISD::SSUBO, llvm::ISD::SSUBSAT, llvm::ISD::STACKRESTORE, llvm::ISD::STACKSAVE, llvm::ISD::STORE, llvm::ISD::SUB, llvm::ISD::SUBCARRY, llvm::ISD::TRAP, llvm::ISD::TRUNCATE, llvm::TargetLoweringBase::TypeSoftenFloat, llvm::ISD::UADDO, llvm::ISD::UADDSAT, llvm::ISD::UDIV, llvm::ISD::UDIVREM, llvm::ISD::UINT_TO_FP, llvm::ISD::UMAX, llvm::ISD::UMIN, llvm::ISD::UMUL_LOHI, llvm::ISD::UMULO, llvm::ISD::UNDEF, llvm::ISD::UREM, llvm::X86Subtarget::useAVX512Regs(), llvm::X86Subtarget::useBWIRegs(), useSoftFloat(), llvm::X86Subtarget::useSoftFloat(), llvm::ISD::USUBO, llvm::ISD::USUBSAT, llvm::MVT::v16f32, llvm::MVT::v16i1, llvm::MVT::v16i16, llvm::MVT::v16i32, llvm::MVT::v16i8, llvm::MVT::v1i1, llvm::MVT::v2f32, llvm::MVT::v2f64, llvm::MVT::v2i1, llvm::MVT::v2i16, llvm::MVT::v2i32, llvm::MVT::v2i64, llvm::MVT::v2i8, llvm::MVT::v32i1, llvm::MVT::v32i16, llvm::MVT::v32i8, llvm::MVT::v4f32, llvm::MVT::v4f64, llvm::MVT::v4i1, llvm::MVT::v4i16, llvm::MVT::v4i32, llvm::MVT::v4i64, llvm::MVT::v4i8, llvm::MVT::v64i1, llvm::MVT::v64i8, llvm::MVT::v8f32, llvm::MVT::v8f64, llvm::MVT::v8i1, llvm::MVT::v8i16, llvm::MVT::v8i32, llvm::MVT::v8i64, llvm::MVT::v8i8, llvm::ISD::VAARG, llvm::ISD::VACOPY, llvm::ISD::VAEND, llvm::TargetLoweringBase::ValueTypeActions, llvm::ISD::VASTART, llvm::ISD::VECTOR_SHUFFLE, llvm::MVT::vector_valuetypes(), llvm::verifyIntrinsicTables(), llvm::ISD::VSELECT, llvm::CallingConv::X86_StdCall, llvm::MVT::x86mmx, llvm::APFloatBase::x87DoubleExtended(), llvm::ISD::XOR, llvm::ISD::ZERO_EXTEND, llvm::ISD::ZERO_EXTEND_VECTOR_INREG, llvm::TargetLoweringBase::ZeroOrNegativeOneBooleanContent, llvm::TargetLoweringBase::ZeroOrOneBooleanContent, and llvm::ISD::ZEXTLOAD.
Member Function Documentation
◆ allowsMisalignedMemoryAccesses()
|
overridevirtual |
Returns true if the target allows unaligned memory accesses of the specified type.
Returns whether it is "fast" in the last argument.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 2108 of file X86ISelLowering.cpp.
References llvm::EVT::getSizeInBits(), llvm::X86Subtarget::isUnalignedMem16Slow(), and llvm::X86Subtarget::isUnalignedMem32Slow().
◆ allowTruncateForTailCall()
|
overridevirtual |
Return true if a truncation from FromTy to ToTy is permitted when deciding whether a call is in tail position.
Typically this means that both results would be assigned to the same register or stack slot, but it could mean the target performs adequate checks of its own before proceeding with the tail call. Targets must return false when FromTy <= ToTy.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 27500 of file X86ISelLowering.cpp.
References assert(), llvm::EVT::getEVT(), llvm::Type::getPrimitiveSizeInBits(), llvm::Type::isIntegerTy(), and llvm::TargetLoweringBase::isTypeLegal().
◆ areJTsAllowed()
Returns true if lowering to a jump table is allowed.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 27638 of file X86ISelLowering.cpp.
References llvm::TargetLoweringBase::areJTsAllowed(), and llvm::X86Subtarget::useRetpolineIndirectBranches().
◆ BuildFILD()
| SDValue X86TargetLowering::BuildFILD | ( | SDValue | Op, |
| EVT | SrcVT, | ||
| SDValue | Chain, | ||
| SDValue | StackSlot, | ||
| SelectionDAG & | DAG | ||
| ) | const |
Definition at line 17371 of file X86ISelLowering.cpp.
References llvm::MachineFrameInfo::CreateStackObject(), llvm::dyn_cast(), llvm::MVT::f64, llvm::X86ISD::FILD, llvm::X86ISD::FILD_FLAG, llvm::X86ISD::FST, llvm::MachineFunction::getDataLayout(), llvm::MachinePointerInfo::getFixedStack(), llvm::SelectionDAG::getFrameIndex(), llvm::MachineFunction::getFrameInfo(), llvm::FrameIndexSDNode::getIndex(), llvm::SelectionDAG::getLoad(), llvm::SelectionDAG::getMachineFunction(), llvm::MachineFunction::getMachineMemOperand(), llvm::SelectionDAG::getMemIntrinsicNode(), llvm::SDValue::getOperand(), llvm::TargetLoweringBase::getPointerTy(), llvm::EVT::getSizeInBits(), llvm::SDValue::getValue(), llvm::SDValue::getValueSizeInBits(), llvm::SDValue::getValueType(), llvm::SelectionDAG::getValueType(), llvm::SelectionDAG::getVTList(), llvm::MVT::Glue, isScalarFPTypeInSSEReg(), llvm::MachineMemOperand::MOLoad, llvm::MachineMemOperand::MOStore, and llvm::MVT::Other.
Referenced by combineSIntToFP(), LowerI64IntToFP_AVX512DQ(), and lowerUINT_TO_FP_vec().
◆ canMergeStoresTo()
|
overridevirtual |
Returns if it's reasonable to merge stores to MemVT size.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 4945 of file X86ISelLowering.cpp.
References llvm::MachineFunction::getFunction(), llvm::SelectionDAG::getMachineFunction(), llvm::EVT::getSizeInBits(), llvm::Function::hasFnAttribute(), llvm::X86Subtarget::is64Bit(), and llvm::Attribute::NoImplicitFloat.
◆ computeKnownBitsForTargetNode()
|
overridevirtual |
Determine which of the bits specified in Mask are known to be either zero or one and return them in the KnownZero/KnownOne bitsets.
Reimplemented from llvm::TargetLowering.
Definition at line 30074 of file X86ISelLowering.cpp.
References llvm::APInt::ashrInPlace(), assert(), llvm::ISD::BUILTIN_OP_END, llvm::APInt::clearAllBits(), llvm::X86ISD::CMOV, llvm::SelectionDAG::computeKnownBits(), llvm::KnownBits::countMinLeadingZeros(), llvm::APInt::getAllOnesValue(), llvm::KnownBits::getBitWidth(), llvm::SDValue::getConstantOperandVal(), llvm::SDValue::getNode(), llvm::APInt::getOneBitSet(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), getPackDemandedElts(), llvm::EVT::getScalarSizeInBits(), llvm::EVT::getSimpleVT(), getTargetShuffleMask(), llvm::SDValue::getValueType(), llvm::TargetLoweringBase::getValueType(), llvm::EVT::getVectorNumElements(), llvm::ISD::INTRINSIC_VOID, llvm::ISD::INTRINSIC_W_CHAIN, llvm::ISD::INTRINSIC_WO_CHAIN, isTargetShuffle(), llvm::KnownBits::isUnknown(), llvm::APInt::lshrInPlace(), llvm::BitmaskEnumDetail::Mask(), llvm::X86ISD::MOVMSK, llvm::KnownBits::One, llvm::X86ISD::PACKUS, llvm::X86ISD::PEXTRB, llvm::X86ISD::PEXTRW, llvm::KnownBits::resetAll(), llvm::APInt::setAllBits(), llvm::KnownBits::setAllZero(), llvm::APInt::setBitsFrom(), llvm::X86ISD::SETCC, llvm::APInt::setHighBits(), llvm::APInt::setLowBits(), llvm::SmallVectorBase::size(), llvm::SM_SentinelUndef, llvm::SM_SentinelZero, llvm::KnownBits::trunc(), llvm::X86ISD::VSHLI, llvm::X86ISD::VSRAI, llvm::X86ISD::VSRLI, llvm::KnownBits::Zero, and llvm::KnownBits::zextOrTrunc().
◆ ComputeNumSignBitsForTargetNode()
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overridevirtual |
Determine the number of bits in the operation that are sign bits.
Reimplemented from llvm::TargetLowering.
Definition at line 30230 of file X86ISelLowering.cpp.
References assert(), llvm::X86ISD::CMOV, llvm::X86ISD::CMPP, llvm::SelectionDAG::ComputeNumSignBits(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), getPackDemandedElts(), llvm::SDValue::getScalarValueSizeInBits(), llvm::SDValue::getValueType(), llvm::APInt::getZExtValue(), llvm::X86ISD::PACKSS, llvm::X86ISD::PCMPEQ, llvm::X86ISD::PCMPGT, llvm::X86ISD::SETCC_CARRY, llvm::APInt::uge(), llvm::X86ISD::VPCOM, llvm::X86ISD::VPCOMU, llvm::X86ISD::VSHLI, llvm::X86ISD::VSRAI, and llvm::X86ISD::VTRUNC.
◆ convertSelectOfConstantsToMath()
Return true if a select of constants (select Cond, C1, C2) should be transformed into simple math ops with the condition value.
For example: select Cond, C1, C1-1 –> add (zext Cond), C1-1
Reimplemented from llvm::TargetLoweringBase.
Definition at line 4863 of file X86ISelLowering.cpp.
References llvm::X86Subtarget::hasAVX512(), and llvm::EVT::isVector().
◆ convertSetCCLogicToBitwiseLogic()
Use bitwise logic to make pairs of compares more efficient.
For example: and (seteq A, B), (seteq C, D) –> seteq (or (xor A, B), (xor C, D)), 0 This should be true when it takes more than one instruction to lower setcc (cmp+set on x86 scalar), when bitwise ops are faster than logic on condition bits (crand on PowerPC), and/or when reducing cmp+br is a win.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 835 of file X86ISelLowering.h.
References llvm::EVT::isScalarInteger().
◆ createFastISel()
|
overridevirtual |
This method returns a target specific FastISel object, or null if the target does not support "fast" ISel.
Reimplemented from llvm::TargetLowering.
Definition at line 4497 of file X86ISelLowering.cpp.
References llvm::X86::createFastISel().
◆ decomposeMulByConstant()
Return true if it is profitable to transform an integer multiplication-by-constant into simpler operations like shifts and adds.
This may be true if the target does not directly support the multiplication operation for the specified type or the sequence of simpler ops is faster than the multiply.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 4872 of file X86ISelLowering.cpp.
References llvm::SDValue::getNode(), llvm::ISD::isConstantSplatVector(), llvm::TargetLoweringBase::isOperationLegal(), llvm::APInt::isPowerOf2(), and llvm::ISD::MUL.
◆ EmitInstrWithCustomInserter()
|
overridevirtual |
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' flag.
These instructions are special in various ways, which require special support to insert. The specified MachineInstr is created but not inserted into any basic blocks, and this method is called to expand it into a sequence of instructions, potentially also creating new basic blocks and control flow. As long as the returned basic block is different (i.e., we created a new one), the custom inserter is free to modify the rest of MBB.
Reimplemented from llvm::TargetLowering.
Definition at line 29751 of file X86ISelLowering.cpp.
References llvm::addFrameReference(), llvm::addFullAddress(), llvm::MachineInstrBuilder::addImm(), llvm::MachineBasicBlock::addLiveIn(), llvm::MachineInstrBuilder::addReg(), llvm::X86::AddrNumOperands, assert(), llvm::BuildMI(), llvm::ISD::CATCHPAD, llvm::ISD::CATCHRET, llvm::MachineFrameInfo::CreateStackObject(), llvm::MachineRegisterInfo::createVirtualRegister(), llvm::N86::EAX, llvm::N86::EBX, llvm::N86::ECX, llvm::N86::EDX, emitClzero(), emitMonitor(), llvm::TargetLoweringBase::emitPatchPoint(), emitRDPKRU(), emitWRPKRU(), emitXBegin(), llvm::TargetLoweringBase::emitXRayCustomEvent(), llvm::TargetLoweringBase::emitXRayTypedEvent(), llvm::MachineInstr::eraseFromParent(), llvm::N86::ESI, llvm::X86ISD::FNSTCW16m, llvm::MCInstrInfo::get(), llvm::getAddressFromInstr(), llvm::X86RegisterInfo::getBaseRegister(), llvm::MachineFunction::getDataLayout(), llvm::MachineInstr::getDebugLoc(), llvm::MachineFunction::getFrameInfo(), llvm::X86Subtarget::getInstrInfo(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::TargetLoweringBase::getPointerTy(), llvm::MachineOperand::getReg(), llvm::TargetLoweringBase::getRegClassFor(), llvm::MachineFunction::getRegInfo(), llvm::X86Subtarget::getRegisterInfo(), llvm::X86RegisterInfo::hasBasePointer(), llvm::X86AddressMode::IndexReg, llvm::X86Subtarget::is32Bit(), llvm::MachineBasicBlock::isLiveIn(), llvm_unreachable, MRI, llvm::setDirectAddressInInstr(), llvm::MachineOperand::setIsUndef(), TII, TRI, llvm::X86ISD::VAARG_64, and llvm::X86ISD::VASTART_SAVE_XMM_REGS.
◆ emitStackGuardXorFP()
|
overridevirtual |
Reimplemented from llvm::TargetLowering.
Definition at line 1929 of file X86ISelLowering.cpp.
References llvm::SelectionDAG::getDataLayout(), llvm::TargetLoweringBase::getPointerTy(), and llvm::X86Subtarget::is64Bit().
◆ expandIndirectJTBranch()
|
overridevirtual |
Expands target specific indirect branch for the case of JumpTable expanasion.
Reimplemented from llvm::TargetLowering.
Definition at line 41674 of file X86ISelLowering.cpp.
References llvm::TargetLowering::expandIndirectJTBranch(), llvm::SelectionDAG::getMachineFunction(), llvm::MachineFunction::getMMI(), llvm::MachineModuleInfo::getModule(), llvm::Module::getModuleFlag(), llvm::SelectionDAG::getNode(), llvm::X86ISD::NT_BRIND, and llvm::MVT::Other.
◆ ExpandInlineAsm()
This hook allows the target to expand an inline asm call to be explicit llvm code if it wants to.
This is useful for turning simple inline asms into LLVM intrinsics, which gives the compiler more information about the behavior of the code.
Reimplemented from llvm::TargetLowering.
Definition at line 41830 of file X86ISelLowering.cpp.
References llvm::array_pod_sort(), llvm::SmallVectorTemplateCommon< T >::begin(), llvm::SmallVectorImpl< T >::clear(), clobbersFlagRegisters(), llvm::dyn_cast(), llvm::SmallVectorTemplateCommon< T >::end(), llvm::InlineAsm::getAsmString(), llvm::IntegerType::getBitWidth(), llvm::CallBase::getCalledValue(), llvm::InlineAsm::getConstraintString(), llvm::Value::getType(), llvm::Type::isIntegerTy(), llvm::IntrinsicLowering::LowerToByteSwap(), matchAsm(), llvm::InlineAsm::ParseConstraints(), llvm::SmallVectorBase::size(), and llvm::SplitString().
◆ findRepresentativeClass()
|
overrideprotectedvirtual |
Return the largest legal super-reg register class of the register class for the specified type and its associated "cost".
findRepresentativeClass - Return the largest legal super-reg register class of the register class for the specified type and its associated "cost".
Reimplemented from llvm::TargetLoweringBase.
Definition at line 2212 of file X86ISelLowering.cpp.
References llvm::MVT::f32, llvm::MVT::f64, llvm::TargetLoweringBase::findRepresentativeClass(), llvm::TargetMachine::getCodeModel(), llvm::TargetLoweringBase::getTargetMachine(), llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i64, llvm::MVT::i8, llvm::X86Subtarget::is64Bit(), llvm::CodeModel::Kernel, llvm::MSP430ISD::RRC, llvm::MVT::SimpleTy, llvm::MVT::v16f32, llvm::MVT::v16i16, llvm::MVT::v16i32, llvm::MVT::v16i8, llvm::MVT::v2f64, llvm::MVT::v2i64, llvm::MVT::v32i16, llvm::MVT::v32i8, llvm::MVT::v4f32, llvm::MVT::v4f64, llvm::MVT::v4i32, llvm::MVT::v4i64, llvm::MVT::v64i8, llvm::MVT::v8f32, llvm::MVT::v8f64, llvm::MVT::v8i16, llvm::MVT::v8i32, llvm::MVT::v8i64, and llvm::MVT::x86mmx.
◆ getByValTypeAlignment()
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overridevirtual |
Return the desired alignment for ByVal aggregate function arguments in the caller parameter area.
For X86, aggregates that contains are placed at 16-byte boundaries while the rest are at 4-byte boundaries.
For X86, aggregates that contain SSE vectors are placed at 16-byte boundaries while the rest are at 4-byte boundaries.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 2026 of file X86ISelLowering.cpp.
References llvm::AMDGPU::HSAMD::Kernel::Arg::Key::Align, llvm::DataLayout::getABITypeAlignment(), getMaxByValAlign(), llvm::X86Subtarget::hasSSE1(), and llvm::X86Subtarget::is64Bit().
◆ getClearCacheBuiltinName()
Intel processors have a unified instruction and data cache.
Reimplemented from llvm::TargetLowering.
Definition at line 1074 of file X86ISelLowering.h.
References llvm::X86::createFastISel().
◆ getConstraintType()
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overridevirtual |
Given a constraint letter, return the type of constraint for this target.
Reimplemented from llvm::TargetLowering.
Definition at line 41908 of file X86ISelLowering.cpp.
References llvm::TargetLowering::C_Other, llvm::TargetLowering::C_Register, llvm::TargetLowering::C_RegisterClass, llvm::TargetLowering::getConstraintType(), and llvm::StringRef::size().
◆ getExceptionPointerRegister()
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overridevirtual |
If a physical register, this returns the register that receives the exception address on entry to an EH pad.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 22934 of file X86ISelLowering.cpp.
References llvm::classifyEHPersonality(), llvm::CoreCLR, llvm::N86::EAX, llvm::N86::EDX, and llvm::X86Subtarget::isTarget64BitLP64().
◆ getExceptionSelectorRegister()
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overridevirtual |
If a physical register, this returns the register that receives the exception typeid on entry to a landing pad.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 22942 of file X86ISelLowering.cpp.
References assert(), llvm::classifyEHPersonality(), llvm::N86::EDX, llvm::isFuncletEHPersonality(), and llvm::X86Subtarget::isTarget64BitLP64().
◆ getInlineAsmMemConstraint()
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inlineoverridevirtual |
Reimplemented from llvm::TargetLowering.
Definition at line 907 of file X86ISelLowering.h.
References llvm::InlineAsm::Constraint_i, llvm::InlineAsm::Constraint_o, llvm::InlineAsm::Constraint_v, llvm::InlineAsm::Constraint_X, llvm::TargetLowering::getInlineAsmMemConstraint(), getScalingFactorCost(), I, Info, llvm::BitmaskEnumDetail::Mask(), and TRI.
◆ getIRStackGuard()
If the target has a standard location for the stack protector cookie, returns the address of that location.
Otherwise, returns nullptr.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 2256 of file X86ISelLowering.cpp.
References llvm::TargetLoweringBase::getIRStackGuard(), llvm::X86Subtarget::getTargetTriple(), hasStackGuardSlotTLS(), llvm::X86Subtarget::is64Bit(), llvm::X86Subtarget::isTargetFuchsia(), and SegmentOffset().
◆ getJumpTableEncoding()
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overridevirtual |
Return the entry encoding for a jump table in the current function.
The returned value is a member of the MachineJumpTableInfo::JTEntryKind enum.
Reimplemented from llvm::TargetLowering.
Definition at line 2134 of file X86ISelLowering.cpp.
References llvm::MachineJumpTableInfo::EK_Custom32, llvm::TargetLowering::getJumpTableEncoding(), llvm::X86Subtarget::isPICStyleGOT(), and llvm::TargetLowering::isPositionIndependent().
Referenced by getRetpolineSymbol().
◆ getMaxSupportedInterleaveFactor()
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inlineoverridevirtual |
Get the maximum supported factor for interleaved memory accesses.
Default to be the minimum interleave factor: 2.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 1139 of file X86ISelLowering.h.
References Arg, Callee, llvm::X86::createFastISel(), llvm::CallingConv::CXX_FAST_TLS, Enabled, llvm::Function::getCallingConv(), llvm::MachineFunction::getFunction(), llvm::Function::hasFnAttribute(), llvm::MipsISD::Ins, LowerCallResult(), LowerDYNAMIC_STACKALLOC(), LowerEXTRACT_VECTOR_ELT(), LowerFRAMEADDR(), LowerINSERT_VECTOR_ELT(), LowerMemOpCallTo(), LowerRETURNADDR(), LowerSETCCCARRY(), LowerSINT_TO_FP(), LowerUINT_TO_FP(), LowerVAARG(), LowerVASTART(), llvm::Attribute::NoUnwind, and SI.
◆ getMemcmpEqZeroLoadsPerBlock()
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inlineoverridevirtual |
Allow multiple load pairs per block for smaller and faster code.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 843 of file X86ISelLowering.h.
References Context, llvm::Depth, and info.
◆ getNumRegistersForCallingConv()
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overridevirtual |
Certain targets require unusual breakdowns of certain types.
For MIPS, this occurs when a vector type is used, as vector are passed through the integer register set.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 1958 of file X86ISelLowering.cpp.
References llvm::TargetLoweringBase::getNumRegistersForCallingConv(), llvm::X86Subtarget::hasAVX512(), llvm::X86Subtarget::hasBWI(), and llvm::MVT::v32i1.
◆ getOptimalMemOpType()
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overridevirtual |
Returns the target specific optimal type for load and store operations as a result of memset, memcpy, and memmove lowering.
If DstAlign is zero that means it's safe to destination alignment can satisfy any constraint. Similarly if SrcAlign is zero it means there isn't a need to check it against alignment requirement, probably because the source does not need to be loaded. If 'IsMemset' is true, that means it's expanding a memset. If 'ZeroMemset' is true, that means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy source is constant so it does not need to be loaded. It returns EVT::Other if the type should be determined using generic target-independent logic.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 2054 of file X86ISelLowering.cpp.
References F(), llvm::MVT::f64, llvm::MachineFunction::getFunction(), llvm::X86Subtarget::hasAVX(), llvm::Function::hasFnAttribute(), llvm::X86Subtarget::hasSSE1(), llvm::X86Subtarget::hasSSE2(), llvm::X86Subtarget::hasX87(), llvm::MVT::i32, llvm::MVT::i64, llvm::X86Subtarget::is64Bit(), llvm::X86Subtarget::isUnalignedMem16Slow(), llvm::Attribute::NoImplicitFloat, llvm::MVT::v16i8, llvm::MVT::v32i8, and llvm::MVT::v4f32.
◆ getPICJumpTableRelocBase()
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overridevirtual |
Returns relocation base for the given PIC jumptable.
Reimplemented from llvm::TargetLowering.
Definition at line 2188 of file X86ISelLowering.cpp.
References llvm::SelectionDAG::getDataLayout(), llvm::SelectionDAG::getNode(), getPICJumpTableRelocBaseExpr(), llvm::TargetLoweringBase::getPointerTy(), llvm::X86ISD::GlobalBaseReg, and llvm::X86Subtarget::is64Bit().
◆ getPICJumpTableRelocBaseExpr()
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overridevirtual |
This returns the relocation base for the given PIC jumptable, the same as getPICJumpTableRelocBase, but as an MCExpr.
Reimplemented from llvm::TargetLowering.
Definition at line 2201 of file X86ISelLowering.cpp.
References llvm::MCSymbolRefExpr::create(), llvm::MachineFunction::getPICBaseSymbol(), llvm::TargetLowering::getPICJumpTableRelocBaseExpr(), and llvm::X86Subtarget::isPICStyleRIPRel().
Referenced by getPICJumpTableRelocBase().
◆ getPreferredVectorAction()
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overridevirtual |
Customize the preferred legalization strategy for certain types.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 1938 of file X86ISelLowering.cpp.
References ExperimentalVectorWideningLegalization, llvm::TargetLoweringBase::getPreferredVectorAction(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorNumElements(), llvm::X86Subtarget::hasAVX512(), llvm::X86Subtarget::hasBWI(), llvm::MVT::i1, llvm::TargetLoweringBase::TypeSplitVector, llvm::TargetLoweringBase::TypeWidenVector, and llvm::MVT::v32i1.
◆ getRegForInlineAsmConstraint()
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overridevirtual |
Given a physical register constraint (e.g.
{edx}), return the register number and the register class for the register. This should only be used for C_Register constraints. On error, this returns a register number of 0.
Reimplemented from llvm::TargetLowering.
Definition at line 42325 of file X86ISelLowering.cpp.
References assert(), llvm::TargetRegisterClass::contains(), llvm::N86::EAX, llvm::N86::EBX, llvm::N86::ECX, llvm::N86::EDI, llvm::N86::EDX, llvm::N86::ESI, llvm::MVT::f32, llvm::MVT::f64, llvm::MCRegisterInfo::getEncodingValue(), llvm::TargetLowering::getRegForInlineAsmConstraint(), llvm::MVT::getSizeInBits(), llvm::getX86SubSuperRegisterOrZero(), llvm::X86Subtarget::hasAVX512(), llvm::X86Subtarget::hasMMX(), llvm::X86Subtarget::hasSSE1(), llvm::X86Subtarget::hasSSE2(), llvm::X86Subtarget::hasVLX(), llvm::MVT::i1, llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i64, llvm::MVT::i8, if(), llvm::X86Subtarget::is16Bit(), llvm::X86Subtarget::is32Bit(), llvm::X86Subtarget::is64Bit(), is64Bit(), isFRClass(), isGRClass(), isScalarFPTypeInSSEReg(), llvm::TargetRegisterInfo::isTypeLegalForClass(), LLVM_FALLTHROUGH, llvm::MVT::Other, llvm::MVT::SimpleTy, Size, llvm::StringRef::size(), llvm::MVT::v16f32, llvm::MVT::v16i16, llvm::MVT::v16i32, llvm::MVT::v16i8, llvm::MVT::v2f64, llvm::MVT::v2i64, llvm::MVT::v32i8, llvm::MVT::v4f32, llvm::MVT::v4f64, llvm::MVT::v4i32, llvm::MVT::v4i64, llvm::MVT::v8f32, llvm::MVT::v8f64, llvm::MVT::v8i16, llvm::MVT::v8i32, and llvm::MVT::v8i64.
◆ getRegisterByName()
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overridevirtual |
Return the register ID of the name passed in.
Used by named register global variables extension. There is no target-independent behaviour so the default action is to bail.
Reimplemented from llvm::TargetLowering.
Definition at line 22895 of file X86ISelLowering.cpp.
References assert(), llvm::StringSwitch< T, R >::Case(), llvm::StringSwitch< T, R >::Default(), llvm::N86::ESP, llvm::X86Subtarget::getFrameLowering(), llvm::SelectionDAG::getIntPtrConstant(), llvm::SelectionDAG::getMachineFunction(), llvm::X86RegisterInfo::getPtrSizedFrameRegister(), llvm::X86Subtarget::getRegisterInfo(), llvm::X86RegisterInfo::getSlotSize(), llvm::TargetFrameLowering::hasFP(), Reg, and llvm::report_fatal_error().
◆ getRegisterTypeForCallingConv()
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overridevirtual |
Certain combinations of ABIs, Targets and features require that types are legal for some operations and not for other operations.
For MIPS all vector types must be passed through the integer register set.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 1950 of file X86ISelLowering.cpp.
References llvm::TargetLoweringBase::getRegisterTypeForCallingConv(), llvm::X86Subtarget::hasAVX512(), llvm::X86Subtarget::hasBWI(), llvm::MVT::v32i1, and llvm::MVT::v32i8.
◆ getReturnAddressFrameIndex()
| SDValue X86TargetLowering::getReturnAddressFrameIndex | ( | SelectionDAG & | DAG | ) | const |
Definition at line 4580 of file X86ISelLowering.cpp.
References llvm::MachineFrameInfo::CreateFixedObject(), llvm::SelectionDAG::getDataLayout(), llvm::SelectionDAG::getFrameIndex(), llvm::MachineFunction::getFrameInfo(), llvm::MachineFunction::getInfo(), llvm::SelectionDAG::getMachineFunction(), llvm::TargetLoweringBase::getPointerTy(), llvm::X86MachineFunctionInfo::getRAIndex(), llvm::X86Subtarget::getRegisterInfo(), llvm::X86RegisterInfo::getSlotSize(), and llvm::X86MachineFunctionInfo::setRAIndex().
Referenced by isSortedByValueNo(), and LowerINTRINSIC_W_CHAIN().
◆ getSafeStackPointerLocation()
Return true if the target stores SafeStack pointer at a fixed offset in some non-standard address space, and populates the address space and offset as appropriate.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 2316 of file X86ISelLowering.cpp.
References llvm::TargetLoweringBase::getDefaultSafeStackPointerLocation(), llvm::TargetLoweringBase::getSafeStackPointerLocation(), llvm::X86Subtarget::getTargetTriple(), llvm::X86Subtarget::is64Bit(), llvm::Triple::isOSContiki(), llvm::X86Subtarget::isTargetAndroid(), llvm::X86Subtarget::isTargetFuchsia(), and SegmentOffset().
◆ getScalarShiftAmountTy()
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inlineoverridevirtual |
EVT is not used in-tree, but is used by out-of-tree target.
A documentation for this function would be nice...
Reimplemented from llvm::TargetLoweringBase.
Definition at line 673 of file X86ISelLowering.h.
References llvm::AMDGPU::HSAMD::Kernel::Arg::Key::Align, llvm::CallingConv::Fast, llvm::MVT::i8, MI, N, Results, and Size.
◆ getScalingFactorCost()
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overridevirtual |
Return the cost of the scaling factor used in the addressing mode represented by AM for this target, for a load/store of the specified type.
If the AM is supported, the return value must be >= 0. If the AM is not supported, it returns a negative value.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 42638 of file X86ISelLowering.cpp.
References isLegalAddressingMode(), and llvm::TargetLoweringBase::AddrMode::Scale.
◆ getSDagStackGuard()
Return the variable that's previously inserted by insertSSPDeclarations, if any, otherwise return nullptr.
Should be used only when getIRStackGuard returns nullptr.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 2298 of file X86ISelLowering.cpp.
References llvm::Module::getGlobalVariable(), llvm::TargetLoweringBase::getSDagStackGuard(), llvm::X86Subtarget::getTargetTriple(), llvm::Triple::isWindowsItaniumEnvironment(), and llvm::Triple::isWindowsMSVCEnvironment().
◆ getSetCCResultType()
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overridevirtual |
Return the value type to use for ISD::SETCC.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 1966 of file X86ISelLowering.cpp.
References llvm::EVT::changeVectorElementTypeToInteger(), llvm::EVT::getSimpleVT(), llvm::MVT::getSizeInBits(), llvm::TargetLoweringBase::getTypeAction(), llvm::TargetLoweringBase::getTypeToTransformTo(), llvm::MVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::EVT::getVectorVT(), llvm::X86Subtarget::hasAVX512(), llvm::X86Subtarget::hasBWI(), llvm::X86Subtarget::hasVLX(), llvm::MVT::i1, llvm::MVT::i8, llvm::MVT::is512BitVector(), llvm::EVT::isVector(), llvm::MVT::isVector(), and llvm::TargetLoweringBase::TypeLegal.
Referenced by lowerUINT_TO_FP_vec().
◆ getSingleConstraintMatchWeight()
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overridevirtual |
Examine constraint string and operand type and determine a weight value.
Examine constraint type and operand type and determine a weight value.
The operand object must already have been set up with the operand type.
This object must already have been set up with the operand type and the current alternative constraint selected.
Reimplemented from llvm::TargetLowering.
Definition at line 41974 of file X86ISelLowering.cpp.
References C, llvm::TargetLowering::AsmOperandInfo::CallOperandVal, llvm::TargetLowering::CW_Constant, llvm::TargetLowering::CW_Default, llvm::TargetLowering::CW_Invalid, llvm::TargetLowering::CW_Register, llvm::TargetLowering::CW_SpecificReg, llvm::Type::getPrimitiveSizeInBits(), llvm::TargetLowering::getSingleConstraintMatchWeight(), llvm::Value::getType(), llvm::X86Subtarget::hasAVX(), llvm::X86Subtarget::hasAVX512(), llvm::X86Subtarget::hasMMX(), llvm::X86Subtarget::hasSSE1(), llvm::X86Subtarget::hasSSE2(), llvm::Type::isFloatingPointTy(), llvm::Type::isIntegerTy(), llvm::Type::isX86_MMXTy(), LLVM_FALLTHROUGH, LowerXConstraint(), Size, and llvm::StringRef::size().
◆ getSSPStackGuardCheck()
If the target has a standard stack protection check function that performs validation and error handling, returns the function.
Otherwise, returns nullptr. Must be previously inserted by insertSSPDeclarations. Should be used only when getIRStackGuard returns nullptr.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 2307 of file X86ISelLowering.cpp.
References llvm::Module::getFunction(), llvm::TargetLoweringBase::getSSPStackGuardCheck(), llvm::X86Subtarget::getTargetTriple(), llvm::Triple::isWindowsItaniumEnvironment(), and llvm::Triple::isWindowsMSVCEnvironment().
◆ getStackProbeSymbolName()
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overridevirtual |
Returns the name of the symbol used to emit stack probes or the empty string if not applicable.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 42734 of file X86ISelLowering.cpp.
References llvm::Function::getFnAttribute(), llvm::MachineFunction::getFunction(), llvm::Attribute::getValueAsString(), llvm::Function::hasFnAttribute(), llvm::X86Subtarget::is64Bit(), llvm::X86Subtarget::isOSWindows(), llvm::X86Subtarget::isTargetCygMing(), and llvm::X86Subtarget::isTargetMachO().
Referenced by llvm::X86FrameLowering::emitPrologue(), llvm::X86FrameLowering::inlineStackProbe(), and isXor1OfSetCC().
◆ getTargetNodeName()
This method returns the name of a target specific DAG node.
Reimplemented from llvm::TargetLowering.
Definition at line 27091 of file X86ISelLowering.cpp.
References llvm::X86ISD::ADC, llvm::X86ISD::ADD, llvm::X86ISD::ADDSUB, llvm::X86ISD::AND, llvm::X86ISD::ANDNP, llvm::X86ISD::AVG, llvm::X86ISD::BEXTR, llvm::X86ISD::BLENDI, llvm::X86ISD::BLENDV, llvm::X86ISD::BRCOND, llvm::X86ISD::BSF, llvm::X86ISD::BSR, llvm::X86ISD::BT, llvm::X86ISD::BZHI, llvm::X86ISD::CALL, llvm::X86ISD::CMOV, llvm::X86ISD::CMP, llvm::X86ISD::CMPM, llvm::X86ISD::CMPM_RND, llvm::X86ISD::CMPP, llvm::X86ISD::COMI, llvm::X86ISD::COMPRESS, llvm::X86ISD::CONFLICT, llvm::X86ISD::CVTP2SI, llvm::X86ISD::CVTP2SI_RND, llvm::X86ISD::CVTP2UI, llvm::X86ISD::CVTP2UI_RND, llvm::X86ISD::CVTPH2PS, llvm::X86ISD::CVTPH2PS_RND, llvm::X86ISD::CVTPS2PH, llvm::X86ISD::CVTS2SI, llvm::X86ISD::CVTS2SI_RND, llvm::X86ISD::CVTS2UI, llvm::X86ISD::CVTS2UI_RND, llvm::X86ISD::CVTSI2P, llvm::X86ISD::CVTTP2SI, llvm::X86ISD::CVTTP2SI_RND, llvm::X86ISD::CVTTP2UI, llvm::X86ISD::CVTTP2UI_RND, llvm::X86ISD::CVTTS2SI, llvm::X86ISD::CVTTS2SI_RND, llvm::X86ISD::CVTTS2UI, llvm::X86ISD::CVTTS2UI_RND, llvm::X86ISD::CVTUI2P, llvm::X86ISD::DBPSADBW, llvm::X86ISD::EH_RETURN, llvm::X86ISD::EH_SJLJ_LONGJMP, llvm::X86ISD::EH_SJLJ_SETJMP, llvm::X86ISD::EH_SJLJ_SETUP_DISPATCH, llvm::X86ISD::EXP2, llvm::X86ISD::EXPAND, llvm::X86ISD::EXTRQI, llvm::X86ISD::FADD_RND, llvm::X86ISD::FADDS_RND, llvm::X86ISD::FAND, llvm::X86ISD::FANDN, llvm::X86ISD::FDIV_RND, llvm::X86ISD::FDIVS_RND, llvm::X86ISD::FGETEXP_RND, llvm::X86ISD::FGETEXPS_RND, llvm::X86ISD::FHADD, llvm::X86ISD::FHSUB, llvm::X86ISD::FILD, llvm::X86ISD::FILD_FLAG, llvm::X86ISD::FIRST_NUMBER, llvm::X86ISD::FLD, llvm::X86ISD::FMADD_RND, llvm::X86ISD::FMADDSUB, llvm::X86ISD::FMADDSUB_RND, llvm::X86ISD::FMAX, llvm::X86ISD::FMAX_RND, llvm::X86ISD::FMAXC, llvm::X86ISD::FMAXS, llvm::X86ISD::FMAXS_RND, llvm::X86ISD::FMIN, llvm::X86ISD::FMIN_RND, llvm::X86ISD::FMINC, llvm::X86ISD::FMINS, llvm::X86ISD::FMINS_RND, llvm::X86ISD::FMSUB, llvm::X86ISD::FMSUB_RND, llvm::X86ISD::FMSUBADD, llvm::X86ISD::FMSUBADD_RND, llvm::X86ISD::FMUL_RND, llvm::X86ISD::FMULS_RND, llvm::X86ISD::FNMADD, llvm::X86ISD::FNMADD_RND, llvm::X86ISD::FNMSUB, llvm::X86ISD::FNMSUB_RND, llvm::X86ISD::FNSTCW16m, llvm::X86ISD::FNSTSW16r, llvm::X86ISD::FOR, llvm::X86ISD::FP_TO_INT16_IN_MEM, llvm::X86ISD::FP_TO_INT32_IN_MEM, llvm::X86ISD::FP_TO_INT64_IN_MEM, llvm::X86ISD::FRCP, llvm::X86ISD::FRSQRT, llvm::X86ISD::FSETCC, llvm::X86ISD::FSETCCM, llvm::X86ISD::FSETCCM_RND, llvm::X86ISD::FSQRT_RND, llvm::X86ISD::FSQRTS_RND, llvm::X86ISD::FST, llvm::X86ISD::FSUB_RND, llvm::X86ISD::FSUBS_RND, llvm::X86ISD::FXOR, llvm::X86ISD::GF2P8AFFINEINVQB, llvm::X86ISD::GF2P8AFFINEQB, llvm::X86ISD::GF2P8MULB, llvm::X86ISD::GlobalBaseReg, llvm::X86ISD::HADD, llvm::X86ISD::HSUB, llvm::X86ISD::INSERTPS, llvm::X86ISD::INSERTQI, llvm::X86ISD::IRET, llvm::X86ISD::KADD, llvm::X86ISD::KORTEST, llvm::X86ISD::KSHIFTL, llvm::X86ISD::KSHIFTR, llvm::X86ISD::KTEST, llvm::X86ISD::LADD, llvm::X86ISD::LAND, llvm::X86ISD::LCMPXCHG16_DAG, llvm::X86ISD::LCMPXCHG16_SAVE_RBX_DAG, llvm::X86ISD::LCMPXCHG8_DAG, llvm::X86ISD::LCMPXCHG8_SAVE_EBX_DAG, llvm::X86ISD::LCMPXCHG_DAG, llvm::X86ISD::LOR, llvm::X86ISD::LSUB, llvm::X86ISD::LWPINS, llvm::X86ISD::LXOR, llvm::X86ISD::MCVTP2SI, llvm::X86ISD::MCVTP2UI, llvm::X86ISD::MCVTPS2PH, llvm::X86ISD::MCVTTP2SI, llvm::X86ISD::MCVTTP2UI, llvm::X86ISD::MEMBARRIER, llvm::X86ISD::MFENCE, llvm::X86ISD::MGATHER, llvm::X86ISD::MMX_MOVD2W, llvm::X86ISD::MMX_MOVW2D, llvm::X86ISD::MOVDDUP, llvm::X86ISD::MOVDQ2Q, llvm::X86ISD::MOVHLPS, llvm::X86ISD::MOVLHPS, llvm::X86ISD::MOVMSK, llvm::X86ISD::MOVSD, llvm::X86ISD::MOVSHDUP, llvm::X86ISD::MOVSLDUP, llvm::X86ISD::MOVSS, llvm::X86ISD::MSCATTER, llvm::X86ISD::MUL_IMM, llvm::X86ISD::MULHRS, llvm::X86ISD::MULTISHIFT, llvm::X86ISD::NT_BRIND, llvm::X86ISD::NT_CALL, llvm::X86ISD::OR, llvm::X86ISD::PACKSS, llvm::X86ISD::PACKUS, llvm::X86ISD::PALIGNR, llvm::X86ISD::PCMPEQ, llvm::X86ISD::PCMPESTR, llvm::X86ISD::PCMPGT, llvm::X86ISD::PCMPISTR, llvm::X86ISD::PEXTRB, llvm::X86ISD::PEXTRW, llvm::X86ISD::PHMINPOS, llvm::X86ISD::PINSRB, llvm::X86ISD::PINSRW, llvm::X86ISD::PMULDQ, llvm::X86ISD::PMULUDQ, llvm::X86ISD::PSADBW, llvm::X86ISD::PSHUFB, llvm::X86ISD::PSHUFD, llvm::X86ISD::PSHUFHW, llvm::X86ISD::PSHUFLW, llvm::X86ISD::PTEST, llvm::X86ISD::RCP14, llvm::X86ISD::RCP14S, llvm::X86ISD::RCP28, llvm::X86ISD::RCP28S, llvm::X86ISD::RDPMC_DAG, llvm::X86ISD::RDRAND, llvm::X86ISD::RDSEED, llvm::X86ISD::RDTSC_DAG, llvm::X86ISD::RDTSCP_DAG, llvm::X86ISD::REP_MOVS, llvm::X86ISD::REP_STOS, llvm::X86ISD::RET_FLAG, llvm::X86ISD::RSQRT14, llvm::X86ISD::RSQRT14S, llvm::X86ISD::RSQRT28, llvm::X86ISD::RSQRT28S, llvm::X86ISD::SAHF, llvm::X86ISD::SBB, llvm::X86ISD::SCALAR_SINT_TO_FP_RND, llvm::X86ISD::SCALAR_UINT_TO_FP_RND, llvm::X86ISD::SCALEF, llvm::X86ISD::SCALEFS, llvm::X86ISD::SEG_ALLOCA, llvm::X86ISD::SELECTS, llvm::X86ISD::SETCC, llvm::X86ISD::SETCC_CARRY, llvm::X86ISD::SHLD, llvm::X86ISD::SHRD, llvm::X86ISD::SHUF128, llvm::X86ISD::SHUFP, llvm::X86ISD::SINT_TO_FP_RND, llvm::X86ISD::SMUL, llvm::X86ISD::SUB, llvm::X86ISD::SUBV_BROADCAST, llvm::X86ISD::TC_RETURN, llvm::X86ISD::TESTP, llvm::X86ISD::TLSADDR, llvm::X86ISD::TLSBASEADDR, llvm::X86ISD::TLSCALL, llvm::X86ISD::TPAUSE, llvm::X86ISD::UCOMI, llvm::X86ISD::UINT_TO_FP_RND, llvm::X86ISD::UMUL, llvm::X86ISD::UMWAIT, llvm::X86ISD::UNPCKH, llvm::X86ISD::UNPCKL, llvm::X86ISD::VAARG_64, llvm::X86ISD::VALIGN, llvm::X86ISD::VASTART_SAVE_XMM_REGS, llvm::X86ISD::VBROADCAST, llvm::X86ISD::VBROADCASTM, llvm::X86ISD::VFIXUPIMM, llvm::X86ISD::VFIXUPIMMS, llvm::X86ISD::VFPCLASS, llvm::X86ISD::VFPCLASSS, llvm::X86ISD::VFPEXT, llvm::X86ISD::VFPEXT_RND, llvm::X86ISD::VFPEXTS_RND, llvm::X86ISD::VFPROUND, llvm::X86ISD::VFPROUND_RND, llvm::X86ISD::VFPROUNDS_RND, llvm::X86ISD::VGETMANT, llvm::X86ISD::VGETMANT_RND, llvm::X86ISD::VGETMANTS, llvm::X86ISD::VGETMANTS_RND, llvm::X86ISD::VMFPROUND, llvm::X86ISD::VMTRUNC, llvm::X86ISD::VMTRUNCS, llvm::X86ISD::VMTRUNCSTORES, llvm::X86ISD::VMTRUNCSTOREUS, llvm::X86ISD::VMTRUNCUS, llvm::X86ISD::VPCOM, llvm::X86ISD::VPCOMU, llvm::X86ISD::VPDPBUSD, llvm::X86ISD::VPDPBUSDS, llvm::X86ISD::VPDPWSSD, llvm::X86ISD::VPDPWSSDS, llvm::X86ISD::VPERM2X128, llvm::X86ISD::VPERMI, llvm::X86ISD::VPERMIL2, llvm::X86ISD::VPERMILPI, llvm::X86ISD::VPERMILPV, llvm::X86ISD::VPERMV, llvm::X86ISD::VPERMV3, llvm::X86ISD::VPMADD52H, llvm::X86ISD::VPMADD52L, llvm::X86ISD::VPMADDUBSW, llvm::X86ISD::VPMADDWD, llvm::X86ISD::VPPERM, llvm::X86ISD::VPSHA, llvm::X86ISD::VPSHL, llvm::X86ISD::VPSHUFBITQMB, llvm::X86ISD::VPTERNLOG, llvm::X86ISD::VRANGE, llvm::X86ISD::VRANGE_RND, llvm::X86ISD::VRANGES, llvm::X86ISD::VRANGES_RND, llvm::X86ISD::VREDUCE, llvm::X86ISD::VREDUCE_RND, llvm::X86ISD::VREDUCES, llvm::X86ISD::VREDUCES_RND, llvm::X86ISD::VRNDSCALE, llvm::X86ISD::VRNDSCALE_RND, llvm::X86ISD::VRNDSCALES, llvm::X86ISD::VRNDSCALES_RND, llvm::X86ISD::VROTLI, llvm::X86ISD::VROTRI, llvm::X86ISD::VSHL, llvm::X86ISD::VSHLD, llvm::X86ISD::VSHLDQ, llvm::X86ISD::VSHLDV, llvm::X86ISD::VSHLI, llvm::X86ISD::VSHLV, llvm::X86ISD::VSHRD, llvm::X86ISD::VSHRDV, llvm::X86ISD::VSRA, llvm::X86ISD::VSRAI, llvm::X86ISD::VSRAV, llvm::X86ISD::VSRL, llvm::X86ISD::VSRLDQ, llvm::X86ISD::VSRLI, llvm::X86ISD::VSRLV, llvm::X86ISD::VTRUNC, llvm::X86ISD::VTRUNCS, llvm::X86ISD::VTRUNCSTORES, llvm::X86ISD::VTRUNCSTOREUS, llvm::X86ISD::VTRUNCUS, llvm::X86ISD::VZEXT_LOAD, llvm::X86ISD::VZEXT_MOVL, llvm::X86ISD::WIN_ALLOCA, llvm::X86ISD::Wrapper, llvm::X86ISD::WrapperRIP, llvm::X86ISD::XOR, and llvm::X86ISD::XTEST.
◆ getTgtMemIntrinsic()
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overridevirtual |
Given an intrinsic, checks if on the target the intrinsic will need to map to a MemIntrinsicNode (touches memory).
If this is the case, it returns true and stores the intrinsic information into the IntrinsicInfo that was passed to the function.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 4781 of file X86ISelLowering.cpp.
References llvm::TargetLoweringBase::IntrinsicInfo::align, llvm::TargetLoweringBase::IntrinsicInfo::flags, llvm::CallBase::getArgOperand(), llvm::getIntrinsicWithChain(), llvm::Value::getType(), llvm::MVT::getVectorNumElements(), llvm::MVT::getVectorVT(), llvm::MVT::getVT(), llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i8, llvm::ISD::INTRINSIC_W_CHAIN, llvm::MVT::INVALID_SIMPLE_VALUE_TYPE, llvm::TargetLoweringBase::IntrinsicInfo::memVT, llvm::MachineMemOperand::MONone, llvm::MachineMemOperand::MOStore, llvm::TargetLoweringBase::IntrinsicInfo::offset, llvm::TargetLoweringBase::IntrinsicInfo::opc, llvm::TargetLoweringBase::IntrinsicInfo::ptrVal, llvm::TRUNCATE_TO_MEM_VI16, llvm::TRUNCATE_TO_MEM_VI32, llvm::TRUNCATE_TO_MEM_VI8, and llvm::IntrinsicData::Type.
◆ hasAndNot()
Return true if the target has a bitwise and-not operation: X = ~A & B This can be used to simplify select or other instructions.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 4984 of file X86ISelLowering.cpp.
References llvm::EVT::getSizeInBits(), llvm::SDValue::getValueType(), hasAndNotCompare(), llvm::X86Subtarget::hasSSE1(), llvm::X86Subtarget::hasSSE2(), llvm::EVT::isVector(), and llvm::MVT::v4i32.
◆ hasAndNotCompare()
Return true if the target should transform: (X & Y) == Y —> (~X & Y) == 0 (X & Y) != Y —> (~X & Y) != 0.
This may be profitable if the target has a bitwise and-not operation that sets comparison flags. A target may want to limit the transformation based on the type of Y or if Y is a constant.
Note that the transform will not occur if Y is known to be a power-of-2 because a mask and compare of a single bit can be handled by inverting the predicate, for example: (X & 8) == 8 —> (X & 8) != 0
Reimplemented from llvm::TargetLoweringBase.
Definition at line 4968 of file X86ISelLowering.cpp.
References llvm::SDValue::getValueType(), llvm::X86Subtarget::hasBMI(), llvm::MVT::i32, llvm::MVT::i64, llvm::EVT::isVector(), and Y.
Referenced by hasAndNot().
◆ hasBitPreservingFPLogic()
Return true if it is safe to transform an integer-domain bitwise operation into the equivalent floating-point operation.
This should be set to true if the target has IEEE-754-compliant fabs/fneg operations for the input type.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 787 of file X86ISelLowering.h.
References llvm::MVT::f32, llvm::MVT::f64, and llvm::EVT::isVector().
◆ hasFastEqualityCompare()
Vector-sized comparisons are fast using PCMPEQ + PMOVMSK or PTEST.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 5021 of file X86ISelLowering.cpp.
References llvm::MVT::getIntegerVT(), llvm::MVT::INVALID_SIMPLE_VALUE_TYPE, llvm::TargetLoweringBase::isTypeLegal(), llvm::MVT::v16i8, and llvm::MVT::v32i8.
◆ hasVectorBlend()
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inlineoverridevirtual |
Return true if the target has a vector blend instruction.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 1137 of file X86ISelLowering.h.
◆ insertSSPDeclarations()
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overridevirtual |
Inserts necessary declarations for SSP (stack protection) purpose.
Should be used only when getIRStackGuard returns nullptr.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 2275 of file X86ISelLowering.cpp.
References llvm::Module::getContext(), llvm::Type::getInt8PtrTy(), llvm::Module::getOrInsertFunction(), llvm::Module::getOrInsertGlobal(), llvm::X86Subtarget::getTargetTriple(), llvm::Type::getVoidTy(), hasStackGuardSlotTLS(), llvm::TargetLoweringBase::insertSSPDeclarations(), llvm::Triple::isWindowsItaniumEnvironment(), llvm::Triple::isWindowsMSVCEnvironment(), and llvm::CallingConv::X86_FastCall.
◆ isCheapToSpeculateCtlz()
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overridevirtual |
Return true if it is cheap to speculate a call to intrinsic ctlz.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 4928 of file X86ISelLowering.cpp.
References llvm::X86Subtarget::hasLZCNT().
◆ isCheapToSpeculateCttz()
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overridevirtual |
Return true if it is cheap to speculate a call to intrinsic cttz.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 4923 of file X86ISelLowering.cpp.
References llvm::X86Subtarget::hasBMI().
◆ isCtlzFast()
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overridevirtual |
Return true if ctlz instruction is fast.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 4959 of file X86ISelLowering.cpp.
References llvm::X86Subtarget::hasFastLZCNT().
Referenced by combineOrCmpEqZeroToCtlzSrl().
◆ isDesirableToCombineBuildVectorToShuffleTruncate()
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overridevirtual |
Reimplemented from llvm::TargetLowering.
Definition at line 41771 of file X86ISelLowering.cpp.
References assert(), llvm::EVT::getScalarSizeInBits(), llvm::EVT::getSimpleVT(), llvm::X86Subtarget::getTargetLowering(), llvm::EVT::getVectorNumElements(), llvm::X86Subtarget::hasAVX2(), is128BitLaneCrossingShuffleMask(), isShuffleMaskLegal(), and llvm::ArrayRef< T >::size().
Referenced by IsDesirableToPromoteOp().
◆ IsDesirableToPromoteOp()
Return true if the target has native support for the specified value type and it is 'desirable' to use the type.
e.g. On x86 i16 is legal, but undesirable since i16 instruction encodings are longer and some i16 instructions are slow.
Reimplemented from llvm::TargetLowering.
Definition at line 41690 of file X86ISelLowering.cpp.
References llvm::ISD::ADD, llvm::ISD::AND, llvm::ISD::ANY_EXTEND, llvm::ISD::ATOMIC_LOAD, llvm::ISD::ATOMIC_STORE, llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getValueType(), llvm::SDValue::hasOneUse(), llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i8, isDesirableToCombineBuildVectorToShuffleTruncate(), llvm::ISD::isNormalStore(), LLVM_FALLTHROUGH, llvm::SPII::Load, MayFoldLoad(), llvm::ISD::MUL, llvm::ISD::OR, llvm::ISD::SHL, llvm::ISD::SIGN_EXTEND, llvm::ISD::SRL, llvm::ISD::SUB, llvm::SDNode::use_begin(), llvm::ISD::XOR, and llvm::ISD::ZERO_EXTEND.
◆ isExtractSubvectorCheap()
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overridevirtual |
Return true if EXTRACT_SUBVECTOR is cheap for this result type with this index.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 4897 of file X86ISelLowering.cpp.
References llvm::ISD::EXTRACT_SUBVECTOR, llvm::EVT::getSizeInBits(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::MVT::i1, and llvm::TargetLoweringBase::isOperationLegalOrCustom().
◆ isFMAFasterThanFMulAndFAdd()
Return true if an FMA operation is faster than a pair of fmul and fadd instructions.
fmuladd intrinsics will be expanded to FMAs when this method returns true, otherwise fmuladd is expanded to fmul + fadd.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 27580 of file X86ISelLowering.cpp.
References llvm::MVT::f32, llvm::MVT::f64, llvm::EVT::getScalarType(), llvm::EVT::getSimpleVT(), llvm::X86Subtarget::hasAnyFMA(), llvm::EVT::isSimple(), and llvm::MVT::SimpleTy.
◆ isFPImmLegal()
Returns true if the target can instruction select the specified FP immediate natively.
If false, the legalizer will materialize the FP immediate as a load from a constant pool.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 4823 of file X86ISelLowering.cpp.
References llvm::APFloat::bitwiseIsEqual().
◆ isIntDivCheap()
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overridevirtual |
Return true if integer divide is usually cheaper than a sequence of several shifts, adds, and multiplies for this target.
The definition of "cheaper" may depend on whether we're optimizing for speed or for size.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 42666 of file X86ISelLowering.cpp.
References llvm::MachineBasicBlock::addLiveIn(), assert(), llvm::MachineBasicBlock::begin(), llvm::BuildMI(), contains(), llvm::MachineRegisterInfo::createVirtualRegister(), llvm::AttributeList::FunctionIndex, llvm::MCInstrInfo::get(), llvm::X86RegisterInfo::getCalleeSavedRegsViaCopy(), llvm::MachineFunction::getFunction(), llvm::MachineFunction::getInfo(), llvm::X86Subtarget::getInstrInfo(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), llvm::X86Subtarget::getRegisterInfo(), llvm::AttributeList::hasAttribute(), llvm::Function::hasFnAttribute(), I, llvm::X86Subtarget::is64Bit(), llvm::EVT::isVector(), llvm_unreachable, llvm::Attribute::MinSize, MRI, llvm::Attribute::NoUnwind, llvm::X86MachineFunctionInfo::setIsSplitCSR(), TII, and TRI.
◆ isLegalAddImmediate()
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overridevirtual |
Return true if the specified immediate is legal add immediate, that is the target has add instructions which can add a register and the immediate without having to materialize the immediate into a register.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 27518 of file X86ISelLowering.cpp.
References llvm::isInt< 32 >().
◆ isLegalAddressingMode()
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overridevirtual |
Return true if the addressing mode represented by AM is legal for this target, for a load/store of the specified type.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 27413 of file X86ISelLowering.cpp.
References llvm::TargetLoweringBase::AddrMode::BaseGV, llvm::TargetLoweringBase::AddrMode::BaseOffs, llvm::X86Subtarget::classifyGlobalReference(), llvm::TargetMachine::getCodeModel(), llvm::TargetLoweringBase::getTargetMachine(), llvm::TargetLoweringBase::AddrMode::HasBaseReg, llvm::X86Subtarget::is64Bit(), llvm::isGlobalRelativeToPICBase(), llvm::isGlobalStubReference(), llvm::X86::isOffsetSuitableForCodeModel(), llvm::TargetLowering::isPositionIndependent(), llvm::TargetLoweringBase::AddrMode::Scale, and llvm::CodeModel::Small.
Referenced by getScalingFactorCost().
◆ isLegalICmpImmediate()
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overridevirtual |
Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructions which can compare a register against the immediate without having to materialize the immediate into a register.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 27514 of file X86ISelLowering.cpp.
References llvm::isInt< 32 >().
◆ isLegalStoreImmediate()
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overridevirtual |
Return true if the specified immediate is legal for the value input of a store instruction.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 27523 of file X86ISelLowering.cpp.
References llvm::isInt< 32 >().
◆ isLoadBitCastBeneficial()
Return true if the following transform is beneficial: fold (conv (load x)) -> (load (conv*)x) On architectures that don't natively support some vector loads efficiently, casting the load to a smaller vector of larger types and loading is more efficient, however, this can be undone by optimizations in dag combiner.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 4933 of file X86ISelLowering.cpp.
References llvm::EVT::getVectorElementType(), llvm::X86Subtarget::hasAVX512(), llvm::X86Subtarget::hasDQI(), llvm::MVT::i1, llvm::MVT::i8, llvm::TargetLoweringBase::isLoadBitCastBeneficial(), llvm::EVT::isVector(), and llvm::MVT::v8i1.
◆ isMaskAndCmp0FoldingBeneficial()
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overridevirtual |
Return if the target supports combining a chain like:
into a single machine instruction of a form like:
Reimplemented from llvm::TargetLoweringBase.
Definition at line 4963 of file X86ISelLowering.cpp.
◆ isMultiStoresCheaperThanBitsMerge()
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inlineoverridevirtual |
Return true if it is cheaper to split the store of a merged int val from a pair of smaller values into multiple stores.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 791 of file X86ISelLowering.h.
References llvm::EVT::isFloatingPoint(), llvm::EVT::isInteger(), and Y.
◆ isNarrowingProfitable()
Return true if it's profitable to narrow operations of type VT1 to VT2.
e.g. on x86, it's profitable to narrow from i32 to i8 but not from i32 to i16.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 27600 of file X86ISelLowering.cpp.
References llvm::MVT::i16, and llvm::MVT::i32.
◆ isNoopAddrSpaceCast()
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overridevirtual |
Returns true if a cast between SrcAS and DestAS is a noop.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 2339 of file X86ISelLowering.cpp.
References assert(), llvm::CCState::CheckReturn(), and Context.
◆ isSafeMemOpType()
Returns true if it's safe to use load / store of the specified type to expand memcpy / memset inline.
This is mostly true for all types except for some special cases. For example, on X86 targets without SSE2 f64 load / store are done with fldl / fstpl which also does type conversion. Note the specified type doesn't have to be legal as the hook is used before type legalization.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 2099 of file X86ISelLowering.cpp.
References llvm::MVT::f32, and llvm::MVT::f64.
◆ isScalarFPTypeInSSEReg()
Return true if the specified scalar FP type is computed in an SSE register, not on the X87 floating point stack.
Definition at line 1035 of file X86ISelLowering.h.
References C, llvm::MVT::f32, and llvm::MVT::f64.
Referenced by BuildFILD(), getRegForInlineAsmConstraint(), isCalleeLoad(), isTruncWithZeroHighBitsInput(), LowerI64IntToFP_AVX512DQ(), lowerRegToMasks(), lowerUINT_TO_FP_vec(), and Passv64i1ArgInRegs().
◆ isShuffleMaskLegal()
Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations, those with specific masks.
By default, if a target supports the VECTOR_SHUFFLE node, all mask values are assumed to be legal.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 27609 of file X86ISelLowering.cpp.
References llvm::MVT::getScalarType(), llvm::EVT::getSimpleVT(), llvm::MVT::getSizeInBits(), llvm::MVT::i1, llvm::EVT::isSimple(), and llvm::TargetLoweringBase::isTypeLegal().
Referenced by isDesirableToCombineBuildVectorToShuffleTruncate(), and isVectorClearMaskLegal().
◆ isTruncateFree() [1/2]
Return true if it's free to truncate a value of type Ty1 to type Ty2.
e.g. On x86 it's free to truncate a i32 value in register EAX to i16 by referencing its sub-register AX.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 27492 of file X86ISelLowering.cpp.
References llvm::Type::getPrimitiveSizeInBits(), and llvm::Type::isIntegerTy().
◆ isTruncateFree() [2/2]
Reimplemented from llvm::TargetLoweringBase.
Definition at line 27527 of file X86ISelLowering.cpp.
References llvm::EVT::getSizeInBits(), and llvm::EVT::isInteger().
◆ isTypeDesirableForOp()
Return true if the target has native support for the specified value type and it is 'desirable' to use the type for the given node type.
e.g. On x86 i16 is legal, but undesirable since i16 instruction encodings are longer and some i16 instructions are slow.
Reimplemented from llvm::TargetLowering.
Definition at line 41633 of file X86ISelLowering.cpp.
References llvm::ISD::ADD, llvm::ISD::AND, llvm::ISD::ANY_EXTEND, llvm::EVT::getVectorElementType(), llvm::MVT::i16, llvm::MVT::i8, llvm::TargetLoweringBase::isTypeLegal(), llvm::EVT::isVector(), llvm::ISD::LOAD, llvm::ISD::MUL, llvm::ISD::OR, llvm::ISD::SHL, llvm::ISD::SIGN_EXTEND, llvm::ISD::SRL, llvm::ISD::SUB, llvm::ISD::XOR, and llvm::ISD::ZERO_EXTEND.
◆ isVectorClearMaskLegal()
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overridevirtual |
Similar to isShuffleMaskLegal.
Targets can use this to indicate if there is a suitable VECTOR_SHUFFLE that can be used to replace a VAND with a constant pool entry.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 27626 of file X86ISelLowering.cpp.
References llvm::X86Subtarget::hasAVX2(), isShuffleMaskLegal(), llvm::MVT::v16i16, and llvm::MVT::v32i8.
◆ isVectorLoadExtDesirable()
Return true if folding a vector load into ExtVal (a sign, zero, or any extend node) is profitable.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 27569 of file X86ISelLowering.cpp.
References llvm::SDValue::getOperand(), llvm::EVT::getScalarType(), llvm::SDValue::getValueType(), and llvm::MVT::i1.
◆ isVectorShiftByScalarCheap()
Return true if it's significantly cheaper to shift a vector by a uniform scalar than by an amount which will vary across each lane.
On x86, for example, there is a "psllw" instruction for the former case, but no simple instruction for a general "a << b" operation on vectors.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 27465 of file X86ISelLowering.cpp.
References llvm::tgtok::Bits, llvm::Type::getPrimitiveSizeInBits(), llvm::Type::getScalarSizeInBits(), llvm::X86Subtarget::hasAVX2(), llvm::X86Subtarget::hasBWI(), and llvm::X86Subtarget::hasXOP().
◆ isZExtFree() [1/3]
Return true if any actual instruction that defines a value of type Ty1 implicit zero-extends the value to Ty2 in the result register.
This does not necessarily include registers defined in unknown ways, such as incoming arguments, or copies from unknown virtual registers. Also, if isTruncateFree(Ty2, Ty1) is true, this does not necessarily apply to truncate instructions. e.g. on x86-64, all instructions that define 32-bit values implicit zero-extend the result out to 64 bits.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 27535 of file X86ISelLowering.cpp.
References llvm::X86Subtarget::is64Bit(), and llvm::Type::isIntegerTy().
Referenced by isZExtFree().
◆ isZExtFree() [2/3]
Reimplemented from llvm::TargetLoweringBase.
Definition at line 27540 of file X86ISelLowering.cpp.
References llvm::MVT::i32, llvm::MVT::i64, and llvm::X86Subtarget::is64Bit().
◆ isZExtFree() [3/3]
Return true if zero-extending the specific node Val to type VT2 is free (either because it's implicitly zero-extended such as ARM ldrb / ldrh or because it's folded such as X86 zero-extending loads).
Reimplemented from llvm::TargetLoweringBase.
Definition at line 27545 of file X86ISelLowering.cpp.
References llvm::SDValue::getOpcode(), llvm::EVT::getSimpleVT(), llvm::SDValue::getValueType(), llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i8, llvm::EVT::isInteger(), llvm::EVT::isSimple(), isZExtFree(), llvm::ISD::LOAD, and llvm::MVT::SimpleTy.
◆ LowerAsmOperandForConstraint()
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overridevirtual |
Lower the specified operand into the Ops vector.
If it is invalid, don't add anything to Ops. If hasMemory is true it means one of the asm constraint of the inline asm instruction being processed is 'm'.
If it is invalid, don't add anything to Ops.
Reimplemented from llvm::TargetLowering.
Definition at line 42139 of file X86ISelLowering.cpp.
References llvm::ISD::ADD, C, llvm::X86Subtarget::classifyGlobalReference(), llvm::SelectionDAG::getContext(), llvm::GlobalAddressSDNode::getGlobal(), llvm::Type::getInt32Ty(), llvm::SDValue::getNode(), llvm::GlobalAddressSDNode::getOffset(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getTargetConstant(), llvm::SelectionDAG::getTargetGlobalAddress(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::MVT::i64, llvm::X86Subtarget::is64Bit(), llvm::isGlobalStubReference(), llvm::isInt< 8 >(), llvm::X86Subtarget::isPICStyleGOT(), llvm::X86Subtarget::isPICStyleStubPIC(), llvm::ConstantInt::isValueValidForType(), llvm::TargetLowering::LowerAsmOperandForConstraint(), and llvm::ISD::SUB.
◆ LowerCustomJumpTableEntry()
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overridevirtual |
Reimplemented from llvm::TargetLowering.
Definition at line 2177 of file X86ISelLowering.cpp.
References assert(), llvm::MCSymbolRefExpr::create(), llvm::MachineBasicBlock::getSymbol(), llvm::X86Subtarget::isPICStyleGOT(), llvm::TargetLowering::isPositionIndependent(), and llvm::MCSymbolRefExpr::VK_GOTOFF.
◆ lowerInterleavedLoad()
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overridevirtual |
Lower interleaved load(s) into target specific instructions/intrinsics.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 803 of file X86InterleavedAccess.cpp.
References assert(), llvm::ArrayRef< T >::empty(), and llvm::ArrayRef< T >::size().
◆ lowerInterleavedStore()
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overridevirtual |
Lower interleaved store(s) into target specific instructions/intrinsics.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 820 of file X86InterleavedAccess.cpp.
References assert(), llvm::ShuffleVectorInst::getShuffleMask(), llvm::ShuffleVectorInst::getType(), llvm::Type::getVectorNumElements(), llvm::makeArrayRef(), and llvm::BitmaskEnumDetail::Mask().
◆ LowerOperation()
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overridevirtual |
Provide custom lowering hooks for some operations.
Reimplemented from llvm::TargetLowering.
Definition at line 26179 of file X86ISelLowering.cpp.
References llvm::ISD::ABS, llvm::ISD::ADD, llvm::ISD::ADDCARRY, llvm::ISD::ADDROFRETURNADDR, llvm::ISD::ADJUST_TRAMPOLINE, llvm::ISD::ANY_EXTEND, llvm::ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, llvm::ISD::ATOMIC_FENCE, llvm::ISD::ATOMIC_LOAD_ADD, llvm::ISD::ATOMIC_LOAD_AND, llvm::ISD::ATOMIC_LOAD_OR, llvm::ISD::ATOMIC_LOAD_SUB, llvm::ISD::ATOMIC_LOAD_XOR, llvm::ISD::ATOMIC_STORE, llvm::ISD::BITCAST, llvm::ISD::BITREVERSE, llvm::ISD::BlockAddress, llvm::ISD::BRCOND, llvm::ISD::BUILD_VECTOR, llvm::ISD::CONCAT_VECTORS, llvm::ISD::ConstantPool, llvm::ISD::CTLZ, llvm::ISD::CTLZ_ZERO_UNDEF, llvm::ISD::CTPOP, llvm::ISD::CTTZ, llvm::ISD::CTTZ_ZERO_UNDEF, llvm::ISD::DYNAMIC_STACKALLOC, llvm::ISD::EH_RETURN, llvm::ISD::EH_SJLJ_LONGJMP, llvm::ISD::EH_SJLJ_SETJMP, llvm::ISD::EH_SJLJ_SETUP_DISPATCH, llvm::ISD::ExternalSymbol, llvm::ISD::EXTRACT_SUBVECTOR, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::ISD::FABS, llvm::ISD::FADD, llvm::ISD::FCOPYSIGN, llvm::ISD::FGETSIGN, llvm::ISD::FLT_ROUNDS_, llvm::ISD::FNEG, llvm::ISD::FP_EXTEND, llvm::ISD::FP_TO_SINT, llvm::ISD::FP_TO_UINT, llvm::ISD::FRAME_TO_ARGS_OFFSET, llvm::ISD::FRAMEADDR, llvm::ISD::FSHL, llvm::ISD::FSHR, llvm::ISD::FSINCOS, llvm::ISD::FSUB, llvm::ISD::GC_TRANSITION_END, llvm::ISD::GC_TRANSITION_START, llvm::SDValue::getOpcode(), llvm::ISD::GlobalAddress, llvm::ISD::GlobalTLSAddress, llvm::ISD::INIT_TRAMPOLINE, llvm::ISD::INSERT_SUBVECTOR, llvm::ISD::INSERT_VECTOR_ELT, llvm::ISD::INTRINSIC_VOID, llvm::ISD::INTRINSIC_W_CHAIN, llvm::ISD::INTRINSIC_WO_CHAIN, llvm::ISD::JumpTable, llvm_unreachable, llvm::ISD::LOAD, LowerABS(), LowerADDSAT_SUBSAT(), lowerAddSub(), LowerADDSUBCARRY(), LowerADJUST_TRAMPOLINE(), LowerANY_EXTEND(), LowerATOMIC_FENCE(), LowerATOMIC_STORE(), lowerAtomicArith(), LowerBITCAST(), LowerBITREVERSE(), LowerCMP_SWAP(), LowerCONCAT_VECTORS(), LowerCTLZ(), LowerCTPOP(), LowerCTTZ(), LowerEXTEND_VECTOR_INREG(), LowerEXTRACT_SUBVECTOR(), LowerFABSorFNEG(), lowerFaddFsub(), LowerFCOPYSIGN(), LowerFGETSIGN(), LowerFP_EXTEND(), LowerFSINCOS(), LowerFunnelShift(), LowerINSERT_SUBVECTOR(), LowerINTRINSIC_W_CHAIN(), LowerLoad(), LowerMGATHER(), LowerMINMAX(), LowerMLOAD(), LowerMSCATTER(), LowerMSTORE(), LowerMUL(), LowerMULH(), LowerREADCYCLECOUNTER(), LowerRotate(), LowerSCALAR_TO_VECTOR(), LowerShift(), LowerShiftParts(), LowerSIGN_EXTEND(), LowerStore(), LowerVACOPY(), lowerVectorShuffle(), LowerXALUO(), LowerZERO_EXTEND(), llvm::ISD::MGATHER, llvm::ISD::MLOAD, llvm::ISD::MSCATTER, llvm::ISD::MSTORE, llvm::ISD::MUL, llvm::ISD::MULHS, llvm::ISD::MULHU, llvm::ISD::READCYCLECOUNTER, llvm::ISD::RETURNADDR, llvm::ISD::ROTL, llvm::ISD::ROTR, llvm::ISD::SADDO, llvm::ISD::SADDSAT, llvm::ISD::SCALAR_TO_VECTOR, llvm::ISD::SELECT, llvm::ISD::SETCC, llvm::ISD::SETCCCARRY, llvm::ISD::SHL, llvm::ISD::SHL_PARTS, llvm::ISD::SIGN_EXTEND, llvm::ISD::SIGN_EXTEND_VECTOR_INREG, llvm::ISD::SINT_TO_FP, llvm::ISD::SMAX, llvm::ISD::SMIN, llvm::ISD::SMULO, llvm::ISD::SRA, llvm::ISD::SRA_PARTS, llvm::ISD::SRL, llvm::ISD::SRL_PARTS, llvm::ISD::SSUBO, llvm::ISD::SSUBSAT, llvm::ISD::STORE, llvm::ISD::SUB, llvm::ISD::SUBCARRY, llvm::ISD::TRUNCATE, llvm::ISD::UADDO, llvm::ISD::UADDSAT, llvm::ISD::UINT_TO_FP, llvm::ISD::UMAX, llvm::ISD::UMIN, llvm::ISD::UMULO, llvm::ISD::USUBO, llvm::ISD::USUBSAT, llvm::ISD::VAARG, llvm::ISD::VACOPY, llvm::ISD::VASTART, llvm::ISD::VECTOR_SHUFFLE, llvm::ISD::VSELECT, llvm::ISD::ZERO_EXTEND, and llvm::ISD::ZERO_EXTEND_VECTOR_INREG.
Referenced by LowerOperationWrapper().
◆ LowerOperationWrapper()
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overridevirtual |
Places new result values for the node in Results (their number and types must exactly match those of the original return values of the node), or leaves Results empty, which indicates that the node is not to be custom lowered after all.
Reimplemented from llvm::TargetLowering.
Definition at line 26305 of file X86ISelLowering.cpp.
References assert(), E, llvm::SDValue::getNode(), llvm::SDNode::getNumValues(), llvm::SDValue::getValue(), I, LowerOperation(), and llvm::SmallVectorTemplateBase< T >::push_back().
◆ LowerXConstraint()
Try to replace an X constraint, which matches anything, with another that has more specific requirements based on the type of the corresponding operand.
Reimplemented from llvm::TargetLowering.
Definition at line 42124 of file X86ISelLowering.cpp.
References llvm::X86Subtarget::hasSSE1(), llvm::X86Subtarget::hasSSE2(), llvm::EVT::isFloatingPoint(), and llvm::TargetLowering::LowerXConstraint().
Referenced by getSingleConstraintMatchWeight().
◆ markLibCallAttributes()
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overridevirtual |
Reimplemented from llvm::TargetLoweringBase.
Definition at line 2148 of file X86ISelLowering.cpp.
References llvm::CallingConv::C, llvm::MachineFunction::getDataLayout(), llvm::MachineFunction::getFunction(), llvm::GlobalValue::getParent(), llvm::DataLayout::getTypeAllocSize(), llvm::X86Subtarget::is64Bit(), llvm::Type::isIntOrPtrTy(), and llvm::CallingConv::X86_StdCall.
◆ mergeStoresAfterLegalization()
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inlineoverridevirtual |
Allow store merging after legalization in addition to before legalization.
This may catch stores that do not exist earlier (eg, stores created from intrinsics).
Reimplemented from llvm::TargetLoweringBase.
Definition at line 776 of file X86ISelLowering.h.
◆ needsFixedCatchObjects()
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overridevirtual |
Reimplemented from llvm::TargetLoweringBase.
Definition at line 22949 of file X86ISelLowering.cpp.
References llvm::ISD::ADD, assert(), llvm::N86::ECX, llvm::X86ISD::EH_RETURN, llvm::X86ISD::EH_SJLJ_LONGJMP, llvm::X86ISD::EH_SJLJ_SETJMP, llvm::X86ISD::EH_SJLJ_SETUP_DISPATCH, llvm::SelectionDAG::getCopyFromReg(), llvm::SelectionDAG::getCopyToReg(), llvm::SelectionDAG::getDataLayout(), llvm::SelectionDAG::getEntryNode(), llvm::X86RegisterInfo::getFrameRegister(), llvm::X86InstrInfo::getGlobalBaseReg(), llvm::X86Subtarget::getInstrInfo(), llvm::SelectionDAG::getIntPtrConstant(), llvm::SelectionDAG::getMachineFunction(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOperand(), llvm::TargetLoweringBase::getPointerTy(), llvm::SelectionDAG::getRegister(), llvm::X86Subtarget::getRegisterInfo(), llvm::SelectionDAG::getStore(), llvm::SelectionDAG::getVTList(), llvm::MVT::i32, llvm::MVT::i64, llvm::X86Subtarget::is64Bit(), llvm::X86Subtarget::isTargetWin64(), llvm::MVT::Other, and TII.
◆ PerformDAGCombine()
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overridevirtual |
This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for.
The semantics are as follows: Return Value: SDValue.Val == 0 - No change was made SDValue.Val == N - N was replaced, is dead, and is already handled. otherwise - N should be replaced by the returned Operand.
In addition, methods provided by DAGCombinerInfo may be used to perform more complex transformations.
Reimplemented from llvm::TargetLowering.
Definition at line 41500 of file X86ISelLowering.cpp.
References llvm::X86ISD::ADC, llvm::ISD::ADD, llvm::ISD::AND, llvm::X86ISD::ANDNP, llvm::ISD::ANY_EXTEND, llvm::X86ISD::BEXTR, llvm::ISD::BITCAST, llvm::X86ISD::BLENDI, llvm::X86ISD::BLENDV, llvm::X86ISD::BRCOND, llvm::X86ISD::BT, llvm::X86ISD::CMOV, llvm::X86ISD::CMP, combineADC(), combineAdd(), combineAnd(), combineAndnp(), combineBEXTR(), combineBitcast(), combineBrCond(), combineBT(), combineCMov(), combineCMP(), combineExtractSubvector(), combineExtractVectorElt(), combineFaddFsub(), combineFAnd(), combineFAndn(), combineFMA(), combineFMADDSUB(), combineFMinFMax(), combineFMinNumFMaxNum(), combineFneg(), combineFOr(), combineGatherScatter(), combineInsertSubvector(), combineLoad(), combineMaskedLoad(), combineMaskedStore(), combineMOVMSK(), combineMul(), combineOr(), combinePMULDQ(), combineSBB(), combineScalarToVector(), combineSelect(), combineSetCC(), combineSext(), combineShift(), combineShuffle(), combineSignExtendInReg(), combineSIntToFP(), combineStore(), combineSub(), combineTruncate(), combineUIntToFP(), combineVectorCompare(), combineVectorInsert(), combineVectorPack(), combineVectorShiftImm(), combineVectorShiftVar(), combineX86INT_TO_FP(), combineX86SetCC(), combineXor(), combineZext(), llvm::X86ISD::CVTSI2P, llvm::X86ISD::CVTUI2P, llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::ISD::EXTRACT_SUBVECTOR, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::X86ISD::EXTRQI, llvm::ISD::FADD, llvm::X86ISD::FAND, llvm::X86ISD::FANDN, llvm::ISD::FMA, llvm::X86ISD::FMADD_RND, llvm::X86ISD::FMADDSUB, llvm::X86ISD::FMADDSUB_RND, llvm::X86ISD::FMAX, llvm::ISD::FMAXNUM, llvm::X86ISD::FMIN, llvm::ISD::FMINNUM, llvm::X86ISD::FMSUB, llvm::X86ISD::FMSUB_RND, llvm::X86ISD::FMSUBADD, llvm::X86ISD::FMSUBADD_RND, llvm::ISD::FNEG, llvm::X86ISD::FNMADD, llvm::X86ISD::FNMADD_RND, llvm::X86ISD::FNMSUB, llvm::X86ISD::FNMSUB_RND, llvm::X86ISD::FOR, llvm::ISD::FSUB, llvm::X86ISD::FXOR, llvm::SDNode::getOpcode(), llvm::ISD::INSERT_SUBVECTOR, llvm::X86ISD::INSERTPS, llvm::X86ISD::INSERTQI, llvm::ISD::LOAD, llvm::X86ISD::MGATHER, llvm::ISD::MGATHER, llvm::ISD::MLOAD, llvm::X86ISD::MOVDDUP, llvm::X86ISD::MOVHLPS, llvm::X86ISD::MOVLHPS, llvm::X86ISD::MOVMSK, llvm::X86ISD::MOVSD, llvm::X86ISD::MOVSHDUP, llvm::X86ISD::MOVSLDUP, llvm::X86ISD::MOVSS, llvm::X86ISD::MSCATTER, llvm::ISD::MSCATTER, llvm::ISD::MSTORE, llvm::ISD::MUL, llvm::ISD::OR, llvm::X86ISD::PACKSS, llvm::X86ISD::PACKUS, llvm::X86ISD::PALIGNR, llvm::X86ISD::PCMPEQ, llvm::X86ISD::PCMPGT, llvm::X86ISD::PEXTRB, llvm::X86ISD::PEXTRW, llvm::X86ISD::PINSRB, llvm::X86ISD::PINSRW, llvm::X86ISD::PMULDQ, llvm::X86ISD::PMULUDQ, llvm::X86ISD::PSHUFB, llvm::X86ISD::PSHUFD, llvm::X86ISD::PSHUFHW, llvm::X86ISD::PSHUFLW, llvm::X86ISD::SBB, llvm::ISD::SCALAR_TO_VECTOR, llvm::ISD::SELECT, llvm::X86ISD::SETCC, llvm::ISD::SETCC, llvm::ISD::SHL, llvm::X86ISD::SHUF128, llvm::X86ISD::SHUFP, llvm::ISD::SIGN_EXTEND, llvm::ISD::SIGN_EXTEND_INREG, llvm::ISD::SINT_TO_FP, llvm::ISD::SRA, llvm::ISD::SRL, llvm::ISD::STORE, llvm::ISD::SUB, llvm::ISD::TRUNCATE, llvm::ISD::UINT_TO_FP, llvm::X86ISD::UNPCKH, llvm::X86ISD::UNPCKL, llvm::X86ISD::VBROADCAST, llvm::ISD::VECTOR_SHUFFLE, llvm::X86ISD::VPERM2X128, llvm::X86ISD::VPERMI, llvm::X86ISD::VPERMIL2, llvm::X86ISD::VPERMILPI, llvm::X86ISD::VPERMILPV, llvm::X86ISD::VPERMV, llvm::X86ISD::VPERMV3, llvm::X86ISD::VPPERM, llvm::ISD::VSELECT, llvm::X86ISD::VSHL, llvm::X86ISD::VSHLDQ, llvm::X86ISD::VSHLI, llvm::X86ISD::VSRA, llvm::X86ISD::VSRAI, llvm::X86ISD::VSRL, llvm::X86ISD::VSRLDQ, llvm::X86ISD::VSRLI, llvm::X86ISD::VZEXT_MOVL, llvm::ISD::XOR, and llvm::ISD::ZERO_EXTEND.
◆ preferShiftsToClearExtremeBits()
There are two ways to clear extreme bits (either low or high): Mask: x & (-1 << y) (the instcombine canonical form) Shifts: x >> y << y Return true if the variant with 2 shifts is preferred.
Return false if there is no preference.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 5001 of file X86ISelLowering.cpp.
References llvm::SDValue::getValueType(), llvm::MVT::i64, llvm::X86Subtarget::is64Bit(), and llvm::EVT::isVector().
◆ reduceSelectOfFPConstantLoads()
Return true if it is profitable to convert a select of FP constants into a constant pool load whose address depends on the select condition.
The parameter may be used to differentiate a select with FP compare from integer compare.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 4855 of file X86ISelLowering.cpp.
References llvm::X86Subtarget::hasAVX(), and llvm::X86Subtarget::isTarget64BitLP64().
◆ ReplaceNodeResults()
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overridevirtual |
Replace the results of node with an illegal result type with new values built out of custom code.
Replace a node with an illegal result type with a new node built out of custom code.
Reimplemented from llvm::TargetLowering.
Definition at line 26325 of file X86ISelLowering.cpp.
References llvm::ISD::ANY_EXTEND, assert(), llvm::ISD::AssertSext, llvm::ISD::AssertZext, llvm::ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, llvm::ISD::ATOMIC_LOAD, llvm::ISD::ATOMIC_LOAD_ADD, llvm::ISD::ATOMIC_LOAD_AND, llvm::ISD::ATOMIC_LOAD_MAX, llvm::ISD::ATOMIC_LOAD_MIN, llvm::ISD::ATOMIC_LOAD_NAND, llvm::ISD::ATOMIC_LOAD_OR, llvm::ISD::ATOMIC_LOAD_SUB, llvm::ISD::ATOMIC_LOAD_UMAX, llvm::ISD::ATOMIC_LOAD_UMIN, llvm::ISD::ATOMIC_LOAD_XOR, llvm::ISD::ATOMIC_SWAP, llvm::X86ISD::AVG, llvm::ISD::BITCAST, llvm::BitsToDouble(), llvm::ISD::BUILD_PAIR, llvm::ISD::CONCAT_VECTORS, llvm::X86::COND_E, llvm::X86ISD::CVTSI2P, llvm::X86ISD::CVTTP2SI, llvm::X86ISD::CVTTP2UI, llvm::X86ISD::CVTUI2P, llvm::N86::EAX, llvm::N86::EBX, llvm::N86::ECX, llvm::N86::EDX, ExperimentalVectorWideningLegalization, llvm::ISD::EXTRACT_ELEMENT, llvm::ISD::EXTRACT_SUBVECTOR, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::MVT::f32, llvm::MVT::f64, llvm::X86ISD::FMAX, llvm::X86ISD::FMAXC, llvm::X86ISD::FMIN, llvm::X86ISD::FMINC, llvm::ISD::FP_EXTEND, llvm::ISD::FP_ROUND, llvm::ISD::FP_TO_SINT, llvm::ISD::FP_TO_UINT, llvm::ISD::FSUB, llvm::X86RegisterInfo::getBaseRegister(), llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getBuildVector(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getConstantFP(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getCopyFromReg(), llvm::SelectionDAG::getCopyToReg(), getExtendedControlRegister(), getExtendInVec(), llvm::MVT::getIntegerVT(), llvm::SelectionDAG::getIntPtrConstant(), llvm::SelectionDAG::getLoad(), llvm::SelectionDAG::getMachineFunction(), llvm::SelectionDAG::getMaskedGather(), llvm::SelectionDAG::getMemIntrinsicNode(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), getReadPerformanceCounter(), getReadTimeStampCounter(), llvm::X86Subtarget::getRegisterInfo(), llvm::EVT::getScalarSizeInBits(), llvm::EVT::getScalarType(), llvm::SelectionDAG::getSetCC(), getSETCC(), llvm::SDNode::getSimpleValueType(), llvm::EVT::getSimpleVT(), llvm::EVT::getSizeInBits(), llvm::MVT::getSizeInBits(), llvm::SelectionDAG::GetSplitDestVTs(), llvm::SelectionDAG::getTargetMemSDNode(), llvm::TargetLoweringBase::getTypeAction(), llvm::TargetLoweringBase::getTypeToTransformTo(), llvm::SelectionDAG::getUNDEF(), getUnpackh(), getUnpackl(), llvm::SDValue::getValue(), llvm::SDValue::getValueType(), llvm::SelectionDAG::getValueType(), llvm::SDNode::getValueType(), llvm::EVT::getVectorElementType(), llvm::MVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::MVT::getVectorNumElements(), llvm::SelectionDAG::getVectorShuffle(), llvm::EVT::getVectorVT(), llvm::MVT::getVectorVT(), llvm::SelectionDAG::getVTList(), llvm::SelectionDAG::getZExtOrTrunc(), llvm::MVT::Glue, llvm::X86Subtarget::hasAVX512(), llvm::X86RegisterInfo::hasBasePointer(), llvm::X86Subtarget::hasBWI(), llvm::X86Subtarget::hasDQI(), llvm::X86Subtarget::hasSSE2(), llvm::X86Subtarget::hasSSE41(), llvm::X86Subtarget::hasVLX(), llvm::MipsISD::Hi, llvm::MVT::i128, llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i64, llvm::MVT::i8, llvm::tgtok::In, llvm::ISD::INSERT_VECTOR_ELT, llvm::ISD::INTRINSIC_W_CHAIN, llvm::ISD::INTRINSIC_WO_CHAIN, llvm::X86Subtarget::is64Bit(), llvm::ISD::isConstantSplatVector(), llvm::MVT::isInteger(), llvm::ISD::isNON_EXTLoad(), llvm::TargetLoweringBase::isTypeLegal(), llvm::EVT::isVector(), llvm::MVT::isVector(), llvm::X86ISD::LCMPXCHG16_DAG, llvm::X86ISD::LCMPXCHG16_SAVE_RBX_DAG, llvm::X86ISD::LCMPXCHG8_DAG, llvm::X86ISD::LCMPXCHG8_SAVE_EBX_DAG, LLVM_FALLTHROUGH, llvm_unreachable, llvm::MipsISD::Lo, llvm::ISD::LOAD, llvm::BitmaskEnumDetail::Mask(), llvm::ISD::MGATHER, llvm::ISD::MUL, N, llvm::ISD::OR, llvm::MVT::Other, llvm::X86ISD::PMULUDQ, llvm::SmallVectorTemplateBase< T >::push_back(), llvm::X86ISD::RDTSC_DAG, llvm::X86ISD::RDTSCP_DAG, llvm::ISD::READCYCLECOUNTER, llvm::ISD::SADDSAT, llvm::ISD::SCALAR_TO_VECTOR, llvm::ISD::SDIV, llvm::ISD::SDIVREM, llvm::ISD::SETCC, llvm::ISD::SETGT, llvm::ISD::SIGN_EXTEND, llvm::ISD::SIGN_EXTEND_VECTOR_INREG, llvm::ISD::SINT_TO_FP, llvm::SM_SentinelUndef, llvm::SelectionDAG::SplitVectorOperand(), llvm::ISD::SREM, llvm::ISD::SSUBSAT, Success, TRI, llvm::ISD::TRUNCATE, llvm::TargetLoweringBase::TypePromoteInteger, llvm::TargetLoweringBase::TypeWidenVector, llvm::ISD::UADDSAT, llvm::ISD::UDIV, llvm::ISD::UDIVREM, llvm::ISD::UINT_TO_FP, llvm::ISD::UNDEF, llvm::SelectionDAG::UnrollVectorOp(), llvm::ISD::UREM, llvm::ISD::USUBSAT, llvm::MVT::v16i16, llvm::MVT::v16i32, llvm::MVT::v16i8, llvm::MVT::v2f32, llvm::MVT::v2f64, llvm::MVT::v2i1, llvm::MVT::v2i16, llvm::MVT::v2i32, llvm::MVT::v2i64, llvm::MVT::v2i8, llvm::MVT::v32i16, llvm::MVT::v32i8, llvm::MVT::v4f32, llvm::MVT::v4f64, llvm::MVT::v4i1, llvm::MVT::v4i16, llvm::MVT::v4i32, llvm::MVT::v4i64, llvm::MVT::v4i8, llvm::MVT::v64i1, llvm::MVT::v64i8, llvm::MVT::v8i64, llvm::MVT::v8i8, llvm::X86ISD::VFPROUND, llvm::X86ISD::VPMADDWD, llvm::X86ISD::VTRUNC, llvm::Intrinsic::x86_rdpmc, llvm::Intrinsic::x86_rdtsc, llvm::Intrinsic::x86_rdtscp, llvm::Intrinsic::x86_xgetbv, and llvm::ISD::ZERO_EXTEND.
◆ shouldConvertConstantLoadToIntImm()
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overridevirtual |
Returns true if it is beneficial to convert a load of a constant to just the constant itself.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 4845 of file X86ISelLowering.cpp.
References assert(), llvm::Type::getPrimitiveSizeInBits(), and llvm::Type::isIntegerTy().
◆ shouldReduceLoadWidth()
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overridevirtual |
Return true if we believe it is correct and profitable to reduce the load node to a smaller type.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 4831 of file X86ISelLowering.cpp.
References llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SPII::Load, llvm::X86II::MO_GOTTPOFF, and llvm::X86ISD::WrapperRIP.
◆ shouldScalarizeBinop()
Scalar ops always have equal or better analysis/performance/power than the vector equivalent, so this always makes sense if the scalar op is supported.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 4911 of file X86ISelLowering.cpp.
References llvm::SDValue::getOpcode(), llvm::EVT::getScalarType(), llvm::SDValue::getValueType(), and llvm::TargetLoweringBase::isOperationLegalOrCustomOrPromote().
◆ ShouldShrinkFPConstant()
If true, then instruction selection should seek to shrink the FP constant of the specified type to a smaller type in order to save space and / or reduce runtime.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 1021 of file X86ISelLowering.h.
References llvm::MVT::f80, and llvm::SPII::Load.
◆ shouldSplatInsEltVarIndex()
Return true if inserting a scalar into a variable element of an undef vector is more efficiently handled by splatting the scalar instead.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 5015 of file X86ISelLowering.cpp.
References llvm::TargetLoweringBase::isTypeLegal().
◆ shouldTransformSignedTruncationCheck()
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inlineoverridevirtual |
Should we tranform the IR-optimal check for whether given truncation down into KeptBits would be truncating or not: (add x, (1 << (KeptBits-1))) srccond (1 << KeptBits) Into it's more traditional form: ((x << C) a>> C) dstcond x Return true if we should transform.
Return false if there is no preference.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 816 of file X86ISelLowering.h.
References llvm::MVT::getIntegerVT(), llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i64, llvm::MVT::i8, and llvm::EVT::isVector().
◆ shouldUseStrictFP_TO_INT()
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overridevirtual |
Return true if it is more correct/profitable to use strict FP_TO_INT conversion operations - canonicalizing the FP source value instead of converting all cases and then selecting based on value.
This may be true if the target throws exceptions for out of bounds conversions or has fast FP CMOV.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 4891 of file X86ISelLowering.cpp.
References llvm::MVT::f80, and llvm::X86Subtarget::hasCMov().
◆ SimplifyDemandedBitsForTargetNode()
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overridevirtual |
Attempt to simplify any target nodes based on the demanded bits/elts, returning true on success.
Otherwise, analyze the expression and return a mask of KnownOne and KnownZero bits for the expression (used to simplify the caller). The KnownZero/One bits may only be accurate for those bits in the Demanded masks.
Reimplemented from llvm::TargetLowering.
Definition at line 32604 of file X86ISelLowering.cpp.
References llvm::abs(), assert(), llvm::TargetLowering::TargetLoweringOpt::CombineTo(), llvm::SelectionDAG::ComputeNumSignBits(), llvm::APInt::countLeadingZeros(), llvm::APInt::countTrailingZeros(), llvm::TargetLowering::TargetLoweringOpt::DAG, llvm::APInt::getBitWidth(), llvm::SelectionDAG::getConstant(), llvm::APInt::getLowBitsSet(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::MVT::getScalarSizeInBits(), llvm::APInt::getSignMask(), llvm::SDValue::getSimpleValueType(), llvm::SDValue::getValueType(), llvm::MVT::getVectorNumElements(), llvm::KnownBits::hasConflict(), llvm::MVT::i8, llvm::APInt::isSignMask(), llvm::APInt::lshr(), llvm::APInt::lshrInPlace(), llvm::X86ISD::MOVMSK, llvm::KnownBits::One, llvm::X86ISD::PMULDQ, llvm::X86ISD::PMULUDQ, llvm::APInt::setHighBits(), llvm::APInt::setLowBits(), llvm::APInt::setSignBit(), llvm::TargetLowering::SimplifyDemandedBits(), llvm::TargetLowering::SimplifyDemandedBitsForTargetNode(), llvm::TargetLowering::SimplifyDemandedVectorElts(), llvm::X86ISD::VSHLI, llvm::X86ISD::VSRAI, llvm::X86ISD::VSRLI, llvm::KnownBits::Zero, llvm::APInt::zextOrSelf(), and llvm::APInt::zextOrTrunc().
◆ SimplifyDemandedVectorEltsForTargetNode()
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overridevirtual |
Attempt to simplify any target nodes based on the demanded vector elements, returning true on success.
Otherwise, analyze the expression and return a mask of KnownUndef and KnownZero elements for the expression (used to simplify the caller). The KnownUndef/Zero elements may only be accurate for those bits in the DemandedMask.
Reimplemented from llvm::TargetLowering.
Definition at line 32441 of file X86ISelLowering.cpp.
References llvm::any_of(), assert(), llvm::APInt::clearAllBits(), llvm::TargetLowering::TargetLoweringOpt::CombineTo(), llvm::X86ISD::CVTSI2P, llvm::X86ISD::CVTUI2P, llvm::TargetLowering::TargetLoweringOpt::DAG, llvm::APInt::getBitWidth(), llvm::APInt::getLowBitsSet(), llvm::SDValue::getNode(), llvm::APInt::getNullValue(), llvm::APInt::getOneBitSet(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), getPackDemandedElts(), llvm::SDValue::getSimpleValueType(), llvm::EVT::getSimpleVT(), getTargetShuffleMask(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueType(), llvm::MVT::getVectorNumElements(), getZeroVector(), llvm::MVT::is128BitVector(), isSequentialOrUndefInRange(), llvm::EVT::isSimple(), isTargetShuffle(), isUndef(), isUndefInRange(), isUndefOrZeroInRange(), llvm::MVT::isVector(), LLVM_FALLTHROUGH, llvm::MipsISD::Lo, llvm::X86ISD::PACKSS, llvm::X86ISD::PACKUS, llvm::X86ISD::PSHUFB, llvm::APInt::setAllBits(), llvm::APInt::setBit(), llvm::TargetLowering::SimplifyDemandedVectorElts(), llvm::SmallVectorBase::size(), llvm::SM_SentinelUndef, llvm::SM_SentinelZero, llvm::X86ISD::VBROADCAST, llvm::X86ISD::VSHL, llvm::X86ISD::VSHLI, llvm::X86ISD::VSRA, llvm::X86ISD::VSRAI, llvm::X86ISD::VSRL, llvm::X86ISD::VSRLI, widenSubVector(), and llvm::APInt::zextOrTrunc().
◆ storeOfVectorConstantIsCheap()
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inlineoverridevirtual |
Return true if it is expected to be cheaper to do a store of a non-zero vector constant with the given size and type for the address space than to store the individual scalar element constants.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 1064 of file X86ISelLowering.h.
◆ supportSwiftError()
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overridevirtual |
Return true if the target supports swifterror attribute.
It optimizes loads and stores to reading and writing a specific register.
Reimplemented from llvm::TargetLowering.
Definition at line 42728 of file X86ISelLowering.cpp.
References llvm::X86Subtarget::is64Bit().
Referenced by llvm::X86RegisterInfo::getCalleeSavedRegs(), and llvm::X86RegisterInfo::getCallPreservedMask().
◆ targetShrinkDemandedConstant()
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overridevirtual |
Reimplemented from llvm::TargetLowering.
Definition at line 30016 of file X86ISelLowering.cpp.
References llvm::ISD::AND, C, llvm::TargetLowering::TargetLoweringOpt::CombineTo(), llvm::TargetLowering::TargetLoweringOpt::DAG, llvm::dyn_cast(), llvm::APInt::getActiveBits(), llvm::ConstantSDNode::getAPIntValue(), llvm::SelectionDAG::getConstant(), llvm::APInt::getLowBitsSet(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getSizeInBits(), llvm::SDValue::getValueType(), llvm::APInt::isSubsetOf(), llvm::EVT::isVector(), llvm::max(), llvm::PowerOf2Ceil(), and Size.
◆ unwrapAddress()
Reimplemented from llvm::TargetLowering.
Definition at line 30310 of file X86ISelLowering.cpp.
References llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), N, llvm::X86ISD::Wrapper, and llvm::X86ISD::WrapperRIP.
◆ useLoadStackGuardNode()
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overridevirtual |
If this function returns true, SelectionDAGBuilder emits a LOAD_STACK_GUARD node when it is lowering Intrinsic::stackprotector.
Reimplemented from llvm::TargetLowering.
Definition at line 1920 of file X86ISelLowering.cpp.
References llvm::X86Subtarget::is64Bit(), and llvm::X86Subtarget::isTargetMachO().
◆ useSoftFloat()
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overridevirtual |
Reimplemented from llvm::TargetLoweringBase.
Definition at line 2144 of file X86ISelLowering.cpp.
References llvm::X86Subtarget::useSoftFloat().
Referenced by X86TargetLowering().
◆ useStackGuardXorFP()
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overridevirtual |
If this function returns true, stack protection checks should XOR the frame pointer (or whichever pointer is used to address locals) into the stack guard value before checking it.
getIRStackGuard must return nullptr if this returns true.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 1924 of file X86ISelLowering.cpp.
References llvm::X86Subtarget::getTargetTriple(), and llvm::Triple::isOSMSVCRT().
The documentation for this class was generated from the following files:
- lib/Target/X86/X86ISelLowering.h
- lib/Target/X86/X86InterleavedAccess.cpp
- lib/Target/X86/X86ISelLowering.cpp
