- e -

E : BuiltinGCs.cpp
EarlyInlineAll : AMDGPUTargetMachine.cpp
EarlyLiveIntervals : TargetPassConfig.cpp
EAXThunkName : X86RetpolineThunks.cpp
ECXThunkName : X86RetpolineThunks.cpp
EDIThunkName : X86RetpolineThunks.cpp
EDXThunkName : X86RetpolineThunks.cpp
eh : PruneEH.cpp
EHTimerDescription : AsmPrinter.cpp
EHTimerName : AsmPrinter.cpp
EHWhitelist : WebAssemblyLowerEmscriptenEHSjLj.cpp
elide : CoroElide.cpp
EliminateFramePointer : HexagonFrameLowering.cpp
Elimination : ADCE.cpp , BDCE.cpp , DeadStoreElimination.cpp , TailRecursionElimination.cpp
elimination : InductiveRangeCheckElimination.cpp
Elimination : MachineCSE.cpp
EmbeddedData : MipsTargetObjectFile.cpp
EmitBranchProbability : PGOInstrumentation.cpp
emitclausemarkers : R600EmitClauseMarkers.cpp
EmitJalrReloc : MipsAsmParser.cpp , MipsABIInfo.cpp , MipsAsmPrinter.cpp , MipsFastISel.cpp , MipsISelLowering.cpp
EmitJtInText : HexagonTargetObjectFile.cpp
EmitJumpTables : HexagonISelLowering.cpp
EmitLookupTables : HexagonTargetTransformInfo.cpp
EmitLutInText : HexagonTargetObjectFile.cpp
EmptyHash : TypeHashing.cpp
EnableA53Fix835769 : AArch64TargetMachine.cpp
EnableAArch64ELFLocalDynamicTLSGeneration : AArch64ISelLowering.cpp , AArch64MCInstLower.cpp
EnableAArch64SlrGeneration : AArch64ISelLowering.cpp
EnableAASchedMI : ScheduleDAGInstrs.cpp
EnableACCForwarding : HexagonInstrInfo.cpp
EnableAddressRebalancing : HexagonISelDAGToDAG.cpp
EnableAdvSIMDScalar : AArch64TargetMachine.cpp
EnableALUForwarding : HexagonInstrInfo.cpp
EnableAMDGPUAliasAnalysis : AMDGPUTargetMachine.cpp
EnableAMDGPUFunctionCalls : AMDGPUTargetMachine.cpp
EnableAndCmpSinking : CodeGenPrepare.cpp
EnableAntiDepBreaking : PostRASchedulerList.cpp
EnableARCOptimizations : ObjCARCAnalysisUtils.cpp
EnableARM3Addr : ARMBaseInstrInfo.cpp
EnableARMLoadStoreOpt : ARMTargetMachine.cpp
EnableAtomicOptimizations : AMDGPUTargetMachine.cpp
EnableAtomicTidy : AArch64TargetMachine.cpp , ARMTargetMachine.cpp
EnableBasePointer : PPCRegisterInfo.cpp , X86RegisterInfo.cpp
EnableBitSimplify : HexagonTargetMachine.cpp
EnableBlockPlacementStats : TargetPassConfig.cpp
EnableBranchCoalescing : PPCTargetMachine.cpp
EnableBranchHint : PPCISelDAGToDAG.cpp
EnableBranchPrediction : HexagonInstrInfo.cpp
EnableBranchTargets : AArch64TargetMachine.cpp
EnableBSBSched : HexagonSubtarget.cpp
EnableCCMP : AArch64TargetMachine.cpp
EnableCExtOpt : HexagonTargetMachine.cpp
EnableCheckBankConflict : HexagonSubtarget.cpp
EnableCHR : PassBuilder.cpp , PassManagerBuilder.cpp
EnableCmovConverter : X86CmovConversion.cpp
EnableCodeSinking : InstructionCombining.cpp
EnableColdCCStressTest : GlobalOpt.cpp
EnableCollectLOH : AArch64TargetMachine.cpp
EnableCommGEP : HexagonTargetMachine.cpp
EnableCompressJumpTables : AArch64TargetMachine.cpp
EnableCondBrFoldingPass : X86TargetMachine.cpp
EnableCondBrTuning : AArch64TargetMachine.cpp
EnableCondOpt : AArch64TargetMachine.cpp
EnableCondStoresVectorization : LoopVectorize.cpp
EnableConstpoolPromotion : ARMISelLowering.cpp
EnableCountDownLoop : LoopPredication.cpp
EnableCSEInIRTranslator : IRTranslator.cpp
EnableCSEInLegalizer : Legalizer.cpp
EnableCyclicPath : MachineScheduler.cpp
Enabled : Statistic.cpp
EnableDeadRegisterElimination : AArch64TargetMachine.cpp
EnableDeferredSpilling : RegAllocGreedy.cpp
EnableDiscriminateMemops : X86DiscriminateMemOps.cpp
EnableDotCurSched : HexagonSubtarget.cpp
EnableDPPCombine : AMDGPUTargetMachine.cpp
EnableDSP : ARMCodeGenPrepare.cpp
EnableDSPWithImms : ARMCodeGenPrepare.cpp
EnableEarlyCSEMemSSA : PassBuilder.cpp , PassManagerBuilder.cpp
EnableEarlyIf : HexagonTargetMachine.cpp
EnableEarlyIfConversion : AArch64TargetMachine.cpp , AMDGPUTargetMachine.cpp
EnableEarlyIfConvert : AArch64Subtarget.cpp
EnableEmException : WebAssemblyTargetMachine.cpp
EnableEmSjLj : WebAssemblyTargetMachine.cpp
EnableExpandCondsets : HexagonTargetMachine.cpp
EnableExpensiveChecks : LegalizeTypes.cpp
EnableExpensiveCombines : InstructionCombining.cpp
EnableExtraTOCRegDeps : PPCTargetMachine.cpp
EnableFalkorHWPFFix : AArch64TargetMachine.cpp
EnableFalkorHWPFUnrollFix : AArch64TargetTransformInfo.cpp
EnableFastISelAbort : SelectionDAGISel.cpp
EnableFastISelFallbackReport : SelectionDAGISel.cpp
EnableFastISelOption : TargetPassConfig.cpp
EnableFastMath : HexagonISelLowering.cpp
EnableForwardingConflictDetection : LoopAccessAnalysis.cpp
EnableGenAllInsnClass : HexagonVLIWPacketizer.cpp
EnableGenExtract : HexagonTargetMachine.cpp
EnableGenInsert : HexagonTargetMachine.cpp
EnableGenMux : HexagonTargetMachine.cpp
EnableGenPred : HexagonTargetMachine.cpp
EnableGEPOffsetSplit : CodeGenPrepare.cpp
EnableGEPOpt : AArch64TargetMachine.cpp , PPCTargetMachine.cpp
EnableGlobalCopies : RegisterCoalescer.cpp
EnableGlobalISelAbort : TargetPassConfig.cpp
EnableGlobalISelAtO : AArch64TargetMachine.cpp
EnableGlobalISelOption : TargetPassConfig.cpp
EnableGlobalMerge : GlobalMerge.cpp , AArch64TargetMachine.cpp , ARMTargetMachine.cpp
EnableGlobalMergeOnConst : GlobalMerge.cpp
EnableGlobalMergeOnExternal : GlobalMerge.cpp
EnableGlobalSGPRAddr : SIFixupVectorISel.cpp
EnableGPRToVecSpills : PPCRegisterInfo.cpp
EnableGVNHoist : PassManagerBuilder.cpp , PassBuilder.cpp
EnableGVNSink : PassBuilder.cpp , PassManagerBuilder.cpp
EnableHCFGVerifier : VPlanVerifier.cpp
EnableHexagonBP : HexagonEarlyIfConv.cpp
EnableHexSDNodeSched : HexagonISelLowering.cpp
EnableHotColdSplit : PassBuilder.cpp , PassManagerBuilder.cpp
EnableHVX : HexagonMCTargetDesc.cpp
EnableIfConversion : LoopVectorizationLegality.cpp
EnableImplicitNullChecks : TargetPassConfig.cpp
EnableImportMetadata : FunctionImport.cpp
EnableIndVarRegisterHeur : LoopVectorize.cpp
EnableInitialCFGCleanup : HexagonTargetMachine.cpp
EnableInterleavedMemAccesses : LoopVectorize.cpp
EnableIPRA : TargetPassConfig.cpp
EnableIVTruncation : LoopPredication.cpp
EnableJoining : RegisterCoalescer.cpp
EnableJoinSplits : RegisterCoalescer.cpp
EnableLDV : LiveDebugVariables.cpp
EnableLibCallSimplify : AMDGPUTargetMachine.cpp
EnableLicmCap : LICM.cpp
EnableLinkOnceODROutlining : MachineOutliner.cpp
EnableLoadPRE : GVN.cpp
EnableLoadStoreOpt : AArch64TargetMachine.cpp
EnableLoadStoreRuntimeInterleave : LoopVectorize.cpp
EnableLoadStoreVectorizer : AMDGPUTargetMachine.cpp
EnableLocalReassignment : RegAllocGreedy.cpp
EnableLoopDataPrefetch : AArch64TargetMachine.cpp
EnableLoopDistribute : LoopDistribute.cpp
EnableLoopInterchange : PassManagerBuilder.cpp
EnableLoopPrefetch : HexagonTargetMachine.cpp
EnableLoopResched : HexagonTargetMachine.cpp
EnableLowerKernelArguments : AMDGPUTargetMachine.cpp
EnableLTOInternalization : LTOCodeGenerator.h , LTO.cpp
EnableM0Merge : SIFixSGPRCopies.cpp
EnableMachineCombinerPass : PPCTargetMachine.cpp , X86TargetMachine.cpp
EnableMachineOutliner : TargetPassConfig.cpp
EnableMachineSched : MachineScheduler.cpp
EnableMacroFusion : MacroFusion.cpp
EnableMaskedInterleavedMemAccesses : LoopVectorize.cpp
EnableMCR : AArch64TargetMachine.cpp
EnableMemAccessVersioning : LoopAccessAnalysis.cpp
EnableMemCpyDAGOpt : SelectionDAG.cpp
EnableMemDep : GVN.cpp
EnableMemOpCluster : MachineScheduler.cpp
EnableNoAliasConversion : InlineFunction.cpp
EnableNonnullArgPropagation : FunctionAttrs.cpp
EnableNonTrivialUnswitch : SimpleLoopUnswitch.cpp
EnableOptimizeLogicalImm : AArch64ISelLowering.cpp
EnablePartialOverwriteTracking : DeadStoreElimination.cpp
EnablePartialStoreMerging : DeadStoreElimination.cpp
EnablePatchPointLiveness : StackMapLivenessAnalysis.cpp
EnablePEVectorSpills : PPCFrameLowering.cpp
EnablePhiElim : LoopStrengthReduce.cpp
EnablePhiOfOps : NewGVN.cpp
EnablePostLoadHardening : X86SpeculativeLoadHardening.cpp
EnablePostRAMachineSched : MachineScheduler.cpp
EnablePostRAScheduler : PostRASchedulerList.cpp
EnablePPCColdCC : PPCTargetTransformInfo.cpp
EnablePRE : GVN.cpp
EnablePredicatedCalls : HexagonSubtarget.cpp
EnablePrefetch : PPCTargetMachine.cpp
EnablePreLink : AMDGPULibCalls.cpp
EnablePrepareForThinLTO : PassManagerBuilder.cpp
EnablePromoteConstant : AArch64TargetMachine.cpp
EnableQuadPrecision : PPCISelLowering.cpp
EnableR600IfConvert : AMDGPUTargetMachine.cpp
EnableR600StructurizeCFG : AMDGPUTargetMachine.cpp
EnableRDFOpt : HexagonTargetMachine.cpp
EnableRecPhiAnalysis : BasicAliasAnalysis.cpp
EnableRedundantCopyElimination : AArch64TargetMachine.cpp
EnableReduxCost : TargetTransformInfo.cpp
EnableRedZone : AArch64FrameLowering.cpp
EnableRegPressure : MachineScheduler.cpp
EnableRescheduling : TwoAddressInstructionPass.cpp
EnableSaveRestoreLong : HexagonFrameLowering.cpp
EnableSchedItins : TargetSchedule.cpp
EnableSchedModel : TargetSchedule.cpp
EnableScopedNoAlias : ScopedNoAliasAA.cpp
EnableSDWAPeephole : AMDGPUTargetMachine.cpp
EnableSelectionDAGSP : StackProtector.cpp
EnableSExtElimination : PPCMIPeephole.cpp
EnableShrinkWrapOpt : ShrinkWrap.cpp
EnableShrinkWrapping : HexagonFrameLowering.cpp
EnableSIModeRegisterPass : AMDGPUTargetMachine.cpp
EnableSimpleLoopUnswitch : PassManagerBuilder.cpp
EnableSpeculativeLoadHardening : X86SpeculativeLoadHardening.cpp
EnableSpillSGPRToSMEM : SIRegisterInfo.cpp
EnableSpillSGPRToVGPR : SIRegisterInfo.cpp
EnableSROA : AMDGPUTargetMachine.cpp
EnableStackOVFSanitizer : HexagonFrameLowering.cpp
EnableStaticAnalyis : HotColdSplitting.cpp
EnableStoreRefinement : NewGVN.cpp
EnableStPairSuppress : AArch64TargetMachine.cpp
EnableSubRegLiveness : MachineRegisterInfo.cpp
EnableSubregLiveness : HexagonSubtarget.cpp
EnableSWP : MachinePipeliner.cpp
EnableSWPOptSize : MachinePipeliner.cpp
EnableSyntheticCounts : PassBuilder.cpp
EnableTBAA : TypeBasedAliasAnalysis.cpp
EnableTCLatencySched : HexagonSubtarget.cpp
EnableTermFolding : LoopSimplifyCFG.cpp
EnableTimingClassLatency : HexagonInstrInfo.cpp
EnableTLSOpt : PPCISelDAGToDAG.cpp
EnableTrapUnreachable : LLVMTargetMachine.cpp
EnableTypePromotionMerge : CodeGenPrepare.cpp
EnableUnrollAndJam : PassBuilder.cpp , PassManagerBuilder.cpp
EnableUnsafeFPShrink : SimplifyLibCalls.cpp
EnableUnsafeGlobalsModRefAliasResults : GlobalsModRef.cpp
EnableUnswitchCostMultiplier : SimpleLoopUnswitch.cpp
EnableVectorPrint : HexagonTargetMachine.cpp
EnableVExtractOpt : HexagonTargetMachine.cpp
EnableVGPRIndexMode : SIISelLowering.cpp
EnableVPlanNativePath : VPlan.cpp , LoopVectorize.cpp
EnableZExtElimination : PPCMIPeephole.cpp
EncodingExpansionRegionBit : CoverageMappingReader.cpp
entry : MustExecute.cpp
EnumName : MCSectionMachO.cpp
EraseGPOpnd : MipsOptimizePICCall.cpp
error_category : Error.cpp
ErrorCategory : SampleProf.cpp , BitcodeReader.cpp , CoverageMapping.cpp , InstrProf.cpp
ErrorErrorCat : Error.cpp
ErrorHandler : ErrorHandling.cpp
ErrorHandlerMutex : ErrorHandling.cpp
ErrorHandlerUserData : ErrorHandling.cpp
ErrorMissingParenthesis : HexagonAsmParser.cpp
ErrorNoncontigiousRegister : HexagonAsmParser.cpp
esan : EfficiencySanitizer.cpp
EsanCtorAndDtorPriority : EfficiencySanitizer.cpp
EsanExitName : EfficiencySanitizer.cpp
EsanInitName : EfficiencySanitizer.cpp
EsanModuleCtorName : EfficiencySanitizer.cpp
EsanModuleDtorName : EfficiencySanitizer.cpp
EsanWhichToolName : EfficiencySanitizer.cpp
eval : AliasAnalysisEvaluator.cpp , ProvenanceAnalysisEvaluator.cpp
EvalAAMD : AliasAnalysisEvaluator.cpp
Evaluator : AliasAnalysisEvaluator.cpp
everything : MetaRenamer.cpp
evolution : ScalarEvolution.cpp
EVTs : SelectionDAG.cpp
exceptions : DwarfEHPrepare.cpp
execution : SpeculativeExecution.cpp
executionMode : jitprofiling.c
ExhaustiveSearch : RegAllocGreedy.cpp
ExitBlockBias : MachineBlockPlacement.cpp
ExpandLimit : MLxExpansionPass.cpp
expandmemcmp : ExpandMemCmp.cpp
ExpensiveAsserts : InstructionPrecedenceTracking.cpp
ExpensiveChecksEnabled : PostDominators.cpp , Dominators.cpp
ExperimentalPrefLoopAlignment : X86ISelLowering.cpp
ExperimentalVectorWideningLegalization : X86ISelLowering.cpp
ExportedFunctions : ExternalFunctions.cpp
ExportSymFlagNames : EnumTables.cpp
Expressions : GVNSink.cpp
expressions : AggressiveInstCombine.cpp
Expressions : GVNHoist.cpp
ExtensionMap : AArch64AsmParser.cpp
Extensions : ARMAsmParser.cpp
ExternSData : MipsTargetObjectFile.cpp
ExtFixups : HexagonMCCodeEmitter.cpp
extract : LoopExtractor.cpp
ExtractCutoff : HexagonGenExtract.cpp
ExtraOutliningPenalty : PartialInlining.cpp
ExtraVectorizerPasses : PassManagerBuilder.cpp
ExtraVersionPrinters : CommandLine.cpp