SI Implementation of TargetInstrInfo. More...

#include "SIInstrInfo.h"
#include "AMDGPU.h"
#include "AMDGPUIntrinsicInfo.h"
#include "AMDGPUSubtarget.h"
#include "GCNHazardRecognizer.h"
#include "SIDefines.h"
#include "SIMachineFunctionInfo.h"
#include "SIRegisterInfo.h"
#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
#include "Utils/AMDGPUBaseInfo.h"
#include "llvm/ADT/APInt.h"
#include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/StringRef.h"
#include "llvm/ADT/iterator_range.h"
#include "llvm/Analysis/AliasAnalysis.h"
#include "llvm/Analysis/MemoryLocation.h"
#include "llvm/Analysis/ValueTracking.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineDominators.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineInstrBundle.h"
#include "llvm/CodeGen/MachineMemOperand.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/RegisterScavenging.h"
#include "llvm/CodeGen/ScheduleDAG.h"
#include "llvm/CodeGen/SelectionDAGNodes.h"
#include "llvm/CodeGen/TargetOpcodes.h"
#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/IR/DebugLoc.h"
#include "llvm/IR/DiagnosticInfo.h"
#include "llvm/IR/Function.h"
#include "llvm/IR/InlineAsm.h"
#include "llvm/IR/LLVMContext.h"
#include "llvm/MC/MCInstrDesc.h"
#include "llvm/Support/Casting.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Compiler.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/MachineValueType.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Target/TargetMachine.h"
#include <cassert>
#include <cstdint>
#include <iterator>
#include <utility>
#include "AMDGPUGenInstrInfo.inc"
#include "AMDGPUGenSearchableTables.inc"

Namespaces
	llvm
	This class represents lattice values for constants.

	llvm::AMDGPU

Macros
#define	GET_INSTRINFO_CTOR_DTOR

#define	GET_D16ImageDimIntrinsics_IMPL

#define	GET_ImageDimIntrinsicTable_IMPL

#define	GET_RsrcIntrinsics_IMPL

Enumerations
enum	SIEncodingFamily { SI = 0, VI = 1, SDWA = 2, SDWA9 = 3, GFX80 = 4, GFX9 = 5 }

Functions
static unsigned	getNumOperandsNoGlue (SDNode *Node)

static SDValue	findChainOperand (SDNode *Load)

static bool	nodesHaveSameOperandValue (SDNode N0, SDNode N1, unsigned OpName)
	Returns true if both nodes have the same value for the given operand `Op`, or if both nodes do not have this operand. More...

static bool	isStride64 (unsigned Opc)

static bool	memOpsHaveSameBasePtr (const MachineInstr &MI1, const MachineOperand &BaseOp1, const MachineInstr &MI2, const MachineOperand &BaseOp2)

static void	reportIllegalCopy (const SIInstrInfo *TII, MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, bool KillSrc)

static unsigned	getSGPRSpillSaveOpcode (unsigned Size)

static unsigned	getVGPRSpillSaveOpcode (unsigned Size)

static unsigned	getSGPRSpillRestoreOpcode (unsigned Size)

static unsigned	getVGPRSpillRestoreOpcode (unsigned Size)

static MachineInstr *	swapRegAndNonRegOperand (MachineInstr &MI, MachineOperand &RegOp, MachineOperand &NonRegOp)

static void	preserveCondRegFlags (MachineOperand &CondReg, const MachineOperand &OrigCond)

static void	removeModOperands (MachineInstr &MI)

static bool	offsetsDoNotOverlap (int WidthA, int OffsetA, int WidthB, int OffsetB)

static int64_t	getFoldableImm (const MachineOperand *MO)

static bool	changesVGPRIndexingMode (const MachineInstr &MI)

static bool	compareMachineOp (const MachineOperand &Op0, const MachineOperand &Op1)

static void	copyFlagsToImplicitVCC (MachineInstr &MI, const MachineOperand &Orig)

static unsigned	findImplicitSGPRRead (const MachineInstr &MI)

static bool	shouldReadExec (const MachineInstr &MI)

static bool	isSubRegOf (const SIRegisterInfo &TRI, const MachineOperand &SuperVec, const MachineOperand &SubReg)

static void	emitLoadSRsrcFromVGPRLoop (const SIInstrInfo &TII, MachineRegisterInfo &MRI, MachineBasicBlock &OrigBB, MachineBasicBlock &LoopBB, const DebugLoc &DL, MachineOperand &Rsrc)

static void	loadSRsrcFromVGPR (const SIInstrInfo &TII, MachineInstr &MI, MachineOperand &Rsrc, MachineDominatorTree *MDT)

static std::tuple< unsigned, unsigned >	extractRsrcPtr (const SIInstrInfo &TII, MachineInstr &MI, MachineOperand &Rsrc)

static SIEncodingFamily	subtargetEncodingFamily (const GCNSubtarget &ST)

static TargetInstrInfo::RegSubRegPair	getRegOrUndef (const MachineOperand &RegOpnd)

static bool	followSubRegDef (MachineInstr &MI, TargetInstrInfo::RegSubRegPair &RSR)

Variables
static cl::opt< unsigned >	BranchOffsetBits ("amdgpu-s-branch-bits", cl::ReallyHidden, cl::init(16), cl::desc("Restrict range of branch instructions (DEBUG)"))

Detailed Description

SI Implementation of TargetInstrInfo.

Definition in file SIInstrInfo.cpp.

Macro Definition Documentation

◆ GET_D16ImageDimIntrinsics_IMPL

#define GET_D16ImageDimIntrinsics_IMPL

Definition at line 73 of file SIInstrInfo.cpp.

◆ GET_ImageDimIntrinsicTable_IMPL

#define GET_ImageDimIntrinsicTable_IMPL

Definition at line 74 of file SIInstrInfo.cpp.

◆ GET_INSTRINFO_CTOR_DTOR

#define GET_INSTRINFO_CTOR_DTOR

Definition at line 68 of file SIInstrInfo.cpp.

◆ GET_RsrcIntrinsics_IMPL

#define GET_RsrcIntrinsics_IMPL

Definition at line 75 of file SIInstrInfo.cpp.

Enumeration Type Documentation

◆ SIEncodingFamily

enum SIEncodingFamily

Enumerator
SI
VI
SDWA
SDWA9
GFX80
GFX9

Definition at line 5508 of file SIInstrInfo.cpp.

Function Documentation

◆ changesVGPRIndexingMode()

static bool changesVGPRIndexingMode ( const MachineInstr & MI )

static

Definition at line 2367 of file SIInstrInfo.cpp.

References llvm::MachineInstr::getOpcode().

Referenced by llvm::SIInstrInfo::isSchedulingBoundary().

◆ compareMachineOp()

static bool compareMachineOp	(	const MachineOperand &	Op0,
		const MachineOperand &	Op1
	)

static

Definition at line 2531 of file SIInstrInfo.cpp.

References llvm::MachineOperand::getImm(), llvm::MachineOperand::getReg(), llvm::MachineOperand::getType(), llvm_unreachable, llvm::MachineOperand::MO_Immediate, and llvm::MachineOperand::MO_Register.

Referenced by llvm::SIInstrInfo::verifyInstruction().

◆ copyFlagsToImplicitVCC()

static void copyFlagsToImplicitVCC	(	MachineInstr &	MI,
		const MachineOperand &	Orig
	)

static

Definition at line 2651 of file SIInstrInfo.cpp.

References llvm::MachineInstr::implicit_operands(), llvm::MachineOperand::isKill(), and llvm::MachineOperand::isUndef().

Referenced by llvm::SIInstrInfo::buildShrunkInst().

◆ emitLoadSRsrcFromVGPRLoop()

static void emitLoadSRsrcFromVGPRLoop	(	const SIInstrInfo &	TII,
		MachineRegisterInfo &	MRI,
		MachineBasicBlock &	OrigBB,
		MachineBasicBlock &	LoopBB,
		const DebugLoc &	DL,
		MachineOperand &	Rsrc
	)

static

Definition at line 3702 of file SIInstrInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::MachineBasicBlock::begin(), llvm::BuildMI(), llvm::MachineRegisterInfo::createVirtualRegister(), llvm::MachineBasicBlock::end(), llvm::MachineOperand::getReg(), llvm::getUndefRegState(), I, llvm::MachineOperand::isUndef(), llvm::RegState::Kill, llvm::MachineOperand::setIsKill(), llvm::MachineOperand::setReg(), and llvm::MachineRegisterInfo::setSimpleHint().

Referenced by loadSRsrcFromVGPR().

◆ extractRsrcPtr()

static std::tuple<unsigned, unsigned> extractRsrcPtr	(	const SIInstrInfo &	TII,
		MachineInstr &	MI,
		MachineOperand &	Rsrc
	)

static

Definition at line 3840 of file SIInstrInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::SIInstrInfo::buildExtractSubReg(), llvm::BuildMI(), llvm::MachineRegisterInfo::createVirtualRegister(), llvm::MachineInstr::getDebugLoc(), llvm::SIInstrInfo::getDefaultRsrcDataFormat(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), llvm::MachineFunction::getRegInfo(), and MRI.

Referenced by llvm::SIInstrInfo::legalizeOperands().

◆ findChainOperand()

static SDValue findChainOperand ( SDNode * Load )

static

Definition at line 103 of file SIInstrInfo.cpp.

References assert(), getNumOperandsNoGlue(), llvm::SDNode::getOperand(), llvm::SDValue::getValueType(), and llvm::MVT::Other.

Referenced by llvm::SIInstrInfo::areLoadsFromSameBasePtr().

◆ findImplicitSGPRRead()

static unsigned findImplicitSGPRRead ( const MachineInstr & MI )

static

Definition at line 2736 of file SIInstrInfo.cpp.

References llvm::MachineInstr::implicit_operands().

Referenced by llvm::SIInstrInfo::legalizeOperandsVOP2(), llvm::SIInstrInfo::moveToVALU(), and llvm::SIInstrInfo::verifyInstruction().

◆ followSubRegDef()

static bool followSubRegDef	(	MachineInstr &	MI,
		TargetInstrInfo::RegSubRegPair &	RSR
	)

static

Definition at line 5581 of file SIInstrInfo.cpp.

References llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), getRegOrUndef(), llvm::getRegSequenceSubReg(), llvm::TargetInstrInfo::RegSubRegPair::Reg, and llvm::TargetInstrInfo::RegSubRegPair::SubReg.

Referenced by llvm::getVRegSubRegDef().

◆ getFoldableImm()

static int64_t getFoldableImm ( const MachineOperand * MO )

static

Definition at line 2261 of file SIInstrInfo.cpp.

References llvm::tgtok::Def, llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getParent(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), llvm::MachineRegisterInfo::getUniqueVRegDef(), llvm::MachineOperand::isReg(), and MRI.

Referenced by llvm::SIInstrInfo::convertToThreeAddress().

◆ getNumOperandsNoGlue()

static unsigned getNumOperandsNoGlue ( SDNode * Node )

static

Definition at line 96 of file SIInstrInfo.cpp.

Referenced by llvm::SIInstrInfo::areLoadsFromSameBasePtr(), and findChainOperand().

◆ getRegOrUndef()

static TargetInstrInfo::RegSubRegPair getRegOrUndef ( const MachineOperand & RegOpnd )

static

Definition at line 5562 of file SIInstrInfo.cpp.

References assert(), llvm::getRegSubRegPair(), llvm::MachineOperand::isReg(), and llvm::MachineOperand::isUndef().

Referenced by followSubRegDef(), and llvm::getRegSequenceSubReg().

◆ getSGPRSpillRestoreOpcode()

static unsigned getSGPRSpillRestoreOpcode ( unsigned Size )

static

Definition at line 936 of file SIInstrInfo.cpp.

References llvm_unreachable.

Referenced by llvm::SIInstrInfo::loadRegFromStackSlot().

◆ getSGPRSpillSaveOpcode()

static unsigned getSGPRSpillSaveOpcode ( unsigned Size )

static

Definition at line 834 of file SIInstrInfo.cpp.

References llvm_unreachable.

Referenced by llvm::SIInstrInfo::storeRegToStackSlot().

◆ getVGPRSpillRestoreOpcode()

static unsigned getVGPRSpillRestoreOpcode ( unsigned Size )

static

Definition at line 953 of file SIInstrInfo.cpp.

References llvm_unreachable.

Referenced by llvm::SIInstrInfo::loadRegFromStackSlot().

◆ getVGPRSpillSaveOpcode()

static unsigned getVGPRSpillSaveOpcode ( unsigned Size )

static

Definition at line 851 of file SIInstrInfo.cpp.

References llvm_unreachable.

Referenced by llvm::SIInstrInfo::storeRegToStackSlot().

◆ isStride64()

static bool isStride64 ( unsigned Opc )

static

Definition at line 256 of file SIInstrInfo.cpp.

Referenced by llvm::SIInstrInfo::getMemOperandWithOffset().

◆ isSubRegOf()

static bool isSubRegOf	(	const SIRegisterInfo &	TRI,
		const MachineOperand &	SuperVec,
		const MachineOperand &	SubReg
	)

static

Definition at line 2779 of file SIInstrInfo.cpp.

References llvm::MachineOperand::getReg(), llvm::MachineOperand::getSubReg(), and llvm::TargetRegisterInfo::isPhysicalRegister().

Referenced by llvm::SIInstrInfo::verifyInstruction().

◆ loadSRsrcFromVGPR()

static void loadSRsrcFromVGPR	(	const SIInstrInfo &	TII,
		MachineInstr &	MI,
		MachineOperand &	Rsrc,
		MachineDominatorTree *	MDT
	)

static

Definition at line 3773 of file SIInstrInfo.cpp.

References llvm::MachineDominatorTree::addNewBlock(), llvm::MachineBasicBlock::addSuccessor(), llvm::MachineBasicBlock::begin(), llvm::BuildMI(), llvm::MachineDominatorTree::changeImmediateDominator(), llvm::MachineRegisterInfo::clearKillFlags(), llvm::MachineFunction::CreateMachineBasicBlock(), llvm::MachineRegisterInfo::createVirtualRegister(), llvm::MachineDominatorTree::dominates(), emitLoadSRsrcFromVGPRLoop(), llvm::MachineBasicBlock::end(), llvm::MachineInstr::getDebugLoc(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), llvm::MachineFunction::getRegInfo(), I, llvm::MachineFunction::insert(), MRI, llvm::MachineBasicBlock::splice(), llvm::MachineBasicBlock::successors(), llvm::MachineBasicBlock::transferSuccessorsAndUpdatePHIs(), and llvm::MachineInstr::uses().

Referenced by llvm::SIInstrInfo::legalizeOperands().

◆ memOpsHaveSameBasePtr()

static bool memOpsHaveSameBasePtr	(	const MachineInstr &	MI1,
		const MachineOperand &	BaseOp1,
		const MachineInstr &	MI2,
		const MachineOperand &	BaseOp2
	)

static

Definition at line 381 of file SIInstrInfo.cpp.

References llvm::Module::getDataLayout(), llvm::MachineFunction::getFunction(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), llvm::GlobalValue::getParent(), llvm::GetUnderlyingObject(), llvm::MachineInstr::hasOneMemOperand(), llvm::MachineOperand::isIdenticalTo(), llvm::MachineOperand::isReg(), and llvm::MachineInstr::memoperands_begin().

Referenced by llvm::SIInstrInfo::shouldClusterMemOps().

◆ nodesHaveSameOperandValue()

static bool nodesHaveSameOperandValue	(	SDNode *	N0,
		SDNode *	N1,
		unsigned	OpName
	)

static

Returns true if both nodes have the same value for the given operand Op, or if both nodes do not have this operand.

Definition at line 111 of file SIInstrInfo.cpp.

References llvm::SDNode::getMachineOpcode(), llvm::AMDGPU::getNamedOperandIdx(), and llvm::SDNode::getOperand().

Referenced by llvm::SIInstrInfo::areLoadsFromSameBasePtr().

◆ offsetsDoNotOverlap()

static bool offsetsDoNotOverlap	(	int	WidthA,
		int	OffsetA,
		int	WidthB,
		int	OffsetB
	)

static

Definition at line 2167 of file SIInstrInfo.cpp.

References llvm::SIInstrInfo::getMemOperandWithOffset(), llvm::MachineInstr::hasOneMemOperand(), llvm::MachineOperand::isIdenticalTo(), and llvm::MachineInstr::memoperands_begin().

◆ preserveCondRegFlags()

static void preserveCondRegFlags	(	MachineOperand &	CondReg,
		const MachineOperand &	OrigCond
	)

static

Definition at line 1735 of file SIInstrInfo.cpp.

References llvm::MachineOperand::isKill(), llvm::MachineOperand::isUndef(), llvm::MachineOperand::setIsKill(), and llvm::MachineOperand::setIsUndef().

Referenced by llvm::SIInstrInfo::insertBranch(), and llvm::SIInstrInfo::insertSelect().

◆ removeModOperands()

static void removeModOperands ( MachineInstr & MI )

static

Definition at line 1981 of file SIInstrInfo.cpp.

References llvm::AMDGPU::getNamedOperandIdx(), llvm::MachineInstr::getOpcode(), and llvm::MachineInstr::RemoveOperand().

Referenced by llvm::SIInstrInfo::FoldImmediate().

◆ reportIllegalCopy()

static void reportIllegalCopy	(	const SIInstrInfo *	TII,
		MachineBasicBlock &	MBB,
		MachineBasicBlock::iterator	MI,
		const DebugLoc &	DL,
		unsigned	DestReg,
		unsigned	SrcReg,
		bool	KillSrc
	)

static

Definition at line 491 of file SIInstrInfo.cpp.

References llvm::BuildMI(), C, llvm::LLVMContext::diagnose(), llvm::DS_Error, llvm::Function::getContext(), llvm::MachineFunction::getFunction(), llvm::getKillRegState(), and llvm::MachineBasicBlock::getParent().

Referenced by llvm::SIInstrInfo::copyPhysReg().

◆ shouldReadExec()

static bool shouldReadExec ( const MachineInstr & MI )

static

Definition at line 2756 of file SIInstrInfo.cpp.

References llvm::MachineInstr::getOpcode(), llvm::SIInstrInfo::isSALU(), llvm::SIInstrInfo::isSMRD(), and llvm::SIInstrInfo::isVALU().

Referenced by llvm::SIInstrInfo::verifyInstruction().

◆ subtargetEncodingFamily()

static SIEncodingFamily subtargetEncodingFamily ( const GCNSubtarget & ST )

static

Definition at line 5517 of file SIInstrInfo.cpp.

References llvm::GCNSubtarget::getGeneration(), llvm::AMDGPUSubtarget::GFX9, llvm_unreachable, llvm::AMDGPUSubtarget::SEA_ISLANDS, SI, llvm::AMDGPUSubtarget::SOUTHERN_ISLANDS, VI, and llvm::AMDGPUSubtarget::VOLCANIC_ISLANDS.

Referenced by llvm::SIInstrInfo::pseudoToMCOpcode().

◆ swapRegAndNonRegOperand()

static MachineInstr* swapRegAndNonRegOperand	(	MachineInstr &	MI,
		MachineOperand &	RegOp,
		MachineOperand &	NonRegOp
	)

static

Variable Documentation

◆ BranchOffsetBits

cl::opt<unsigned> BranchOffsetBits("amdgpu-s-branch-bits", cl::ReallyHidden, cl::init(16), cl::desc("Restrict range of branch instructions (DEBUG)"))

static

Referenced by llvm::SIInstrInfo::isBranchOffsetInRange().

Namespaces

Macros

Enumerations

Functions

Variables

Detailed Description

Macro Definition Documentation

◆ GET_D16ImageDimIntrinsics_IMPL

◆ GET_ImageDimIntrinsicTable_IMPL

◆ GET_INSTRINFO_CTOR_DTOR

◆ GET_RsrcIntrinsics_IMPL

Enumeration Type Documentation

◆ SIEncodingFamily

Function Documentation

◆ changesVGPRIndexingMode()

◆ compareMachineOp()

◆ copyFlagsToImplicitVCC()

◆ emitLoadSRsrcFromVGPRLoop()

◆ extractRsrcPtr()

◆ findChainOperand()

◆ findImplicitSGPRRead()

◆ followSubRegDef()

◆ getFoldableImm()

◆ getNumOperandsNoGlue()

◆ getRegOrUndef()

◆ getSGPRSpillRestoreOpcode()

◆ getSGPRSpillSaveOpcode()

◆ getVGPRSpillRestoreOpcode()

◆ getVGPRSpillSaveOpcode()

◆ isStride64()

◆ isSubRegOf()

◆ loadSRsrcFromVGPR()

◆ memOpsHaveSameBasePtr()

◆ nodesHaveSameOperandValue()

◆ offsetsDoNotOverlap()

◆ preserveCondRegFlags()

◆ removeModOperands()

◆ reportIllegalCopy()

◆ shouldReadExec()

◆ subtargetEncodingFamily()

◆ swapRegAndNonRegOperand()

Variable Documentation

◆ BranchOffsetBits