llvm::Intrinsic Namespace Reference

This namespace contains an enum with a value for every intrinsic/builtin function known by LLVM. More...

Classes
struct	IITDescriptor
	This is a type descriptor which explains the type requirements of an intrinsic. More...

Enumerations
enum	ID : unsigned {   not_intrinsic = 0, addressofreturnaddress, adjust_trampoline, annotation,   assume, bitreverse, bswap, canonicalize,   ceil, clear_cache, codeview_annotation, convert_from_fp16,   convert_to_fp16, copysign, coro_alloc, coro_begin,   coro_destroy, coro_done, coro_end, coro_frame,   coro_free, coro_id, coro_noop, coro_param,   coro_promise, coro_resume, coro_save, coro_size,   coro_subfn_addr, coro_suspend, cos, ctlz,   ctpop, cttz, dbg_addr, dbg_declare,   dbg_label, dbg_value, debugtrap, donothing,   eh_dwarf_cfa, eh_exceptioncode, eh_exceptionpointer, eh_recoverfp,   eh_return_i32, eh_return_i64, eh_sjlj_callsite, eh_sjlj_functioncontext,   eh_sjlj_longjmp, eh_sjlj_lsda, eh_sjlj_setjmp, eh_sjlj_setup_dispatch,   eh_typeid_for, eh_unwind_init, exp, exp2,   expect, experimental_constrained_ceil, experimental_constrained_cos, experimental_constrained_exp,   experimental_constrained_exp2, experimental_constrained_fadd, experimental_constrained_fdiv, experimental_constrained_floor,   experimental_constrained_fma, experimental_constrained_fmul, experimental_constrained_frem, experimental_constrained_fsub,   experimental_constrained_log, experimental_constrained_log10, experimental_constrained_log2, experimental_constrained_maxnum,   experimental_constrained_minnum, experimental_constrained_nearbyint, experimental_constrained_pow, experimental_constrained_powi,   experimental_constrained_rint, experimental_constrained_round, experimental_constrained_sin, experimental_constrained_sqrt,   experimental_constrained_trunc, experimental_deoptimize, experimental_gc_relocate, experimental_gc_result,   experimental_gc_statepoint, experimental_guard, experimental_patchpoint_i64, experimental_patchpoint_void,   experimental_stackmap, experimental_vector_reduce_add, experimental_vector_reduce_and, experimental_vector_reduce_fadd,   experimental_vector_reduce_fmax, experimental_vector_reduce_fmin, experimental_vector_reduce_fmul, experimental_vector_reduce_mul,   experimental_vector_reduce_or, experimental_vector_reduce_smax, experimental_vector_reduce_smin, experimental_vector_reduce_umax,   experimental_vector_reduce_umin, experimental_vector_reduce_xor, experimental_widenable_condition, fabs,   floor, flt_rounds, fma, fmuladd,   frameaddress, fshl, fshr, gcread,   gcroot, gcwrite, get_dynamic_area_offset, icall_branch_funnel,   init_trampoline, instrprof_increment, instrprof_increment_step, instrprof_value_profile,   invariant_end, invariant_start, is_constant, launder_invariant_group,   lifetime_end, lifetime_start, load_relative, localaddress,   localescape, localrecover, log, log10,   log2, longjmp, masked_compressstore, masked_expandload,   masked_gather, masked_load, masked_scatter, masked_store,   maximum, maxnum, memcpy, memcpy_element_unordered_atomic,   memmove, memmove_element_unordered_atomic, memset, memset_element_unordered_atomic,   minimum, minnum, nearbyint, objc_arc_annotation_bottomup_bbend,   objc_arc_annotation_bottomup_bbstart, objc_arc_annotation_topdown_bbend, objc_arc_annotation_topdown_bbstart, objc_autorelease,   objc_autoreleasePoolPop, objc_autoreleasePoolPush, objc_autoreleaseReturnValue, objc_clang_arc_use,   objc_copyWeak, objc_destroyWeak, objc_initWeak, objc_loadWeak,   objc_loadWeakRetained, objc_moveWeak, objc_release, objc_retain,   objc_retain_autorelease, objc_retainAutorelease, objc_retainAutoreleaseReturnValue, objc_retainAutoreleasedReturnValue,   objc_retainBlock, objc_retainedObject, objc_storeStrong, objc_storeWeak,   objc_sync_enter, objc_sync_exit, objc_unretainedObject, objc_unretainedPointer,   objc_unsafeClaimAutoreleasedReturnValue, objectsize, pcmarker, pow,   powi, prefetch, ptr_annotation, read_register,   readcyclecounter, returnaddress, rint, round,   sadd_sat, sadd_with_overflow, setjmp, sideeffect,   siglongjmp, sigsetjmp, sin, smul_fix,   smul_with_overflow, sponentry, sqrt, ssa_copy,   ssub_sat, ssub_with_overflow, stackguard, stackprotector,   stackrestore, stacksave, strip_invariant_group, thread_pointer,   trap, trunc, type_checked_load, type_test,   uadd_sat, uadd_with_overflow, umul_with_overflow, usub_sat,   usub_with_overflow, vacopy, vaend, vastart,   var_annotation, write_register, xray_customevent, xray_typedevent,   aarch64_clrex, aarch64_crc32b, aarch64_crc32cb, aarch64_crc32ch,   aarch64_crc32cw, aarch64_crc32cx, aarch64_crc32h, aarch64_crc32w,   aarch64_crc32x, aarch64_crypto_aesd, aarch64_crypto_aese, aarch64_crypto_aesimc,   aarch64_crypto_aesmc, aarch64_crypto_sha1c, aarch64_crypto_sha1h, aarch64_crypto_sha1m,   aarch64_crypto_sha1p, aarch64_crypto_sha1su0, aarch64_crypto_sha1su1, aarch64_crypto_sha256h,   aarch64_crypto_sha256h2, aarch64_crypto_sha256su0, aarch64_crypto_sha256su1, aarch64_dmb,   aarch64_dsb, aarch64_get_fpcr, aarch64_hint, aarch64_isb,   aarch64_ldaxp, aarch64_ldaxr, aarch64_ldxp, aarch64_ldxr,   aarch64_neon_abs, aarch64_neon_addhn, aarch64_neon_addp, aarch64_neon_cls,   aarch64_neon_fabd, aarch64_neon_facge, aarch64_neon_facgt, aarch64_neon_faddv,   aarch64_neon_fcvtas, aarch64_neon_fcvtau, aarch64_neon_fcvtms, aarch64_neon_fcvtmu,   aarch64_neon_fcvtns, aarch64_neon_fcvtnu, aarch64_neon_fcvtps, aarch64_neon_fcvtpu,   aarch64_neon_fcvtxn, aarch64_neon_fcvtzs, aarch64_neon_fcvtzu, aarch64_neon_fmax,   aarch64_neon_fmaxnm, aarch64_neon_fmaxnmp, aarch64_neon_fmaxnmv, aarch64_neon_fmaxp,   aarch64_neon_fmaxv, aarch64_neon_fmin, aarch64_neon_fminnm, aarch64_neon_fminnmp,   aarch64_neon_fminnmv, aarch64_neon_fminp, aarch64_neon_fminv, aarch64_neon_fmlal,   aarch64_neon_fmlal2, aarch64_neon_fmlsl, aarch64_neon_fmlsl2, aarch64_neon_fmulx,   aarch64_neon_frecpe, aarch64_neon_frecps, aarch64_neon_frecpx, aarch64_neon_frintn,   aarch64_neon_frsqrte, aarch64_neon_frsqrts, aarch64_neon_ld1x2, aarch64_neon_ld1x3,   aarch64_neon_ld1x4, aarch64_neon_ld2, aarch64_neon_ld2lane, aarch64_neon_ld2r,   aarch64_neon_ld3, aarch64_neon_ld3lane, aarch64_neon_ld3r, aarch64_neon_ld4,   aarch64_neon_ld4lane, aarch64_neon_ld4r, aarch64_neon_pmul, aarch64_neon_pmull,   aarch64_neon_pmull64, aarch64_neon_raddhn, aarch64_neon_rbit, aarch64_neon_rshrn,   aarch64_neon_rsubhn, aarch64_neon_sabd, aarch64_neon_saddlp, aarch64_neon_saddlv,   aarch64_neon_saddv, aarch64_neon_scalar_sqxtn, aarch64_neon_scalar_sqxtun, aarch64_neon_scalar_uqxtn,   aarch64_neon_sdot, aarch64_neon_shadd, aarch64_neon_shll, aarch64_neon_shsub,   aarch64_neon_smax, aarch64_neon_smaxp, aarch64_neon_smaxv, aarch64_neon_smin,   aarch64_neon_sminp, aarch64_neon_sminv, aarch64_neon_smull, aarch64_neon_sqabs,   aarch64_neon_sqadd, aarch64_neon_sqdmulh, aarch64_neon_sqdmull, aarch64_neon_sqdmulls_scalar,   aarch64_neon_sqneg, aarch64_neon_sqrdmulh, aarch64_neon_sqrshl, aarch64_neon_sqrshrn,   aarch64_neon_sqrshrun, aarch64_neon_sqshl, aarch64_neon_sqshlu, aarch64_neon_sqshrn,   aarch64_neon_sqshrun, aarch64_neon_sqsub, aarch64_neon_sqxtn, aarch64_neon_sqxtun,   aarch64_neon_srhadd, aarch64_neon_srshl, aarch64_neon_sshl, aarch64_neon_sshll,   aarch64_neon_st1x2, aarch64_neon_st1x3, aarch64_neon_st1x4, aarch64_neon_st2,   aarch64_neon_st2lane, aarch64_neon_st3, aarch64_neon_st3lane, aarch64_neon_st4,   aarch64_neon_st4lane, aarch64_neon_subhn, aarch64_neon_suqadd, aarch64_neon_tbl1,   aarch64_neon_tbl2, aarch64_neon_tbl3, aarch64_neon_tbl4, aarch64_neon_tbx1,   aarch64_neon_tbx2, aarch64_neon_tbx3, aarch64_neon_tbx4, aarch64_neon_uabd,   aarch64_neon_uaddlp, aarch64_neon_uaddlv, aarch64_neon_uaddv, aarch64_neon_udot,   aarch64_neon_uhadd, aarch64_neon_uhsub, aarch64_neon_umax, aarch64_neon_umaxp,   aarch64_neon_umaxv, aarch64_neon_umin, aarch64_neon_uminp, aarch64_neon_uminv,   aarch64_neon_umull, aarch64_neon_uqadd, aarch64_neon_uqrshl, aarch64_neon_uqrshrn,   aarch64_neon_uqshl, aarch64_neon_uqshrn, aarch64_neon_uqsub, aarch64_neon_uqxtn,   aarch64_neon_urecpe, aarch64_neon_urhadd, aarch64_neon_urshl, aarch64_neon_ursqrte,   aarch64_neon_ushl, aarch64_neon_ushll, aarch64_neon_usqadd, aarch64_neon_vcopy_lane,   aarch64_neon_vcvtfp2fxs, aarch64_neon_vcvtfp2fxu, aarch64_neon_vcvtfp2hf, aarch64_neon_vcvtfxs2fp,   aarch64_neon_vcvtfxu2fp, aarch64_neon_vcvthf2fp, aarch64_neon_vsli, aarch64_neon_vsri,   aarch64_sdiv, aarch64_sisd_fabd, aarch64_sisd_fcvtxn, aarch64_space,   aarch64_stlxp, aarch64_stlxr, aarch64_stxp, aarch64_stxr,   aarch64_udiv, amdgcn_alignbit, amdgcn_alignbyte, amdgcn_atomic_dec,   amdgcn_atomic_inc, amdgcn_buffer_atomic_add, amdgcn_buffer_atomic_and, amdgcn_buffer_atomic_cmpswap,   amdgcn_buffer_atomic_or, amdgcn_buffer_atomic_smax, amdgcn_buffer_atomic_smin, amdgcn_buffer_atomic_sub,   amdgcn_buffer_atomic_swap, amdgcn_buffer_atomic_umax, amdgcn_buffer_atomic_umin, amdgcn_buffer_atomic_xor,   amdgcn_buffer_load, amdgcn_buffer_load_format, amdgcn_buffer_store, amdgcn_buffer_store_format,   amdgcn_buffer_wbinvl1, amdgcn_buffer_wbinvl1_sc, amdgcn_buffer_wbinvl1_vol, amdgcn_class,   amdgcn_cos, amdgcn_cubeid, amdgcn_cubema, amdgcn_cubesc,   amdgcn_cubetc, amdgcn_cvt_pk_i16, amdgcn_cvt_pk_u16, amdgcn_cvt_pk_u8_f32,   amdgcn_cvt_pknorm_i16, amdgcn_cvt_pknorm_u16, amdgcn_cvt_pkrtz, amdgcn_dispatch_id,   amdgcn_dispatch_ptr, amdgcn_div_fixup, amdgcn_div_fmas, amdgcn_div_scale,   amdgcn_ds_bpermute, amdgcn_ds_fadd, amdgcn_ds_fmax, amdgcn_ds_fmin,   amdgcn_ds_ordered_add, amdgcn_ds_ordered_swap, amdgcn_ds_permute, amdgcn_ds_swizzle,   amdgcn_else, amdgcn_end_cf, amdgcn_exp, amdgcn_exp_compr,   amdgcn_fcmp, amdgcn_fdiv_fast, amdgcn_fdot2, amdgcn_fmad_ftz,   amdgcn_fmed3, amdgcn_fmul_legacy, amdgcn_fract, amdgcn_frexp_exp,   amdgcn_frexp_mant, amdgcn_groupstaticsize, amdgcn_icmp, amdgcn_if,   amdgcn_if_break, amdgcn_image_atomic_add_1d, amdgcn_image_atomic_add_1darray, amdgcn_image_atomic_add_2d,   amdgcn_image_atomic_add_2darray, amdgcn_image_atomic_add_2darraymsaa, amdgcn_image_atomic_add_2dmsaa, amdgcn_image_atomic_add_3d,   amdgcn_image_atomic_add_cube, amdgcn_image_atomic_and_1d, amdgcn_image_atomic_and_1darray, amdgcn_image_atomic_and_2d,   amdgcn_image_atomic_and_2darray, amdgcn_image_atomic_and_2darraymsaa, amdgcn_image_atomic_and_2dmsaa, amdgcn_image_atomic_and_3d,   amdgcn_image_atomic_and_cube, amdgcn_image_atomic_cmpswap_1d, amdgcn_image_atomic_cmpswap_1darray, amdgcn_image_atomic_cmpswap_2d,   amdgcn_image_atomic_cmpswap_2darray, amdgcn_image_atomic_cmpswap_2darraymsaa, amdgcn_image_atomic_cmpswap_2dmsaa, amdgcn_image_atomic_cmpswap_3d,   amdgcn_image_atomic_cmpswap_cube, amdgcn_image_atomic_dec_1d, amdgcn_image_atomic_dec_1darray, amdgcn_image_atomic_dec_2d,   amdgcn_image_atomic_dec_2darray, amdgcn_image_atomic_dec_2darraymsaa, amdgcn_image_atomic_dec_2dmsaa, amdgcn_image_atomic_dec_3d,   amdgcn_image_atomic_dec_cube, amdgcn_image_atomic_inc_1d, amdgcn_image_atomic_inc_1darray, amdgcn_image_atomic_inc_2d,   amdgcn_image_atomic_inc_2darray, amdgcn_image_atomic_inc_2darraymsaa, amdgcn_image_atomic_inc_2dmsaa, amdgcn_image_atomic_inc_3d,   amdgcn_image_atomic_inc_cube, amdgcn_image_atomic_or_1d, amdgcn_image_atomic_or_1darray, amdgcn_image_atomic_or_2d,   amdgcn_image_atomic_or_2darray, amdgcn_image_atomic_or_2darraymsaa, amdgcn_image_atomic_or_2dmsaa, amdgcn_image_atomic_or_3d,   amdgcn_image_atomic_or_cube, amdgcn_image_atomic_smax_1d, amdgcn_image_atomic_smax_1darray, amdgcn_image_atomic_smax_2d,   amdgcn_image_atomic_smax_2darray, amdgcn_image_atomic_smax_2darraymsaa, amdgcn_image_atomic_smax_2dmsaa, amdgcn_image_atomic_smax_3d,   amdgcn_image_atomic_smax_cube, amdgcn_image_atomic_smin_1d, amdgcn_image_atomic_smin_1darray, amdgcn_image_atomic_smin_2d,   amdgcn_image_atomic_smin_2darray, amdgcn_image_atomic_smin_2darraymsaa, amdgcn_image_atomic_smin_2dmsaa, amdgcn_image_atomic_smin_3d,   amdgcn_image_atomic_smin_cube, amdgcn_image_atomic_sub_1d, amdgcn_image_atomic_sub_1darray, amdgcn_image_atomic_sub_2d,   amdgcn_image_atomic_sub_2darray, amdgcn_image_atomic_sub_2darraymsaa, amdgcn_image_atomic_sub_2dmsaa, amdgcn_image_atomic_sub_3d,   amdgcn_image_atomic_sub_cube, amdgcn_image_atomic_swap_1d, amdgcn_image_atomic_swap_1darray, amdgcn_image_atomic_swap_2d,   amdgcn_image_atomic_swap_2darray, amdgcn_image_atomic_swap_2darraymsaa, amdgcn_image_atomic_swap_2dmsaa, amdgcn_image_atomic_swap_3d,   amdgcn_image_atomic_swap_cube, amdgcn_image_atomic_umax_1d, amdgcn_image_atomic_umax_1darray, amdgcn_image_atomic_umax_2d,   amdgcn_image_atomic_umax_2darray, amdgcn_image_atomic_umax_2darraymsaa, amdgcn_image_atomic_umax_2dmsaa, amdgcn_image_atomic_umax_3d,   amdgcn_image_atomic_umax_cube, amdgcn_image_atomic_umin_1d, amdgcn_image_atomic_umin_1darray, amdgcn_image_atomic_umin_2d,   amdgcn_image_atomic_umin_2darray, amdgcn_image_atomic_umin_2darraymsaa, amdgcn_image_atomic_umin_2dmsaa, amdgcn_image_atomic_umin_3d,   amdgcn_image_atomic_umin_cube, amdgcn_image_atomic_xor_1d, amdgcn_image_atomic_xor_1darray, amdgcn_image_atomic_xor_2d,   amdgcn_image_atomic_xor_2darray, amdgcn_image_atomic_xor_2darraymsaa, amdgcn_image_atomic_xor_2dmsaa, amdgcn_image_atomic_xor_3d,   amdgcn_image_atomic_xor_cube, amdgcn_image_gather4_2d, amdgcn_image_gather4_2darray, amdgcn_image_gather4_b_2d,   amdgcn_image_gather4_b_2darray, amdgcn_image_gather4_b_cl_2d, amdgcn_image_gather4_b_cl_2darray, amdgcn_image_gather4_b_cl_cube,   amdgcn_image_gather4_b_cl_o_2d, amdgcn_image_gather4_b_cl_o_2darray, amdgcn_image_gather4_b_cl_o_cube, amdgcn_image_gather4_b_cube,   amdgcn_image_gather4_b_o_2d, amdgcn_image_gather4_b_o_2darray, amdgcn_image_gather4_b_o_cube, amdgcn_image_gather4_c_2d,   amdgcn_image_gather4_c_2darray, amdgcn_image_gather4_c_b_2d, amdgcn_image_gather4_c_b_2darray, amdgcn_image_gather4_c_b_cl_2d,   amdgcn_image_gather4_c_b_cl_2darray, amdgcn_image_gather4_c_b_cl_cube, amdgcn_image_gather4_c_b_cl_o_2d, amdgcn_image_gather4_c_b_cl_o_2darray,   amdgcn_image_gather4_c_b_cl_o_cube, amdgcn_image_gather4_c_b_cube, amdgcn_image_gather4_c_b_o_2d, amdgcn_image_gather4_c_b_o_2darray,   amdgcn_image_gather4_c_b_o_cube, amdgcn_image_gather4_c_cl_2d, amdgcn_image_gather4_c_cl_2darray, amdgcn_image_gather4_c_cl_cube,   amdgcn_image_gather4_c_cl_o_2d, amdgcn_image_gather4_c_cl_o_2darray, amdgcn_image_gather4_c_cl_o_cube, amdgcn_image_gather4_c_cube,   amdgcn_image_gather4_c_l_2d, amdgcn_image_gather4_c_l_2darray, amdgcn_image_gather4_c_l_cube, amdgcn_image_gather4_c_l_o_2d,   amdgcn_image_gather4_c_l_o_2darray, amdgcn_image_gather4_c_l_o_cube, amdgcn_image_gather4_c_lz_2d, amdgcn_image_gather4_c_lz_2darray,   amdgcn_image_gather4_c_lz_cube, amdgcn_image_gather4_c_lz_o_2d, amdgcn_image_gather4_c_lz_o_2darray, amdgcn_image_gather4_c_lz_o_cube,   amdgcn_image_gather4_c_o_2d, amdgcn_image_gather4_c_o_2darray, amdgcn_image_gather4_c_o_cube, amdgcn_image_gather4_cl_2d,   amdgcn_image_gather4_cl_2darray, amdgcn_image_gather4_cl_cube, amdgcn_image_gather4_cl_o_2d, amdgcn_image_gather4_cl_o_2darray,   amdgcn_image_gather4_cl_o_cube, amdgcn_image_gather4_cube, amdgcn_image_gather4_l_2d, amdgcn_image_gather4_l_2darray,   amdgcn_image_gather4_l_cube, amdgcn_image_gather4_l_o_2d, amdgcn_image_gather4_l_o_2darray, amdgcn_image_gather4_l_o_cube,   amdgcn_image_gather4_lz_2d, amdgcn_image_gather4_lz_2darray, amdgcn_image_gather4_lz_cube, amdgcn_image_gather4_lz_o_2d,   amdgcn_image_gather4_lz_o_2darray, amdgcn_image_gather4_lz_o_cube, amdgcn_image_gather4_o_2d, amdgcn_image_gather4_o_2darray,   amdgcn_image_gather4_o_cube, amdgcn_image_getlod_1d, amdgcn_image_getlod_1darray, amdgcn_image_getlod_2d,   amdgcn_image_getlod_2darray, amdgcn_image_getlod_3d, amdgcn_image_getlod_cube, amdgcn_image_getresinfo_1d,   amdgcn_image_getresinfo_1darray, amdgcn_image_getresinfo_2d, amdgcn_image_getresinfo_2darray, amdgcn_image_getresinfo_2darraymsaa,   amdgcn_image_getresinfo_2dmsaa, amdgcn_image_getresinfo_3d, amdgcn_image_getresinfo_cube, amdgcn_image_load_1d,   amdgcn_image_load_1darray, amdgcn_image_load_2d, amdgcn_image_load_2darray, amdgcn_image_load_2darraymsaa,   amdgcn_image_load_2dmsaa, amdgcn_image_load_3d, amdgcn_image_load_cube, amdgcn_image_load_mip_1d,   amdgcn_image_load_mip_1darray, amdgcn_image_load_mip_2d, amdgcn_image_load_mip_2darray, amdgcn_image_load_mip_3d,   amdgcn_image_load_mip_cube, amdgcn_image_sample_1d, amdgcn_image_sample_1darray, amdgcn_image_sample_2d,   amdgcn_image_sample_2darray, amdgcn_image_sample_3d, amdgcn_image_sample_b_1d, amdgcn_image_sample_b_1darray,   amdgcn_image_sample_b_2d, amdgcn_image_sample_b_2darray, amdgcn_image_sample_b_3d, amdgcn_image_sample_b_cl_1d,   amdgcn_image_sample_b_cl_1darray, amdgcn_image_sample_b_cl_2d, amdgcn_image_sample_b_cl_2darray, amdgcn_image_sample_b_cl_3d,   amdgcn_image_sample_b_cl_cube, amdgcn_image_sample_b_cl_o_1d, amdgcn_image_sample_b_cl_o_1darray, amdgcn_image_sample_b_cl_o_2d,   amdgcn_image_sample_b_cl_o_2darray, amdgcn_image_sample_b_cl_o_3d, amdgcn_image_sample_b_cl_o_cube, amdgcn_image_sample_b_cube,   amdgcn_image_sample_b_o_1d, amdgcn_image_sample_b_o_1darray, amdgcn_image_sample_b_o_2d, amdgcn_image_sample_b_o_2darray,   amdgcn_image_sample_b_o_3d, amdgcn_image_sample_b_o_cube, amdgcn_image_sample_c_1d, amdgcn_image_sample_c_1darray,   amdgcn_image_sample_c_2d, amdgcn_image_sample_c_2darray, amdgcn_image_sample_c_3d, amdgcn_image_sample_c_b_1d,   amdgcn_image_sample_c_b_1darray, amdgcn_image_sample_c_b_2d, amdgcn_image_sample_c_b_2darray, amdgcn_image_sample_c_b_3d,   amdgcn_image_sample_c_b_cl_1d, amdgcn_image_sample_c_b_cl_1darray, amdgcn_image_sample_c_b_cl_2d, amdgcn_image_sample_c_b_cl_2darray,   amdgcn_image_sample_c_b_cl_3d, amdgcn_image_sample_c_b_cl_cube, amdgcn_image_sample_c_b_cl_o_1d, amdgcn_image_sample_c_b_cl_o_1darray,   amdgcn_image_sample_c_b_cl_o_2d, amdgcn_image_sample_c_b_cl_o_2darray, amdgcn_image_sample_c_b_cl_o_3d, amdgcn_image_sample_c_b_cl_o_cube,   amdgcn_image_sample_c_b_cube, amdgcn_image_sample_c_b_o_1d, amdgcn_image_sample_c_b_o_1darray, amdgcn_image_sample_c_b_o_2d,   amdgcn_image_sample_c_b_o_2darray, amdgcn_image_sample_c_b_o_3d, amdgcn_image_sample_c_b_o_cube, amdgcn_image_sample_c_cd_1d,   amdgcn_image_sample_c_cd_1darray, amdgcn_image_sample_c_cd_2d, amdgcn_image_sample_c_cd_2darray, amdgcn_image_sample_c_cd_3d,   amdgcn_image_sample_c_cd_cl_1d, amdgcn_image_sample_c_cd_cl_1darray, amdgcn_image_sample_c_cd_cl_2d, amdgcn_image_sample_c_cd_cl_2darray,   amdgcn_image_sample_c_cd_cl_3d, amdgcn_image_sample_c_cd_cl_cube, amdgcn_image_sample_c_cd_cl_o_1d, amdgcn_image_sample_c_cd_cl_o_1darray,   amdgcn_image_sample_c_cd_cl_o_2d, amdgcn_image_sample_c_cd_cl_o_2darray, amdgcn_image_sample_c_cd_cl_o_3d, amdgcn_image_sample_c_cd_cl_o_cube,   amdgcn_image_sample_c_cd_cube, amdgcn_image_sample_c_cd_o_1d, amdgcn_image_sample_c_cd_o_1darray, amdgcn_image_sample_c_cd_o_2d,   amdgcn_image_sample_c_cd_o_2darray, amdgcn_image_sample_c_cd_o_3d, amdgcn_image_sample_c_cd_o_cube, amdgcn_image_sample_c_cl_1d,   amdgcn_image_sample_c_cl_1darray, amdgcn_image_sample_c_cl_2d, amdgcn_image_sample_c_cl_2darray, amdgcn_image_sample_c_cl_3d,   amdgcn_image_sample_c_cl_cube, amdgcn_image_sample_c_cl_o_1d, amdgcn_image_sample_c_cl_o_1darray, amdgcn_image_sample_c_cl_o_2d,   amdgcn_image_sample_c_cl_o_2darray, amdgcn_image_sample_c_cl_o_3d, amdgcn_image_sample_c_cl_o_cube, amdgcn_image_sample_c_cube,   amdgcn_image_sample_c_d_1d, amdgcn_image_sample_c_d_1darray, amdgcn_image_sample_c_d_2d, amdgcn_image_sample_c_d_2darray,   amdgcn_image_sample_c_d_3d, amdgcn_image_sample_c_d_cl_1d, amdgcn_image_sample_c_d_cl_1darray, amdgcn_image_sample_c_d_cl_2d,   amdgcn_image_sample_c_d_cl_2darray, amdgcn_image_sample_c_d_cl_3d, amdgcn_image_sample_c_d_cl_cube, amdgcn_image_sample_c_d_cl_o_1d,   amdgcn_image_sample_c_d_cl_o_1darray, amdgcn_image_sample_c_d_cl_o_2d, amdgcn_image_sample_c_d_cl_o_2darray, amdgcn_image_sample_c_d_cl_o_3d,   amdgcn_image_sample_c_d_cl_o_cube, amdgcn_image_sample_c_d_cube, amdgcn_image_sample_c_d_o_1d, amdgcn_image_sample_c_d_o_1darray,   amdgcn_image_sample_c_d_o_2d, amdgcn_image_sample_c_d_o_2darray, amdgcn_image_sample_c_d_o_3d, amdgcn_image_sample_c_d_o_cube,   amdgcn_image_sample_c_l_1d, amdgcn_image_sample_c_l_1darray, amdgcn_image_sample_c_l_2d, amdgcn_image_sample_c_l_2darray,   amdgcn_image_sample_c_l_3d, amdgcn_image_sample_c_l_cube, amdgcn_image_sample_c_l_o_1d, amdgcn_image_sample_c_l_o_1darray,   amdgcn_image_sample_c_l_o_2d, amdgcn_image_sample_c_l_o_2darray, amdgcn_image_sample_c_l_o_3d, amdgcn_image_sample_c_l_o_cube,   amdgcn_image_sample_c_lz_1d, amdgcn_image_sample_c_lz_1darray, amdgcn_image_sample_c_lz_2d, amdgcn_image_sample_c_lz_2darray,   amdgcn_image_sample_c_lz_3d, amdgcn_image_sample_c_lz_cube, amdgcn_image_sample_c_lz_o_1d, amdgcn_image_sample_c_lz_o_1darray,   amdgcn_image_sample_c_lz_o_2d, amdgcn_image_sample_c_lz_o_2darray, amdgcn_image_sample_c_lz_o_3d, amdgcn_image_sample_c_lz_o_cube,   amdgcn_image_sample_c_o_1d, amdgcn_image_sample_c_o_1darray, amdgcn_image_sample_c_o_2d, amdgcn_image_sample_c_o_2darray,   amdgcn_image_sample_c_o_3d, amdgcn_image_sample_c_o_cube, amdgcn_image_sample_cd_1d, amdgcn_image_sample_cd_1darray,   amdgcn_image_sample_cd_2d, amdgcn_image_sample_cd_2darray, amdgcn_image_sample_cd_3d, amdgcn_image_sample_cd_cl_1d,   amdgcn_image_sample_cd_cl_1darray, amdgcn_image_sample_cd_cl_2d, amdgcn_image_sample_cd_cl_2darray, amdgcn_image_sample_cd_cl_3d,   amdgcn_image_sample_cd_cl_cube, amdgcn_image_sample_cd_cl_o_1d, amdgcn_image_sample_cd_cl_o_1darray, amdgcn_image_sample_cd_cl_o_2d,   amdgcn_image_sample_cd_cl_o_2darray, amdgcn_image_sample_cd_cl_o_3d, amdgcn_image_sample_cd_cl_o_cube, amdgcn_image_sample_cd_cube,   amdgcn_image_sample_cd_o_1d, amdgcn_image_sample_cd_o_1darray, amdgcn_image_sample_cd_o_2d, amdgcn_image_sample_cd_o_2darray,   amdgcn_image_sample_cd_o_3d, amdgcn_image_sample_cd_o_cube, amdgcn_image_sample_cl_1d, amdgcn_image_sample_cl_1darray,   amdgcn_image_sample_cl_2d, amdgcn_image_sample_cl_2darray, amdgcn_image_sample_cl_3d, amdgcn_image_sample_cl_cube,   amdgcn_image_sample_cl_o_1d, amdgcn_image_sample_cl_o_1darray, amdgcn_image_sample_cl_o_2d, amdgcn_image_sample_cl_o_2darray,   amdgcn_image_sample_cl_o_3d, amdgcn_image_sample_cl_o_cube, amdgcn_image_sample_cube, amdgcn_image_sample_d_1d,   amdgcn_image_sample_d_1darray, amdgcn_image_sample_d_2d, amdgcn_image_sample_d_2darray, amdgcn_image_sample_d_3d,   amdgcn_image_sample_d_cl_1d, amdgcn_image_sample_d_cl_1darray, amdgcn_image_sample_d_cl_2d, amdgcn_image_sample_d_cl_2darray,   amdgcn_image_sample_d_cl_3d, amdgcn_image_sample_d_cl_cube, amdgcn_image_sample_d_cl_o_1d, amdgcn_image_sample_d_cl_o_1darray,   amdgcn_image_sample_d_cl_o_2d, amdgcn_image_sample_d_cl_o_2darray, amdgcn_image_sample_d_cl_o_3d, amdgcn_image_sample_d_cl_o_cube,   amdgcn_image_sample_d_cube, amdgcn_image_sample_d_o_1d, amdgcn_image_sample_d_o_1darray, amdgcn_image_sample_d_o_2d,   amdgcn_image_sample_d_o_2darray, amdgcn_image_sample_d_o_3d, amdgcn_image_sample_d_o_cube, amdgcn_image_sample_l_1d,   amdgcn_image_sample_l_1darray, amdgcn_image_sample_l_2d, amdgcn_image_sample_l_2darray, amdgcn_image_sample_l_3d,   amdgcn_image_sample_l_cube, amdgcn_image_sample_l_o_1d, amdgcn_image_sample_l_o_1darray, amdgcn_image_sample_l_o_2d,   amdgcn_image_sample_l_o_2darray, amdgcn_image_sample_l_o_3d, amdgcn_image_sample_l_o_cube, amdgcn_image_sample_lz_1d,   amdgcn_image_sample_lz_1darray, amdgcn_image_sample_lz_2d, amdgcn_image_sample_lz_2darray, amdgcn_image_sample_lz_3d,   amdgcn_image_sample_lz_cube, amdgcn_image_sample_lz_o_1d, amdgcn_image_sample_lz_o_1darray, amdgcn_image_sample_lz_o_2d,   amdgcn_image_sample_lz_o_2darray, amdgcn_image_sample_lz_o_3d, amdgcn_image_sample_lz_o_cube, amdgcn_image_sample_o_1d,   amdgcn_image_sample_o_1darray, amdgcn_image_sample_o_2d, amdgcn_image_sample_o_2darray, amdgcn_image_sample_o_3d,   amdgcn_image_sample_o_cube, amdgcn_image_store_1d, amdgcn_image_store_1darray, amdgcn_image_store_2d,   amdgcn_image_store_2darray, amdgcn_image_store_2darraymsaa, amdgcn_image_store_2dmsaa, amdgcn_image_store_3d,   amdgcn_image_store_cube, amdgcn_image_store_mip_1d, amdgcn_image_store_mip_1darray, amdgcn_image_store_mip_2d,   amdgcn_image_store_mip_2darray, amdgcn_image_store_mip_3d, amdgcn_image_store_mip_cube, amdgcn_implicit_buffer_ptr,   amdgcn_implicitarg_ptr, amdgcn_init_exec, amdgcn_init_exec_from_input, amdgcn_interp_mov,   amdgcn_interp_p1, amdgcn_interp_p2, amdgcn_kernarg_segment_ptr, amdgcn_kill,   amdgcn_ldexp, amdgcn_lerp, amdgcn_log_clamp, amdgcn_loop,   amdgcn_mbcnt_hi, amdgcn_mbcnt_lo, amdgcn_mov_dpp, amdgcn_mqsad_pk_u16_u8,   amdgcn_mqsad_u32_u8, amdgcn_msad_u8, amdgcn_ps_live, amdgcn_qsad_pk_u16_u8,   amdgcn_queue_ptr, amdgcn_raw_buffer_atomic_add, amdgcn_raw_buffer_atomic_and, amdgcn_raw_buffer_atomic_cmpswap,   amdgcn_raw_buffer_atomic_or, amdgcn_raw_buffer_atomic_smax, amdgcn_raw_buffer_atomic_smin, amdgcn_raw_buffer_atomic_sub,   amdgcn_raw_buffer_atomic_swap, amdgcn_raw_buffer_atomic_umax, amdgcn_raw_buffer_atomic_umin, amdgcn_raw_buffer_atomic_xor,   amdgcn_raw_buffer_load, amdgcn_raw_buffer_load_format, amdgcn_raw_buffer_store, amdgcn_raw_buffer_store_format,   amdgcn_raw_tbuffer_load, amdgcn_raw_tbuffer_store, amdgcn_rcp, amdgcn_rcp_legacy,   amdgcn_readfirstlane, amdgcn_readlane, amdgcn_rsq, amdgcn_rsq_clamp,   amdgcn_rsq_legacy, amdgcn_s_barrier, amdgcn_s_buffer_load, amdgcn_s_dcache_inv,   amdgcn_s_dcache_inv_vol, amdgcn_s_dcache_wb, amdgcn_s_dcache_wb_vol, amdgcn_s_decperflevel,   amdgcn_s_getpc, amdgcn_s_getreg, amdgcn_s_incperflevel, amdgcn_s_memrealtime,   amdgcn_s_memtime, amdgcn_s_sendmsg, amdgcn_s_sendmsghalt, amdgcn_s_sleep,   amdgcn_s_waitcnt, amdgcn_sad_hi_u8, amdgcn_sad_u16, amdgcn_sad_u8,   amdgcn_sbfe, amdgcn_sdot2, amdgcn_sdot4, amdgcn_sdot8,   amdgcn_set_inactive, amdgcn_sffbh, amdgcn_sin, amdgcn_struct_buffer_atomic_add,   amdgcn_struct_buffer_atomic_and, amdgcn_struct_buffer_atomic_cmpswap, amdgcn_struct_buffer_atomic_or, amdgcn_struct_buffer_atomic_smax,   amdgcn_struct_buffer_atomic_smin, amdgcn_struct_buffer_atomic_sub, amdgcn_struct_buffer_atomic_swap, amdgcn_struct_buffer_atomic_umax,   amdgcn_struct_buffer_atomic_umin, amdgcn_struct_buffer_atomic_xor, amdgcn_struct_buffer_load, amdgcn_struct_buffer_load_format,   amdgcn_struct_buffer_store, amdgcn_struct_buffer_store_format, amdgcn_struct_tbuffer_load, amdgcn_struct_tbuffer_store,   amdgcn_tbuffer_load, amdgcn_tbuffer_store, amdgcn_trig_preop, amdgcn_ubfe,   amdgcn_udot2, amdgcn_udot4, amdgcn_udot8, amdgcn_unreachable,   amdgcn_update_dpp, amdgcn_wave_barrier, amdgcn_workgroup_id_x, amdgcn_workgroup_id_y,   amdgcn_workgroup_id_z, amdgcn_workitem_id_x, amdgcn_workitem_id_y, amdgcn_workitem_id_z,   amdgcn_wqm, amdgcn_wqm_vote, amdgcn_writelane, amdgcn_wwm,   arm_cdp, arm_cdp2, arm_clrex, arm_crc32b,   arm_crc32cb, arm_crc32ch, arm_crc32cw, arm_crc32h,   arm_crc32w, arm_dbg, arm_dmb, arm_dsb,   arm_get_fpscr, arm_hint, arm_isb, arm_ldaex,   arm_ldaexd, arm_ldc, arm_ldc2, arm_ldc2l,   arm_ldcl, arm_ldrex, arm_ldrexd, arm_mcr,   arm_mcr2, arm_mcrr, arm_mcrr2, arm_mrc,   arm_mrc2, arm_mrrc, arm_mrrc2, arm_neon_aesd,   arm_neon_aese, arm_neon_aesimc, arm_neon_aesmc, arm_neon_sdot,   arm_neon_sha1c, arm_neon_sha1h, arm_neon_sha1m, arm_neon_sha1p,   arm_neon_sha1su0, arm_neon_sha1su1, arm_neon_sha256h, arm_neon_sha256h2,   arm_neon_sha256su0, arm_neon_sha256su1, arm_neon_udot, arm_neon_vabds,   arm_neon_vabdu, arm_neon_vabs, arm_neon_vacge, arm_neon_vacgt,   arm_neon_vbsl, arm_neon_vcls, arm_neon_vcvtas, arm_neon_vcvtau,   arm_neon_vcvtfp2fxs, arm_neon_vcvtfp2fxu, arm_neon_vcvtfp2hf, arm_neon_vcvtfxs2fp,   arm_neon_vcvtfxu2fp, arm_neon_vcvthf2fp, arm_neon_vcvtms, arm_neon_vcvtmu,   arm_neon_vcvtns, arm_neon_vcvtnu, arm_neon_vcvtps, arm_neon_vcvtpu,   arm_neon_vhadds, arm_neon_vhaddu, arm_neon_vhsubs, arm_neon_vhsubu,   arm_neon_vld1, arm_neon_vld1x2, arm_neon_vld1x3, arm_neon_vld1x4,   arm_neon_vld2, arm_neon_vld2dup, arm_neon_vld2lane, arm_neon_vld3,   arm_neon_vld3dup, arm_neon_vld3lane, arm_neon_vld4, arm_neon_vld4dup,   arm_neon_vld4lane, arm_neon_vmaxnm, arm_neon_vmaxs, arm_neon_vmaxu,   arm_neon_vminnm, arm_neon_vmins, arm_neon_vminu, arm_neon_vmullp,   arm_neon_vmulls, arm_neon_vmullu, arm_neon_vmulp, arm_neon_vpadals,   arm_neon_vpadalu, arm_neon_vpadd, arm_neon_vpaddls, arm_neon_vpaddlu,   arm_neon_vpmaxs, arm_neon_vpmaxu, arm_neon_vpmins, arm_neon_vpminu,   arm_neon_vqabs, arm_neon_vqadds, arm_neon_vqaddu, arm_neon_vqdmulh,   arm_neon_vqdmull, arm_neon_vqmovns, arm_neon_vqmovnsu, arm_neon_vqmovnu,   arm_neon_vqneg, arm_neon_vqrdmulh, arm_neon_vqrshiftns, arm_neon_vqrshiftnsu,   arm_neon_vqrshiftnu, arm_neon_vqrshifts, arm_neon_vqrshiftu, arm_neon_vqshiftns,   arm_neon_vqshiftnsu, arm_neon_vqshiftnu, arm_neon_vqshifts, arm_neon_vqshiftsu,   arm_neon_vqshiftu, arm_neon_vqsubs, arm_neon_vqsubu, arm_neon_vraddhn,   arm_neon_vrecpe, arm_neon_vrecps, arm_neon_vrhadds, arm_neon_vrhaddu,   arm_neon_vrinta, arm_neon_vrintm, arm_neon_vrintn, arm_neon_vrintp,   arm_neon_vrintx, arm_neon_vrintz, arm_neon_vrshiftn, arm_neon_vrshifts,   arm_neon_vrshiftu, arm_neon_vrsqrte, arm_neon_vrsqrts, arm_neon_vrsubhn,   arm_neon_vshiftins, arm_neon_vshifts, arm_neon_vshiftu, arm_neon_vst1,   arm_neon_vst1x2, arm_neon_vst1x3, arm_neon_vst1x4, arm_neon_vst2,   arm_neon_vst2lane, arm_neon_vst3, arm_neon_vst3lane, arm_neon_vst4,   arm_neon_vst4lane, arm_neon_vtbl1, arm_neon_vtbl2, arm_neon_vtbl3,   arm_neon_vtbl4, arm_neon_vtbx1, arm_neon_vtbx2, arm_neon_vtbx3,   arm_neon_vtbx4, arm_qadd, arm_qadd16, arm_qadd8,   arm_qasx, arm_qsax, arm_qsub, arm_qsub16,   arm_qsub8, arm_sadd16, arm_sadd8, arm_sasx,   arm_sel, arm_set_fpscr, arm_shadd16, arm_shadd8,   arm_shasx, arm_shsax, arm_shsub16, arm_shsub8,   arm_smlabb, arm_smlabt, arm_smlad, arm_smladx,   arm_smlald, arm_smlaldx, arm_smlatb, arm_smlatt,   arm_smlawb, arm_smlawt, arm_smlsd, arm_smlsdx,   arm_smlsld, arm_smlsldx, arm_smuad, arm_smuadx,   arm_smulbb, arm_smulbt, arm_smultb, arm_smultt,   arm_smulwb, arm_smulwt, arm_smusd, arm_smusdx,   arm_space, arm_ssat, arm_ssat16, arm_ssax,   arm_ssub16, arm_ssub8, arm_stc, arm_stc2,   arm_stc2l, arm_stcl, arm_stlex, arm_stlexd,   arm_strex, arm_strexd, arm_sxtab16, arm_sxtb16,   arm_uadd16, arm_uadd8, arm_uasx, arm_uhadd16,   arm_uhadd8, arm_uhasx, arm_uhsax, arm_uhsub16,   arm_uhsub8, arm_undefined, arm_uqadd16, arm_uqadd8,   arm_uqasx, arm_uqsax, arm_uqsub16, arm_uqsub8,   arm_usad8, arm_usada8, arm_usat, arm_usat16,   arm_usax, arm_usub16, arm_usub8, arm_uxtab16,   arm_uxtb16, arm_vcvtr, arm_vcvtru, bpf_load_byte,   bpf_load_half, bpf_load_word, bpf_pseudo, hexagon_A2_abs,   hexagon_A2_absp, hexagon_A2_abssat, hexagon_A2_add, hexagon_A2_addh_h16_hh,   hexagon_A2_addh_h16_hl, hexagon_A2_addh_h16_lh, hexagon_A2_addh_h16_ll, hexagon_A2_addh_h16_sat_hh,   hexagon_A2_addh_h16_sat_hl, hexagon_A2_addh_h16_sat_lh, hexagon_A2_addh_h16_sat_ll, hexagon_A2_addh_l16_hl,   hexagon_A2_addh_l16_ll, hexagon_A2_addh_l16_sat_hl, hexagon_A2_addh_l16_sat_ll, hexagon_A2_addi,   hexagon_A2_addp, hexagon_A2_addpsat, hexagon_A2_addsat, hexagon_A2_addsp,   hexagon_A2_and, hexagon_A2_andir, hexagon_A2_andp, hexagon_A2_aslh,   hexagon_A2_asrh, hexagon_A2_combine_hh, hexagon_A2_combine_hl, hexagon_A2_combine_lh,   hexagon_A2_combine_ll, hexagon_A2_combineii, hexagon_A2_combinew, hexagon_A2_max,   hexagon_A2_maxp, hexagon_A2_maxu, hexagon_A2_maxup, hexagon_A2_min,   hexagon_A2_minp, hexagon_A2_minu, hexagon_A2_minup, hexagon_A2_neg,   hexagon_A2_negp, hexagon_A2_negsat, hexagon_A2_not, hexagon_A2_notp,   hexagon_A2_or, hexagon_A2_orir, hexagon_A2_orp, hexagon_A2_pxorf,   hexagon_A2_roundsat, hexagon_A2_sat, hexagon_A2_satb, hexagon_A2_sath,   hexagon_A2_satub, hexagon_A2_satuh, hexagon_A2_sub, hexagon_A2_subh_h16_hh,   hexagon_A2_subh_h16_hl, hexagon_A2_subh_h16_lh, hexagon_A2_subh_h16_ll, hexagon_A2_subh_h16_sat_hh,   hexagon_A2_subh_h16_sat_hl, hexagon_A2_subh_h16_sat_lh, hexagon_A2_subh_h16_sat_ll, hexagon_A2_subh_l16_hl,   hexagon_A2_subh_l16_ll, hexagon_A2_subh_l16_sat_hl, hexagon_A2_subh_l16_sat_ll, hexagon_A2_subp,   hexagon_A2_subri, hexagon_A2_subsat, hexagon_A2_svaddh, hexagon_A2_svaddhs,   hexagon_A2_svadduhs, hexagon_A2_svavgh, hexagon_A2_svavghs, hexagon_A2_svnavgh,   hexagon_A2_svsubh, hexagon_A2_svsubhs, hexagon_A2_svsubuhs, hexagon_A2_swiz,   hexagon_A2_sxtb, hexagon_A2_sxth, hexagon_A2_sxtw, hexagon_A2_tfr,   hexagon_A2_tfrcrr, hexagon_A2_tfrih, hexagon_A2_tfril, hexagon_A2_tfrp,   hexagon_A2_tfrpi, hexagon_A2_tfrrcr, hexagon_A2_tfrsi, hexagon_A2_vabsh,   hexagon_A2_vabshsat, hexagon_A2_vabsw, hexagon_A2_vabswsat, hexagon_A2_vaddb_map,   hexagon_A2_vaddh, hexagon_A2_vaddhs, hexagon_A2_vaddub, hexagon_A2_vaddubs,   hexagon_A2_vadduhs, hexagon_A2_vaddw, hexagon_A2_vaddws, hexagon_A2_vavgh,   hexagon_A2_vavghcr, hexagon_A2_vavghr, hexagon_A2_vavgub, hexagon_A2_vavgubr,   hexagon_A2_vavguh, hexagon_A2_vavguhr, hexagon_A2_vavguw, hexagon_A2_vavguwr,   hexagon_A2_vavgw, hexagon_A2_vavgwcr, hexagon_A2_vavgwr, hexagon_A2_vcmpbeq,   hexagon_A2_vcmpbgtu, hexagon_A2_vcmpheq, hexagon_A2_vcmphgt, hexagon_A2_vcmphgtu,   hexagon_A2_vcmpweq, hexagon_A2_vcmpwgt, hexagon_A2_vcmpwgtu, hexagon_A2_vconj,   hexagon_A2_vmaxb, hexagon_A2_vmaxh, hexagon_A2_vmaxub, hexagon_A2_vmaxuh,   hexagon_A2_vmaxuw, hexagon_A2_vmaxw, hexagon_A2_vminb, hexagon_A2_vminh,   hexagon_A2_vminub, hexagon_A2_vminuh, hexagon_A2_vminuw, hexagon_A2_vminw,   hexagon_A2_vnavgh, hexagon_A2_vnavghcr, hexagon_A2_vnavghr, hexagon_A2_vnavgw,   hexagon_A2_vnavgwcr, hexagon_A2_vnavgwr, hexagon_A2_vraddub, hexagon_A2_vraddub_acc,   hexagon_A2_vrsadub, hexagon_A2_vrsadub_acc, hexagon_A2_vsubb_map, hexagon_A2_vsubh,   hexagon_A2_vsubhs, hexagon_A2_vsubub, hexagon_A2_vsububs, hexagon_A2_vsubuhs,   hexagon_A2_vsubw, hexagon_A2_vsubws, hexagon_A2_xor, hexagon_A2_xorp,   hexagon_A2_zxtb, hexagon_A2_zxth, hexagon_A4_addp_c, hexagon_A4_andn,   hexagon_A4_andnp, hexagon_A4_bitsplit, hexagon_A4_bitspliti, hexagon_A4_boundscheck,   hexagon_A4_cmpbeq, hexagon_A4_cmpbeqi, hexagon_A4_cmpbgt, hexagon_A4_cmpbgti,   hexagon_A4_cmpbgtu, hexagon_A4_cmpbgtui, hexagon_A4_cmpheq, hexagon_A4_cmpheqi,   hexagon_A4_cmphgt, hexagon_A4_cmphgti, hexagon_A4_cmphgtu, hexagon_A4_cmphgtui,   hexagon_A4_combineii, hexagon_A4_combineir, hexagon_A4_combineri, hexagon_A4_cround_ri,   hexagon_A4_cround_rr, hexagon_A4_modwrapu, hexagon_A4_orn, hexagon_A4_ornp,   hexagon_A4_rcmpeq, hexagon_A4_rcmpeqi, hexagon_A4_rcmpneq, hexagon_A4_rcmpneqi,   hexagon_A4_round_ri, hexagon_A4_round_ri_sat, hexagon_A4_round_rr, hexagon_A4_round_rr_sat,   hexagon_A4_subp_c, hexagon_A4_tfrcpp, hexagon_A4_tfrpcp, hexagon_A4_tlbmatch,   hexagon_A4_vcmpbeq_any, hexagon_A4_vcmpbeqi, hexagon_A4_vcmpbgt, hexagon_A4_vcmpbgti,   hexagon_A4_vcmpbgtui, hexagon_A4_vcmpheqi, hexagon_A4_vcmphgti, hexagon_A4_vcmphgtui,   hexagon_A4_vcmpweqi, hexagon_A4_vcmpwgti, hexagon_A4_vcmpwgtui, hexagon_A4_vrmaxh,   hexagon_A4_vrmaxuh, hexagon_A4_vrmaxuw, hexagon_A4_vrmaxw, hexagon_A4_vrminh,   hexagon_A4_vrminuh, hexagon_A4_vrminuw, hexagon_A4_vrminw, hexagon_A5_ACS,   hexagon_A5_vaddhubs, hexagon_A6_vcmpbeq_notany, hexagon_A6_vminub_RdP, hexagon_C2_all8,   hexagon_C2_and, hexagon_C2_andn, hexagon_C2_any8, hexagon_C2_bitsclr,   hexagon_C2_bitsclri, hexagon_C2_bitsset, hexagon_C2_cmpeq, hexagon_C2_cmpeqi,   hexagon_C2_cmpeqp, hexagon_C2_cmpgei, hexagon_C2_cmpgeui, hexagon_C2_cmpgt,   hexagon_C2_cmpgti, hexagon_C2_cmpgtp, hexagon_C2_cmpgtu, hexagon_C2_cmpgtui,   hexagon_C2_cmpgtup, hexagon_C2_cmplt, hexagon_C2_cmpltu, hexagon_C2_mask,   hexagon_C2_mux, hexagon_C2_muxii, hexagon_C2_muxir, hexagon_C2_muxri,   hexagon_C2_not, hexagon_C2_or, hexagon_C2_orn, hexagon_C2_pxfer_map,   hexagon_C2_tfrpr, hexagon_C2_tfrrp, hexagon_C2_vitpack, hexagon_C2_vmux,   hexagon_C2_xor, hexagon_C4_and_and, hexagon_C4_and_andn, hexagon_C4_and_or,   hexagon_C4_and_orn, hexagon_C4_cmplte, hexagon_C4_cmpltei, hexagon_C4_cmplteu,   hexagon_C4_cmplteui, hexagon_C4_cmpneq, hexagon_C4_cmpneqi, hexagon_C4_fastcorner9,   hexagon_C4_fastcorner9_not, hexagon_C4_nbitsclr, hexagon_C4_nbitsclri, hexagon_C4_nbitsset,   hexagon_C4_or_and, hexagon_C4_or_andn, hexagon_C4_or_or, hexagon_C4_or_orn,   hexagon_F2_conv_d2df, hexagon_F2_conv_d2sf, hexagon_F2_conv_df2d, hexagon_F2_conv_df2d_chop,   hexagon_F2_conv_df2sf, hexagon_F2_conv_df2ud, hexagon_F2_conv_df2ud_chop, hexagon_F2_conv_df2uw,   hexagon_F2_conv_df2uw_chop, hexagon_F2_conv_df2w, hexagon_F2_conv_df2w_chop, hexagon_F2_conv_sf2d,   hexagon_F2_conv_sf2d_chop, hexagon_F2_conv_sf2df, hexagon_F2_conv_sf2ud, hexagon_F2_conv_sf2ud_chop,   hexagon_F2_conv_sf2uw, hexagon_F2_conv_sf2uw_chop, hexagon_F2_conv_sf2w, hexagon_F2_conv_sf2w_chop,   hexagon_F2_conv_ud2df, hexagon_F2_conv_ud2sf, hexagon_F2_conv_uw2df, hexagon_F2_conv_uw2sf,   hexagon_F2_conv_w2df, hexagon_F2_conv_w2sf, hexagon_F2_dfadd, hexagon_F2_dfclass,   hexagon_F2_dfcmpeq, hexagon_F2_dfcmpge, hexagon_F2_dfcmpgt, hexagon_F2_dfcmpuo,   hexagon_F2_dfimm_n, hexagon_F2_dfimm_p, hexagon_F2_dfsub, hexagon_F2_sfadd,   hexagon_F2_sfclass, hexagon_F2_sfcmpeq, hexagon_F2_sfcmpge, hexagon_F2_sfcmpgt,   hexagon_F2_sfcmpuo, hexagon_F2_sffixupd, hexagon_F2_sffixupn, hexagon_F2_sffixupr,   hexagon_F2_sffma, hexagon_F2_sffma_lib, hexagon_F2_sffma_sc, hexagon_F2_sffms,   hexagon_F2_sffms_lib, hexagon_F2_sfimm_n, hexagon_F2_sfimm_p, hexagon_F2_sfinvsqrta,   hexagon_F2_sfmax, hexagon_F2_sfmin, hexagon_F2_sfmpy, hexagon_F2_sfrecipa,   hexagon_F2_sfsub, hexagon_L2_loadrb_pbr, hexagon_L2_loadrb_pci, hexagon_L2_loadrb_pcr,   hexagon_L2_loadrd_pbr, hexagon_L2_loadrd_pci, hexagon_L2_loadrd_pcr, hexagon_L2_loadrh_pbr,   hexagon_L2_loadrh_pci, hexagon_L2_loadrh_pcr, hexagon_L2_loadri_pbr, hexagon_L2_loadri_pci,   hexagon_L2_loadri_pcr, hexagon_L2_loadrub_pbr, hexagon_L2_loadrub_pci, hexagon_L2_loadrub_pcr,   hexagon_L2_loadruh_pbr, hexagon_L2_loadruh_pci, hexagon_L2_loadruh_pcr, hexagon_L2_loadw_locked,   hexagon_L4_loadd_locked, hexagon_M2_acci, hexagon_M2_accii, hexagon_M2_cmaci_s0,   hexagon_M2_cmacr_s0, hexagon_M2_cmacs_s0, hexagon_M2_cmacs_s1, hexagon_M2_cmacsc_s0,   hexagon_M2_cmacsc_s1, hexagon_M2_cmpyi_s0, hexagon_M2_cmpyr_s0, hexagon_M2_cmpyrs_s0,   hexagon_M2_cmpyrs_s1, hexagon_M2_cmpyrsc_s0, hexagon_M2_cmpyrsc_s1, hexagon_M2_cmpys_s0,   hexagon_M2_cmpys_s1, hexagon_M2_cmpysc_s0, hexagon_M2_cmpysc_s1, hexagon_M2_cnacs_s0,   hexagon_M2_cnacs_s1, hexagon_M2_cnacsc_s0, hexagon_M2_cnacsc_s1, hexagon_M2_dpmpyss_acc_s0,   hexagon_M2_dpmpyss_nac_s0, hexagon_M2_dpmpyss_rnd_s0, hexagon_M2_dpmpyss_s0, hexagon_M2_dpmpyuu_acc_s0,   hexagon_M2_dpmpyuu_nac_s0, hexagon_M2_dpmpyuu_s0, hexagon_M2_hmmpyh_rs1, hexagon_M2_hmmpyh_s1,   hexagon_M2_hmmpyl_rs1, hexagon_M2_hmmpyl_s1, hexagon_M2_maci, hexagon_M2_macsin,   hexagon_M2_macsip, hexagon_M2_mmachs_rs0, hexagon_M2_mmachs_rs1, hexagon_M2_mmachs_s0,   hexagon_M2_mmachs_s1, hexagon_M2_mmacls_rs0, hexagon_M2_mmacls_rs1, hexagon_M2_mmacls_s0,   hexagon_M2_mmacls_s1, hexagon_M2_mmacuhs_rs0, hexagon_M2_mmacuhs_rs1, hexagon_M2_mmacuhs_s0,   hexagon_M2_mmacuhs_s1, hexagon_M2_mmaculs_rs0, hexagon_M2_mmaculs_rs1, hexagon_M2_mmaculs_s0,   hexagon_M2_mmaculs_s1, hexagon_M2_mmpyh_rs0, hexagon_M2_mmpyh_rs1, hexagon_M2_mmpyh_s0,   hexagon_M2_mmpyh_s1, hexagon_M2_mmpyl_rs0, hexagon_M2_mmpyl_rs1, hexagon_M2_mmpyl_s0,   hexagon_M2_mmpyl_s1, hexagon_M2_mmpyuh_rs0, hexagon_M2_mmpyuh_rs1, hexagon_M2_mmpyuh_s0,   hexagon_M2_mmpyuh_s1, hexagon_M2_mmpyul_rs0, hexagon_M2_mmpyul_rs1, hexagon_M2_mmpyul_s0,   hexagon_M2_mmpyul_s1, hexagon_M2_mnaci, hexagon_M2_mpy_acc_hh_s0, hexagon_M2_mpy_acc_hh_s1,   hexagon_M2_mpy_acc_hl_s0, hexagon_M2_mpy_acc_hl_s1, hexagon_M2_mpy_acc_lh_s0, hexagon_M2_mpy_acc_lh_s1,   hexagon_M2_mpy_acc_ll_s0, hexagon_M2_mpy_acc_ll_s1, hexagon_M2_mpy_acc_sat_hh_s0, hexagon_M2_mpy_acc_sat_hh_s1,   hexagon_M2_mpy_acc_sat_hl_s0, hexagon_M2_mpy_acc_sat_hl_s1, hexagon_M2_mpy_acc_sat_lh_s0, hexagon_M2_mpy_acc_sat_lh_s1,   hexagon_M2_mpy_acc_sat_ll_s0, hexagon_M2_mpy_acc_sat_ll_s1, hexagon_M2_mpy_hh_s0, hexagon_M2_mpy_hh_s1,   hexagon_M2_mpy_hl_s0, hexagon_M2_mpy_hl_s1, hexagon_M2_mpy_lh_s0, hexagon_M2_mpy_lh_s1,   hexagon_M2_mpy_ll_s0, hexagon_M2_mpy_ll_s1, hexagon_M2_mpy_nac_hh_s0, hexagon_M2_mpy_nac_hh_s1,   hexagon_M2_mpy_nac_hl_s0, hexagon_M2_mpy_nac_hl_s1, hexagon_M2_mpy_nac_lh_s0, hexagon_M2_mpy_nac_lh_s1,   hexagon_M2_mpy_nac_ll_s0, hexagon_M2_mpy_nac_ll_s1, hexagon_M2_mpy_nac_sat_hh_s0, hexagon_M2_mpy_nac_sat_hh_s1,   hexagon_M2_mpy_nac_sat_hl_s0, hexagon_M2_mpy_nac_sat_hl_s1, hexagon_M2_mpy_nac_sat_lh_s0, hexagon_M2_mpy_nac_sat_lh_s1,   hexagon_M2_mpy_nac_sat_ll_s0, hexagon_M2_mpy_nac_sat_ll_s1, hexagon_M2_mpy_rnd_hh_s0, hexagon_M2_mpy_rnd_hh_s1,   hexagon_M2_mpy_rnd_hl_s0, hexagon_M2_mpy_rnd_hl_s1, hexagon_M2_mpy_rnd_lh_s0, hexagon_M2_mpy_rnd_lh_s1,   hexagon_M2_mpy_rnd_ll_s0, hexagon_M2_mpy_rnd_ll_s1, hexagon_M2_mpy_sat_hh_s0, hexagon_M2_mpy_sat_hh_s1,   hexagon_M2_mpy_sat_hl_s0, hexagon_M2_mpy_sat_hl_s1, hexagon_M2_mpy_sat_lh_s0, hexagon_M2_mpy_sat_lh_s1,   hexagon_M2_mpy_sat_ll_s0, hexagon_M2_mpy_sat_ll_s1, hexagon_M2_mpy_sat_rnd_hh_s0, hexagon_M2_mpy_sat_rnd_hh_s1,   hexagon_M2_mpy_sat_rnd_hl_s0, hexagon_M2_mpy_sat_rnd_hl_s1, hexagon_M2_mpy_sat_rnd_lh_s0, hexagon_M2_mpy_sat_rnd_lh_s1,   hexagon_M2_mpy_sat_rnd_ll_s0, hexagon_M2_mpy_sat_rnd_ll_s1, hexagon_M2_mpy_up, hexagon_M2_mpy_up_s1,   hexagon_M2_mpy_up_s1_sat, hexagon_M2_mpyd_acc_hh_s0, hexagon_M2_mpyd_acc_hh_s1, hexagon_M2_mpyd_acc_hl_s0,   hexagon_M2_mpyd_acc_hl_s1, hexagon_M2_mpyd_acc_lh_s0, hexagon_M2_mpyd_acc_lh_s1, hexagon_M2_mpyd_acc_ll_s0,   hexagon_M2_mpyd_acc_ll_s1, hexagon_M2_mpyd_hh_s0, hexagon_M2_mpyd_hh_s1, hexagon_M2_mpyd_hl_s0,   hexagon_M2_mpyd_hl_s1, hexagon_M2_mpyd_lh_s0, hexagon_M2_mpyd_lh_s1, hexagon_M2_mpyd_ll_s0,   hexagon_M2_mpyd_ll_s1, hexagon_M2_mpyd_nac_hh_s0, hexagon_M2_mpyd_nac_hh_s1, hexagon_M2_mpyd_nac_hl_s0,   hexagon_M2_mpyd_nac_hl_s1, hexagon_M2_mpyd_nac_lh_s0, hexagon_M2_mpyd_nac_lh_s1, hexagon_M2_mpyd_nac_ll_s0,   hexagon_M2_mpyd_nac_ll_s1, hexagon_M2_mpyd_rnd_hh_s0, hexagon_M2_mpyd_rnd_hh_s1, hexagon_M2_mpyd_rnd_hl_s0,   hexagon_M2_mpyd_rnd_hl_s1, hexagon_M2_mpyd_rnd_lh_s0, hexagon_M2_mpyd_rnd_lh_s1, hexagon_M2_mpyd_rnd_ll_s0,   hexagon_M2_mpyd_rnd_ll_s1, hexagon_M2_mpyi, hexagon_M2_mpysin, hexagon_M2_mpysip,   hexagon_M2_mpysmi, hexagon_M2_mpysu_up, hexagon_M2_mpyu_acc_hh_s0, hexagon_M2_mpyu_acc_hh_s1,   hexagon_M2_mpyu_acc_hl_s0, hexagon_M2_mpyu_acc_hl_s1, hexagon_M2_mpyu_acc_lh_s0, hexagon_M2_mpyu_acc_lh_s1,   hexagon_M2_mpyu_acc_ll_s0, hexagon_M2_mpyu_acc_ll_s1, hexagon_M2_mpyu_hh_s0, hexagon_M2_mpyu_hh_s1,   hexagon_M2_mpyu_hl_s0, hexagon_M2_mpyu_hl_s1, hexagon_M2_mpyu_lh_s0, hexagon_M2_mpyu_lh_s1,   hexagon_M2_mpyu_ll_s0, hexagon_M2_mpyu_ll_s1, hexagon_M2_mpyu_nac_hh_s0, hexagon_M2_mpyu_nac_hh_s1,   hexagon_M2_mpyu_nac_hl_s0, hexagon_M2_mpyu_nac_hl_s1, hexagon_M2_mpyu_nac_lh_s0, hexagon_M2_mpyu_nac_lh_s1,   hexagon_M2_mpyu_nac_ll_s0, hexagon_M2_mpyu_nac_ll_s1, hexagon_M2_mpyu_up, hexagon_M2_mpyud_acc_hh_s0,   hexagon_M2_mpyud_acc_hh_s1, hexagon_M2_mpyud_acc_hl_s0, hexagon_M2_mpyud_acc_hl_s1, hexagon_M2_mpyud_acc_lh_s0,   hexagon_M2_mpyud_acc_lh_s1, hexagon_M2_mpyud_acc_ll_s0, hexagon_M2_mpyud_acc_ll_s1, hexagon_M2_mpyud_hh_s0,   hexagon_M2_mpyud_hh_s1, hexagon_M2_mpyud_hl_s0, hexagon_M2_mpyud_hl_s1, hexagon_M2_mpyud_lh_s0,   hexagon_M2_mpyud_lh_s1, hexagon_M2_mpyud_ll_s0, hexagon_M2_mpyud_ll_s1, hexagon_M2_mpyud_nac_hh_s0,   hexagon_M2_mpyud_nac_hh_s1, hexagon_M2_mpyud_nac_hl_s0, hexagon_M2_mpyud_nac_hl_s1, hexagon_M2_mpyud_nac_lh_s0,   hexagon_M2_mpyud_nac_lh_s1, hexagon_M2_mpyud_nac_ll_s0, hexagon_M2_mpyud_nac_ll_s1, hexagon_M2_mpyui,   hexagon_M2_nacci, hexagon_M2_naccii, hexagon_M2_subacc, hexagon_M2_vabsdiffh,   hexagon_M2_vabsdiffw, hexagon_M2_vcmac_s0_sat_i, hexagon_M2_vcmac_s0_sat_r, hexagon_M2_vcmpy_s0_sat_i,   hexagon_M2_vcmpy_s0_sat_r, hexagon_M2_vcmpy_s1_sat_i, hexagon_M2_vcmpy_s1_sat_r, hexagon_M2_vdmacs_s0,   hexagon_M2_vdmacs_s1, hexagon_M2_vdmpyrs_s0, hexagon_M2_vdmpyrs_s1, hexagon_M2_vdmpys_s0,   hexagon_M2_vdmpys_s1, hexagon_M2_vmac2, hexagon_M2_vmac2es, hexagon_M2_vmac2es_s0,   hexagon_M2_vmac2es_s1, hexagon_M2_vmac2s_s0, hexagon_M2_vmac2s_s1, hexagon_M2_vmac2su_s0,   hexagon_M2_vmac2su_s1, hexagon_M2_vmpy2es_s0, hexagon_M2_vmpy2es_s1, hexagon_M2_vmpy2s_s0,   hexagon_M2_vmpy2s_s0pack, hexagon_M2_vmpy2s_s1, hexagon_M2_vmpy2s_s1pack, hexagon_M2_vmpy2su_s0,   hexagon_M2_vmpy2su_s1, hexagon_M2_vraddh, hexagon_M2_vradduh, hexagon_M2_vrcmaci_s0,   hexagon_M2_vrcmaci_s0c, hexagon_M2_vrcmacr_s0, hexagon_M2_vrcmacr_s0c, hexagon_M2_vrcmpyi_s0,   hexagon_M2_vrcmpyi_s0c, hexagon_M2_vrcmpyr_s0, hexagon_M2_vrcmpyr_s0c, hexagon_M2_vrcmpys_acc_s1,   hexagon_M2_vrcmpys_s1, hexagon_M2_vrcmpys_s1rp, hexagon_M2_vrmac_s0, hexagon_M2_vrmpy_s0,   hexagon_M2_xor_xacc, hexagon_M4_and_and, hexagon_M4_and_andn, hexagon_M4_and_or,   hexagon_M4_and_xor, hexagon_M4_cmpyi_wh, hexagon_M4_cmpyi_whc, hexagon_M4_cmpyr_wh,   hexagon_M4_cmpyr_whc, hexagon_M4_mac_up_s1_sat, hexagon_M4_mpyri_addi, hexagon_M4_mpyri_addr,   hexagon_M4_mpyri_addr_u2, hexagon_M4_mpyrr_addi, hexagon_M4_mpyrr_addr, hexagon_M4_nac_up_s1_sat,   hexagon_M4_or_and, hexagon_M4_or_andn, hexagon_M4_or_or, hexagon_M4_or_xor,   hexagon_M4_pmpyw, hexagon_M4_pmpyw_acc, hexagon_M4_vpmpyh, hexagon_M4_vpmpyh_acc,   hexagon_M4_vrmpyeh_acc_s0, hexagon_M4_vrmpyeh_acc_s1, hexagon_M4_vrmpyeh_s0, hexagon_M4_vrmpyeh_s1,   hexagon_M4_vrmpyoh_acc_s0, hexagon_M4_vrmpyoh_acc_s1, hexagon_M4_vrmpyoh_s0, hexagon_M4_vrmpyoh_s1,   hexagon_M4_xor_and, hexagon_M4_xor_andn, hexagon_M4_xor_or, hexagon_M4_xor_xacc,   hexagon_M5_vdmacbsu, hexagon_M5_vdmpybsu, hexagon_M5_vmacbsu, hexagon_M5_vmacbuu,   hexagon_M5_vmpybsu, hexagon_M5_vmpybuu, hexagon_M5_vrmacbsu, hexagon_M5_vrmacbuu,   hexagon_M5_vrmpybsu, hexagon_M5_vrmpybuu, hexagon_M6_vabsdiffb, hexagon_M6_vabsdiffub,   hexagon_S2_addasl_rrri, hexagon_S2_asl_i_p, hexagon_S2_asl_i_p_acc, hexagon_S2_asl_i_p_and,   hexagon_S2_asl_i_p_nac, hexagon_S2_asl_i_p_or, hexagon_S2_asl_i_p_xacc, hexagon_S2_asl_i_r,   hexagon_S2_asl_i_r_acc, hexagon_S2_asl_i_r_and, hexagon_S2_asl_i_r_nac, hexagon_S2_asl_i_r_or,   hexagon_S2_asl_i_r_sat, hexagon_S2_asl_i_r_xacc, hexagon_S2_asl_i_vh, hexagon_S2_asl_i_vw,   hexagon_S2_asl_r_p, hexagon_S2_asl_r_p_acc, hexagon_S2_asl_r_p_and, hexagon_S2_asl_r_p_nac,   hexagon_S2_asl_r_p_or, hexagon_S2_asl_r_p_xor, hexagon_S2_asl_r_r, hexagon_S2_asl_r_r_acc,   hexagon_S2_asl_r_r_and, hexagon_S2_asl_r_r_nac, hexagon_S2_asl_r_r_or, hexagon_S2_asl_r_r_sat,   hexagon_S2_asl_r_vh, hexagon_S2_asl_r_vw, hexagon_S2_asr_i_p, hexagon_S2_asr_i_p_acc,   hexagon_S2_asr_i_p_and, hexagon_S2_asr_i_p_nac, hexagon_S2_asr_i_p_or, hexagon_S2_asr_i_p_rnd,   hexagon_S2_asr_i_p_rnd_goodsyntax, hexagon_S2_asr_i_r, hexagon_S2_asr_i_r_acc, hexagon_S2_asr_i_r_and,   hexagon_S2_asr_i_r_nac, hexagon_S2_asr_i_r_or, hexagon_S2_asr_i_r_rnd, hexagon_S2_asr_i_r_rnd_goodsyntax,   hexagon_S2_asr_i_svw_trun, hexagon_S2_asr_i_vh, hexagon_S2_asr_i_vw, hexagon_S2_asr_r_p,   hexagon_S2_asr_r_p_acc, hexagon_S2_asr_r_p_and, hexagon_S2_asr_r_p_nac, hexagon_S2_asr_r_p_or,   hexagon_S2_asr_r_p_xor, hexagon_S2_asr_r_r, hexagon_S2_asr_r_r_acc, hexagon_S2_asr_r_r_and,   hexagon_S2_asr_r_r_nac, hexagon_S2_asr_r_r_or, hexagon_S2_asr_r_r_sat, hexagon_S2_asr_r_svw_trun,   hexagon_S2_asr_r_vh, hexagon_S2_asr_r_vw, hexagon_S2_brev, hexagon_S2_brevp,   hexagon_S2_cl0, hexagon_S2_cl0p, hexagon_S2_cl1, hexagon_S2_cl1p,   hexagon_S2_clb, hexagon_S2_clbnorm, hexagon_S2_clbp, hexagon_S2_clrbit_i,   hexagon_S2_clrbit_r, hexagon_S2_ct0, hexagon_S2_ct0p, hexagon_S2_ct1,   hexagon_S2_ct1p, hexagon_S2_deinterleave, hexagon_S2_extractu, hexagon_S2_extractu_rp,   hexagon_S2_extractup, hexagon_S2_extractup_rp, hexagon_S2_insert, hexagon_S2_insert_rp,   hexagon_S2_insertp, hexagon_S2_insertp_rp, hexagon_S2_interleave, hexagon_S2_lfsp,   hexagon_S2_lsl_r_p, hexagon_S2_lsl_r_p_acc, hexagon_S2_lsl_r_p_and, hexagon_S2_lsl_r_p_nac,   hexagon_S2_lsl_r_p_or, hexagon_S2_lsl_r_p_xor, hexagon_S2_lsl_r_r, hexagon_S2_lsl_r_r_acc,   hexagon_S2_lsl_r_r_and, hexagon_S2_lsl_r_r_nac, hexagon_S2_lsl_r_r_or, hexagon_S2_lsl_r_vh,   hexagon_S2_lsl_r_vw, hexagon_S2_lsr_i_p, hexagon_S2_lsr_i_p_acc, hexagon_S2_lsr_i_p_and,   hexagon_S2_lsr_i_p_nac, hexagon_S2_lsr_i_p_or, hexagon_S2_lsr_i_p_xacc, hexagon_S2_lsr_i_r,   hexagon_S2_lsr_i_r_acc, hexagon_S2_lsr_i_r_and, hexagon_S2_lsr_i_r_nac, hexagon_S2_lsr_i_r_or,   hexagon_S2_lsr_i_r_xacc, hexagon_S2_lsr_i_vh, hexagon_S2_lsr_i_vw, hexagon_S2_lsr_r_p,   hexagon_S2_lsr_r_p_acc, hexagon_S2_lsr_r_p_and, hexagon_S2_lsr_r_p_nac, hexagon_S2_lsr_r_p_or,   hexagon_S2_lsr_r_p_xor, hexagon_S2_lsr_r_r, hexagon_S2_lsr_r_r_acc, hexagon_S2_lsr_r_r_and,   hexagon_S2_lsr_r_r_nac, hexagon_S2_lsr_r_r_or, hexagon_S2_lsr_r_vh, hexagon_S2_lsr_r_vw,   hexagon_S2_mask, hexagon_S2_packhl, hexagon_S2_parityp, hexagon_S2_setbit_i,   hexagon_S2_setbit_r, hexagon_S2_shuffeb, hexagon_S2_shuffeh, hexagon_S2_shuffob,   hexagon_S2_shuffoh, hexagon_S2_storerb_pbr, hexagon_S2_storerb_pci, hexagon_S2_storerb_pcr,   hexagon_S2_storerd_pbr, hexagon_S2_storerd_pci, hexagon_S2_storerd_pcr, hexagon_S2_storerf_pbr,   hexagon_S2_storerf_pci, hexagon_S2_storerf_pcr, hexagon_S2_storerh_pbr, hexagon_S2_storerh_pci,   hexagon_S2_storerh_pcr, hexagon_S2_storeri_pbr, hexagon_S2_storeri_pci, hexagon_S2_storeri_pcr,   hexagon_S2_storew_locked, hexagon_S2_svsathb, hexagon_S2_svsathub, hexagon_S2_tableidxb_goodsyntax,   hexagon_S2_tableidxd_goodsyntax, hexagon_S2_tableidxh_goodsyntax, hexagon_S2_tableidxw_goodsyntax, hexagon_S2_togglebit_i,   hexagon_S2_togglebit_r, hexagon_S2_tstbit_i, hexagon_S2_tstbit_r, hexagon_S2_valignib,   hexagon_S2_valignrb, hexagon_S2_vcnegh, hexagon_S2_vcrotate, hexagon_S2_vrcnegh,   hexagon_S2_vrndpackwh, hexagon_S2_vrndpackwhs, hexagon_S2_vsathb, hexagon_S2_vsathb_nopack,   hexagon_S2_vsathub, hexagon_S2_vsathub_nopack, hexagon_S2_vsatwh, hexagon_S2_vsatwh_nopack,   hexagon_S2_vsatwuh, hexagon_S2_vsatwuh_nopack, hexagon_S2_vsplatrb, hexagon_S2_vsplatrh,   hexagon_S2_vspliceib, hexagon_S2_vsplicerb, hexagon_S2_vsxtbh, hexagon_S2_vsxthw,   hexagon_S2_vtrunehb, hexagon_S2_vtrunewh, hexagon_S2_vtrunohb, hexagon_S2_vtrunowh,   hexagon_S2_vzxtbh, hexagon_S2_vzxthw, hexagon_S4_addaddi, hexagon_S4_addi_asl_ri,   hexagon_S4_addi_lsr_ri, hexagon_S4_andi_asl_ri, hexagon_S4_andi_lsr_ri, hexagon_S4_clbaddi,   hexagon_S4_clbpaddi, hexagon_S4_clbpnorm, hexagon_S4_extract, hexagon_S4_extract_rp,   hexagon_S4_extractp, hexagon_S4_extractp_rp, hexagon_S4_lsli, hexagon_S4_ntstbit_i,   hexagon_S4_ntstbit_r, hexagon_S4_or_andi, hexagon_S4_or_andix, hexagon_S4_or_ori,   hexagon_S4_ori_asl_ri, hexagon_S4_ori_lsr_ri, hexagon_S4_parity, hexagon_S4_stored_locked,   hexagon_S4_subaddi, hexagon_S4_subi_asl_ri, hexagon_S4_subi_lsr_ri, hexagon_S4_vrcrotate,   hexagon_S4_vrcrotate_acc, hexagon_S4_vxaddsubh, hexagon_S4_vxaddsubhr, hexagon_S4_vxaddsubw,   hexagon_S4_vxsubaddh, hexagon_S4_vxsubaddhr, hexagon_S4_vxsubaddw, hexagon_S5_asrhub_rnd_sat_goodsyntax,   hexagon_S5_asrhub_sat, hexagon_S5_popcountp, hexagon_S5_vasrhrnd_goodsyntax, hexagon_S6_rol_i_p,   hexagon_S6_rol_i_p_acc, hexagon_S6_rol_i_p_and, hexagon_S6_rol_i_p_nac, hexagon_S6_rol_i_p_or,   hexagon_S6_rol_i_p_xacc, hexagon_S6_rol_i_r, hexagon_S6_rol_i_r_acc, hexagon_S6_rol_i_r_and,   hexagon_S6_rol_i_r_nac, hexagon_S6_rol_i_r_or, hexagon_S6_rol_i_r_xacc, hexagon_S6_vsplatrbp,   hexagon_S6_vtrunehb_ppp, hexagon_S6_vtrunohb_ppp, hexagon_V6_extractw, hexagon_V6_extractw_128B,   hexagon_V6_hi, hexagon_V6_hi_128B, hexagon_V6_ld0, hexagon_V6_ld0_128B,   hexagon_V6_ldcnp0, hexagon_V6_ldcnp0_128B, hexagon_V6_ldcnpnt0, hexagon_V6_ldcnpnt0_128B,   hexagon_V6_ldcp0, hexagon_V6_ldcp0_128B, hexagon_V6_ldcpnt0, hexagon_V6_ldcpnt0_128B,   hexagon_V6_ldnp0, hexagon_V6_ldnp0_128B, hexagon_V6_ldnpnt0, hexagon_V6_ldnpnt0_128B,   hexagon_V6_ldnt0, hexagon_V6_ldnt0_128B, hexagon_V6_ldntnt0, hexagon_V6_ldp0,   hexagon_V6_ldp0_128B, hexagon_V6_ldpnt0, hexagon_V6_ldpnt0_128B, hexagon_V6_ldtnp0,   hexagon_V6_ldtnp0_128B, hexagon_V6_ldtnpnt0, hexagon_V6_ldtnpnt0_128B, hexagon_V6_ldtp0,   hexagon_V6_ldtp0_128B, hexagon_V6_ldtpnt0, hexagon_V6_ldtpnt0_128B, hexagon_V6_ldu0,   hexagon_V6_ldu0_128B, hexagon_V6_lo, hexagon_V6_lo_128B, hexagon_V6_lvsplatb,   hexagon_V6_lvsplatb_128B, hexagon_V6_lvsplath, hexagon_V6_lvsplath_128B, hexagon_V6_lvsplatw,   hexagon_V6_lvsplatw_128B, hexagon_V6_pred_and, hexagon_V6_pred_and_128B, hexagon_V6_pred_and_n,   hexagon_V6_pred_and_n_128B, hexagon_V6_pred_not, hexagon_V6_pred_not_128B, hexagon_V6_pred_or,   hexagon_V6_pred_or_128B, hexagon_V6_pred_or_n, hexagon_V6_pred_or_n_128B, hexagon_V6_pred_scalar2,   hexagon_V6_pred_scalar2_128B, hexagon_V6_pred_scalar2v2, hexagon_V6_pred_scalar2v2_128B, hexagon_V6_pred_xor,   hexagon_V6_pred_xor_128B, hexagon_V6_shuffeqh, hexagon_V6_shuffeqh_128B, hexagon_V6_shuffeqw,   hexagon_V6_shuffeqw_128B, hexagon_V6_vS32b_nqpred_ai, hexagon_V6_vS32b_nqpred_ai_128B, hexagon_V6_vS32b_nt_nqpred_ai,   hexagon_V6_vS32b_nt_nqpred_ai_128B, hexagon_V6_vS32b_nt_qpred_ai, hexagon_V6_vS32b_nt_qpred_ai_128B, hexagon_V6_vS32b_qpred_ai,   hexagon_V6_vS32b_qpred_ai_128B, hexagon_V6_vabsb, hexagon_V6_vabsb_128B, hexagon_V6_vabsb_sat,   hexagon_V6_vabsb_sat_128B, hexagon_V6_vabsdiffh, hexagon_V6_vabsdiffh_128B, hexagon_V6_vabsdiffub,   hexagon_V6_vabsdiffub_128B, hexagon_V6_vabsdiffuh, hexagon_V6_vabsdiffuh_128B, hexagon_V6_vabsdiffw,   hexagon_V6_vabsdiffw_128B, hexagon_V6_vabsh, hexagon_V6_vabsh_128B, hexagon_V6_vabsh_sat,   hexagon_V6_vabsh_sat_128B, hexagon_V6_vabsw, hexagon_V6_vabsw_128B, hexagon_V6_vabsw_sat,   hexagon_V6_vabsw_sat_128B, hexagon_V6_vaddb, hexagon_V6_vaddb_128B, hexagon_V6_vaddb_dv,   hexagon_V6_vaddb_dv_128B, hexagon_V6_vaddbnq, hexagon_V6_vaddbnq_128B, hexagon_V6_vaddbq,   hexagon_V6_vaddbq_128B, hexagon_V6_vaddbsat, hexagon_V6_vaddbsat_128B, hexagon_V6_vaddbsat_dv,   hexagon_V6_vaddbsat_dv_128B, hexagon_V6_vaddcarry, hexagon_V6_vaddcarry_128B, hexagon_V6_vaddcarrysat,   hexagon_V6_vaddcarrysat_128B, hexagon_V6_vaddclbh, hexagon_V6_vaddclbh_128B, hexagon_V6_vaddclbw,   hexagon_V6_vaddclbw_128B, hexagon_V6_vaddh, hexagon_V6_vaddh_128B, hexagon_V6_vaddh_dv,   hexagon_V6_vaddh_dv_128B, hexagon_V6_vaddhnq, hexagon_V6_vaddhnq_128B, hexagon_V6_vaddhq,   hexagon_V6_vaddhq_128B, hexagon_V6_vaddhsat, hexagon_V6_vaddhsat_128B, hexagon_V6_vaddhsat_dv,   hexagon_V6_vaddhsat_dv_128B, hexagon_V6_vaddhw, hexagon_V6_vaddhw_128B, hexagon_V6_vaddhw_acc,   hexagon_V6_vaddhw_acc_128B, hexagon_V6_vaddubh, hexagon_V6_vaddubh_128B, hexagon_V6_vaddubh_acc,   hexagon_V6_vaddubh_acc_128B, hexagon_V6_vaddubsat, hexagon_V6_vaddubsat_128B, hexagon_V6_vaddubsat_dv,   hexagon_V6_vaddubsat_dv_128B, hexagon_V6_vaddububb_sat, hexagon_V6_vaddububb_sat_128B, hexagon_V6_vadduhsat,   hexagon_V6_vadduhsat_128B, hexagon_V6_vadduhsat_dv, hexagon_V6_vadduhsat_dv_128B, hexagon_V6_vadduhw,   hexagon_V6_vadduhw_128B, hexagon_V6_vadduhw_acc, hexagon_V6_vadduhw_acc_128B, hexagon_V6_vadduwsat,   hexagon_V6_vadduwsat_128B, hexagon_V6_vadduwsat_dv, hexagon_V6_vadduwsat_dv_128B, hexagon_V6_vaddw,   hexagon_V6_vaddw_128B, hexagon_V6_vaddw_dv, hexagon_V6_vaddw_dv_128B, hexagon_V6_vaddwnq,   hexagon_V6_vaddwnq_128B, hexagon_V6_vaddwq, hexagon_V6_vaddwq_128B, hexagon_V6_vaddwsat,   hexagon_V6_vaddwsat_128B, hexagon_V6_vaddwsat_dv, hexagon_V6_vaddwsat_dv_128B, hexagon_V6_valignb,   hexagon_V6_valignb_128B, hexagon_V6_valignbi, hexagon_V6_valignbi_128B, hexagon_V6_vand,   hexagon_V6_vand_128B, hexagon_V6_vandnqrt, hexagon_V6_vandnqrt_128B, hexagon_V6_vandnqrt_acc,   hexagon_V6_vandnqrt_acc_128B, hexagon_V6_vandqrt, hexagon_V6_vandqrt_128B, hexagon_V6_vandqrt_acc,   hexagon_V6_vandqrt_acc_128B, hexagon_V6_vandvnqv, hexagon_V6_vandvnqv_128B, hexagon_V6_vandvqv,   hexagon_V6_vandvqv_128B, hexagon_V6_vandvrt, hexagon_V6_vandvrt_128B, hexagon_V6_vandvrt_acc,   hexagon_V6_vandvrt_acc_128B, hexagon_V6_vaslh, hexagon_V6_vaslh_128B, hexagon_V6_vaslh_acc,   hexagon_V6_vaslh_acc_128B, hexagon_V6_vaslhv, hexagon_V6_vaslhv_128B, hexagon_V6_vaslw,   hexagon_V6_vaslw_128B, hexagon_V6_vaslw_acc, hexagon_V6_vaslw_acc_128B, hexagon_V6_vaslwv,   hexagon_V6_vaslwv_128B, hexagon_V6_vasr_into, hexagon_V6_vasr_into_128B, hexagon_V6_vasrh,   hexagon_V6_vasrh_128B, hexagon_V6_vasrh_acc, hexagon_V6_vasrh_acc_128B, hexagon_V6_vasrhbrndsat,   hexagon_V6_vasrhbrndsat_128B, hexagon_V6_vasrhbsat, hexagon_V6_vasrhbsat_128B, hexagon_V6_vasrhubrndsat,   hexagon_V6_vasrhubrndsat_128B, hexagon_V6_vasrhubsat, hexagon_V6_vasrhubsat_128B, hexagon_V6_vasrhv,   hexagon_V6_vasrhv_128B, hexagon_V6_vasruhubrndsat, hexagon_V6_vasruhubrndsat_128B, hexagon_V6_vasruhubsat,   hexagon_V6_vasruhubsat_128B, hexagon_V6_vasruwuhrndsat, hexagon_V6_vasruwuhrndsat_128B, hexagon_V6_vasruwuhsat,   hexagon_V6_vasruwuhsat_128B, hexagon_V6_vasrw, hexagon_V6_vasrw_128B, hexagon_V6_vasrw_acc,   hexagon_V6_vasrw_acc_128B, hexagon_V6_vasrwh, hexagon_V6_vasrwh_128B, hexagon_V6_vasrwhrndsat,   hexagon_V6_vasrwhrndsat_128B, hexagon_V6_vasrwhsat, hexagon_V6_vasrwhsat_128B, hexagon_V6_vasrwuhrndsat,   hexagon_V6_vasrwuhrndsat_128B, hexagon_V6_vasrwuhsat, hexagon_V6_vasrwuhsat_128B, hexagon_V6_vasrwv,   hexagon_V6_vasrwv_128B, hexagon_V6_vassign, hexagon_V6_vassign_128B, hexagon_V6_vassignp,   hexagon_V6_vassignp_128B, hexagon_V6_vavgb, hexagon_V6_vavgb_128B, hexagon_V6_vavgbrnd,   hexagon_V6_vavgbrnd_128B, hexagon_V6_vavgh, hexagon_V6_vavgh_128B, hexagon_V6_vavghrnd,   hexagon_V6_vavghrnd_128B, hexagon_V6_vavgub, hexagon_V6_vavgub_128B, hexagon_V6_vavgubrnd,   hexagon_V6_vavgubrnd_128B, hexagon_V6_vavguh, hexagon_V6_vavguh_128B, hexagon_V6_vavguhrnd,   hexagon_V6_vavguhrnd_128B, hexagon_V6_vavguw, hexagon_V6_vavguw_128B, hexagon_V6_vavguwrnd,   hexagon_V6_vavguwrnd_128B, hexagon_V6_vavgw, hexagon_V6_vavgw_128B, hexagon_V6_vavgwrnd,   hexagon_V6_vavgwrnd_128B, hexagon_V6_vcl0h, hexagon_V6_vcl0h_128B, hexagon_V6_vcl0w,   hexagon_V6_vcl0w_128B, hexagon_V6_vcombine, hexagon_V6_vcombine_128B, hexagon_V6_vd0,   hexagon_V6_vd0_128B, hexagon_V6_vdd0, hexagon_V6_vdd0_128B, hexagon_V6_vdealb,   hexagon_V6_vdealb_128B, hexagon_V6_vdealb4w, hexagon_V6_vdealb4w_128B, hexagon_V6_vdealh,   hexagon_V6_vdealh_128B, hexagon_V6_vdealvdd, hexagon_V6_vdealvdd_128B, hexagon_V6_vdelta,   hexagon_V6_vdelta_128B, hexagon_V6_vdmpybus, hexagon_V6_vdmpybus_128B, hexagon_V6_vdmpybus_acc,   hexagon_V6_vdmpybus_acc_128B, hexagon_V6_vdmpybus_dv, hexagon_V6_vdmpybus_dv_128B, hexagon_V6_vdmpybus_dv_acc,   hexagon_V6_vdmpybus_dv_acc_128B, hexagon_V6_vdmpyhb, hexagon_V6_vdmpyhb_128B, hexagon_V6_vdmpyhb_acc,   hexagon_V6_vdmpyhb_acc_128B, hexagon_V6_vdmpyhb_dv, hexagon_V6_vdmpyhb_dv_128B, hexagon_V6_vdmpyhb_dv_acc,   hexagon_V6_vdmpyhb_dv_acc_128B, hexagon_V6_vdmpyhisat, hexagon_V6_vdmpyhisat_128B, hexagon_V6_vdmpyhisat_acc,   hexagon_V6_vdmpyhisat_acc_128B, hexagon_V6_vdmpyhsat, hexagon_V6_vdmpyhsat_128B, hexagon_V6_vdmpyhsat_acc,   hexagon_V6_vdmpyhsat_acc_128B, hexagon_V6_vdmpyhsuisat, hexagon_V6_vdmpyhsuisat_128B, hexagon_V6_vdmpyhsuisat_acc,   hexagon_V6_vdmpyhsuisat_acc_128B, hexagon_V6_vdmpyhsusat, hexagon_V6_vdmpyhsusat_128B, hexagon_V6_vdmpyhsusat_acc,   hexagon_V6_vdmpyhsusat_acc_128B, hexagon_V6_vdmpyhvsat, hexagon_V6_vdmpyhvsat_128B, hexagon_V6_vdmpyhvsat_acc,   hexagon_V6_vdmpyhvsat_acc_128B, hexagon_V6_vdsaduh, hexagon_V6_vdsaduh_128B, hexagon_V6_vdsaduh_acc,   hexagon_V6_vdsaduh_acc_128B, hexagon_V6_veqb, hexagon_V6_veqb_128B, hexagon_V6_veqb_and,   hexagon_V6_veqb_and_128B, hexagon_V6_veqb_or, hexagon_V6_veqb_or_128B, hexagon_V6_veqb_xor,   hexagon_V6_veqb_xor_128B, hexagon_V6_veqh, hexagon_V6_veqh_128B, hexagon_V6_veqh_and,   hexagon_V6_veqh_and_128B, hexagon_V6_veqh_or, hexagon_V6_veqh_or_128B, hexagon_V6_veqh_xor,   hexagon_V6_veqh_xor_128B, hexagon_V6_veqw, hexagon_V6_veqw_128B, hexagon_V6_veqw_and,   hexagon_V6_veqw_and_128B, hexagon_V6_veqw_or, hexagon_V6_veqw_or_128B, hexagon_V6_veqw_xor,   hexagon_V6_veqw_xor_128B, hexagon_V6_vgathermh, hexagon_V6_vgathermh_128B, hexagon_V6_vgathermhq,   hexagon_V6_vgathermhq_128B, hexagon_V6_vgathermhw, hexagon_V6_vgathermhw_128B, hexagon_V6_vgathermhwq,   hexagon_V6_vgathermhwq_128B, hexagon_V6_vgathermw, hexagon_V6_vgathermw_128B, hexagon_V6_vgathermwq,   hexagon_V6_vgathermwq_128B, hexagon_V6_vgtb, hexagon_V6_vgtb_128B, hexagon_V6_vgtb_and,   hexagon_V6_vgtb_and_128B, hexagon_V6_vgtb_or, hexagon_V6_vgtb_or_128B, hexagon_V6_vgtb_xor,   hexagon_V6_vgtb_xor_128B, hexagon_V6_vgth, hexagon_V6_vgth_128B, hexagon_V6_vgth_and,   hexagon_V6_vgth_and_128B, hexagon_V6_vgth_or, hexagon_V6_vgth_or_128B, hexagon_V6_vgth_xor,   hexagon_V6_vgth_xor_128B, hexagon_V6_vgtub, hexagon_V6_vgtub_128B, hexagon_V6_vgtub_and,   hexagon_V6_vgtub_and_128B, hexagon_V6_vgtub_or, hexagon_V6_vgtub_or_128B, hexagon_V6_vgtub_xor,   hexagon_V6_vgtub_xor_128B, hexagon_V6_vgtuh, hexagon_V6_vgtuh_128B, hexagon_V6_vgtuh_and,   hexagon_V6_vgtuh_and_128B, hexagon_V6_vgtuh_or, hexagon_V6_vgtuh_or_128B, hexagon_V6_vgtuh_xor,   hexagon_V6_vgtuh_xor_128B, hexagon_V6_vgtuw, hexagon_V6_vgtuw_128B, hexagon_V6_vgtuw_and,   hexagon_V6_vgtuw_and_128B, hexagon_V6_vgtuw_or, hexagon_V6_vgtuw_or_128B, hexagon_V6_vgtuw_xor,   hexagon_V6_vgtuw_xor_128B, hexagon_V6_vgtw, hexagon_V6_vgtw_128B, hexagon_V6_vgtw_and,   hexagon_V6_vgtw_and_128B, hexagon_V6_vgtw_or, hexagon_V6_vgtw_or_128B, hexagon_V6_vgtw_xor,   hexagon_V6_vgtw_xor_128B, hexagon_V6_vinsertwr, hexagon_V6_vinsertwr_128B, hexagon_V6_vlalignb,   hexagon_V6_vlalignb_128B, hexagon_V6_vlalignbi, hexagon_V6_vlalignbi_128B, hexagon_V6_vlsrb,   hexagon_V6_vlsrb_128B, hexagon_V6_vlsrh, hexagon_V6_vlsrh_128B, hexagon_V6_vlsrhv,   hexagon_V6_vlsrhv_128B, hexagon_V6_vlsrw, hexagon_V6_vlsrw_128B, hexagon_V6_vlsrwv,   hexagon_V6_vlsrwv_128B, hexagon_V6_vlut4, hexagon_V6_vlut4_128B, hexagon_V6_vlutvvb,   hexagon_V6_vlutvvb_128B, hexagon_V6_vlutvvb_nm, hexagon_V6_vlutvvb_nm_128B, hexagon_V6_vlutvvb_oracc,   hexagon_V6_vlutvvb_oracc_128B, hexagon_V6_vlutvvb_oracci, hexagon_V6_vlutvvb_oracci_128B, hexagon_V6_vlutvvbi,   hexagon_V6_vlutvvbi_128B, hexagon_V6_vlutvwh, hexagon_V6_vlutvwh_128B, hexagon_V6_vlutvwh_nm,   hexagon_V6_vlutvwh_nm_128B, hexagon_V6_vlutvwh_oracc, hexagon_V6_vlutvwh_oracc_128B, hexagon_V6_vlutvwh_oracci,   hexagon_V6_vlutvwh_oracci_128B, hexagon_V6_vlutvwhi, hexagon_V6_vlutvwhi_128B, hexagon_V6_vmaskedstorenq,   hexagon_V6_vmaskedstorenq_128B, hexagon_V6_vmaskedstorentnq, hexagon_V6_vmaskedstorentnq_128B, hexagon_V6_vmaskedstorentq,   hexagon_V6_vmaskedstorentq_128B, hexagon_V6_vmaskedstoreq, hexagon_V6_vmaskedstoreq_128B, hexagon_V6_vmaxb,   hexagon_V6_vmaxb_128B, hexagon_V6_vmaxh, hexagon_V6_vmaxh_128B, hexagon_V6_vmaxub,   hexagon_V6_vmaxub_128B, hexagon_V6_vmaxuh, hexagon_V6_vmaxuh_128B, hexagon_V6_vmaxw,   hexagon_V6_vmaxw_128B, hexagon_V6_vminb, hexagon_V6_vminb_128B, hexagon_V6_vminh,   hexagon_V6_vminh_128B, hexagon_V6_vminub, hexagon_V6_vminub_128B, hexagon_V6_vminuh,   hexagon_V6_vminuh_128B, hexagon_V6_vminw, hexagon_V6_vminw_128B, hexagon_V6_vmpabus,   hexagon_V6_vmpabus_128B, hexagon_V6_vmpabus_acc, hexagon_V6_vmpabus_acc_128B, hexagon_V6_vmpabusv,   hexagon_V6_vmpabusv_128B, hexagon_V6_vmpabuu, hexagon_V6_vmpabuu_128B, hexagon_V6_vmpabuu_acc,   hexagon_V6_vmpabuu_acc_128B, hexagon_V6_vmpabuuv, hexagon_V6_vmpabuuv_128B, hexagon_V6_vmpahb,   hexagon_V6_vmpahb_128B, hexagon_V6_vmpahb_acc, hexagon_V6_vmpahb_acc_128B, hexagon_V6_vmpahhsat,   hexagon_V6_vmpahhsat_128B, hexagon_V6_vmpauhb, hexagon_V6_vmpauhb_128B, hexagon_V6_vmpauhb_acc,   hexagon_V6_vmpauhb_acc_128B, hexagon_V6_vmpauhuhsat, hexagon_V6_vmpauhuhsat_128B, hexagon_V6_vmpsuhuhsat,   hexagon_V6_vmpsuhuhsat_128B, hexagon_V6_vmpybus, hexagon_V6_vmpybus_128B, hexagon_V6_vmpybus_acc,   hexagon_V6_vmpybus_acc_128B, hexagon_V6_vmpybusv, hexagon_V6_vmpybusv_128B, hexagon_V6_vmpybusv_acc,   hexagon_V6_vmpybusv_acc_128B, hexagon_V6_vmpybv, hexagon_V6_vmpybv_128B, hexagon_V6_vmpybv_acc,   hexagon_V6_vmpybv_acc_128B, hexagon_V6_vmpyewuh, hexagon_V6_vmpyewuh_128B, hexagon_V6_vmpyewuh_64,   hexagon_V6_vmpyewuh_64_128B, hexagon_V6_vmpyh, hexagon_V6_vmpyh_128B, hexagon_V6_vmpyh_acc,   hexagon_V6_vmpyh_acc_128B, hexagon_V6_vmpyhsat_acc, hexagon_V6_vmpyhsat_acc_128B, hexagon_V6_vmpyhsrs,   hexagon_V6_vmpyhsrs_128B, hexagon_V6_vmpyhss, hexagon_V6_vmpyhss_128B, hexagon_V6_vmpyhus,   hexagon_V6_vmpyhus_128B, hexagon_V6_vmpyhus_acc, hexagon_V6_vmpyhus_acc_128B, hexagon_V6_vmpyhv,   hexagon_V6_vmpyhv_128B, hexagon_V6_vmpyhv_acc, hexagon_V6_vmpyhv_acc_128B, hexagon_V6_vmpyhvsrs,   hexagon_V6_vmpyhvsrs_128B, hexagon_V6_vmpyieoh, hexagon_V6_vmpyieoh_128B, hexagon_V6_vmpyiewh_acc,   hexagon_V6_vmpyiewh_acc_128B, hexagon_V6_vmpyiewuh, hexagon_V6_vmpyiewuh_128B, hexagon_V6_vmpyiewuh_acc,   hexagon_V6_vmpyiewuh_acc_128B, hexagon_V6_vmpyih, hexagon_V6_vmpyih_128B, hexagon_V6_vmpyih_acc,   hexagon_V6_vmpyih_acc_128B, hexagon_V6_vmpyihb, hexagon_V6_vmpyihb_128B, hexagon_V6_vmpyihb_acc,   hexagon_V6_vmpyihb_acc_128B, hexagon_V6_vmpyiowh, hexagon_V6_vmpyiowh_128B, hexagon_V6_vmpyiwb,   hexagon_V6_vmpyiwb_128B, hexagon_V6_vmpyiwb_acc, hexagon_V6_vmpyiwb_acc_128B, hexagon_V6_vmpyiwh,   hexagon_V6_vmpyiwh_128B, hexagon_V6_vmpyiwh_acc, hexagon_V6_vmpyiwh_acc_128B, hexagon_V6_vmpyiwub,   hexagon_V6_vmpyiwub_128B, hexagon_V6_vmpyiwub_acc, hexagon_V6_vmpyiwub_acc_128B, hexagon_V6_vmpyowh,   hexagon_V6_vmpyowh_128B, hexagon_V6_vmpyowh_64_acc, hexagon_V6_vmpyowh_64_acc_128B, hexagon_V6_vmpyowh_rnd,   hexagon_V6_vmpyowh_rnd_128B, hexagon_V6_vmpyowh_rnd_sacc, hexagon_V6_vmpyowh_rnd_sacc_128B, hexagon_V6_vmpyowh_sacc,   hexagon_V6_vmpyowh_sacc_128B, hexagon_V6_vmpyub, hexagon_V6_vmpyub_128B, hexagon_V6_vmpyub_acc,   hexagon_V6_vmpyub_acc_128B, hexagon_V6_vmpyubv, hexagon_V6_vmpyubv_128B, hexagon_V6_vmpyubv_acc,   hexagon_V6_vmpyubv_acc_128B, hexagon_V6_vmpyuh, hexagon_V6_vmpyuh_128B, hexagon_V6_vmpyuh_acc,   hexagon_V6_vmpyuh_acc_128B, hexagon_V6_vmpyuhe, hexagon_V6_vmpyuhe_128B, hexagon_V6_vmpyuhe_acc,   hexagon_V6_vmpyuhe_acc_128B, hexagon_V6_vmpyuhv, hexagon_V6_vmpyuhv_128B, hexagon_V6_vmpyuhv_acc,   hexagon_V6_vmpyuhv_acc_128B, hexagon_V6_vmux, hexagon_V6_vmux_128B, hexagon_V6_vnavgb,   hexagon_V6_vnavgb_128B, hexagon_V6_vnavgh, hexagon_V6_vnavgh_128B, hexagon_V6_vnavgub,   hexagon_V6_vnavgub_128B, hexagon_V6_vnavgw, hexagon_V6_vnavgw_128B, hexagon_V6_vnormamth,   hexagon_V6_vnormamth_128B, hexagon_V6_vnormamtw, hexagon_V6_vnormamtw_128B, hexagon_V6_vnot,   hexagon_V6_vnot_128B, hexagon_V6_vor, hexagon_V6_vor_128B, hexagon_V6_vpackeb,   hexagon_V6_vpackeb_128B, hexagon_V6_vpackeh, hexagon_V6_vpackeh_128B, hexagon_V6_vpackhb_sat,   hexagon_V6_vpackhb_sat_128B, hexagon_V6_vpackhub_sat, hexagon_V6_vpackhub_sat_128B, hexagon_V6_vpackob,   hexagon_V6_vpackob_128B, hexagon_V6_vpackoh, hexagon_V6_vpackoh_128B, hexagon_V6_vpackwh_sat,   hexagon_V6_vpackwh_sat_128B, hexagon_V6_vpackwuh_sat, hexagon_V6_vpackwuh_sat_128B, hexagon_V6_vpopcounth,   hexagon_V6_vpopcounth_128B, hexagon_V6_vprefixqb, hexagon_V6_vprefixqb_128B, hexagon_V6_vprefixqh,   hexagon_V6_vprefixqh_128B, hexagon_V6_vprefixqw, hexagon_V6_vprefixqw_128B, hexagon_V6_vrdelta,   hexagon_V6_vrdelta_128B, hexagon_V6_vrmpybub_rtt, hexagon_V6_vrmpybub_rtt_128B, hexagon_V6_vrmpybub_rtt_acc,   hexagon_V6_vrmpybub_rtt_acc_128B, hexagon_V6_vrmpybus, hexagon_V6_vrmpybus_128B, hexagon_V6_vrmpybus_acc,   hexagon_V6_vrmpybus_acc_128B, hexagon_V6_vrmpybusi, hexagon_V6_vrmpybusi_128B, hexagon_V6_vrmpybusi_acc,   hexagon_V6_vrmpybusi_acc_128B, hexagon_V6_vrmpybusv, hexagon_V6_vrmpybusv_128B, hexagon_V6_vrmpybusv_acc,   hexagon_V6_vrmpybusv_acc_128B, hexagon_V6_vrmpybv, hexagon_V6_vrmpybv_128B, hexagon_V6_vrmpybv_acc,   hexagon_V6_vrmpybv_acc_128B, hexagon_V6_vrmpyub, hexagon_V6_vrmpyub_128B, hexagon_V6_vrmpyub_acc,   hexagon_V6_vrmpyub_acc_128B, hexagon_V6_vrmpyub_rtt, hexagon_V6_vrmpyub_rtt_128B, hexagon_V6_vrmpyub_rtt_acc,   hexagon_V6_vrmpyub_rtt_acc_128B, hexagon_V6_vrmpyubi, hexagon_V6_vrmpyubi_128B, hexagon_V6_vrmpyubi_acc,   hexagon_V6_vrmpyubi_acc_128B, hexagon_V6_vrmpyubv, hexagon_V6_vrmpyubv_128B, hexagon_V6_vrmpyubv_acc,   hexagon_V6_vrmpyubv_acc_128B, hexagon_V6_vror, hexagon_V6_vror_128B, hexagon_V6_vrotr,   hexagon_V6_vrotr_128B, hexagon_V6_vroundhb, hexagon_V6_vroundhb_128B, hexagon_V6_vroundhub,   hexagon_V6_vroundhub_128B, hexagon_V6_vrounduhub, hexagon_V6_vrounduhub_128B, hexagon_V6_vrounduwuh,   hexagon_V6_vrounduwuh_128B, hexagon_V6_vroundwh, hexagon_V6_vroundwh_128B, hexagon_V6_vroundwuh,   hexagon_V6_vroundwuh_128B, hexagon_V6_vrsadubi, hexagon_V6_vrsadubi_128B, hexagon_V6_vrsadubi_acc,   hexagon_V6_vrsadubi_acc_128B, hexagon_V6_vsatdw, hexagon_V6_vsatdw_128B, hexagon_V6_vsathub,   hexagon_V6_vsathub_128B, hexagon_V6_vsatuwuh, hexagon_V6_vsatuwuh_128B, hexagon_V6_vsatwh,   hexagon_V6_vsatwh_128B, hexagon_V6_vsb, hexagon_V6_vsb_128B, hexagon_V6_vscattermh,   hexagon_V6_vscattermh_128B, hexagon_V6_vscattermh_add, hexagon_V6_vscattermh_add_128B, hexagon_V6_vscattermhq,   hexagon_V6_vscattermhq_128B, hexagon_V6_vscattermhw, hexagon_V6_vscattermhw_128B, hexagon_V6_vscattermhw_add,   hexagon_V6_vscattermhw_add_128B, hexagon_V6_vscattermhwq, hexagon_V6_vscattermhwq_128B, hexagon_V6_vscattermw,   hexagon_V6_vscattermw_128B, hexagon_V6_vscattermw_add, hexagon_V6_vscattermw_add_128B, hexagon_V6_vscattermwq,   hexagon_V6_vscattermwq_128B, hexagon_V6_vsh, hexagon_V6_vsh_128B, hexagon_V6_vshufeh,   hexagon_V6_vshufeh_128B, hexagon_V6_vshuffb, hexagon_V6_vshuffb_128B, hexagon_V6_vshuffeb,   hexagon_V6_vshuffeb_128B, hexagon_V6_vshuffh, hexagon_V6_vshuffh_128B, hexagon_V6_vshuffob,   hexagon_V6_vshuffob_128B, hexagon_V6_vshuffvdd, hexagon_V6_vshuffvdd_128B, hexagon_V6_vshufoeb,   hexagon_V6_vshufoeb_128B, hexagon_V6_vshufoeh, hexagon_V6_vshufoeh_128B, hexagon_V6_vshufoh,   hexagon_V6_vshufoh_128B, hexagon_V6_vsubb, hexagon_V6_vsubb_128B, hexagon_V6_vsubb_dv,   hexagon_V6_vsubb_dv_128B, hexagon_V6_vsubbnq, hexagon_V6_vsubbnq_128B, hexagon_V6_vsubbq,   hexagon_V6_vsubbq_128B, hexagon_V6_vsubbsat, hexagon_V6_vsubbsat_128B, hexagon_V6_vsubbsat_dv,   hexagon_V6_vsubbsat_dv_128B, hexagon_V6_vsubcarry, hexagon_V6_vsubcarry_128B, hexagon_V6_vsubh,   hexagon_V6_vsubh_128B, hexagon_V6_vsubh_dv, hexagon_V6_vsubh_dv_128B, hexagon_V6_vsubhnq,   hexagon_V6_vsubhnq_128B, hexagon_V6_vsubhq, hexagon_V6_vsubhq_128B, hexagon_V6_vsubhsat,   hexagon_V6_vsubhsat_128B, hexagon_V6_vsubhsat_dv, hexagon_V6_vsubhsat_dv_128B, hexagon_V6_vsubhw,   hexagon_V6_vsubhw_128B, hexagon_V6_vsububh, hexagon_V6_vsububh_128B, hexagon_V6_vsububsat,   hexagon_V6_vsububsat_128B, hexagon_V6_vsububsat_dv, hexagon_V6_vsububsat_dv_128B, hexagon_V6_vsubububb_sat,   hexagon_V6_vsubububb_sat_128B, hexagon_V6_vsubuhsat, hexagon_V6_vsubuhsat_128B, hexagon_V6_vsubuhsat_dv,   hexagon_V6_vsubuhsat_dv_128B, hexagon_V6_vsubuhw, hexagon_V6_vsubuhw_128B, hexagon_V6_vsubuwsat,   hexagon_V6_vsubuwsat_128B, hexagon_V6_vsubuwsat_dv, hexagon_V6_vsubuwsat_dv_128B, hexagon_V6_vsubw,   hexagon_V6_vsubw_128B, hexagon_V6_vsubw_dv, hexagon_V6_vsubw_dv_128B, hexagon_V6_vsubwnq,   hexagon_V6_vsubwnq_128B, hexagon_V6_vsubwq, hexagon_V6_vsubwq_128B, hexagon_V6_vsubwsat,   hexagon_V6_vsubwsat_128B, hexagon_V6_vsubwsat_dv, hexagon_V6_vsubwsat_dv_128B, hexagon_V6_vswap,   hexagon_V6_vswap_128B, hexagon_V6_vtmpyb, hexagon_V6_vtmpyb_128B, hexagon_V6_vtmpyb_acc,   hexagon_V6_vtmpyb_acc_128B, hexagon_V6_vtmpybus, hexagon_V6_vtmpybus_128B, hexagon_V6_vtmpybus_acc,   hexagon_V6_vtmpybus_acc_128B, hexagon_V6_vtmpyhb, hexagon_V6_vtmpyhb_128B, hexagon_V6_vtmpyhb_acc,   hexagon_V6_vtmpyhb_acc_128B, hexagon_V6_vtran2x2_map, hexagon_V6_vtran2x2_map_128B, hexagon_V6_vunpackb,   hexagon_V6_vunpackb_128B, hexagon_V6_vunpackh, hexagon_V6_vunpackh_128B, hexagon_V6_vunpackob,   hexagon_V6_vunpackob_128B, hexagon_V6_vunpackoh, hexagon_V6_vunpackoh_128B, hexagon_V6_vunpackub,   hexagon_V6_vunpackub_128B, hexagon_V6_vunpackuh, hexagon_V6_vunpackuh_128B, hexagon_V6_vxor,   hexagon_V6_vxor_128B, hexagon_V6_vzb, hexagon_V6_vzb_128B, hexagon_V6_vzh,   hexagon_V6_vzh_128B, hexagon_Y2_dccleana, hexagon_Y2_dccleaninva, hexagon_Y2_dcinva,   hexagon_Y2_dczeroa, hexagon_Y4_l2fetch, hexagon_Y5_l2fetch, hexagon_circ_ldb,   hexagon_circ_ldd, hexagon_circ_ldh, hexagon_circ_ldub, hexagon_circ_lduh,   hexagon_circ_ldw, hexagon_circ_stb, hexagon_circ_std, hexagon_circ_sth,   hexagon_circ_sthhi, hexagon_circ_stw, hexagon_prefetch, hexagon_vmemcpy,   hexagon_vmemset, mips_absq_s_ph, mips_absq_s_qb, mips_absq_s_w,   mips_add_a_b, mips_add_a_d, mips_add_a_h, mips_add_a_w,   mips_addq_ph, mips_addq_s_ph, mips_addq_s_w, mips_addqh_ph,   mips_addqh_r_ph, mips_addqh_r_w, mips_addqh_w, mips_adds_a_b,   mips_adds_a_d, mips_adds_a_h, mips_adds_a_w, mips_adds_s_b,   mips_adds_s_d, mips_adds_s_h, mips_adds_s_w, mips_adds_u_b,   mips_adds_u_d, mips_adds_u_h, mips_adds_u_w, mips_addsc,   mips_addu_ph, mips_addu_qb, mips_addu_s_ph, mips_addu_s_qb,   mips_adduh_qb, mips_adduh_r_qb, mips_addv_b, mips_addv_d,   mips_addv_h, mips_addv_w, mips_addvi_b, mips_addvi_d,   mips_addvi_h, mips_addvi_w, mips_addwc, mips_and_v,   mips_andi_b, mips_append, mips_asub_s_b, mips_asub_s_d,   mips_asub_s_h, mips_asub_s_w, mips_asub_u_b, mips_asub_u_d,   mips_asub_u_h, mips_asub_u_w, mips_ave_s_b, mips_ave_s_d,   mips_ave_s_h, mips_ave_s_w, mips_ave_u_b, mips_ave_u_d,   mips_ave_u_h, mips_ave_u_w, mips_aver_s_b, mips_aver_s_d,   mips_aver_s_h, mips_aver_s_w, mips_aver_u_b, mips_aver_u_d,   mips_aver_u_h, mips_aver_u_w, mips_balign, mips_bclr_b,   mips_bclr_d, mips_bclr_h, mips_bclr_w, mips_bclri_b,   mips_bclri_d, mips_bclri_h, mips_bclri_w, mips_binsl_b,   mips_binsl_d, mips_binsl_h, mips_binsl_w, mips_binsli_b,   mips_binsli_d, mips_binsli_h, mips_binsli_w, mips_binsr_b,   mips_binsr_d, mips_binsr_h, mips_binsr_w, mips_binsri_b,   mips_binsri_d, mips_binsri_h, mips_binsri_w, mips_bitrev,   mips_bmnz_v, mips_bmnzi_b, mips_bmz_v, mips_bmzi_b,   mips_bneg_b, mips_bneg_d, mips_bneg_h, mips_bneg_w,   mips_bnegi_b, mips_bnegi_d, mips_bnegi_h, mips_bnegi_w,   mips_bnz_b, mips_bnz_d, mips_bnz_h, mips_bnz_v,   mips_bnz_w, mips_bposge32, mips_bsel_v, mips_bseli_b,   mips_bset_b, mips_bset_d, mips_bset_h, mips_bset_w,   mips_bseti_b, mips_bseti_d, mips_bseti_h, mips_bseti_w,   mips_bz_b, mips_bz_d, mips_bz_h, mips_bz_v,   mips_bz_w, mips_ceq_b, mips_ceq_d, mips_ceq_h,   mips_ceq_w, mips_ceqi_b, mips_ceqi_d, mips_ceqi_h,   mips_ceqi_w, mips_cfcmsa, mips_cle_s_b, mips_cle_s_d,   mips_cle_s_h, mips_cle_s_w, mips_cle_u_b, mips_cle_u_d,   mips_cle_u_h, mips_cle_u_w, mips_clei_s_b, mips_clei_s_d,   mips_clei_s_h, mips_clei_s_w, mips_clei_u_b, mips_clei_u_d,   mips_clei_u_h, mips_clei_u_w, mips_clt_s_b, mips_clt_s_d,   mips_clt_s_h, mips_clt_s_w, mips_clt_u_b, mips_clt_u_d,   mips_clt_u_h, mips_clt_u_w, mips_clti_s_b, mips_clti_s_d,   mips_clti_s_h, mips_clti_s_w, mips_clti_u_b, mips_clti_u_d,   mips_clti_u_h, mips_clti_u_w, mips_cmp_eq_ph, mips_cmp_le_ph,   mips_cmp_lt_ph, mips_cmpgdu_eq_qb, mips_cmpgdu_le_qb, mips_cmpgdu_lt_qb,   mips_cmpgu_eq_qb, mips_cmpgu_le_qb, mips_cmpgu_lt_qb, mips_cmpu_eq_qb,   mips_cmpu_le_qb, mips_cmpu_lt_qb, mips_copy_s_b, mips_copy_s_d,   mips_copy_s_h, mips_copy_s_w, mips_copy_u_b, mips_copy_u_d,   mips_copy_u_h, mips_copy_u_w, mips_ctcmsa, mips_div_s_b,   mips_div_s_d, mips_div_s_h, mips_div_s_w, mips_div_u_b,   mips_div_u_d, mips_div_u_h, mips_div_u_w, mips_dlsa,   mips_dotp_s_d, mips_dotp_s_h, mips_dotp_s_w, mips_dotp_u_d,   mips_dotp_u_h, mips_dotp_u_w, mips_dpa_w_ph, mips_dpadd_s_d,   mips_dpadd_s_h, mips_dpadd_s_w, mips_dpadd_u_d, mips_dpadd_u_h,   mips_dpadd_u_w, mips_dpaq_s_w_ph, mips_dpaq_sa_l_w, mips_dpaqx_s_w_ph,   mips_dpaqx_sa_w_ph, mips_dpau_h_qbl, mips_dpau_h_qbr, mips_dpax_w_ph,   mips_dps_w_ph, mips_dpsq_s_w_ph, mips_dpsq_sa_l_w, mips_dpsqx_s_w_ph,   mips_dpsqx_sa_w_ph, mips_dpsu_h_qbl, mips_dpsu_h_qbr, mips_dpsub_s_d,   mips_dpsub_s_h, mips_dpsub_s_w, mips_dpsub_u_d, mips_dpsub_u_h,   mips_dpsub_u_w, mips_dpsx_w_ph, mips_extp, mips_extpdp,   mips_extr_r_w, mips_extr_rs_w, mips_extr_s_h, mips_extr_w,   mips_fadd_d, mips_fadd_w, mips_fcaf_d, mips_fcaf_w,   mips_fceq_d, mips_fceq_w, mips_fclass_d, mips_fclass_w,   mips_fcle_d, mips_fcle_w, mips_fclt_d, mips_fclt_w,   mips_fcne_d, mips_fcne_w, mips_fcor_d, mips_fcor_w,   mips_fcueq_d, mips_fcueq_w, mips_fcule_d, mips_fcule_w,   mips_fcult_d, mips_fcult_w, mips_fcun_d, mips_fcun_w,   mips_fcune_d, mips_fcune_w, mips_fdiv_d, mips_fdiv_w,   mips_fexdo_h, mips_fexdo_w, mips_fexp2_d, mips_fexp2_w,   mips_fexupl_d, mips_fexupl_w, mips_fexupr_d, mips_fexupr_w,   mips_ffint_s_d, mips_ffint_s_w, mips_ffint_u_d, mips_ffint_u_w,   mips_ffql_d, mips_ffql_w, mips_ffqr_d, mips_ffqr_w,   mips_fill_b, mips_fill_d, mips_fill_h, mips_fill_w,   mips_flog2_d, mips_flog2_w, mips_fmadd_d, mips_fmadd_w,   mips_fmax_a_d, mips_fmax_a_w, mips_fmax_d, mips_fmax_w,   mips_fmin_a_d, mips_fmin_a_w, mips_fmin_d, mips_fmin_w,   mips_fmsub_d, mips_fmsub_w, mips_fmul_d, mips_fmul_w,   mips_frcp_d, mips_frcp_w, mips_frint_d, mips_frint_w,   mips_frsqrt_d, mips_frsqrt_w, mips_fsaf_d, mips_fsaf_w,   mips_fseq_d, mips_fseq_w, mips_fsle_d, mips_fsle_w,   mips_fslt_d, mips_fslt_w, mips_fsne_d, mips_fsne_w,   mips_fsor_d, mips_fsor_w, mips_fsqrt_d, mips_fsqrt_w,   mips_fsub_d, mips_fsub_w, mips_fsueq_d, mips_fsueq_w,   mips_fsule_d, mips_fsule_w, mips_fsult_d, mips_fsult_w,   mips_fsun_d, mips_fsun_w, mips_fsune_d, mips_fsune_w,   mips_ftint_s_d, mips_ftint_s_w, mips_ftint_u_d, mips_ftint_u_w,   mips_ftq_h, mips_ftq_w, mips_ftrunc_s_d, mips_ftrunc_s_w,   mips_ftrunc_u_d, mips_ftrunc_u_w, mips_hadd_s_d, mips_hadd_s_h,   mips_hadd_s_w, mips_hadd_u_d, mips_hadd_u_h, mips_hadd_u_w,   mips_hsub_s_d, mips_hsub_s_h, mips_hsub_s_w, mips_hsub_u_d,   mips_hsub_u_h, mips_hsub_u_w, mips_ilvev_b, mips_ilvev_d,   mips_ilvev_h, mips_ilvev_w, mips_ilvl_b, mips_ilvl_d,   mips_ilvl_h, mips_ilvl_w, mips_ilvod_b, mips_ilvod_d,   mips_ilvod_h, mips_ilvod_w, mips_ilvr_b, mips_ilvr_d,   mips_ilvr_h, mips_ilvr_w, mips_insert_b, mips_insert_d,   mips_insert_h, mips_insert_w, mips_insv, mips_insve_b,   mips_insve_d, mips_insve_h, mips_insve_w, mips_lbux,   mips_ld_b, mips_ld_d, mips_ld_h, mips_ld_w,   mips_ldi_b, mips_ldi_d, mips_ldi_h, mips_ldi_w,   mips_lhx, mips_lsa, mips_lwx, mips_madd,   mips_madd_q_h, mips_madd_q_w, mips_maddr_q_h, mips_maddr_q_w,   mips_maddu, mips_maddv_b, mips_maddv_d, mips_maddv_h,   mips_maddv_w, mips_maq_s_w_phl, mips_maq_s_w_phr, mips_maq_sa_w_phl,   mips_maq_sa_w_phr, mips_max_a_b, mips_max_a_d, mips_max_a_h,   mips_max_a_w, mips_max_s_b, mips_max_s_d, mips_max_s_h,   mips_max_s_w, mips_max_u_b, mips_max_u_d, mips_max_u_h,   mips_max_u_w, mips_maxi_s_b, mips_maxi_s_d, mips_maxi_s_h,   mips_maxi_s_w, mips_maxi_u_b, mips_maxi_u_d, mips_maxi_u_h,   mips_maxi_u_w, mips_min_a_b, mips_min_a_d, mips_min_a_h,   mips_min_a_w, mips_min_s_b, mips_min_s_d, mips_min_s_h,   mips_min_s_w, mips_min_u_b, mips_min_u_d, mips_min_u_h,   mips_min_u_w, mips_mini_s_b, mips_mini_s_d, mips_mini_s_h,   mips_mini_s_w, mips_mini_u_b, mips_mini_u_d, mips_mini_u_h,   mips_mini_u_w, mips_mod_s_b, mips_mod_s_d, mips_mod_s_h,   mips_mod_s_w, mips_mod_u_b, mips_mod_u_d, mips_mod_u_h,   mips_mod_u_w, mips_modsub, mips_move_v, mips_msub,   mips_msub_q_h, mips_msub_q_w, mips_msubr_q_h, mips_msubr_q_w,   mips_msubu, mips_msubv_b, mips_msubv_d, mips_msubv_h,   mips_msubv_w, mips_mthlip, mips_mul_ph, mips_mul_q_h,   mips_mul_q_w, mips_mul_s_ph, mips_muleq_s_w_phl, mips_muleq_s_w_phr,   mips_muleu_s_ph_qbl, mips_muleu_s_ph_qbr, mips_mulq_rs_ph, mips_mulq_rs_w,   mips_mulq_s_ph, mips_mulq_s_w, mips_mulr_q_h, mips_mulr_q_w,   mips_mulsa_w_ph, mips_mulsaq_s_w_ph, mips_mult, mips_multu,   mips_mulv_b, mips_mulv_d, mips_mulv_h, mips_mulv_w,   mips_nloc_b, mips_nloc_d, mips_nloc_h, mips_nloc_w,   mips_nlzc_b, mips_nlzc_d, mips_nlzc_h, mips_nlzc_w,   mips_nor_v, mips_nori_b, mips_or_v, mips_ori_b,   mips_packrl_ph, mips_pckev_b, mips_pckev_d, mips_pckev_h,   mips_pckev_w, mips_pckod_b, mips_pckod_d, mips_pckod_h,   mips_pckod_w, mips_pcnt_b, mips_pcnt_d, mips_pcnt_h,   mips_pcnt_w, mips_pick_ph, mips_pick_qb, mips_preceq_w_phl,   mips_preceq_w_phr, mips_precequ_ph_qbl, mips_precequ_ph_qbla, mips_precequ_ph_qbr,   mips_precequ_ph_qbra, mips_preceu_ph_qbl, mips_preceu_ph_qbla, mips_preceu_ph_qbr,   mips_preceu_ph_qbra, mips_precr_qb_ph, mips_precr_sra_ph_w, mips_precr_sra_r_ph_w,   mips_precrq_ph_w, mips_precrq_qb_ph, mips_precrq_rs_ph_w, mips_precrqu_s_qb_ph,   mips_prepend, mips_raddu_w_qb, mips_rddsp, mips_repl_ph,   mips_repl_qb, mips_sat_s_b, mips_sat_s_d, mips_sat_s_h,   mips_sat_s_w, mips_sat_u_b, mips_sat_u_d, mips_sat_u_h,   mips_sat_u_w, mips_shf_b, mips_shf_h, mips_shf_w,   mips_shilo, mips_shll_ph, mips_shll_qb, mips_shll_s_ph,   mips_shll_s_w, mips_shra_ph, mips_shra_qb, mips_shra_r_ph,   mips_shra_r_qb, mips_shra_r_w, mips_shrl_ph, mips_shrl_qb,   mips_sld_b, mips_sld_d, mips_sld_h, mips_sld_w,   mips_sldi_b, mips_sldi_d, mips_sldi_h, mips_sldi_w,   mips_sll_b, mips_sll_d, mips_sll_h, mips_sll_w,   mips_slli_b, mips_slli_d, mips_slli_h, mips_slli_w,   mips_splat_b, mips_splat_d, mips_splat_h, mips_splat_w,   mips_splati_b, mips_splati_d, mips_splati_h, mips_splati_w,   mips_sra_b, mips_sra_d, mips_sra_h, mips_sra_w,   mips_srai_b, mips_srai_d, mips_srai_h, mips_srai_w,   mips_srar_b, mips_srar_d, mips_srar_h, mips_srar_w,   mips_srari_b, mips_srari_d, mips_srari_h, mips_srari_w,   mips_srl_b, mips_srl_d, mips_srl_h, mips_srl_w,   mips_srli_b, mips_srli_d, mips_srli_h, mips_srli_w,   mips_srlr_b, mips_srlr_d, mips_srlr_h, mips_srlr_w,   mips_srlri_b, mips_srlri_d, mips_srlri_h, mips_srlri_w,   mips_st_b, mips_st_d, mips_st_h, mips_st_w,   mips_subq_ph, mips_subq_s_ph, mips_subq_s_w, mips_subqh_ph,   mips_subqh_r_ph, mips_subqh_r_w, mips_subqh_w, mips_subs_s_b,   mips_subs_s_d, mips_subs_s_h, mips_subs_s_w, mips_subs_u_b,   mips_subs_u_d, mips_subs_u_h, mips_subs_u_w, mips_subsus_u_b,   mips_subsus_u_d, mips_subsus_u_h, mips_subsus_u_w, mips_subsuu_s_b,   mips_subsuu_s_d, mips_subsuu_s_h, mips_subsuu_s_w, mips_subu_ph,   mips_subu_qb, mips_subu_s_ph, mips_subu_s_qb, mips_subuh_qb,   mips_subuh_r_qb, mips_subv_b, mips_subv_d, mips_subv_h,   mips_subv_w, mips_subvi_b, mips_subvi_d, mips_subvi_h,   mips_subvi_w, mips_vshf_b, mips_vshf_d, mips_vshf_h,   mips_vshf_w, mips_wrdsp, mips_xor_v, mips_xori_b,   nvvm_add_rm_d, nvvm_add_rm_f, nvvm_add_rm_ftz_f, nvvm_add_rn_d,   nvvm_add_rn_f, nvvm_add_rn_ftz_f, nvvm_add_rp_d, nvvm_add_rp_f,   nvvm_add_rp_ftz_f, nvvm_add_rz_d, nvvm_add_rz_f, nvvm_add_rz_ftz_f,   nvvm_atomic_add_gen_f_cta, nvvm_atomic_add_gen_f_sys, nvvm_atomic_add_gen_i_cta, nvvm_atomic_add_gen_i_sys,   nvvm_atomic_and_gen_i_cta, nvvm_atomic_and_gen_i_sys, nvvm_atomic_cas_gen_i_cta, nvvm_atomic_cas_gen_i_sys,   nvvm_atomic_dec_gen_i_cta, nvvm_atomic_dec_gen_i_sys, nvvm_atomic_exch_gen_i_cta, nvvm_atomic_exch_gen_i_sys,   nvvm_atomic_inc_gen_i_cta, nvvm_atomic_inc_gen_i_sys, nvvm_atomic_load_add_f32, nvvm_atomic_load_add_f64,   nvvm_atomic_load_dec_32, nvvm_atomic_load_inc_32, nvvm_atomic_max_gen_i_cta, nvvm_atomic_max_gen_i_sys,   nvvm_atomic_min_gen_i_cta, nvvm_atomic_min_gen_i_sys, nvvm_atomic_or_gen_i_cta, nvvm_atomic_or_gen_i_sys,   nvvm_atomic_xor_gen_i_cta, nvvm_atomic_xor_gen_i_sys, nvvm_bar_sync, nvvm_bar_warp_sync,   nvvm_barrier, nvvm_barrier_n, nvvm_barrier_sync, nvvm_barrier_sync_cnt,   nvvm_barrier0, nvvm_barrier0_and, nvvm_barrier0_or, nvvm_barrier0_popc,   nvvm_bitcast_d2ll, nvvm_bitcast_f2i, nvvm_bitcast_i2f, nvvm_bitcast_ll2d,   nvvm_ceil_d, nvvm_ceil_f, nvvm_ceil_ftz_f, nvvm_compiler_error,   nvvm_compiler_warn, nvvm_cos_approx_f, nvvm_cos_approx_ftz_f, nvvm_d2f_rm,   nvvm_d2f_rm_ftz, nvvm_d2f_rn, nvvm_d2f_rn_ftz, nvvm_d2f_rp,   nvvm_d2f_rp_ftz, nvvm_d2f_rz, nvvm_d2f_rz_ftz, nvvm_d2i_hi,   nvvm_d2i_lo, nvvm_d2i_rm, nvvm_d2i_rn, nvvm_d2i_rp,   nvvm_d2i_rz, nvvm_d2ll_rm, nvvm_d2ll_rn, nvvm_d2ll_rp,   nvvm_d2ll_rz, nvvm_d2ui_rm, nvvm_d2ui_rn, nvvm_d2ui_rp,   nvvm_d2ui_rz, nvvm_d2ull_rm, nvvm_d2ull_rn, nvvm_d2ull_rp,   nvvm_d2ull_rz, nvvm_div_approx_f, nvvm_div_approx_ftz_f, nvvm_div_rm_d,   nvvm_div_rm_f, nvvm_div_rm_ftz_f, nvvm_div_rn_d, nvvm_div_rn_f,   nvvm_div_rn_ftz_f, nvvm_div_rp_d, nvvm_div_rp_f, nvvm_div_rp_ftz_f,   nvvm_div_rz_d, nvvm_div_rz_f, nvvm_div_rz_ftz_f, nvvm_ex2_approx_d,   nvvm_ex2_approx_f, nvvm_ex2_approx_ftz_f, nvvm_f2h_rn, nvvm_f2h_rn_ftz,   nvvm_f2i_rm, nvvm_f2i_rm_ftz, nvvm_f2i_rn, nvvm_f2i_rn_ftz,   nvvm_f2i_rp, nvvm_f2i_rp_ftz, nvvm_f2i_rz, nvvm_f2i_rz_ftz,   nvvm_f2ll_rm, nvvm_f2ll_rm_ftz, nvvm_f2ll_rn, nvvm_f2ll_rn_ftz,   nvvm_f2ll_rp, nvvm_f2ll_rp_ftz, nvvm_f2ll_rz, nvvm_f2ll_rz_ftz,   nvvm_f2ui_rm, nvvm_f2ui_rm_ftz, nvvm_f2ui_rn, nvvm_f2ui_rn_ftz,   nvvm_f2ui_rp, nvvm_f2ui_rp_ftz, nvvm_f2ui_rz, nvvm_f2ui_rz_ftz,   nvvm_f2ull_rm, nvvm_f2ull_rm_ftz, nvvm_f2ull_rn, nvvm_f2ull_rn_ftz,   nvvm_f2ull_rp, nvvm_f2ull_rp_ftz, nvvm_f2ull_rz, nvvm_f2ull_rz_ftz,   nvvm_fabs_d, nvvm_fabs_f, nvvm_fabs_ftz_f, nvvm_floor_d,   nvvm_floor_f, nvvm_floor_ftz_f, nvvm_fma_rm_d, nvvm_fma_rm_f,   nvvm_fma_rm_ftz_f, nvvm_fma_rn_d, nvvm_fma_rn_f, nvvm_fma_rn_ftz_f,   nvvm_fma_rp_d, nvvm_fma_rp_f, nvvm_fma_rp_ftz_f, nvvm_fma_rz_d,   nvvm_fma_rz_f, nvvm_fma_rz_ftz_f, nvvm_fmax_d, nvvm_fmax_f,   nvvm_fmax_ftz_f, nvvm_fmin_d, nvvm_fmin_f, nvvm_fmin_ftz_f,   nvvm_fns, nvvm_i2d_rm, nvvm_i2d_rn, nvvm_i2d_rp,   nvvm_i2d_rz, nvvm_i2f_rm, nvvm_i2f_rn, nvvm_i2f_rp,   nvvm_i2f_rz, nvvm_isspacep_const, nvvm_isspacep_global, nvvm_isspacep_local,   nvvm_isspacep_shared, nvvm_istypep_sampler, nvvm_istypep_surface, nvvm_istypep_texture,   nvvm_ldg_global_f, nvvm_ldg_global_i, nvvm_ldg_global_p, nvvm_ldu_global_f,   nvvm_ldu_global_i, nvvm_ldu_global_p, nvvm_lg2_approx_d, nvvm_lg2_approx_f,   nvvm_lg2_approx_ftz_f, nvvm_ll2d_rm, nvvm_ll2d_rn, nvvm_ll2d_rp,   nvvm_ll2d_rz, nvvm_ll2f_rm, nvvm_ll2f_rn, nvvm_ll2f_rp,   nvvm_ll2f_rz, nvvm_lohi_i2d, nvvm_match_all_sync_i32p, nvvm_match_all_sync_i64p,   nvvm_match_any_sync_i32, nvvm_match_any_sync_i64, nvvm_membar_cta, nvvm_membar_gl,   nvvm_membar_sys, nvvm_move_double, nvvm_move_float, nvvm_move_i16,   nvvm_move_i32, nvvm_move_i64, nvvm_move_ptr, nvvm_mul_rm_d,   nvvm_mul_rm_f, nvvm_mul_rm_ftz_f, nvvm_mul_rn_d, nvvm_mul_rn_f,   nvvm_mul_rn_ftz_f, nvvm_mul_rp_d, nvvm_mul_rp_f, nvvm_mul_rp_ftz_f,   nvvm_mul_rz_d, nvvm_mul_rz_f, nvvm_mul_rz_ftz_f, nvvm_mul24_i,   nvvm_mul24_ui, nvvm_mulhi_i, nvvm_mulhi_ll, nvvm_mulhi_ui,   nvvm_mulhi_ull, nvvm_prmt, nvvm_ptr_constant_to_gen, nvvm_ptr_gen_to_constant,   nvvm_ptr_gen_to_global, nvvm_ptr_gen_to_local, nvvm_ptr_gen_to_param, nvvm_ptr_gen_to_shared,   nvvm_ptr_global_to_gen, nvvm_ptr_local_to_gen, nvvm_ptr_shared_to_gen, nvvm_rcp_approx_ftz_d,   nvvm_rcp_rm_d, nvvm_rcp_rm_f, nvvm_rcp_rm_ftz_f, nvvm_rcp_rn_d,   nvvm_rcp_rn_f, nvvm_rcp_rn_ftz_f, nvvm_rcp_rp_d, nvvm_rcp_rp_f,   nvvm_rcp_rp_ftz_f, nvvm_rcp_rz_d, nvvm_rcp_rz_f, nvvm_rcp_rz_ftz_f,   nvvm_read_ptx_sreg_clock, nvvm_read_ptx_sreg_clock64, nvvm_read_ptx_sreg_ctaid_w, nvvm_read_ptx_sreg_ctaid_x,   nvvm_read_ptx_sreg_ctaid_y, nvvm_read_ptx_sreg_ctaid_z, nvvm_read_ptx_sreg_envreg0, nvvm_read_ptx_sreg_envreg1,   nvvm_read_ptx_sreg_envreg10, nvvm_read_ptx_sreg_envreg11, nvvm_read_ptx_sreg_envreg12, nvvm_read_ptx_sreg_envreg13,   nvvm_read_ptx_sreg_envreg14, nvvm_read_ptx_sreg_envreg15, nvvm_read_ptx_sreg_envreg16, nvvm_read_ptx_sreg_envreg17,   nvvm_read_ptx_sreg_envreg18, nvvm_read_ptx_sreg_envreg19, nvvm_read_ptx_sreg_envreg2, nvvm_read_ptx_sreg_envreg20,   nvvm_read_ptx_sreg_envreg21, nvvm_read_ptx_sreg_envreg22, nvvm_read_ptx_sreg_envreg23, nvvm_read_ptx_sreg_envreg24,   nvvm_read_ptx_sreg_envreg25, nvvm_read_ptx_sreg_envreg26, nvvm_read_ptx_sreg_envreg27, nvvm_read_ptx_sreg_envreg28,   nvvm_read_ptx_sreg_envreg29, nvvm_read_ptx_sreg_envreg3, nvvm_read_ptx_sreg_envreg30, nvvm_read_ptx_sreg_envreg31,   nvvm_read_ptx_sreg_envreg4, nvvm_read_ptx_sreg_envreg5, nvvm_read_ptx_sreg_envreg6, nvvm_read_ptx_sreg_envreg7,   nvvm_read_ptx_sreg_envreg8, nvvm_read_ptx_sreg_envreg9, nvvm_read_ptx_sreg_gridid, nvvm_read_ptx_sreg_laneid,   nvvm_read_ptx_sreg_lanemask_eq, nvvm_read_ptx_sreg_lanemask_ge, nvvm_read_ptx_sreg_lanemask_gt, nvvm_read_ptx_sreg_lanemask_le,   nvvm_read_ptx_sreg_lanemask_lt, nvvm_read_ptx_sreg_nctaid_w, nvvm_read_ptx_sreg_nctaid_x, nvvm_read_ptx_sreg_nctaid_y,   nvvm_read_ptx_sreg_nctaid_z, nvvm_read_ptx_sreg_nsmid, nvvm_read_ptx_sreg_ntid_w, nvvm_read_ptx_sreg_ntid_x,   nvvm_read_ptx_sreg_ntid_y, nvvm_read_ptx_sreg_ntid_z, nvvm_read_ptx_sreg_nwarpid, nvvm_read_ptx_sreg_pm0,   nvvm_read_ptx_sreg_pm1, nvvm_read_ptx_sreg_pm2, nvvm_read_ptx_sreg_pm3, nvvm_read_ptx_sreg_smid,   nvvm_read_ptx_sreg_tid_w, nvvm_read_ptx_sreg_tid_x, nvvm_read_ptx_sreg_tid_y, nvvm_read_ptx_sreg_tid_z,   nvvm_read_ptx_sreg_warpid, nvvm_read_ptx_sreg_warpsize, nvvm_reflect, nvvm_rotate_b32,   nvvm_rotate_b64, nvvm_rotate_right_b64, nvvm_round_d, nvvm_round_f,   nvvm_round_ftz_f, nvvm_rsqrt_approx_d, nvvm_rsqrt_approx_f, nvvm_rsqrt_approx_ftz_f,   nvvm_sad_i, nvvm_sad_ui, nvvm_saturate_d, nvvm_saturate_f,   nvvm_saturate_ftz_f, nvvm_shfl_bfly_f32, nvvm_shfl_bfly_i32, nvvm_shfl_down_f32,   nvvm_shfl_down_i32, nvvm_shfl_idx_f32, nvvm_shfl_idx_i32, nvvm_shfl_sync_bfly_f32,   nvvm_shfl_sync_bfly_i32, nvvm_shfl_sync_down_f32, nvvm_shfl_sync_down_i32, nvvm_shfl_sync_idx_f32,   nvvm_shfl_sync_idx_i32, nvvm_shfl_sync_up_f32, nvvm_shfl_sync_up_i32, nvvm_shfl_up_f32,   nvvm_shfl_up_i32, nvvm_sin_approx_f, nvvm_sin_approx_ftz_f, nvvm_sqrt_approx_f,   nvvm_sqrt_approx_ftz_f, nvvm_sqrt_f, nvvm_sqrt_rm_d, nvvm_sqrt_rm_f,   nvvm_sqrt_rm_ftz_f, nvvm_sqrt_rn_d, nvvm_sqrt_rn_f, nvvm_sqrt_rn_ftz_f,   nvvm_sqrt_rp_d, nvvm_sqrt_rp_f, nvvm_sqrt_rp_ftz_f, nvvm_sqrt_rz_d,   nvvm_sqrt_rz_f, nvvm_sqrt_rz_ftz_f, nvvm_suld_1d_array_i16_clamp, nvvm_suld_1d_array_i16_trap,   nvvm_suld_1d_array_i16_zero, nvvm_suld_1d_array_i32_clamp, nvvm_suld_1d_array_i32_trap, nvvm_suld_1d_array_i32_zero,   nvvm_suld_1d_array_i64_clamp, nvvm_suld_1d_array_i64_trap, nvvm_suld_1d_array_i64_zero, nvvm_suld_1d_array_i8_clamp,   nvvm_suld_1d_array_i8_trap, nvvm_suld_1d_array_i8_zero, nvvm_suld_1d_array_v2i16_clamp, nvvm_suld_1d_array_v2i16_trap,   nvvm_suld_1d_array_v2i16_zero, nvvm_suld_1d_array_v2i32_clamp, nvvm_suld_1d_array_v2i32_trap, nvvm_suld_1d_array_v2i32_zero,   nvvm_suld_1d_array_v2i64_clamp, nvvm_suld_1d_array_v2i64_trap, nvvm_suld_1d_array_v2i64_zero, nvvm_suld_1d_array_v2i8_clamp,   nvvm_suld_1d_array_v2i8_trap, nvvm_suld_1d_array_v2i8_zero, nvvm_suld_1d_array_v4i16_clamp, nvvm_suld_1d_array_v4i16_trap,   nvvm_suld_1d_array_v4i16_zero, nvvm_suld_1d_array_v4i32_clamp, nvvm_suld_1d_array_v4i32_trap, nvvm_suld_1d_array_v4i32_zero,   nvvm_suld_1d_array_v4i8_clamp, nvvm_suld_1d_array_v4i8_trap, nvvm_suld_1d_array_v4i8_zero, nvvm_suld_1d_i16_clamp,   nvvm_suld_1d_i16_trap, nvvm_suld_1d_i16_zero, nvvm_suld_1d_i32_clamp, nvvm_suld_1d_i32_trap,   nvvm_suld_1d_i32_zero, nvvm_suld_1d_i64_clamp, nvvm_suld_1d_i64_trap, nvvm_suld_1d_i64_zero,   nvvm_suld_1d_i8_clamp, nvvm_suld_1d_i8_trap, nvvm_suld_1d_i8_zero, nvvm_suld_1d_v2i16_clamp,   nvvm_suld_1d_v2i16_trap, nvvm_suld_1d_v2i16_zero, nvvm_suld_1d_v2i32_clamp, nvvm_suld_1d_v2i32_trap,   nvvm_suld_1d_v2i32_zero, nvvm_suld_1d_v2i64_clamp, nvvm_suld_1d_v2i64_trap, nvvm_suld_1d_v2i64_zero,   nvvm_suld_1d_v2i8_clamp, nvvm_suld_1d_v2i8_trap, nvvm_suld_1d_v2i8_zero, nvvm_suld_1d_v4i16_clamp,   nvvm_suld_1d_v4i16_trap, nvvm_suld_1d_v4i16_zero, nvvm_suld_1d_v4i32_clamp, nvvm_suld_1d_v4i32_trap,   nvvm_suld_1d_v4i32_zero, nvvm_suld_1d_v4i8_clamp, nvvm_suld_1d_v4i8_trap, nvvm_suld_1d_v4i8_zero,   nvvm_suld_2d_array_i16_clamp, nvvm_suld_2d_array_i16_trap, nvvm_suld_2d_array_i16_zero, nvvm_suld_2d_array_i32_clamp,   nvvm_suld_2d_array_i32_trap, nvvm_suld_2d_array_i32_zero, nvvm_suld_2d_array_i64_clamp, nvvm_suld_2d_array_i64_trap,   nvvm_suld_2d_array_i64_zero, nvvm_suld_2d_array_i8_clamp, nvvm_suld_2d_array_i8_trap, nvvm_suld_2d_array_i8_zero,   nvvm_suld_2d_array_v2i16_clamp, nvvm_suld_2d_array_v2i16_trap, nvvm_suld_2d_array_v2i16_zero, nvvm_suld_2d_array_v2i32_clamp,   nvvm_suld_2d_array_v2i32_trap, nvvm_suld_2d_array_v2i32_zero, nvvm_suld_2d_array_v2i64_clamp, nvvm_suld_2d_array_v2i64_trap,   nvvm_suld_2d_array_v2i64_zero, nvvm_suld_2d_array_v2i8_clamp, nvvm_suld_2d_array_v2i8_trap, nvvm_suld_2d_array_v2i8_zero,   nvvm_suld_2d_array_v4i16_clamp, nvvm_suld_2d_array_v4i16_trap, nvvm_suld_2d_array_v4i16_zero, nvvm_suld_2d_array_v4i32_clamp,   nvvm_suld_2d_array_v4i32_trap, nvvm_suld_2d_array_v4i32_zero, nvvm_suld_2d_array_v4i8_clamp, nvvm_suld_2d_array_v4i8_trap,   nvvm_suld_2d_array_v4i8_zero, nvvm_suld_2d_i16_clamp, nvvm_suld_2d_i16_trap, nvvm_suld_2d_i16_zero,   nvvm_suld_2d_i32_clamp, nvvm_suld_2d_i32_trap, nvvm_suld_2d_i32_zero, nvvm_suld_2d_i64_clamp,   nvvm_suld_2d_i64_trap, nvvm_suld_2d_i64_zero, nvvm_suld_2d_i8_clamp, nvvm_suld_2d_i8_trap,   nvvm_suld_2d_i8_zero, nvvm_suld_2d_v2i16_clamp, nvvm_suld_2d_v2i16_trap, nvvm_suld_2d_v2i16_zero,   nvvm_suld_2d_v2i32_clamp, nvvm_suld_2d_v2i32_trap, nvvm_suld_2d_v2i32_zero, nvvm_suld_2d_v2i64_clamp,   nvvm_suld_2d_v2i64_trap, nvvm_suld_2d_v2i64_zero, nvvm_suld_2d_v2i8_clamp, nvvm_suld_2d_v2i8_trap,   nvvm_suld_2d_v2i8_zero, nvvm_suld_2d_v4i16_clamp, nvvm_suld_2d_v4i16_trap, nvvm_suld_2d_v4i16_zero,   nvvm_suld_2d_v4i32_clamp, nvvm_suld_2d_v4i32_trap, nvvm_suld_2d_v4i32_zero, nvvm_suld_2d_v4i8_clamp,   nvvm_suld_2d_v4i8_trap, nvvm_suld_2d_v4i8_zero, nvvm_suld_3d_i16_clamp, nvvm_suld_3d_i16_trap,   nvvm_suld_3d_i16_zero, nvvm_suld_3d_i32_clamp, nvvm_suld_3d_i32_trap, nvvm_suld_3d_i32_zero,   nvvm_suld_3d_i64_clamp, nvvm_suld_3d_i64_trap, nvvm_suld_3d_i64_zero, nvvm_suld_3d_i8_clamp,   nvvm_suld_3d_i8_trap, nvvm_suld_3d_i8_zero, nvvm_suld_3d_v2i16_clamp, nvvm_suld_3d_v2i16_trap,   nvvm_suld_3d_v2i16_zero, nvvm_suld_3d_v2i32_clamp, nvvm_suld_3d_v2i32_trap, nvvm_suld_3d_v2i32_zero,   nvvm_suld_3d_v2i64_clamp, nvvm_suld_3d_v2i64_trap, nvvm_suld_3d_v2i64_zero, nvvm_suld_3d_v2i8_clamp,   nvvm_suld_3d_v2i8_trap, nvvm_suld_3d_v2i8_zero, nvvm_suld_3d_v4i16_clamp, nvvm_suld_3d_v4i16_trap,   nvvm_suld_3d_v4i16_zero, nvvm_suld_3d_v4i32_clamp, nvvm_suld_3d_v4i32_trap, nvvm_suld_3d_v4i32_zero,   nvvm_suld_3d_v4i8_clamp, nvvm_suld_3d_v4i8_trap, nvvm_suld_3d_v4i8_zero, nvvm_suq_array_size,   nvvm_suq_channel_data_type, nvvm_suq_channel_order, nvvm_suq_depth, nvvm_suq_height,   nvvm_suq_width, nvvm_sust_b_1d_array_i16_clamp, nvvm_sust_b_1d_array_i16_trap, nvvm_sust_b_1d_array_i16_zero,   nvvm_sust_b_1d_array_i32_clamp, nvvm_sust_b_1d_array_i32_trap, nvvm_sust_b_1d_array_i32_zero, nvvm_sust_b_1d_array_i64_clamp,   nvvm_sust_b_1d_array_i64_trap, nvvm_sust_b_1d_array_i64_zero, nvvm_sust_b_1d_array_i8_clamp, nvvm_sust_b_1d_array_i8_trap,   nvvm_sust_b_1d_array_i8_zero, nvvm_sust_b_1d_array_v2i16_clamp, nvvm_sust_b_1d_array_v2i16_trap, nvvm_sust_b_1d_array_v2i16_zero,   nvvm_sust_b_1d_array_v2i32_clamp, nvvm_sust_b_1d_array_v2i32_trap, nvvm_sust_b_1d_array_v2i32_zero, nvvm_sust_b_1d_array_v2i64_clamp,   nvvm_sust_b_1d_array_v2i64_trap, nvvm_sust_b_1d_array_v2i64_zero, nvvm_sust_b_1d_array_v2i8_clamp, nvvm_sust_b_1d_array_v2i8_trap,   nvvm_sust_b_1d_array_v2i8_zero, nvvm_sust_b_1d_array_v4i16_clamp, nvvm_sust_b_1d_array_v4i16_trap, nvvm_sust_b_1d_array_v4i16_zero,   nvvm_sust_b_1d_array_v4i32_clamp, nvvm_sust_b_1d_array_v4i32_trap, nvvm_sust_b_1d_array_v4i32_zero, nvvm_sust_b_1d_array_v4i8_clamp,   nvvm_sust_b_1d_array_v4i8_trap, nvvm_sust_b_1d_array_v4i8_zero, nvvm_sust_b_1d_i16_clamp, nvvm_sust_b_1d_i16_trap,   nvvm_sust_b_1d_i16_zero, nvvm_sust_b_1d_i32_clamp, nvvm_sust_b_1d_i32_trap, nvvm_sust_b_1d_i32_zero,   nvvm_sust_b_1d_i64_clamp, nvvm_sust_b_1d_i64_trap, nvvm_sust_b_1d_i64_zero, nvvm_sust_b_1d_i8_clamp,   nvvm_sust_b_1d_i8_trap, nvvm_sust_b_1d_i8_zero, nvvm_sust_b_1d_v2i16_clamp, nvvm_sust_b_1d_v2i16_trap,   nvvm_sust_b_1d_v2i16_zero, nvvm_sust_b_1d_v2i32_clamp, nvvm_sust_b_1d_v2i32_trap, nvvm_sust_b_1d_v2i32_zero,   nvvm_sust_b_1d_v2i64_clamp, nvvm_sust_b_1d_v2i64_trap, nvvm_sust_b_1d_v2i64_zero, nvvm_sust_b_1d_v2i8_clamp,   nvvm_sust_b_1d_v2i8_trap, nvvm_sust_b_1d_v2i8_zero, nvvm_sust_b_1d_v4i16_clamp, nvvm_sust_b_1d_v4i16_trap,   nvvm_sust_b_1d_v4i16_zero, nvvm_sust_b_1d_v4i32_clamp, nvvm_sust_b_1d_v4i32_trap, nvvm_sust_b_1d_v4i32_zero,   nvvm_sust_b_1d_v4i8_clamp, nvvm_sust_b_1d_v4i8_trap, nvvm_sust_b_1d_v4i8_zero, nvvm_sust_b_2d_array_i16_clamp,   nvvm_sust_b_2d_array_i16_trap, nvvm_sust_b_2d_array_i16_zero, nvvm_sust_b_2d_array_i32_clamp, nvvm_sust_b_2d_array_i32_trap,   nvvm_sust_b_2d_array_i32_zero, nvvm_sust_b_2d_array_i64_clamp, nvvm_sust_b_2d_array_i64_trap, nvvm_sust_b_2d_array_i64_zero,   nvvm_sust_b_2d_array_i8_clamp, nvvm_sust_b_2d_array_i8_trap, nvvm_sust_b_2d_array_i8_zero, nvvm_sust_b_2d_array_v2i16_clamp,   nvvm_sust_b_2d_array_v2i16_trap, nvvm_sust_b_2d_array_v2i16_zero, nvvm_sust_b_2d_array_v2i32_clamp, nvvm_sust_b_2d_array_v2i32_trap,   nvvm_sust_b_2d_array_v2i32_zero, nvvm_sust_b_2d_array_v2i64_clamp, nvvm_sust_b_2d_array_v2i64_trap, nvvm_sust_b_2d_array_v2i64_zero,   nvvm_sust_b_2d_array_v2i8_clamp, nvvm_sust_b_2d_array_v2i8_trap, nvvm_sust_b_2d_array_v2i8_zero, nvvm_sust_b_2d_array_v4i16_clamp,   nvvm_sust_b_2d_array_v4i16_trap, nvvm_sust_b_2d_array_v4i16_zero, nvvm_sust_b_2d_array_v4i32_clamp, nvvm_sust_b_2d_array_v4i32_trap,   nvvm_sust_b_2d_array_v4i32_zero, nvvm_sust_b_2d_array_v4i8_clamp, nvvm_sust_b_2d_array_v4i8_trap, nvvm_sust_b_2d_array_v4i8_zero,   nvvm_sust_b_2d_i16_clamp, nvvm_sust_b_2d_i16_trap, nvvm_sust_b_2d_i16_zero, nvvm_sust_b_2d_i32_clamp,   nvvm_sust_b_2d_i32_trap, nvvm_sust_b_2d_i32_zero, nvvm_sust_b_2d_i64_clamp, nvvm_sust_b_2d_i64_trap,   nvvm_sust_b_2d_i64_zero, nvvm_sust_b_2d_i8_clamp, nvvm_sust_b_2d_i8_trap, nvvm_sust_b_2d_i8_zero,   nvvm_sust_b_2d_v2i16_clamp, nvvm_sust_b_2d_v2i16_trap, nvvm_sust_b_2d_v2i16_zero, nvvm_sust_b_2d_v2i32_clamp,   nvvm_sust_b_2d_v2i32_trap, nvvm_sust_b_2d_v2i32_zero, nvvm_sust_b_2d_v2i64_clamp, nvvm_sust_b_2d_v2i64_trap,   nvvm_sust_b_2d_v2i64_zero, nvvm_sust_b_2d_v2i8_clamp, nvvm_sust_b_2d_v2i8_trap, nvvm_sust_b_2d_v2i8_zero,   nvvm_sust_b_2d_v4i16_clamp, nvvm_sust_b_2d_v4i16_trap, nvvm_sust_b_2d_v4i16_zero, nvvm_sust_b_2d_v4i32_clamp,   nvvm_sust_b_2d_v4i32_trap, nvvm_sust_b_2d_v4i32_zero, nvvm_sust_b_2d_v4i8_clamp, nvvm_sust_b_2d_v4i8_trap,   nvvm_sust_b_2d_v4i8_zero, nvvm_sust_b_3d_i16_clamp, nvvm_sust_b_3d_i16_trap, nvvm_sust_b_3d_i16_zero,   nvvm_sust_b_3d_i32_clamp, nvvm_sust_b_3d_i32_trap, nvvm_sust_b_3d_i32_zero, nvvm_sust_b_3d_i64_clamp,   nvvm_sust_b_3d_i64_trap, nvvm_sust_b_3d_i64_zero, nvvm_sust_b_3d_i8_clamp, nvvm_sust_b_3d_i8_trap,   nvvm_sust_b_3d_i8_zero, nvvm_sust_b_3d_v2i16_clamp, nvvm_sust_b_3d_v2i16_trap, nvvm_sust_b_3d_v2i16_zero,   nvvm_sust_b_3d_v2i32_clamp, nvvm_sust_b_3d_v2i32_trap, nvvm_sust_b_3d_v2i32_zero, nvvm_sust_b_3d_v2i64_clamp,   nvvm_sust_b_3d_v2i64_trap, nvvm_sust_b_3d_v2i64_zero, nvvm_sust_b_3d_v2i8_clamp, nvvm_sust_b_3d_v2i8_trap,   nvvm_sust_b_3d_v2i8_zero, nvvm_sust_b_3d_v4i16_clamp, nvvm_sust_b_3d_v4i16_trap, nvvm_sust_b_3d_v4i16_zero,   nvvm_sust_b_3d_v4i32_clamp, nvvm_sust_b_3d_v4i32_trap, nvvm_sust_b_3d_v4i32_zero, nvvm_sust_b_3d_v4i8_clamp,   nvvm_sust_b_3d_v4i8_trap, nvvm_sust_b_3d_v4i8_zero, nvvm_sust_p_1d_array_i16_trap, nvvm_sust_p_1d_array_i32_trap,   nvvm_sust_p_1d_array_i8_trap, nvvm_sust_p_1d_array_v2i16_trap, nvvm_sust_p_1d_array_v2i32_trap, nvvm_sust_p_1d_array_v2i8_trap,   nvvm_sust_p_1d_array_v4i16_trap, nvvm_sust_p_1d_array_v4i32_trap, nvvm_sust_p_1d_array_v4i8_trap, nvvm_sust_p_1d_i16_trap,   nvvm_sust_p_1d_i32_trap, nvvm_sust_p_1d_i8_trap, nvvm_sust_p_1d_v2i16_trap, nvvm_sust_p_1d_v2i32_trap,   nvvm_sust_p_1d_v2i8_trap, nvvm_sust_p_1d_v4i16_trap, nvvm_sust_p_1d_v4i32_trap, nvvm_sust_p_1d_v4i8_trap,   nvvm_sust_p_2d_array_i16_trap, nvvm_sust_p_2d_array_i32_trap, nvvm_sust_p_2d_array_i8_trap, nvvm_sust_p_2d_array_v2i16_trap,   nvvm_sust_p_2d_array_v2i32_trap, nvvm_sust_p_2d_array_v2i8_trap, nvvm_sust_p_2d_array_v4i16_trap, nvvm_sust_p_2d_array_v4i32_trap,   nvvm_sust_p_2d_array_v4i8_trap, nvvm_sust_p_2d_i16_trap, nvvm_sust_p_2d_i32_trap, nvvm_sust_p_2d_i8_trap,   nvvm_sust_p_2d_v2i16_trap, nvvm_sust_p_2d_v2i32_trap, nvvm_sust_p_2d_v2i8_trap, nvvm_sust_p_2d_v4i16_trap,   nvvm_sust_p_2d_v4i32_trap, nvvm_sust_p_2d_v4i8_trap, nvvm_sust_p_3d_i16_trap, nvvm_sust_p_3d_i32_trap,   nvvm_sust_p_3d_i8_trap, nvvm_sust_p_3d_v2i16_trap, nvvm_sust_p_3d_v2i32_trap, nvvm_sust_p_3d_v2i8_trap,   nvvm_sust_p_3d_v4i16_trap, nvvm_sust_p_3d_v4i32_trap, nvvm_sust_p_3d_v4i8_trap, nvvm_swap_lo_hi_b64,   nvvm_tex_1d_array_grad_v4f32_f32, nvvm_tex_1d_array_grad_v4s32_f32, nvvm_tex_1d_array_grad_v4u32_f32, nvvm_tex_1d_array_level_v4f32_f32,   nvvm_tex_1d_array_level_v4s32_f32, nvvm_tex_1d_array_level_v4u32_f32, nvvm_tex_1d_array_v4f32_f32, nvvm_tex_1d_array_v4f32_s32,   nvvm_tex_1d_array_v4s32_f32, nvvm_tex_1d_array_v4s32_s32, nvvm_tex_1d_array_v4u32_f32, nvvm_tex_1d_array_v4u32_s32,   nvvm_tex_1d_grad_v4f32_f32, nvvm_tex_1d_grad_v4s32_f32, nvvm_tex_1d_grad_v4u32_f32, nvvm_tex_1d_level_v4f32_f32,   nvvm_tex_1d_level_v4s32_f32, nvvm_tex_1d_level_v4u32_f32, nvvm_tex_1d_v4f32_f32, nvvm_tex_1d_v4f32_s32,   nvvm_tex_1d_v4s32_f32, nvvm_tex_1d_v4s32_s32, nvvm_tex_1d_v4u32_f32, nvvm_tex_1d_v4u32_s32,   nvvm_tex_2d_array_grad_v4f32_f32, nvvm_tex_2d_array_grad_v4s32_f32, nvvm_tex_2d_array_grad_v4u32_f32, nvvm_tex_2d_array_level_v4f32_f32,   nvvm_tex_2d_array_level_v4s32_f32, nvvm_tex_2d_array_level_v4u32_f32, nvvm_tex_2d_array_v4f32_f32, nvvm_tex_2d_array_v4f32_s32,   nvvm_tex_2d_array_v4s32_f32, nvvm_tex_2d_array_v4s32_s32, nvvm_tex_2d_array_v4u32_f32, nvvm_tex_2d_array_v4u32_s32,   nvvm_tex_2d_grad_v4f32_f32, nvvm_tex_2d_grad_v4s32_f32, nvvm_tex_2d_grad_v4u32_f32, nvvm_tex_2d_level_v4f32_f32,   nvvm_tex_2d_level_v4s32_f32, nvvm_tex_2d_level_v4u32_f32, nvvm_tex_2d_v4f32_f32, nvvm_tex_2d_v4f32_s32,   nvvm_tex_2d_v4s32_f32, nvvm_tex_2d_v4s32_s32, nvvm_tex_2d_v4u32_f32, nvvm_tex_2d_v4u32_s32,   nvvm_tex_3d_grad_v4f32_f32, nvvm_tex_3d_grad_v4s32_f32, nvvm_tex_3d_grad_v4u32_f32, nvvm_tex_3d_level_v4f32_f32,   nvvm_tex_3d_level_v4s32_f32, nvvm_tex_3d_level_v4u32_f32, nvvm_tex_3d_v4f32_f32, nvvm_tex_3d_v4f32_s32,   nvvm_tex_3d_v4s32_f32, nvvm_tex_3d_v4s32_s32, nvvm_tex_3d_v4u32_f32, nvvm_tex_3d_v4u32_s32,   nvvm_tex_cube_array_level_v4f32_f32, nvvm_tex_cube_array_level_v4s32_f32, nvvm_tex_cube_array_level_v4u32_f32, nvvm_tex_cube_array_v4f32_f32,   nvvm_tex_cube_array_v4s32_f32, nvvm_tex_cube_array_v4u32_f32, nvvm_tex_cube_level_v4f32_f32, nvvm_tex_cube_level_v4s32_f32,   nvvm_tex_cube_level_v4u32_f32, nvvm_tex_cube_v4f32_f32, nvvm_tex_cube_v4s32_f32, nvvm_tex_cube_v4u32_f32,   nvvm_tex_unified_1d_array_grad_v4f32_f32, nvvm_tex_unified_1d_array_grad_v4s32_f32, nvvm_tex_unified_1d_array_grad_v4u32_f32, nvvm_tex_unified_1d_array_level_v4f32_f32,   nvvm_tex_unified_1d_array_level_v4s32_f32, nvvm_tex_unified_1d_array_level_v4u32_f32, nvvm_tex_unified_1d_array_v4f32_f32, nvvm_tex_unified_1d_array_v4f32_s32,   nvvm_tex_unified_1d_array_v4s32_f32, nvvm_tex_unified_1d_array_v4s32_s32, nvvm_tex_unified_1d_array_v4u32_f32, nvvm_tex_unified_1d_array_v4u32_s32,   nvvm_tex_unified_1d_grad_v4f32_f32, nvvm_tex_unified_1d_grad_v4s32_f32, nvvm_tex_unified_1d_grad_v4u32_f32, nvvm_tex_unified_1d_level_v4f32_f32,   nvvm_tex_unified_1d_level_v4s32_f32, nvvm_tex_unified_1d_level_v4u32_f32, nvvm_tex_unified_1d_v4f32_f32, nvvm_tex_unified_1d_v4f32_s32,   nvvm_tex_unified_1d_v4s32_f32, nvvm_tex_unified_1d_v4s32_s32, nvvm_tex_unified_1d_v4u32_f32, nvvm_tex_unified_1d_v4u32_s32,   nvvm_tex_unified_2d_array_grad_v4f32_f32, nvvm_tex_unified_2d_array_grad_v4s32_f32, nvvm_tex_unified_2d_array_grad_v4u32_f32, nvvm_tex_unified_2d_array_level_v4f32_f32,   nvvm_tex_unified_2d_array_level_v4s32_f32, nvvm_tex_unified_2d_array_level_v4u32_f32, nvvm_tex_unified_2d_array_v4f32_f32, nvvm_tex_unified_2d_array_v4f32_s32,   nvvm_tex_unified_2d_array_v4s32_f32, nvvm_tex_unified_2d_array_v4s32_s32, nvvm_tex_unified_2d_array_v4u32_f32, nvvm_tex_unified_2d_array_v4u32_s32,   nvvm_tex_unified_2d_grad_v4f32_f32, nvvm_tex_unified_2d_grad_v4s32_f32, nvvm_tex_unified_2d_grad_v4u32_f32, nvvm_tex_unified_2d_level_v4f32_f32,   nvvm_tex_unified_2d_level_v4s32_f32, nvvm_tex_unified_2d_level_v4u32_f32, nvvm_tex_unified_2d_v4f32_f32, nvvm_tex_unified_2d_v4f32_s32,   nvvm_tex_unified_2d_v4s32_f32, nvvm_tex_unified_2d_v4s32_s32, nvvm_tex_unified_2d_v4u32_f32, nvvm_tex_unified_2d_v4u32_s32,   nvvm_tex_unified_3d_grad_v4f32_f32, nvvm_tex_unified_3d_grad_v4s32_f32, nvvm_tex_unified_3d_grad_v4u32_f32, nvvm_tex_unified_3d_level_v4f32_f32,   nvvm_tex_unified_3d_level_v4s32_f32, nvvm_tex_unified_3d_level_v4u32_f32, nvvm_tex_unified_3d_v4f32_f32, nvvm_tex_unified_3d_v4f32_s32,   nvvm_tex_unified_3d_v4s32_f32, nvvm_tex_unified_3d_v4s32_s32, nvvm_tex_unified_3d_v4u32_f32, nvvm_tex_unified_3d_v4u32_s32,   nvvm_tex_unified_cube_array_level_v4f32_f32, nvvm_tex_unified_cube_array_level_v4s32_f32, nvvm_tex_unified_cube_array_level_v4u32_f32, nvvm_tex_unified_cube_array_v4f32_f32,   nvvm_tex_unified_cube_array_v4s32_f32, nvvm_tex_unified_cube_array_v4u32_f32, nvvm_tex_unified_cube_level_v4f32_f32, nvvm_tex_unified_cube_level_v4s32_f32,   nvvm_tex_unified_cube_level_v4u32_f32, nvvm_tex_unified_cube_v4f32_f32, nvvm_tex_unified_cube_v4s32_f32, nvvm_tex_unified_cube_v4u32_f32,   nvvm_texsurf_handle, nvvm_texsurf_handle_internal, nvvm_tld4_a_2d_v4f32_f32, nvvm_tld4_a_2d_v4s32_f32,   nvvm_tld4_a_2d_v4u32_f32, nvvm_tld4_b_2d_v4f32_f32, nvvm_tld4_b_2d_v4s32_f32, nvvm_tld4_b_2d_v4u32_f32,   nvvm_tld4_g_2d_v4f32_f32, nvvm_tld4_g_2d_v4s32_f32, nvvm_tld4_g_2d_v4u32_f32, nvvm_tld4_r_2d_v4f32_f32,   nvvm_tld4_r_2d_v4s32_f32, nvvm_tld4_r_2d_v4u32_f32, nvvm_tld4_unified_a_2d_v4f32_f32, nvvm_tld4_unified_a_2d_v4s32_f32,   nvvm_tld4_unified_a_2d_v4u32_f32, nvvm_tld4_unified_b_2d_v4f32_f32, nvvm_tld4_unified_b_2d_v4s32_f32, nvvm_tld4_unified_b_2d_v4u32_f32,   nvvm_tld4_unified_g_2d_v4f32_f32, nvvm_tld4_unified_g_2d_v4s32_f32, nvvm_tld4_unified_g_2d_v4u32_f32, nvvm_tld4_unified_r_2d_v4f32_f32,   nvvm_tld4_unified_r_2d_v4s32_f32, nvvm_tld4_unified_r_2d_v4u32_f32, nvvm_trunc_d, nvvm_trunc_f,   nvvm_trunc_ftz_f, nvvm_txq_array_size, nvvm_txq_channel_data_type, nvvm_txq_channel_order,   nvvm_txq_depth, nvvm_txq_height, nvvm_txq_num_mipmap_levels, nvvm_txq_num_samples,   nvvm_txq_width, nvvm_ui2d_rm, nvvm_ui2d_rn, nvvm_ui2d_rp,   nvvm_ui2d_rz, nvvm_ui2f_rm, nvvm_ui2f_rn, nvvm_ui2f_rp,   nvvm_ui2f_rz, nvvm_ull2d_rm, nvvm_ull2d_rn, nvvm_ull2d_rp,   nvvm_ull2d_rz, nvvm_ull2f_rm, nvvm_ull2f_rn, nvvm_ull2f_rp,   nvvm_ull2f_rz, nvvm_vote_all, nvvm_vote_all_sync, nvvm_vote_any,   nvvm_vote_any_sync, nvvm_vote_ballot, nvvm_vote_ballot_sync, nvvm_vote_uni,   nvvm_vote_uni_sync, nvvm_wmma_m16n16k16_load_a_f16_col, nvvm_wmma_m16n16k16_load_a_f16_col_stride, nvvm_wmma_m16n16k16_load_a_f16_row,   nvvm_wmma_m16n16k16_load_a_f16_row_stride, nvvm_wmma_m16n16k16_load_b_f16_col, nvvm_wmma_m16n16k16_load_b_f16_col_stride, nvvm_wmma_m16n16k16_load_b_f16_row,   nvvm_wmma_m16n16k16_load_b_f16_row_stride, nvvm_wmma_m16n16k16_load_c_f16_col, nvvm_wmma_m16n16k16_load_c_f32_col, nvvm_wmma_m16n16k16_load_c_f16_col_stride,   nvvm_wmma_m16n16k16_load_c_f32_col_stride, nvvm_wmma_m16n16k16_load_c_f16_row, nvvm_wmma_m16n16k16_load_c_f32_row, nvvm_wmma_m16n16k16_load_c_f16_row_stride,   nvvm_wmma_m16n16k16_load_c_f32_row_stride, nvvm_wmma_m16n16k16_mma_col_col_f16_f16, nvvm_wmma_m16n16k16_mma_col_col_f16_f16_satfinite, nvvm_wmma_m16n16k16_mma_col_col_f16_f32,   nvvm_wmma_m16n16k16_mma_col_col_f16_f32_satfinite, nvvm_wmma_m16n16k16_mma_col_col_f32_f16, nvvm_wmma_m16n16k16_mma_col_col_f32_f16_satfinite, nvvm_wmma_m16n16k16_mma_col_col_f32_f32,   nvvm_wmma_m16n16k16_mma_col_col_f32_f32_satfinite, nvvm_wmma_m16n16k16_mma_col_row_f16_f16, nvvm_wmma_m16n16k16_mma_col_row_f16_f16_satfinite, nvvm_wmma_m16n16k16_mma_col_row_f16_f32,   nvvm_wmma_m16n16k16_mma_col_row_f16_f32_satfinite, nvvm_wmma_m16n16k16_mma_col_row_f32_f16, nvvm_wmma_m16n16k16_mma_col_row_f32_f16_satfinite, nvvm_wmma_m16n16k16_mma_col_row_f32_f32,   nvvm_wmma_m16n16k16_mma_col_row_f32_f32_satfinite, nvvm_wmma_m16n16k16_mma_row_col_f16_f16, nvvm_wmma_m16n16k16_mma_row_col_f16_f16_satfinite, nvvm_wmma_m16n16k16_mma_row_col_f16_f32,   nvvm_wmma_m16n16k16_mma_row_col_f16_f32_satfinite, nvvm_wmma_m16n16k16_mma_row_col_f32_f16, nvvm_wmma_m16n16k16_mma_row_col_f32_f16_satfinite, nvvm_wmma_m16n16k16_mma_row_col_f32_f32,   nvvm_wmma_m16n16k16_mma_row_col_f32_f32_satfinite, nvvm_wmma_m16n16k16_mma_row_row_f16_f16, nvvm_wmma_m16n16k16_mma_row_row_f16_f16_satfinite, nvvm_wmma_m16n16k16_mma_row_row_f16_f32,   nvvm_wmma_m16n16k16_mma_row_row_f16_f32_satfinite, nvvm_wmma_m16n16k16_mma_row_row_f32_f16, nvvm_wmma_m16n16k16_mma_row_row_f32_f16_satfinite, nvvm_wmma_m16n16k16_mma_row_row_f32_f32,   nvvm_wmma_m16n16k16_mma_row_row_f32_f32_satfinite, nvvm_wmma_m16n16k16_store_d_f16_col, nvvm_wmma_m16n16k16_store_d_f32_col, nvvm_wmma_m16n16k16_store_d_f16_col_stride,   nvvm_wmma_m16n16k16_store_d_f32_col_stride, nvvm_wmma_m16n16k16_store_d_f16_row, nvvm_wmma_m16n16k16_store_d_f32_row, nvvm_wmma_m16n16k16_store_d_f16_row_stride,   nvvm_wmma_m16n16k16_store_d_f32_row_stride, nvvm_wmma_m32n8k16_load_a_f16_col, nvvm_wmma_m32n8k16_load_a_f16_col_stride, nvvm_wmma_m32n8k16_load_a_f16_row,   nvvm_wmma_m32n8k16_load_a_f16_row_stride, nvvm_wmma_m32n8k16_load_b_f16_col, nvvm_wmma_m32n8k16_load_b_f16_col_stride, nvvm_wmma_m32n8k16_load_b_f16_row,   nvvm_wmma_m32n8k16_load_b_f16_row_stride, nvvm_wmma_m32n8k16_load_c_f16_col, nvvm_wmma_m32n8k16_load_c_f32_col, nvvm_wmma_m32n8k16_load_c_f16_col_stride,   nvvm_wmma_m32n8k16_load_c_f32_col_stride, nvvm_wmma_m32n8k16_load_c_f16_row, nvvm_wmma_m32n8k16_load_c_f32_row, nvvm_wmma_m32n8k16_load_c_f16_row_stride,   nvvm_wmma_m32n8k16_load_c_f32_row_stride, nvvm_wmma_m32n8k16_mma_col_col_f16_f16, nvvm_wmma_m32n8k16_mma_col_col_f16_f16_satfinite, nvvm_wmma_m32n8k16_mma_col_col_f16_f32,   nvvm_wmma_m32n8k16_mma_col_col_f16_f32_satfinite, nvvm_wmma_m32n8k16_mma_col_col_f32_f16, nvvm_wmma_m32n8k16_mma_col_col_f32_f16_satfinite, nvvm_wmma_m32n8k16_mma_col_col_f32_f32,   nvvm_wmma_m32n8k16_mma_col_col_f32_f32_satfinite, nvvm_wmma_m32n8k16_mma_col_row_f16_f16, nvvm_wmma_m32n8k16_mma_col_row_f16_f16_satfinite, nvvm_wmma_m32n8k16_mma_col_row_f16_f32,   nvvm_wmma_m32n8k16_mma_col_row_f16_f32_satfinite, nvvm_wmma_m32n8k16_mma_col_row_f32_f16, nvvm_wmma_m32n8k16_mma_col_row_f32_f16_satfinite, nvvm_wmma_m32n8k16_mma_col_row_f32_f32,   nvvm_wmma_m32n8k16_mma_col_row_f32_f32_satfinite, nvvm_wmma_m32n8k16_mma_row_col_f16_f16, nvvm_wmma_m32n8k16_mma_row_col_f16_f16_satfinite, nvvm_wmma_m32n8k16_mma_row_col_f16_f32,   nvvm_wmma_m32n8k16_mma_row_col_f16_f32_satfinite, nvvm_wmma_m32n8k16_mma_row_col_f32_f16, nvvm_wmma_m32n8k16_mma_row_col_f32_f16_satfinite, nvvm_wmma_m32n8k16_mma_row_col_f32_f32,   nvvm_wmma_m32n8k16_mma_row_col_f32_f32_satfinite, nvvm_wmma_m32n8k16_mma_row_row_f16_f16, nvvm_wmma_m32n8k16_mma_row_row_f16_f16_satfinite, nvvm_wmma_m32n8k16_mma_row_row_f16_f32,   nvvm_wmma_m32n8k16_mma_row_row_f16_f32_satfinite, nvvm_wmma_m32n8k16_mma_row_row_f32_f16, nvvm_wmma_m32n8k16_mma_row_row_f32_f16_satfinite, nvvm_wmma_m32n8k16_mma_row_row_f32_f32,   nvvm_wmma_m32n8k16_mma_row_row_f32_f32_satfinite, nvvm_wmma_m32n8k16_store_d_f16_col, nvvm_wmma_m32n8k16_store_d_f32_col, nvvm_wmma_m32n8k16_store_d_f16_col_stride,   nvvm_wmma_m32n8k16_store_d_f32_col_stride, nvvm_wmma_m32n8k16_store_d_f16_row, nvvm_wmma_m32n8k16_store_d_f32_row, nvvm_wmma_m32n8k16_store_d_f16_row_stride,   nvvm_wmma_m32n8k16_store_d_f32_row_stride, nvvm_wmma_m8n32k16_load_a_f16_col, nvvm_wmma_m8n32k16_load_a_f16_col_stride, nvvm_wmma_m8n32k16_load_a_f16_row,   nvvm_wmma_m8n32k16_load_a_f16_row_stride, nvvm_wmma_m8n32k16_load_b_f16_col, nvvm_wmma_m8n32k16_load_b_f16_col_stride, nvvm_wmma_m8n32k16_load_b_f16_row,   nvvm_wmma_m8n32k16_load_b_f16_row_stride, nvvm_wmma_m8n32k16_load_c_f16_col, nvvm_wmma_m8n32k16_load_c_f32_col, nvvm_wmma_m8n32k16_load_c_f16_col_stride,   nvvm_wmma_m8n32k16_load_c_f32_col_stride, nvvm_wmma_m8n32k16_load_c_f16_row, nvvm_wmma_m8n32k16_load_c_f32_row, nvvm_wmma_m8n32k16_load_c_f16_row_stride,   nvvm_wmma_m8n32k16_load_c_f32_row_stride, nvvm_wmma_m8n32k16_mma_col_col_f16_f16, nvvm_wmma_m8n32k16_mma_col_col_f16_f16_satfinite, nvvm_wmma_m8n32k16_mma_col_col_f16_f32,   nvvm_wmma_m8n32k16_mma_col_col_f16_f32_satfinite, nvvm_wmma_m8n32k16_mma_col_col_f32_f16, nvvm_wmma_m8n32k16_mma_col_col_f32_f16_satfinite, nvvm_wmma_m8n32k16_mma_col_col_f32_f32,   nvvm_wmma_m8n32k16_mma_col_col_f32_f32_satfinite, nvvm_wmma_m8n32k16_mma_col_row_f16_f16, nvvm_wmma_m8n32k16_mma_col_row_f16_f16_satfinite, nvvm_wmma_m8n32k16_mma_col_row_f16_f32,   nvvm_wmma_m8n32k16_mma_col_row_f16_f32_satfinite, nvvm_wmma_m8n32k16_mma_col_row_f32_f16, nvvm_wmma_m8n32k16_mma_col_row_f32_f16_satfinite, nvvm_wmma_m8n32k16_mma_col_row_f32_f32,   nvvm_wmma_m8n32k16_mma_col_row_f32_f32_satfinite, nvvm_wmma_m8n32k16_mma_row_col_f16_f16, nvvm_wmma_m8n32k16_mma_row_col_f16_f16_satfinite, nvvm_wmma_m8n32k16_mma_row_col_f16_f32,   nvvm_wmma_m8n32k16_mma_row_col_f16_f32_satfinite, nvvm_wmma_m8n32k16_mma_row_col_f32_f16, nvvm_wmma_m8n32k16_mma_row_col_f32_f16_satfinite, nvvm_wmma_m8n32k16_mma_row_col_f32_f32,   nvvm_wmma_m8n32k16_mma_row_col_f32_f32_satfinite, nvvm_wmma_m8n32k16_mma_row_row_f16_f16, nvvm_wmma_m8n32k16_mma_row_row_f16_f16_satfinite, nvvm_wmma_m8n32k16_mma_row_row_f16_f32,   nvvm_wmma_m8n32k16_mma_row_row_f16_f32_satfinite, nvvm_wmma_m8n32k16_mma_row_row_f32_f16, nvvm_wmma_m8n32k16_mma_row_row_f32_f16_satfinite, nvvm_wmma_m8n32k16_mma_row_row_f32_f32,   nvvm_wmma_m8n32k16_mma_row_row_f32_f32_satfinite, nvvm_wmma_m8n32k16_store_d_f16_col, nvvm_wmma_m8n32k16_store_d_f32_col, nvvm_wmma_m8n32k16_store_d_f16_col_stride,   nvvm_wmma_m8n32k16_store_d_f32_col_stride, nvvm_wmma_m8n32k16_store_d_f16_row, nvvm_wmma_m8n32k16_store_d_f32_row, nvvm_wmma_m8n32k16_store_d_f16_row_stride,   nvvm_wmma_m8n32k16_store_d_f32_row_stride, ppc_addf128_round_to_odd, ppc_altivec_crypto_vcipher, ppc_altivec_crypto_vcipherlast,   ppc_altivec_crypto_vncipher, ppc_altivec_crypto_vncipherlast, ppc_altivec_crypto_vpermxor, ppc_altivec_crypto_vpmsumb,   ppc_altivec_crypto_vpmsumd, ppc_altivec_crypto_vpmsumh, ppc_altivec_crypto_vpmsumw, ppc_altivec_crypto_vsbox,   ppc_altivec_crypto_vshasigmad, ppc_altivec_crypto_vshasigmaw, ppc_altivec_dss, ppc_altivec_dssall,   ppc_altivec_dst, ppc_altivec_dstst, ppc_altivec_dststt, ppc_altivec_dstt,   ppc_altivec_lvebx, ppc_altivec_lvehx, ppc_altivec_lvewx, ppc_altivec_lvsl,   ppc_altivec_lvsr, ppc_altivec_lvx, ppc_altivec_lvxl, ppc_altivec_mfvscr,   ppc_altivec_mtvscr, ppc_altivec_stvebx, ppc_altivec_stvehx, ppc_altivec_stvewx,   ppc_altivec_stvx, ppc_altivec_stvxl, ppc_altivec_vabsdub, ppc_altivec_vabsduh,   ppc_altivec_vabsduw, ppc_altivec_vaddcuq, ppc_altivec_vaddcuw, ppc_altivec_vaddecuq,   ppc_altivec_vaddeuqm, ppc_altivec_vaddsbs, ppc_altivec_vaddshs, ppc_altivec_vaddsws,   ppc_altivec_vaddubs, ppc_altivec_vadduhs, ppc_altivec_vadduws, ppc_altivec_vavgsb,   ppc_altivec_vavgsh, ppc_altivec_vavgsw, ppc_altivec_vavgub, ppc_altivec_vavguh,   ppc_altivec_vavguw, ppc_altivec_vbpermq, ppc_altivec_vcfsx, ppc_altivec_vcfux,   ppc_altivec_vclzlsbb, ppc_altivec_vcmpbfp, ppc_altivec_vcmpbfp_p, ppc_altivec_vcmpeqfp,   ppc_altivec_vcmpeqfp_p, ppc_altivec_vcmpequb, ppc_altivec_vcmpequb_p, ppc_altivec_vcmpequd,   ppc_altivec_vcmpequd_p, ppc_altivec_vcmpequh, ppc_altivec_vcmpequh_p, ppc_altivec_vcmpequw,   ppc_altivec_vcmpequw_p, ppc_altivec_vcmpgefp, ppc_altivec_vcmpgefp_p, ppc_altivec_vcmpgtfp,   ppc_altivec_vcmpgtfp_p, ppc_altivec_vcmpgtsb, ppc_altivec_vcmpgtsb_p, ppc_altivec_vcmpgtsd,   ppc_altivec_vcmpgtsd_p, ppc_altivec_vcmpgtsh, ppc_altivec_vcmpgtsh_p, ppc_altivec_vcmpgtsw,   ppc_altivec_vcmpgtsw_p, ppc_altivec_vcmpgtub, ppc_altivec_vcmpgtub_p, ppc_altivec_vcmpgtud,   ppc_altivec_vcmpgtud_p, ppc_altivec_vcmpgtuh, ppc_altivec_vcmpgtuh_p, ppc_altivec_vcmpgtuw,   ppc_altivec_vcmpgtuw_p, ppc_altivec_vcmpneb, ppc_altivec_vcmpneb_p, ppc_altivec_vcmpneh,   ppc_altivec_vcmpneh_p, ppc_altivec_vcmpnew, ppc_altivec_vcmpnew_p, ppc_altivec_vcmpnezb,   ppc_altivec_vcmpnezb_p, ppc_altivec_vcmpnezh, ppc_altivec_vcmpnezh_p, ppc_altivec_vcmpnezw,   ppc_altivec_vcmpnezw_p, ppc_altivec_vctsxs, ppc_altivec_vctuxs, ppc_altivec_vctzlsbb,   ppc_altivec_vexptefp, ppc_altivec_vgbbd, ppc_altivec_vlogefp, ppc_altivec_vmaddfp,   ppc_altivec_vmaxfp, ppc_altivec_vmaxsb, ppc_altivec_vmaxsd, ppc_altivec_vmaxsh,   ppc_altivec_vmaxsw, ppc_altivec_vmaxub, ppc_altivec_vmaxud, ppc_altivec_vmaxuh,   ppc_altivec_vmaxuw, ppc_altivec_vmhaddshs, ppc_altivec_vmhraddshs, ppc_altivec_vminfp,   ppc_altivec_vminsb, ppc_altivec_vminsd, ppc_altivec_vminsh, ppc_altivec_vminsw,   ppc_altivec_vminub, ppc_altivec_vminud, ppc_altivec_vminuh, ppc_altivec_vminuw,   ppc_altivec_vmladduhm, ppc_altivec_vmsummbm, ppc_altivec_vmsumshm, ppc_altivec_vmsumshs,   ppc_altivec_vmsumubm, ppc_altivec_vmsumuhm, ppc_altivec_vmsumuhs, ppc_altivec_vmulesb,   ppc_altivec_vmulesh, ppc_altivec_vmulesw, ppc_altivec_vmuleub, ppc_altivec_vmuleuh,   ppc_altivec_vmuleuw, ppc_altivec_vmulosb, ppc_altivec_vmulosh, ppc_altivec_vmulosw,   ppc_altivec_vmuloub, ppc_altivec_vmulouh, ppc_altivec_vmulouw, ppc_altivec_vnmsubfp,   ppc_altivec_vperm, ppc_altivec_vpkpx, ppc_altivec_vpksdss, ppc_altivec_vpksdus,   ppc_altivec_vpkshss, ppc_altivec_vpkshus, ppc_altivec_vpkswss, ppc_altivec_vpkswus,   ppc_altivec_vpkudus, ppc_altivec_vpkuhus, ppc_altivec_vpkuwus, ppc_altivec_vprtybd,   ppc_altivec_vprtybq, ppc_altivec_vprtybw, ppc_altivec_vrefp, ppc_altivec_vrfim,   ppc_altivec_vrfin, ppc_altivec_vrfip, ppc_altivec_vrfiz, ppc_altivec_vrlb,   ppc_altivec_vrld, ppc_altivec_vrldmi, ppc_altivec_vrldnm, ppc_altivec_vrlh,   ppc_altivec_vrlw, ppc_altivec_vrlwmi, ppc_altivec_vrlwnm, ppc_altivec_vrsqrtefp,   ppc_altivec_vsel, ppc_altivec_vsl, ppc_altivec_vslb, ppc_altivec_vslh,   ppc_altivec_vslo, ppc_altivec_vslv, ppc_altivec_vslw, ppc_altivec_vsr,   ppc_altivec_vsrab, ppc_altivec_vsrah, ppc_altivec_vsraw, ppc_altivec_vsrb,   ppc_altivec_vsrh, ppc_altivec_vsro, ppc_altivec_vsrv, ppc_altivec_vsrw,   ppc_altivec_vsubcuq, ppc_altivec_vsubcuw, ppc_altivec_vsubecuq, ppc_altivec_vsubeuqm,   ppc_altivec_vsubsbs, ppc_altivec_vsubshs, ppc_altivec_vsubsws, ppc_altivec_vsububs,   ppc_altivec_vsubuhs, ppc_altivec_vsubuws, ppc_altivec_vsum2sws, ppc_altivec_vsum4sbs,   ppc_altivec_vsum4shs, ppc_altivec_vsum4ubs, ppc_altivec_vsumsws, ppc_altivec_vupkhpx,   ppc_altivec_vupkhsb, ppc_altivec_vupkhsh, ppc_altivec_vupkhsw, ppc_altivec_vupklpx,   ppc_altivec_vupklsb, ppc_altivec_vupklsh, ppc_altivec_vupklsw, ppc_bpermd,   ppc_cfence, ppc_dcba, ppc_dcbf, ppc_dcbi,   ppc_dcbst, ppc_dcbt, ppc_dcbtst, ppc_dcbz,   ppc_dcbzl, ppc_divde, ppc_divdeu, ppc_divf128_round_to_odd,   ppc_divwe, ppc_divweu, ppc_fmaf128_round_to_odd, ppc_get_texasr,   ppc_get_texasru, ppc_get_tfhar, ppc_get_tfiar, ppc_is_decremented_ctr_nonzero,   ppc_lwsync, ppc_mtctr, ppc_mulf128_round_to_odd, ppc_qpx_qvfabs,   ppc_qpx_qvfadd, ppc_qpx_qvfadds, ppc_qpx_qvfcfid, ppc_qpx_qvfcfids,   ppc_qpx_qvfcfidu, ppc_qpx_qvfcfidus, ppc_qpx_qvfcmpeq, ppc_qpx_qvfcmpgt,   ppc_qpx_qvfcmplt, ppc_qpx_qvfcpsgn, ppc_qpx_qvfctid, ppc_qpx_qvfctidu,   ppc_qpx_qvfctiduz, ppc_qpx_qvfctidz, ppc_qpx_qvfctiw, ppc_qpx_qvfctiwu,   ppc_qpx_qvfctiwuz, ppc_qpx_qvfctiwz, ppc_qpx_qvflogical, ppc_qpx_qvfmadd,   ppc_qpx_qvfmadds, ppc_qpx_qvfmsub, ppc_qpx_qvfmsubs, ppc_qpx_qvfmul,   ppc_qpx_qvfmuls, ppc_qpx_qvfnabs, ppc_qpx_qvfneg, ppc_qpx_qvfnmadd,   ppc_qpx_qvfnmadds, ppc_qpx_qvfnmsub, ppc_qpx_qvfnmsubs, ppc_qpx_qvfperm,   ppc_qpx_qvfre, ppc_qpx_qvfres, ppc_qpx_qvfrim, ppc_qpx_qvfrin,   ppc_qpx_qvfrip, ppc_qpx_qvfriz, ppc_qpx_qvfrsp, ppc_qpx_qvfrsqrte,   ppc_qpx_qvfrsqrtes, ppc_qpx_qvfsel, ppc_qpx_qvfsub, ppc_qpx_qvfsubs,   ppc_qpx_qvftstnan, ppc_qpx_qvfxmadd, ppc_qpx_qvfxmadds, ppc_qpx_qvfxmul,   ppc_qpx_qvfxmuls, ppc_qpx_qvfxxcpnmadd, ppc_qpx_qvfxxcpnmadds, ppc_qpx_qvfxxmadd,   ppc_qpx_qvfxxmadds, ppc_qpx_qvfxxnpmadd, ppc_qpx_qvfxxnpmadds, ppc_qpx_qvgpci,   ppc_qpx_qvlfcd, ppc_qpx_qvlfcda, ppc_qpx_qvlfcs, ppc_qpx_qvlfcsa,   ppc_qpx_qvlfd, ppc_qpx_qvlfda, ppc_qpx_qvlfiwa, ppc_qpx_qvlfiwaa,   ppc_qpx_qvlfiwz, ppc_qpx_qvlfiwza, ppc_qpx_qvlfs, ppc_qpx_qvlfsa,   ppc_qpx_qvlpcld, ppc_qpx_qvlpcls, ppc_qpx_qvlpcrd, ppc_qpx_qvlpcrs,   ppc_qpx_qvstfcd, ppc_qpx_qvstfcda, ppc_qpx_qvstfcs, ppc_qpx_qvstfcsa,   ppc_qpx_qvstfd, ppc_qpx_qvstfda, ppc_qpx_qvstfiw, ppc_qpx_qvstfiwa,   ppc_qpx_qvstfs, ppc_qpx_qvstfsa, ppc_scalar_extract_expq, ppc_scalar_insert_exp_qp,   ppc_set_texasr, ppc_set_texasru, ppc_set_tfhar, ppc_set_tfiar,   ppc_sqrtf128_round_to_odd, ppc_subf128_round_to_odd, ppc_sync, ppc_tabort,   ppc_tabortdc, ppc_tabortdci, ppc_tabortwc, ppc_tabortwci,   ppc_tbegin, ppc_tcheck, ppc_tend, ppc_tendall,   ppc_trechkpt, ppc_treclaim, ppc_tresume, ppc_truncf128_round_to_odd,   ppc_tsr, ppc_tsuspend, ppc_ttest, ppc_vsx_lxvd2x,   ppc_vsx_lxvd2x_be, ppc_vsx_lxvl, ppc_vsx_lxvll, ppc_vsx_lxvw4x,   ppc_vsx_lxvw4x_be, ppc_vsx_stxvd2x, ppc_vsx_stxvd2x_be, ppc_vsx_stxvl,   ppc_vsx_stxvll, ppc_vsx_stxvw4x, ppc_vsx_stxvw4x_be, ppc_vsx_xsmaxdp,   ppc_vsx_xsmindp, ppc_vsx_xvcmpeqdp, ppc_vsx_xvcmpeqdp_p, ppc_vsx_xvcmpeqsp,   ppc_vsx_xvcmpeqsp_p, ppc_vsx_xvcmpgedp, ppc_vsx_xvcmpgedp_p, ppc_vsx_xvcmpgesp,   ppc_vsx_xvcmpgesp_p, ppc_vsx_xvcmpgtdp, ppc_vsx_xvcmpgtdp_p, ppc_vsx_xvcmpgtsp,   ppc_vsx_xvcmpgtsp_p, ppc_vsx_xvcvdpsp, ppc_vsx_xvcvdpsxws, ppc_vsx_xvcvdpuxws,   ppc_vsx_xvcvhpsp, ppc_vsx_xvcvspdp, ppc_vsx_xvcvsphp, ppc_vsx_xvcvsxdsp,   ppc_vsx_xvcvsxwdp, ppc_vsx_xvcvuxdsp, ppc_vsx_xvcvuxwdp, ppc_vsx_xvdivdp,   ppc_vsx_xvdivsp, ppc_vsx_xviexpdp, ppc_vsx_xviexpsp, ppc_vsx_xvmaxdp,   ppc_vsx_xvmaxsp, ppc_vsx_xvmindp, ppc_vsx_xvminsp, ppc_vsx_xvrdpip,   ppc_vsx_xvredp, ppc_vsx_xvresp, ppc_vsx_xvrspip, ppc_vsx_xvrsqrtedp,   ppc_vsx_xvrsqrtesp, ppc_vsx_xvtstdcdp, ppc_vsx_xvtstdcsp, ppc_vsx_xvxexpdp,   ppc_vsx_xvxexpsp, ppc_vsx_xvxsigdp, ppc_vsx_xvxsigsp, ppc_vsx_xxextractuw,   ppc_vsx_xxinsertw, ppc_vsx_xxleqv, r600_cube, r600_ddx,   r600_ddy, r600_dot4, r600_group_barrier, r600_implicitarg_ptr,   r600_kill, r600_rat_store_typed, r600_read_global_size_x, r600_read_global_size_y,   r600_read_global_size_z, r600_read_local_size_x, r600_read_local_size_y, r600_read_local_size_z,   r600_read_ngroups_x, r600_read_ngroups_y, r600_read_ngroups_z, r600_read_tgid_x,   r600_read_tgid_y, r600_read_tgid_z, r600_read_tidig_x, r600_read_tidig_y,   r600_read_tidig_z, r600_recipsqrt_clamped, r600_recipsqrt_ieee, r600_store_stream_output,   r600_store_swizzle, r600_tex, r600_texc, r600_txb,   r600_txbc, r600_txf, r600_txl, r600_txlc,   r600_txq, riscv_masked_atomicrmw_add_i32, riscv_masked_atomicrmw_max_i32, riscv_masked_atomicrmw_min_i32,   riscv_masked_atomicrmw_nand_i32, riscv_masked_atomicrmw_sub_i32, riscv_masked_atomicrmw_umax_i32, riscv_masked_atomicrmw_umin_i32,   riscv_masked_atomicrmw_xchg_i32, riscv_masked_cmpxchg_i32, s390_efpc, s390_etnd,   s390_lcbb, s390_ntstg, s390_ppa_txassist, s390_sfpc,   s390_tabort, s390_tbegin, s390_tbegin_nofloat, s390_tbeginc,   s390_tdc, s390_tend, s390_vaccb, s390_vacccq,   s390_vaccf, s390_vaccg, s390_vacch, s390_vaccq,   s390_vacq, s390_vaq, s390_vavgb, s390_vavgf,   s390_vavgg, s390_vavgh, s390_vavglb, s390_vavglf,   s390_vavglg, s390_vavglh, s390_vbperm, s390_vceqbs,   s390_vceqfs, s390_vceqgs, s390_vceqhs, s390_vchbs,   s390_vchfs, s390_vchgs, s390_vchhs, s390_vchlbs,   s390_vchlfs, s390_vchlgs, s390_vchlhs, s390_vcksm,   s390_verimb, s390_verimf, s390_verimg, s390_verimh,   s390_verllb, s390_verllf, s390_verllg, s390_verllh,   s390_verllvb, s390_verllvf, s390_verllvg, s390_verllvh,   s390_vfaeb, s390_vfaebs, s390_vfaef, s390_vfaefs,   s390_vfaeh, s390_vfaehs, s390_vfaezb, s390_vfaezbs,   s390_vfaezf, s390_vfaezfs, s390_vfaezh, s390_vfaezhs,   s390_vfcedbs, s390_vfcesbs, s390_vfchdbs, s390_vfchedbs,   s390_vfchesbs, s390_vfchsbs, s390_vfeeb, s390_vfeebs,   s390_vfeef, s390_vfeefs, s390_vfeeh, s390_vfeehs,   s390_vfeezb, s390_vfeezbs, s390_vfeezf, s390_vfeezfs,   s390_vfeezh, s390_vfeezhs, s390_vfeneb, s390_vfenebs,   s390_vfenef, s390_vfenefs, s390_vfeneh, s390_vfenehs,   s390_vfenezb, s390_vfenezbs, s390_vfenezf, s390_vfenezfs,   s390_vfenezh, s390_vfenezhs, s390_vfidb, s390_vfisb,   s390_vfmaxdb, s390_vfmaxsb, s390_vfmindb, s390_vfminsb,   s390_vftcidb, s390_vftcisb, s390_vgfmab, s390_vgfmaf,   s390_vgfmag, s390_vgfmah, s390_vgfmb, s390_vgfmf,   s390_vgfmg, s390_vgfmh, s390_vistrb, s390_vistrbs,   s390_vistrf, s390_vistrfs, s390_vistrh, s390_vistrhs,   s390_vlbb, s390_vll, s390_vlrl, s390_vmaeb,   s390_vmaef, s390_vmaeh, s390_vmahb, s390_vmahf,   s390_vmahh, s390_vmaleb, s390_vmalef, s390_vmaleh,   s390_vmalhb, s390_vmalhf, s390_vmalhh, s390_vmalob,   s390_vmalof, s390_vmaloh, s390_vmaob, s390_vmaof,   s390_vmaoh, s390_vmeb, s390_vmef, s390_vmeh,   s390_vmhb, s390_vmhf, s390_vmhh, s390_vmleb,   s390_vmlef, s390_vmleh, s390_vmlhb, s390_vmlhf,   s390_vmlhh, s390_vmlob, s390_vmlof, s390_vmloh,   s390_vmob, s390_vmof, s390_vmoh, s390_vmslg,   s390_vpdi, s390_vperm, s390_vpklsf, s390_vpklsfs,   s390_vpklsg, s390_vpklsgs, s390_vpklsh, s390_vpklshs,   s390_vpksf, s390_vpksfs, s390_vpksg, s390_vpksgs,   s390_vpksh, s390_vpkshs, s390_vsbcbiq, s390_vsbiq,   s390_vscbib, s390_vscbif, s390_vscbig, s390_vscbih,   s390_vscbiq, s390_vsl, s390_vslb, s390_vsldb,   s390_vsq, s390_vsra, s390_vsrab, s390_vsrl,   s390_vsrlb, s390_vstl, s390_vstrcb, s390_vstrcbs,   s390_vstrcf, s390_vstrcfs, s390_vstrch, s390_vstrchs,   s390_vstrczb, s390_vstrczbs, s390_vstrczf, s390_vstrczfs,   s390_vstrczh, s390_vstrczhs, s390_vstrl, s390_vsumb,   s390_vsumgf, s390_vsumgh, s390_vsumh, s390_vsumqf,   s390_vsumqg, s390_vtm, s390_vuphb, s390_vuphf,   s390_vuphh, s390_vuplb, s390_vuplf, s390_vuplhb,   s390_vuplhf, s390_vuplhh, s390_vuplhw, s390_vupllb,   s390_vupllf, s390_vupllh, wasm_alltrue, wasm_anytrue,   wasm_atomic_notify, wasm_atomic_wait_i32, wasm_atomic_wait_i64, wasm_bitselect,   wasm_catch, wasm_get_ehselector, wasm_get_exception, wasm_landingpad_index,   wasm_lsda, wasm_memory_grow, wasm_memory_size, wasm_rethrow,   wasm_sub_saturate_signed, wasm_sub_saturate_unsigned, wasm_throw, wasm_trunc_saturate_signed,   wasm_trunc_saturate_unsigned, x86_3dnow_pavgusb, x86_3dnow_pf2id, x86_3dnow_pfacc,   x86_3dnow_pfadd, x86_3dnow_pfcmpeq, x86_3dnow_pfcmpge, x86_3dnow_pfcmpgt,   x86_3dnow_pfmax, x86_3dnow_pfmin, x86_3dnow_pfmul, x86_3dnow_pfrcp,   x86_3dnow_pfrcpit1, x86_3dnow_pfrcpit2, x86_3dnow_pfrsqit1, x86_3dnow_pfrsqrt,   x86_3dnow_pfsub, x86_3dnow_pfsubr, x86_3dnow_pi2fd, x86_3dnow_pmulhrw,   x86_3dnowa_pf2iw, x86_3dnowa_pfnacc, x86_3dnowa_pfpnacc, x86_3dnowa_pi2fw,   x86_3dnowa_pswapd, x86_addcarry_32, x86_addcarry_64, x86_aesni_aesdec,   x86_aesni_aesdec_256, x86_aesni_aesdec_512, x86_aesni_aesdeclast, x86_aesni_aesdeclast_256,   x86_aesni_aesdeclast_512, x86_aesni_aesenc, x86_aesni_aesenc_256, x86_aesni_aesenc_512,   x86_aesni_aesenclast, x86_aesni_aesenclast_256, x86_aesni_aesenclast_512, x86_aesni_aesimc,   x86_aesni_aeskeygenassist, x86_avx_addsub_pd_256, x86_avx_addsub_ps_256, x86_avx_blendv_pd_256,   x86_avx_blendv_ps_256, x86_avx_cmp_pd_256, x86_avx_cmp_ps_256, x86_avx_cvt_pd2_ps_256,   x86_avx_cvt_pd2dq_256, x86_avx_cvt_ps2dq_256, x86_avx_cvtt_pd2dq_256, x86_avx_cvtt_ps2dq_256,   x86_avx_dp_ps_256, x86_avx_hadd_pd_256, x86_avx_hadd_ps_256, x86_avx_hsub_pd_256,   x86_avx_hsub_ps_256, x86_avx_ldu_dq_256, x86_avx_maskload_pd, x86_avx_maskload_pd_256,   x86_avx_maskload_ps, x86_avx_maskload_ps_256, x86_avx_maskstore_pd, x86_avx_maskstore_pd_256,   x86_avx_maskstore_ps, x86_avx_maskstore_ps_256, x86_avx_max_pd_256, x86_avx_max_ps_256,   x86_avx_min_pd_256, x86_avx_min_ps_256, x86_avx_movmsk_pd_256, x86_avx_movmsk_ps_256,   x86_avx_ptestc_256, x86_avx_ptestnzc_256, x86_avx_ptestz_256, x86_avx_rcp_ps_256,   x86_avx_round_pd_256, x86_avx_round_ps_256, x86_avx_rsqrt_ps_256, x86_avx_vpermilvar_pd,   x86_avx_vpermilvar_pd_256, x86_avx_vpermilvar_ps, x86_avx_vpermilvar_ps_256, x86_avx_vtestc_pd,   x86_avx_vtestc_pd_256, x86_avx_vtestc_ps, x86_avx_vtestc_ps_256, x86_avx_vtestnzc_pd,   x86_avx_vtestnzc_pd_256, x86_avx_vtestnzc_ps, x86_avx_vtestnzc_ps_256, x86_avx_vtestz_pd,   x86_avx_vtestz_pd_256, x86_avx_vtestz_ps, x86_avx_vtestz_ps_256, x86_avx_vzeroall,   x86_avx_vzeroupper, x86_avx2_gather_d_d, x86_avx2_gather_d_d_256, x86_avx2_gather_d_pd,   x86_avx2_gather_d_pd_256, x86_avx2_gather_d_ps, x86_avx2_gather_d_ps_256, x86_avx2_gather_d_q,   x86_avx2_gather_d_q_256, x86_avx2_gather_q_d, x86_avx2_gather_q_d_256, x86_avx2_gather_q_pd,   x86_avx2_gather_q_pd_256, x86_avx2_gather_q_ps, x86_avx2_gather_q_ps_256, x86_avx2_gather_q_q,   x86_avx2_gather_q_q_256, x86_avx2_maskload_d, x86_avx2_maskload_d_256, x86_avx2_maskload_q,   x86_avx2_maskload_q_256, x86_avx2_maskstore_d, x86_avx2_maskstore_d_256, x86_avx2_maskstore_q,   x86_avx2_maskstore_q_256, x86_avx2_mpsadbw, x86_avx2_packssdw, x86_avx2_packsswb,   x86_avx2_packusdw, x86_avx2_packuswb, x86_avx2_pblendvb, x86_avx2_permd,   x86_avx2_permps, x86_avx2_phadd_d, x86_avx2_phadd_sw, x86_avx2_phadd_w,   x86_avx2_phsub_d, x86_avx2_phsub_sw, x86_avx2_phsub_w, x86_avx2_pmadd_ub_sw,   x86_avx2_pmadd_wd, x86_avx2_pmovmskb, x86_avx2_pmul_hr_sw, x86_avx2_pmulh_w,   x86_avx2_pmulhu_w, x86_avx2_psad_bw, x86_avx2_pshuf_b, x86_avx2_psign_b,   x86_avx2_psign_d, x86_avx2_psign_w, x86_avx2_psll_d, x86_avx2_psll_q,   x86_avx2_psll_w, x86_avx2_pslli_d, x86_avx2_pslli_q, x86_avx2_pslli_w,   x86_avx2_psllv_d, x86_avx2_psllv_d_256, x86_avx2_psllv_q, x86_avx2_psllv_q_256,   x86_avx2_psra_d, x86_avx2_psra_w, x86_avx2_psrai_d, x86_avx2_psrai_w,   x86_avx2_psrav_d, x86_avx2_psrav_d_256, x86_avx2_psrl_d, x86_avx2_psrl_q,   x86_avx2_psrl_w, x86_avx2_psrli_d, x86_avx2_psrli_q, x86_avx2_psrli_w,   x86_avx2_psrlv_d, x86_avx2_psrlv_d_256, x86_avx2_psrlv_q, x86_avx2_psrlv_q_256,   x86_avx512_add_pd_512, x86_avx512_add_ps_512, x86_avx512_broadcastmb_128, x86_avx512_broadcastmb_256,   x86_avx512_broadcastmb_512, x86_avx512_broadcastmw_128, x86_avx512_broadcastmw_256, x86_avx512_broadcastmw_512,   x86_avx512_cmp_pd_128, x86_avx512_cmp_pd_256, x86_avx512_cmp_pd_512, x86_avx512_cmp_ps_128,   x86_avx512_cmp_ps_256, x86_avx512_cmp_ps_512, x86_avx512_cvtsi2sd64, x86_avx512_cvtsi2ss32,   x86_avx512_cvtsi2ss64, x86_avx512_cvttsd2si, x86_avx512_cvttsd2si64, x86_avx512_cvttsd2usi,   x86_avx512_cvttsd2usi64, x86_avx512_cvttss2si, x86_avx512_cvttss2si64, x86_avx512_cvttss2usi,   x86_avx512_cvttss2usi64, x86_avx512_cvtusi2ss, x86_avx512_cvtusi642sd, x86_avx512_cvtusi642ss,   x86_avx512_dbpsadbw_128, x86_avx512_dbpsadbw_256, x86_avx512_dbpsadbw_512, x86_avx512_div_pd_512,   x86_avx512_div_ps_512, x86_avx512_exp2_pd, x86_avx512_exp2_ps, x86_avx512_fpclass_pd_128,   x86_avx512_fpclass_pd_256, x86_avx512_fpclass_pd_512, x86_avx512_fpclass_ps_128, x86_avx512_fpclass_ps_256,   x86_avx512_fpclass_ps_512, x86_avx512_gather_dpd_512, x86_avx512_gather_dpi_512, x86_avx512_gather_dpq_512,   x86_avx512_gather_dps_512, x86_avx512_gather_qpd_512, x86_avx512_gather_qpi_512, x86_avx512_gather_qpq_512,   x86_avx512_gather_qps_512, x86_avx512_gather3div2_df, x86_avx512_gather3div2_di, x86_avx512_gather3div4_df,   x86_avx512_gather3div4_di, x86_avx512_gather3div4_sf, x86_avx512_gather3div4_si, x86_avx512_gather3div8_sf,   x86_avx512_gather3div8_si, x86_avx512_gather3siv2_df, x86_avx512_gather3siv2_di, x86_avx512_gather3siv4_df,   x86_avx512_gather3siv4_di, x86_avx512_gather3siv4_sf, x86_avx512_gather3siv4_si, x86_avx512_gather3siv8_sf,   x86_avx512_gather3siv8_si, x86_avx512_gatherpf_dpd_512, x86_avx512_gatherpf_dps_512, x86_avx512_gatherpf_qpd_512,   x86_avx512_gatherpf_qps_512, x86_avx512_kadd_b, x86_avx512_kadd_d, x86_avx512_kadd_q,   x86_avx512_kadd_w, x86_avx512_ktestc_b, x86_avx512_ktestc_d, x86_avx512_ktestc_q,   x86_avx512_ktestc_w, x86_avx512_ktestz_b, x86_avx512_ktestz_d, x86_avx512_ktestz_q,   x86_avx512_ktestz_w, x86_avx512_mask_add_sd_round, x86_avx512_mask_add_ss_round, x86_avx512_mask_cmp_sd,   x86_avx512_mask_cmp_ss, x86_avx512_mask_compress_b_128, x86_avx512_mask_compress_b_256, x86_avx512_mask_compress_b_512,   x86_avx512_mask_compress_d_128, x86_avx512_mask_compress_d_256, x86_avx512_mask_compress_d_512, x86_avx512_mask_compress_pd_128,   x86_avx512_mask_compress_pd_256, x86_avx512_mask_compress_pd_512, x86_avx512_mask_compress_ps_128, x86_avx512_mask_compress_ps_256,   x86_avx512_mask_compress_ps_512, x86_avx512_mask_compress_q_128, x86_avx512_mask_compress_q_256, x86_avx512_mask_compress_q_512,   x86_avx512_mask_compress_w_128, x86_avx512_mask_compress_w_256, x86_avx512_mask_compress_w_512, x86_avx512_mask_conflict_d_128,   x86_avx512_mask_conflict_d_256, x86_avx512_mask_conflict_d_512, x86_avx512_mask_conflict_q_128, x86_avx512_mask_conflict_q_256,   x86_avx512_mask_conflict_q_512, x86_avx512_mask_cvtdq2ps_512, x86_avx512_mask_cvtpd2dq_128, x86_avx512_mask_cvtpd2dq_512,   x86_avx512_mask_cvtpd2ps, x86_avx512_mask_cvtpd2ps_512, x86_avx512_mask_cvtpd2qq_128, x86_avx512_mask_cvtpd2qq_256,   x86_avx512_mask_cvtpd2qq_512, x86_avx512_mask_cvtpd2udq_128, x86_avx512_mask_cvtpd2udq_256, x86_avx512_mask_cvtpd2udq_512,   x86_avx512_mask_cvtpd2uqq_128, x86_avx512_mask_cvtpd2uqq_256, x86_avx512_mask_cvtpd2uqq_512, x86_avx512_mask_cvtps2dq_128,   x86_avx512_mask_cvtps2dq_256, x86_avx512_mask_cvtps2dq_512, x86_avx512_mask_cvtps2pd_512, x86_avx512_mask_cvtps2qq_128,   x86_avx512_mask_cvtps2qq_256, x86_avx512_mask_cvtps2qq_512, x86_avx512_mask_cvtps2udq_128, x86_avx512_mask_cvtps2udq_256,   x86_avx512_mask_cvtps2udq_512, x86_avx512_mask_cvtps2uqq_128, x86_avx512_mask_cvtps2uqq_256, x86_avx512_mask_cvtps2uqq_512,   x86_avx512_mask_cvtqq2pd_512, x86_avx512_mask_cvtqq2ps_128, x86_avx512_mask_cvtqq2ps_256, x86_avx512_mask_cvtqq2ps_512,   x86_avx512_mask_cvtsd2ss_round, x86_avx512_mask_cvtss2sd_round, x86_avx512_mask_cvttpd2dq_128, x86_avx512_mask_cvttpd2dq_512,   x86_avx512_mask_cvttpd2qq_128, x86_avx512_mask_cvttpd2qq_256, x86_avx512_mask_cvttpd2qq_512, x86_avx512_mask_cvttpd2udq_128,   x86_avx512_mask_cvttpd2udq_256, x86_avx512_mask_cvttpd2udq_512, x86_avx512_mask_cvttpd2uqq_128, x86_avx512_mask_cvttpd2uqq_256,   x86_avx512_mask_cvttpd2uqq_512, x86_avx512_mask_cvttps2dq_512, x86_avx512_mask_cvttps2qq_128, x86_avx512_mask_cvttps2qq_256,   x86_avx512_mask_cvttps2qq_512, x86_avx512_mask_cvttps2udq_128, x86_avx512_mask_cvttps2udq_256, x86_avx512_mask_cvttps2udq_512,   x86_avx512_mask_cvttps2uqq_128, x86_avx512_mask_cvttps2uqq_256, x86_avx512_mask_cvttps2uqq_512, x86_avx512_mask_cvtudq2ps_512,   x86_avx512_mask_cvtuqq2pd_512, x86_avx512_mask_cvtuqq2ps_128, x86_avx512_mask_cvtuqq2ps_256, x86_avx512_mask_cvtuqq2ps_512,   x86_avx512_mask_div_sd_round, x86_avx512_mask_div_ss_round, x86_avx512_mask_expand_b_128, x86_avx512_mask_expand_b_256,   x86_avx512_mask_expand_b_512, x86_avx512_mask_expand_d_128, x86_avx512_mask_expand_d_256, x86_avx512_mask_expand_d_512,   x86_avx512_mask_expand_pd_128, x86_avx512_mask_expand_pd_256, x86_avx512_mask_expand_pd_512, x86_avx512_mask_expand_ps_128,   x86_avx512_mask_expand_ps_256, x86_avx512_mask_expand_ps_512, x86_avx512_mask_expand_q_128, x86_avx512_mask_expand_q_256,   x86_avx512_mask_expand_q_512, x86_avx512_mask_expand_w_128, x86_avx512_mask_expand_w_256, x86_avx512_mask_expand_w_512,   x86_avx512_mask_fixupimm_pd_128, x86_avx512_mask_fixupimm_pd_256, x86_avx512_mask_fixupimm_pd_512, x86_avx512_mask_fixupimm_ps_128,   x86_avx512_mask_fixupimm_ps_256, x86_avx512_mask_fixupimm_ps_512, x86_avx512_mask_fixupimm_sd, x86_avx512_mask_fixupimm_ss,   x86_avx512_mask_fpclass_sd, x86_avx512_mask_fpclass_ss, x86_avx512_mask_gather_dpd_512, x86_avx512_mask_gather_dpi_512,   x86_avx512_mask_gather_dpq_512, x86_avx512_mask_gather_dps_512, x86_avx512_mask_gather_qpd_512, x86_avx512_mask_gather_qpi_512,   x86_avx512_mask_gather_qpq_512, x86_avx512_mask_gather_qps_512, x86_avx512_mask_gather3div2_df, x86_avx512_mask_gather3div2_di,   x86_avx512_mask_gather3div4_df, x86_avx512_mask_gather3div4_di, x86_avx512_mask_gather3div4_sf, x86_avx512_mask_gather3div4_si,   x86_avx512_mask_gather3div8_sf, x86_avx512_mask_gather3div8_si, x86_avx512_mask_gather3siv2_df, x86_avx512_mask_gather3siv2_di,   x86_avx512_mask_gather3siv4_df, x86_avx512_mask_gather3siv4_di, x86_avx512_mask_gather3siv4_sf, x86_avx512_mask_gather3siv4_si,   x86_avx512_mask_gather3siv8_sf, x86_avx512_mask_gather3siv8_si, x86_avx512_mask_getexp_pd_128, x86_avx512_mask_getexp_pd_256,   x86_avx512_mask_getexp_pd_512, x86_avx512_mask_getexp_ps_128, x86_avx512_mask_getexp_ps_256, x86_avx512_mask_getexp_ps_512,   x86_avx512_mask_getexp_sd, x86_avx512_mask_getexp_ss, x86_avx512_mask_getmant_pd_128, x86_avx512_mask_getmant_pd_256,   x86_avx512_mask_getmant_pd_512, x86_avx512_mask_getmant_ps_128, x86_avx512_mask_getmant_ps_256, x86_avx512_mask_getmant_ps_512,   x86_avx512_mask_getmant_sd, x86_avx512_mask_getmant_ss, x86_avx512_mask_max_sd_round, x86_avx512_mask_max_ss_round,   x86_avx512_mask_min_sd_round, x86_avx512_mask_min_ss_round, x86_avx512_mask_mul_sd_round, x86_avx512_mask_mul_ss_round,   x86_avx512_mask_pmov_db_128, x86_avx512_mask_pmov_db_256, x86_avx512_mask_pmov_db_512, x86_avx512_mask_pmov_db_mem_128,   x86_avx512_mask_pmov_db_mem_256, x86_avx512_mask_pmov_db_mem_512, x86_avx512_mask_pmov_dw_128, x86_avx512_mask_pmov_dw_256,   x86_avx512_mask_pmov_dw_512, x86_avx512_mask_pmov_dw_mem_128, x86_avx512_mask_pmov_dw_mem_256, x86_avx512_mask_pmov_dw_mem_512,   x86_avx512_mask_pmov_qb_128, x86_avx512_mask_pmov_qb_256, x86_avx512_mask_pmov_qb_512, x86_avx512_mask_pmov_qb_mem_128,   x86_avx512_mask_pmov_qb_mem_256, x86_avx512_mask_pmov_qb_mem_512, x86_avx512_mask_pmov_qd_128, x86_avx512_mask_pmov_qd_256,   x86_avx512_mask_pmov_qd_512, x86_avx512_mask_pmov_qd_mem_128, x86_avx512_mask_pmov_qd_mem_256, x86_avx512_mask_pmov_qd_mem_512,   x86_avx512_mask_pmov_qw_128, x86_avx512_mask_pmov_qw_256, x86_avx512_mask_pmov_qw_512, x86_avx512_mask_pmov_qw_mem_128,   x86_avx512_mask_pmov_qw_mem_256, x86_avx512_mask_pmov_qw_mem_512, x86_avx512_mask_pmov_wb_128, x86_avx512_mask_pmov_wb_256,   x86_avx512_mask_pmov_wb_512, x86_avx512_mask_pmov_wb_mem_128, x86_avx512_mask_pmov_wb_mem_256, x86_avx512_mask_pmov_wb_mem_512,   x86_avx512_mask_pmovs_db_128, x86_avx512_mask_pmovs_db_256, x86_avx512_mask_pmovs_db_512, x86_avx512_mask_pmovs_db_mem_128,   x86_avx512_mask_pmovs_db_mem_256, x86_avx512_mask_pmovs_db_mem_512, x86_avx512_mask_pmovs_dw_128, x86_avx512_mask_pmovs_dw_256,   x86_avx512_mask_pmovs_dw_512, x86_avx512_mask_pmovs_dw_mem_128, x86_avx512_mask_pmovs_dw_mem_256, x86_avx512_mask_pmovs_dw_mem_512,   x86_avx512_mask_pmovs_qb_128, x86_avx512_mask_pmovs_qb_256, x86_avx512_mask_pmovs_qb_512, x86_avx512_mask_pmovs_qb_mem_128,   x86_avx512_mask_pmovs_qb_mem_256, x86_avx512_mask_pmovs_qb_mem_512, x86_avx512_mask_pmovs_qd_128, x86_avx512_mask_pmovs_qd_256,   x86_avx512_mask_pmovs_qd_512, x86_avx512_mask_pmovs_qd_mem_128, x86_avx512_mask_pmovs_qd_mem_256, x86_avx512_mask_pmovs_qd_mem_512,   x86_avx512_mask_pmovs_qw_128, x86_avx512_mask_pmovs_qw_256, x86_avx512_mask_pmovs_qw_512, x86_avx512_mask_pmovs_qw_mem_128,   x86_avx512_mask_pmovs_qw_mem_256, x86_avx512_mask_pmovs_qw_mem_512, x86_avx512_mask_pmovs_wb_128, x86_avx512_mask_pmovs_wb_256,   x86_avx512_mask_pmovs_wb_512, x86_avx512_mask_pmovs_wb_mem_128, x86_avx512_mask_pmovs_wb_mem_256, x86_avx512_mask_pmovs_wb_mem_512,   x86_avx512_mask_pmovus_db_128, x86_avx512_mask_pmovus_db_256, x86_avx512_mask_pmovus_db_512, x86_avx512_mask_pmovus_db_mem_128,   x86_avx512_mask_pmovus_db_mem_256, x86_avx512_mask_pmovus_db_mem_512, x86_avx512_mask_pmovus_dw_128, x86_avx512_mask_pmovus_dw_256,   x86_avx512_mask_pmovus_dw_512, x86_avx512_mask_pmovus_dw_mem_128, x86_avx512_mask_pmovus_dw_mem_256, x86_avx512_mask_pmovus_dw_mem_512,   x86_avx512_mask_pmovus_qb_128, x86_avx512_mask_pmovus_qb_256, x86_avx512_mask_pmovus_qb_512, x86_avx512_mask_pmovus_qb_mem_128,   x86_avx512_mask_pmovus_qb_mem_256, x86_avx512_mask_pmovus_qb_mem_512, x86_avx512_mask_pmovus_qd_128, x86_avx512_mask_pmovus_qd_256,   x86_avx512_mask_pmovus_qd_512, x86_avx512_mask_pmovus_qd_mem_128, x86_avx512_mask_pmovus_qd_mem_256, x86_avx512_mask_pmovus_qd_mem_512,   x86_avx512_mask_pmovus_qw_128, x86_avx512_mask_pmovus_qw_256, x86_avx512_mask_pmovus_qw_512, x86_avx512_mask_pmovus_qw_mem_128,   x86_avx512_mask_pmovus_qw_mem_256, x86_avx512_mask_pmovus_qw_mem_512, x86_avx512_mask_pmovus_wb_128, x86_avx512_mask_pmovus_wb_256,   x86_avx512_mask_pmovus_wb_512, x86_avx512_mask_pmovus_wb_mem_128, x86_avx512_mask_pmovus_wb_mem_256, x86_avx512_mask_pmovus_wb_mem_512,   x86_avx512_mask_range_pd_128, x86_avx512_mask_range_pd_256, x86_avx512_mask_range_pd_512, x86_avx512_mask_range_ps_128,   x86_avx512_mask_range_ps_256, x86_avx512_mask_range_ps_512, x86_avx512_mask_range_sd, x86_avx512_mask_range_ss,   x86_avx512_mask_reduce_pd_128, x86_avx512_mask_reduce_pd_256, x86_avx512_mask_reduce_pd_512, x86_avx512_mask_reduce_ps_128,   x86_avx512_mask_reduce_ps_256, x86_avx512_mask_reduce_ps_512, x86_avx512_mask_reduce_sd, x86_avx512_mask_reduce_ss,   x86_avx512_mask_rndscale_pd_128, x86_avx512_mask_rndscale_pd_256, x86_avx512_mask_rndscale_pd_512, x86_avx512_mask_rndscale_ps_128,   x86_avx512_mask_rndscale_ps_256, x86_avx512_mask_rndscale_ps_512, x86_avx512_mask_rndscale_sd, x86_avx512_mask_rndscale_ss,   x86_avx512_mask_scalef_pd_128, x86_avx512_mask_scalef_pd_256, x86_avx512_mask_scalef_pd_512, x86_avx512_mask_scalef_ps_128,   x86_avx512_mask_scalef_ps_256, x86_avx512_mask_scalef_ps_512, x86_avx512_mask_scalef_sd, x86_avx512_mask_scalef_ss,   x86_avx512_mask_scatter_dpd_512, x86_avx512_mask_scatter_dpi_512, x86_avx512_mask_scatter_dpq_512, x86_avx512_mask_scatter_dps_512,   x86_avx512_mask_scatter_qpd_512, x86_avx512_mask_scatter_qpi_512, x86_avx512_mask_scatter_qpq_512, x86_avx512_mask_scatter_qps_512,   x86_avx512_mask_scatterdiv2_df, x86_avx512_mask_scatterdiv2_di, x86_avx512_mask_scatterdiv4_df, x86_avx512_mask_scatterdiv4_di,   x86_avx512_mask_scatterdiv4_sf, x86_avx512_mask_scatterdiv4_si, x86_avx512_mask_scatterdiv8_sf, x86_avx512_mask_scatterdiv8_si,   x86_avx512_mask_scattersiv2_df, x86_avx512_mask_scattersiv2_di, x86_avx512_mask_scattersiv4_df, x86_avx512_mask_scattersiv4_di,   x86_avx512_mask_scattersiv4_sf, x86_avx512_mask_scattersiv4_si, x86_avx512_mask_scattersiv8_sf, x86_avx512_mask_scattersiv8_si,   x86_avx512_mask_sqrt_sd, x86_avx512_mask_sqrt_ss, x86_avx512_mask_sub_sd_round, x86_avx512_mask_sub_ss_round,   x86_avx512_mask_vcvtph2ps_128, x86_avx512_mask_vcvtph2ps_256, x86_avx512_mask_vcvtph2ps_512, x86_avx512_mask_vcvtps2ph_128,   x86_avx512_mask_vcvtps2ph_256, x86_avx512_mask_vcvtps2ph_512, x86_avx512_maskz_fixupimm_pd_128, x86_avx512_maskz_fixupimm_pd_256,   x86_avx512_maskz_fixupimm_pd_512, x86_avx512_maskz_fixupimm_ps_128, x86_avx512_maskz_fixupimm_ps_256, x86_avx512_maskz_fixupimm_ps_512,   x86_avx512_maskz_fixupimm_sd, x86_avx512_maskz_fixupimm_ss, x86_avx512_max_pd_512, x86_avx512_max_ps_512,   x86_avx512_min_pd_512, x86_avx512_min_ps_512, x86_avx512_mul_pd_512, x86_avx512_mul_ps_512,   x86_avx512_packssdw_512, x86_avx512_packsswb_512, x86_avx512_packusdw_512, x86_avx512_packuswb_512,   x86_avx512_permvar_df_256, x86_avx512_permvar_df_512, x86_avx512_permvar_di_256, x86_avx512_permvar_di_512,   x86_avx512_permvar_hi_128, x86_avx512_permvar_hi_256, x86_avx512_permvar_hi_512, x86_avx512_permvar_qi_128,   x86_avx512_permvar_qi_256, x86_avx512_permvar_qi_512, x86_avx512_permvar_sf_512, x86_avx512_permvar_si_512,   x86_avx512_pmaddubs_w_512, x86_avx512_pmaddw_d_512, x86_avx512_pmul_hr_sw_512, x86_avx512_pmulh_w_512,   x86_avx512_pmulhu_w_512, x86_avx512_pmultishift_qb_128, x86_avx512_pmultishift_qb_256, x86_avx512_pmultishift_qb_512,   x86_avx512_psad_bw_512, x86_avx512_pshuf_b_512, x86_avx512_psll_d_512, x86_avx512_psll_q_512,   x86_avx512_psll_w_512, x86_avx512_pslli_d_512, x86_avx512_pslli_q_512, x86_avx512_pslli_w_512,   x86_avx512_psllv_d_512, x86_avx512_psllv_q_512, x86_avx512_psllv_w_128, x86_avx512_psllv_w_256,   x86_avx512_psllv_w_512, x86_avx512_psra_d_512, x86_avx512_psra_q_128, x86_avx512_psra_q_256,   x86_avx512_psra_q_512, x86_avx512_psra_w_512, x86_avx512_psrai_d_512, x86_avx512_psrai_q_128,   x86_avx512_psrai_q_256, x86_avx512_psrai_q_512, x86_avx512_psrai_w_512, x86_avx512_psrav_d_512,   x86_avx512_psrav_q_128, x86_avx512_psrav_q_256, x86_avx512_psrav_q_512, x86_avx512_psrav_w_128,   x86_avx512_psrav_w_256, x86_avx512_psrav_w_512, x86_avx512_psrl_d_512, x86_avx512_psrl_q_512,   x86_avx512_psrl_w_512, x86_avx512_psrli_d_512, x86_avx512_psrli_q_512, x86_avx512_psrli_w_512,   x86_avx512_psrlv_d_512, x86_avx512_psrlv_q_512, x86_avx512_psrlv_w_128, x86_avx512_psrlv_w_256,   x86_avx512_psrlv_w_512, x86_avx512_pternlog_d_128, x86_avx512_pternlog_d_256, x86_avx512_pternlog_d_512,   x86_avx512_pternlog_q_128, x86_avx512_pternlog_q_256, x86_avx512_pternlog_q_512, x86_avx512_rcp14_pd_128,   x86_avx512_rcp14_pd_256, x86_avx512_rcp14_pd_512, x86_avx512_rcp14_ps_128, x86_avx512_rcp14_ps_256,   x86_avx512_rcp14_ps_512, x86_avx512_rcp14_sd, x86_avx512_rcp14_ss, x86_avx512_rcp28_pd,   x86_avx512_rcp28_ps, x86_avx512_rcp28_sd, x86_avx512_rcp28_ss, x86_avx512_rsqrt14_pd_128,   x86_avx512_rsqrt14_pd_256, x86_avx512_rsqrt14_pd_512, x86_avx512_rsqrt14_ps_128, x86_avx512_rsqrt14_ps_256,   x86_avx512_rsqrt14_ps_512, x86_avx512_rsqrt14_sd, x86_avx512_rsqrt14_ss, x86_avx512_rsqrt28_pd,   x86_avx512_rsqrt28_ps, x86_avx512_rsqrt28_sd, x86_avx512_rsqrt28_ss, x86_avx512_scatter_dpd_512,   x86_avx512_scatter_dpi_512, x86_avx512_scatter_dpq_512, x86_avx512_scatter_dps_512, x86_avx512_scatter_qpd_512,   x86_avx512_scatter_qpi_512, x86_avx512_scatter_qpq_512, x86_avx512_scatter_qps_512, x86_avx512_scatterdiv2_df,   x86_avx512_scatterdiv2_di, x86_avx512_scatterdiv4_df, x86_avx512_scatterdiv4_di, x86_avx512_scatterdiv4_sf,   x86_avx512_scatterdiv4_si, x86_avx512_scatterdiv8_sf, x86_avx512_scatterdiv8_si, x86_avx512_scatterpf_dpd_512,   x86_avx512_scatterpf_dps_512, x86_avx512_scatterpf_qpd_512, x86_avx512_scatterpf_qps_512, x86_avx512_scattersiv2_df,   x86_avx512_scattersiv2_di, x86_avx512_scattersiv4_df, x86_avx512_scattersiv4_di, x86_avx512_scattersiv4_sf,   x86_avx512_scattersiv4_si, x86_avx512_scattersiv8_sf, x86_avx512_scattersiv8_si, x86_avx512_sqrt_pd_512,   x86_avx512_sqrt_ps_512, x86_avx512_sub_pd_512, x86_avx512_sub_ps_512, x86_avx512_vcomi_sd,   x86_avx512_vcomi_ss, x86_avx512_vcvtsd2si32, x86_avx512_vcvtsd2si64, x86_avx512_vcvtsd2usi32,   x86_avx512_vcvtsd2usi64, x86_avx512_vcvtss2si32, x86_avx512_vcvtss2si64, x86_avx512_vcvtss2usi32,   x86_avx512_vcvtss2usi64, x86_avx512_vfmadd_f32, x86_avx512_vfmadd_f64, x86_avx512_vfmadd_pd_512,   x86_avx512_vfmadd_ps_512, x86_avx512_vfmaddsub_pd_512, x86_avx512_vfmaddsub_ps_512, x86_avx512_vpdpbusd_128,   x86_avx512_vpdpbusd_256, x86_avx512_vpdpbusd_512, x86_avx512_vpdpbusds_128, x86_avx512_vpdpbusds_256,   x86_avx512_vpdpbusds_512, x86_avx512_vpdpwssd_128, x86_avx512_vpdpwssd_256, x86_avx512_vpdpwssd_512,   x86_avx512_vpdpwssds_128, x86_avx512_vpdpwssds_256, x86_avx512_vpdpwssds_512, x86_avx512_vpermi2var_d_128,   x86_avx512_vpermi2var_d_256, x86_avx512_vpermi2var_d_512, x86_avx512_vpermi2var_hi_128, x86_avx512_vpermi2var_hi_256,   x86_avx512_vpermi2var_hi_512, x86_avx512_vpermi2var_pd_128, x86_avx512_vpermi2var_pd_256, x86_avx512_vpermi2var_pd_512,   x86_avx512_vpermi2var_ps_128, x86_avx512_vpermi2var_ps_256, x86_avx512_vpermi2var_ps_512, x86_avx512_vpermi2var_q_128,   x86_avx512_vpermi2var_q_256, x86_avx512_vpermi2var_q_512, x86_avx512_vpermi2var_qi_128, x86_avx512_vpermi2var_qi_256,   x86_avx512_vpermi2var_qi_512, x86_avx512_vpermilvar_pd_512, x86_avx512_vpermilvar_ps_512, x86_avx512_vpmadd52h_uq_128,   x86_avx512_vpmadd52h_uq_256, x86_avx512_vpmadd52h_uq_512, x86_avx512_vpmadd52l_uq_128, x86_avx512_vpmadd52l_uq_256,   x86_avx512_vpmadd52l_uq_512, x86_avx512_vpshufbitqmb_128, x86_avx512_vpshufbitqmb_256, x86_avx512_vpshufbitqmb_512,   x86_bmi_bextr_32, x86_bmi_bextr_64, x86_bmi_bzhi_32, x86_bmi_bzhi_64,   x86_bmi_pdep_32, x86_bmi_pdep_64, x86_bmi_pext_32, x86_bmi_pext_64,   x86_cldemote, x86_clflushopt, x86_clrssbsy, x86_clwb,   x86_clzero, x86_directstore32, x86_directstore64, x86_flags_read_u32,   x86_flags_read_u64, x86_flags_write_u32, x86_flags_write_u64, x86_fxrstor,   x86_fxrstor64, x86_fxsave, x86_fxsave64, x86_incsspd,   x86_incsspq, x86_int, x86_invpcid, x86_llwpcb,   x86_lwpins32, x86_lwpins64, x86_lwpval32, x86_lwpval64,   x86_mmx_emms, x86_mmx_femms, x86_mmx_maskmovq, x86_mmx_movnt_dq,   x86_mmx_packssdw, x86_mmx_packsswb, x86_mmx_packuswb, x86_mmx_padd_b,   x86_mmx_padd_d, x86_mmx_padd_q, x86_mmx_padd_w, x86_mmx_padds_b,   x86_mmx_padds_w, x86_mmx_paddus_b, x86_mmx_paddus_w, x86_mmx_palignr_b,   x86_mmx_pand, x86_mmx_pandn, x86_mmx_pavg_b, x86_mmx_pavg_w,   x86_mmx_pcmpeq_b, x86_mmx_pcmpeq_d, x86_mmx_pcmpeq_w, x86_mmx_pcmpgt_b,   x86_mmx_pcmpgt_d, x86_mmx_pcmpgt_w, x86_mmx_pextr_w, x86_mmx_pinsr_w,   x86_mmx_pmadd_wd, x86_mmx_pmaxs_w, x86_mmx_pmaxu_b, x86_mmx_pmins_w,   x86_mmx_pminu_b, x86_mmx_pmovmskb, x86_mmx_pmulh_w, x86_mmx_pmulhu_w,   x86_mmx_pmull_w, x86_mmx_pmulu_dq, x86_mmx_por, x86_mmx_psad_bw,   x86_mmx_psll_d, x86_mmx_psll_q, x86_mmx_psll_w, x86_mmx_pslli_d,   x86_mmx_pslli_q, x86_mmx_pslli_w, x86_mmx_psra_d, x86_mmx_psra_w,   x86_mmx_psrai_d, x86_mmx_psrai_w, x86_mmx_psrl_d, x86_mmx_psrl_q,   x86_mmx_psrl_w, x86_mmx_psrli_d, x86_mmx_psrli_q, x86_mmx_psrli_w,   x86_mmx_psub_b, x86_mmx_psub_d, x86_mmx_psub_q, x86_mmx_psub_w,   x86_mmx_psubs_b, x86_mmx_psubs_w, x86_mmx_psubus_b, x86_mmx_psubus_w,   x86_mmx_punpckhbw, x86_mmx_punpckhdq, x86_mmx_punpckhwd, x86_mmx_punpcklbw,   x86_mmx_punpckldq, x86_mmx_punpcklwd, x86_mmx_pxor, x86_monitorx,   x86_movdir64b, x86_mwaitx, x86_pclmulqdq, x86_pclmulqdq_256,   x86_pclmulqdq_512, x86_ptwrite32, x86_ptwrite64, x86_rdfsbase_32,   x86_rdfsbase_64, x86_rdgsbase_32, x86_rdgsbase_64, x86_rdpid,   x86_rdpkru, x86_rdpmc, x86_rdrand_16, x86_rdrand_32,   x86_rdrand_64, x86_rdseed_16, x86_rdseed_32, x86_rdseed_64,   x86_rdsspd, x86_rdsspq, x86_rdtsc, x86_rdtscp,   x86_rstorssp, x86_saveprevssp, x86_seh_ehguard, x86_seh_ehregnode,   x86_seh_lsda, x86_setssbsy, x86_sha1msg1, x86_sha1msg2,   x86_sha1nexte, x86_sha1rnds4, x86_sha256msg1, x86_sha256msg2,   x86_sha256rnds2, x86_slwpcb, x86_sse_cmp_ps, x86_sse_cmp_ss,   x86_sse_comieq_ss, x86_sse_comige_ss, x86_sse_comigt_ss, x86_sse_comile_ss,   x86_sse_comilt_ss, x86_sse_comineq_ss, x86_sse_cvtpd2pi, x86_sse_cvtpi2pd,   x86_sse_cvtpi2ps, x86_sse_cvtps2pi, x86_sse_cvtss2si, x86_sse_cvtss2si64,   x86_sse_cvttpd2pi, x86_sse_cvttps2pi, x86_sse_cvttss2si, x86_sse_cvttss2si64,   x86_sse_ldmxcsr, x86_sse_max_ps, x86_sse_max_ss, x86_sse_min_ps,   x86_sse_min_ss, x86_sse_movmsk_ps, x86_sse_pshuf_w, x86_sse_rcp_ps,   x86_sse_rcp_ss, x86_sse_rsqrt_ps, x86_sse_rsqrt_ss, x86_sse_sfence,   x86_sse_stmxcsr, x86_sse_ucomieq_ss, x86_sse_ucomige_ss, x86_sse_ucomigt_ss,   x86_sse_ucomile_ss, x86_sse_ucomilt_ss, x86_sse_ucomineq_ss, x86_sse2_clflush,   x86_sse2_cmp_pd, x86_sse2_cmp_sd, x86_sse2_comieq_sd, x86_sse2_comige_sd,   x86_sse2_comigt_sd, x86_sse2_comile_sd, x86_sse2_comilt_sd, x86_sse2_comineq_sd,   x86_sse2_cvtpd2dq, x86_sse2_cvtpd2ps, x86_sse2_cvtps2dq, x86_sse2_cvtsd2si,   x86_sse2_cvtsd2si64, x86_sse2_cvtsd2ss, x86_sse2_cvttpd2dq, x86_sse2_cvttps2dq,   x86_sse2_cvttsd2si, x86_sse2_cvttsd2si64, x86_sse2_lfence, x86_sse2_maskmov_dqu,   x86_sse2_max_pd, x86_sse2_max_sd, x86_sse2_mfence, x86_sse2_min_pd,   x86_sse2_min_sd, x86_sse2_movmsk_pd, x86_sse2_packssdw_128, x86_sse2_packsswb_128,   x86_sse2_packuswb_128, x86_sse2_pause, x86_sse2_pmadd_wd, x86_sse2_pmovmskb_128,   x86_sse2_pmulh_w, x86_sse2_pmulhu_w, x86_sse2_psad_bw, x86_sse2_psll_d,   x86_sse2_psll_q, x86_sse2_psll_w, x86_sse2_pslli_d, x86_sse2_pslli_q,   x86_sse2_pslli_w, x86_sse2_psra_d, x86_sse2_psra_w, x86_sse2_psrai_d,   x86_sse2_psrai_w, x86_sse2_psrl_d, x86_sse2_psrl_q, x86_sse2_psrl_w,   x86_sse2_psrli_d, x86_sse2_psrli_q, x86_sse2_psrli_w, x86_sse2_ucomieq_sd,   x86_sse2_ucomige_sd, x86_sse2_ucomigt_sd, x86_sse2_ucomile_sd, x86_sse2_ucomilt_sd,   x86_sse2_ucomineq_sd, x86_sse3_addsub_pd, x86_sse3_addsub_ps, x86_sse3_hadd_pd,   x86_sse3_hadd_ps, x86_sse3_hsub_pd, x86_sse3_hsub_ps, x86_sse3_ldu_dq,   x86_sse3_monitor, x86_sse3_mwait, x86_sse41_blendvpd, x86_sse41_blendvps,   x86_sse41_dppd, x86_sse41_dpps, x86_sse41_insertps, x86_sse41_mpsadbw,   x86_sse41_packusdw, x86_sse41_pblendvb, x86_sse41_phminposuw, x86_sse41_ptestc,   x86_sse41_ptestnzc, x86_sse41_ptestz, x86_sse41_round_pd, x86_sse41_round_ps,   x86_sse41_round_sd, x86_sse41_round_ss, x86_sse42_crc32_32_16, x86_sse42_crc32_32_32,   x86_sse42_crc32_32_8, x86_sse42_crc32_64_64, x86_sse42_pcmpestri128, x86_sse42_pcmpestria128,   x86_sse42_pcmpestric128, x86_sse42_pcmpestrio128, x86_sse42_pcmpestris128, x86_sse42_pcmpestriz128,   x86_sse42_pcmpestrm128, x86_sse42_pcmpistri128, x86_sse42_pcmpistria128, x86_sse42_pcmpistric128,   x86_sse42_pcmpistrio128, x86_sse42_pcmpistris128, x86_sse42_pcmpistriz128, x86_sse42_pcmpistrm128,   x86_sse4a_extrq, x86_sse4a_extrqi, x86_sse4a_insertq, x86_sse4a_insertqi,   x86_ssse3_pabs_b, x86_ssse3_pabs_d, x86_ssse3_pabs_w, x86_ssse3_phadd_d,   x86_ssse3_phadd_d_128, x86_ssse3_phadd_sw, x86_ssse3_phadd_sw_128, x86_ssse3_phadd_w,   x86_ssse3_phadd_w_128, x86_ssse3_phsub_d, x86_ssse3_phsub_d_128, x86_ssse3_phsub_sw,   x86_ssse3_phsub_sw_128, x86_ssse3_phsub_w, x86_ssse3_phsub_w_128, x86_ssse3_pmadd_ub_sw,   x86_ssse3_pmadd_ub_sw_128, x86_ssse3_pmul_hr_sw, x86_ssse3_pmul_hr_sw_128, x86_ssse3_pshuf_b,   x86_ssse3_pshuf_b_128, x86_ssse3_psign_b, x86_ssse3_psign_b_128, x86_ssse3_psign_d,   x86_ssse3_psign_d_128, x86_ssse3_psign_w, x86_ssse3_psign_w_128, x86_subborrow_32,   x86_subborrow_64, x86_tbm_bextri_u32, x86_tbm_bextri_u64, x86_tpause,   x86_umonitor, x86_umwait, x86_vcvtph2ps_128, x86_vcvtph2ps_256,   x86_vcvtps2ph_128, x86_vcvtps2ph_256, x86_vgf2p8affineinvqb_128, x86_vgf2p8affineinvqb_256,   x86_vgf2p8affineinvqb_512, x86_vgf2p8affineqb_128, x86_vgf2p8affineqb_256, x86_vgf2p8affineqb_512,   x86_vgf2p8mulb_128, x86_vgf2p8mulb_256, x86_vgf2p8mulb_512, x86_wbinvd,   x86_wbnoinvd, x86_wrfsbase_32, x86_wrfsbase_64, x86_wrgsbase_32,   x86_wrgsbase_64, x86_wrpkru, x86_wrssd, x86_wrssq,   x86_wrussd, x86_wrussq, x86_xabort, x86_xbegin,   x86_xend, x86_xgetbv, x86_xop_vfrcz_pd, x86_xop_vfrcz_pd_256,   x86_xop_vfrcz_ps, x86_xop_vfrcz_ps_256, x86_xop_vfrcz_sd, x86_xop_vfrcz_ss,   x86_xop_vpcomb, x86_xop_vpcomd, x86_xop_vpcomq, x86_xop_vpcomub,   x86_xop_vpcomud, x86_xop_vpcomuq, x86_xop_vpcomuw, x86_xop_vpcomw,   x86_xop_vpermil2pd, x86_xop_vpermil2pd_256, x86_xop_vpermil2ps, x86_xop_vpermil2ps_256,   x86_xop_vphaddbd, x86_xop_vphaddbq, x86_xop_vphaddbw, x86_xop_vphadddq,   x86_xop_vphaddubd, x86_xop_vphaddubq, x86_xop_vphaddubw, x86_xop_vphaddudq,   x86_xop_vphadduwd, x86_xop_vphadduwq, x86_xop_vphaddwd, x86_xop_vphaddwq,   x86_xop_vphsubbw, x86_xop_vphsubdq, x86_xop_vphsubwd, x86_xop_vpmacsdd,   x86_xop_vpmacsdqh, x86_xop_vpmacsdql, x86_xop_vpmacssdd, x86_xop_vpmacssdqh,   x86_xop_vpmacssdql, x86_xop_vpmacsswd, x86_xop_vpmacssww, x86_xop_vpmacswd,   x86_xop_vpmacsww, x86_xop_vpmadcsswd, x86_xop_vpmadcswd, x86_xop_vpperm,   x86_xop_vpshab, x86_xop_vpshad, x86_xop_vpshaq, x86_xop_vpshaw,   x86_xop_vpshlb, x86_xop_vpshld, x86_xop_vpshlq, x86_xop_vpshlw,   x86_xrstor, x86_xrstor64, x86_xrstors, x86_xrstors64,   x86_xsave, x86_xsave64, x86_xsavec, x86_xsavec64,   x86_xsaveopt, x86_xsaveopt64, x86_xsaves, x86_xsaves64,   x86_xsetbv, x86_xtest, xcore_bitrev, xcore_checkevent,   xcore_chkct, xcore_clre, xcore_clrpt, xcore_clrsr,   xcore_crc32, xcore_crc8, xcore_edu, xcore_eeu,   xcore_endin, xcore_freer, xcore_geted, xcore_getet,   xcore_getid, xcore_getps, xcore_getr, xcore_getst,   xcore_getts, xcore_in, xcore_inct, xcore_initcp,   xcore_initdp, xcore_initlr, xcore_initpc, xcore_initsp,   xcore_inshr, xcore_int, xcore_mjoin, xcore_msync,   xcore_out, xcore_outct, xcore_outshr, xcore_outt,   xcore_peek, xcore_setc, xcore_setclk, xcore_setd,   xcore_setev, xcore_setps, xcore_setpsc, xcore_setpt,   xcore_setrdy, xcore_setsr, xcore_settw, xcore_setv,   xcore_sext, xcore_ssync, xcore_syncr, xcore_testct,   xcore_testwct, xcore_waitevent, xcore_zext, num_intrinsics }

Functions
StringRef	getName (ID id)
	Return the LLVM name for an intrinsic, such as "llvm.ppc.altivec.lvx". More...
std::string	getName (ID id, ArrayRef< Type *> Tys)
	Return the LLVM name for an intrinsic, such as "llvm.ppc.altivec.lvx". More...
FunctionType *	getType (LLVMContext &Context, ID id, ArrayRef< Type *> Tys=None)
	Return the function type for an intrinsic. More...
bool	isOverloaded (ID id)
	Returns true if the intrinsic can be overloaded. More...
bool	isLeaf (ID id)
	Returns true if the intrinsic is a leaf, i.e. More...
AttributeList	getAttributes (LLVMContext &C, ID id)
	Return the attributes for an intrinsic. More...
Function *	getDeclaration (Module *M, ID id, ArrayRef< Type *> Tys=None)
	Create or insert an LLVM Function declaration for an intrinsic, and return it. More...
int	lookupLLVMIntrinsicByName (ArrayRef< const char *> NameTable, StringRef Name)
	Looks up Name in NameTable via binary search. More...
ID	getIntrinsicForGCCBuiltin (const char *Prefix, StringRef BuiltinName)
	Map a GCC builtin name to an intrinsic ID. More...
ID	getIntrinsicForMSBuiltin (const char *Prefix, StringRef BuiltinName)
	Map a MS builtin name to an intrinsic ID. More...
void	getIntrinsicInfoTableEntries (ID id, SmallVectorImpl< IITDescriptor > &T)
	Return the IIT table descriptor for the specified intrinsic into an array of IITDescriptors. More...
bool	matchIntrinsicType (Type *Ty, ArrayRef< IITDescriptor > &Infos, SmallVectorImpl< Type *> &ArgTys)
	Match the specified type (which comes from an intrinsic argument or return value) with the type constraints specified by the .td file. More...
bool	matchIntrinsicVarArg (bool isVarArg, ArrayRef< IITDescriptor > &Infos)
	Verify if the intrinsic has variable arguments. More...
llvm::Optional< Function * >	remangleIntrinsicFunction (Function *F)

Detailed Description

This namespace contains an enum with a value for every intrinsic/builtin function known by LLVM.

The enum values are returned by Function::getIntrinsicID().

Enumeration Type Documentation

ID

enum llvm::Intrinsic::ID : unsigned

Enumerator
not_intrinsic
addressofreturnaddress
adjust_trampoline
annotation
assume
bitreverse
bswap
canonicalize
ceil
clear_cache
codeview_annotation
convert_from_fp16
convert_to_fp16
copysign
coro_alloc
coro_begin
coro_destroy
coro_done
coro_end
coro_frame
coro_free
coro_id
coro_noop
coro_param
coro_promise
coro_resume
coro_save
coro_size
coro_subfn_addr
coro_suspend
cos
ctlz
ctpop
cttz
dbg_addr
dbg_declare
dbg_label
dbg_value
debugtrap
donothing
eh_dwarf_cfa
eh_exceptioncode
eh_exceptionpointer
eh_recoverfp
eh_return_i32
eh_return_i64
eh_sjlj_callsite
eh_sjlj_functioncontext
eh_sjlj_longjmp
eh_sjlj_lsda
eh_sjlj_setjmp
eh_sjlj_setup_dispatch
eh_typeid_for
eh_unwind_init
exp
exp2
expect
experimental_constrained_ceil
experimental_constrained_cos
experimental_constrained_exp
experimental_constrained_exp2
experimental_constrained_fadd
experimental_constrained_fdiv
experimental_constrained_floor
experimental_constrained_fma
experimental_constrained_fmul
experimental_constrained_frem
experimental_constrained_fsub
experimental_constrained_log
experimental_constrained_log10
experimental_constrained_log2
experimental_constrained_maxnum
experimental_constrained_minnum
experimental_constrained_nearbyint
experimental_constrained_pow
experimental_constrained_powi
experimental_constrained_rint
experimental_constrained_round
experimental_constrained_sin
experimental_constrained_sqrt
experimental_constrained_trunc
experimental_deoptimize
experimental_gc_relocate
experimental_gc_result
experimental_gc_statepoint
experimental_guard
experimental_patchpoint_i64
experimental_patchpoint_void
experimental_stackmap
experimental_vector_reduce_add
experimental_vector_reduce_and
experimental_vector_reduce_fadd
experimental_vector_reduce_fmax
experimental_vector_reduce_fmin
experimental_vector_reduce_fmul
experimental_vector_reduce_mul
experimental_vector_reduce_or
experimental_vector_reduce_smax
experimental_vector_reduce_smin
experimental_vector_reduce_umax
experimental_vector_reduce_umin
experimental_vector_reduce_xor
experimental_widenable_condition
fabs
floor
flt_rounds
fma
fmuladd
frameaddress
fshl
fshr
gcread
gcroot
gcwrite
get_dynamic_area_offset
icall_branch_funnel
init_trampoline
instrprof_increment
instrprof_increment_step
instrprof_value_profile
invariant_end
invariant_start
is_constant
launder_invariant_group
lifetime_end
lifetime_start
load_relative
localaddress
localescape
localrecover
log
log10
log2
longjmp
masked_compressstore
masked_expandload
masked_gather
masked_load
masked_scatter
masked_store
maximum
maxnum
memcpy
memcpy_element_unordered_atomic
memmove
memmove_element_unordered_atomic
memset
memset_element_unordered_atomic
minimum
minnum
nearbyint
objc_arc_annotation_bottomup_bbend
objc_arc_annotation_bottomup_bbstart
objc_arc_annotation_topdown_bbend
objc_arc_annotation_topdown_bbstart
objc_autorelease
objc_autoreleasePoolPop
objc_autoreleasePoolPush
objc_autoreleaseReturnValue
objc_clang_arc_use
objc_copyWeak
objc_destroyWeak
objc_initWeak
objc_loadWeak
objc_loadWeakRetained
objc_moveWeak
objc_release
objc_retain
objc_retain_autorelease
objc_retainAutorelease
objc_retainAutoreleaseReturnValue
objc_retainAutoreleasedReturnValue
objc_retainBlock
objc_retainedObject
objc_storeStrong
objc_storeWeak
objc_sync_enter
objc_sync_exit
objc_unretainedObject
objc_unretainedPointer
objc_unsafeClaimAutoreleasedReturnValue
objectsize
pcmarker
pow
powi
prefetch
ptr_annotation
read_register
readcyclecounter
returnaddress
rint
round
sadd_sat
sadd_with_overflow
setjmp
sideeffect
siglongjmp
sigsetjmp
sin
smul_fix
smul_with_overflow
sponentry
sqrt
ssa_copy
ssub_sat
ssub_with_overflow
stackguard
stackprotector
stackrestore
stacksave
strip_invariant_group
thread_pointer
trap
trunc
type_checked_load
type_test
uadd_sat
uadd_with_overflow
umul_with_overflow
usub_sat
usub_with_overflow
vacopy
vaend
vastart
var_annotation
write_register
xray_customevent
xray_typedevent
aarch64_clrex
aarch64_crc32b
aarch64_crc32cb
aarch64_crc32ch
aarch64_crc32cw
aarch64_crc32cx
aarch64_crc32h
aarch64_crc32w
aarch64_crc32x
aarch64_crypto_aesd
aarch64_crypto_aese
aarch64_crypto_aesimc
aarch64_crypto_aesmc
aarch64_crypto_sha1c
aarch64_crypto_sha1h
aarch64_crypto_sha1m
aarch64_crypto_sha1p
aarch64_crypto_sha1su0
aarch64_crypto_sha1su1
aarch64_crypto_sha256h
aarch64_crypto_sha256h2
aarch64_crypto_sha256su0
aarch64_crypto_sha256su1
aarch64_dmb
aarch64_dsb
aarch64_get_fpcr
aarch64_hint
aarch64_isb
aarch64_ldaxp
aarch64_ldaxr
aarch64_ldxp
aarch64_ldxr
aarch64_neon_abs
aarch64_neon_addhn
aarch64_neon_addp
aarch64_neon_cls
aarch64_neon_fabd
aarch64_neon_facge
aarch64_neon_facgt
aarch64_neon_faddv
aarch64_neon_fcvtas
aarch64_neon_fcvtau
aarch64_neon_fcvtms
aarch64_neon_fcvtmu
aarch64_neon_fcvtns
aarch64_neon_fcvtnu
aarch64_neon_fcvtps
aarch64_neon_fcvtpu
aarch64_neon_fcvtxn
aarch64_neon_fcvtzs
aarch64_neon_fcvtzu
aarch64_neon_fmax
aarch64_neon_fmaxnm
aarch64_neon_fmaxnmp
aarch64_neon_fmaxnmv
aarch64_neon_fmaxp
aarch64_neon_fmaxv
aarch64_neon_fmin
aarch64_neon_fminnm
aarch64_neon_fminnmp
aarch64_neon_fminnmv
aarch64_neon_fminp
aarch64_neon_fminv
aarch64_neon_fmlal
aarch64_neon_fmlal2
aarch64_neon_fmlsl
aarch64_neon_fmlsl2
aarch64_neon_fmulx
aarch64_neon_frecpe
aarch64_neon_frecps
aarch64_neon_frecpx
aarch64_neon_frintn
aarch64_neon_frsqrte
aarch64_neon_frsqrts
aarch64_neon_ld1x2
aarch64_neon_ld1x3
aarch64_neon_ld1x4
aarch64_neon_ld2
aarch64_neon_ld2lane
aarch64_neon_ld2r
aarch64_neon_ld3
aarch64_neon_ld3lane
aarch64_neon_ld3r
aarch64_neon_ld4
aarch64_neon_ld4lane
aarch64_neon_ld4r
aarch64_neon_pmul
aarch64_neon_pmull
aarch64_neon_pmull64
aarch64_neon_raddhn
aarch64_neon_rbit
aarch64_neon_rshrn
aarch64_neon_rsubhn
aarch64_neon_sabd
aarch64_neon_saddlp
aarch64_neon_saddlv
aarch64_neon_saddv
aarch64_neon_scalar_sqxtn
aarch64_neon_scalar_sqxtun
aarch64_neon_scalar_uqxtn
aarch64_neon_sdot
aarch64_neon_shadd
aarch64_neon_shll
aarch64_neon_shsub
aarch64_neon_smax
aarch64_neon_smaxp
aarch64_neon_smaxv
aarch64_neon_smin
aarch64_neon_sminp
aarch64_neon_sminv
aarch64_neon_smull
aarch64_neon_sqabs
aarch64_neon_sqadd
aarch64_neon_sqdmulh
aarch64_neon_sqdmull
aarch64_neon_sqdmulls_scalar
aarch64_neon_sqneg
aarch64_neon_sqrdmulh
aarch64_neon_sqrshl
aarch64_neon_sqrshrn
aarch64_neon_sqrshrun
aarch64_neon_sqshl
aarch64_neon_sqshlu
aarch64_neon_sqshrn
aarch64_neon_sqshrun
aarch64_neon_sqsub
aarch64_neon_sqxtn
aarch64_neon_sqxtun
aarch64_neon_srhadd
aarch64_neon_srshl
aarch64_neon_sshl
aarch64_neon_sshll
aarch64_neon_st1x2
aarch64_neon_st1x3
aarch64_neon_st1x4
aarch64_neon_st2
aarch64_neon_st2lane
aarch64_neon_st3
aarch64_neon_st3lane
aarch64_neon_st4
aarch64_neon_st4lane
aarch64_neon_subhn
aarch64_neon_suqadd
aarch64_neon_tbl1
aarch64_neon_tbl2
aarch64_neon_tbl3
aarch64_neon_tbl4
aarch64_neon_tbx1
aarch64_neon_tbx2
aarch64_neon_tbx3
aarch64_neon_tbx4
aarch64_neon_uabd
aarch64_neon_uaddlp
aarch64_neon_uaddlv
aarch64_neon_uaddv
aarch64_neon_udot
aarch64_neon_uhadd
aarch64_neon_uhsub
aarch64_neon_umax
aarch64_neon_umaxp
aarch64_neon_umaxv
aarch64_neon_umin
aarch64_neon_uminp
aarch64_neon_uminv
aarch64_neon_umull
aarch64_neon_uqadd
aarch64_neon_uqrshl
aarch64_neon_uqrshrn
aarch64_neon_uqshl
aarch64_neon_uqshrn
aarch64_neon_uqsub
aarch64_neon_uqxtn
aarch64_neon_urecpe
aarch64_neon_urhadd
aarch64_neon_urshl
aarch64_neon_ursqrte
aarch64_neon_ushl
aarch64_neon_ushll
aarch64_neon_usqadd
aarch64_neon_vcopy_lane
aarch64_neon_vcvtfp2fxs
aarch64_neon_vcvtfp2fxu
aarch64_neon_vcvtfp2hf
aarch64_neon_vcvtfxs2fp
aarch64_neon_vcvtfxu2fp
aarch64_neon_vcvthf2fp
aarch64_neon_vsli
aarch64_neon_vsri
aarch64_sdiv
aarch64_sisd_fabd
aarch64_sisd_fcvtxn
aarch64_space
aarch64_stlxp
aarch64_stlxr
aarch64_stxp
aarch64_stxr
aarch64_udiv
amdgcn_alignbit
amdgcn_alignbyte
amdgcn_atomic_dec
amdgcn_atomic_inc
amdgcn_buffer_atomic_add
amdgcn_buffer_atomic_and
amdgcn_buffer_atomic_cmpswap
amdgcn_buffer_atomic_or
amdgcn_buffer_atomic_smax
amdgcn_buffer_atomic_smin
amdgcn_buffer_atomic_sub
amdgcn_buffer_atomic_swap
amdgcn_buffer_atomic_umax
amdgcn_buffer_atomic_umin
amdgcn_buffer_atomic_xor
amdgcn_buffer_load
amdgcn_buffer_load_format
amdgcn_buffer_store
amdgcn_buffer_store_format
amdgcn_buffer_wbinvl1
amdgcn_buffer_wbinvl1_sc
amdgcn_buffer_wbinvl1_vol
amdgcn_class
amdgcn_cos
amdgcn_cubeid
amdgcn_cubema
amdgcn_cubesc
amdgcn_cubetc
amdgcn_cvt_pk_i16
amdgcn_cvt_pk_u16
amdgcn_cvt_pk_u8_f32
amdgcn_cvt_pknorm_i16
amdgcn_cvt_pknorm_u16
amdgcn_cvt_pkrtz
amdgcn_dispatch_id
amdgcn_dispatch_ptr
amdgcn_div_fixup
amdgcn_div_fmas
amdgcn_div_scale
amdgcn_ds_bpermute
amdgcn_ds_fadd
amdgcn_ds_fmax
amdgcn_ds_fmin
amdgcn_ds_ordered_add
amdgcn_ds_ordered_swap
amdgcn_ds_permute
amdgcn_ds_swizzle
amdgcn_else
amdgcn_end_cf
amdgcn_exp
amdgcn_exp_compr
amdgcn_fcmp
amdgcn_fdiv_fast
amdgcn_fdot2
amdgcn_fmad_ftz
amdgcn_fmed3
amdgcn_fmul_legacy
amdgcn_fract
amdgcn_frexp_exp
amdgcn_frexp_mant
amdgcn_groupstaticsize
amdgcn_icmp
amdgcn_if
amdgcn_if_break
amdgcn_image_atomic_add_1d
amdgcn_image_atomic_add_1darray
amdgcn_image_atomic_add_2d
amdgcn_image_atomic_add_2darray
amdgcn_image_atomic_add_2darraymsaa
amdgcn_image_atomic_add_2dmsaa
amdgcn_image_atomic_add_3d
amdgcn_image_atomic_add_cube
amdgcn_image_atomic_and_1d
amdgcn_image_atomic_and_1darray
amdgcn_image_atomic_and_2d
amdgcn_image_atomic_and_2darray
amdgcn_image_atomic_and_2darraymsaa
amdgcn_image_atomic_and_2dmsaa
amdgcn_image_atomic_and_3d
amdgcn_image_atomic_and_cube
amdgcn_image_atomic_cmpswap_1d
amdgcn_image_atomic_cmpswap_1darray
amdgcn_image_atomic_cmpswap_2d
amdgcn_image_atomic_cmpswap_2darray
amdgcn_image_atomic_cmpswap_2darraymsaa
amdgcn_image_atomic_cmpswap_2dmsaa
amdgcn_image_atomic_cmpswap_3d
amdgcn_image_atomic_cmpswap_cube
amdgcn_image_atomic_dec_1d
amdgcn_image_atomic_dec_1darray
amdgcn_image_atomic_dec_2d
amdgcn_image_atomic_dec_2darray
amdgcn_image_atomic_dec_2darraymsaa
amdgcn_image_atomic_dec_2dmsaa
amdgcn_image_atomic_dec_3d
amdgcn_image_atomic_dec_cube
amdgcn_image_atomic_inc_1d
amdgcn_image_atomic_inc_1darray
amdgcn_image_atomic_inc_2d
amdgcn_image_atomic_inc_2darray
amdgcn_image_atomic_inc_2darraymsaa
amdgcn_image_atomic_inc_2dmsaa
amdgcn_image_atomic_inc_3d
amdgcn_image_atomic_inc_cube
amdgcn_image_atomic_or_1d
amdgcn_image_atomic_or_1darray
amdgcn_image_atomic_or_2d
amdgcn_image_atomic_or_2darray
amdgcn_image_atomic_or_2darraymsaa
amdgcn_image_atomic_or_2dmsaa
amdgcn_image_atomic_or_3d
amdgcn_image_atomic_or_cube
amdgcn_image_atomic_smax_1d
amdgcn_image_atomic_smax_1darray
amdgcn_image_atomic_smax_2d
amdgcn_image_atomic_smax_2darray
amdgcn_image_atomic_smax_2darraymsaa
amdgcn_image_atomic_smax_2dmsaa
amdgcn_image_atomic_smax_3d
amdgcn_image_atomic_smax_cube
amdgcn_image_atomic_smin_1d
amdgcn_image_atomic_smin_1darray
amdgcn_image_atomic_smin_2d
amdgcn_image_atomic_smin_2darray
amdgcn_image_atomic_smin_2darraymsaa
amdgcn_image_atomic_smin_2dmsaa
amdgcn_image_atomic_smin_3d
amdgcn_image_atomic_smin_cube
amdgcn_image_atomic_sub_1d
amdgcn_image_atomic_sub_1darray
amdgcn_image_atomic_sub_2d
amdgcn_image_atomic_sub_2darray
amdgcn_image_atomic_sub_2darraymsaa
amdgcn_image_atomic_sub_2dmsaa
amdgcn_image_atomic_sub_3d
amdgcn_image_atomic_sub_cube
amdgcn_image_atomic_swap_1d
amdgcn_image_atomic_swap_1darray
amdgcn_image_atomic_swap_2d
amdgcn_image_atomic_swap_2darray
amdgcn_image_atomic_swap_2darraymsaa
amdgcn_image_atomic_swap_2dmsaa
amdgcn_image_atomic_swap_3d
amdgcn_image_atomic_swap_cube
amdgcn_image_atomic_umax_1d
amdgcn_image_atomic_umax_1darray
amdgcn_image_atomic_umax_2d
amdgcn_image_atomic_umax_2darray
amdgcn_image_atomic_umax_2darraymsaa
amdgcn_image_atomic_umax_2dmsaa
amdgcn_image_atomic_umax_3d
amdgcn_image_atomic_umax_cube
amdgcn_image_atomic_umin_1d
amdgcn_image_atomic_umin_1darray
amdgcn_image_atomic_umin_2d
amdgcn_image_atomic_umin_2darray
amdgcn_image_atomic_umin_2darraymsaa
amdgcn_image_atomic_umin_2dmsaa
amdgcn_image_atomic_umin_3d
amdgcn_image_atomic_umin_cube
amdgcn_image_atomic_xor_1d
amdgcn_image_atomic_xor_1darray
amdgcn_image_atomic_xor_2d
amdgcn_image_atomic_xor_2darray
amdgcn_image_atomic_xor_2darraymsaa
amdgcn_image_atomic_xor_2dmsaa
amdgcn_image_atomic_xor_3d
amdgcn_image_atomic_xor_cube
amdgcn_image_gather4_2d
amdgcn_image_gather4_2darray
amdgcn_image_gather4_b_2d
amdgcn_image_gather4_b_2darray
amdgcn_image_gather4_b_cl_2d
amdgcn_image_gather4_b_cl_2darray
amdgcn_image_gather4_b_cl_cube
amdgcn_image_gather4_b_cl_o_2d
amdgcn_image_gather4_b_cl_o_2darray
amdgcn_image_gather4_b_cl_o_cube
amdgcn_image_gather4_b_cube
amdgcn_image_gather4_b_o_2d
amdgcn_image_gather4_b_o_2darray
amdgcn_image_gather4_b_o_cube
amdgcn_image_gather4_c_2d
amdgcn_image_gather4_c_2darray
amdgcn_image_gather4_c_b_2d
amdgcn_image_gather4_c_b_2darray
amdgcn_image_gather4_c_b_cl_2d
amdgcn_image_gather4_c_b_cl_2darray
amdgcn_image_gather4_c_b_cl_cube
amdgcn_image_gather4_c_b_cl_o_2d
amdgcn_image_gather4_c_b_cl_o_2darray
amdgcn_image_gather4_c_b_cl_o_cube
amdgcn_image_gather4_c_b_cube
amdgcn_image_gather4_c_b_o_2d
amdgcn_image_gather4_c_b_o_2darray
amdgcn_image_gather4_c_b_o_cube
amdgcn_image_gather4_c_cl_2d
amdgcn_image_gather4_c_cl_2darray
amdgcn_image_gather4_c_cl_cube
amdgcn_image_gather4_c_cl_o_2d
amdgcn_image_gather4_c_cl_o_2darray
amdgcn_image_gather4_c_cl_o_cube
amdgcn_image_gather4_c_cube
amdgcn_image_gather4_c_l_2d
amdgcn_image_gather4_c_l_2darray
amdgcn_image_gather4_c_l_cube
amdgcn_image_gather4_c_l_o_2d
amdgcn_image_gather4_c_l_o_2darray
amdgcn_image_gather4_c_l_o_cube
amdgcn_image_gather4_c_lz_2d
amdgcn_image_gather4_c_lz_2darray
amdgcn_image_gather4_c_lz_cube
amdgcn_image_gather4_c_lz_o_2d
amdgcn_image_gather4_c_lz_o_2darray
amdgcn_image_gather4_c_lz_o_cube
amdgcn_image_gather4_c_o_2d
amdgcn_image_gather4_c_o_2darray
amdgcn_image_gather4_c_o_cube
amdgcn_image_gather4_cl_2d
amdgcn_image_gather4_cl_2darray
amdgcn_image_gather4_cl_cube
amdgcn_image_gather4_cl_o_2d
amdgcn_image_gather4_cl_o_2darray
amdgcn_image_gather4_cl_o_cube
amdgcn_image_gather4_cube
amdgcn_image_gather4_l_2d
amdgcn_image_gather4_l_2darray
amdgcn_image_gather4_l_cube
amdgcn_image_gather4_l_o_2d
amdgcn_image_gather4_l_o_2darray
amdgcn_image_gather4_l_o_cube
amdgcn_image_gather4_lz_2d
amdgcn_image_gather4_lz_2darray
amdgcn_image_gather4_lz_cube
amdgcn_image_gather4_lz_o_2d
amdgcn_image_gather4_lz_o_2darray
amdgcn_image_gather4_lz_o_cube
amdgcn_image_gather4_o_2d
amdgcn_image_gather4_o_2darray
amdgcn_image_gather4_o_cube
amdgcn_image_getlod_1d
amdgcn_image_getlod_1darray
amdgcn_image_getlod_2d
amdgcn_image_getlod_2darray
amdgcn_image_getlod_3d
amdgcn_image_getlod_cube
amdgcn_image_getresinfo_1d
amdgcn_image_getresinfo_1darray
amdgcn_image_getresinfo_2d
amdgcn_image_getresinfo_2darray
amdgcn_image_getresinfo_2darraymsaa
amdgcn_image_getresinfo_2dmsaa
amdgcn_image_getresinfo_3d
amdgcn_image_getresinfo_cube
amdgcn_image_load_1d
amdgcn_image_load_1darray
amdgcn_image_load_2d
amdgcn_image_load_2darray
amdgcn_image_load_2darraymsaa
amdgcn_image_load_2dmsaa
amdgcn_image_load_3d
amdgcn_image_load_cube
amdgcn_image_load_mip_1d
amdgcn_image_load_mip_1darray
amdgcn_image_load_mip_2d
amdgcn_image_load_mip_2darray
amdgcn_image_load_mip_3d
amdgcn_image_load_mip_cube
amdgcn_image_sample_1d
amdgcn_image_sample_1darray
amdgcn_image_sample_2d
amdgcn_image_sample_2darray
amdgcn_image_sample_3d
amdgcn_image_sample_b_1d
amdgcn_image_sample_b_1darray
amdgcn_image_sample_b_2d
amdgcn_image_sample_b_2darray
amdgcn_image_sample_b_3d
amdgcn_image_sample_b_cl_1d
amdgcn_image_sample_b_cl_1darray
amdgcn_image_sample_b_cl_2d
amdgcn_image_sample_b_cl_2darray
amdgcn_image_sample_b_cl_3d
amdgcn_image_sample_b_cl_cube
amdgcn_image_sample_b_cl_o_1d
amdgcn_image_sample_b_cl_o_1darray
amdgcn_image_sample_b_cl_o_2d
amdgcn_image_sample_b_cl_o_2darray
amdgcn_image_sample_b_cl_o_3d
amdgcn_image_sample_b_cl_o_cube
amdgcn_image_sample_b_cube
amdgcn_image_sample_b_o_1d
amdgcn_image_sample_b_o_1darray
amdgcn_image_sample_b_o_2d
amdgcn_image_sample_b_o_2darray
amdgcn_image_sample_b_o_3d
amdgcn_image_sample_b_o_cube
amdgcn_image_sample_c_1d
amdgcn_image_sample_c_1darray
amdgcn_image_sample_c_2d
amdgcn_image_sample_c_2darray
amdgcn_image_sample_c_3d
amdgcn_image_sample_c_b_1d
amdgcn_image_sample_c_b_1darray
amdgcn_image_sample_c_b_2d
amdgcn_image_sample_c_b_2darray
amdgcn_image_sample_c_b_3d
amdgcn_image_sample_c_b_cl_1d
amdgcn_image_sample_c_b_cl_1darray
amdgcn_image_sample_c_b_cl_2d
amdgcn_image_sample_c_b_cl_2darray
amdgcn_image_sample_c_b_cl_3d
amdgcn_image_sample_c_b_cl_cube
amdgcn_image_sample_c_b_cl_o_1d
amdgcn_image_sample_c_b_cl_o_1darray
amdgcn_image_sample_c_b_cl_o_2d
amdgcn_image_sample_c_b_cl_o_2darray
amdgcn_image_sample_c_b_cl_o_3d
amdgcn_image_sample_c_b_cl_o_cube
amdgcn_image_sample_c_b_cube
amdgcn_image_sample_c_b_o_1d
amdgcn_image_sample_c_b_o_1darray
amdgcn_image_sample_c_b_o_2d
amdgcn_image_sample_c_b_o_2darray
amdgcn_image_sample_c_b_o_3d
amdgcn_image_sample_c_b_o_cube
amdgcn_image_sample_c_cd_1d
amdgcn_image_sample_c_cd_1darray
amdgcn_image_sample_c_cd_2d
amdgcn_image_sample_c_cd_2darray
amdgcn_image_sample_c_cd_3d
amdgcn_image_sample_c_cd_cl_1d
amdgcn_image_sample_c_cd_cl_1darray
amdgcn_image_sample_c_cd_cl_2d
amdgcn_image_sample_c_cd_cl_2darray
amdgcn_image_sample_c_cd_cl_3d
amdgcn_image_sample_c_cd_cl_cube
amdgcn_image_sample_c_cd_cl_o_1d
amdgcn_image_sample_c_cd_cl_o_1darray
amdgcn_image_sample_c_cd_cl_o_2d
amdgcn_image_sample_c_cd_cl_o_2darray
amdgcn_image_sample_c_cd_cl_o_3d
amdgcn_image_sample_c_cd_cl_o_cube
amdgcn_image_sample_c_cd_cube
amdgcn_image_sample_c_cd_o_1d
amdgcn_image_sample_c_cd_o_1darray
amdgcn_image_sample_c_cd_o_2d
amdgcn_image_sample_c_cd_o_2darray
amdgcn_image_sample_c_cd_o_3d
amdgcn_image_sample_c_cd_o_cube
amdgcn_image_sample_c_cl_1d
amdgcn_image_sample_c_cl_1darray
amdgcn_image_sample_c_cl_2d
amdgcn_image_sample_c_cl_2darray
amdgcn_image_sample_c_cl_3d
amdgcn_image_sample_c_cl_cube
amdgcn_image_sample_c_cl_o_1d
amdgcn_image_sample_c_cl_o_1darray
amdgcn_image_sample_c_cl_o_2d
amdgcn_image_sample_c_cl_o_2darray
amdgcn_image_sample_c_cl_o_3d
amdgcn_image_sample_c_cl_o_cube
amdgcn_image_sample_c_cube
amdgcn_image_sample_c_d_1d
amdgcn_image_sample_c_d_1darray
amdgcn_image_sample_c_d_2d
amdgcn_image_sample_c_d_2darray
amdgcn_image_sample_c_d_3d
amdgcn_image_sample_c_d_cl_1d
amdgcn_image_sample_c_d_cl_1darray
amdgcn_image_sample_c_d_cl_2d
amdgcn_image_sample_c_d_cl_2darray
amdgcn_image_sample_c_d_cl_3d
amdgcn_image_sample_c_d_cl_cube
amdgcn_image_sample_c_d_cl_o_1d
amdgcn_image_sample_c_d_cl_o_1darray
amdgcn_image_sample_c_d_cl_o_2d
amdgcn_image_sample_c_d_cl_o_2darray
amdgcn_image_sample_c_d_cl_o_3d
amdgcn_image_sample_c_d_cl_o_cube
amdgcn_image_sample_c_d_cube
amdgcn_image_sample_c_d_o_1d
amdgcn_image_sample_c_d_o_1darray
amdgcn_image_sample_c_d_o_2d
amdgcn_image_sample_c_d_o_2darray
amdgcn_image_sample_c_d_o_3d
amdgcn_image_sample_c_d_o_cube
amdgcn_image_sample_c_l_1d
amdgcn_image_sample_c_l_1darray
amdgcn_image_sample_c_l_2d
amdgcn_image_sample_c_l_2darray
amdgcn_image_sample_c_l_3d
amdgcn_image_sample_c_l_cube
amdgcn_image_sample_c_l_o_1d
amdgcn_image_sample_c_l_o_1darray
amdgcn_image_sample_c_l_o_2d
amdgcn_image_sample_c_l_o_2darray
amdgcn_image_sample_c_l_o_3d
amdgcn_image_sample_c_l_o_cube
amdgcn_image_sample_c_lz_1d
amdgcn_image_sample_c_lz_1darray
amdgcn_image_sample_c_lz_2d
amdgcn_image_sample_c_lz_2darray
amdgcn_image_sample_c_lz_3d
amdgcn_image_sample_c_lz_cube
amdgcn_image_sample_c_lz_o_1d
amdgcn_image_sample_c_lz_o_1darray
amdgcn_image_sample_c_lz_o_2d
amdgcn_image_sample_c_lz_o_2darray
amdgcn_image_sample_c_lz_o_3d
amdgcn_image_sample_c_lz_o_cube
amdgcn_image_sample_c_o_1d
amdgcn_image_sample_c_o_1darray
amdgcn_image_sample_c_o_2d
amdgcn_image_sample_c_o_2darray
amdgcn_image_sample_c_o_3d
amdgcn_image_sample_c_o_cube
amdgcn_image_sample_cd_1d
amdgcn_image_sample_cd_1darray
amdgcn_image_sample_cd_2d
amdgcn_image_sample_cd_2darray
amdgcn_image_sample_cd_3d
amdgcn_image_sample_cd_cl_1d
amdgcn_image_sample_cd_cl_1darray
amdgcn_image_sample_cd_cl_2d
amdgcn_image_sample_cd_cl_2darray
amdgcn_image_sample_cd_cl_3d
amdgcn_image_sample_cd_cl_cube
amdgcn_image_sample_cd_cl_o_1d
amdgcn_image_sample_cd_cl_o_1darray
amdgcn_image_sample_cd_cl_o_2d
amdgcn_image_sample_cd_cl_o_2darray
amdgcn_image_sample_cd_cl_o_3d
amdgcn_image_sample_cd_cl_o_cube
amdgcn_image_sample_cd_cube
amdgcn_image_sample_cd_o_1d
amdgcn_image_sample_cd_o_1darray
amdgcn_image_sample_cd_o_2d
amdgcn_image_sample_cd_o_2darray
amdgcn_image_sample_cd_o_3d
amdgcn_image_sample_cd_o_cube
amdgcn_image_sample_cl_1d
amdgcn_image_sample_cl_1darray
amdgcn_image_sample_cl_2d
amdgcn_image_sample_cl_2darray
amdgcn_image_sample_cl_3d
amdgcn_image_sample_cl_cube
amdgcn_image_sample_cl_o_1d
amdgcn_image_sample_cl_o_1darray
amdgcn_image_sample_cl_o_2d
amdgcn_image_sample_cl_o_2darray
amdgcn_image_sample_cl_o_3d
amdgcn_image_sample_cl_o_cube
amdgcn_image_sample_cube
amdgcn_image_sample_d_1d
amdgcn_image_sample_d_1darray
amdgcn_image_sample_d_2d
amdgcn_image_sample_d_2darray
amdgcn_image_sample_d_3d
amdgcn_image_sample_d_cl_1d
amdgcn_image_sample_d_cl_1darray
amdgcn_image_sample_d_cl_2d
amdgcn_image_sample_d_cl_2darray
amdgcn_image_sample_d_cl_3d
amdgcn_image_sample_d_cl_cube
amdgcn_image_sample_d_cl_o_1d
amdgcn_image_sample_d_cl_o_1darray
amdgcn_image_sample_d_cl_o_2d
amdgcn_image_sample_d_cl_o_2darray
amdgcn_image_sample_d_cl_o_3d
amdgcn_image_sample_d_cl_o_cube
amdgcn_image_sample_d_cube
amdgcn_image_sample_d_o_1d
amdgcn_image_sample_d_o_1darray
amdgcn_image_sample_d_o_2d
amdgcn_image_sample_d_o_2darray
amdgcn_image_sample_d_o_3d
amdgcn_image_sample_d_o_cube
amdgcn_image_sample_l_1d
amdgcn_image_sample_l_1darray
amdgcn_image_sample_l_2d
amdgcn_image_sample_l_2darray
amdgcn_image_sample_l_3d
amdgcn_image_sample_l_cube
amdgcn_image_sample_l_o_1d
amdgcn_image_sample_l_o_1darray
amdgcn_image_sample_l_o_2d
amdgcn_image_sample_l_o_2darray
amdgcn_image_sample_l_o_3d
amdgcn_image_sample_l_o_cube
amdgcn_image_sample_lz_1d
amdgcn_image_sample_lz_1darray
amdgcn_image_sample_lz_2d
amdgcn_image_sample_lz_2darray
amdgcn_image_sample_lz_3d
amdgcn_image_sample_lz_cube
amdgcn_image_sample_lz_o_1d
amdgcn_image_sample_lz_o_1darray
amdgcn_image_sample_lz_o_2d
amdgcn_image_sample_lz_o_2darray
amdgcn_image_sample_lz_o_3d
amdgcn_image_sample_lz_o_cube
amdgcn_image_sample_o_1d
amdgcn_image_sample_o_1darray
amdgcn_image_sample_o_2d
amdgcn_image_sample_o_2darray
amdgcn_image_sample_o_3d
amdgcn_image_sample_o_cube
amdgcn_image_store_1d
amdgcn_image_store_1darray
amdgcn_image_store_2d
amdgcn_image_store_2darray
amdgcn_image_store_2darraymsaa
amdgcn_image_store_2dmsaa
amdgcn_image_store_3d
amdgcn_image_store_cube
amdgcn_image_store_mip_1d
amdgcn_image_store_mip_1darray
amdgcn_image_store_mip_2d
amdgcn_image_store_mip_2darray
amdgcn_image_store_mip_3d
amdgcn_image_store_mip_cube
amdgcn_implicit_buffer_ptr
amdgcn_implicitarg_ptr
amdgcn_init_exec
amdgcn_init_exec_from_input
amdgcn_interp_mov
amdgcn_interp_p1
amdgcn_interp_p2
amdgcn_kernarg_segment_ptr
amdgcn_kill
amdgcn_ldexp
amdgcn_lerp
amdgcn_log_clamp
amdgcn_loop
amdgcn_mbcnt_hi
amdgcn_mbcnt_lo
amdgcn_mov_dpp
amdgcn_mqsad_pk_u16_u8
amdgcn_mqsad_u32_u8
amdgcn_msad_u8
amdgcn_ps_live
amdgcn_qsad_pk_u16_u8
amdgcn_queue_ptr
amdgcn_raw_buffer_atomic_add
amdgcn_raw_buffer_atomic_and
amdgcn_raw_buffer_atomic_cmpswap
amdgcn_raw_buffer_atomic_or
amdgcn_raw_buffer_atomic_smax
amdgcn_raw_buffer_atomic_smin
amdgcn_raw_buffer_atomic_sub
amdgcn_raw_buffer_atomic_swap
amdgcn_raw_buffer_atomic_umax
amdgcn_raw_buffer_atomic_umin
amdgcn_raw_buffer_atomic_xor
amdgcn_raw_buffer_load
amdgcn_raw_buffer_load_format
amdgcn_raw_buffer_store
amdgcn_raw_buffer_store_format
amdgcn_raw_tbuffer_load
amdgcn_raw_tbuffer_store
amdgcn_rcp
amdgcn_rcp_legacy
amdgcn_readfirstlane
amdgcn_readlane
amdgcn_rsq
amdgcn_rsq_clamp
amdgcn_rsq_legacy
amdgcn_s_barrier
amdgcn_s_buffer_load
amdgcn_s_dcache_inv
amdgcn_s_dcache_inv_vol
amdgcn_s_dcache_wb
amdgcn_s_dcache_wb_vol
amdgcn_s_decperflevel
amdgcn_s_getpc
amdgcn_s_getreg
amdgcn_s_incperflevel
amdgcn_s_memrealtime
amdgcn_s_memtime
amdgcn_s_sendmsg
amdgcn_s_sendmsghalt
amdgcn_s_sleep
amdgcn_s_waitcnt
amdgcn_sad_hi_u8
amdgcn_sad_u16
amdgcn_sad_u8
amdgcn_sbfe
amdgcn_sdot2
amdgcn_sdot4
amdgcn_sdot8
amdgcn_set_inactive
amdgcn_sffbh
amdgcn_sin
amdgcn_struct_buffer_atomic_add
amdgcn_struct_buffer_atomic_and
amdgcn_struct_buffer_atomic_cmpswap
amdgcn_struct_buffer_atomic_or
amdgcn_struct_buffer_atomic_smax
amdgcn_struct_buffer_atomic_smin
amdgcn_struct_buffer_atomic_sub
amdgcn_struct_buffer_atomic_swap
amdgcn_struct_buffer_atomic_umax
amdgcn_struct_buffer_atomic_umin
amdgcn_struct_buffer_atomic_xor
amdgcn_struct_buffer_load
amdgcn_struct_buffer_load_format
amdgcn_struct_buffer_store
amdgcn_struct_buffer_store_format
amdgcn_struct_tbuffer_load
amdgcn_struct_tbuffer_store
amdgcn_tbuffer_load
amdgcn_tbuffer_store
amdgcn_trig_preop
amdgcn_ubfe
amdgcn_udot2
amdgcn_udot4
amdgcn_udot8
amdgcn_unreachable
amdgcn_update_dpp
amdgcn_wave_barrier
amdgcn_workgroup_id_x
amdgcn_workgroup_id_y
amdgcn_workgroup_id_z
amdgcn_workitem_id_x
amdgcn_workitem_id_y
amdgcn_workitem_id_z
amdgcn_wqm
amdgcn_wqm_vote
amdgcn_writelane
amdgcn_wwm
arm_cdp
arm_cdp2
arm_clrex
arm_crc32b
arm_crc32cb
arm_crc32ch
arm_crc32cw
arm_crc32h
arm_crc32w
arm_dbg
arm_dmb
arm_dsb
arm_get_fpscr
arm_hint
arm_isb
arm_ldaex
arm_ldaexd
arm_ldc
arm_ldc2
arm_ldc2l
arm_ldcl
arm_ldrex
arm_ldrexd
arm_mcr
arm_mcr2
arm_mcrr
arm_mcrr2
arm_mrc
arm_mrc2
arm_mrrc
arm_mrrc2
arm_neon_aesd
arm_neon_aese
arm_neon_aesimc
arm_neon_aesmc
arm_neon_sdot
arm_neon_sha1c
arm_neon_sha1h
arm_neon_sha1m
arm_neon_sha1p
arm_neon_sha1su0
arm_neon_sha1su1
arm_neon_sha256h
arm_neon_sha256h2
arm_neon_sha256su0
arm_neon_sha256su1
arm_neon_udot
arm_neon_vabds
arm_neon_vabdu
arm_neon_vabs
arm_neon_vacge
arm_neon_vacgt
arm_neon_vbsl
arm_neon_vcls
arm_neon_vcvtas
arm_neon_vcvtau
arm_neon_vcvtfp2fxs
arm_neon_vcvtfp2fxu
arm_neon_vcvtfp2hf
arm_neon_vcvtfxs2fp
arm_neon_vcvtfxu2fp
arm_neon_vcvthf2fp
arm_neon_vcvtms
arm_neon_vcvtmu
arm_neon_vcvtns
arm_neon_vcvtnu
arm_neon_vcvtps
arm_neon_vcvtpu
arm_neon_vhadds
arm_neon_vhaddu
arm_neon_vhsubs
arm_neon_vhsubu
arm_neon_vld1
arm_neon_vld1x2
arm_neon_vld1x3
arm_neon_vld1x4
arm_neon_vld2
arm_neon_vld2dup
arm_neon_vld2lane
arm_neon_vld3
arm_neon_vld3dup
arm_neon_vld3lane
arm_neon_vld4
arm_neon_vld4dup
arm_neon_vld4lane
arm_neon_vmaxnm
arm_neon_vmaxs
arm_neon_vmaxu
arm_neon_vminnm
arm_neon_vmins
arm_neon_vminu
arm_neon_vmullp
arm_neon_vmulls
arm_neon_vmullu
arm_neon_vmulp
arm_neon_vpadals
arm_neon_vpadalu
arm_neon_vpadd
arm_neon_vpaddls
arm_neon_vpaddlu
arm_neon_vpmaxs
arm_neon_vpmaxu
arm_neon_vpmins
arm_neon_vpminu
arm_neon_vqabs
arm_neon_vqadds
arm_neon_vqaddu
arm_neon_vqdmulh
arm_neon_vqdmull
arm_neon_vqmovns
arm_neon_vqmovnsu
arm_neon_vqmovnu
arm_neon_vqneg
arm_neon_vqrdmulh
arm_neon_vqrshiftns
arm_neon_vqrshiftnsu
arm_neon_vqrshiftnu
arm_neon_vqrshifts
arm_neon_vqrshiftu
arm_neon_vqshiftns
arm_neon_vqshiftnsu
arm_neon_vqshiftnu
arm_neon_vqshifts
arm_neon_vqshiftsu
arm_neon_vqshiftu
arm_neon_vqsubs
arm_neon_vqsubu
arm_neon_vraddhn
arm_neon_vrecpe
arm_neon_vrecps
arm_neon_vrhadds
arm_neon_vrhaddu
arm_neon_vrinta
arm_neon_vrintm
arm_neon_vrintn
arm_neon_vrintp
arm_neon_vrintx
arm_neon_vrintz
arm_neon_vrshiftn
arm_neon_vrshifts
arm_neon_vrshiftu
arm_neon_vrsqrte
arm_neon_vrsqrts
arm_neon_vrsubhn
arm_neon_vshiftins
arm_neon_vshifts
arm_neon_vshiftu
arm_neon_vst1
arm_neon_vst1x2
arm_neon_vst1x3
arm_neon_vst1x4
arm_neon_vst2
arm_neon_vst2lane
arm_neon_vst3
arm_neon_vst3lane
arm_neon_vst4
arm_neon_vst4lane
arm_neon_vtbl1
arm_neon_vtbl2
arm_neon_vtbl3
arm_neon_vtbl4
arm_neon_vtbx1
arm_neon_vtbx2
arm_neon_vtbx3
arm_neon_vtbx4
arm_qadd
arm_qadd16
arm_qadd8
arm_qasx
arm_qsax
arm_qsub
arm_qsub16
arm_qsub8
arm_sadd16
arm_sadd8
arm_sasx
arm_sel
arm_set_fpscr
arm_shadd16
arm_shadd8
arm_shasx
arm_shsax
arm_shsub16
arm_shsub8
arm_smlabb
arm_smlabt
arm_smlad
arm_smladx
arm_smlald
arm_smlaldx
arm_smlatb
arm_smlatt
arm_smlawb
arm_smlawt
arm_smlsd
arm_smlsdx
arm_smlsld
arm_smlsldx
arm_smuad
arm_smuadx
arm_smulbb
arm_smulbt
arm_smultb
arm_smultt
arm_smulwb
arm_smulwt
arm_smusd
arm_smusdx
arm_space
arm_ssat
arm_ssat16
arm_ssax
arm_ssub16
arm_ssub8
arm_stc
arm_stc2
arm_stc2l
arm_stcl
arm_stlex
arm_stlexd
arm_strex
arm_strexd
arm_sxtab16
arm_sxtb16
arm_uadd16
arm_uadd8
arm_uasx
arm_uhadd16
arm_uhadd8
arm_uhasx
arm_uhsax
arm_uhsub16
arm_uhsub8
arm_undefined
arm_uqadd16
arm_uqadd8
arm_uqasx
arm_uqsax
arm_uqsub16
arm_uqsub8
arm_usad8
arm_usada8
arm_usat
arm_usat16
arm_usax
arm_usub16
arm_usub8
arm_uxtab16
arm_uxtb16
arm_vcvtr
arm_vcvtru
bpf_load_byte
bpf_load_half
bpf_load_word
bpf_pseudo
hexagon_A2_abs
hexagon_A2_absp
hexagon_A2_abssat
hexagon_A2_add
hexagon_A2_addh_h16_hh
hexagon_A2_addh_h16_hl
hexagon_A2_addh_h16_lh
hexagon_A2_addh_h16_ll
hexagon_A2_addh_h16_sat_hh
hexagon_A2_addh_h16_sat_hl
hexagon_A2_addh_h16_sat_lh
hexagon_A2_addh_h16_sat_ll
hexagon_A2_addh_l16_hl
hexagon_A2_addh_l16_ll
hexagon_A2_addh_l16_sat_hl
hexagon_A2_addh_l16_sat_ll
hexagon_A2_addi
hexagon_A2_addp
hexagon_A2_addpsat
hexagon_A2_addsat
hexagon_A2_addsp
hexagon_A2_and
hexagon_A2_andir
hexagon_A2_andp
hexagon_A2_aslh
hexagon_A2_asrh
hexagon_A2_combine_hh
hexagon_A2_combine_hl
hexagon_A2_combine_lh
hexagon_A2_combine_ll
hexagon_A2_combineii
hexagon_A2_combinew
hexagon_A2_max
hexagon_A2_maxp
hexagon_A2_maxu
hexagon_A2_maxup
hexagon_A2_min
hexagon_A2_minp
hexagon_A2_minu
hexagon_A2_minup
hexagon_A2_neg
hexagon_A2_negp
hexagon_A2_negsat
hexagon_A2_not
hexagon_A2_notp
hexagon_A2_or
hexagon_A2_orir
hexagon_A2_orp
hexagon_A2_pxorf
hexagon_A2_roundsat
hexagon_A2_sat
hexagon_A2_satb
hexagon_A2_sath
hexagon_A2_satub
hexagon_A2_satuh
hexagon_A2_sub
hexagon_A2_subh_h16_hh
hexagon_A2_subh_h16_hl
hexagon_A2_subh_h16_lh
hexagon_A2_subh_h16_ll
hexagon_A2_subh_h16_sat_hh
hexagon_A2_subh_h16_sat_hl
hexagon_A2_subh_h16_sat_lh
hexagon_A2_subh_h16_sat_ll
hexagon_A2_subh_l16_hl
hexagon_A2_subh_l16_ll
hexagon_A2_subh_l16_sat_hl
hexagon_A2_subh_l16_sat_ll
hexagon_A2_subp
hexagon_A2_subri
hexagon_A2_subsat
hexagon_A2_svaddh
hexagon_A2_svaddhs
hexagon_A2_svadduhs
hexagon_A2_svavgh
hexagon_A2_svavghs
hexagon_A2_svnavgh
hexagon_A2_svsubh
hexagon_A2_svsubhs
hexagon_A2_svsubuhs
hexagon_A2_swiz
hexagon_A2_sxtb
hexagon_A2_sxth
hexagon_A2_sxtw
hexagon_A2_tfr
hexagon_A2_tfrcrr
hexagon_A2_tfrih
hexagon_A2_tfril
hexagon_A2_tfrp
hexagon_A2_tfrpi
hexagon_A2_tfrrcr
hexagon_A2_tfrsi
hexagon_A2_vabsh
hexagon_A2_vabshsat
hexagon_A2_vabsw
hexagon_A2_vabswsat
hexagon_A2_vaddb_map
hexagon_A2_vaddh
hexagon_A2_vaddhs
hexagon_A2_vaddub
hexagon_A2_vaddubs
hexagon_A2_vadduhs
hexagon_A2_vaddw
hexagon_A2_vaddws
hexagon_A2_vavgh
hexagon_A2_vavghcr
hexagon_A2_vavghr
hexagon_A2_vavgub
hexagon_A2_vavgubr
hexagon_A2_vavguh
hexagon_A2_vavguhr
hexagon_A2_vavguw
hexagon_A2_vavguwr
hexagon_A2_vavgw
hexagon_A2_vavgwcr
hexagon_A2_vavgwr
hexagon_A2_vcmpbeq
hexagon_A2_vcmpbgtu
hexagon_A2_vcmpheq
hexagon_A2_vcmphgt
hexagon_A2_vcmphgtu
hexagon_A2_vcmpweq
hexagon_A2_vcmpwgt
hexagon_A2_vcmpwgtu
hexagon_A2_vconj
hexagon_A2_vmaxb
hexagon_A2_vmaxh
hexagon_A2_vmaxub
hexagon_A2_vmaxuh
hexagon_A2_vmaxuw
hexagon_A2_vmaxw
hexagon_A2_vminb
hexagon_A2_vminh
hexagon_A2_vminub
hexagon_A2_vminuh
hexagon_A2_vminuw
hexagon_A2_vminw
hexagon_A2_vnavgh
hexagon_A2_vnavghcr
hexagon_A2_vnavghr
hexagon_A2_vnavgw
hexagon_A2_vnavgwcr
hexagon_A2_vnavgwr
hexagon_A2_vraddub
hexagon_A2_vraddub_acc
hexagon_A2_vrsadub
hexagon_A2_vrsadub_acc
hexagon_A2_vsubb_map
hexagon_A2_vsubh
hexagon_A2_vsubhs
hexagon_A2_vsubub
hexagon_A2_vsububs
hexagon_A2_vsubuhs
hexagon_A2_vsubw
hexagon_A2_vsubws
hexagon_A2_xor
hexagon_A2_xorp
hexagon_A2_zxtb
hexagon_A2_zxth
hexagon_A4_addp_c
hexagon_A4_andn
hexagon_A4_andnp
hexagon_A4_bitsplit
hexagon_A4_bitspliti
hexagon_A4_boundscheck
hexagon_A4_cmpbeq
hexagon_A4_cmpbeqi
hexagon_A4_cmpbgt
hexagon_A4_cmpbgti
hexagon_A4_cmpbgtu
hexagon_A4_cmpbgtui
hexagon_A4_cmpheq
hexagon_A4_cmpheqi
hexagon_A4_cmphgt
hexagon_A4_cmphgti
hexagon_A4_cmphgtu
hexagon_A4_cmphgtui
hexagon_A4_combineii
hexagon_A4_combineir
hexagon_A4_combineri
hexagon_A4_cround_ri
hexagon_A4_cround_rr
hexagon_A4_modwrapu
hexagon_A4_orn
hexagon_A4_ornp
hexagon_A4_rcmpeq
hexagon_A4_rcmpeqi
hexagon_A4_rcmpneq
hexagon_A4_rcmpneqi
hexagon_A4_round_ri
hexagon_A4_round_ri_sat
hexagon_A4_round_rr
hexagon_A4_round_rr_sat
hexagon_A4_subp_c
hexagon_A4_tfrcpp
hexagon_A4_tfrpcp
hexagon_A4_tlbmatch
hexagon_A4_vcmpbeq_any
hexagon_A4_vcmpbeqi
hexagon_A4_vcmpbgt
hexagon_A4_vcmpbgti
hexagon_A4_vcmpbgtui
hexagon_A4_vcmpheqi
hexagon_A4_vcmphgti
hexagon_A4_vcmphgtui
hexagon_A4_vcmpweqi
hexagon_A4_vcmpwgti
hexagon_A4_vcmpwgtui
hexagon_A4_vrmaxh
hexagon_A4_vrmaxuh
hexagon_A4_vrmaxuw
hexagon_A4_vrmaxw
hexagon_A4_vrminh
hexagon_A4_vrminuh
hexagon_A4_vrminuw
hexagon_A4_vrminw
hexagon_A5_ACS
hexagon_A5_vaddhubs
hexagon_A6_vcmpbeq_notany
hexagon_A6_vminub_RdP
hexagon_C2_all8
hexagon_C2_and
hexagon_C2_andn
hexagon_C2_any8
hexagon_C2_bitsclr
hexagon_C2_bitsclri
hexagon_C2_bitsset
hexagon_C2_cmpeq
hexagon_C2_cmpeqi
hexagon_C2_cmpeqp
hexagon_C2_cmpgei
hexagon_C2_cmpgeui
hexagon_C2_cmpgt
hexagon_C2_cmpgti
hexagon_C2_cmpgtp
hexagon_C2_cmpgtu
hexagon_C2_cmpgtui
hexagon_C2_cmpgtup
hexagon_C2_cmplt
hexagon_C2_cmpltu
hexagon_C2_mask
hexagon_C2_mux
hexagon_C2_muxii
hexagon_C2_muxir
hexagon_C2_muxri
hexagon_C2_not
hexagon_C2_or
hexagon_C2_orn
hexagon_C2_pxfer_map
hexagon_C2_tfrpr
hexagon_C2_tfrrp
hexagon_C2_vitpack
hexagon_C2_vmux
hexagon_C2_xor
hexagon_C4_and_and
hexagon_C4_and_andn
hexagon_C4_and_or
hexagon_C4_and_orn
hexagon_C4_cmplte
hexagon_C4_cmpltei
hexagon_C4_cmplteu
hexagon_C4_cmplteui
hexagon_C4_cmpneq
hexagon_C4_cmpneqi
hexagon_C4_fastcorner9
hexagon_C4_fastcorner9_not
hexagon_C4_nbitsclr
hexagon_C4_nbitsclri
hexagon_C4_nbitsset
hexagon_C4_or_and
hexagon_C4_or_andn
hexagon_C4_or_or
hexagon_C4_or_orn
hexagon_F2_conv_d2df
hexagon_F2_conv_d2sf
hexagon_F2_conv_df2d
hexagon_F2_conv_df2d_chop
hexagon_F2_conv_df2sf
hexagon_F2_conv_df2ud
hexagon_F2_conv_df2ud_chop
hexagon_F2_conv_df2uw
hexagon_F2_conv_df2uw_chop
hexagon_F2_conv_df2w
hexagon_F2_conv_df2w_chop
hexagon_F2_conv_sf2d
hexagon_F2_conv_sf2d_chop
hexagon_F2_conv_sf2df
hexagon_F2_conv_sf2ud
hexagon_F2_conv_sf2ud_chop
hexagon_F2_conv_sf2uw
hexagon_F2_conv_sf2uw_chop
hexagon_F2_conv_sf2w
hexagon_F2_conv_sf2w_chop
hexagon_F2_conv_ud2df
hexagon_F2_conv_ud2sf
hexagon_F2_conv_uw2df
hexagon_F2_conv_uw2sf
hexagon_F2_conv_w2df
hexagon_F2_conv_w2sf
hexagon_F2_dfadd
hexagon_F2_dfclass
hexagon_F2_dfcmpeq
hexagon_F2_dfcmpge
hexagon_F2_dfcmpgt
hexagon_F2_dfcmpuo
hexagon_F2_dfimm_n
hexagon_F2_dfimm_p
hexagon_F2_dfsub
hexagon_F2_sfadd
hexagon_F2_sfclass
hexagon_F2_sfcmpeq
hexagon_F2_sfcmpge
hexagon_F2_sfcmpgt
hexagon_F2_sfcmpuo
hexagon_F2_sffixupd
hexagon_F2_sffixupn
hexagon_F2_sffixupr
hexagon_F2_sffma
hexagon_F2_sffma_lib
hexagon_F2_sffma_sc
hexagon_F2_sffms
hexagon_F2_sffms_lib
hexagon_F2_sfimm_n
hexagon_F2_sfimm_p
hexagon_F2_sfinvsqrta
hexagon_F2_sfmax
hexagon_F2_sfmin
hexagon_F2_sfmpy
hexagon_F2_sfrecipa
hexagon_F2_sfsub
hexagon_L2_loadrb_pbr
hexagon_L2_loadrb_pci
hexagon_L2_loadrb_pcr
hexagon_L2_loadrd_pbr
hexagon_L2_loadrd_pci
hexagon_L2_loadrd_pcr
hexagon_L2_loadrh_pbr
hexagon_L2_loadrh_pci
hexagon_L2_loadrh_pcr
hexagon_L2_loadri_pbr
hexagon_L2_loadri_pci
hexagon_L2_loadri_pcr
hexagon_L2_loadrub_pbr
hexagon_L2_loadrub_pci
hexagon_L2_loadrub_pcr
hexagon_L2_loadruh_pbr
hexagon_L2_loadruh_pci
hexagon_L2_loadruh_pcr
hexagon_L2_loadw_locked
hexagon_L4_loadd_locked
hexagon_M2_acci
hexagon_M2_accii
hexagon_M2_cmaci_s0
hexagon_M2_cmacr_s0
hexagon_M2_cmacs_s0
hexagon_M2_cmacs_s1
hexagon_M2_cmacsc_s0
hexagon_M2_cmacsc_s1
hexagon_M2_cmpyi_s0
hexagon_M2_cmpyr_s0
hexagon_M2_cmpyrs_s0
hexagon_M2_cmpyrs_s1
hexagon_M2_cmpyrsc_s0
hexagon_M2_cmpyrsc_s1
hexagon_M2_cmpys_s0
hexagon_M2_cmpys_s1
hexagon_M2_cmpysc_s0
hexagon_M2_cmpysc_s1
hexagon_M2_cnacs_s0
hexagon_M2_cnacs_s1
hexagon_M2_cnacsc_s0
hexagon_M2_cnacsc_s1
hexagon_M2_dpmpyss_acc_s0
hexagon_M2_dpmpyss_nac_s0
hexagon_M2_dpmpyss_rnd_s0
hexagon_M2_dpmpyss_s0
hexagon_M2_dpmpyuu_acc_s0
hexagon_M2_dpmpyuu_nac_s0
hexagon_M2_dpmpyuu_s0
hexagon_M2_hmmpyh_rs1
hexagon_M2_hmmpyh_s1
hexagon_M2_hmmpyl_rs1
hexagon_M2_hmmpyl_s1
hexagon_M2_maci
hexagon_M2_macsin
hexagon_M2_macsip
hexagon_M2_mmachs_rs0
hexagon_M2_mmachs_rs1
hexagon_M2_mmachs_s0
hexagon_M2_mmachs_s1
hexagon_M2_mmacls_rs0
hexagon_M2_mmacls_rs1
hexagon_M2_mmacls_s0
hexagon_M2_mmacls_s1
hexagon_M2_mmacuhs_rs0
hexagon_M2_mmacuhs_rs1
hexagon_M2_mmacuhs_s0
hexagon_M2_mmacuhs_s1
hexagon_M2_mmaculs_rs0
hexagon_M2_mmaculs_rs1
hexagon_M2_mmaculs_s0
hexagon_M2_mmaculs_s1
hexagon_M2_mmpyh_rs0
hexagon_M2_mmpyh_rs1
hexagon_M2_mmpyh_s0
hexagon_M2_mmpyh_s1
hexagon_M2_mmpyl_rs0
hexagon_M2_mmpyl_rs1
hexagon_M2_mmpyl_s0
hexagon_M2_mmpyl_s1
hexagon_M2_mmpyuh_rs0
hexagon_M2_mmpyuh_rs1
hexagon_M2_mmpyuh_s0
hexagon_M2_mmpyuh_s1
hexagon_M2_mmpyul_rs0
hexagon_M2_mmpyul_rs1
hexagon_M2_mmpyul_s0
hexagon_M2_mmpyul_s1
hexagon_M2_mnaci
hexagon_M2_mpy_acc_hh_s0
hexagon_M2_mpy_acc_hh_s1
hexagon_M2_mpy_acc_hl_s0
hexagon_M2_mpy_acc_hl_s1
hexagon_M2_mpy_acc_lh_s0
hexagon_M2_mpy_acc_lh_s1
hexagon_M2_mpy_acc_ll_s0
hexagon_M2_mpy_acc_ll_s1
hexagon_M2_mpy_acc_sat_hh_s0
hexagon_M2_mpy_acc_sat_hh_s1
hexagon_M2_mpy_acc_sat_hl_s0
hexagon_M2_mpy_acc_sat_hl_s1
hexagon_M2_mpy_acc_sat_lh_s0
hexagon_M2_mpy_acc_sat_lh_s1
hexagon_M2_mpy_acc_sat_ll_s0
hexagon_M2_mpy_acc_sat_ll_s1
hexagon_M2_mpy_hh_s0
hexagon_M2_mpy_hh_s1
hexagon_M2_mpy_hl_s0
hexagon_M2_mpy_hl_s1
hexagon_M2_mpy_lh_s0
hexagon_M2_mpy_lh_s1
hexagon_M2_mpy_ll_s0
hexagon_M2_mpy_ll_s1
hexagon_M2_mpy_nac_hh_s0
hexagon_M2_mpy_nac_hh_s1
hexagon_M2_mpy_nac_hl_s0
hexagon_M2_mpy_nac_hl_s1
hexagon_M2_mpy_nac_lh_s0
hexagon_M2_mpy_nac_lh_s1
hexagon_M2_mpy_nac_ll_s0
hexagon_M2_mpy_nac_ll_s1
hexagon_M2_mpy_nac_sat_hh_s0
hexagon_M2_mpy_nac_sat_hh_s1
hexagon_M2_mpy_nac_sat_hl_s0
hexagon_M2_mpy_nac_sat_hl_s1
hexagon_M2_mpy_nac_sat_lh_s0
hexagon_M2_mpy_nac_sat_lh_s1
hexagon_M2_mpy_nac_sat_ll_s0
hexagon_M2_mpy_nac_sat_ll_s1
hexagon_M2_mpy_rnd_hh_s0
hexagon_M2_mpy_rnd_hh_s1
hexagon_M2_mpy_rnd_hl_s0
hexagon_M2_mpy_rnd_hl_s1
hexagon_M2_mpy_rnd_lh_s0
hexagon_M2_mpy_rnd_lh_s1
hexagon_M2_mpy_rnd_ll_s0
hexagon_M2_mpy_rnd_ll_s1
hexagon_M2_mpy_sat_hh_s0
hexagon_M2_mpy_sat_hh_s1
hexagon_M2_mpy_sat_hl_s0
hexagon_M2_mpy_sat_hl_s1
hexagon_M2_mpy_sat_lh_s0
hexagon_M2_mpy_sat_lh_s1
hexagon_M2_mpy_sat_ll_s0
hexagon_M2_mpy_sat_ll_s1
hexagon_M2_mpy_sat_rnd_hh_s0
hexagon_M2_mpy_sat_rnd_hh_s1
hexagon_M2_mpy_sat_rnd_hl_s0
hexagon_M2_mpy_sat_rnd_hl_s1
hexagon_M2_mpy_sat_rnd_lh_s0
hexagon_M2_mpy_sat_rnd_lh_s1
hexagon_M2_mpy_sat_rnd_ll_s0
hexagon_M2_mpy_sat_rnd_ll_s1
hexagon_M2_mpy_up
hexagon_M2_mpy_up_s1
hexagon_M2_mpy_up_s1_sat
hexagon_M2_mpyd_acc_hh_s0
hexagon_M2_mpyd_acc_hh_s1
hexagon_M2_mpyd_acc_hl_s0
hexagon_M2_mpyd_acc_hl_s1
hexagon_M2_mpyd_acc_lh_s0
hexagon_M2_mpyd_acc_lh_s1
hexagon_M2_mpyd_acc_ll_s0
hexagon_M2_mpyd_acc_ll_s1
hexagon_M2_mpyd_hh_s0
hexagon_M2_mpyd_hh_s1
hexagon_M2_mpyd_hl_s0
hexagon_M2_mpyd_hl_s1
hexagon_M2_mpyd_lh_s0
hexagon_M2_mpyd_lh_s1
hexagon_M2_mpyd_ll_s0
hexagon_M2_mpyd_ll_s1
hexagon_M2_mpyd_nac_hh_s0
hexagon_M2_mpyd_nac_hh_s1
hexagon_M2_mpyd_nac_hl_s0
hexagon_M2_mpyd_nac_hl_s1
hexagon_M2_mpyd_nac_lh_s0
hexagon_M2_mpyd_nac_lh_s1
hexagon_M2_mpyd_nac_ll_s0
hexagon_M2_mpyd_nac_ll_s1
hexagon_M2_mpyd_rnd_hh_s0
hexagon_M2_mpyd_rnd_hh_s1
hexagon_M2_mpyd_rnd_hl_s0
hexagon_M2_mpyd_rnd_hl_s1
hexagon_M2_mpyd_rnd_lh_s0
hexagon_M2_mpyd_rnd_lh_s1
hexagon_M2_mpyd_rnd_ll_s0
hexagon_M2_mpyd_rnd_ll_s1
hexagon_M2_mpyi
hexagon_M2_mpysin
hexagon_M2_mpysip
hexagon_M2_mpysmi
hexagon_M2_mpysu_up
hexagon_M2_mpyu_acc_hh_s0
hexagon_M2_mpyu_acc_hh_s1
hexagon_M2_mpyu_acc_hl_s0
hexagon_M2_mpyu_acc_hl_s1
hexagon_M2_mpyu_acc_lh_s0
hexagon_M2_mpyu_acc_lh_s1
hexagon_M2_mpyu_acc_ll_s0
hexagon_M2_mpyu_acc_ll_s1
hexagon_M2_mpyu_hh_s0
hexagon_M2_mpyu_hh_s1
hexagon_M2_mpyu_hl_s0
hexagon_M2_mpyu_hl_s1
hexagon_M2_mpyu_lh_s0
hexagon_M2_mpyu_lh_s1
hexagon_M2_mpyu_ll_s0
hexagon_M2_mpyu_ll_s1
hexagon_M2_mpyu_nac_hh_s0
hexagon_M2_mpyu_nac_hh_s1
hexagon_M2_mpyu_nac_hl_s0
hexagon_M2_mpyu_nac_hl_s1
hexagon_M2_mpyu_nac_lh_s0
hexagon_M2_mpyu_nac_lh_s1
hexagon_M2_mpyu_nac_ll_s0
hexagon_M2_mpyu_nac_ll_s1
hexagon_M2_mpyu_up
hexagon_M2_mpyud_acc_hh_s0
hexagon_M2_mpyud_acc_hh_s1
hexagon_M2_mpyud_acc_hl_s0
hexagon_M2_mpyud_acc_hl_s1
hexagon_M2_mpyud_acc_lh_s0
hexagon_M2_mpyud_acc_lh_s1
hexagon_M2_mpyud_acc_ll_s0
hexagon_M2_mpyud_acc_ll_s1
hexagon_M2_mpyud_hh_s0
hexagon_M2_mpyud_hh_s1
hexagon_M2_mpyud_hl_s0
hexagon_M2_mpyud_hl_s1
hexagon_M2_mpyud_lh_s0
hexagon_M2_mpyud_lh_s1
hexagon_M2_mpyud_ll_s0
hexagon_M2_mpyud_ll_s1
hexagon_M2_mpyud_nac_hh_s0
hexagon_M2_mpyud_nac_hh_s1
hexagon_M2_mpyud_nac_hl_s0
hexagon_M2_mpyud_nac_hl_s1
hexagon_M2_mpyud_nac_lh_s0
hexagon_M2_mpyud_nac_lh_s1
hexagon_M2_mpyud_nac_ll_s0
hexagon_M2_mpyud_nac_ll_s1
hexagon_M2_mpyui
hexagon_M2_nacci
hexagon_M2_naccii
hexagon_M2_subacc
hexagon_M2_vabsdiffh
hexagon_M2_vabsdiffw
hexagon_M2_vcmac_s0_sat_i
hexagon_M2_vcmac_s0_sat_r
hexagon_M2_vcmpy_s0_sat_i
hexagon_M2_vcmpy_s0_sat_r
hexagon_M2_vcmpy_s1_sat_i
hexagon_M2_vcmpy_s1_sat_r
hexagon_M2_vdmacs_s0
hexagon_M2_vdmacs_s1
hexagon_M2_vdmpyrs_s0
hexagon_M2_vdmpyrs_s1
hexagon_M2_vdmpys_s0
hexagon_M2_vdmpys_s1
hexagon_M2_vmac2
hexagon_M2_vmac2es
hexagon_M2_vmac2es_s0
hexagon_M2_vmac2es_s1
hexagon_M2_vmac2s_s0
hexagon_M2_vmac2s_s1
hexagon_M2_vmac2su_s0
hexagon_M2_vmac2su_s1
hexagon_M2_vmpy2es_s0
hexagon_M2_vmpy2es_s1
hexagon_M2_vmpy2s_s0
hexagon_M2_vmpy2s_s0pack
hexagon_M2_vmpy2s_s1
hexagon_M2_vmpy2s_s1pack
hexagon_M2_vmpy2su_s0
hexagon_M2_vmpy2su_s1
hexagon_M2_vraddh
hexagon_M2_vradduh
hexagon_M2_vrcmaci_s0
hexagon_M2_vrcmaci_s0c
hexagon_M2_vrcmacr_s0
hexagon_M2_vrcmacr_s0c
hexagon_M2_vrcmpyi_s0
hexagon_M2_vrcmpyi_s0c
hexagon_M2_vrcmpyr_s0
hexagon_M2_vrcmpyr_s0c
hexagon_M2_vrcmpys_acc_s1
hexagon_M2_vrcmpys_s1
hexagon_M2_vrcmpys_s1rp
hexagon_M2_vrmac_s0
hexagon_M2_vrmpy_s0
hexagon_M2_xor_xacc
hexagon_M4_and_and
hexagon_M4_and_andn
hexagon_M4_and_or
hexagon_M4_and_xor
hexagon_M4_cmpyi_wh
hexagon_M4_cmpyi_whc
hexagon_M4_cmpyr_wh
hexagon_M4_cmpyr_whc
hexagon_M4_mac_up_s1_sat
hexagon_M4_mpyri_addi
hexagon_M4_mpyri_addr
hexagon_M4_mpyri_addr_u2
hexagon_M4_mpyrr_addi
hexagon_M4_mpyrr_addr
hexagon_M4_nac_up_s1_sat
hexagon_M4_or_and
hexagon_M4_or_andn
hexagon_M4_or_or
hexagon_M4_or_xor
hexagon_M4_pmpyw
hexagon_M4_pmpyw_acc
hexagon_M4_vpmpyh
hexagon_M4_vpmpyh_acc
hexagon_M4_vrmpyeh_acc_s0
hexagon_M4_vrmpyeh_acc_s1
hexagon_M4_vrmpyeh_s0
hexagon_M4_vrmpyeh_s1
hexagon_M4_vrmpyoh_acc_s0
hexagon_M4_vrmpyoh_acc_s1
hexagon_M4_vrmpyoh_s0
hexagon_M4_vrmpyoh_s1
hexagon_M4_xor_and
hexagon_M4_xor_andn
hexagon_M4_xor_or
hexagon_M4_xor_xacc
hexagon_M5_vdmacbsu
hexagon_M5_vdmpybsu
hexagon_M5_vmacbsu
hexagon_M5_vmacbuu
hexagon_M5_vmpybsu
hexagon_M5_vmpybuu
hexagon_M5_vrmacbsu
hexagon_M5_vrmacbuu
hexagon_M5_vrmpybsu
hexagon_M5_vrmpybuu
hexagon_M6_vabsdiffb
hexagon_M6_vabsdiffub
hexagon_S2_addasl_rrri
hexagon_S2_asl_i_p
hexagon_S2_asl_i_p_acc
hexagon_S2_asl_i_p_and
hexagon_S2_asl_i_p_nac
hexagon_S2_asl_i_p_or
hexagon_S2_asl_i_p_xacc
hexagon_S2_asl_i_r
hexagon_S2_asl_i_r_acc
hexagon_S2_asl_i_r_and
hexagon_S2_asl_i_r_nac
hexagon_S2_asl_i_r_or
hexagon_S2_asl_i_r_sat
hexagon_S2_asl_i_r_xacc
hexagon_S2_asl_i_vh
hexagon_S2_asl_i_vw
hexagon_S2_asl_r_p
hexagon_S2_asl_r_p_acc
hexagon_S2_asl_r_p_and
hexagon_S2_asl_r_p_nac
hexagon_S2_asl_r_p_or
hexagon_S2_asl_r_p_xor
hexagon_S2_asl_r_r
hexagon_S2_asl_r_r_acc
hexagon_S2_asl_r_r_and
hexagon_S2_asl_r_r_nac
hexagon_S2_asl_r_r_or
hexagon_S2_asl_r_r_sat
hexagon_S2_asl_r_vh
hexagon_S2_asl_r_vw
hexagon_S2_asr_i_p
hexagon_S2_asr_i_p_acc
hexagon_S2_asr_i_p_and
hexagon_S2_asr_i_p_nac
hexagon_S2_asr_i_p_or
hexagon_S2_asr_i_p_rnd
hexagon_S2_asr_i_p_rnd_goodsyntax
hexagon_S2_asr_i_r
hexagon_S2_asr_i_r_acc
hexagon_S2_asr_i_r_and
hexagon_S2_asr_i_r_nac
hexagon_S2_asr_i_r_or
hexagon_S2_asr_i_r_rnd
hexagon_S2_asr_i_r_rnd_goodsyntax
hexagon_S2_asr_i_svw_trun
hexagon_S2_asr_i_vh
hexagon_S2_asr_i_vw
hexagon_S2_asr_r_p
hexagon_S2_asr_r_p_acc
hexagon_S2_asr_r_p_and
hexagon_S2_asr_r_p_nac
hexagon_S2_asr_r_p_or
hexagon_S2_asr_r_p_xor
hexagon_S2_asr_r_r
hexagon_S2_asr_r_r_acc
hexagon_S2_asr_r_r_and
hexagon_S2_asr_r_r_nac
hexagon_S2_asr_r_r_or
hexagon_S2_asr_r_r_sat
hexagon_S2_asr_r_svw_trun
hexagon_S2_asr_r_vh
hexagon_S2_asr_r_vw
hexagon_S2_brev
hexagon_S2_brevp
hexagon_S2_cl0
hexagon_S2_cl0p
hexagon_S2_cl1
hexagon_S2_cl1p
hexagon_S2_clb
hexagon_S2_clbnorm
hexagon_S2_clbp
hexagon_S2_clrbit_i
hexagon_S2_clrbit_r
hexagon_S2_ct0
hexagon_S2_ct0p
hexagon_S2_ct1
hexagon_S2_ct1p
hexagon_S2_deinterleave
hexagon_S2_extractu
hexagon_S2_extractu_rp
hexagon_S2_extractup
hexagon_S2_extractup_rp
hexagon_S2_insert
hexagon_S2_insert_rp
hexagon_S2_insertp
hexagon_S2_insertp_rp
hexagon_S2_interleave
hexagon_S2_lfsp
hexagon_S2_lsl_r_p
hexagon_S2_lsl_r_p_acc
hexagon_S2_lsl_r_p_and
hexagon_S2_lsl_r_p_nac
hexagon_S2_lsl_r_p_or
hexagon_S2_lsl_r_p_xor
hexagon_S2_lsl_r_r
hexagon_S2_lsl_r_r_acc
hexagon_S2_lsl_r_r_and
hexagon_S2_lsl_r_r_nac
hexagon_S2_lsl_r_r_or
hexagon_S2_lsl_r_vh
hexagon_S2_lsl_r_vw
hexagon_S2_lsr_i_p
hexagon_S2_lsr_i_p_acc
hexagon_S2_lsr_i_p_and
hexagon_S2_lsr_i_p_nac
hexagon_S2_lsr_i_p_or
hexagon_S2_lsr_i_p_xacc
hexagon_S2_lsr_i_r
hexagon_S2_lsr_i_r_acc
hexagon_S2_lsr_i_r_and
hexagon_S2_lsr_i_r_nac
hexagon_S2_lsr_i_r_or
hexagon_S2_lsr_i_r_xacc
hexagon_S2_lsr_i_vh
hexagon_S2_lsr_i_vw
hexagon_S2_lsr_r_p
hexagon_S2_lsr_r_p_acc
hexagon_S2_lsr_r_p_and
hexagon_S2_lsr_r_p_nac
hexagon_S2_lsr_r_p_or
hexagon_S2_lsr_r_p_xor
hexagon_S2_lsr_r_r
hexagon_S2_lsr_r_r_acc
hexagon_S2_lsr_r_r_and
hexagon_S2_lsr_r_r_nac
hexagon_S2_lsr_r_r_or
hexagon_S2_lsr_r_vh
hexagon_S2_lsr_r_vw
hexagon_S2_mask
hexagon_S2_packhl
hexagon_S2_parityp
hexagon_S2_setbit_i
hexagon_S2_setbit_r
hexagon_S2_shuffeb
hexagon_S2_shuffeh
hexagon_S2_shuffob
hexagon_S2_shuffoh
hexagon_S2_storerb_pbr
hexagon_S2_storerb_pci
hexagon_S2_storerb_pcr
hexagon_S2_storerd_pbr
hexagon_S2_storerd_pci
hexagon_S2_storerd_pcr
hexagon_S2_storerf_pbr
hexagon_S2_storerf_pci
hexagon_S2_storerf_pcr
hexagon_S2_storerh_pbr
hexagon_S2_storerh_pci
hexagon_S2_storerh_pcr
hexagon_S2_storeri_pbr
hexagon_S2_storeri_pci
hexagon_S2_storeri_pcr
hexagon_S2_storew_locked
hexagon_S2_svsathb
hexagon_S2_svsathub
hexagon_S2_tableidxb_goodsyntax
hexagon_S2_tableidxd_goodsyntax
hexagon_S2_tableidxh_goodsyntax
hexagon_S2_tableidxw_goodsyntax
hexagon_S2_togglebit_i
hexagon_S2_togglebit_r
hexagon_S2_tstbit_i
hexagon_S2_tstbit_r
hexagon_S2_valignib
hexagon_S2_valignrb
hexagon_S2_vcnegh
hexagon_S2_vcrotate
hexagon_S2_vrcnegh
hexagon_S2_vrndpackwh
hexagon_S2_vrndpackwhs
hexagon_S2_vsathb
hexagon_S2_vsathb_nopack
hexagon_S2_vsathub
hexagon_S2_vsathub_nopack
hexagon_S2_vsatwh
hexagon_S2_vsatwh_nopack
hexagon_S2_vsatwuh
hexagon_S2_vsatwuh_nopack
hexagon_S2_vsplatrb
hexagon_S2_vsplatrh
hexagon_S2_vspliceib
hexagon_S2_vsplicerb
hexagon_S2_vsxtbh
hexagon_S2_vsxthw
hexagon_S2_vtrunehb
hexagon_S2_vtrunewh
hexagon_S2_vtrunohb
hexagon_S2_vtrunowh
hexagon_S2_vzxtbh
hexagon_S2_vzxthw
hexagon_S4_addaddi
hexagon_S4_addi_asl_ri
hexagon_S4_addi_lsr_ri
hexagon_S4_andi_asl_ri
hexagon_S4_andi_lsr_ri
hexagon_S4_clbaddi
hexagon_S4_clbpaddi
hexagon_S4_clbpnorm
hexagon_S4_extract
hexagon_S4_extract_rp
hexagon_S4_extractp
hexagon_S4_extractp_rp
hexagon_S4_lsli
hexagon_S4_ntstbit_i
hexagon_S4_ntstbit_r
hexagon_S4_or_andi
hexagon_S4_or_andix
hexagon_S4_or_ori
hexagon_S4_ori_asl_ri
hexagon_S4_ori_lsr_ri
hexagon_S4_parity
hexagon_S4_stored_locked
hexagon_S4_subaddi
hexagon_S4_subi_asl_ri
hexagon_S4_subi_lsr_ri
hexagon_S4_vrcrotate
hexagon_S4_vrcrotate_acc
hexagon_S4_vxaddsubh
hexagon_S4_vxaddsubhr
hexagon_S4_vxaddsubw
hexagon_S4_vxsubaddh
hexagon_S4_vxsubaddhr
hexagon_S4_vxsubaddw
hexagon_S5_asrhub_rnd_sat_goodsyntax
hexagon_S5_asrhub_sat
hexagon_S5_popcountp
hexagon_S5_vasrhrnd_goodsyntax
hexagon_S6_rol_i_p
hexagon_S6_rol_i_p_acc
hexagon_S6_rol_i_p_and
hexagon_S6_rol_i_p_nac
hexagon_S6_rol_i_p_or
hexagon_S6_rol_i_p_xacc
hexagon_S6_rol_i_r
hexagon_S6_rol_i_r_acc
hexagon_S6_rol_i_r_and
hexagon_S6_rol_i_r_nac
hexagon_S6_rol_i_r_or
hexagon_S6_rol_i_r_xacc
hexagon_S6_vsplatrbp
hexagon_S6_vtrunehb_ppp
hexagon_S6_vtrunohb_ppp
hexagon_V6_extractw
hexagon_V6_extractw_128B
hexagon_V6_hi
hexagon_V6_hi_128B
hexagon_V6_ld0
hexagon_V6_ld0_128B
hexagon_V6_ldcnp0
hexagon_V6_ldcnp0_128B
hexagon_V6_ldcnpnt0
hexagon_V6_ldcnpnt0_128B
hexagon_V6_ldcp0
hexagon_V6_ldcp0_128B
hexagon_V6_ldcpnt0
hexagon_V6_ldcpnt0_128B
hexagon_V6_ldnp0
hexagon_V6_ldnp0_128B
hexagon_V6_ldnpnt0
hexagon_V6_ldnpnt0_128B
hexagon_V6_ldnt0
hexagon_V6_ldnt0_128B
hexagon_V6_ldntnt0
hexagon_V6_ldp0
hexagon_V6_ldp0_128B
hexagon_V6_ldpnt0
hexagon_V6_ldpnt0_128B
hexagon_V6_ldtnp0
hexagon_V6_ldtnp0_128B
hexagon_V6_ldtnpnt0
hexagon_V6_ldtnpnt0_128B
hexagon_V6_ldtp0
hexagon_V6_ldtp0_128B
hexagon_V6_ldtpnt0
hexagon_V6_ldtpnt0_128B
hexagon_V6_ldu0
hexagon_V6_ldu0_128B
hexagon_V6_lo
hexagon_V6_lo_128B
hexagon_V6_lvsplatb
hexagon_V6_lvsplatb_128B
hexagon_V6_lvsplath
hexagon_V6_lvsplath_128B
hexagon_V6_lvsplatw
hexagon_V6_lvsplatw_128B
hexagon_V6_pred_and
hexagon_V6_pred_and_128B
hexagon_V6_pred_and_n
hexagon_V6_pred_and_n_128B
hexagon_V6_pred_not
hexagon_V6_pred_not_128B
hexagon_V6_pred_or
hexagon_V6_pred_or_128B
hexagon_V6_pred_or_n
hexagon_V6_pred_or_n_128B
hexagon_V6_pred_scalar2
hexagon_V6_pred_scalar2_128B
hexagon_V6_pred_scalar2v2
hexagon_V6_pred_scalar2v2_128B
hexagon_V6_pred_xor
hexagon_V6_pred_xor_128B
hexagon_V6_shuffeqh
hexagon_V6_shuffeqh_128B
hexagon_V6_shuffeqw
hexagon_V6_shuffeqw_128B
hexagon_V6_vS32b_nqpred_ai
hexagon_V6_vS32b_nqpred_ai_128B
hexagon_V6_vS32b_nt_nqpred_ai
hexagon_V6_vS32b_nt_nqpred_ai_128B
hexagon_V6_vS32b_nt_qpred_ai
hexagon_V6_vS32b_nt_qpred_ai_128B
hexagon_V6_vS32b_qpred_ai
hexagon_V6_vS32b_qpred_ai_128B
hexagon_V6_vabsb
hexagon_V6_vabsb_128B
hexagon_V6_vabsb_sat
hexagon_V6_vabsb_sat_128B
hexagon_V6_vabsdiffh
hexagon_V6_vabsdiffh_128B
hexagon_V6_vabsdiffub
hexagon_V6_vabsdiffub_128B
hexagon_V6_vabsdiffuh
hexagon_V6_vabsdiffuh_128B
hexagon_V6_vabsdiffw
hexagon_V6_vabsdiffw_128B
hexagon_V6_vabsh
hexagon_V6_vabsh_128B
hexagon_V6_vabsh_sat
hexagon_V6_vabsh_sat_128B
hexagon_V6_vabsw
hexagon_V6_vabsw_128B
hexagon_V6_vabsw_sat
hexagon_V6_vabsw_sat_128B
hexagon_V6_vaddb
hexagon_V6_vaddb_128B
hexagon_V6_vaddb_dv
hexagon_V6_vaddb_dv_128B
hexagon_V6_vaddbnq
hexagon_V6_vaddbnq_128B
hexagon_V6_vaddbq
hexagon_V6_vaddbq_128B
hexagon_V6_vaddbsat
hexagon_V6_vaddbsat_128B
hexagon_V6_vaddbsat_dv
hexagon_V6_vaddbsat_dv_128B
hexagon_V6_vaddcarry
hexagon_V6_vaddcarry_128B
hexagon_V6_vaddcarrysat
hexagon_V6_vaddcarrysat_128B
hexagon_V6_vaddclbh
hexagon_V6_vaddclbh_128B
hexagon_V6_vaddclbw
hexagon_V6_vaddclbw_128B
hexagon_V6_vaddh
hexagon_V6_vaddh_128B
hexagon_V6_vaddh_dv
hexagon_V6_vaddh_dv_128B
hexagon_V6_vaddhnq
hexagon_V6_vaddhnq_128B
hexagon_V6_vaddhq
hexagon_V6_vaddhq_128B
hexagon_V6_vaddhsat
hexagon_V6_vaddhsat_128B
hexagon_V6_vaddhsat_dv
hexagon_V6_vaddhsat_dv_128B
hexagon_V6_vaddhw
hexagon_V6_vaddhw_128B
hexagon_V6_vaddhw_acc
hexagon_V6_vaddhw_acc_128B
hexagon_V6_vaddubh
hexagon_V6_vaddubh_128B
hexagon_V6_vaddubh_acc
hexagon_V6_vaddubh_acc_128B
hexagon_V6_vaddubsat
hexagon_V6_vaddubsat_128B
hexagon_V6_vaddubsat_dv
hexagon_V6_vaddubsat_dv_128B
hexagon_V6_vaddububb_sat
hexagon_V6_vaddububb_sat_128B
hexagon_V6_vadduhsat
hexagon_V6_vadduhsat_128B
hexagon_V6_vadduhsat_dv
hexagon_V6_vadduhsat_dv_128B
hexagon_V6_vadduhw
hexagon_V6_vadduhw_128B
hexagon_V6_vadduhw_acc
hexagon_V6_vadduhw_acc_128B
hexagon_V6_vadduwsat
hexagon_V6_vadduwsat_128B
hexagon_V6_vadduwsat_dv
hexagon_V6_vadduwsat_dv_128B
hexagon_V6_vaddw
hexagon_V6_vaddw_128B
hexagon_V6_vaddw_dv
hexagon_V6_vaddw_dv_128B
hexagon_V6_vaddwnq
hexagon_V6_vaddwnq_128B
hexagon_V6_vaddwq
hexagon_V6_vaddwq_128B
hexagon_V6_vaddwsat
hexagon_V6_vaddwsat_128B
hexagon_V6_vaddwsat_dv
hexagon_V6_vaddwsat_dv_128B
hexagon_V6_valignb
hexagon_V6_valignb_128B
hexagon_V6_valignbi
hexagon_V6_valignbi_128B
hexagon_V6_vand
hexagon_V6_vand_128B
hexagon_V6_vandnqrt
hexagon_V6_vandnqrt_128B
hexagon_V6_vandnqrt_acc
hexagon_V6_vandnqrt_acc_128B
hexagon_V6_vandqrt
hexagon_V6_vandqrt_128B
hexagon_V6_vandqrt_acc
hexagon_V6_vandqrt_acc_128B
hexagon_V6_vandvnqv
hexagon_V6_vandvnqv_128B
hexagon_V6_vandvqv
hexagon_V6_vandvqv_128B
hexagon_V6_vandvrt
hexagon_V6_vandvrt_128B
hexagon_V6_vandvrt_acc
hexagon_V6_vandvrt_acc_128B
hexagon_V6_vaslh
hexagon_V6_vaslh_128B
hexagon_V6_vaslh_acc
hexagon_V6_vaslh_acc_128B
hexagon_V6_vaslhv
hexagon_V6_vaslhv_128B
hexagon_V6_vaslw
hexagon_V6_vaslw_128B
hexagon_V6_vaslw_acc
hexagon_V6_vaslw_acc_128B
hexagon_V6_vaslwv
hexagon_V6_vaslwv_128B
hexagon_V6_vasr_into
hexagon_V6_vasr_into_128B
hexagon_V6_vasrh
hexagon_V6_vasrh_128B
hexagon_V6_vasrh_acc
hexagon_V6_vasrh_acc_128B
hexagon_V6_vasrhbrndsat
hexagon_V6_vasrhbrndsat_128B
hexagon_V6_vasrhbsat
hexagon_V6_vasrhbsat_128B
hexagon_V6_vasrhubrndsat
hexagon_V6_vasrhubrndsat_128B
hexagon_V6_vasrhubsat
hexagon_V6_vasrhubsat_128B
hexagon_V6_vasrhv
hexagon_V6_vasrhv_128B
hexagon_V6_vasruhubrndsat
hexagon_V6_vasruhubrndsat_128B
hexagon_V6_vasruhubsat
hexagon_V6_vasruhubsat_128B
hexagon_V6_vasruwuhrndsat
hexagon_V6_vasruwuhrndsat_128B
hexagon_V6_vasruwuhsat
hexagon_V6_vasruwuhsat_128B
hexagon_V6_vasrw
hexagon_V6_vasrw_128B
hexagon_V6_vasrw_acc
hexagon_V6_vasrw_acc_128B
hexagon_V6_vasrwh
hexagon_V6_vasrwh_128B
hexagon_V6_vasrwhrndsat
hexagon_V6_vasrwhrndsat_128B
hexagon_V6_vasrwhsat
hexagon_V6_vasrwhsat_128B
hexagon_V6_vasrwuhrndsat
hexagon_V6_vasrwuhrndsat_128B
hexagon_V6_vasrwuhsat
hexagon_V6_vasrwuhsat_128B
hexagon_V6_vasrwv
hexagon_V6_vasrwv_128B
hexagon_V6_vassign
hexagon_V6_vassign_128B
hexagon_V6_vassignp
hexagon_V6_vassignp_128B
hexagon_V6_vavgb
hexagon_V6_vavgb_128B
hexagon_V6_vavgbrnd
hexagon_V6_vavgbrnd_128B
hexagon_V6_vavgh
hexagon_V6_vavgh_128B
hexagon_V6_vavghrnd
hexagon_V6_vavghrnd_128B
hexagon_V6_vavgub
hexagon_V6_vavgub_128B
hexagon_V6_vavgubrnd
hexagon_V6_vavgubrnd_128B
hexagon_V6_vavguh
hexagon_V6_vavguh_128B
hexagon_V6_vavguhrnd
hexagon_V6_vavguhrnd_128B
hexagon_V6_vavguw
hexagon_V6_vavguw_128B
hexagon_V6_vavguwrnd
hexagon_V6_vavguwrnd_128B
hexagon_V6_vavgw
hexagon_V6_vavgw_128B
hexagon_V6_vavgwrnd
hexagon_V6_vavgwrnd_128B
hexagon_V6_vcl0h
hexagon_V6_vcl0h_128B
hexagon_V6_vcl0w
hexagon_V6_vcl0w_128B
hexagon_V6_vcombine
hexagon_V6_vcombine_128B
hexagon_V6_vd0
hexagon_V6_vd0_128B
hexagon_V6_vdd0
hexagon_V6_vdd0_128B
hexagon_V6_vdealb
hexagon_V6_vdealb_128B
hexagon_V6_vdealb4w
hexagon_V6_vdealb4w_128B
hexagon_V6_vdealh
hexagon_V6_vdealh_128B
hexagon_V6_vdealvdd
hexagon_V6_vdealvdd_128B
hexagon_V6_vdelta
hexagon_V6_vdelta_128B
hexagon_V6_vdmpybus
hexagon_V6_vdmpybus_128B
hexagon_V6_vdmpybus_acc
hexagon_V6_vdmpybus_acc_128B
hexagon_V6_vdmpybus_dv
hexagon_V6_vdmpybus_dv_128B
hexagon_V6_vdmpybus_dv_acc
hexagon_V6_vdmpybus_dv_acc_128B
hexagon_V6_vdmpyhb
hexagon_V6_vdmpyhb_128B
hexagon_V6_vdmpyhb_acc
hexagon_V6_vdmpyhb_acc_128B
hexagon_V6_vdmpyhb_dv
hexagon_V6_vdmpyhb_dv_128B
hexagon_V6_vdmpyhb_dv_acc
hexagon_V6_vdmpyhb_dv_acc_128B
hexagon_V6_vdmpyhisat
hexagon_V6_vdmpyhisat_128B
hexagon_V6_vdmpyhisat_acc
hexagon_V6_vdmpyhisat_acc_128B
hexagon_V6_vdmpyhsat
hexagon_V6_vdmpyhsat_128B
hexagon_V6_vdmpyhsat_acc
hexagon_V6_vdmpyhsat_acc_128B
hexagon_V6_vdmpyhsuisat
hexagon_V6_vdmpyhsuisat_128B
hexagon_V6_vdmpyhsuisat_acc
hexagon_V6_vdmpyhsuisat_acc_128B
hexagon_V6_vdmpyhsusat
hexagon_V6_vdmpyhsusat_128B
hexagon_V6_vdmpyhsusat_acc
hexagon_V6_vdmpyhsusat_acc_128B
hexagon_V6_vdmpyhvsat
hexagon_V6_vdmpyhvsat_128B
hexagon_V6_vdmpyhvsat_acc
hexagon_V6_vdmpyhvsat_acc_128B
hexagon_V6_vdsaduh
hexagon_V6_vdsaduh_128B
hexagon_V6_vdsaduh_acc
hexagon_V6_vdsaduh_acc_128B
hexagon_V6_veqb
hexagon_V6_veqb_128B
hexagon_V6_veqb_and
hexagon_V6_veqb_and_128B
hexagon_V6_veqb_or
hexagon_V6_veqb_or_128B
hexagon_V6_veqb_xor
hexagon_V6_veqb_xor_128B
hexagon_V6_veqh
hexagon_V6_veqh_128B
hexagon_V6_veqh_and
hexagon_V6_veqh_and_128B
hexagon_V6_veqh_or
hexagon_V6_veqh_or_128B
hexagon_V6_veqh_xor
hexagon_V6_veqh_xor_128B
hexagon_V6_veqw
hexagon_V6_veqw_128B
hexagon_V6_veqw_and
hexagon_V6_veqw_and_128B
hexagon_V6_veqw_or
hexagon_V6_veqw_or_128B
hexagon_V6_veqw_xor
hexagon_V6_veqw_xor_128B
hexagon_V6_vgathermh
hexagon_V6_vgathermh_128B
hexagon_V6_vgathermhq
hexagon_V6_vgathermhq_128B
hexagon_V6_vgathermhw
hexagon_V6_vgathermhw_128B
hexagon_V6_vgathermhwq
hexagon_V6_vgathermhwq_128B
hexagon_V6_vgathermw
hexagon_V6_vgathermw_128B
hexagon_V6_vgathermwq
hexagon_V6_vgathermwq_128B
hexagon_V6_vgtb
hexagon_V6_vgtb_128B
hexagon_V6_vgtb_and
hexagon_V6_vgtb_and_128B
hexagon_V6_vgtb_or
hexagon_V6_vgtb_or_128B
hexagon_V6_vgtb_xor
hexagon_V6_vgtb_xor_128B
hexagon_V6_vgth
hexagon_V6_vgth_128B
hexagon_V6_vgth_and
hexagon_V6_vgth_and_128B
hexagon_V6_vgth_or
hexagon_V6_vgth_or_128B
hexagon_V6_vgth_xor
hexagon_V6_vgth_xor_128B
hexagon_V6_vgtub
hexagon_V6_vgtub_128B
hexagon_V6_vgtub_and
hexagon_V6_vgtub_and_128B
hexagon_V6_vgtub_or
hexagon_V6_vgtub_or_128B
hexagon_V6_vgtub_xor
hexagon_V6_vgtub_xor_128B
hexagon_V6_vgtuh
hexagon_V6_vgtuh_128B
hexagon_V6_vgtuh_and
hexagon_V6_vgtuh_and_128B
hexagon_V6_vgtuh_or
hexagon_V6_vgtuh_or_128B
hexagon_V6_vgtuh_xor
hexagon_V6_vgtuh_xor_128B
hexagon_V6_vgtuw
hexagon_V6_vgtuw_128B
hexagon_V6_vgtuw_and
hexagon_V6_vgtuw_and_128B
hexagon_V6_vgtuw_or
hexagon_V6_vgtuw_or_128B
hexagon_V6_vgtuw_xor
hexagon_V6_vgtuw_xor_128B
hexagon_V6_vgtw
hexagon_V6_vgtw_128B
hexagon_V6_vgtw_and
hexagon_V6_vgtw_and_128B
hexagon_V6_vgtw_or
hexagon_V6_vgtw_or_128B
hexagon_V6_vgtw_xor
hexagon_V6_vgtw_xor_128B
hexagon_V6_vinsertwr
hexagon_V6_vinsertwr_128B
hexagon_V6_vlalignb
hexagon_V6_vlalignb_128B
hexagon_V6_vlalignbi
hexagon_V6_vlalignbi_128B
hexagon_V6_vlsrb
hexagon_V6_vlsrb_128B
hexagon_V6_vlsrh
hexagon_V6_vlsrh_128B
hexagon_V6_vlsrhv
hexagon_V6_vlsrhv_128B
hexagon_V6_vlsrw
hexagon_V6_vlsrw_128B
hexagon_V6_vlsrwv
hexagon_V6_vlsrwv_128B
hexagon_V6_vlut4
hexagon_V6_vlut4_128B
hexagon_V6_vlutvvb
hexagon_V6_vlutvvb_128B
hexagon_V6_vlutvvb_nm
hexagon_V6_vlutvvb_nm_128B
hexagon_V6_vlutvvb_oracc
hexagon_V6_vlutvvb_oracc_128B
hexagon_V6_vlutvvb_oracci
hexagon_V6_vlutvvb_oracci_128B
hexagon_V6_vlutvvbi
hexagon_V6_vlutvvbi_128B
hexagon_V6_vlutvwh
hexagon_V6_vlutvwh_128B
hexagon_V6_vlutvwh_nm
hexagon_V6_vlutvwh_nm_128B
hexagon_V6_vlutvwh_oracc
hexagon_V6_vlutvwh_oracc_128B
hexagon_V6_vlutvwh_oracci
hexagon_V6_vlutvwh_oracci_128B
hexagon_V6_vlutvwhi
hexagon_V6_vlutvwhi_128B
hexagon_V6_vmaskedstorenq
hexagon_V6_vmaskedstorenq_128B
hexagon_V6_vmaskedstorentnq
hexagon_V6_vmaskedstorentnq_128B
hexagon_V6_vmaskedstorentq
hexagon_V6_vmaskedstorentq_128B
hexagon_V6_vmaskedstoreq
hexagon_V6_vmaskedstoreq_128B
hexagon_V6_vmaxb
hexagon_V6_vmaxb_128B
hexagon_V6_vmaxh
hexagon_V6_vmaxh_128B
hexagon_V6_vmaxub
hexagon_V6_vmaxub_128B
hexagon_V6_vmaxuh
hexagon_V6_vmaxuh_128B
hexagon_V6_vmaxw
hexagon_V6_vmaxw_128B
hexagon_V6_vminb
hexagon_V6_vminb_128B
hexagon_V6_vminh
hexagon_V6_vminh_128B
hexagon_V6_vminub
hexagon_V6_vminub_128B
hexagon_V6_vminuh
hexagon_V6_vminuh_128B
hexagon_V6_vminw
hexagon_V6_vminw_128B
hexagon_V6_vmpabus
hexagon_V6_vmpabus_128B
hexagon_V6_vmpabus_acc
hexagon_V6_vmpabus_acc_128B
hexagon_V6_vmpabusv
hexagon_V6_vmpabusv_128B
hexagon_V6_vmpabuu
hexagon_V6_vmpabuu_128B
hexagon_V6_vmpabuu_acc
hexagon_V6_vmpabuu_acc_128B
hexagon_V6_vmpabuuv
hexagon_V6_vmpabuuv_128B
hexagon_V6_vmpahb
hexagon_V6_vmpahb_128B
hexagon_V6_vmpahb_acc
hexagon_V6_vmpahb_acc_128B
hexagon_V6_vmpahhsat
hexagon_V6_vmpahhsat_128B
hexagon_V6_vmpauhb
hexagon_V6_vmpauhb_128B
hexagon_V6_vmpauhb_acc
hexagon_V6_vmpauhb_acc_128B
hexagon_V6_vmpauhuhsat
hexagon_V6_vmpauhuhsat_128B
hexagon_V6_vmpsuhuhsat
hexagon_V6_vmpsuhuhsat_128B
hexagon_V6_vmpybus
hexagon_V6_vmpybus_128B
hexagon_V6_vmpybus_acc
hexagon_V6_vmpybus_acc_128B
hexagon_V6_vmpybusv
hexagon_V6_vmpybusv_128B
hexagon_V6_vmpybusv_acc
hexagon_V6_vmpybusv_acc_128B
hexagon_V6_vmpybv
hexagon_V6_vmpybv_128B
hexagon_V6_vmpybv_acc
hexagon_V6_vmpybv_acc_128B
hexagon_V6_vmpyewuh
hexagon_V6_vmpyewuh_128B
hexagon_V6_vmpyewuh_64
hexagon_V6_vmpyewuh_64_128B
hexagon_V6_vmpyh
hexagon_V6_vmpyh_128B
hexagon_V6_vmpyh_acc
hexagon_V6_vmpyh_acc_128B
hexagon_V6_vmpyhsat_acc
hexagon_V6_vmpyhsat_acc_128B
hexagon_V6_vmpyhsrs
hexagon_V6_vmpyhsrs_128B
hexagon_V6_vmpyhss
hexagon_V6_vmpyhss_128B
hexagon_V6_vmpyhus
hexagon_V6_vmpyhus_128B
hexagon_V6_vmpyhus_acc
hexagon_V6_vmpyhus_acc_128B
hexagon_V6_vmpyhv
hexagon_V6_vmpyhv_128B
hexagon_V6_vmpyhv_acc
hexagon_V6_vmpyhv_acc_128B
hexagon_V6_vmpyhvsrs
hexagon_V6_vmpyhvsrs_128B
hexagon_V6_vmpyieoh
hexagon_V6_vmpyieoh_128B
hexagon_V6_vmpyiewh_acc
hexagon_V6_vmpyiewh_acc_128B
hexagon_V6_vmpyiewuh
hexagon_V6_vmpyiewuh_128B
hexagon_V6_vmpyiewuh_acc
hexagon_V6_vmpyiewuh_acc_128B
hexagon_V6_vmpyih
hexagon_V6_vmpyih_128B
hexagon_V6_vmpyih_acc
hexagon_V6_vmpyih_acc_128B
hexagon_V6_vmpyihb
hexagon_V6_vmpyihb_128B
hexagon_V6_vmpyihb_acc
hexagon_V6_vmpyihb_acc_128B
hexagon_V6_vmpyiowh
hexagon_V6_vmpyiowh_128B
hexagon_V6_vmpyiwb
hexagon_V6_vmpyiwb_128B
hexagon_V6_vmpyiwb_acc
hexagon_V6_vmpyiwb_acc_128B
hexagon_V6_vmpyiwh
hexagon_V6_vmpyiwh_128B
hexagon_V6_vmpyiwh_acc
hexagon_V6_vmpyiwh_acc_128B
hexagon_V6_vmpyiwub
hexagon_V6_vmpyiwub_128B
hexagon_V6_vmpyiwub_acc
hexagon_V6_vmpyiwub_acc_128B
hexagon_V6_vmpyowh
hexagon_V6_vmpyowh_128B
hexagon_V6_vmpyowh_64_acc
hexagon_V6_vmpyowh_64_acc_128B
hexagon_V6_vmpyowh_rnd
hexagon_V6_vmpyowh_rnd_128B
hexagon_V6_vmpyowh_rnd_sacc
hexagon_V6_vmpyowh_rnd_sacc_128B
hexagon_V6_vmpyowh_sacc
hexagon_V6_vmpyowh_sacc_128B
hexagon_V6_vmpyub
hexagon_V6_vmpyub_128B
hexagon_V6_vmpyub_acc
hexagon_V6_vmpyub_acc_128B
hexagon_V6_vmpyubv
hexagon_V6_vmpyubv_128B
hexagon_V6_vmpyubv_acc
hexagon_V6_vmpyubv_acc_128B
hexagon_V6_vmpyuh
hexagon_V6_vmpyuh_128B
hexagon_V6_vmpyuh_acc
hexagon_V6_vmpyuh_acc_128B
hexagon_V6_vmpyuhe
hexagon_V6_vmpyuhe_128B
hexagon_V6_vmpyuhe_acc
hexagon_V6_vmpyuhe_acc_128B
hexagon_V6_vmpyuhv
hexagon_V6_vmpyuhv_128B
hexagon_V6_vmpyuhv_acc
hexagon_V6_vmpyuhv_acc_128B
hexagon_V6_vmux
hexagon_V6_vmux_128B
hexagon_V6_vnavgb
hexagon_V6_vnavgb_128B
hexagon_V6_vnavgh
hexagon_V6_vnavgh_128B
hexagon_V6_vnavgub
hexagon_V6_vnavgub_128B
hexagon_V6_vnavgw
hexagon_V6_vnavgw_128B
hexagon_V6_vnormamth
hexagon_V6_vnormamth_128B
hexagon_V6_vnormamtw
hexagon_V6_vnormamtw_128B
hexagon_V6_vnot
hexagon_V6_vnot_128B
hexagon_V6_vor
hexagon_V6_vor_128B
hexagon_V6_vpackeb
hexagon_V6_vpackeb_128B
hexagon_V6_vpackeh
hexagon_V6_vpackeh_128B
hexagon_V6_vpackhb_sat
hexagon_V6_vpackhb_sat_128B
hexagon_V6_vpackhub_sat
hexagon_V6_vpackhub_sat_128B
hexagon_V6_vpackob
hexagon_V6_vpackob_128B
hexagon_V6_vpackoh
hexagon_V6_vpackoh_128B
hexagon_V6_vpackwh_sat
hexagon_V6_vpackwh_sat_128B
hexagon_V6_vpackwuh_sat
hexagon_V6_vpackwuh_sat_128B
hexagon_V6_vpopcounth
hexagon_V6_vpopcounth_128B
hexagon_V6_vprefixqb
hexagon_V6_vprefixqb_128B
hexagon_V6_vprefixqh
hexagon_V6_vprefixqh_128B
hexagon_V6_vprefixqw
hexagon_V6_vprefixqw_128B
hexagon_V6_vrdelta
hexagon_V6_vrdelta_128B
hexagon_V6_vrmpybub_rtt
hexagon_V6_vrmpybub_rtt_128B
hexagon_V6_vrmpybub_rtt_acc
hexagon_V6_vrmpybub_rtt_acc_128B
hexagon_V6_vrmpybus
hexagon_V6_vrmpybus_128B
hexagon_V6_vrmpybus_acc
hexagon_V6_vrmpybus_acc_128B
hexagon_V6_vrmpybusi
hexagon_V6_vrmpybusi_128B
hexagon_V6_vrmpybusi_acc
hexagon_V6_vrmpybusi_acc_128B
hexagon_V6_vrmpybusv
hexagon_V6_vrmpybusv_128B
hexagon_V6_vrmpybusv_acc
hexagon_V6_vrmpybusv_acc_128B
hexagon_V6_vrmpybv
hexagon_V6_vrmpybv_128B
hexagon_V6_vrmpybv_acc
hexagon_V6_vrmpybv_acc_128B
hexagon_V6_vrmpyub
hexagon_V6_vrmpyub_128B
hexagon_V6_vrmpyub_acc
hexagon_V6_vrmpyub_acc_128B
hexagon_V6_vrmpyub_rtt
hexagon_V6_vrmpyub_rtt_128B
hexagon_V6_vrmpyub_rtt_acc
hexagon_V6_vrmpyub_rtt_acc_128B
hexagon_V6_vrmpyubi
hexagon_V6_vrmpyubi_128B
hexagon_V6_vrmpyubi_acc
hexagon_V6_vrmpyubi_acc_128B
hexagon_V6_vrmpyubv
hexagon_V6_vrmpyubv_128B
hexagon_V6_vrmpyubv_acc
hexagon_V6_vrmpyubv_acc_128B
hexagon_V6_vror
hexagon_V6_vror_128B
hexagon_V6_vrotr
hexagon_V6_vrotr_128B
hexagon_V6_vroundhb
hexagon_V6_vroundhb_128B
hexagon_V6_vroundhub
hexagon_V6_vroundhub_128B
hexagon_V6_vrounduhub
hexagon_V6_vrounduhub_128B
hexagon_V6_vrounduwuh
hexagon_V6_vrounduwuh_128B
hexagon_V6_vroundwh
hexagon_V6_vroundwh_128B
hexagon_V6_vroundwuh
hexagon_V6_vroundwuh_128B
hexagon_V6_vrsadubi
hexagon_V6_vrsadubi_128B
hexagon_V6_vrsadubi_acc
hexagon_V6_vrsadubi_acc_128B
hexagon_V6_vsatdw
hexagon_V6_vsatdw_128B
hexagon_V6_vsathub
hexagon_V6_vsathub_128B
hexagon_V6_vsatuwuh
hexagon_V6_vsatuwuh_128B
hexagon_V6_vsatwh
hexagon_V6_vsatwh_128B
hexagon_V6_vsb
hexagon_V6_vsb_128B
hexagon_V6_vscattermh
hexagon_V6_vscattermh_128B
hexagon_V6_vscattermh_add
hexagon_V6_vscattermh_add_128B
hexagon_V6_vscattermhq
hexagon_V6_vscattermhq_128B
hexagon_V6_vscattermhw
hexagon_V6_vscattermhw_128B
hexagon_V6_vscattermhw_add
hexagon_V6_vscattermhw_add_128B
hexagon_V6_vscattermhwq
hexagon_V6_vscattermhwq_128B
hexagon_V6_vscattermw
hexagon_V6_vscattermw_128B
hexagon_V6_vscattermw_add
hexagon_V6_vscattermw_add_128B
hexagon_V6_vscattermwq
hexagon_V6_vscattermwq_128B
hexagon_V6_vsh
hexagon_V6_vsh_128B
hexagon_V6_vshufeh
hexagon_V6_vshufeh_128B
hexagon_V6_vshuffb
hexagon_V6_vshuffb_128B
hexagon_V6_vshuffeb
hexagon_V6_vshuffeb_128B
hexagon_V6_vshuffh
hexagon_V6_vshuffh_128B
hexagon_V6_vshuffob
hexagon_V6_vshuffob_128B
hexagon_V6_vshuffvdd
hexagon_V6_vshuffvdd_128B
hexagon_V6_vshufoeb
hexagon_V6_vshufoeb_128B
hexagon_V6_vshufoeh
hexagon_V6_vshufoeh_128B
hexagon_V6_vshufoh
hexagon_V6_vshufoh_128B
hexagon_V6_vsubb
hexagon_V6_vsubb_128B
hexagon_V6_vsubb_dv
hexagon_V6_vsubb_dv_128B
hexagon_V6_vsubbnq
hexagon_V6_vsubbnq_128B
hexagon_V6_vsubbq
hexagon_V6_vsubbq_128B
hexagon_V6_vsubbsat
hexagon_V6_vsubbsat_128B
hexagon_V6_vsubbsat_dv
hexagon_V6_vsubbsat_dv_128B
hexagon_V6_vsubcarry
hexagon_V6_vsubcarry_128B
hexagon_V6_vsubh
hexagon_V6_vsubh_128B
hexagon_V6_vsubh_dv
hexagon_V6_vsubh_dv_128B
hexagon_V6_vsubhnq
hexagon_V6_vsubhnq_128B
hexagon_V6_vsubhq
hexagon_V6_vsubhq_128B
hexagon_V6_vsubhsat
hexagon_V6_vsubhsat_128B
hexagon_V6_vsubhsat_dv
hexagon_V6_vsubhsat_dv_128B
hexagon_V6_vsubhw
hexagon_V6_vsubhw_128B
hexagon_V6_vsububh
hexagon_V6_vsububh_128B
hexagon_V6_vsububsat
hexagon_V6_vsububsat_128B
hexagon_V6_vsububsat_dv
hexagon_V6_vsububsat_dv_128B
hexagon_V6_vsubububb_sat
hexagon_V6_vsubububb_sat_128B
hexagon_V6_vsubuhsat
hexagon_V6_vsubuhsat_128B
hexagon_V6_vsubuhsat_dv
hexagon_V6_vsubuhsat_dv_128B
hexagon_V6_vsubuhw
hexagon_V6_vsubuhw_128B
hexagon_V6_vsubuwsat
hexagon_V6_vsubuwsat_128B
hexagon_V6_vsubuwsat_dv
hexagon_V6_vsubuwsat_dv_128B
hexagon_V6_vsubw
hexagon_V6_vsubw_128B
hexagon_V6_vsubw_dv
hexagon_V6_vsubw_dv_128B
hexagon_V6_vsubwnq
hexagon_V6_vsubwnq_128B
hexagon_V6_vsubwq
hexagon_V6_vsubwq_128B
hexagon_V6_vsubwsat
hexagon_V6_vsubwsat_128B
hexagon_V6_vsubwsat_dv
hexagon_V6_vsubwsat_dv_128B
hexagon_V6_vswap
hexagon_V6_vswap_128B
hexagon_V6_vtmpyb
hexagon_V6_vtmpyb_128B
hexagon_V6_vtmpyb_acc
hexagon_V6_vtmpyb_acc_128B
hexagon_V6_vtmpybus
hexagon_V6_vtmpybus_128B
hexagon_V6_vtmpybus_acc
hexagon_V6_vtmpybus_acc_128B
hexagon_V6_vtmpyhb
hexagon_V6_vtmpyhb_128B
hexagon_V6_vtmpyhb_acc
hexagon_V6_vtmpyhb_acc_128B
hexagon_V6_vtran2x2_map
hexagon_V6_vtran2x2_map_128B
hexagon_V6_vunpackb
hexagon_V6_vunpackb_128B
hexagon_V6_vunpackh
hexagon_V6_vunpackh_128B
hexagon_V6_vunpackob
hexagon_V6_vunpackob_128B
hexagon_V6_vunpackoh
hexagon_V6_vunpackoh_128B
hexagon_V6_vunpackub
hexagon_V6_vunpackub_128B
hexagon_V6_vunpackuh
hexagon_V6_vunpackuh_128B
hexagon_V6_vxor
hexagon_V6_vxor_128B
hexagon_V6_vzb
hexagon_V6_vzb_128B
hexagon_V6_vzh
hexagon_V6_vzh_128B
hexagon_Y2_dccleana
hexagon_Y2_dccleaninva
hexagon_Y2_dcinva
hexagon_Y2_dczeroa
hexagon_Y4_l2fetch
hexagon_Y5_l2fetch
hexagon_circ_ldb
hexagon_circ_ldd
hexagon_circ_ldh
hexagon_circ_ldub
hexagon_circ_lduh
hexagon_circ_ldw
hexagon_circ_stb
hexagon_circ_std
hexagon_circ_sth
hexagon_circ_sthhi
hexagon_circ_stw
hexagon_prefetch
hexagon_vmemcpy
hexagon_vmemset
mips_absq_s_ph
mips_absq_s_qb
mips_absq_s_w
mips_add_a_b
mips_add_a_d
mips_add_a_h
mips_add_a_w
mips_addq_ph
mips_addq_s_ph
mips_addq_s_w
mips_addqh_ph
mips_addqh_r_ph
mips_addqh_r_w
mips_addqh_w
mips_adds_a_b
mips_adds_a_d
mips_adds_a_h
mips_adds_a_w
mips_adds_s_b
mips_adds_s_d
mips_adds_s_h
mips_adds_s_w
mips_adds_u_b
mips_adds_u_d
mips_adds_u_h
mips_adds_u_w
mips_addsc
mips_addu_ph
mips_addu_qb
mips_addu_s_ph
mips_addu_s_qb
mips_adduh_qb
mips_adduh_r_qb
mips_addv_b
mips_addv_d
mips_addv_h
mips_addv_w
mips_addvi_b
mips_addvi_d
mips_addvi_h
mips_addvi_w
mips_addwc
mips_and_v
mips_andi_b
mips_append
mips_asub_s_b
mips_asub_s_d
mips_asub_s_h
mips_asub_s_w
mips_asub_u_b
mips_asub_u_d
mips_asub_u_h
mips_asub_u_w
mips_ave_s_b
mips_ave_s_d
mips_ave_s_h
mips_ave_s_w
mips_ave_u_b
mips_ave_u_d
mips_ave_u_h
mips_ave_u_w
mips_aver_s_b
mips_aver_s_d
mips_aver_s_h
mips_aver_s_w
mips_aver_u_b
mips_aver_u_d
mips_aver_u_h
mips_aver_u_w
mips_balign
mips_bclr_b
mips_bclr_d
mips_bclr_h
mips_bclr_w
mips_bclri_b
mips_bclri_d
mips_bclri_h
mips_bclri_w
mips_binsl_b
mips_binsl_d
mips_binsl_h
mips_binsl_w
mips_binsli_b
mips_binsli_d
mips_binsli_h
mips_binsli_w
mips_binsr_b
mips_binsr_d
mips_binsr_h
mips_binsr_w
mips_binsri_b
mips_binsri_d
mips_binsri_h
mips_binsri_w
mips_bitrev
mips_bmnz_v
mips_bmnzi_b
mips_bmz_v
mips_bmzi_b
mips_bneg_b
mips_bneg_d
mips_bneg_h
mips_bneg_w
mips_bnegi_b
mips_bnegi_d
mips_bnegi_h
mips_bnegi_w
mips_bnz_b
mips_bnz_d
mips_bnz_h
mips_bnz_v
mips_bnz_w
mips_bposge32
mips_bsel_v
mips_bseli_b
mips_bset_b
mips_bset_d
mips_bset_h
mips_bset_w
mips_bseti_b
mips_bseti_d
mips_bseti_h
mips_bseti_w
mips_bz_b
mips_bz_d
mips_bz_h
mips_bz_v
mips_bz_w
mips_ceq_b
mips_ceq_d
mips_ceq_h
mips_ceq_w
mips_ceqi_b
mips_ceqi_d
mips_ceqi_h
mips_ceqi_w
mips_cfcmsa
mips_cle_s_b
mips_cle_s_d
mips_cle_s_h
mips_cle_s_w
mips_cle_u_b
mips_cle_u_d
mips_cle_u_h
mips_cle_u_w
mips_clei_s_b
mips_clei_s_d
mips_clei_s_h
mips_clei_s_w
mips_clei_u_b
mips_clei_u_d
mips_clei_u_h
mips_clei_u_w
mips_clt_s_b
mips_clt_s_d
mips_clt_s_h
mips_clt_s_w
mips_clt_u_b
mips_clt_u_d
mips_clt_u_h
mips_clt_u_w
mips_clti_s_b
mips_clti_s_d
mips_clti_s_h
mips_clti_s_w
mips_clti_u_b
mips_clti_u_d
mips_clti_u_h
mips_clti_u_w
mips_cmp_eq_ph
mips_cmp_le_ph
mips_cmp_lt_ph
mips_cmpgdu_eq_qb
mips_cmpgdu_le_qb
mips_cmpgdu_lt_qb
mips_cmpgu_eq_qb
mips_cmpgu_le_qb
mips_cmpgu_lt_qb
mips_cmpu_eq_qb
mips_cmpu_le_qb
mips_cmpu_lt_qb
mips_copy_s_b
mips_copy_s_d
mips_copy_s_h
mips_copy_s_w
mips_copy_u_b
mips_copy_u_d
mips_copy_u_h
mips_copy_u_w
mips_ctcmsa
mips_div_s_b
mips_div_s_d
mips_div_s_h
mips_div_s_w
mips_div_u_b
mips_div_u_d
mips_div_u_h
mips_div_u_w
mips_dlsa
mips_dotp_s_d
mips_dotp_s_h
mips_dotp_s_w
mips_dotp_u_d
mips_dotp_u_h
mips_dotp_u_w
mips_dpa_w_ph
mips_dpadd_s_d
mips_dpadd_s_h
mips_dpadd_s_w
mips_dpadd_u_d
mips_dpadd_u_h
mips_dpadd_u_w
mips_dpaq_s_w_ph
mips_dpaq_sa_l_w
mips_dpaqx_s_w_ph
mips_dpaqx_sa_w_ph
mips_dpau_h_qbl
mips_dpau_h_qbr
mips_dpax_w_ph
mips_dps_w_ph
mips_dpsq_s_w_ph
mips_dpsq_sa_l_w
mips_dpsqx_s_w_ph
mips_dpsqx_sa_w_ph
mips_dpsu_h_qbl
mips_dpsu_h_qbr
mips_dpsub_s_d
mips_dpsub_s_h
mips_dpsub_s_w
mips_dpsub_u_d
mips_dpsub_u_h
mips_dpsub_u_w
mips_dpsx_w_ph
mips_extp
mips_extpdp
mips_extr_r_w
mips_extr_rs_w
mips_extr_s_h
mips_extr_w
mips_fadd_d
mips_fadd_w
mips_fcaf_d
mips_fcaf_w
mips_fceq_d
mips_fceq_w
mips_fclass_d
mips_fclass_w
mips_fcle_d
mips_fcle_w
mips_fclt_d
mips_fclt_w
mips_fcne_d
mips_fcne_w
mips_fcor_d
mips_fcor_w
mips_fcueq_d
mips_fcueq_w
mips_fcule_d
mips_fcule_w
mips_fcult_d
mips_fcult_w
mips_fcun_d
mips_fcun_w
mips_fcune_d
mips_fcune_w
mips_fdiv_d
mips_fdiv_w
mips_fexdo_h
mips_fexdo_w
mips_fexp2_d
mips_fexp2_w
mips_fexupl_d
mips_fexupl_w
mips_fexupr_d
mips_fexupr_w
mips_ffint_s_d
mips_ffint_s_w
mips_ffint_u_d
mips_ffint_u_w
mips_ffql_d
mips_ffql_w
mips_ffqr_d
mips_ffqr_w
mips_fill_b
mips_fill_d
mips_fill_h
mips_fill_w
mips_flog2_d
mips_flog2_w
mips_fmadd_d
mips_fmadd_w
mips_fmax_a_d
mips_fmax_a_w
mips_fmax_d
mips_fmax_w
mips_fmin_a_d
mips_fmin_a_w
mips_fmin_d
mips_fmin_w
mips_fmsub_d
mips_fmsub_w
mips_fmul_d
mips_fmul_w
mips_frcp_d
mips_frcp_w
mips_frint_d
mips_frint_w
mips_frsqrt_d
mips_frsqrt_w
mips_fsaf_d
mips_fsaf_w
mips_fseq_d
mips_fseq_w
mips_fsle_d
mips_fsle_w
mips_fslt_d
mips_fslt_w
mips_fsne_d
mips_fsne_w
mips_fsor_d
mips_fsor_w
mips_fsqrt_d
mips_fsqrt_w
mips_fsub_d
mips_fsub_w
mips_fsueq_d
mips_fsueq_w
mips_fsule_d
mips_fsule_w
mips_fsult_d
mips_fsult_w
mips_fsun_d
mips_fsun_w
mips_fsune_d
mips_fsune_w
mips_ftint_s_d
mips_ftint_s_w
mips_ftint_u_d
mips_ftint_u_w
mips_ftq_h
mips_ftq_w
mips_ftrunc_s_d
mips_ftrunc_s_w
mips_ftrunc_u_d
mips_ftrunc_u_w
mips_hadd_s_d
mips_hadd_s_h
mips_hadd_s_w
mips_hadd_u_d
mips_hadd_u_h
mips_hadd_u_w
mips_hsub_s_d
mips_hsub_s_h
mips_hsub_s_w
mips_hsub_u_d
mips_hsub_u_h
mips_hsub_u_w
mips_ilvev_b
mips_ilvev_d
mips_ilvev_h
mips_ilvev_w
mips_ilvl_b
mips_ilvl_d
mips_ilvl_h
mips_ilvl_w
mips_ilvod_b
mips_ilvod_d
mips_ilvod_h
mips_ilvod_w
mips_ilvr_b
mips_ilvr_d
mips_ilvr_h
mips_ilvr_w
mips_insert_b
mips_insert_d
mips_insert_h
mips_insert_w
mips_insv
mips_insve_b
mips_insve_d
mips_insve_h
mips_insve_w
mips_lbux
mips_ld_b
mips_ld_d
mips_ld_h
mips_ld_w
mips_ldi_b
mips_ldi_d
mips_ldi_h
mips_ldi_w
mips_lhx
mips_lsa
mips_lwx
mips_madd
mips_madd_q_h
mips_madd_q_w
mips_maddr_q_h
mips_maddr_q_w
mips_maddu
mips_maddv_b
mips_maddv_d
mips_maddv_h
mips_maddv_w
mips_maq_s_w_phl
mips_maq_s_w_phr
mips_maq_sa_w_phl
mips_maq_sa_w_phr
mips_max_a_b
mips_max_a_d
mips_max_a_h
mips_max_a_w
mips_max_s_b
mips_max_s_d
mips_max_s_h
mips_max_s_w
mips_max_u_b
mips_max_u_d
mips_max_u_h
mips_max_u_w
mips_maxi_s_b
mips_maxi_s_d
mips_maxi_s_h
mips_maxi_s_w
mips_maxi_u_b
mips_maxi_u_d
mips_maxi_u_h
mips_maxi_u_w
mips_min_a_b
mips_min_a_d
mips_min_a_h
mips_min_a_w
mips_min_s_b
mips_min_s_d
mips_min_s_h
mips_min_s_w
mips_min_u_b
mips_min_u_d
mips_min_u_h
mips_min_u_w
mips_mini_s_b
mips_mini_s_d
mips_mini_s_h
mips_mini_s_w
mips_mini_u_b
mips_mini_u_d
mips_mini_u_h
mips_mini_u_w
mips_mod_s_b
mips_mod_s_d
mips_mod_s_h
mips_mod_s_w
mips_mod_u_b
mips_mod_u_d
mips_mod_u_h
mips_mod_u_w
mips_modsub
mips_move_v
mips_msub
mips_msub_q_h
mips_msub_q_w
mips_msubr_q_h
mips_msubr_q_w
mips_msubu
mips_msubv_b
mips_msubv_d
mips_msubv_h
mips_msubv_w
mips_mthlip
mips_mul_ph
mips_mul_q_h
mips_mul_q_w
mips_mul_s_ph
mips_muleq_s_w_phl
mips_muleq_s_w_phr
mips_muleu_s_ph_qbl
mips_muleu_s_ph_qbr
mips_mulq_rs_ph
mips_mulq_rs_w
mips_mulq_s_ph
mips_mulq_s_w
mips_mulr_q_h
mips_mulr_q_w
mips_mulsa_w_ph
mips_mulsaq_s_w_ph
mips_mult
mips_multu
mips_mulv_b
mips_mulv_d
mips_mulv_h
mips_mulv_w
mips_nloc_b
mips_nloc_d
mips_nloc_h
mips_nloc_w
mips_nlzc_b
mips_nlzc_d
mips_nlzc_h
mips_nlzc_w
mips_nor_v
mips_nori_b
mips_or_v
mips_ori_b
mips_packrl_ph
mips_pckev_b
mips_pckev_d
mips_pckev_h
mips_pckev_w
mips_pckod_b
mips_pckod_d
mips_pckod_h
mips_pckod_w
mips_pcnt_b
mips_pcnt_d
mips_pcnt_h
mips_pcnt_w
mips_pick_ph
mips_pick_qb
mips_preceq_w_phl
mips_preceq_w_phr
mips_precequ_ph_qbl
mips_precequ_ph_qbla
mips_precequ_ph_qbr
mips_precequ_ph_qbra
mips_preceu_ph_qbl
mips_preceu_ph_qbla
mips_preceu_ph_qbr
mips_preceu_ph_qbra
mips_precr_qb_ph
mips_precr_sra_ph_w
mips_precr_sra_r_ph_w
mips_precrq_ph_w
mips_precrq_qb_ph
mips_precrq_rs_ph_w
mips_precrqu_s_qb_ph
mips_prepend
mips_raddu_w_qb
mips_rddsp
mips_repl_ph
mips_repl_qb
mips_sat_s_b
mips_sat_s_d
mips_sat_s_h
mips_sat_s_w
mips_sat_u_b
mips_sat_u_d
mips_sat_u_h
mips_sat_u_w
mips_shf_b
mips_shf_h
mips_shf_w
mips_shilo
mips_shll_ph
mips_shll_qb
mips_shll_s_ph
mips_shll_s_w
mips_shra_ph
mips_shra_qb
mips_shra_r_ph
mips_shra_r_qb
mips_shra_r_w
mips_shrl_ph
mips_shrl_qb
mips_sld_b
mips_sld_d
mips_sld_h
mips_sld_w
mips_sldi_b
mips_sldi_d
mips_sldi_h
mips_sldi_w
mips_sll_b
mips_sll_d
mips_sll_h
mips_sll_w
mips_slli_b
mips_slli_d
mips_slli_h
mips_slli_w
mips_splat_b
mips_splat_d
mips_splat_h
mips_splat_w
mips_splati_b
mips_splati_d
mips_splati_h
mips_splati_w
mips_sra_b
mips_sra_d
mips_sra_h
mips_sra_w
mips_srai_b
mips_srai_d
mips_srai_h
mips_srai_w
mips_srar_b
mips_srar_d
mips_srar_h
mips_srar_w
mips_srari_b
mips_srari_d
mips_srari_h
mips_srari_w
mips_srl_b
mips_srl_d
mips_srl_h
mips_srl_w
mips_srli_b
mips_srli_d
mips_srli_h
mips_srli_w
mips_srlr_b
mips_srlr_d
mips_srlr_h
mips_srlr_w
mips_srlri_b
mips_srlri_d
mips_srlri_h
mips_srlri_w
mips_st_b
mips_st_d
mips_st_h
mips_st_w
mips_subq_ph
mips_subq_s_ph
mips_subq_s_w
mips_subqh_ph
mips_subqh_r_ph
mips_subqh_r_w
mips_subqh_w
mips_subs_s_b
mips_subs_s_d
mips_subs_s_h
mips_subs_s_w
mips_subs_u_b
mips_subs_u_d
mips_subs_u_h
mips_subs_u_w
mips_subsus_u_b
mips_subsus_u_d
mips_subsus_u_h
mips_subsus_u_w
mips_subsuu_s_b
mips_subsuu_s_d
mips_subsuu_s_h
mips_subsuu_s_w
mips_subu_ph
mips_subu_qb
mips_subu_s_ph
mips_subu_s_qb
mips_subuh_qb
mips_subuh_r_qb
mips_subv_b
mips_subv_d
mips_subv_h
mips_subv_w
mips_subvi_b
mips_subvi_d
mips_subvi_h
mips_subvi_w
mips_vshf_b
mips_vshf_d
mips_vshf_h
mips_vshf_w
mips_wrdsp
mips_xor_v
mips_xori_b
nvvm_add_rm_d
nvvm_add_rm_f
nvvm_add_rm_ftz_f
nvvm_add_rn_d
nvvm_add_rn_f
nvvm_add_rn_ftz_f
nvvm_add_rp_d
nvvm_add_rp_f
nvvm_add_rp_ftz_f
nvvm_add_rz_d
nvvm_add_rz_f
nvvm_add_rz_ftz_f
nvvm_atomic_add_gen_f_cta
nvvm_atomic_add_gen_f_sys
nvvm_atomic_add_gen_i_cta
nvvm_atomic_add_gen_i_sys
nvvm_atomic_and_gen_i_cta
nvvm_atomic_and_gen_i_sys
nvvm_atomic_cas_gen_i_cta
nvvm_atomic_cas_gen_i_sys
nvvm_atomic_dec_gen_i_cta
nvvm_atomic_dec_gen_i_sys
nvvm_atomic_exch_gen_i_cta
nvvm_atomic_exch_gen_i_sys
nvvm_atomic_inc_gen_i_cta
nvvm_atomic_inc_gen_i_sys
nvvm_atomic_load_add_f32
nvvm_atomic_load_add_f64
nvvm_atomic_load_dec_32
nvvm_atomic_load_inc_32
nvvm_atomic_max_gen_i_cta
nvvm_atomic_max_gen_i_sys
nvvm_atomic_min_gen_i_cta
nvvm_atomic_min_gen_i_sys
nvvm_atomic_or_gen_i_cta
nvvm_atomic_or_gen_i_sys
nvvm_atomic_xor_gen_i_cta
nvvm_atomic_xor_gen_i_sys
nvvm_bar_sync
nvvm_bar_warp_sync
nvvm_barrier
nvvm_barrier_n
nvvm_barrier_sync
nvvm_barrier_sync_cnt
nvvm_barrier0
nvvm_barrier0_and
nvvm_barrier0_or
nvvm_barrier0_popc
nvvm_bitcast_d2ll
nvvm_bitcast_f2i
nvvm_bitcast_i2f
nvvm_bitcast_ll2d
nvvm_ceil_d
nvvm_ceil_f
nvvm_ceil_ftz_f
nvvm_compiler_error
nvvm_compiler_warn
nvvm_cos_approx_f
nvvm_cos_approx_ftz_f
nvvm_d2f_rm
nvvm_d2f_rm_ftz
nvvm_d2f_rn
nvvm_d2f_rn_ftz
nvvm_d2f_rp
nvvm_d2f_rp_ftz
nvvm_d2f_rz
nvvm_d2f_rz_ftz
nvvm_d2i_hi
nvvm_d2i_lo
nvvm_d2i_rm
nvvm_d2i_rn
nvvm_d2i_rp
nvvm_d2i_rz
nvvm_d2ll_rm
nvvm_d2ll_rn
nvvm_d2ll_rp
nvvm_d2ll_rz
nvvm_d2ui_rm
nvvm_d2ui_rn
nvvm_d2ui_rp
nvvm_d2ui_rz
nvvm_d2ull_rm
nvvm_d2ull_rn
nvvm_d2ull_rp
nvvm_d2ull_rz
nvvm_div_approx_f
nvvm_div_approx_ftz_f
nvvm_div_rm_d
nvvm_div_rm_f
nvvm_div_rm_ftz_f
nvvm_div_rn_d
nvvm_div_rn_f
nvvm_div_rn_ftz_f
nvvm_div_rp_d
nvvm_div_rp_f
nvvm_div_rp_ftz_f
nvvm_div_rz_d
nvvm_div_rz_f
nvvm_div_rz_ftz_f
nvvm_ex2_approx_d
nvvm_ex2_approx_f
nvvm_ex2_approx_ftz_f
nvvm_f2h_rn
nvvm_f2h_rn_ftz
nvvm_f2i_rm
nvvm_f2i_rm_ftz
nvvm_f2i_rn
nvvm_f2i_rn_ftz
nvvm_f2i_rp
nvvm_f2i_rp_ftz
nvvm_f2i_rz
nvvm_f2i_rz_ftz
nvvm_f2ll_rm
nvvm_f2ll_rm_ftz
nvvm_f2ll_rn
nvvm_f2ll_rn_ftz
nvvm_f2ll_rp
nvvm_f2ll_rp_ftz
nvvm_f2ll_rz
nvvm_f2ll_rz_ftz
nvvm_f2ui_rm
nvvm_f2ui_rm_ftz
nvvm_f2ui_rn
nvvm_f2ui_rn_ftz
nvvm_f2ui_rp
nvvm_f2ui_rp_ftz
nvvm_f2ui_rz
nvvm_f2ui_rz_ftz
nvvm_f2ull_rm
nvvm_f2ull_rm_ftz
nvvm_f2ull_rn
nvvm_f2ull_rn_ftz
nvvm_f2ull_rp
nvvm_f2ull_rp_ftz
nvvm_f2ull_rz
nvvm_f2ull_rz_ftz
nvvm_fabs_d
nvvm_fabs_f
nvvm_fabs_ftz_f
nvvm_floor_d
nvvm_floor_f
nvvm_floor_ftz_f
nvvm_fma_rm_d
nvvm_fma_rm_f
nvvm_fma_rm_ftz_f
nvvm_fma_rn_d
nvvm_fma_rn_f
nvvm_fma_rn_ftz_f
nvvm_fma_rp_d
nvvm_fma_rp_f
nvvm_fma_rp_ftz_f
nvvm_fma_rz_d
nvvm_fma_rz_f
nvvm_fma_rz_ftz_f
nvvm_fmax_d
nvvm_fmax_f
nvvm_fmax_ftz_f
nvvm_fmin_d
nvvm_fmin_f
nvvm_fmin_ftz_f
nvvm_fns
nvvm_i2d_rm
nvvm_i2d_rn
nvvm_i2d_rp
nvvm_i2d_rz
nvvm_i2f_rm
nvvm_i2f_rn
nvvm_i2f_rp
nvvm_i2f_rz
nvvm_isspacep_const
nvvm_isspacep_global
nvvm_isspacep_local
nvvm_isspacep_shared
nvvm_istypep_sampler
nvvm_istypep_surface
nvvm_istypep_texture
nvvm_ldg_global_f
nvvm_ldg_global_i
nvvm_ldg_global_p
nvvm_ldu_global_f
nvvm_ldu_global_i
nvvm_ldu_global_p
nvvm_lg2_approx_d
nvvm_lg2_approx_f
nvvm_lg2_approx_ftz_f
nvvm_ll2d_rm
nvvm_ll2d_rn
nvvm_ll2d_rp
nvvm_ll2d_rz
nvvm_ll2f_rm
nvvm_ll2f_rn
nvvm_ll2f_rp
nvvm_ll2f_rz
nvvm_lohi_i2d
nvvm_match_all_sync_i32p
nvvm_match_all_sync_i64p
nvvm_match_any_sync_i32
nvvm_match_any_sync_i64
nvvm_membar_cta
nvvm_membar_gl
nvvm_membar_sys
nvvm_move_double
nvvm_move_float
nvvm_move_i16
nvvm_move_i32
nvvm_move_i64
nvvm_move_ptr
nvvm_mul_rm_d
nvvm_mul_rm_f
nvvm_mul_rm_ftz_f
nvvm_mul_rn_d
nvvm_mul_rn_f
nvvm_mul_rn_ftz_f
nvvm_mul_rp_d
nvvm_mul_rp_f
nvvm_mul_rp_ftz_f
nvvm_mul_rz_d
nvvm_mul_rz_f
nvvm_mul_rz_ftz_f
nvvm_mul24_i
nvvm_mul24_ui
nvvm_mulhi_i
nvvm_mulhi_ll
nvvm_mulhi_ui
nvvm_mulhi_ull
nvvm_prmt
nvvm_ptr_constant_to_gen
nvvm_ptr_gen_to_constant
nvvm_ptr_gen_to_global
nvvm_ptr_gen_to_local
nvvm_ptr_gen_to_param
nvvm_ptr_gen_to_shared
nvvm_ptr_global_to_gen
nvvm_ptr_local_to_gen
nvvm_ptr_shared_to_gen
nvvm_rcp_approx_ftz_d
nvvm_rcp_rm_d
nvvm_rcp_rm_f
nvvm_rcp_rm_ftz_f
nvvm_rcp_rn_d
nvvm_rcp_rn_f
nvvm_rcp_rn_ftz_f
nvvm_rcp_rp_d
nvvm_rcp_rp_f
nvvm_rcp_rp_ftz_f
nvvm_rcp_rz_d
nvvm_rcp_rz_f
nvvm_rcp_rz_ftz_f
nvvm_read_ptx_sreg_clock
nvvm_read_ptx_sreg_clock64
nvvm_read_ptx_sreg_ctaid_w
nvvm_read_ptx_sreg_ctaid_x
nvvm_read_ptx_sreg_ctaid_y
nvvm_read_ptx_sreg_ctaid_z
nvvm_read_ptx_sreg_envreg0
nvvm_read_ptx_sreg_envreg1
nvvm_read_ptx_sreg_envreg10
nvvm_read_ptx_sreg_envreg11
nvvm_read_ptx_sreg_envreg12
nvvm_read_ptx_sreg_envreg13
nvvm_read_ptx_sreg_envreg14
nvvm_read_ptx_sreg_envreg15
nvvm_read_ptx_sreg_envreg16
nvvm_read_ptx_sreg_envreg17
nvvm_read_ptx_sreg_envreg18
nvvm_read_ptx_sreg_envreg19
nvvm_read_ptx_sreg_envreg2
nvvm_read_ptx_sreg_envreg20
nvvm_read_ptx_sreg_envreg21
nvvm_read_ptx_sreg_envreg22
nvvm_read_ptx_sreg_envreg23
nvvm_read_ptx_sreg_envreg24
nvvm_read_ptx_sreg_envreg25
nvvm_read_ptx_sreg_envreg26
nvvm_read_ptx_sreg_envreg27
nvvm_read_ptx_sreg_envreg28
nvvm_read_ptx_sreg_envreg29
nvvm_read_ptx_sreg_envreg3
nvvm_read_ptx_sreg_envreg30
nvvm_read_ptx_sreg_envreg31
nvvm_read_ptx_sreg_envreg4
nvvm_read_ptx_sreg_envreg5
nvvm_read_ptx_sreg_envreg6
nvvm_read_ptx_sreg_envreg7
nvvm_read_ptx_sreg_envreg8
nvvm_read_ptx_sreg_envreg9
nvvm_read_ptx_sreg_gridid
nvvm_read_ptx_sreg_laneid
nvvm_read_ptx_sreg_lanemask_eq
nvvm_read_ptx_sreg_lanemask_ge
nvvm_read_ptx_sreg_lanemask_gt
nvvm_read_ptx_sreg_lanemask_le
nvvm_read_ptx_sreg_lanemask_lt
nvvm_read_ptx_sreg_nctaid_w
nvvm_read_ptx_sreg_nctaid_x
nvvm_read_ptx_sreg_nctaid_y
nvvm_read_ptx_sreg_nctaid_z
nvvm_read_ptx_sreg_nsmid
nvvm_read_ptx_sreg_ntid_w
nvvm_read_ptx_sreg_ntid_x
nvvm_read_ptx_sreg_ntid_y
nvvm_read_ptx_sreg_ntid_z
nvvm_read_ptx_sreg_nwarpid
nvvm_read_ptx_sreg_pm0
nvvm_read_ptx_sreg_pm1
nvvm_read_ptx_sreg_pm2
nvvm_read_ptx_sreg_pm3
nvvm_read_ptx_sreg_smid
nvvm_read_ptx_sreg_tid_w
nvvm_read_ptx_sreg_tid_x
nvvm_read_ptx_sreg_tid_y
nvvm_read_ptx_sreg_tid_z
nvvm_read_ptx_sreg_warpid
nvvm_read_ptx_sreg_warpsize
nvvm_reflect
nvvm_rotate_b32
nvvm_rotate_b64
nvvm_rotate_right_b64
nvvm_round_d
nvvm_round_f
nvvm_round_ftz_f
nvvm_rsqrt_approx_d
nvvm_rsqrt_approx_f
nvvm_rsqrt_approx_ftz_f
nvvm_sad_i
nvvm_sad_ui
nvvm_saturate_d
nvvm_saturate_f
nvvm_saturate_ftz_f
nvvm_shfl_bfly_f32
nvvm_shfl_bfly_i32
nvvm_shfl_down_f32
nvvm_shfl_down_i32
nvvm_shfl_idx_f32
nvvm_shfl_idx_i32
nvvm_shfl_sync_bfly_f32
nvvm_shfl_sync_bfly_i32
nvvm_shfl_sync_down_f32
nvvm_shfl_sync_down_i32
nvvm_shfl_sync_idx_f32
nvvm_shfl_sync_idx_i32
nvvm_shfl_sync_up_f32
nvvm_shfl_sync_up_i32
nvvm_shfl_up_f32
nvvm_shfl_up_i32
nvvm_sin_approx_f
nvvm_sin_approx_ftz_f
nvvm_sqrt_approx_f
nvvm_sqrt_approx_ftz_f
nvvm_sqrt_f
nvvm_sqrt_rm_d
nvvm_sqrt_rm_f
nvvm_sqrt_rm_ftz_f
nvvm_sqrt_rn_d
nvvm_sqrt_rn_f
nvvm_sqrt_rn_ftz_f
nvvm_sqrt_rp_d
nvvm_sqrt_rp_f
nvvm_sqrt_rp_ftz_f
nvvm_sqrt_rz_d
nvvm_sqrt_rz_f
nvvm_sqrt_rz_ftz_f
nvvm_suld_1d_array_i16_clamp
nvvm_suld_1d_array_i16_trap
nvvm_suld_1d_array_i16_zero
nvvm_suld_1d_array_i32_clamp
nvvm_suld_1d_array_i32_trap
nvvm_suld_1d_array_i32_zero
nvvm_suld_1d_array_i64_clamp
nvvm_suld_1d_array_i64_trap
nvvm_suld_1d_array_i64_zero
nvvm_suld_1d_array_i8_clamp
nvvm_suld_1d_array_i8_trap
nvvm_suld_1d_array_i8_zero
nvvm_suld_1d_array_v2i16_clamp
nvvm_suld_1d_array_v2i16_trap
nvvm_suld_1d_array_v2i16_zero
nvvm_suld_1d_array_v2i32_clamp
nvvm_suld_1d_array_v2i32_trap
nvvm_suld_1d_array_v2i32_zero
nvvm_suld_1d_array_v2i64_clamp
nvvm_suld_1d_array_v2i64_trap
nvvm_suld_1d_array_v2i64_zero
nvvm_suld_1d_array_v2i8_clamp
nvvm_suld_1d_array_v2i8_trap
nvvm_suld_1d_array_v2i8_zero
nvvm_suld_1d_array_v4i16_clamp
nvvm_suld_1d_array_v4i16_trap
nvvm_suld_1d_array_v4i16_zero
nvvm_suld_1d_array_v4i32_clamp
nvvm_suld_1d_array_v4i32_trap
nvvm_suld_1d_array_v4i32_zero
nvvm_suld_1d_array_v4i8_clamp
nvvm_suld_1d_array_v4i8_trap
nvvm_suld_1d_array_v4i8_zero
nvvm_suld_1d_i16_clamp
nvvm_suld_1d_i16_trap
nvvm_suld_1d_i16_zero
nvvm_suld_1d_i32_clamp
nvvm_suld_1d_i32_trap
nvvm_suld_1d_i32_zero
nvvm_suld_1d_i64_clamp
nvvm_suld_1d_i64_trap
nvvm_suld_1d_i64_zero
nvvm_suld_1d_i8_clamp
nvvm_suld_1d_i8_trap
nvvm_suld_1d_i8_zero
nvvm_suld_1d_v2i16_clamp
nvvm_suld_1d_v2i16_trap
nvvm_suld_1d_v2i16_zero
nvvm_suld_1d_v2i32_clamp
nvvm_suld_1d_v2i32_trap
nvvm_suld_1d_v2i32_zero
nvvm_suld_1d_v2i64_clamp
nvvm_suld_1d_v2i64_trap
nvvm_suld_1d_v2i64_zero
nvvm_suld_1d_v2i8_clamp
nvvm_suld_1d_v2i8_trap
nvvm_suld_1d_v2i8_zero
nvvm_suld_1d_v4i16_clamp
nvvm_suld_1d_v4i16_trap
nvvm_suld_1d_v4i16_zero
nvvm_suld_1d_v4i32_clamp
nvvm_suld_1d_v4i32_trap
nvvm_suld_1d_v4i32_zero
nvvm_suld_1d_v4i8_clamp
nvvm_suld_1d_v4i8_trap
nvvm_suld_1d_v4i8_zero
nvvm_suld_2d_array_i16_clamp
nvvm_suld_2d_array_i16_trap
nvvm_suld_2d_array_i16_zero
nvvm_suld_2d_array_i32_clamp
nvvm_suld_2d_array_i32_trap
nvvm_suld_2d_array_i32_zero
nvvm_suld_2d_array_i64_clamp
nvvm_suld_2d_array_i64_trap
nvvm_suld_2d_array_i64_zero
nvvm_suld_2d_array_i8_clamp
nvvm_suld_2d_array_i8_trap
nvvm_suld_2d_array_i8_zero
nvvm_suld_2d_array_v2i16_clamp
nvvm_suld_2d_array_v2i16_trap
nvvm_suld_2d_array_v2i16_zero
nvvm_suld_2d_array_v2i32_clamp
nvvm_suld_2d_array_v2i32_trap
nvvm_suld_2d_array_v2i32_zero
nvvm_suld_2d_array_v2i64_clamp
nvvm_suld_2d_array_v2i64_trap
nvvm_suld_2d_array_v2i64_zero
nvvm_suld_2d_array_v2i8_clamp
nvvm_suld_2d_array_v2i8_trap
nvvm_suld_2d_array_v2i8_zero
nvvm_suld_2d_array_v4i16_clamp
nvvm_suld_2d_array_v4i16_trap
nvvm_suld_2d_array_v4i16_zero
nvvm_suld_2d_array_v4i32_clamp
nvvm_suld_2d_array_v4i32_trap
nvvm_suld_2d_array_v4i32_zero
nvvm_suld_2d_array_v4i8_clamp
nvvm_suld_2d_array_v4i8_trap
nvvm_suld_2d_array_v4i8_zero
nvvm_suld_2d_i16_clamp
nvvm_suld_2d_i16_trap
nvvm_suld_2d_i16_zero
nvvm_suld_2d_i32_clamp
nvvm_suld_2d_i32_trap
nvvm_suld_2d_i32_zero
nvvm_suld_2d_i64_clamp
nvvm_suld_2d_i64_trap
nvvm_suld_2d_i64_zero
nvvm_suld_2d_i8_clamp
nvvm_suld_2d_i8_trap
nvvm_suld_2d_i8_zero
nvvm_suld_2d_v2i16_clamp
nvvm_suld_2d_v2i16_trap
nvvm_suld_2d_v2i16_zero
nvvm_suld_2d_v2i32_clamp
nvvm_suld_2d_v2i32_trap
nvvm_suld_2d_v2i32_zero
nvvm_suld_2d_v2i64_clamp
nvvm_suld_2d_v2i64_trap
nvvm_suld_2d_v2i64_zero
nvvm_suld_2d_v2i8_clamp
nvvm_suld_2d_v2i8_trap
nvvm_suld_2d_v2i8_zero
nvvm_suld_2d_v4i16_clamp
nvvm_suld_2d_v4i16_trap
nvvm_suld_2d_v4i16_zero
nvvm_suld_2d_v4i32_clamp
nvvm_suld_2d_v4i32_trap
nvvm_suld_2d_v4i32_zero
nvvm_suld_2d_v4i8_clamp
nvvm_suld_2d_v4i8_trap
nvvm_suld_2d_v4i8_zero
nvvm_suld_3d_i16_clamp
nvvm_suld_3d_i16_trap
nvvm_suld_3d_i16_zero
nvvm_suld_3d_i32_clamp
nvvm_suld_3d_i32_trap
nvvm_suld_3d_i32_zero
nvvm_suld_3d_i64_clamp
nvvm_suld_3d_i64_trap
nvvm_suld_3d_i64_zero
nvvm_suld_3d_i8_clamp
nvvm_suld_3d_i8_trap
nvvm_suld_3d_i8_zero
nvvm_suld_3d_v2i16_clamp
nvvm_suld_3d_v2i16_trap
nvvm_suld_3d_v2i16_zero
nvvm_suld_3d_v2i32_clamp
nvvm_suld_3d_v2i32_trap
nvvm_suld_3d_v2i32_zero
nvvm_suld_3d_v2i64_clamp
nvvm_suld_3d_v2i64_trap
nvvm_suld_3d_v2i64_zero
nvvm_suld_3d_v2i8_clamp
nvvm_suld_3d_v2i8_trap
nvvm_suld_3d_v2i8_zero
nvvm_suld_3d_v4i16_clamp
nvvm_suld_3d_v4i16_trap
nvvm_suld_3d_v4i16_zero
nvvm_suld_3d_v4i32_clamp
nvvm_suld_3d_v4i32_trap
nvvm_suld_3d_v4i32_zero
nvvm_suld_3d_v4i8_clamp
nvvm_suld_3d_v4i8_trap
nvvm_suld_3d_v4i8_zero
nvvm_suq_array_size
nvvm_suq_channel_data_type
nvvm_suq_channel_order
nvvm_suq_depth
nvvm_suq_height
nvvm_suq_width
nvvm_sust_b_1d_array_i16_clamp
nvvm_sust_b_1d_array_i16_trap
nvvm_sust_b_1d_array_i16_zero
nvvm_sust_b_1d_array_i32_clamp
nvvm_sust_b_1d_array_i32_trap
nvvm_sust_b_1d_array_i32_zero
nvvm_sust_b_1d_array_i64_clamp
nvvm_sust_b_1d_array_i64_trap
nvvm_sust_b_1d_array_i64_zero
nvvm_sust_b_1d_array_i8_clamp
nvvm_sust_b_1d_array_i8_trap
nvvm_sust_b_1d_array_i8_zero
nvvm_sust_b_1d_array_v2i16_clamp
nvvm_sust_b_1d_array_v2i16_trap
nvvm_sust_b_1d_array_v2i16_zero
nvvm_sust_b_1d_array_v2i32_clamp
nvvm_sust_b_1d_array_v2i32_trap
nvvm_sust_b_1d_array_v2i32_zero
nvvm_sust_b_1d_array_v2i64_clamp
nvvm_sust_b_1d_array_v2i64_trap
nvvm_sust_b_1d_array_v2i64_zero
nvvm_sust_b_1d_array_v2i8_clamp
nvvm_sust_b_1d_array_v2i8_trap
nvvm_sust_b_1d_array_v2i8_zero
nvvm_sust_b_1d_array_v4i16_clamp
nvvm_sust_b_1d_array_v4i16_trap
nvvm_sust_b_1d_array_v4i16_zero
nvvm_sust_b_1d_array_v4i32_clamp
nvvm_sust_b_1d_array_v4i32_trap
nvvm_sust_b_1d_array_v4i32_zero
nvvm_sust_b_1d_array_v4i8_clamp
nvvm_sust_b_1d_array_v4i8_trap
nvvm_sust_b_1d_array_v4i8_zero
nvvm_sust_b_1d_i16_clamp
nvvm_sust_b_1d_i16_trap
nvvm_sust_b_1d_i16_zero
nvvm_sust_b_1d_i32_clamp
nvvm_sust_b_1d_i32_trap
nvvm_sust_b_1d_i32_zero
nvvm_sust_b_1d_i64_clamp
nvvm_sust_b_1d_i64_trap
nvvm_sust_b_1d_i64_zero
nvvm_sust_b_1d_i8_clamp
nvvm_sust_b_1d_i8_trap
nvvm_sust_b_1d_i8_zero
nvvm_sust_b_1d_v2i16_clamp
nvvm_sust_b_1d_v2i16_trap
nvvm_sust_b_1d_v2i16_zero
nvvm_sust_b_1d_v2i32_clamp
nvvm_sust_b_1d_v2i32_trap
nvvm_sust_b_1d_v2i32_zero
nvvm_sust_b_1d_v2i64_clamp
nvvm_sust_b_1d_v2i64_trap
nvvm_sust_b_1d_v2i64_zero
nvvm_sust_b_1d_v2i8_clamp
nvvm_sust_b_1d_v2i8_trap
nvvm_sust_b_1d_v2i8_zero
nvvm_sust_b_1d_v4i16_clamp
nvvm_sust_b_1d_v4i16_trap
nvvm_sust_b_1d_v4i16_zero
nvvm_sust_b_1d_v4i32_clamp
nvvm_sust_b_1d_v4i32_trap
nvvm_sust_b_1d_v4i32_zero
nvvm_sust_b_1d_v4i8_clamp
nvvm_sust_b_1d_v4i8_trap
nvvm_sust_b_1d_v4i8_zero
nvvm_sust_b_2d_array_i16_clamp
nvvm_sust_b_2d_array_i16_trap
nvvm_sust_b_2d_array_i16_zero
nvvm_sust_b_2d_array_i32_clamp
nvvm_sust_b_2d_array_i32_trap
nvvm_sust_b_2d_array_i32_zero
nvvm_sust_b_2d_array_i64_clamp
nvvm_sust_b_2d_array_i64_trap
nvvm_sust_b_2d_array_i64_zero
nvvm_sust_b_2d_array_i8_clamp
nvvm_sust_b_2d_array_i8_trap
nvvm_sust_b_2d_array_i8_zero
nvvm_sust_b_2d_array_v2i16_clamp
nvvm_sust_b_2d_array_v2i16_trap
nvvm_sust_b_2d_array_v2i16_zero
nvvm_sust_b_2d_array_v2i32_clamp
nvvm_sust_b_2d_array_v2i32_trap
nvvm_sust_b_2d_array_v2i32_zero
nvvm_sust_b_2d_array_v2i64_clamp
nvvm_sust_b_2d_array_v2i64_trap
nvvm_sust_b_2d_array_v2i64_zero
nvvm_sust_b_2d_array_v2i8_clamp
nvvm_sust_b_2d_array_v2i8_trap
nvvm_sust_b_2d_array_v2i8_zero
nvvm_sust_b_2d_array_v4i16_clamp
nvvm_sust_b_2d_array_v4i16_trap
nvvm_sust_b_2d_array_v4i16_zero
nvvm_sust_b_2d_array_v4i32_clamp
nvvm_sust_b_2d_array_v4i32_trap
nvvm_sust_b_2d_array_v4i32_zero
nvvm_sust_b_2d_array_v4i8_clamp
nvvm_sust_b_2d_array_v4i8_trap
nvvm_sust_b_2d_array_v4i8_zero
nvvm_sust_b_2d_i16_clamp
nvvm_sust_b_2d_i16_trap
nvvm_sust_b_2d_i16_zero
nvvm_sust_b_2d_i32_clamp
nvvm_sust_b_2d_i32_trap
nvvm_sust_b_2d_i32_zero
nvvm_sust_b_2d_i64_clamp
nvvm_sust_b_2d_i64_trap
nvvm_sust_b_2d_i64_zero
nvvm_sust_b_2d_i8_clamp
nvvm_sust_b_2d_i8_trap
nvvm_sust_b_2d_i8_zero
nvvm_sust_b_2d_v2i16_clamp
nvvm_sust_b_2d_v2i16_trap
nvvm_sust_b_2d_v2i16_zero
nvvm_sust_b_2d_v2i32_clamp
nvvm_sust_b_2d_v2i32_trap
nvvm_sust_b_2d_v2i32_zero
nvvm_sust_b_2d_v2i64_clamp
nvvm_sust_b_2d_v2i64_trap
nvvm_sust_b_2d_v2i64_zero
nvvm_sust_b_2d_v2i8_clamp
nvvm_sust_b_2d_v2i8_trap
nvvm_sust_b_2d_v2i8_zero
nvvm_sust_b_2d_v4i16_clamp
nvvm_sust_b_2d_v4i16_trap
nvvm_sust_b_2d_v4i16_zero
nvvm_sust_b_2d_v4i32_clamp
nvvm_sust_b_2d_v4i32_trap
nvvm_sust_b_2d_v4i32_zero
nvvm_sust_b_2d_v4i8_clamp
nvvm_sust_b_2d_v4i8_trap
nvvm_sust_b_2d_v4i8_zero
nvvm_sust_b_3d_i16_clamp
nvvm_sust_b_3d_i16_trap
nvvm_sust_b_3d_i16_zero
nvvm_sust_b_3d_i32_clamp
nvvm_sust_b_3d_i32_trap
nvvm_sust_b_3d_i32_zero
nvvm_sust_b_3d_i64_clamp
nvvm_sust_b_3d_i64_trap
nvvm_sust_b_3d_i64_zero
nvvm_sust_b_3d_i8_clamp
nvvm_sust_b_3d_i8_trap
nvvm_sust_b_3d_i8_zero
nvvm_sust_b_3d_v2i16_clamp
nvvm_sust_b_3d_v2i16_trap
nvvm_sust_b_3d_v2i16_zero
nvvm_sust_b_3d_v2i32_clamp
nvvm_sust_b_3d_v2i32_trap
nvvm_sust_b_3d_v2i32_zero
nvvm_sust_b_3d_v2i64_clamp
nvvm_sust_b_3d_v2i64_trap
nvvm_sust_b_3d_v2i64_zero
nvvm_sust_b_3d_v2i8_clamp
nvvm_sust_b_3d_v2i8_trap
nvvm_sust_b_3d_v2i8_zero
nvvm_sust_b_3d_v4i16_clamp
nvvm_sust_b_3d_v4i16_trap
nvvm_sust_b_3d_v4i16_zero
nvvm_sust_b_3d_v4i32_clamp
nvvm_sust_b_3d_v4i32_trap
nvvm_sust_b_3d_v4i32_zero
nvvm_sust_b_3d_v4i8_clamp
nvvm_sust_b_3d_v4i8_trap
nvvm_sust_b_3d_v4i8_zero
nvvm_sust_p_1d_array_i16_trap
nvvm_sust_p_1d_array_i32_trap
nvvm_sust_p_1d_array_i8_trap
nvvm_sust_p_1d_array_v2i16_trap
nvvm_sust_p_1d_array_v2i32_trap
nvvm_sust_p_1d_array_v2i8_trap
nvvm_sust_p_1d_array_v4i16_trap
nvvm_sust_p_1d_array_v4i32_trap
nvvm_sust_p_1d_array_v4i8_trap
nvvm_sust_p_1d_i16_trap
nvvm_sust_p_1d_i32_trap
nvvm_sust_p_1d_i8_trap
nvvm_sust_p_1d_v2i16_trap
nvvm_sust_p_1d_v2i32_trap
nvvm_sust_p_1d_v2i8_trap
nvvm_sust_p_1d_v4i16_trap
nvvm_sust_p_1d_v4i32_trap
nvvm_sust_p_1d_v4i8_trap
nvvm_sust_p_2d_array_i16_trap
nvvm_sust_p_2d_array_i32_trap
nvvm_sust_p_2d_array_i8_trap
nvvm_sust_p_2d_array_v2i16_trap
nvvm_sust_p_2d_array_v2i32_trap
nvvm_sust_p_2d_array_v2i8_trap
nvvm_sust_p_2d_array_v4i16_trap
nvvm_sust_p_2d_array_v4i32_trap
nvvm_sust_p_2d_array_v4i8_trap
nvvm_sust_p_2d_i16_trap
nvvm_sust_p_2d_i32_trap
nvvm_sust_p_2d_i8_trap
nvvm_sust_p_2d_v2i16_trap
nvvm_sust_p_2d_v2i32_trap
nvvm_sust_p_2d_v2i8_trap
nvvm_sust_p_2d_v4i16_trap
nvvm_sust_p_2d_v4i32_trap
nvvm_sust_p_2d_v4i8_trap
nvvm_sust_p_3d_i16_trap
nvvm_sust_p_3d_i32_trap
nvvm_sust_p_3d_i8_trap
nvvm_sust_p_3d_v2i16_trap
nvvm_sust_p_3d_v2i32_trap
nvvm_sust_p_3d_v2i8_trap
nvvm_sust_p_3d_v4i16_trap
nvvm_sust_p_3d_v4i32_trap
nvvm_sust_p_3d_v4i8_trap
nvvm_swap_lo_hi_b64
nvvm_tex_1d_array_grad_v4f32_f32
nvvm_tex_1d_array_grad_v4s32_f32
nvvm_tex_1d_array_grad_v4u32_f32
nvvm_tex_1d_array_level_v4f32_f32
nvvm_tex_1d_array_level_v4s32_f32
nvvm_tex_1d_array_level_v4u32_f32
nvvm_tex_1d_array_v4f32_f32
nvvm_tex_1d_array_v4f32_s32
nvvm_tex_1d_array_v4s32_f32
nvvm_tex_1d_array_v4s32_s32
nvvm_tex_1d_array_v4u32_f32
nvvm_tex_1d_array_v4u32_s32
nvvm_tex_1d_grad_v4f32_f32
nvvm_tex_1d_grad_v4s32_f32
nvvm_tex_1d_grad_v4u32_f32
nvvm_tex_1d_level_v4f32_f32
nvvm_tex_1d_level_v4s32_f32
nvvm_tex_1d_level_v4u32_f32
nvvm_tex_1d_v4f32_f32
nvvm_tex_1d_v4f32_s32
nvvm_tex_1d_v4s32_f32
nvvm_tex_1d_v4s32_s32
nvvm_tex_1d_v4u32_f32
nvvm_tex_1d_v4u32_s32
nvvm_tex_2d_array_grad_v4f32_f32
nvvm_tex_2d_array_grad_v4s32_f32
nvvm_tex_2d_array_grad_v4u32_f32
nvvm_tex_2d_array_level_v4f32_f32
nvvm_tex_2d_array_level_v4s32_f32
nvvm_tex_2d_array_level_v4u32_f32
nvvm_tex_2d_array_v4f32_f32
nvvm_tex_2d_array_v4f32_s32
nvvm_tex_2d_array_v4s32_f32
nvvm_tex_2d_array_v4s32_s32
nvvm_tex_2d_array_v4u32_f32
nvvm_tex_2d_array_v4u32_s32
nvvm_tex_2d_grad_v4f32_f32
nvvm_tex_2d_grad_v4s32_f32
nvvm_tex_2d_grad_v4u32_f32
nvvm_tex_2d_level_v4f32_f32
nvvm_tex_2d_level_v4s32_f32
nvvm_tex_2d_level_v4u32_f32
nvvm_tex_2d_v4f32_f32
nvvm_tex_2d_v4f32_s32
nvvm_tex_2d_v4s32_f32
nvvm_tex_2d_v4s32_s32
nvvm_tex_2d_v4u32_f32
nvvm_tex_2d_v4u32_s32
nvvm_tex_3d_grad_v4f32_f32
nvvm_tex_3d_grad_v4s32_f32
nvvm_tex_3d_grad_v4u32_f32
nvvm_tex_3d_level_v4f32_f32
nvvm_tex_3d_level_v4s32_f32
nvvm_tex_3d_level_v4u32_f32
nvvm_tex_3d_v4f32_f32
nvvm_tex_3d_v4f32_s32
nvvm_tex_3d_v4s32_f32
nvvm_tex_3d_v4s32_s32
nvvm_tex_3d_v4u32_f32
nvvm_tex_3d_v4u32_s32
nvvm_tex_cube_array_level_v4f32_f32
nvvm_tex_cube_array_level_v4s32_f32
nvvm_tex_cube_array_level_v4u32_f32
nvvm_tex_cube_array_v4f32_f32
nvvm_tex_cube_array_v4s32_f32
nvvm_tex_cube_array_v4u32_f32
nvvm_tex_cube_level_v4f32_f32
nvvm_tex_cube_level_v4s32_f32
nvvm_tex_cube_level_v4u32_f32
nvvm_tex_cube_v4f32_f32
nvvm_tex_cube_v4s32_f32
nvvm_tex_cube_v4u32_f32
nvvm_tex_unified_1d_array_grad_v4f32_f32
nvvm_tex_unified_1d_array_grad_v4s32_f32
nvvm_tex_unified_1d_array_grad_v4u32_f32
nvvm_tex_unified_1d_array_level_v4f32_f32
nvvm_tex_unified_1d_array_level_v4s32_f32
nvvm_tex_unified_1d_array_level_v4u32_f32
nvvm_tex_unified_1d_array_v4f32_f32
nvvm_tex_unified_1d_array_v4f32_s32
nvvm_tex_unified_1d_array_v4s32_f32
nvvm_tex_unified_1d_array_v4s32_s32
nvvm_tex_unified_1d_array_v4u32_f32
nvvm_tex_unified_1d_array_v4u32_s32
nvvm_tex_unified_1d_grad_v4f32_f32
nvvm_tex_unified_1d_grad_v4s32_f32
nvvm_tex_unified_1d_grad_v4u32_f32
nvvm_tex_unified_1d_level_v4f32_f32
nvvm_tex_unified_1d_level_v4s32_f32
nvvm_tex_unified_1d_level_v4u32_f32
nvvm_tex_unified_1d_v4f32_f32
nvvm_tex_unified_1d_v4f32_s32
nvvm_tex_unified_1d_v4s32_f32
nvvm_tex_unified_1d_v4s32_s32
nvvm_tex_unified_1d_v4u32_f32
nvvm_tex_unified_1d_v4u32_s32
nvvm_tex_unified_2d_array_grad_v4f32_f32
nvvm_tex_unified_2d_array_grad_v4s32_f32
nvvm_tex_unified_2d_array_grad_v4u32_f32
nvvm_tex_unified_2d_array_level_v4f32_f32
nvvm_tex_unified_2d_array_level_v4s32_f32
nvvm_tex_unified_2d_array_level_v4u32_f32
nvvm_tex_unified_2d_array_v4f32_f32
nvvm_tex_unified_2d_array_v4f32_s32
nvvm_tex_unified_2d_array_v4s32_f32
nvvm_tex_unified_2d_array_v4s32_s32
nvvm_tex_unified_2d_array_v4u32_f32
nvvm_tex_unified_2d_array_v4u32_s32
nvvm_tex_unified_2d_grad_v4f32_f32
nvvm_tex_unified_2d_grad_v4s32_f32
nvvm_tex_unified_2d_grad_v4u32_f32
nvvm_tex_unified_2d_level_v4f32_f32
nvvm_tex_unified_2d_level_v4s32_f32
nvvm_tex_unified_2d_level_v4u32_f32
nvvm_tex_unified_2d_v4f32_f32
nvvm_tex_unified_2d_v4f32_s32
nvvm_tex_unified_2d_v4s32_f32
nvvm_tex_unified_2d_v4s32_s32
nvvm_tex_unified_2d_v4u32_f32
nvvm_tex_unified_2d_v4u32_s32
nvvm_tex_unified_3d_grad_v4f32_f32
nvvm_tex_unified_3d_grad_v4s32_f32
nvvm_tex_unified_3d_grad_v4u32_f32
nvvm_tex_unified_3d_level_v4f32_f32
nvvm_tex_unified_3d_level_v4s32_f32
nvvm_tex_unified_3d_level_v4u32_f32
nvvm_tex_unified_3d_v4f32_f32
nvvm_tex_unified_3d_v4f32_s32
nvvm_tex_unified_3d_v4s32_f32
nvvm_tex_unified_3d_v4s32_s32
nvvm_tex_unified_3d_v4u32_f32
nvvm_tex_unified_3d_v4u32_s32
nvvm_tex_unified_cube_array_level_v4f32_f32
nvvm_tex_unified_cube_array_level_v4s32_f32
nvvm_tex_unified_cube_array_level_v4u32_f32
nvvm_tex_unified_cube_array_v4f32_f32
nvvm_tex_unified_cube_array_v4s32_f32
nvvm_tex_unified_cube_array_v4u32_f32
nvvm_tex_unified_cube_level_v4f32_f32
nvvm_tex_unified_cube_level_v4s32_f32
nvvm_tex_unified_cube_level_v4u32_f32
nvvm_tex_unified_cube_v4f32_f32
nvvm_tex_unified_cube_v4s32_f32
nvvm_tex_unified_cube_v4u32_f32
nvvm_texsurf_handle
nvvm_texsurf_handle_internal
nvvm_tld4_a_2d_v4f32_f32
nvvm_tld4_a_2d_v4s32_f32
nvvm_tld4_a_2d_v4u32_f32
nvvm_tld4_b_2d_v4f32_f32
nvvm_tld4_b_2d_v4s32_f32
nvvm_tld4_b_2d_v4u32_f32
nvvm_tld4_g_2d_v4f32_f32
nvvm_tld4_g_2d_v4s32_f32
nvvm_tld4_g_2d_v4u32_f32
nvvm_tld4_r_2d_v4f32_f32
nvvm_tld4_r_2d_v4s32_f32
nvvm_tld4_r_2d_v4u32_f32
nvvm_tld4_unified_a_2d_v4f32_f32
nvvm_tld4_unified_a_2d_v4s32_f32
nvvm_tld4_unified_a_2d_v4u32_f32
nvvm_tld4_unified_b_2d_v4f32_f32
nvvm_tld4_unified_b_2d_v4s32_f32
nvvm_tld4_unified_b_2d_v4u32_f32
nvvm_tld4_unified_g_2d_v4f32_f32
nvvm_tld4_unified_g_2d_v4s32_f32
nvvm_tld4_unified_g_2d_v4u32_f32
nvvm_tld4_unified_r_2d_v4f32_f32
nvvm_tld4_unified_r_2d_v4s32_f32
nvvm_tld4_unified_r_2d_v4u32_f32
nvvm_trunc_d
nvvm_trunc_f
nvvm_trunc_ftz_f
nvvm_txq_array_size
nvvm_txq_channel_data_type
nvvm_txq_channel_order
nvvm_txq_depth
nvvm_txq_height
nvvm_txq_num_mipmap_levels
nvvm_txq_num_samples
nvvm_txq_width
nvvm_ui2d_rm
nvvm_ui2d_rn
nvvm_ui2d_rp
nvvm_ui2d_rz
nvvm_ui2f_rm
nvvm_ui2f_rn
nvvm_ui2f_rp
nvvm_ui2f_rz
nvvm_ull2d_rm
nvvm_ull2d_rn
nvvm_ull2d_rp
nvvm_ull2d_rz
nvvm_ull2f_rm
nvvm_ull2f_rn
nvvm_ull2f_rp
nvvm_ull2f_rz
nvvm_vote_all
nvvm_vote_all_sync
nvvm_vote_any
nvvm_vote_any_sync
nvvm_vote_ballot
nvvm_vote_ballot_sync
nvvm_vote_uni
nvvm_vote_uni_sync
nvvm_wmma_m16n16k16_load_a_f16_col
nvvm_wmma_m16n16k16_load_a_f16_col_stride
nvvm_wmma_m16n16k16_load_a_f16_row
nvvm_wmma_m16n16k16_load_a_f16_row_stride
nvvm_wmma_m16n16k16_load_b_f16_col
nvvm_wmma_m16n16k16_load_b_f16_col_stride
nvvm_wmma_m16n16k16_load_b_f16_row
nvvm_wmma_m16n16k16_load_b_f16_row_stride
nvvm_wmma_m16n16k16_load_c_f16_col
nvvm_wmma_m16n16k16_load_c_f32_col
nvvm_wmma_m16n16k16_load_c_f16_col_stride
nvvm_wmma_m16n16k16_load_c_f32_col_stride
nvvm_wmma_m16n16k16_load_c_f16_row
nvvm_wmma_m16n16k16_load_c_f32_row
nvvm_wmma_m16n16k16_load_c_f16_row_stride
nvvm_wmma_m16n16k16_load_c_f32_row_stride
nvvm_wmma_m16n16k16_mma_col_col_f16_f16
nvvm_wmma_m16n16k16_mma_col_col_f16_f16_satfinite
nvvm_wmma_m16n16k16_mma_col_col_f16_f32
nvvm_wmma_m16n16k16_mma_col_col_f16_f32_satfinite
nvvm_wmma_m16n16k16_mma_col_col_f32_f16
nvvm_wmma_m16n16k16_mma_col_col_f32_f16_satfinite
nvvm_wmma_m16n16k16_mma_col_col_f32_f32
nvvm_wmma_m16n16k16_mma_col_col_f32_f32_satfinite
nvvm_wmma_m16n16k16_mma_col_row_f16_f16
nvvm_wmma_m16n16k16_mma_col_row_f16_f16_satfinite
nvvm_wmma_m16n16k16_mma_col_row_f16_f32
nvvm_wmma_m16n16k16_mma_col_row_f16_f32_satfinite
nvvm_wmma_m16n16k16_mma_col_row_f32_f16
nvvm_wmma_m16n16k16_mma_col_row_f32_f16_satfinite
nvvm_wmma_m16n16k16_mma_col_row_f32_f32
nvvm_wmma_m16n16k16_mma_col_row_f32_f32_satfinite
nvvm_wmma_m16n16k16_mma_row_col_f16_f16
nvvm_wmma_m16n16k16_mma_row_col_f16_f16_satfinite
nvvm_wmma_m16n16k16_mma_row_col_f16_f32
nvvm_wmma_m16n16k16_mma_row_col_f16_f32_satfinite
nvvm_wmma_m16n16k16_mma_row_col_f32_f16
nvvm_wmma_m16n16k16_mma_row_col_f32_f16_satfinite
nvvm_wmma_m16n16k16_mma_row_col_f32_f32
nvvm_wmma_m16n16k16_mma_row_col_f32_f32_satfinite
nvvm_wmma_m16n16k16_mma_row_row_f16_f16
nvvm_wmma_m16n16k16_mma_row_row_f16_f16_satfinite
nvvm_wmma_m16n16k16_mma_row_row_f16_f32
nvvm_wmma_m16n16k16_mma_row_row_f16_f32_satfinite
nvvm_wmma_m16n16k16_mma_row_row_f32_f16
nvvm_wmma_m16n16k16_mma_row_row_f32_f16_satfinite
nvvm_wmma_m16n16k16_mma_row_row_f32_f32
nvvm_wmma_m16n16k16_mma_row_row_f32_f32_satfinite
nvvm_wmma_m16n16k16_store_d_f16_col
nvvm_wmma_m16n16k16_store_d_f32_col
nvvm_wmma_m16n16k16_store_d_f16_col_stride
nvvm_wmma_m16n16k16_store_d_f32_col_stride
nvvm_wmma_m16n16k16_store_d_f16_row
nvvm_wmma_m16n16k16_store_d_f32_row
nvvm_wmma_m16n16k16_store_d_f16_row_stride
nvvm_wmma_m16n16k16_store_d_f32_row_stride
nvvm_wmma_m32n8k16_load_a_f16_col
nvvm_wmma_m32n8k16_load_a_f16_col_stride
nvvm_wmma_m32n8k16_load_a_f16_row
nvvm_wmma_m32n8k16_load_a_f16_row_stride
nvvm_wmma_m32n8k16_load_b_f16_col
nvvm_wmma_m32n8k16_load_b_f16_col_stride
nvvm_wmma_m32n8k16_load_b_f16_row
nvvm_wmma_m32n8k16_load_b_f16_row_stride
nvvm_wmma_m32n8k16_load_c_f16_col
nvvm_wmma_m32n8k16_load_c_f32_col
nvvm_wmma_m32n8k16_load_c_f16_col_stride
nvvm_wmma_m32n8k16_load_c_f32_col_stride
nvvm_wmma_m32n8k16_load_c_f16_row
nvvm_wmma_m32n8k16_load_c_f32_row
nvvm_wmma_m32n8k16_load_c_f16_row_stride
nvvm_wmma_m32n8k16_load_c_f32_row_stride
nvvm_wmma_m32n8k16_mma_col_col_f16_f16
nvvm_wmma_m32n8k16_mma_col_col_f16_f16_satfinite
nvvm_wmma_m32n8k16_mma_col_col_f16_f32
nvvm_wmma_m32n8k16_mma_col_col_f16_f32_satfinite
nvvm_wmma_m32n8k16_mma_col_col_f32_f16
nvvm_wmma_m32n8k16_mma_col_col_f32_f16_satfinite
nvvm_wmma_m32n8k16_mma_col_col_f32_f32
nvvm_wmma_m32n8k16_mma_col_col_f32_f32_satfinite
nvvm_wmma_m32n8k16_mma_col_row_f16_f16
nvvm_wmma_m32n8k16_mma_col_row_f16_f16_satfinite
nvvm_wmma_m32n8k16_mma_col_row_f16_f32
nvvm_wmma_m32n8k16_mma_col_row_f16_f32_satfinite
nvvm_wmma_m32n8k16_mma_col_row_f32_f16
nvvm_wmma_m32n8k16_mma_col_row_f32_f16_satfinite
nvvm_wmma_m32n8k16_mma_col_row_f32_f32
nvvm_wmma_m32n8k16_mma_col_row_f32_f32_satfinite
nvvm_wmma_m32n8k16_mma_row_col_f16_f16
nvvm_wmma_m32n8k16_mma_row_col_f16_f16_satfinite
nvvm_wmma_m32n8k16_mma_row_col_f16_f32
nvvm_wmma_m32n8k16_mma_row_col_f16_f32_satfinite
nvvm_wmma_m32n8k16_mma_row_col_f32_f16
nvvm_wmma_m32n8k16_mma_row_col_f32_f16_satfinite
nvvm_wmma_m32n8k16_mma_row_col_f32_f32
nvvm_wmma_m32n8k16_mma_row_col_f32_f32_satfinite
nvvm_wmma_m32n8k16_mma_row_row_f16_f16
nvvm_wmma_m32n8k16_mma_row_row_f16_f16_satfinite
nvvm_wmma_m32n8k16_mma_row_row_f16_f32
nvvm_wmma_m32n8k16_mma_row_row_f16_f32_satfinite
nvvm_wmma_m32n8k16_mma_row_row_f32_f16
nvvm_wmma_m32n8k16_mma_row_row_f32_f16_satfinite
nvvm_wmma_m32n8k16_mma_row_row_f32_f32
nvvm_wmma_m32n8k16_mma_row_row_f32_f32_satfinite
nvvm_wmma_m32n8k16_store_d_f16_col
nvvm_wmma_m32n8k16_store_d_f32_col
nvvm_wmma_m32n8k16_store_d_f16_col_stride
nvvm_wmma_m32n8k16_store_d_f32_col_stride
nvvm_wmma_m32n8k16_store_d_f16_row
nvvm_wmma_m32n8k16_store_d_f32_row
nvvm_wmma_m32n8k16_store_d_f16_row_stride
nvvm_wmma_m32n8k16_store_d_f32_row_stride
nvvm_wmma_m8n32k16_load_a_f16_col
nvvm_wmma_m8n32k16_load_a_f16_col_stride
nvvm_wmma_m8n32k16_load_a_f16_row
nvvm_wmma_m8n32k16_load_a_f16_row_stride
nvvm_wmma_m8n32k16_load_b_f16_col
nvvm_wmma_m8n32k16_load_b_f16_col_stride
nvvm_wmma_m8n32k16_load_b_f16_row
nvvm_wmma_m8n32k16_load_b_f16_row_stride
nvvm_wmma_m8n32k16_load_c_f16_col
nvvm_wmma_m8n32k16_load_c_f32_col
nvvm_wmma_m8n32k16_load_c_f16_col_stride
nvvm_wmma_m8n32k16_load_c_f32_col_stride
nvvm_wmma_m8n32k16_load_c_f16_row
nvvm_wmma_m8n32k16_load_c_f32_row
nvvm_wmma_m8n32k16_load_c_f16_row_stride
nvvm_wmma_m8n32k16_load_c_f32_row_stride
nvvm_wmma_m8n32k16_mma_col_col_f16_f16
nvvm_wmma_m8n32k16_mma_col_col_f16_f16_satfinite
nvvm_wmma_m8n32k16_mma_col_col_f16_f32
nvvm_wmma_m8n32k16_mma_col_col_f16_f32_satfinite
nvvm_wmma_m8n32k16_mma_col_col_f32_f16
nvvm_wmma_m8n32k16_mma_col_col_f32_f16_satfinite
nvvm_wmma_m8n32k16_mma_col_col_f32_f32
nvvm_wmma_m8n32k16_mma_col_col_f32_f32_satfinite
nvvm_wmma_m8n32k16_mma_col_row_f16_f16
nvvm_wmma_m8n32k16_mma_col_row_f16_f16_satfinite
nvvm_wmma_m8n32k16_mma_col_row_f16_f32
nvvm_wmma_m8n32k16_mma_col_row_f16_f32_satfinite
nvvm_wmma_m8n32k16_mma_col_row_f32_f16
nvvm_wmma_m8n32k16_mma_col_row_f32_f16_satfinite
nvvm_wmma_m8n32k16_mma_col_row_f32_f32
nvvm_wmma_m8n32k16_mma_col_row_f32_f32_satfinite
nvvm_wmma_m8n32k16_mma_row_col_f16_f16
nvvm_wmma_m8n32k16_mma_row_col_f16_f16_satfinite
nvvm_wmma_m8n32k16_mma_row_col_f16_f32
nvvm_wmma_m8n32k16_mma_row_col_f16_f32_satfinite
nvvm_wmma_m8n32k16_mma_row_col_f32_f16
nvvm_wmma_m8n32k16_mma_row_col_f32_f16_satfinite
nvvm_wmma_m8n32k16_mma_row_col_f32_f32
nvvm_wmma_m8n32k16_mma_row_col_f32_f32_satfinite
nvvm_wmma_m8n32k16_mma_row_row_f16_f16
nvvm_wmma_m8n32k16_mma_row_row_f16_f16_satfinite
nvvm_wmma_m8n32k16_mma_row_row_f16_f32
nvvm_wmma_m8n32k16_mma_row_row_f16_f32_satfinite
nvvm_wmma_m8n32k16_mma_row_row_f32_f16
nvvm_wmma_m8n32k16_mma_row_row_f32_f16_satfinite
nvvm_wmma_m8n32k16_mma_row_row_f32_f32
nvvm_wmma_m8n32k16_mma_row_row_f32_f32_satfinite
nvvm_wmma_m8n32k16_store_d_f16_col
nvvm_wmma_m8n32k16_store_d_f32_col
nvvm_wmma_m8n32k16_store_d_f16_col_stride
nvvm_wmma_m8n32k16_store_d_f32_col_stride
nvvm_wmma_m8n32k16_store_d_f16_row
nvvm_wmma_m8n32k16_store_d_f32_row
nvvm_wmma_m8n32k16_store_d_f16_row_stride
nvvm_wmma_m8n32k16_store_d_f32_row_stride
ppc_addf128_round_to_odd
ppc_altivec_crypto_vcipher
ppc_altivec_crypto_vcipherlast
ppc_altivec_crypto_vncipher
ppc_altivec_crypto_vncipherlast
ppc_altivec_crypto_vpermxor
ppc_altivec_crypto_vpmsumb
ppc_altivec_crypto_vpmsumd
ppc_altivec_crypto_vpmsumh
ppc_altivec_crypto_vpmsumw
ppc_altivec_crypto_vsbox
ppc_altivec_crypto_vshasigmad
ppc_altivec_crypto_vshasigmaw
ppc_altivec_dss
ppc_altivec_dssall
ppc_altivec_dst
ppc_altivec_dstst
ppc_altivec_dststt
ppc_altivec_dstt
ppc_altivec_lvebx
ppc_altivec_lvehx
ppc_altivec_lvewx
ppc_altivec_lvsl
ppc_altivec_lvsr
ppc_altivec_lvx
ppc_altivec_lvxl
ppc_altivec_mfvscr
ppc_altivec_mtvscr
ppc_altivec_stvebx
ppc_altivec_stvehx
ppc_altivec_stvewx
ppc_altivec_stvx
ppc_altivec_stvxl
ppc_altivec_vabsdub
ppc_altivec_vabsduh
ppc_altivec_vabsduw
ppc_altivec_vaddcuq
ppc_altivec_vaddcuw
ppc_altivec_vaddecuq
ppc_altivec_vaddeuqm
ppc_altivec_vaddsbs
ppc_altivec_vaddshs
ppc_altivec_vaddsws
ppc_altivec_vaddubs
ppc_altivec_vadduhs
ppc_altivec_vadduws
ppc_altivec_vavgsb
ppc_altivec_vavgsh
ppc_altivec_vavgsw
ppc_altivec_vavgub
ppc_altivec_vavguh
ppc_altivec_vavguw
ppc_altivec_vbpermq
ppc_altivec_vcfsx
ppc_altivec_vcfux
ppc_altivec_vclzlsbb
ppc_altivec_vcmpbfp
ppc_altivec_vcmpbfp_p
ppc_altivec_vcmpeqfp
ppc_altivec_vcmpeqfp_p
ppc_altivec_vcmpequb
ppc_altivec_vcmpequb_p
ppc_altivec_vcmpequd
ppc_altivec_vcmpequd_p
ppc_altivec_vcmpequh
ppc_altivec_vcmpequh_p
ppc_altivec_vcmpequw
ppc_altivec_vcmpequw_p
ppc_altivec_vcmpgefp
ppc_altivec_vcmpgefp_p
ppc_altivec_vcmpgtfp
ppc_altivec_vcmpgtfp_p
ppc_altivec_vcmpgtsb
ppc_altivec_vcmpgtsb_p
ppc_altivec_vcmpgtsd
ppc_altivec_vcmpgtsd_p
ppc_altivec_vcmpgtsh
ppc_altivec_vcmpgtsh_p
ppc_altivec_vcmpgtsw
ppc_altivec_vcmpgtsw_p
ppc_altivec_vcmpgtub
ppc_altivec_vcmpgtub_p
ppc_altivec_vcmpgtud
ppc_altivec_vcmpgtud_p
ppc_altivec_vcmpgtuh
ppc_altivec_vcmpgtuh_p
ppc_altivec_vcmpgtuw
ppc_altivec_vcmpgtuw_p
ppc_altivec_vcmpneb
ppc_altivec_vcmpneb_p
ppc_altivec_vcmpneh
ppc_altivec_vcmpneh_p
ppc_altivec_vcmpnew
ppc_altivec_vcmpnew_p
ppc_altivec_vcmpnezb
ppc_altivec_vcmpnezb_p
ppc_altivec_vcmpnezh
ppc_altivec_vcmpnezh_p
ppc_altivec_vcmpnezw
ppc_altivec_vcmpnezw_p
ppc_altivec_vctsxs
ppc_altivec_vctuxs
ppc_altivec_vctzlsbb
ppc_altivec_vexptefp
ppc_altivec_vgbbd
ppc_altivec_vlogefp
ppc_altivec_vmaddfp
ppc_altivec_vmaxfp
ppc_altivec_vmaxsb
ppc_altivec_vmaxsd
ppc_altivec_vmaxsh
ppc_altivec_vmaxsw
ppc_altivec_vmaxub
ppc_altivec_vmaxud
ppc_altivec_vmaxuh
ppc_altivec_vmaxuw
ppc_altivec_vmhaddshs
ppc_altivec_vmhraddshs
ppc_altivec_vminfp
ppc_altivec_vminsb
ppc_altivec_vminsd
ppc_altivec_vminsh
ppc_altivec_vminsw
ppc_altivec_vminub
ppc_altivec_vminud
ppc_altivec_vminuh
ppc_altivec_vminuw
ppc_altivec_vmladduhm
ppc_altivec_vmsummbm
ppc_altivec_vmsumshm
ppc_altivec_vmsumshs
ppc_altivec_vmsumubm
ppc_altivec_vmsumuhm
ppc_altivec_vmsumuhs
ppc_altivec_vmulesb
ppc_altivec_vmulesh
ppc_altivec_vmulesw
ppc_altivec_vmuleub
ppc_altivec_vmuleuh
ppc_altivec_vmuleuw
ppc_altivec_vmulosb
ppc_altivec_vmulosh
ppc_altivec_vmulosw
ppc_altivec_vmuloub
ppc_altivec_vmulouh
ppc_altivec_vmulouw
ppc_altivec_vnmsubfp
ppc_altivec_vperm
ppc_altivec_vpkpx
ppc_altivec_vpksdss
ppc_altivec_vpksdus
ppc_altivec_vpkshss
ppc_altivec_vpkshus
ppc_altivec_vpkswss
ppc_altivec_vpkswus
ppc_altivec_vpkudus
ppc_altivec_vpkuhus
ppc_altivec_vpkuwus
ppc_altivec_vprtybd
ppc_altivec_vprtybq
ppc_altivec_vprtybw
ppc_altivec_vrefp
ppc_altivec_vrfim
ppc_altivec_vrfin
ppc_altivec_vrfip
ppc_altivec_vrfiz
ppc_altivec_vrlb
ppc_altivec_vrld
ppc_altivec_vrldmi
ppc_altivec_vrldnm
ppc_altivec_vrlh
ppc_altivec_vrlw
ppc_altivec_vrlwmi
ppc_altivec_vrlwnm
ppc_altivec_vrsqrtefp
ppc_altivec_vsel
ppc_altivec_vsl
ppc_altivec_vslb
ppc_altivec_vslh
ppc_altivec_vslo
ppc_altivec_vslv
ppc_altivec_vslw
ppc_altivec_vsr
ppc_altivec_vsrab
ppc_altivec_vsrah
ppc_altivec_vsraw
ppc_altivec_vsrb
ppc_altivec_vsrh
ppc_altivec_vsro
ppc_altivec_vsrv
ppc_altivec_vsrw
ppc_altivec_vsubcuq
ppc_altivec_vsubcuw
ppc_altivec_vsubecuq
ppc_altivec_vsubeuqm
ppc_altivec_vsubsbs
ppc_altivec_vsubshs
ppc_altivec_vsubsws
ppc_altivec_vsububs
ppc_altivec_vsubuhs
ppc_altivec_vsubuws
ppc_altivec_vsum2sws
ppc_altivec_vsum4sbs
ppc_altivec_vsum4shs
ppc_altivec_vsum4ubs
ppc_altivec_vsumsws
ppc_altivec_vupkhpx
ppc_altivec_vupkhsb
ppc_altivec_vupkhsh
ppc_altivec_vupkhsw
ppc_altivec_vupklpx
ppc_altivec_vupklsb
ppc_altivec_vupklsh
ppc_altivec_vupklsw
ppc_bpermd
ppc_cfence
ppc_dcba
ppc_dcbf
ppc_dcbi
ppc_dcbst
ppc_dcbt
ppc_dcbtst
ppc_dcbz
ppc_dcbzl
ppc_divde
ppc_divdeu
ppc_divf128_round_to_odd
ppc_divwe
ppc_divweu
ppc_fmaf128_round_to_odd
ppc_get_texasr
ppc_get_texasru
ppc_get_tfhar
ppc_get_tfiar
ppc_is_decremented_ctr_nonzero
ppc_lwsync
ppc_mtctr
ppc_mulf128_round_to_odd
ppc_qpx_qvfabs
ppc_qpx_qvfadd
ppc_qpx_qvfadds
ppc_qpx_qvfcfid
ppc_qpx_qvfcfids
ppc_qpx_qvfcfidu
ppc_qpx_qvfcfidus
ppc_qpx_qvfcmpeq
ppc_qpx_qvfcmpgt
ppc_qpx_qvfcmplt
ppc_qpx_qvfcpsgn
ppc_qpx_qvfctid
ppc_qpx_qvfctidu
ppc_qpx_qvfctiduz
ppc_qpx_qvfctidz
ppc_qpx_qvfctiw
ppc_qpx_qvfctiwu
ppc_qpx_qvfctiwuz
ppc_qpx_qvfctiwz
ppc_qpx_qvflogical
ppc_qpx_qvfmadd
ppc_qpx_qvfmadds
ppc_qpx_qvfmsub
ppc_qpx_qvfmsubs
ppc_qpx_qvfmul
ppc_qpx_qvfmuls
ppc_qpx_qvfnabs
ppc_qpx_qvfneg
ppc_qpx_qvfnmadd
ppc_qpx_qvfnmadds
ppc_qpx_qvfnmsub
ppc_qpx_qvfnmsubs
ppc_qpx_qvfperm
ppc_qpx_qvfre
ppc_qpx_qvfres
ppc_qpx_qvfrim
ppc_qpx_qvfrin
ppc_qpx_qvfrip
ppc_qpx_qvfriz
ppc_qpx_qvfrsp
ppc_qpx_qvfrsqrte
ppc_qpx_qvfrsqrtes
ppc_qpx_qvfsel
ppc_qpx_qvfsub
ppc_qpx_qvfsubs
ppc_qpx_qvftstnan
ppc_qpx_qvfxmadd
ppc_qpx_qvfxmadds
ppc_qpx_qvfxmul
ppc_qpx_qvfxmuls
ppc_qpx_qvfxxcpnmadd
ppc_qpx_qvfxxcpnmadds
ppc_qpx_qvfxxmadd
ppc_qpx_qvfxxmadds
ppc_qpx_qvfxxnpmadd
ppc_qpx_qvfxxnpmadds
ppc_qpx_qvgpci
ppc_qpx_qvlfcd
ppc_qpx_qvlfcda
ppc_qpx_qvlfcs
ppc_qpx_qvlfcsa
ppc_qpx_qvlfd
ppc_qpx_qvlfda
ppc_qpx_qvlfiwa
ppc_qpx_qvlfiwaa
ppc_qpx_qvlfiwz
ppc_qpx_qvlfiwza
ppc_qpx_qvlfs
ppc_qpx_qvlfsa
ppc_qpx_qvlpcld
ppc_qpx_qvlpcls
ppc_qpx_qvlpcrd
ppc_qpx_qvlpcrs
ppc_qpx_qvstfcd
ppc_qpx_qvstfcda
ppc_qpx_qvstfcs
ppc_qpx_qvstfcsa
ppc_qpx_qvstfd
ppc_qpx_qvstfda
ppc_qpx_qvstfiw
ppc_qpx_qvstfiwa
ppc_qpx_qvstfs
ppc_qpx_qvstfsa
ppc_scalar_extract_expq
ppc_scalar_insert_exp_qp
ppc_set_texasr
ppc_set_texasru
ppc_set_tfhar
ppc_set_tfiar
ppc_sqrtf128_round_to_odd
ppc_subf128_round_to_odd
ppc_sync
ppc_tabort
ppc_tabortdc
ppc_tabortdci
ppc_tabortwc
ppc_tabortwci
ppc_tbegin
ppc_tcheck
ppc_tend
ppc_tendall
ppc_trechkpt
ppc_treclaim
ppc_tresume
ppc_truncf128_round_to_odd
ppc_tsr
ppc_tsuspend
ppc_ttest
ppc_vsx_lxvd2x
ppc_vsx_lxvd2x_be
ppc_vsx_lxvl
ppc_vsx_lxvll
ppc_vsx_lxvw4x
ppc_vsx_lxvw4x_be
ppc_vsx_stxvd2x
ppc_vsx_stxvd2x_be
ppc_vsx_stxvl
ppc_vsx_stxvll
ppc_vsx_stxvw4x
ppc_vsx_stxvw4x_be
ppc_vsx_xsmaxdp
ppc_vsx_xsmindp
ppc_vsx_xvcmpeqdp
ppc_vsx_xvcmpeqdp_p
ppc_vsx_xvcmpeqsp
ppc_vsx_xvcmpeqsp_p
ppc_vsx_xvcmpgedp
ppc_vsx_xvcmpgedp_p
ppc_vsx_xvcmpgesp
ppc_vsx_xvcmpgesp_p
ppc_vsx_xvcmpgtdp
ppc_vsx_xvcmpgtdp_p
ppc_vsx_xvcmpgtsp
ppc_vsx_xvcmpgtsp_p
ppc_vsx_xvcvdpsp
ppc_vsx_xvcvdpsxws
ppc_vsx_xvcvdpuxws
ppc_vsx_xvcvhpsp
ppc_vsx_xvcvspdp
ppc_vsx_xvcvsphp
ppc_vsx_xvcvsxdsp
ppc_vsx_xvcvsxwdp
ppc_vsx_xvcvuxdsp
ppc_vsx_xvcvuxwdp
ppc_vsx_xvdivdp
ppc_vsx_xvdivsp
ppc_vsx_xviexpdp
ppc_vsx_xviexpsp
ppc_vsx_xvmaxdp
ppc_vsx_xvmaxsp
ppc_vsx_xvmindp
ppc_vsx_xvminsp
ppc_vsx_xvrdpip
ppc_vsx_xvredp
ppc_vsx_xvresp
ppc_vsx_xvrspip
ppc_vsx_xvrsqrtedp
ppc_vsx_xvrsqrtesp
ppc_vsx_xvtstdcdp
ppc_vsx_xvtstdcsp
ppc_vsx_xvxexpdp
ppc_vsx_xvxexpsp
ppc_vsx_xvxsigdp
ppc_vsx_xvxsigsp
ppc_vsx_xxextractuw
ppc_vsx_xxinsertw
ppc_vsx_xxleqv
r600_cube
r600_ddx
r600_ddy
r600_dot4
r600_group_barrier
r600_implicitarg_ptr
r600_kill
r600_rat_store_typed
r600_read_global_size_x
r600_read_global_size_y
r600_read_global_size_z
r600_read_local_size_x
r600_read_local_size_y
r600_read_local_size_z
r600_read_ngroups_x
r600_read_ngroups_y
r600_read_ngroups_z
r600_read_tgid_x
r600_read_tgid_y
r600_read_tgid_z
r600_read_tidig_x
r600_read_tidig_y
r600_read_tidig_z
r600_recipsqrt_clamped
r600_recipsqrt_ieee
r600_store_stream_output
r600_store_swizzle
r600_tex
r600_texc
r600_txb
r600_txbc
r600_txf
r600_txl
r600_txlc
r600_txq
riscv_masked_atomicrmw_add_i32
riscv_masked_atomicrmw_max_i32
riscv_masked_atomicrmw_min_i32
riscv_masked_atomicrmw_nand_i32
riscv_masked_atomicrmw_sub_i32
riscv_masked_atomicrmw_umax_i32
riscv_masked_atomicrmw_umin_i32
riscv_masked_atomicrmw_xchg_i32
riscv_masked_cmpxchg_i32
s390_efpc
s390_etnd
s390_lcbb
s390_ntstg
s390_ppa_txassist
s390_sfpc
s390_tabort
s390_tbegin
s390_tbegin_nofloat
s390_tbeginc
s390_tdc
s390_tend
s390_vaccb
s390_vacccq
s390_vaccf
s390_vaccg
s390_vacch
s390_vaccq
s390_vacq
s390_vaq
s390_vavgb
s390_vavgf
s390_vavgg
s390_vavgh
s390_vavglb
s390_vavglf
s390_vavglg
s390_vavglh
s390_vbperm
s390_vceqbs
s390_vceqfs
s390_vceqgs
s390_vceqhs
s390_vchbs
s390_vchfs
s390_vchgs
s390_vchhs
s390_vchlbs
s390_vchlfs
s390_vchlgs
s390_vchlhs
s390_vcksm
s390_verimb
s390_verimf
s390_verimg
s390_verimh
s390_verllb
s390_verllf
s390_verllg
s390_verllh
s390_verllvb
s390_verllvf
s390_verllvg
s390_verllvh
s390_vfaeb
s390_vfaebs
s390_vfaef
s390_vfaefs
s390_vfaeh
s390_vfaehs
s390_vfaezb
s390_vfaezbs
s390_vfaezf
s390_vfaezfs
s390_vfaezh
s390_vfaezhs
s390_vfcedbs
s390_vfcesbs
s390_vfchdbs
s390_vfchedbs
s390_vfchesbs
s390_vfchsbs
s390_vfeeb
s390_vfeebs
s390_vfeef
s390_vfeefs
s390_vfeeh
s390_vfeehs
s390_vfeezb
s390_vfeezbs
s390_vfeezf
s390_vfeezfs
s390_vfeezh
s390_vfeezhs
s390_vfeneb
s390_vfenebs
s390_vfenef
s390_vfenefs
s390_vfeneh
s390_vfenehs
s390_vfenezb
s390_vfenezbs
s390_vfenezf
s390_vfenezfs
s390_vfenezh
s390_vfenezhs
s390_vfidb
s390_vfisb
s390_vfmaxdb
s390_vfmaxsb
s390_vfmindb
s390_vfminsb
s390_vftcidb
s390_vftcisb
s390_vgfmab
s390_vgfmaf
s390_vgfmag
s390_vgfmah
s390_vgfmb
s390_vgfmf
s390_vgfmg
s390_vgfmh
s390_vistrb
s390_vistrbs
s390_vistrf
s390_vistrfs
s390_vistrh
s390_vistrhs
s390_vlbb
s390_vll
s390_vlrl
s390_vmaeb
s390_vmaef
s390_vmaeh
s390_vmahb
s390_vmahf
s390_vmahh
s390_vmaleb
s390_vmalef
s390_vmaleh
s390_vmalhb
s390_vmalhf
s390_vmalhh
s390_vmalob
s390_vmalof
s390_vmaloh
s390_vmaob
s390_vmaof
s390_vmaoh
s390_vmeb
s390_vmef
s390_vmeh
s390_vmhb
s390_vmhf
s390_vmhh
s390_vmleb
s390_vmlef
s390_vmleh
s390_vmlhb
s390_vmlhf
s390_vmlhh
s390_vmlob
s390_vmlof
s390_vmloh
s390_vmob
s390_vmof
s390_vmoh
s390_vmslg
s390_vpdi
s390_vperm
s390_vpklsf
s390_vpklsfs
s390_vpklsg
s390_vpklsgs
s390_vpklsh
s390_vpklshs
s390_vpksf
s390_vpksfs
s390_vpksg
s390_vpksgs
s390_vpksh
s390_vpkshs
s390_vsbcbiq
s390_vsbiq
s390_vscbib
s390_vscbif
s390_vscbig
s390_vscbih
s390_vscbiq
s390_vsl
s390_vslb
s390_vsldb
s390_vsq
s390_vsra
s390_vsrab
s390_vsrl
s390_vsrlb
s390_vstl
s390_vstrcb
s390_vstrcbs
s390_vstrcf
s390_vstrcfs
s390_vstrch
s390_vstrchs
s390_vstrczb
s390_vstrczbs
s390_vstrczf
s390_vstrczfs
s390_vstrczh
s390_vstrczhs
s390_vstrl
s390_vsumb
s390_vsumgf
s390_vsumgh
s390_vsumh
s390_vsumqf
s390_vsumqg
s390_vtm
s390_vuphb
s390_vuphf
s390_vuphh
s390_vuplb
s390_vuplf
s390_vuplhb
s390_vuplhf
s390_vuplhh
s390_vuplhw
s390_vupllb
s390_vupllf
s390_vupllh
wasm_alltrue
wasm_anytrue
wasm_atomic_notify
wasm_atomic_wait_i32
wasm_atomic_wait_i64
wasm_bitselect
wasm_catch
wasm_get_ehselector
wasm_get_exception
wasm_landingpad_index
wasm_lsda
wasm_memory_grow
wasm_memory_size
wasm_rethrow
wasm_sub_saturate_signed
wasm_sub_saturate_unsigned
wasm_throw
wasm_trunc_saturate_signed
wasm_trunc_saturate_unsigned
x86_3dnow_pavgusb
x86_3dnow_pf2id
x86_3dnow_pfacc
x86_3dnow_pfadd
x86_3dnow_pfcmpeq
x86_3dnow_pfcmpge
x86_3dnow_pfcmpgt
x86_3dnow_pfmax
x86_3dnow_pfmin
x86_3dnow_pfmul
x86_3dnow_pfrcp
x86_3dnow_pfrcpit1
x86_3dnow_pfrcpit2
x86_3dnow_pfrsqit1
x86_3dnow_pfrsqrt
x86_3dnow_pfsub
x86_3dnow_pfsubr
x86_3dnow_pi2fd
x86_3dnow_pmulhrw
x86_3dnowa_pf2iw
x86_3dnowa_pfnacc
x86_3dnowa_pfpnacc
x86_3dnowa_pi2fw
x86_3dnowa_pswapd
x86_addcarry_32
x86_addcarry_64
x86_aesni_aesdec
x86_aesni_aesdec_256
x86_aesni_aesdec_512
x86_aesni_aesdeclast
x86_aesni_aesdeclast_256
x86_aesni_aesdeclast_512
x86_aesni_aesenc
x86_aesni_aesenc_256
x86_aesni_aesenc_512
x86_aesni_aesenclast
x86_aesni_aesenclast_256
x86_aesni_aesenclast_512
x86_aesni_aesimc
x86_aesni_aeskeygenassist
x86_avx_addsub_pd_256
x86_avx_addsub_ps_256
x86_avx_blendv_pd_256
x86_avx_blendv_ps_256
x86_avx_cmp_pd_256
x86_avx_cmp_ps_256
x86_avx_cvt_pd2_ps_256
x86_avx_cvt_pd2dq_256
x86_avx_cvt_ps2dq_256
x86_avx_cvtt_pd2dq_256
x86_avx_cvtt_ps2dq_256
x86_avx_dp_ps_256
x86_avx_hadd_pd_256
x86_avx_hadd_ps_256
x86_avx_hsub_pd_256
x86_avx_hsub_ps_256
x86_avx_ldu_dq_256
x86_avx_maskload_pd
x86_avx_maskload_pd_256
x86_avx_maskload_ps
x86_avx_maskload_ps_256
x86_avx_maskstore_pd
x86_avx_maskstore_pd_256
x86_avx_maskstore_ps
x86_avx_maskstore_ps_256
x86_avx_max_pd_256
x86_avx_max_ps_256
x86_avx_min_pd_256
x86_avx_min_ps_256
x86_avx_movmsk_pd_256
x86_avx_movmsk_ps_256
x86_avx_ptestc_256
x86_avx_ptestnzc_256
x86_avx_ptestz_256
x86_avx_rcp_ps_256
x86_avx_round_pd_256
x86_avx_round_ps_256
x86_avx_rsqrt_ps_256
x86_avx_vpermilvar_pd
x86_avx_vpermilvar_pd_256
x86_avx_vpermilvar_ps
x86_avx_vpermilvar_ps_256
x86_avx_vtestc_pd
x86_avx_vtestc_pd_256
x86_avx_vtestc_ps
x86_avx_vtestc_ps_256
x86_avx_vtestnzc_pd
x86_avx_vtestnzc_pd_256
x86_avx_vtestnzc_ps
x86_avx_vtestnzc_ps_256
x86_avx_vtestz_pd
x86_avx_vtestz_pd_256
x86_avx_vtestz_ps
x86_avx_vtestz_ps_256
x86_avx_vzeroall
x86_avx_vzeroupper
x86_avx2_gather_d_d
x86_avx2_gather_d_d_256
x86_avx2_gather_d_pd
x86_avx2_gather_d_pd_256
x86_avx2_gather_d_ps
x86_avx2_gather_d_ps_256
x86_avx2_gather_d_q
x86_avx2_gather_d_q_256
x86_avx2_gather_q_d
x86_avx2_gather_q_d_256
x86_avx2_gather_q_pd
x86_avx2_gather_q_pd_256
x86_avx2_gather_q_ps
x86_avx2_gather_q_ps_256
x86_avx2_gather_q_q
x86_avx2_gather_q_q_256
x86_avx2_maskload_d
x86_avx2_maskload_d_256
x86_avx2_maskload_q
x86_avx2_maskload_q_256
x86_avx2_maskstore_d
x86_avx2_maskstore_d_256
x86_avx2_maskstore_q
x86_avx2_maskstore_q_256
x86_avx2_mpsadbw
x86_avx2_packssdw
x86_avx2_packsswb
x86_avx2_packusdw
x86_avx2_packuswb
x86_avx2_pblendvb
x86_avx2_permd
x86_avx2_permps
x86_avx2_phadd_d
x86_avx2_phadd_sw
x86_avx2_phadd_w
x86_avx2_phsub_d
x86_avx2_phsub_sw
x86_avx2_phsub_w
x86_avx2_pmadd_ub_sw
x86_avx2_pmadd_wd
x86_avx2_pmovmskb
x86_avx2_pmul_hr_sw
x86_avx2_pmulh_w
x86_avx2_pmulhu_w
x86_avx2_psad_bw
x86_avx2_pshuf_b
x86_avx2_psign_b
x86_avx2_psign_d
x86_avx2_psign_w
x86_avx2_psll_d
x86_avx2_psll_q
x86_avx2_psll_w
x86_avx2_pslli_d
x86_avx2_pslli_q
x86_avx2_pslli_w
x86_avx2_psllv_d
x86_avx2_psllv_d_256
x86_avx2_psllv_q
x86_avx2_psllv_q_256
x86_avx2_psra_d
x86_avx2_psra_w
x86_avx2_psrai_d
x86_avx2_psrai_w
x86_avx2_psrav_d
x86_avx2_psrav_d_256
x86_avx2_psrl_d
x86_avx2_psrl_q
x86_avx2_psrl_w
x86_avx2_psrli_d
x86_avx2_psrli_q
x86_avx2_psrli_w
x86_avx2_psrlv_d
x86_avx2_psrlv_d_256
x86_avx2_psrlv_q
x86_avx2_psrlv_q_256
x86_avx512_add_pd_512
x86_avx512_add_ps_512
x86_avx512_broadcastmb_128
x86_avx512_broadcastmb_256
x86_avx512_broadcastmb_512
x86_avx512_broadcastmw_128
x86_avx512_broadcastmw_256
x86_avx512_broadcastmw_512
x86_avx512_cmp_pd_128
x86_avx512_cmp_pd_256
x86_avx512_cmp_pd_512
x86_avx512_cmp_ps_128
x86_avx512_cmp_ps_256
x86_avx512_cmp_ps_512
x86_avx512_cvtsi2sd64
x86_avx512_cvtsi2ss32
x86_avx512_cvtsi2ss64
x86_avx512_cvttsd2si
x86_avx512_cvttsd2si64
x86_avx512_cvttsd2usi
x86_avx512_cvttsd2usi64
x86_avx512_cvttss2si
x86_avx512_cvttss2si64
x86_avx512_cvttss2usi
x86_avx512_cvttss2usi64
x86_avx512_cvtusi2ss
x86_avx512_cvtusi642sd
x86_avx512_cvtusi642ss
x86_avx512_dbpsadbw_128
x86_avx512_dbpsadbw_256
x86_avx512_dbpsadbw_512
x86_avx512_div_pd_512
x86_avx512_div_ps_512
x86_avx512_exp2_pd
x86_avx512_exp2_ps
x86_avx512_fpclass_pd_128
x86_avx512_fpclass_pd_256
x86_avx512_fpclass_pd_512
x86_avx512_fpclass_ps_128
x86_avx512_fpclass_ps_256
x86_avx512_fpclass_ps_512
x86_avx512_gather_dpd_512
x86_avx512_gather_dpi_512
x86_avx512_gather_dpq_512
x86_avx512_gather_dps_512
x86_avx512_gather_qpd_512
x86_avx512_gather_qpi_512
x86_avx512_gather_qpq_512
x86_avx512_gather_qps_512
x86_avx512_gather3div2_df
x86_avx512_gather3div2_di
x86_avx512_gather3div4_df
x86_avx512_gather3div4_di
x86_avx512_gather3div4_sf
x86_avx512_gather3div4_si
x86_avx512_gather3div8_sf
x86_avx512_gather3div8_si
x86_avx512_gather3siv2_df
x86_avx512_gather3siv2_di
x86_avx512_gather3siv4_df
x86_avx512_gather3siv4_di
x86_avx512_gather3siv4_sf
x86_avx512_gather3siv4_si
x86_avx512_gather3siv8_sf
x86_avx512_gather3siv8_si
x86_avx512_gatherpf_dpd_512
x86_avx512_gatherpf_dps_512
x86_avx512_gatherpf_qpd_512
x86_avx512_gatherpf_qps_512
x86_avx512_kadd_b
x86_avx512_kadd_d
x86_avx512_kadd_q
x86_avx512_kadd_w
x86_avx512_ktestc_b
x86_avx512_ktestc_d
x86_avx512_ktestc_q
x86_avx512_ktestc_w
x86_avx512_ktestz_b
x86_avx512_ktestz_d
x86_avx512_ktestz_q
x86_avx512_ktestz_w
x86_avx512_mask_add_sd_round
x86_avx512_mask_add_ss_round
x86_avx512_mask_cmp_sd
x86_avx512_mask_cmp_ss
x86_avx512_mask_compress_b_128
x86_avx512_mask_compress_b_256
x86_avx512_mask_compress_b_512
x86_avx512_mask_compress_d_128
x86_avx512_mask_compress_d_256
x86_avx512_mask_compress_d_512
x86_avx512_mask_compress_pd_128
x86_avx512_mask_compress_pd_256
x86_avx512_mask_compress_pd_512
x86_avx512_mask_compress_ps_128
x86_avx512_mask_compress_ps_256
x86_avx512_mask_compress_ps_512
x86_avx512_mask_compress_q_128
x86_avx512_mask_compress_q_256
x86_avx512_mask_compress_q_512
x86_avx512_mask_compress_w_128
x86_avx512_mask_compress_w_256
x86_avx512_mask_compress_w_512
x86_avx512_mask_conflict_d_128
x86_avx512_mask_conflict_d_256
x86_avx512_mask_conflict_d_512
x86_avx512_mask_conflict_q_128
x86_avx512_mask_conflict_q_256
x86_avx512_mask_conflict_q_512
x86_avx512_mask_cvtdq2ps_512
x86_avx512_mask_cvtpd2dq_128
x86_avx512_mask_cvtpd2dq_512
x86_avx512_mask_cvtpd2ps
x86_avx512_mask_cvtpd2ps_512
x86_avx512_mask_cvtpd2qq_128
x86_avx512_mask_cvtpd2qq_256
x86_avx512_mask_cvtpd2qq_512
x86_avx512_mask_cvtpd2udq_128
x86_avx512_mask_cvtpd2udq_256
x86_avx512_mask_cvtpd2udq_512
x86_avx512_mask_cvtpd2uqq_128
x86_avx512_mask_cvtpd2uqq_256
x86_avx512_mask_cvtpd2uqq_512
x86_avx512_mask_cvtps2dq_128
x86_avx512_mask_cvtps2dq_256
x86_avx512_mask_cvtps2dq_512
x86_avx512_mask_cvtps2pd_512
x86_avx512_mask_cvtps2qq_128
x86_avx512_mask_cvtps2qq_256
x86_avx512_mask_cvtps2qq_512
x86_avx512_mask_cvtps2udq_128
x86_avx512_mask_cvtps2udq_256
x86_avx512_mask_cvtps2udq_512
x86_avx512_mask_cvtps2uqq_128
x86_avx512_mask_cvtps2uqq_256
x86_avx512_mask_cvtps2uqq_512
x86_avx512_mask_cvtqq2pd_512
x86_avx512_mask_cvtqq2ps_128
x86_avx512_mask_cvtqq2ps_256
x86_avx512_mask_cvtqq2ps_512
x86_avx512_mask_cvtsd2ss_round
x86_avx512_mask_cvtss2sd_round
x86_avx512_mask_cvttpd2dq_128
x86_avx512_mask_cvttpd2dq_512
x86_avx512_mask_cvttpd2qq_128
x86_avx512_mask_cvttpd2qq_256
x86_avx512_mask_cvttpd2qq_512
x86_avx512_mask_cvttpd2udq_128
x86_avx512_mask_cvttpd2udq_256
x86_avx512_mask_cvttpd2udq_512
x86_avx512_mask_cvttpd2uqq_128
x86_avx512_mask_cvttpd2uqq_256
x86_avx512_mask_cvttpd2uqq_512
x86_avx512_mask_cvttps2dq_512
x86_avx512_mask_cvttps2qq_128
x86_avx512_mask_cvttps2qq_256
x86_avx512_mask_cvttps2qq_512
x86_avx512_mask_cvttps2udq_128
x86_avx512_mask_cvttps2udq_256
x86_avx512_mask_cvttps2udq_512
x86_avx512_mask_cvttps2uqq_128
x86_avx512_mask_cvttps2uqq_256
x86_avx512_mask_cvttps2uqq_512
x86_avx512_mask_cvtudq2ps_512
x86_avx512_mask_cvtuqq2pd_512
x86_avx512_mask_cvtuqq2ps_128
x86_avx512_mask_cvtuqq2ps_256
x86_avx512_mask_cvtuqq2ps_512
x86_avx512_mask_div_sd_round
x86_avx512_mask_div_ss_round
x86_avx512_mask_expand_b_128
x86_avx512_mask_expand_b_256
x86_avx512_mask_expand_b_512
x86_avx512_mask_expand_d_128
x86_avx512_mask_expand_d_256
x86_avx512_mask_expand_d_512
x86_avx512_mask_expand_pd_128
x86_avx512_mask_expand_pd_256
x86_avx512_mask_expand_pd_512
x86_avx512_mask_expand_ps_128
x86_avx512_mask_expand_ps_256
x86_avx512_mask_expand_ps_512
x86_avx512_mask_expand_q_128
x86_avx512_mask_expand_q_256
x86_avx512_mask_expand_q_512
x86_avx512_mask_expand_w_128
x86_avx512_mask_expand_w_256
x86_avx512_mask_expand_w_512
x86_avx512_mask_fixupimm_pd_128
x86_avx512_mask_fixupimm_pd_256
x86_avx512_mask_fixupimm_pd_512
x86_avx512_mask_fixupimm_ps_128
x86_avx512_mask_fixupimm_ps_256
x86_avx512_mask_fixupimm_ps_512
x86_avx512_mask_fixupimm_sd
x86_avx512_mask_fixupimm_ss
x86_avx512_mask_fpclass_sd
x86_avx512_mask_fpclass_ss
x86_avx512_mask_gather_dpd_512
x86_avx512_mask_gather_dpi_512
x86_avx512_mask_gather_dpq_512
x86_avx512_mask_gather_dps_512
x86_avx512_mask_gather_qpd_512
x86_avx512_mask_gather_qpi_512
x86_avx512_mask_gather_qpq_512
x86_avx512_mask_gather_qps_512
x86_avx512_mask_gather3div2_df
x86_avx512_mask_gather3div2_di
x86_avx512_mask_gather3div4_df
x86_avx512_mask_gather3div4_di
x86_avx512_mask_gather3div4_sf
x86_avx512_mask_gather3div4_si
x86_avx512_mask_gather3div8_sf
x86_avx512_mask_gather3div8_si
x86_avx512_mask_gather3siv2_df
x86_avx512_mask_gather3siv2_di
x86_avx512_mask_gather3siv4_df
x86_avx512_mask_gather3siv4_di
x86_avx512_mask_gather3siv4_sf
x86_avx512_mask_gather3siv4_si
x86_avx512_mask_gather3siv8_sf
x86_avx512_mask_gather3siv8_si
x86_avx512_mask_getexp_pd_128
x86_avx512_mask_getexp_pd_256
x86_avx512_mask_getexp_pd_512
x86_avx512_mask_getexp_ps_128
x86_avx512_mask_getexp_ps_256
x86_avx512_mask_getexp_ps_512
x86_avx512_mask_getexp_sd
x86_avx512_mask_getexp_ss
x86_avx512_mask_getmant_pd_128
x86_avx512_mask_getmant_pd_256
x86_avx512_mask_getmant_pd_512
x86_avx512_mask_getmant_ps_128
x86_avx512_mask_getmant_ps_256
x86_avx512_mask_getmant_ps_512
x86_avx512_mask_getmant_sd
x86_avx512_mask_getmant_ss
x86_avx512_mask_max_sd_round
x86_avx512_mask_max_ss_round
x86_avx512_mask_min_sd_round
x86_avx512_mask_min_ss_round
x86_avx512_mask_mul_sd_round
x86_avx512_mask_mul_ss_round
x86_avx512_mask_pmov_db_128
x86_avx512_mask_pmov_db_256
x86_avx512_mask_pmov_db_512
x86_avx512_mask_pmov_db_mem_128
x86_avx512_mask_pmov_db_mem_256
x86_avx512_mask_pmov_db_mem_512
x86_avx512_mask_pmov_dw_128
x86_avx512_mask_pmov_dw_256
x86_avx512_mask_pmov_dw_512
x86_avx512_mask_pmov_dw_mem_128
x86_avx512_mask_pmov_dw_mem_256
x86_avx512_mask_pmov_dw_mem_512
x86_avx512_mask_pmov_qb_128
x86_avx512_mask_pmov_qb_256
x86_avx512_mask_pmov_qb_512
x86_avx512_mask_pmov_qb_mem_128
x86_avx512_mask_pmov_qb_mem_256
x86_avx512_mask_pmov_qb_mem_512
x86_avx512_mask_pmov_qd_128
x86_avx512_mask_pmov_qd_256
x86_avx512_mask_pmov_qd_512
x86_avx512_mask_pmov_qd_mem_128
x86_avx512_mask_pmov_qd_mem_256
x86_avx512_mask_pmov_qd_mem_512
x86_avx512_mask_pmov_qw_128
x86_avx512_mask_pmov_qw_256
x86_avx512_mask_pmov_qw_512
x86_avx512_mask_pmov_qw_mem_128
x86_avx512_mask_pmov_qw_mem_256
x86_avx512_mask_pmov_qw_mem_512
x86_avx512_mask_pmov_wb_128
x86_avx512_mask_pmov_wb_256
x86_avx512_mask_pmov_wb_512
x86_avx512_mask_pmov_wb_mem_128
x86_avx512_mask_pmov_wb_mem_256
x86_avx512_mask_pmov_wb_mem_512
x86_avx512_mask_pmovs_db_128
x86_avx512_mask_pmovs_db_256
x86_avx512_mask_pmovs_db_512
x86_avx512_mask_pmovs_db_mem_128
x86_avx512_mask_pmovs_db_mem_256
x86_avx512_mask_pmovs_db_mem_512
x86_avx512_mask_pmovs_dw_128
x86_avx512_mask_pmovs_dw_256
x86_avx512_mask_pmovs_dw_512
x86_avx512_mask_pmovs_dw_mem_128
x86_avx512_mask_pmovs_dw_mem_256
x86_avx512_mask_pmovs_dw_mem_512
x86_avx512_mask_pmovs_qb_128
x86_avx512_mask_pmovs_qb_256
x86_avx512_mask_pmovs_qb_512
x86_avx512_mask_pmovs_qb_mem_128
x86_avx512_mask_pmovs_qb_mem_256
x86_avx512_mask_pmovs_qb_mem_512
x86_avx512_mask_pmovs_qd_128
x86_avx512_mask_pmovs_qd_256
x86_avx512_mask_pmovs_qd_512
x86_avx512_mask_pmovs_qd_mem_128
x86_avx512_mask_pmovs_qd_mem_256
x86_avx512_mask_pmovs_qd_mem_512
x86_avx512_mask_pmovs_qw_128
x86_avx512_mask_pmovs_qw_256
x86_avx512_mask_pmovs_qw_512
x86_avx512_mask_pmovs_qw_mem_128
x86_avx512_mask_pmovs_qw_mem_256
x86_avx512_mask_pmovs_qw_mem_512
x86_avx512_mask_pmovs_wb_128
x86_avx512_mask_pmovs_wb_256
x86_avx512_mask_pmovs_wb_512
x86_avx512_mask_pmovs_wb_mem_128
x86_avx512_mask_pmovs_wb_mem_256
x86_avx512_mask_pmovs_wb_mem_512
x86_avx512_mask_pmovus_db_128
x86_avx512_mask_pmovus_db_256
x86_avx512_mask_pmovus_db_512
x86_avx512_mask_pmovus_db_mem_128
x86_avx512_mask_pmovus_db_mem_256
x86_avx512_mask_pmovus_db_mem_512
x86_avx512_mask_pmovus_dw_128
x86_avx512_mask_pmovus_dw_256
x86_avx512_mask_pmovus_dw_512
x86_avx512_mask_pmovus_dw_mem_128
x86_avx512_mask_pmovus_dw_mem_256
x86_avx512_mask_pmovus_dw_mem_512
x86_avx512_mask_pmovus_qb_128
x86_avx512_mask_pmovus_qb_256
x86_avx512_mask_pmovus_qb_512
x86_avx512_mask_pmovus_qb_mem_128
x86_avx512_mask_pmovus_qb_mem_256
x86_avx512_mask_pmovus_qb_mem_512
x86_avx512_mask_pmovus_qd_128
x86_avx512_mask_pmovus_qd_256
x86_avx512_mask_pmovus_qd_512
x86_avx512_mask_pmovus_qd_mem_128
x86_avx512_mask_pmovus_qd_mem_256
x86_avx512_mask_pmovus_qd_mem_512
x86_avx512_mask_pmovus_qw_128
x86_avx512_mask_pmovus_qw_256
x86_avx512_mask_pmovus_qw_512
x86_avx512_mask_pmovus_qw_mem_128
x86_avx512_mask_pmovus_qw_mem_256
x86_avx512_mask_pmovus_qw_mem_512
x86_avx512_mask_pmovus_wb_128
x86_avx512_mask_pmovus_wb_256
x86_avx512_mask_pmovus_wb_512
x86_avx512_mask_pmovus_wb_mem_128
x86_avx512_mask_pmovus_wb_mem_256
x86_avx512_mask_pmovus_wb_mem_512
x86_avx512_mask_range_pd_128
x86_avx512_mask_range_pd_256
x86_avx512_mask_range_pd_512
x86_avx512_mask_range_ps_128
x86_avx512_mask_range_ps_256
x86_avx512_mask_range_ps_512
x86_avx512_mask_range_sd
x86_avx512_mask_range_ss
x86_avx512_mask_reduce_pd_128
x86_avx512_mask_reduce_pd_256
x86_avx512_mask_reduce_pd_512
x86_avx512_mask_reduce_ps_128
x86_avx512_mask_reduce_ps_256
x86_avx512_mask_reduce_ps_512
x86_avx512_mask_reduce_sd
x86_avx512_mask_reduce_ss
x86_avx512_mask_rndscale_pd_128
x86_avx512_mask_rndscale_pd_256
x86_avx512_mask_rndscale_pd_512
x86_avx512_mask_rndscale_ps_128
x86_avx512_mask_rndscale_ps_256
x86_avx512_mask_rndscale_ps_512
x86_avx512_mask_rndscale_sd
x86_avx512_mask_rndscale_ss
x86_avx512_mask_scalef_pd_128
x86_avx512_mask_scalef_pd_256
x86_avx512_mask_scalef_pd_512
x86_avx512_mask_scalef_ps_128
x86_avx512_mask_scalef_ps_256
x86_avx512_mask_scalef_ps_512
x86_avx512_mask_scalef_sd
x86_avx512_mask_scalef_ss
x86_avx512_mask_scatter_dpd_512
x86_avx512_mask_scatter_dpi_512
x86_avx512_mask_scatter_dpq_512
x86_avx512_mask_scatter_dps_512
x86_avx512_mask_scatter_qpd_512
x86_avx512_mask_scatter_qpi_512
x86_avx512_mask_scatter_qpq_512
x86_avx512_mask_scatter_qps_512
x86_avx512_mask_scatterdiv2_df
x86_avx512_mask_scatterdiv2_di
x86_avx512_mask_scatterdiv4_df
x86_avx512_mask_scatterdiv4_di
x86_avx512_mask_scatterdiv4_sf
x86_avx512_mask_scatterdiv4_si
x86_avx512_mask_scatterdiv8_sf
x86_avx512_mask_scatterdiv8_si
x86_avx512_mask_scattersiv2_df
x86_avx512_mask_scattersiv2_di
x86_avx512_mask_scattersiv4_df
x86_avx512_mask_scattersiv4_di
x86_avx512_mask_scattersiv4_sf
x86_avx512_mask_scattersiv4_si
x86_avx512_mask_scattersiv8_sf
x86_avx512_mask_scattersiv8_si
x86_avx512_mask_sqrt_sd
x86_avx512_mask_sqrt_ss
x86_avx512_mask_sub_sd_round
x86_avx512_mask_sub_ss_round
x86_avx512_mask_vcvtph2ps_128
x86_avx512_mask_vcvtph2ps_256
x86_avx512_mask_vcvtph2ps_512
x86_avx512_mask_vcvtps2ph_128
x86_avx512_mask_vcvtps2ph_256
x86_avx512_mask_vcvtps2ph_512
x86_avx512_maskz_fixupimm_pd_128
x86_avx512_maskz_fixupimm_pd_256
x86_avx512_maskz_fixupimm_pd_512
x86_avx512_maskz_fixupimm_ps_128
x86_avx512_maskz_fixupimm_ps_256
x86_avx512_maskz_fixupimm_ps_512
x86_avx512_maskz_fixupimm_sd
x86_avx512_maskz_fixupimm_ss
x86_avx512_max_pd_512
x86_avx512_max_ps_512
x86_avx512_min_pd_512
x86_avx512_min_ps_512
x86_avx512_mul_pd_512
x86_avx512_mul_ps_512
x86_avx512_packssdw_512
x86_avx512_packsswb_512
x86_avx512_packusdw_512
x86_avx512_packuswb_512
x86_avx512_permvar_df_256
x86_avx512_permvar_df_512
x86_avx512_permvar_di_256
x86_avx512_permvar_di_512
x86_avx512_permvar_hi_128
x86_avx512_permvar_hi_256
x86_avx512_permvar_hi_512
x86_avx512_permvar_qi_128
x86_avx512_permvar_qi_256
x86_avx512_permvar_qi_512
x86_avx512_permvar_sf_512
x86_avx512_permvar_si_512
x86_avx512_pmaddubs_w_512
x86_avx512_pmaddw_d_512
x86_avx512_pmul_hr_sw_512
x86_avx512_pmulh_w_512
x86_avx512_pmulhu_w_512
x86_avx512_pmultishift_qb_128
x86_avx512_pmultishift_qb_256
x86_avx512_pmultishift_qb_512
x86_avx512_psad_bw_512
x86_avx512_pshuf_b_512
x86_avx512_psll_d_512
x86_avx512_psll_q_512
x86_avx512_psll_w_512
x86_avx512_pslli_d_512
x86_avx512_pslli_q_512
x86_avx512_pslli_w_512
x86_avx512_psllv_d_512
x86_avx512_psllv_q_512
x86_avx512_psllv_w_128
x86_avx512_psllv_w_256
x86_avx512_psllv_w_512
x86_avx512_psra_d_512
x86_avx512_psra_q_128
x86_avx512_psra_q_256
x86_avx512_psra_q_512
x86_avx512_psra_w_512
x86_avx512_psrai_d_512
x86_avx512_psrai_q_128
x86_avx512_psrai_q_256
x86_avx512_psrai_q_512
x86_avx512_psrai_w_512
x86_avx512_psrav_d_512
x86_avx512_psrav_q_128
x86_avx512_psrav_q_256
x86_avx512_psrav_q_512
x86_avx512_psrav_w_128
x86_avx512_psrav_w_256
x86_avx512_psrav_w_512
x86_avx512_psrl_d_512
x86_avx512_psrl_q_512
x86_avx512_psrl_w_512
x86_avx512_psrli_d_512
x86_avx512_psrli_q_512
x86_avx512_psrli_w_512
x86_avx512_psrlv_d_512
x86_avx512_psrlv_q_512
x86_avx512_psrlv_w_128
x86_avx512_psrlv_w_256
x86_avx512_psrlv_w_512
x86_avx512_pternlog_d_128
x86_avx512_pternlog_d_256
x86_avx512_pternlog_d_512
x86_avx512_pternlog_q_128
x86_avx512_pternlog_q_256
x86_avx512_pternlog_q_512
x86_avx512_rcp14_pd_128
x86_avx512_rcp14_pd_256
x86_avx512_rcp14_pd_512
x86_avx512_rcp14_ps_128
x86_avx512_rcp14_ps_256
x86_avx512_rcp14_ps_512
x86_avx512_rcp14_sd
x86_avx512_rcp14_ss
x86_avx512_rcp28_pd
x86_avx512_rcp28_ps
x86_avx512_rcp28_sd
x86_avx512_rcp28_ss
x86_avx512_rsqrt14_pd_128
x86_avx512_rsqrt14_pd_256
x86_avx512_rsqrt14_pd_512
x86_avx512_rsqrt14_ps_128
x86_avx512_rsqrt14_ps_256
x86_avx512_rsqrt14_ps_512
x86_avx512_rsqrt14_sd
x86_avx512_rsqrt14_ss
x86_avx512_rsqrt28_pd
x86_avx512_rsqrt28_ps
x86_avx512_rsqrt28_sd
x86_avx512_rsqrt28_ss
x86_avx512_scatter_dpd_512
x86_avx512_scatter_dpi_512
x86_avx512_scatter_dpq_512
x86_avx512_scatter_dps_512
x86_avx512_scatter_qpd_512
x86_avx512_scatter_qpi_512
x86_avx512_scatter_qpq_512
x86_avx512_scatter_qps_512
x86_avx512_scatterdiv2_df
x86_avx512_scatterdiv2_di
x86_avx512_scatterdiv4_df
x86_avx512_scatterdiv4_di
x86_avx512_scatterdiv4_sf
x86_avx512_scatterdiv4_si
x86_avx512_scatterdiv8_sf
x86_avx512_scatterdiv8_si
x86_avx512_scatterpf_dpd_512
x86_avx512_scatterpf_dps_512
x86_avx512_scatterpf_qpd_512
x86_avx512_scatterpf_qps_512
x86_avx512_scattersiv2_df
x86_avx512_scattersiv2_di
x86_avx512_scattersiv4_df
x86_avx512_scattersiv4_di
x86_avx512_scattersiv4_sf
x86_avx512_scattersiv4_si
x86_avx512_scattersiv8_sf
x86_avx512_scattersiv8_si
x86_avx512_sqrt_pd_512
x86_avx512_sqrt_ps_512
x86_avx512_sub_pd_512
x86_avx512_sub_ps_512
x86_avx512_vcomi_sd
x86_avx512_vcomi_ss
x86_avx512_vcvtsd2si32
x86_avx512_vcvtsd2si64
x86_avx512_vcvtsd2usi32
x86_avx512_vcvtsd2usi64
x86_avx512_vcvtss2si32
x86_avx512_vcvtss2si64
x86_avx512_vcvtss2usi32
x86_avx512_vcvtss2usi64
x86_avx512_vfmadd_f32
x86_avx512_vfmadd_f64
x86_avx512_vfmadd_pd_512
x86_avx512_vfmadd_ps_512
x86_avx512_vfmaddsub_pd_512
x86_avx512_vfmaddsub_ps_512
x86_avx512_vpdpbusd_128
x86_avx512_vpdpbusd_256
x86_avx512_vpdpbusd_512
x86_avx512_vpdpbusds_128
x86_avx512_vpdpbusds_256
x86_avx512_vpdpbusds_512
x86_avx512_vpdpwssd_128
x86_avx512_vpdpwssd_256
x86_avx512_vpdpwssd_512
x86_avx512_vpdpwssds_128
x86_avx512_vpdpwssds_256
x86_avx512_vpdpwssds_512
x86_avx512_vpermi2var_d_128
x86_avx512_vpermi2var_d_256
x86_avx512_vpermi2var_d_512
x86_avx512_vpermi2var_hi_128
x86_avx512_vpermi2var_hi_256
x86_avx512_vpermi2var_hi_512
x86_avx512_vpermi2var_pd_128
x86_avx512_vpermi2var_pd_256
x86_avx512_vpermi2var_pd_512
x86_avx512_vpermi2var_ps_128
x86_avx512_vpermi2var_ps_256
x86_avx512_vpermi2var_ps_512
x86_avx512_vpermi2var_q_128
x86_avx512_vpermi2var_q_256
x86_avx512_vpermi2var_q_512
x86_avx512_vpermi2var_qi_128
x86_avx512_vpermi2var_qi_256
x86_avx512_vpermi2var_qi_512
x86_avx512_vpermilvar_pd_512
x86_avx512_vpermilvar_ps_512
x86_avx512_vpmadd52h_uq_128
x86_avx512_vpmadd52h_uq_256
x86_avx512_vpmadd52h_uq_512
x86_avx512_vpmadd52l_uq_128
x86_avx512_vpmadd52l_uq_256
x86_avx512_vpmadd52l_uq_512
x86_avx512_vpshufbitqmb_128
x86_avx512_vpshufbitqmb_256
x86_avx512_vpshufbitqmb_512
x86_bmi_bextr_32
x86_bmi_bextr_64
x86_bmi_bzhi_32
x86_bmi_bzhi_64
x86_bmi_pdep_32
x86_bmi_pdep_64
x86_bmi_pext_32
x86_bmi_pext_64
x86_cldemote
x86_clflushopt
x86_clrssbsy
x86_clwb
x86_clzero
x86_directstore32
x86_directstore64
x86_flags_read_u32
x86_flags_read_u64
x86_flags_write_u32
x86_flags_write_u64
x86_fxrstor
x86_fxrstor64
x86_fxsave
x86_fxsave64
x86_incsspd
x86_incsspq
x86_int
x86_invpcid
x86_llwpcb
x86_lwpins32
x86_lwpins64
x86_lwpval32
x86_lwpval64
x86_mmx_emms
x86_mmx_femms
x86_mmx_maskmovq
x86_mmx_movnt_dq
x86_mmx_packssdw
x86_mmx_packsswb
x86_mmx_packuswb
x86_mmx_padd_b
x86_mmx_padd_d
x86_mmx_padd_q
x86_mmx_padd_w
x86_mmx_padds_b
x86_mmx_padds_w
x86_mmx_paddus_b
x86_mmx_paddus_w
x86_mmx_palignr_b
x86_mmx_pand
x86_mmx_pandn
x86_mmx_pavg_b
x86_mmx_pavg_w
x86_mmx_pcmpeq_b
x86_mmx_pcmpeq_d
x86_mmx_pcmpeq_w
x86_mmx_pcmpgt_b
x86_mmx_pcmpgt_d
x86_mmx_pcmpgt_w
x86_mmx_pextr_w
x86_mmx_pinsr_w
x86_mmx_pmadd_wd
x86_mmx_pmaxs_w
x86_mmx_pmaxu_b
x86_mmx_pmins_w
x86_mmx_pminu_b
x86_mmx_pmovmskb
x86_mmx_pmulh_w
x86_mmx_pmulhu_w
x86_mmx_pmull_w
x86_mmx_pmulu_dq
x86_mmx_por
x86_mmx_psad_bw
x86_mmx_psll_d
x86_mmx_psll_q
x86_mmx_psll_w
x86_mmx_pslli_d
x86_mmx_pslli_q
x86_mmx_pslli_w
x86_mmx_psra_d
x86_mmx_psra_w
x86_mmx_psrai_d
x86_mmx_psrai_w
x86_mmx_psrl_d
x86_mmx_psrl_q
x86_mmx_psrl_w
x86_mmx_psrli_d
x86_mmx_psrli_q
x86_mmx_psrli_w
x86_mmx_psub_b
x86_mmx_psub_d
x86_mmx_psub_q
x86_mmx_psub_w
x86_mmx_psubs_b
x86_mmx_psubs_w
x86_mmx_psubus_b
x86_mmx_psubus_w
x86_mmx_punpckhbw
x86_mmx_punpckhdq
x86_mmx_punpckhwd
x86_mmx_punpcklbw
x86_mmx_punpckldq
x86_mmx_punpcklwd
x86_mmx_pxor
x86_monitorx
x86_movdir64b
x86_mwaitx
x86_pclmulqdq
x86_pclmulqdq_256
x86_pclmulqdq_512
x86_ptwrite32
x86_ptwrite64
x86_rdfsbase_32
x86_rdfsbase_64
x86_rdgsbase_32
x86_rdgsbase_64
x86_rdpid
x86_rdpkru
x86_rdpmc
x86_rdrand_16
x86_rdrand_32
x86_rdrand_64
x86_rdseed_16
x86_rdseed_32
x86_rdseed_64
x86_rdsspd
x86_rdsspq
x86_rdtsc
x86_rdtscp
x86_rstorssp
x86_saveprevssp
x86_seh_ehguard
x86_seh_ehregnode
x86_seh_lsda
x86_setssbsy
x86_sha1msg1
x86_sha1msg2
x86_sha1nexte
x86_sha1rnds4
x86_sha256msg1
x86_sha256msg2
x86_sha256rnds2
x86_slwpcb
x86_sse_cmp_ps
x86_sse_cmp_ss
x86_sse_comieq_ss
x86_sse_comige_ss
x86_sse_comigt_ss
x86_sse_comile_ss
x86_sse_comilt_ss
x86_sse_comineq_ss
x86_sse_cvtpd2pi
x86_sse_cvtpi2pd
x86_sse_cvtpi2ps
x86_sse_cvtps2pi
x86_sse_cvtss2si
x86_sse_cvtss2si64
x86_sse_cvttpd2pi
x86_sse_cvttps2pi
x86_sse_cvttss2si
x86_sse_cvttss2si64
x86_sse_ldmxcsr
x86_sse_max_ps
x86_sse_max_ss
x86_sse_min_ps
x86_sse_min_ss
x86_sse_movmsk_ps
x86_sse_pshuf_w
x86_sse_rcp_ps
x86_sse_rcp_ss
x86_sse_rsqrt_ps
x86_sse_rsqrt_ss
x86_sse_sfence
x86_sse_stmxcsr
x86_sse_ucomieq_ss
x86_sse_ucomige_ss
x86_sse_ucomigt_ss
x86_sse_ucomile_ss
x86_sse_ucomilt_ss
x86_sse_ucomineq_ss
x86_sse2_clflush
x86_sse2_cmp_pd
x86_sse2_cmp_sd
x86_sse2_comieq_sd
x86_sse2_comige_sd
x86_sse2_comigt_sd
x86_sse2_comile_sd
x86_sse2_comilt_sd
x86_sse2_comineq_sd
x86_sse2_cvtpd2dq
x86_sse2_cvtpd2ps
x86_sse2_cvtps2dq
x86_sse2_cvtsd2si
x86_sse2_cvtsd2si64
x86_sse2_cvtsd2ss
x86_sse2_cvttpd2dq
x86_sse2_cvttps2dq
x86_sse2_cvttsd2si
x86_sse2_cvttsd2si64
x86_sse2_lfence
x86_sse2_maskmov_dqu
x86_sse2_max_pd
x86_sse2_max_sd
x86_sse2_mfence
x86_sse2_min_pd
x86_sse2_min_sd
x86_sse2_movmsk_pd
x86_sse2_packssdw_128
x86_sse2_packsswb_128
x86_sse2_packuswb_128
x86_sse2_pause
x86_sse2_pmadd_wd
x86_sse2_pmovmskb_128
x86_sse2_pmulh_w
x86_sse2_pmulhu_w
x86_sse2_psad_bw
x86_sse2_psll_d
x86_sse2_psll_q
x86_sse2_psll_w
x86_sse2_pslli_d
x86_sse2_pslli_q
x86_sse2_pslli_w
x86_sse2_psra_d
x86_sse2_psra_w
x86_sse2_psrai_d
x86_sse2_psrai_w
x86_sse2_psrl_d
x86_sse2_psrl_q
x86_sse2_psrl_w
x86_sse2_psrli_d
x86_sse2_psrli_q
x86_sse2_psrli_w
x86_sse2_ucomieq_sd
x86_sse2_ucomige_sd
x86_sse2_ucomigt_sd
x86_sse2_ucomile_sd
x86_sse2_ucomilt_sd
x86_sse2_ucomineq_sd
x86_sse3_addsub_pd
x86_sse3_addsub_ps
x86_sse3_hadd_pd
x86_sse3_hadd_ps
x86_sse3_hsub_pd
x86_sse3_hsub_ps
x86_sse3_ldu_dq
x86_sse3_monitor
x86_sse3_mwait
x86_sse41_blendvpd
x86_sse41_blendvps
x86_sse41_dppd
x86_sse41_dpps
x86_sse41_insertps
x86_sse41_mpsadbw
x86_sse41_packusdw
x86_sse41_pblendvb
x86_sse41_phminposuw
x86_sse41_ptestc
x86_sse41_ptestnzc
x86_sse41_ptestz
x86_sse41_round_pd
x86_sse41_round_ps
x86_sse41_round_sd
x86_sse41_round_ss
x86_sse42_crc32_32_16
x86_sse42_crc32_32_32
x86_sse42_crc32_32_8
x86_sse42_crc32_64_64
x86_sse42_pcmpestri128
x86_sse42_pcmpestria128
x86_sse42_pcmpestric128
x86_sse42_pcmpestrio128
x86_sse42_pcmpestris128
x86_sse42_pcmpestriz128
x86_sse42_pcmpestrm128
x86_sse42_pcmpistri128
x86_sse42_pcmpistria128
x86_sse42_pcmpistric128
x86_sse42_pcmpistrio128
x86_sse42_pcmpistris128
x86_sse42_pcmpistriz128
x86_sse42_pcmpistrm128
x86_sse4a_extrq
x86_sse4a_extrqi
x86_sse4a_insertq
x86_sse4a_insertqi
x86_ssse3_pabs_b
x86_ssse3_pabs_d
x86_ssse3_pabs_w
x86_ssse3_phadd_d
x86_ssse3_phadd_d_128
x86_ssse3_phadd_sw
x86_ssse3_phadd_sw_128
x86_ssse3_phadd_w
x86_ssse3_phadd_w_128
x86_ssse3_phsub_d
x86_ssse3_phsub_d_128
x86_ssse3_phsub_sw
x86_ssse3_phsub_sw_128
x86_ssse3_phsub_w
x86_ssse3_phsub_w_128
x86_ssse3_pmadd_ub_sw
x86_ssse3_pmadd_ub_sw_128
x86_ssse3_pmul_hr_sw
x86_ssse3_pmul_hr_sw_128
x86_ssse3_pshuf_b
x86_ssse3_pshuf_b_128
x86_ssse3_psign_b
x86_ssse3_psign_b_128
x86_ssse3_psign_d
x86_ssse3_psign_d_128
x86_ssse3_psign_w
x86_ssse3_psign_w_128
x86_subborrow_32
x86_subborrow_64
x86_tbm_bextri_u32
x86_tbm_bextri_u64
x86_tpause
x86_umonitor
x86_umwait
x86_vcvtph2ps_128
x86_vcvtph2ps_256
x86_vcvtps2ph_128
x86_vcvtps2ph_256
x86_vgf2p8affineinvqb_128
x86_vgf2p8affineinvqb_256
x86_vgf2p8affineinvqb_512
x86_vgf2p8affineqb_128
x86_vgf2p8affineqb_256
x86_vgf2p8affineqb_512
x86_vgf2p8mulb_128
x86_vgf2p8mulb_256
x86_vgf2p8mulb_512
x86_wbinvd
x86_wbnoinvd
x86_wrfsbase_32
x86_wrfsbase_64
x86_wrgsbase_32
x86_wrgsbase_64
x86_wrpkru
x86_wrssd
x86_wrssq
x86_wrussd
x86_wrussq
x86_xabort
x86_xbegin
x86_xend
x86_xgetbv
x86_xop_vfrcz_pd
x86_xop_vfrcz_pd_256
x86_xop_vfrcz_ps
x86_xop_vfrcz_ps_256
x86_xop_vfrcz_sd
x86_xop_vfrcz_ss
x86_xop_vpcomb
x86_xop_vpcomd
x86_xop_vpcomq
x86_xop_vpcomub
x86_xop_vpcomud
x86_xop_vpcomuq
x86_xop_vpcomuw
x86_xop_vpcomw
x86_xop_vpermil2pd
x86_xop_vpermil2pd_256
x86_xop_vpermil2ps
x86_xop_vpermil2ps_256
x86_xop_vphaddbd
x86_xop_vphaddbq
x86_xop_vphaddbw
x86_xop_vphadddq
x86_xop_vphaddubd
x86_xop_vphaddubq
x86_xop_vphaddubw
x86_xop_vphaddudq
x86_xop_vphadduwd
x86_xop_vphadduwq
x86_xop_vphaddwd
x86_xop_vphaddwq
x86_xop_vphsubbw
x86_xop_vphsubdq
x86_xop_vphsubwd
x86_xop_vpmacsdd
x86_xop_vpmacsdqh
x86_xop_vpmacsdql
x86_xop_vpmacssdd
x86_xop_vpmacssdqh
x86_xop_vpmacssdql
x86_xop_vpmacsswd
x86_xop_vpmacssww
x86_xop_vpmacswd
x86_xop_vpmacsww
x86_xop_vpmadcsswd
x86_xop_vpmadcswd
x86_xop_vpperm
x86_xop_vpshab
x86_xop_vpshad
x86_xop_vpshaq
x86_xop_vpshaw
x86_xop_vpshlb
x86_xop_vpshld
x86_xop_vpshlq
x86_xop_vpshlw
x86_xrstor
x86_xrstor64
x86_xrstors
x86_xrstors64
x86_xsave
x86_xsave64
x86_xsavec
x86_xsavec64
x86_xsaveopt
x86_xsaveopt64
x86_xsaves
x86_xsaves64
x86_xsetbv
x86_xtest
xcore_bitrev
xcore_checkevent
xcore_chkct
xcore_clre
xcore_clrpt
xcore_clrsr
xcore_crc32
xcore_crc8
xcore_edu
xcore_eeu
xcore_endin
xcore_freer
xcore_geted
xcore_getet
xcore_getid
xcore_getps
xcore_getr
xcore_getst
xcore_getts
xcore_in
xcore_inct
xcore_initcp
xcore_initdp
xcore_initlr
xcore_initpc
xcore_initsp
xcore_inshr
xcore_int
xcore_mjoin
xcore_msync
xcore_out
xcore_outct
xcore_outshr
xcore_outt
xcore_peek
xcore_setc
xcore_setclk
xcore_setd
xcore_setev
xcore_setps
xcore_setpsc
xcore_setpt
xcore_setrdy
xcore_setsr
xcore_settw
xcore_setv
xcore_sext
xcore_ssync
xcore_syncr
xcore_testct
xcore_testwct
xcore_waitevent
xcore_zext
num_intrinsics

Definition at line 37 of file Intrinsics.h.

Function Documentation

getAttributes()

AttributeList llvm::Intrinsic::getAttributes	(	LLVMContext &	C,
		ID	id
	)

Return the attributes for an intrinsic.

Referenced by llvm::AttributeList::addAllocSizeParamAttr(), llvm::Function::addAttribute(), llvm::CallBase::addAttribute(), llvm::Function::addAttributes(), llvm::AttributeList::addAttributes(), llvm::Function::addDereferenceableAttr(), llvm::CallBase::addDereferenceableAttr(), llvm::Function::addDereferenceableOrNullAttr(), llvm::CallBase::addDereferenceableOrNullAttr(), llvm::Function::addDereferenceableOrNullParamAttr(), llvm::Function::addDereferenceableParamAttr(), llvm::Function::addParamAttr(), llvm::CallBase::addParamAttr(), llvm::Function::addParamAttrs(), llvm::attributesPermitTailCall(), llvm::FunctionComparator::cmpOperations(), computeAddrSpace(), llvm::AttributeList::dump(), llvm::AttributeList::getAllocSizeArgs(), llvm::AttributeList::getAsString(), llvm::AttributeList::getAttribute(), llvm::CallBase::getAttribute(), llvm::CallSiteBase<>::getAttributes(), llvm::AMDGPUIntrinsicInfo::getDeclaration(), llvm::AttributeList::getDereferenceableBytes(), llvm::AttributeList::getDereferenceableOrNullBytes(), llvm::AttributeList::getFnAttributes(), llvm::AttributeList::getParamAlignment(), llvm::CallBase::getParamAttr(), llvm::AttributeList::getParamAttributes(), llvm::AttributeList::getRetAlignment(), llvm::AttributeList::getRetAttributes(), llvm::AttributeList::getStackAlignment(), llvm::SITargetLowering::getTgtMemIntrinsic(), llvm::Function::hasAttribute(), llvm::AttributeList::hasAttribute(), llvm::AttributeList::hasAttributes(), llvm::Function::hasParamAttribute(), haveSameSpecialState(), LLVMGetAttributeCountAtIndex(), LLVMGetAttributesAtIndex(), readTriple(), llvm::Function::removeAttribute(), llvm::CallBase::removeAttribute(), llvm::Function::removeAttributes(), llvm::Function::removeFnAttr(), llvm::Function::removeParamAttr(), llvm::CallBase::removeParamAttr(), llvm::Function::removeParamAttrs(), and llvm::UpgradeIntrinsicFunction().

getDeclaration()

Function * llvm::Intrinsic::getDeclaration	(	Module *	M,
		ID	id,
		ArrayRef< Type *>	Tys = None
	)

Create or insert an LLVM Function declaration for an intrinsic, and return it.

The Tys parameter is for intrinsics with overloaded types (e.g., those using iAny, fAny, vAny, or iPTRAny). For a declaration of an overloaded intrinsic, Tys must provide exactly one type for each overloaded type in the intrinsic.

Definition at line 1020 of file Function.cpp.

References llvm::Module::getContext(), llvm::Value::getName(), llvm::Module::getOrInsertFunction(), and llvm::Value::getType().

Referenced by addAssumeNonNull(), addBoundsChecking(), asmClobbersCTR(), callIntrinsic(), canonicalizeSaturatedSubtract(), llvm::changeToUnreachable(), CombineUAddWithOverflow(), llvm::IRBuilderBase::CreateAssumption(), llvm::IRBuilderBase::CreateBinaryIntrinsic(), createCoroSave(), llvm::IRBuilderBase::CreateElementUnorderedAtomicMemCpy(), llvm::IRBuilderBase::CreateElementUnorderedAtomicMemMove(), llvm::IRBuilderBase::CreateElementUnorderedAtomicMemSet(), llvm::IRBuilderBase::CreateFAddReduce(), createFFSIntrinsic(), llvm::IRBuilderBase::CreateFMulReduce(), llvm::IRBuilderBase::CreateGCRelocate(), CreateGCRelocates(), llvm::IRBuilderBase::CreateGCResult(), CreateGCStatepointCallCommon(), CreateGCStatepointInvokeCommon(), llvm::IRBuilderBase::CreateIntrinsic(), llvm::IRBuilderBase::CreateInvariantStart(), llvm::IRBuilder< TargetFolder >::CreateLaunderInvariantGroup(), llvm::IRBuilderBase::CreateLifetimeEnd(), llvm::IRBuilderBase::CreateLifetimeStart(), CreateLoadIns(), llvm::IRBuilderBase::CreateMaskedStore(), llvm::IRBuilderBase::CreateMemCpy(), llvm::IRBuilderBase::CreateMemMove(), llvm::IRBuilderBase::CreateMemSet(), createPopcntIntrinsic(), CreatePrologue(), llvm::IRBuilder< TargetFolder >::CreateStripInvariantGroup(), llvm::IRBuilderBase::CreateUnaryIntrinsic(), llvm::AArch64TargetLowering::emitAtomicCmpXchgNoStoreLLBalance(), llvm::ARMTargetLowering::emitAtomicCmpXchgNoStoreLLBalance(), llvm::HexagonTargetLowering::emitLoadLinked(), llvm::AArch64TargetLowering::emitLoadLinked(), llvm::ARMTargetLowering::emitLoadLinked(), llvm::HexagonTargetLowering::emitStoreConditional(), llvm::AArch64TargetLowering::emitStoreConditional(), llvm::ARMTargetLowering::emitStoreConditional(), llvm::PPCTargetLowering::emitTrailingFence(), eraseDeadBBsAndChildren(), explicifyGuards(), findStackProtectorIntrinsic(), foldGuardedRotateToFunnelShift(), foldVecTruncToExtElt(), generateUnsignedDivisionCode(), llvm::objcarc::ARCRuntimeEntryPoints::get(), getDeclareIntrin(), getIntrinsicForMaskedAtomicRMWBinOp32(), getNarrowIntrinsic(), getPointerOperands(), getPow(), getReductionIntrinsic(), getScalarIntrinsicDeclaration(), getSqrtCall(), getStackGuard(), getSuccState(), hasUndefContents(), INITIALIZE_PASS(), llvm::InlineFunction(), insertCall(), insertLifetimeMarkersSurroundingCall(), insertSinCosCall(), instrumentOneFunc(), inversePermutation(), isAtomic(), isCallPromotable(), isIndirectBrTarget(), isZeroLengthArray(), LLVMGetIntrinsicDeclaration(), lowerGuardIntrinsic(), llvm::AArch64TargetLowering::lowerInterleavedLoad(), llvm::ARMTargetLowering::lowerInterleavedLoad(), llvm::AArch64TargetLowering::lowerInterleavedStore(), llvm::ARMTargetLowering::lowerInterleavedStore(), LowerRotate(), llvm::IntrinsicLowering::LowerToByteSwap(), llvm::ARMTargetLowering::makeDMB(), llvm::coro::LowererBase::makeSubFnCall(), MarkBlocksLiveIn(), matchRotate(), optimizeBinaryDoubleFP(), optimizeDoubleFP(), processUGT_ADDCST_ADD(), processUMulZExtIdiom(), promotedOpIsNUW(), llvm::recognizeBSwapOrBitReverseIdiom(), RedzoneSizeForScale(), remangleIntrinsicFunction(), replaceUnaryCall(), RetagMask(), llvm::LoopDataPrefetchPass::run(), llvm::WholeProgramDevirtPass::run(), shouldInstrumentBlock(), shouldKeepFDivF32(), ShrinkDemandedConstant(), SimplifyBSwap(), SimplifyNVVMIntrinsic(), llvm::DISubprogram::toSPFlags(), TypeSizeToSizeIndex(), unifyReturnBlockSet(), upgradeAVX512MaskToSelect(), UpgradeIntrinsicFunction1(), UpgradePTESTIntrinsic(), UpgradeX86AddSubSatIntrinsics(), upgradeX86ConcatShift(), UpgradeX86IntrinsicFunction(), UpgradeX86IntrinsicsWith8BitMask(), UpgradeX86MaskedShift(), upgradeX86Rotate(), UpgradeX86VPERMT2Intrinsics(), UseTlsOffset(), llvm::InstCombiner::visitAllocSite(), llvm::InstCombiner::visitCallInst(), llvm::InstCombiner::visitFPTrunc(), and llvm::InnerLoopVectorizer::widenInstruction().

getIntrinsicForGCCBuiltin()

ID llvm::Intrinsic::getIntrinsicForGCCBuiltin	(	const char *	Prefix,
		StringRef	BuiltinName
	)

Map a GCC builtin name to an intrinsic ID.

getIntrinsicForMSBuiltin()

ID llvm::Intrinsic::getIntrinsicForMSBuiltin	(	const char *	Prefix,
		StringRef	BuiltinName
	)

Map a MS builtin name to an intrinsic ID.

getIntrinsicInfoTableEntries()

void llvm::Intrinsic::getIntrinsicInfoTableEntries	(	ID	id,
		SmallVectorImpl< IITDescriptor > &	T
	)

Return the IIT table descriptor for the specified intrinsic into an array of IITDescriptors.

Definition at line 864 of file Function.cpp.

References DecodeIITType(), llvm::SmallVectorTemplateBase< T, bool >::push_back(), and llvm::ArrayRef< T >::size().

Referenced by getParentPad(), getType(), remangleIntrinsicFunction(), and ShrinkDemandedConstant().

getName() [1/2]

StringRef llvm::Intrinsic::getName

(

ID

id

)

Return the LLVM name for an intrinsic, such as "llvm.ppc.altivec.lvx".

Note, this version is for intrinsics with no overloads. Use the other version of getName if overloads are required.

Definition at line 626 of file Function.cpp.

References assert(), isOverloaded(), and num_intrinsics.

Referenced by containsProfilingIntrinsics(), explicifyGuards(), llvm::SDNode::getOperationName(), getParentPad(), isDirectCall(), isObjectDereferencedInBlock(), llvm::SelectionDAGISel::isOrEquivalentToAdd(), LLVMIntrinsicCopyOverloadedName(), LLVMIntrinsicGetName(), lowerGuardIntrinsic(), llvm::MachineOperand::print(), remangleIntrinsicFunction(), llvm::WholeProgramDevirtPass::run(), llvm::JumpThreadingPass::runImpl(), llvm::ScalarEvolution::ScalarEvolution(), splitGlobals(), truncateIVUse(), unswitchBestCondition(), and UpgradeIntrinsicFunction1().

getName() [2/2]

std::string llvm::Intrinsic::getName	(	ID	id,
		ArrayRef< Type *>	Tys
	)

Return the LLVM name for an intrinsic, such as "llvm.ppc.altivec.lvx".

Note, this version of getName supports overloads, but is less efficient than the StringRef version of this function. If no overloads are requried, it is safe to use this version, but better to use the StringRef version.

Definition at line 633 of file Function.cpp.

References assert(), getMangledTypeStr(), and num_intrinsics.

getType()

FunctionType * llvm::Intrinsic::getType	(	LLVMContext &	Context,
		ID	id,
		ArrayRef< Type *>	Tys = None
	)

Return the function type for an intrinsic.

Definition at line 976 of file Function.cpp.

References llvm::SmallVectorTemplateCommon< T >::back(), DecodeFixedType(), llvm::SmallVectorBase::empty(), llvm::ArrayRef< T >::empty(), llvm::FunctionType::get(), getIntrinsicInfoTableEntries(), llvm::Type::isVoidTy(), llvm::SmallVectorTemplateBase< T >::pop_back(), and llvm::SmallVectorTemplateBase< T >::push_back().

Referenced by llvm::CastInst::getDestTy(), llvm::CallSiteBase<>::isReturnNonNull(), and LLVMIntrinsicGetType().

isLeaf()

bool llvm::Intrinsic::isLeaf

(

ID

id

)

Returns true if the intrinsic is a leaf, i.e.

it does not make any calls itself. Most intrinsics are leafs, the exceptions being the patchpoint and statepoint intrinsics. These call (or invoke) their "target" argument.

Definition at line 1003 of file Function.cpp.

References experimental_gc_statepoint, experimental_patchpoint_i64, and experimental_patchpoint_void.

Referenced by llvm::CallGraphNode::addCalledFunction(), and DeleteBasicBlock().

isOverloaded()

bool llvm::Intrinsic::isOverloaded

(

ID

id

)

Returns true if the intrinsic can be overloaded.

Definition at line 997 of file Function.cpp.

Referenced by getName(), LLVMIntrinsicIsOverloaded(), and llvm::Function::lookupIntrinsicID().

lookupLLVMIntrinsicByName()

int llvm::Intrinsic::lookupLLVMIntrinsicByName	(	ArrayRef< const char *>	NameTable,
		StringRef	Name
	)

Looks up Name in NameTable via binary search.

NameTable must be sorted and all entries must start with "llvm.". If NameTable contains an exact match for Name or a prefix of Name followed by a dot, its index in NameTable is returned. Otherwise, -1 is returned.

Definition at line 59 of file IntrinsicInst.cpp.

References assert(), llvm::ArrayRef< T >::begin(), llvm::StringRef::data(), llvm::ArrayRef< T >::end(), llvm::StringRef::find(), High, llvm::StringRef::npos, llvm::StringRef::size(), and llvm::StringRef::startswith().

Referenced by isCoroutineIntrinsicName(), llvm::Function::lookupIntrinsicID(), and llvm::AMDGPUIntrinsicInfo::lookupName().

matchIntrinsicType()

bool llvm::Intrinsic::matchIntrinsicType	(	Type *	Ty,
		ArrayRef< IITDescriptor > &	Infos,
		SmallVectorImpl< Type *> &	ArgTys
	)

Match the specified type (which comes from an intrinsic argument or return value) with the type constraints specified by the .td file.

If the given type is an overloaded type it is pushed to the ArgTys vector.

Returns false if the given type matches with the constraints, true otherwise.

Definition at line 1038 of file Function.cpp.

References assert(), D, llvm::pdb::Double, llvm::dyn_cast(), llvm::ArrayRef< T >::empty(), llvm::NVPTX::PTXLdStInstCode::Float, llvm::ArrayRef< T >::front(), llvm::IntegerType::get(), llvm::PointerType::getAddressSpace(), llvm::Intrinsic::IITDescriptor::getArgumentKind(), llvm::Intrinsic::IITDescriptor::getArgumentNumber(), llvm::StructType::getElementType(), llvm::SequentialType::getElementType(), llvm::PointerType::getElementType(), llvm::VectorType::getExtendedElementVectorType(), llvm::VectorType::getHalfElementsVectorType(), llvm::StructType::getNumElements(), llvm::SequentialType::getNumElements(), llvm::Intrinsic::IITDescriptor::getOverloadArgNumber(), llvm::Intrinsic::IITDescriptor::getRefArgNumber(), llvm::VectorType::getTruncatedElementVectorType(), llvm::Type::getVectorElementType(), llvm::Type::getVectorNumElements(), llvm::Integer, llvm::Intrinsic::IITDescriptor::Integer_Width, llvm::Type::isDoubleTy(), llvm::Type::isFloatTy(), llvm::Type::isFP128Ty(), llvm::Type::isFPOrFPVectorTy(), llvm::Type::isHalfTy(), llvm::Type::isIntegerTy(), llvm::Type::isIntOrIntVectorTy(), llvm::Type::isMetadataTy(), llvm::Type::isTokenTy(), llvm::Type::isVoidTy(), llvm::Type::isX86_MMXTy(), llvm::Intrinsic::IITDescriptor::Kind, llvm_unreachable, llvm::Intrinsic::IITDescriptor::Pointer_AddressSpace, llvm::SmallVectorTemplateBase< T >::push_back(), llvm::SmallVectorBase::size(), llvm::ArrayRef< T >::slice(), llvm::ARM_MB::ST, llvm::Intrinsic::IITDescriptor::Struct_NumElements, and llvm::Intrinsic::IITDescriptor::Vector_Width.

Referenced by getParentPad(), remangleIntrinsicFunction(), and ShrinkDemandedConstant().

matchIntrinsicVarArg()

bool llvm::Intrinsic::matchIntrinsicVarArg	(	bool	isVarArg,
		ArrayRef< IITDescriptor > &	Infos
	)

Verify if the intrinsic has variable arguments.

This method is intended to be called after all the fixed arguments have been matched first.

This method returns true on error.

Definition at line 1199 of file Function.cpp.

References D, llvm::ArrayRef< T >::empty(), llvm::ArrayRef< T >::front(), llvm::Intrinsic::IITDescriptor::Kind, llvm::ArrayRef< T >::size(), and llvm::ArrayRef< T >::slice().

Referenced by getParentPad(), and remangleIntrinsicFunction().

remangleIntrinsicFunction()

Optional< Function * > llvm::Intrinsic::remangleIntrinsicFunction

(

Function *

F

)

Definition at line 1218 of file Function.cpp.

References assert(), llvm::Function::getCallingConv(), getDeclaration(), llvm::Function::getFunctionType(), llvm::Function::getIntrinsicID(), getIntrinsicInfoTableEntries(), getName(), llvm::Value::getName(), llvm::GlobalValue::getParent(), llvm::FunctionType::getReturnType(), llvm::FunctionType::isVarArg(), matchIntrinsicType(), matchIntrinsicVarArg(), Name, llvm::None, llvm::FunctionType::params(), and llvm::Function::setCallingConv().

Referenced by getArrayElements(), and UpgradeIntrinsicFunction1().