33 #define DEBUG_TYPE "arm-disassembler" 52 void advanceITState() {
57 bool instrInITBlock() {
58 return !ITStates.empty();
62 bool instrLastInITBlock() {
63 return ITStates.size() == 1;
69 void setITState(
char Firstcond,
char Mask) {
71 unsigned CondBit0 = Firstcond & 1;
72 unsigned NumTZ = countTrailingZeros<uint8_t>(
Mask);
73 unsigned char CCBits =
static_cast<unsigned char>(Firstcond & 0xf);
74 assert(NumTZ <= 3 &&
"Invalid IT mask!");
76 for (
unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) {
77 bool T = ((Mask >> Pos) & 1) == CondBit0;
79 ITStates.push_back(CCBits);
81 ITStates.push_back(CCBits ^ 1);
83 ITStates.push_back(CCBits);
87 std::vector<unsigned char> ITStates;
97 ~ARMDisassembler()
override =
default;
112 ~ThumbDisassembler()
override =
default;
120 mutable ITStatus ITBlock;
123 void UpdateThumbVFPPredicate(
MCInst&)
const;
146 uint64_t
Address,
const void *Decoder);
148 unsigned RegNo, uint64_t
Address,
149 const void *Decoder);
151 unsigned RegNo, uint64_t
Address,
152 const void *Decoder);
154 uint64_t
Address,
const void *Decoder);
156 uint64_t
Address,
const void *Decoder);
158 uint64_t
Address,
const void *Decoder);
160 uint64_t
Address,
const void *Decoder);
162 uint64_t
Address,
const void *Decoder);
164 uint64_t
Address,
const void *Decoder);
166 uint64_t
Address,
const void *Decoder);
168 uint64_t
Address,
const void *Decoder);
172 const void *Decoder);
174 uint64_t
Address,
const void *Decoder);
176 uint64_t
Address,
const void *Decoder);
178 unsigned RegNo, uint64_t
Address,
179 const void *Decoder);
182 uint64_t
Address,
const void *Decoder);
184 uint64_t
Address,
const void *Decoder);
186 uint64_t
Address,
const void *Decoder);
188 uint64_t
Address,
const void *Decoder);
190 uint64_t
Address,
const void *Decoder);
193 uint64_t
Address,
const void *Decoder);
195 uint64_t
Address,
const void *Decoder);
199 const void *Decoder);
201 uint64_t
Address,
const void *Decoder);
203 uint64_t
Address,
const void *Decoder);
205 uint64_t
Address,
const void *Decoder);
207 uint64_t
Address,
const void *Decoder);
212 const void *Decoder);
214 uint64_t
Address,
const void *Decoder);
216 uint64_t
Address,
const void *Decoder);
218 uint64_t
Address,
const void *Decoder);
220 uint64_t
Address,
const void *Decoder);
222 uint64_t
Address,
const void *Decoder);
224 uint64_t
Address,
const void *Decoder);
226 uint64_t
Address,
const void *Decoder);
228 uint64_t
Address,
const void *Decoder);
230 uint64_t
Address,
const void *Decoder);
232 uint64_t
Address,
const void *Decoder);
234 uint64_t
Address,
const void *Decoder);
236 uint64_t
Address,
const void *Decoder);
238 uint64_t
Address,
const void *Decoder);
240 uint64_t
Address,
const void *Decoder);
242 uint64_t
Address,
const void *Decoder);
244 uint64_t
Address,
const void *Decoder);
246 uint64_t
Address,
const void *Decoder);
248 uint64_t
Address,
const void *Decoder);
250 uint64_t
Address,
const void *Decoder);
252 uint64_t
Address,
const void *Decoder);
254 uint64_t
Address,
const void *Decoder);
256 uint64_t
Address,
const void *Decoder);
258 uint64_t
Address,
const void *Decoder);
260 uint64_t
Address,
const void *Decoder);
262 uint64_t
Address,
const void *Decoder);
264 uint64_t
Address,
const void *Decoder);
266 uint64_t
Address,
const void *Decoder);
268 uint64_t
Address,
const void *Decoder);
270 uint64_t
Address,
const void *Decoder);
272 uint64_t
Address,
const void *Decoder);
274 uint64_t
Address,
const void *Decoder);
276 uint64_t
Address,
const void *Decoder);
278 uint64_t
Address,
const void *Decoder);
280 uint64_t
Address,
const void *Decoder);
282 uint64_t
Address,
const void *Decoder);
284 uint64_t
Address,
const void *Decoder);
286 uint64_t
Address,
const void *Decoder);
288 uint64_t
Address,
const void *Decoder);
290 uint64_t
Address,
const void *Decoder);
292 uint64_t
Address,
const void *Decoder);
294 uint64_t
Address,
const void *Decoder);
296 uint64_t
Address,
const void *Decoder);
298 uint64_t
Address,
const void *Decoder);
300 uint64_t
Address,
const void *Decoder);
302 uint64_t
Address,
const void *Decoder);
304 uint64_t
Address,
const void *Decoder);
306 uint64_t
Address,
const void *Decoder);
308 uint64_t
Address,
const void *Decoder);
310 uint64_t
Address,
const void *Decoder);
312 uint64_t
Address,
const void *Decoder);
314 uint64_t
Address,
const void *Decoder);
316 uint64_t
Address,
const void *Decoder);
318 uint64_t
Address,
const void *Decoder);
320 uint64_t
Address,
const void *Decoder);
322 uint64_t
Address,
const void *Decoder);
324 uint64_t
Address,
const void *Decoder);
326 uint64_t
Address,
const void *Decoder);
330 const void *Decoder);
333 uint64_t
Address,
const void *Decoder);
335 uint64_t
Address,
const void *Decoder);
337 uint64_t
Address,
const void *Decoder);
339 uint64_t
Address,
const void *Decoder);
341 uint64_t
Address,
const void *Decoder);
343 uint64_t
Address,
const void *Decoder);
345 uint64_t
Address,
const void *Decoder);
347 uint64_t
Address,
const void *Decoder);
349 uint64_t
Address,
const void *Decoder);
351 uint64_t
Address,
const void *Decoder);
353 uint64_t
Address,
const void* Decoder);
355 uint64_t
Address,
const void* Decoder);
357 uint64_t
Address,
const void* Decoder);
359 uint64_t
Address,
const void* Decoder);
361 uint64_t
Address,
const void *Decoder);
363 uint64_t
Address,
const void *Decoder);
365 uint64_t
Address,
const void *Decoder);
367 uint64_t
Address,
const void *Decoder);
369 uint64_t
Address,
const void *Decoder);
371 uint64_t
Address,
const void *Decoder);
373 uint64_t
Address,
const void *Decoder);
375 uint64_t
Address,
const void *Decoder);
377 uint64_t
Address,
const void *Decoder);
379 uint64_t
Address,
const void *Decoder);
381 uint64_t
Address,
const void *Decoder);
383 uint64_t
Address,
const void *Decoder);
385 uint64_t
Address,
const void *Decoder);
387 uint64_t
Address,
const void *Decoder);
389 uint64_t
Address,
const void *Decoder);
391 uint64_t
Address,
const void *Decoder);
393 uint64_t
Address,
const void *Decoder);
395 uint64_t
Address,
const void *Decoder);
397 uint64_t
Address,
const void *Decoder);
399 uint64_t
Address,
const void *Decoder);
401 uint64_t
Address,
const void *Decoder);
403 uint64_t
Address,
const void *Decoder);
406 uint64_t
Address,
const void *Decoder);
408 uint64_t
Address,
const void *Decoder);
410 uint64_t
Address,
const void *Decoder);
412 #include "ARMGenDisassemblerTables.inc" 417 return new ARMDisassembler(STI, Ctx);
423 return new ThumbDisassembler(STI, Ctx);
443 default:
return Result;
453 assert(!STI.getFeatureBits()[ARM::ModeThumb] &&
454 "Asked to disassemble an ARM instruction but Subtarget is in Thumb " 458 if (Bytes.
size() < 4) {
465 (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0);
480 const DecodeTable Tables[] = {
481 {DecoderTableVFP32,
false}, {DecoderTableVFPV832,
false},
482 {DecoderTableNEONData32,
true}, {DecoderTableNEONLoadStore32,
true},
483 {DecoderTableNEONDup32,
true}, {DecoderTablev8NEON32,
false},
484 {DecoderTablev8Crypto32,
false},
487 for (
auto Table : Tables) {
530 MCInst &MI,
const void *Decoder) {
547 const void *Decoder) {
560 for (
unsigned i = 0; i < NumOps; ++i, ++
I) {
561 if (I == MI.
end())
break;
562 if (OpInfo[i].isOptionalDef() && OpInfo[i].
RegClass == ARM::CCRRegClassID) {
563 if (i > 0 && OpInfo[i-1].isPredicate())
continue;
577 ThumbDisassembler::AddThumbPredicate(
MCInst &MI)
const {
580 const FeatureBitset &FeatureBits = getSubtargetInfo().getFeatureBits();
597 if (ITBlock.instrInITBlock())
603 if (MI.
getOperand(0).
getImm() == 0x10 && (FeatureBits[ARM::FeatureRAS]) != 0)
612 if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock())
622 CC = ITBlock.getITCC();
625 if (ITBlock.instrInITBlock())
626 ITBlock.advanceITState();
631 for (
unsigned i = 0; i < NumOps; ++i, ++
I) {
632 if (I == MI.
end())
break;
633 if (OpInfo[i].isPredicate()) {
659 void ThumbDisassembler::UpdateThumbVFPPredicate(
MCInst &MI)
const {
661 CC = ITBlock.getITCC();
664 if (ITBlock.instrInITBlock())
665 ITBlock.advanceITState();
670 for (
unsigned i = 0; i < NumOps; ++i, ++
I) {
671 if (OpInfo[i].isPredicate() ) {
677 I->setReg(ARM::CPSR);
690 assert(STI.getFeatureBits()[ARM::ModeThumb] &&
691 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!");
694 if (Bytes.
size() < 2) {
699 uint16_t Insn16 = (Bytes[1] << 8) | Bytes[0];
704 Check(Result, AddThumbPredicate(MI));
712 bool InITBlock = ITBlock.instrInITBlock();
713 Check(Result, AddThumbPredicate(MI));
725 if (MI.
getOpcode() == ARM::t2IT && ITBlock.instrInITBlock())
728 Check(Result, AddThumbPredicate(MI));
736 ITBlock.setITState(Firstcond, Mask);
740 CS <<
"unpredictable IT predicate sequence";
747 if (Bytes.
size() < 4) {
753 (Bytes[3] << 8) | (Bytes[2] << 0) | (Bytes[1] << 24) | (Bytes[0] << 16);
758 bool InITBlock = ITBlock.instrInITBlock();
759 Check(Result, AddThumbPredicate(MI));
768 Check(Result, AddThumbPredicate(MI));
772 if (fieldFromInstruction(Insn32, 28, 4) == 0xE) {
777 UpdateThumbVFPPredicate(MI);
789 if (fieldFromInstruction(Insn32, 28, 4) == 0xE) {
794 Check(Result, AddThumbPredicate(MI));
799 if (fieldFromInstruction(Insn32, 24, 8) == 0xF9) {
801 NEONLdStInsn &= 0xF0FFFFFF;
802 NEONLdStInsn |= 0x04000000;
807 Check(Result, AddThumbPredicate(MI));
812 if (fieldFromInstruction(Insn32, 24, 4) == 0xF) {
814 NEONDataInsn &= 0xF0FFFFFF;
815 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4;
816 NEONDataInsn |= 0x12000000;
821 Check(Result, AddThumbPredicate(MI));
826 NEONCryptoInsn &= 0xF0FFFFFF;
827 NEONCryptoInsn |= (NEONCryptoInsn & 0x10000000) >> 4;
828 NEONCryptoInsn |= 0x12000000;
837 NEONv8Insn &= 0xF3FFFFFF;
850 Check(Result, AddThumbPredicate(MI));
870 ARM::R0, ARM::R1,
ARM::R2, ARM::R3,
872 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
873 ARM::R12, ARM::SP, ARM::LR, ARM::PC
877 uint64_t
Address,
const void *Decoder) {
888 uint64_t
Address,
const void *Decoder) {
901 uint64_t
Address,
const void *Decoder) {
915 uint64_t
Address,
const void *Decoder) {
922 ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7,
923 ARM::R8_R9, ARM::R10_R11, ARM::R12_SP
927 uint64_t
Address,
const void *Decoder) {
933 if ((RegNo & 1) || RegNo == 0xe)
942 uint64_t
Address,
const void *Decoder) {
972 uint64_t
Address,
const void *Decoder) {
976 ((
const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
978 if ((RegNo == 13 && !featureBits[ARM::HasV8Ops]) || RegNo == 15)
986 ARM::S0, ARM::S1, ARM::S2, ARM::S3,
987 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
988 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
989 ARM::S12, ARM::S13, ARM::S14, ARM::S15,
990 ARM::S16, ARM::S17, ARM::S18, ARM::S19,
991 ARM::S20, ARM::S21, ARM::S22, ARM::S23,
992 ARM::S24, ARM::S25, ARM::S26, ARM::S27,
993 ARM::S28, ARM::S29, ARM::S30, ARM::S31
997 uint64_t
Address,
const void *Decoder) {
1007 uint64_t
Address,
const void *Decoder) {
1012 ARM::D0, ARM::D1, ARM::D2, ARM::D3,
1013 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
1014 ARM::D8, ARM::D9, ARM::D10, ARM::D11,
1015 ARM::D12, ARM::D13, ARM::D14, ARM::D15,
1016 ARM::D16, ARM::D17, ARM::D18, ARM::D19,
1017 ARM::D20, ARM::D21, ARM::D22, ARM::D23,
1018 ARM::D24, ARM::D25, ARM::D26, ARM::D27,
1019 ARM::D28, ARM::D29, ARM::D30, ARM::D31
1023 uint64_t
Address,
const void *Decoder) {
1025 ((
const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
1027 bool hasD16 = featureBits[ARM::FeatureD16];
1029 if (RegNo > 31 || (hasD16 && RegNo > 15))
1038 uint64_t
Address,
const void *Decoder) {
1046 uint64_t
Address,
const void *Decoder) {
1053 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
1054 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7,
1055 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11,
1056 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15
1060 uint64_t
Address,
const void *Decoder) {
1061 if (RegNo > 31 || (RegNo & 1) != 0)
1071 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6,
1072 ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12,
1073 ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18,
1074 ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24,
1075 ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30,
1080 uint64_t
Address,
const void *Decoder) {
1090 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5,
1091 ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9,
1092 ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13,
1093 ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17,
1094 ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21,
1095 ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25,
1096 ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29,
1097 ARM::D28_D30, ARM::D29_D31
1103 const void *Decoder) {
1113 uint64_t
Address,
const void *Decoder) {
1116 if (Inst.
getOpcode() == ARM::tBcc && Val == 0xE)
1127 uint64_t
Address,
const void *Decoder) {
1136 uint64_t
Address,
const void *Decoder) {
1139 unsigned Rm = fieldFromInstruction(Val, 0, 4);
1140 unsigned type = fieldFromInstruction(Val, 5, 2);
1141 unsigned imm = fieldFromInstruction(Val, 7, 5);
1166 unsigned Op = Shift | (imm << 3);
1173 uint64_t
Address,
const void *Decoder) {
1176 unsigned Rm = fieldFromInstruction(Val, 0, 4);
1177 unsigned type = fieldFromInstruction(Val, 5, 2);
1178 unsigned Rs = fieldFromInstruction(Val, 8, 4);
1208 uint64_t
Address,
const void *Decoder) {
1211 bool NeedDisjointWriteback =
false;
1212 unsigned WritebackReg = 0;
1216 case ARM::LDMIA_UPD:
1217 case ARM::LDMDB_UPD:
1218 case ARM::LDMIB_UPD:
1219 case ARM::LDMDA_UPD:
1220 case ARM::t2LDMIA_UPD:
1221 case ARM::t2LDMDB_UPD:
1222 case ARM::t2STMIA_UPD:
1223 case ARM::t2STMDB_UPD:
1224 NeedDisjointWriteback =
true;
1231 for (
unsigned i = 0; i < 16; ++i) {
1232 if (Val & (1 << i)) {
1236 if (NeedDisjointWriteback && WritebackReg == Inst.
end()[-1].getReg())
1245 uint64_t
Address,
const void *Decoder) {
1248 unsigned Vd = fieldFromInstruction(Val, 8, 5);
1249 unsigned regs = fieldFromInstruction(Val, 0, 8);
1252 if (regs == 0 || (Vd + regs) > 32) {
1253 regs = Vd + regs > 32 ? 32 - Vd : regs;
1260 for (
unsigned i = 0; i < (regs - 1); ++i) {
1269 uint64_t
Address,
const void *Decoder) {
1272 unsigned Vd = fieldFromInstruction(Val, 8, 5);
1273 unsigned regs = fieldFromInstruction(Val, 1, 7);
1276 if (regs == 0 || regs > 16 || (Vd + regs) > 32) {
1277 regs = Vd + regs > 32 ? 32 - Vd : regs;
1279 regs = std::min(16u, regs);
1285 for (
unsigned i = 0; i < (regs - 1); ++i) {
1294 uint64_t
Address,
const void *Decoder) {
1300 unsigned msb = fieldFromInstruction(Val, 5, 5);
1301 unsigned lsb = fieldFromInstruction(Val, 0, 5);
1313 if (msb != 31) msb_mask = (1U << (msb+1)) - 1;
1314 uint32_t lsb_mask = (1U << lsb) - 1;
1321 uint64_t
Address,
const void *Decoder) {
1324 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1325 unsigned CRd = fieldFromInstruction(Insn, 12, 4);
1326 unsigned coproc = fieldFromInstruction(Insn, 8, 4);
1327 unsigned imm = fieldFromInstruction(Insn, 0, 8);
1328 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1329 unsigned U = fieldFromInstruction(Insn, 23, 1);
1332 case ARM::LDC_OFFSET:
1335 case ARM::LDC_OPTION:
1336 case ARM::LDCL_OFFSET:
1338 case ARM::LDCL_POST:
1339 case ARM::LDCL_OPTION:
1340 case ARM::STC_OFFSET:
1343 case ARM::STC_OPTION:
1344 case ARM::STCL_OFFSET:
1346 case ARM::STCL_POST:
1347 case ARM::STCL_OPTION:
1348 case ARM::t2LDC_OFFSET:
1349 case ARM::t2LDC_PRE:
1350 case ARM::t2LDC_POST:
1351 case ARM::t2LDC_OPTION:
1352 case ARM::t2LDCL_OFFSET:
1353 case ARM::t2LDCL_PRE:
1354 case ARM::t2LDCL_POST:
1355 case ARM::t2LDCL_OPTION:
1356 case ARM::t2STC_OFFSET:
1357 case ARM::t2STC_PRE:
1358 case ARM::t2STC_POST:
1359 case ARM::t2STC_OPTION:
1360 case ARM::t2STCL_OFFSET:
1361 case ARM::t2STCL_PRE:
1362 case ARM::t2STCL_POST:
1363 case ARM::t2STCL_OPTION:
1364 if (coproc == 0xA || coproc == 0xB)
1372 ((
const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
1373 if (featureBits[ARM::HasV8Ops] && (coproc != 14))
1382 case ARM::t2LDC2_OFFSET:
1383 case ARM::t2LDC2L_OFFSET:
1384 case ARM::t2LDC2_PRE:
1385 case ARM::t2LDC2L_PRE:
1386 case ARM::t2STC2_OFFSET:
1387 case ARM::t2STC2L_OFFSET:
1388 case ARM::t2STC2_PRE:
1389 case ARM::t2STC2L_PRE:
1390 case ARM::LDC2_OFFSET:
1391 case ARM::LDC2L_OFFSET:
1393 case ARM::LDC2L_PRE:
1394 case ARM::STC2_OFFSET:
1395 case ARM::STC2L_OFFSET:
1397 case ARM::STC2L_PRE:
1398 case ARM::t2LDC_OFFSET:
1399 case ARM::t2LDCL_OFFSET:
1400 case ARM::t2LDC_PRE:
1401 case ARM::t2LDCL_PRE:
1402 case ARM::t2STC_OFFSET:
1403 case ARM::t2STCL_OFFSET:
1404 case ARM::t2STC_PRE:
1405 case ARM::t2STCL_PRE:
1406 case ARM::LDC_OFFSET:
1407 case ARM::LDCL_OFFSET:
1410 case ARM::STC_OFFSET:
1411 case ARM::STCL_OFFSET:
1417 case ARM::t2LDC2_POST:
1418 case ARM::t2LDC2L_POST:
1419 case ARM::t2STC2_POST:
1420 case ARM::t2STC2L_POST:
1421 case ARM::LDC2_POST:
1422 case ARM::LDC2L_POST:
1423 case ARM::STC2_POST:
1424 case ARM::STC2L_POST:
1425 case ARM::t2LDC_POST:
1426 case ARM::t2LDCL_POST:
1427 case ARM::t2STC_POST:
1428 case ARM::t2STCL_POST:
1430 case ARM::LDCL_POST:
1432 case ARM::STCL_POST:
1443 case ARM::LDC_OFFSET:
1446 case ARM::LDC_OPTION:
1447 case ARM::LDCL_OFFSET:
1449 case ARM::LDCL_POST:
1450 case ARM::LDCL_OPTION:
1451 case ARM::STC_OFFSET:
1454 case ARM::STC_OPTION:
1455 case ARM::STCL_OFFSET:
1457 case ARM::STCL_POST:
1458 case ARM::STCL_OPTION:
1471 uint64_t
Address,
const void *Decoder) {
1474 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1475 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
1476 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
1477 unsigned imm = fieldFromInstruction(Insn, 0, 12);
1478 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1479 unsigned reg = fieldFromInstruction(Insn, 25, 1);
1480 unsigned P = fieldFromInstruction(Insn, 24, 1);
1481 unsigned W = fieldFromInstruction(Insn, 21, 1);
1485 case ARM::STR_POST_IMM:
1486 case ARM::STR_POST_REG:
1487 case ARM::STRB_POST_IMM:
1488 case ARM::STRB_POST_REG:
1489 case ARM::STRT_POST_REG:
1490 case ARM::STRT_POST_IMM:
1491 case ARM::STRBT_POST_REG:
1492 case ARM::STRBT_POST_IMM:
1505 case ARM::LDR_POST_IMM:
1506 case ARM::LDR_POST_REG:
1507 case ARM::LDRB_POST_IMM:
1508 case ARM::LDRB_POST_REG:
1509 case ARM::LDRBT_POST_REG:
1510 case ARM::LDRBT_POST_IMM:
1511 case ARM::LDRT_POST_REG:
1512 case ARM::LDRT_POST_IMM:
1524 if (!fieldFromInstruction(Insn, 23, 1))
1527 bool writeback = (P == 0) || (W == 1);
1528 unsigned idx_mode = 0;
1531 else if (!P && writeback)
1534 if (writeback && (Rn == 15 || Rn == Rt))
1541 switch( fieldFromInstruction(Insn, 5, 2)) {
1557 unsigned amt = fieldFromInstruction(Insn, 7, 5);
1576 uint64_t
Address,
const void *Decoder) {
1579 unsigned Rn = fieldFromInstruction(Val, 13, 4);
1580 unsigned Rm = fieldFromInstruction(Val, 0, 4);
1581 unsigned type = fieldFromInstruction(Val, 5, 2);
1582 unsigned imm = fieldFromInstruction(Val, 7, 5);
1583 unsigned U = fieldFromInstruction(Val, 12, 1);
1620 uint64_t
Address,
const void *Decoder) {
1623 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
1624 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1625 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
1626 unsigned type = fieldFromInstruction(Insn, 22, 1);
1627 unsigned imm = fieldFromInstruction(Insn, 8, 4);
1628 unsigned U = ((~fieldFromInstruction(Insn, 23, 1)) & 1) << 8;
1629 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1630 unsigned W = fieldFromInstruction(Insn, 21, 1);
1631 unsigned P = fieldFromInstruction(Insn, 24, 1);
1632 unsigned Rt2 = Rt + 1;
1634 bool writeback = (W == 1) | (P == 0);
1640 case ARM::STRD_POST:
1643 case ARM::LDRD_POST:
1652 case ARM::STRD_POST:
1653 if (P == 0 && W == 1)
1656 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2))
1658 if (type && Rm == 15)
1662 if (!type && fieldFromInstruction(Insn, 8, 4))
1667 case ARM::STRH_POST:
1670 if (writeback && (Rn == 15 || Rn == Rt))
1672 if (!type && Rm == 15)
1677 case ARM::LDRD_POST:
1678 if (type && Rn == 15) {
1683 if (P == 0 && W == 1)
1685 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2))
1687 if (!type && writeback && Rn == 15)
1689 if (writeback && (Rn == Rt || Rn == Rt2))
1694 case ARM::LDRH_POST:
1695 if (type && Rn == 15) {
1702 if (!type && Rm == 15)
1704 if (!type && writeback && (Rn == 15 || Rn == Rt))
1708 case ARM::LDRSH_PRE:
1709 case ARM::LDRSH_POST:
1711 case ARM::LDRSB_PRE:
1712 case ARM::LDRSB_POST:
1713 if (type && Rn == 15) {
1718 if (type && (Rt == 15 || (writeback && Rn == Rt)))
1720 if (!type && (Rt == 15 || Rm == 15))
1722 if (!type && writeback && (Rn == 15 || Rn == Rt))
1739 case ARM::STRD_POST:
1742 case ARM::STRH_POST:
1756 case ARM::STRD_POST:
1759 case ARM::LDRD_POST:
1772 case ARM::LDRD_POST:
1775 case ARM::LDRH_POST:
1777 case ARM::LDRSH_PRE:
1778 case ARM::LDRSH_POST:
1780 case ARM::LDRSB_PRE:
1781 case ARM::LDRSB_POST:
1811 uint64_t
Address,
const void *Decoder) {
1814 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1815 unsigned mode = fieldFromInstruction(Insn, 23, 2);
1840 uint64_t
Address,
const void *Decoder) {
1843 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
1844 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
1845 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1846 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1864 uint64_t
Address,
const void *Decoder) {
1867 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1868 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1869 unsigned reglist = fieldFromInstruction(Insn, 0, 16);
1877 case ARM::LDMDA_UPD:
1883 case ARM::LDMDB_UPD:
1889 case ARM::LDMIA_UPD:
1895 case ARM::LDMIB_UPD:
1901 case ARM::STMDA_UPD:
1907 case ARM::STMDB_UPD:
1913 case ARM::STMIA_UPD:
1919 case ARM::STMIB_UPD:
1927 if (fieldFromInstruction(Insn, 20, 1) == 0) {
1929 if (!(fieldFromInstruction(Insn, 22, 1) == 1 &&
1930 fieldFromInstruction(Insn, 20, 1) == 0))
1955 uint64_t
Address,
const void *Decoder) {
1956 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1957 unsigned imm8 = fieldFromInstruction(Insn, 0, 8);
1970 if (imm8 == 0x10 && pred != 0xe && ((FeatureBits[ARM::FeatureRAS]) != 0))
1977 uint64_t
Address,
const void *Decoder) {
1978 unsigned imod = fieldFromInstruction(Insn, 18, 2);
1979 unsigned M = fieldFromInstruction(Insn, 17, 1);
1980 unsigned iflags = fieldFromInstruction(Insn, 6, 3);
1981 unsigned mode = fieldFromInstruction(Insn, 0, 5);
1987 if (fieldFromInstruction(Insn, 5, 1) != 0 ||
1988 fieldFromInstruction(Insn, 16, 1) != 0 ||
1989 fieldFromInstruction(Insn, 20, 8) != 0x10)
2004 }
else if (imod && !M) {
2009 }
else if (!imod && M) {
2024 uint64_t
Address,
const void *Decoder) {
2025 unsigned imod = fieldFromInstruction(Insn, 9, 2);
2026 unsigned M = fieldFromInstruction(Insn, 8, 1);
2027 unsigned iflags = fieldFromInstruction(Insn, 5, 3);
2028 unsigned mode = fieldFromInstruction(Insn, 0, 5);
2044 }
else if (imod && !M) {
2049 }
else if (!imod && M) {
2055 int imm = fieldFromInstruction(Insn, 0, 8);
2066 uint64_t
Address,
const void *Decoder) {
2069 unsigned Rd = fieldFromInstruction(Insn, 8, 4);
2072 imm |= (fieldFromInstruction(Insn, 0, 8) << 0);
2073 imm |= (fieldFromInstruction(Insn, 12, 3) << 8);
2074 imm |= (fieldFromInstruction(Insn, 16, 4) << 12);
2075 imm |= (fieldFromInstruction(Insn, 26, 1) << 11);
2090 uint64_t
Address,
const void *Decoder) {
2093 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2094 unsigned pred = fieldFromInstruction(Insn, 28, 4);
2097 imm |= (fieldFromInstruction(Insn, 0, 12) << 0);
2098 imm |= (fieldFromInstruction(Insn, 16, 4) << 12);
2117 uint64_t
Address,
const void *Decoder) {
2120 unsigned Rd = fieldFromInstruction(Insn, 16, 4);
2121 unsigned Rn = fieldFromInstruction(Insn, 0, 4);
2122 unsigned Rm = fieldFromInstruction(Insn, 8, 4);
2123 unsigned Ra = fieldFromInstruction(Insn, 12, 4);
2124 unsigned pred = fieldFromInstruction(Insn, 28, 4);
2145 uint64_t
Address,
const void *Decoder) {
2148 unsigned Pred = fieldFromInstruction(Insn, 28, 4);
2149 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2150 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2166 uint64_t
Address,
const void *Decoder) {
2169 unsigned Imm = fieldFromInstruction(Insn, 9, 1);
2174 if (!FeatureBits[ARM::HasV8_1aOps] ||
2175 !FeatureBits[ARM::HasV8Ops])
2180 if (fieldFromInstruction(Insn, 20,12) != 0xf11 ||
2181 fieldFromInstruction(Insn, 4,4) != 0)
2183 if (fieldFromInstruction(Insn, 10,10) != 0 ||
2184 fieldFromInstruction(Insn, 0,4) != 0)
2194 uint64_t
Address,
const void *Decoder) {
2197 unsigned add = fieldFromInstruction(Val, 12, 1);
2198 unsigned imm = fieldFromInstruction(Val, 0, 12);
2199 unsigned Rn = fieldFromInstruction(Val, 13, 4);
2204 if (!add) imm *= -1;
2205 if (imm == 0 && !add) imm = INT32_MIN;
2214 uint64_t
Address,
const void *Decoder) {
2217 unsigned Rn = fieldFromInstruction(Val, 9, 4);
2219 unsigned U = fieldFromInstruction(Val, 8, 1);
2220 unsigned imm = fieldFromInstruction(Val, 0, 8);
2234 uint64_t
Address,
const void *Decoder) {
2237 unsigned Rn = fieldFromInstruction(Val, 9, 4);
2239 unsigned U = fieldFromInstruction(Val, 8, 1);
2240 unsigned imm = fieldFromInstruction(Val, 0, 8);
2254 uint64_t
Address,
const void *Decoder) {
2260 uint64_t
Address,
const void *Decoder) {
2269 unsigned S = fieldFromInstruction(Insn, 26, 1);
2270 unsigned J1 = fieldFromInstruction(Insn, 13, 1);
2271 unsigned J2 = fieldFromInstruction(Insn, 11, 1);
2272 unsigned I1 = !(J1 ^ S);
2273 unsigned I2 = !(J2 ^ S);
2274 unsigned imm10 = fieldFromInstruction(Insn, 16, 10);
2275 unsigned imm11 = fieldFromInstruction(Insn, 0, 11);
2276 unsigned tmp = (S << 23) | (I1 << 22) | (I2 << 21) | (imm10 << 11) | imm11;
2277 int imm32 = SignExtend32<25>(tmp << 1);
2279 true, 4, Inst, Decoder))
2287 uint64_t
Address,
const void *Decoder) {
2290 unsigned pred = fieldFromInstruction(Insn, 28, 4);
2291 unsigned imm = fieldFromInstruction(Insn, 0, 24) << 2;
2295 imm |= fieldFromInstruction(Insn, 24, 1) << 1;
2297 true, 4, Inst, Decoder))
2303 true, 4, Inst, Decoder))
2312 uint64_t
Address,
const void *Decoder) {
2315 unsigned Rm = fieldFromInstruction(Val, 0, 4);
2316 unsigned align = fieldFromInstruction(Val, 4, 2);
2329 uint64_t
Address,
const void *Decoder) {
2332 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2333 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2334 unsigned wb = fieldFromInstruction(Insn, 16, 4);
2335 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2336 Rn |= fieldFromInstruction(Insn, 4, 2) << 4;
2337 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2341 case ARM::VLD1q16:
case ARM::VLD1q32:
case ARM::VLD1q64:
case ARM::VLD1q8:
2342 case ARM::VLD1q16wb_fixed:
case ARM::VLD1q16wb_register:
2343 case ARM::VLD1q32wb_fixed:
case ARM::VLD1q32wb_register:
2344 case ARM::VLD1q64wb_fixed:
case ARM::VLD1q64wb_register:
2345 case ARM::VLD1q8wb_fixed:
case ARM::VLD1q8wb_register:
2346 case ARM::VLD2d16:
case ARM::VLD2d32:
case ARM::VLD2d8:
2347 case ARM::VLD2d16wb_fixed:
case ARM::VLD2d16wb_register:
2348 case ARM::VLD2d32wb_fixed:
case ARM::VLD2d32wb_register:
2349 case ARM::VLD2d8wb_fixed:
case ARM::VLD2d8wb_register:
2356 case ARM::VLD2b16wb_fixed:
2357 case ARM::VLD2b16wb_register:
2358 case ARM::VLD2b32wb_fixed:
2359 case ARM::VLD2b32wb_register:
2360 case ARM::VLD2b8wb_fixed:
2361 case ARM::VLD2b8wb_register:
2375 case ARM::VLD3d8_UPD:
2376 case ARM::VLD3d16_UPD:
2377 case ARM::VLD3d32_UPD:
2381 case ARM::VLD4d8_UPD:
2382 case ARM::VLD4d16_UPD:
2383 case ARM::VLD4d32_UPD:
2390 case ARM::VLD3q8_UPD:
2391 case ARM::VLD3q16_UPD:
2392 case ARM::VLD3q32_UPD:
2396 case ARM::VLD4q8_UPD:
2397 case ARM::VLD4q16_UPD:
2398 case ARM::VLD4q32_UPD:
2411 case ARM::VLD3d8_UPD:
2412 case ARM::VLD3d16_UPD:
2413 case ARM::VLD3d32_UPD:
2417 case ARM::VLD4d8_UPD:
2418 case ARM::VLD4d16_UPD:
2419 case ARM::VLD4d32_UPD:
2426 case ARM::VLD3q8_UPD:
2427 case ARM::VLD3q16_UPD:
2428 case ARM::VLD3q32_UPD:
2432 case ARM::VLD4q8_UPD:
2433 case ARM::VLD4q16_UPD:
2434 case ARM::VLD4q32_UPD:
2447 case ARM::VLD4d8_UPD:
2448 case ARM::VLD4d16_UPD:
2449 case ARM::VLD4d32_UPD:
2456 case ARM::VLD4q8_UPD:
2457 case ARM::VLD4q16_UPD:
2458 case ARM::VLD4q32_UPD:
2468 case ARM::VLD1d8wb_fixed:
2469 case ARM::VLD1d16wb_fixed:
2470 case ARM::VLD1d32wb_fixed:
2471 case ARM::VLD1d64wb_fixed:
2472 case ARM::VLD1d8wb_register:
2473 case ARM::VLD1d16wb_register:
2474 case ARM::VLD1d32wb_register:
2475 case ARM::VLD1d64wb_register:
2476 case ARM::VLD1q8wb_fixed:
2477 case ARM::VLD1q16wb_fixed:
2478 case ARM::VLD1q32wb_fixed:
2479 case ARM::VLD1q64wb_fixed:
2480 case ARM::VLD1q8wb_register:
2481 case ARM::VLD1q16wb_register:
2482 case ARM::VLD1q32wb_register:
2483 case ARM::VLD1q64wb_register:
2484 case ARM::VLD1d8Twb_fixed:
2485 case ARM::VLD1d8Twb_register:
2486 case ARM::VLD1d16Twb_fixed:
2487 case ARM::VLD1d16Twb_register:
2488 case ARM::VLD1d32Twb_fixed:
2489 case ARM::VLD1d32Twb_register:
2490 case ARM::VLD1d64Twb_fixed:
2491 case ARM::VLD1d64Twb_register:
2492 case ARM::VLD1d8Qwb_fixed:
2493 case ARM::VLD1d8Qwb_register:
2494 case ARM::VLD1d16Qwb_fixed:
2495 case ARM::VLD1d16Qwb_register:
2496 case ARM::VLD1d32Qwb_fixed:
2497 case ARM::VLD1d32Qwb_register:
2498 case ARM::VLD1d64Qwb_fixed:
2499 case ARM::VLD1d64Qwb_register:
2500 case ARM::VLD2d8wb_fixed:
2501 case ARM::VLD2d16wb_fixed:
2502 case ARM::VLD2d32wb_fixed:
2503 case ARM::VLD2q8wb_fixed:
2504 case ARM::VLD2q16wb_fixed:
2505 case ARM::VLD2q32wb_fixed:
2506 case ARM::VLD2d8wb_register:
2507 case ARM::VLD2d16wb_register:
2508 case ARM::VLD2d32wb_register:
2509 case ARM::VLD2q8wb_register:
2510 case ARM::VLD2q16wb_register:
2511 case ARM::VLD2q32wb_register:
2512 case ARM::VLD2b8wb_fixed:
2513 case ARM::VLD2b16wb_fixed:
2514 case ARM::VLD2b32wb_fixed:
2515 case ARM::VLD2b8wb_register:
2516 case ARM::VLD2b16wb_register:
2517 case ARM::VLD2b32wb_register:
2520 case ARM::VLD3d8_UPD:
2521 case ARM::VLD3d16_UPD:
2522 case ARM::VLD3d32_UPD:
2523 case ARM::VLD3q8_UPD:
2524 case ARM::VLD3q16_UPD:
2525 case ARM::VLD3q32_UPD:
2526 case ARM::VLD4d8_UPD:
2527 case ARM::VLD4d16_UPD:
2528 case ARM::VLD4d32_UPD:
2529 case ARM::VLD4q8_UPD:
2530 case ARM::VLD4q16_UPD:
2531 case ARM::VLD4q32_UPD:
2558 case ARM::VLD1d8wb_fixed:
2559 case ARM::VLD1d16wb_fixed:
2560 case ARM::VLD1d32wb_fixed:
2561 case ARM::VLD1d64wb_fixed:
2562 case ARM::VLD1d8Twb_fixed:
2563 case ARM::VLD1d16Twb_fixed:
2564 case ARM::VLD1d32Twb_fixed:
2565 case ARM::VLD1d64Twb_fixed:
2566 case ARM::VLD1d8Qwb_fixed:
2567 case ARM::VLD1d16Qwb_fixed:
2568 case ARM::VLD1d32Qwb_fixed:
2569 case ARM::VLD1d64Qwb_fixed:
2570 case ARM::VLD1d8wb_register:
2571 case ARM::VLD1d16wb_register:
2572 case ARM::VLD1d32wb_register:
2573 case ARM::VLD1d64wb_register:
2574 case ARM::VLD1q8wb_fixed:
2575 case ARM::VLD1q16wb_fixed:
2576 case ARM::VLD1q32wb_fixed:
2577 case ARM::VLD1q64wb_fixed:
2578 case ARM::VLD1q8wb_register:
2579 case ARM::VLD1q16wb_register:
2580 case ARM::VLD1q32wb_register:
2581 case ARM::VLD1q64wb_register:
2585 if (Rm != 0xD && Rm != 0xF &&
2589 case ARM::VLD2d8wb_fixed:
2590 case ARM::VLD2d16wb_fixed:
2591 case ARM::VLD2d32wb_fixed:
2592 case ARM::VLD2b8wb_fixed:
2593 case ARM::VLD2b16wb_fixed:
2594 case ARM::VLD2b32wb_fixed:
2595 case ARM::VLD2q8wb_fixed:
2596 case ARM::VLD2q16wb_fixed:
2597 case ARM::VLD2q32wb_fixed:
2605 uint64_t
Address,
const void *Decoder) {
2606 unsigned type = fieldFromInstruction(Insn, 8, 4);
2607 unsigned align = fieldFromInstruction(Insn, 4, 2);
2612 unsigned load = fieldFromInstruction(Insn, 21, 1);
2618 uint64_t
Address,
const void *Decoder) {
2619 unsigned size = fieldFromInstruction(Insn, 6, 2);
2622 unsigned type = fieldFromInstruction(Insn, 8, 4);
2623 unsigned align = fieldFromInstruction(Insn, 4, 2);
2627 unsigned load = fieldFromInstruction(Insn, 21, 1);
2633 uint64_t
Address,
const void *Decoder) {
2634 unsigned size = fieldFromInstruction(Insn, 6, 2);
2637 unsigned align = fieldFromInstruction(Insn, 4, 2);
2640 unsigned load = fieldFromInstruction(Insn, 21, 1);
2646 uint64_t
Address,
const void *Decoder) {
2647 unsigned size = fieldFromInstruction(Insn, 6, 2);
2650 unsigned load = fieldFromInstruction(Insn, 21, 1);
2656 uint64_t
Address,
const void *Decoder) {
2659 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2660 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2661 unsigned wb = fieldFromInstruction(Insn, 16, 4);
2662 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2663 Rn |= fieldFromInstruction(Insn, 4, 2) << 4;
2664 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2668 case ARM::VST1d8wb_fixed:
2669 case ARM::VST1d16wb_fixed:
2670 case ARM::VST1d32wb_fixed:
2671 case ARM::VST1d64wb_fixed:
2672 case ARM::VST1d8wb_register:
2673 case ARM::VST1d16wb_register:
2674 case ARM::VST1d32wb_register:
2675 case ARM::VST1d64wb_register:
2676 case ARM::VST1q8wb_fixed:
2677 case ARM::VST1q16wb_fixed:
2678 case ARM::VST1q32wb_fixed:
2679 case ARM::VST1q64wb_fixed:
2680 case ARM::VST1q8wb_register:
2681 case ARM::VST1q16wb_register:
2682 case ARM::VST1q32wb_register:
2683 case ARM::VST1q64wb_register:
2684 case ARM::VST1d8Twb_fixed:
2685 case ARM::VST1d16Twb_fixed:
2686 case ARM::VST1d32Twb_fixed:
2687 case ARM::VST1d64Twb_fixed:
2688 case ARM::VST1d8Twb_register:
2689 case ARM::VST1d16Twb_register:
2690 case ARM::VST1d32Twb_register:
2691 case ARM::VST1d64Twb_register:
2692 case ARM::VST1d8Qwb_fixed:
2693 case ARM::VST1d16Qwb_fixed:
2694 case ARM::VST1d32Qwb_fixed:
2695 case ARM::VST1d64Qwb_fixed:
2696 case ARM::VST1d8Qwb_register:
2697 case ARM::VST1d16Qwb_register:
2698 case ARM::VST1d32Qwb_register:
2699 case ARM::VST1d64Qwb_register:
2700 case ARM::VST2d8wb_fixed:
2701 case ARM::VST2d16wb_fixed:
2702 case ARM::VST2d32wb_fixed:
2703 case ARM::VST2d8wb_register:
2704 case ARM::VST2d16wb_register:
2705 case ARM::VST2d32wb_register:
2706 case ARM::VST2q8wb_fixed:
2707 case ARM::VST2q16wb_fixed:
2708 case ARM::VST2q32wb_fixed:
2709 case ARM::VST2q8wb_register:
2710 case ARM::VST2q16wb_register:
2711 case ARM::VST2q32wb_register:
2712 case ARM::VST2b8wb_fixed:
2713 case ARM::VST2b16wb_fixed:
2714 case ARM::VST2b32wb_fixed:
2715 case ARM::VST2b8wb_register:
2716 case ARM::VST2b16wb_register:
2717 case ARM::VST2b32wb_register:
2722 case ARM::VST3d8_UPD:
2723 case ARM::VST3d16_UPD:
2724 case ARM::VST3d32_UPD:
2725 case ARM::VST3q8_UPD:
2726 case ARM::VST3q16_UPD:
2727 case ARM::VST3q32_UPD:
2728 case ARM::VST4d8_UPD:
2729 case ARM::VST4d16_UPD:
2730 case ARM::VST4d32_UPD:
2731 case ARM::VST4q8_UPD:
2732 case ARM::VST4q16_UPD:
2733 case ARM::VST4q32_UPD:
2750 else if (Rm != 0xF) {
2755 case ARM::VST1d8wb_fixed:
2756 case ARM::VST1d16wb_fixed:
2757 case ARM::VST1d32wb_fixed:
2758 case ARM::VST1d64wb_fixed:
2759 case ARM::VST1q8wb_fixed:
2760 case ARM::VST1q16wb_fixed:
2761 case ARM::VST1q32wb_fixed:
2762 case ARM::VST1q64wb_fixed:
2763 case ARM::VST1d8Twb_fixed:
2764 case ARM::VST1d16Twb_fixed:
2765 case ARM::VST1d32Twb_fixed:
2766 case ARM::VST1d64Twb_fixed:
2767 case ARM::VST1d8Qwb_fixed:
2768 case ARM::VST1d16Qwb_fixed:
2769 case ARM::VST1d32Qwb_fixed:
2770 case ARM::VST1d64Qwb_fixed:
2771 case ARM::VST2d8wb_fixed:
2772 case ARM::VST2d16wb_fixed:
2773 case ARM::VST2d32wb_fixed:
2774 case ARM::VST2q8wb_fixed:
2775 case ARM::VST2q16wb_fixed:
2776 case ARM::VST2q32wb_fixed:
2777 case ARM::VST2b8wb_fixed:
2778 case ARM::VST2b16wb_fixed:
2779 case ARM::VST2b32wb_fixed:
2789 case ARM::VST1q16wb_fixed:
2790 case ARM::VST1q16wb_register:
2791 case ARM::VST1q32wb_fixed:
2792 case ARM::VST1q32wb_register:
2793 case ARM::VST1q64wb_fixed:
2794 case ARM::VST1q64wb_register:
2795 case ARM::VST1q8wb_fixed:
2796 case ARM::VST1q8wb_register:
2800 case ARM::VST2d16wb_fixed:
2801 case ARM::VST2d16wb_register:
2802 case ARM::VST2d32wb_fixed:
2803 case ARM::VST2d32wb_register:
2804 case ARM::VST2d8wb_fixed:
2805 case ARM::VST2d8wb_register:
2812 case ARM::VST2b16wb_fixed:
2813 case ARM::VST2b16wb_register:
2814 case ARM::VST2b32wb_fixed:
2815 case ARM::VST2b32wb_register:
2816 case ARM::VST2b8wb_fixed:
2817 case ARM::VST2b8wb_register:
2831 case ARM::VST3d8_UPD:
2832 case ARM::VST3d16_UPD:
2833 case ARM::VST3d32_UPD:
2837 case ARM::VST4d8_UPD:
2838 case ARM::VST4d16_UPD:
2839 case ARM::VST4d32_UPD:
2846 case ARM::VST3q8_UPD:
2847 case ARM::VST3q16_UPD:
2848 case ARM::VST3q32_UPD:
2852 case ARM::VST4q8_UPD:
2853 case ARM::VST4q16_UPD:
2854 case ARM::VST4q32_UPD:
2867 case ARM::VST3d8_UPD:
2868 case ARM::VST3d16_UPD:
2869 case ARM::VST3d32_UPD:
2873 case ARM::VST4d8_UPD:
2874 case ARM::VST4d16_UPD:
2875 case ARM::VST4d32_UPD:
2882 case ARM::VST3q8_UPD:
2883 case ARM::VST3q16_UPD:
2884 case ARM::VST3q32_UPD:
2888 case ARM::VST4q8_UPD:
2889 case ARM::VST4q16_UPD:
2890 case ARM::VST4q32_UPD:
2903 case ARM::VST4d8_UPD:
2904 case ARM::VST4d16_UPD:
2905 case ARM::VST4d32_UPD:
2912 case ARM::VST4q8_UPD:
2913 case ARM::VST4q16_UPD:
2914 case ARM::VST4q32_UPD:
2926 uint64_t
Address,
const void *Decoder) {
2929 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2930 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2931 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2932 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2933 unsigned align = fieldFromInstruction(Insn, 4, 1);
2934 unsigned size = fieldFromInstruction(Insn, 6, 2);
2936 if (size == 0 && align == 1)
2938 align *= (1 <<
size);
2941 case ARM::VLD1DUPq16:
case ARM::VLD1DUPq32:
case ARM::VLD1DUPq8:
2942 case ARM::VLD1DUPq16wb_fixed:
case ARM::VLD1DUPq16wb_register:
2943 case ARM::VLD1DUPq32wb_fixed:
case ARM::VLD1DUPq32wb_register:
2944 case ARM::VLD1DUPq8wb_fixed:
case ARM::VLD1DUPq8wb_register:
2965 if (Rm != 0xD && Rm != 0xF &&
2973 uint64_t
Address,
const void *Decoder) {
2976 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2977 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2978 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2979 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2980 unsigned align = fieldFromInstruction(Insn, 4, 1);
2981 unsigned size = 1 << fieldFromInstruction(Insn, 6, 2);
2985 case ARM::VLD2DUPd16:
case ARM::VLD2DUPd32:
case ARM::VLD2DUPd8:
2986 case ARM::VLD2DUPd16wb_fixed:
case ARM::VLD2DUPd16wb_register:
2987 case ARM::VLD2DUPd32wb_fixed:
case ARM::VLD2DUPd32wb_register:
2988 case ARM::VLD2DUPd8wb_fixed:
case ARM::VLD2DUPd8wb_register:
2992 case ARM::VLD2DUPd16x2:
case ARM::VLD2DUPd32x2:
case ARM::VLD2DUPd8x2:
2993 case ARM::VLD2DUPd16x2wb_fixed:
case ARM::VLD2DUPd16x2wb_register:
2994 case ARM::VLD2DUPd32x2wb_fixed:
case ARM::VLD2DUPd32x2wb_register:
2995 case ARM::VLD2DUPd8x2wb_fixed:
case ARM::VLD2DUPd8x2wb_register:
3012 if (Rm != 0xD && Rm != 0xF) {
3021 uint64_t
Address,
const void *Decoder) {
3024 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3025 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3026 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3027 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3028 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1;
3047 else if (Rm != 0xF) {
3056 uint64_t
Address,
const void *Decoder) {
3059 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3060 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3061 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3062 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3063 unsigned size = fieldFromInstruction(Insn, 6, 2);
3064 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1;
3065 unsigned align = fieldFromInstruction(Insn, 4, 1);
3099 else if (Rm != 0xF) {
3109 uint64_t
Address,
const void *Decoder) {
3112 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3113 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3114 unsigned imm = fieldFromInstruction(Insn, 0, 4);
3115 imm |= fieldFromInstruction(Insn, 16, 3) << 4;
3116 imm |= fieldFromInstruction(Insn, 24, 1) << 7;
3117 imm |= fieldFromInstruction(Insn, 8, 4) << 8;
3118 imm |= fieldFromInstruction(Insn, 5, 1) << 12;
3119 unsigned Q = fieldFromInstruction(Insn, 6, 1);
3132 case ARM::VORRiv4i16:
3133 case ARM::VORRiv2i32:
3134 case ARM::VBICiv4i16:
3135 case ARM::VBICiv2i32:
3139 case ARM::VORRiv8i16:
3140 case ARM::VORRiv4i32:
3141 case ARM::VBICiv8i16:
3142 case ARM::VBICiv4i32:
3154 uint64_t
Address,
const void *Decoder) {
3157 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3158 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3159 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3160 Rm |= fieldFromInstruction(Insn, 5, 1) << 4;
3161 unsigned size = fieldFromInstruction(Insn, 18, 2);
3173 uint64_t
Address,
const void *Decoder) {
3179 uint64_t
Address,
const void *Decoder) {
3185 uint64_t
Address,
const void *Decoder) {
3191 uint64_t
Address,
const void *Decoder) {
3197 uint64_t
Address,
const void *Decoder) {
3200 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3201 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3202 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3203 Rn |= fieldFromInstruction(Insn, 7, 1) << 4;
3204 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3205 Rm |= fieldFromInstruction(Insn, 5, 1) << 4;
3206 unsigned op = fieldFromInstruction(Insn, 6, 1);
3233 uint64_t
Address,
const void *Decoder) {
3236 unsigned dst = fieldFromInstruction(Insn, 8, 3);
3237 unsigned imm = fieldFromInstruction(Insn, 0, 8);
3257 uint64_t
Address,
const void *Decoder) {
3259 true, 2, Inst, Decoder))
3265 uint64_t
Address,
const void *Decoder) {
3267 true, 4, Inst, Decoder))
3273 uint64_t
Address,
const void *Decoder) {
3275 true, 2, Inst, Decoder))
3281 uint64_t
Address,
const void *Decoder) {
3284 unsigned Rn = fieldFromInstruction(Val, 0, 3);
3285 unsigned Rm = fieldFromInstruction(Val, 3, 3);
3296 uint64_t
Address,
const void *Decoder) {
3299 unsigned Rn = fieldFromInstruction(Val, 0, 3);
3300 unsigned imm = fieldFromInstruction(Val, 3, 5);
3310 uint64_t
Address,
const void *Decoder) {
3311 unsigned imm = Val << 2;
3320 uint64_t
Address,
const void *Decoder) {
3328 uint64_t
Address,
const void *Decoder) {
3331 unsigned Rn = fieldFromInstruction(Val, 6, 4);
3332 unsigned Rm = fieldFromInstruction(Val, 2, 4);
3333 unsigned imm = fieldFromInstruction(Val, 0, 2);
3357 uint64_t
Address,
const void *Decoder) {
3360 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3361 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3364 ((
const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
3366 bool hasMP = featureBits[ARM::FeatureMP];
3367 bool hasV7Ops = featureBits[ARM::HasV7Ops];
3422 if (!hasV7Ops || !hasMP)
3430 unsigned addrmode = fieldFromInstruction(Insn, 4, 2);
3431 addrmode |= fieldFromInstruction(Insn, 0, 4) << 2;
3432 addrmode |= fieldFromInstruction(Insn, 16, 4) << 6;
3440 uint64_t
Address,
const void* Decoder) {
3443 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3444 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3445 unsigned U = fieldFromInstruction(Insn, 9, 1);
3446 unsigned imm = fieldFromInstruction(Insn, 0, 8);
3449 unsigned add = fieldFromInstruction(Insn, 9, 1);
3452 ((
const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
3454 bool hasMP = featureBits[ARM::FeatureMP];
3455 bool hasV7Ops = featureBits[ARM::HasV7Ops];
3465 case ARM::t2LDRSBi8:
3471 case ARM::t2LDRSHi8:
3488 case ARM::t2LDRSHi8:
3494 case ARM::t2LDRSBi8:
3510 if (!hasV7Ops || !hasMP)
3524 uint64_t
Address,
const void* Decoder) {
3527 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3528 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3529 unsigned imm = fieldFromInstruction(Insn, 0, 12);
3533 ((
const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
3535 bool hasMP = featureBits[ARM::FeatureMP];
3536 bool hasV7Ops = featureBits[ARM::HasV7Ops];
3543 case ARM::t2LDRHi12:
3546 case ARM::t2LDRSHi12:
3549 case ARM::t2LDRBi12:
3552 case ARM::t2LDRSBi12:
3569 case ARM::t2LDRSHi12:
3571 case ARM::t2LDRHi12:
3574 case ARM::t2LDRSBi12:
3589 case ARM::t2PLDWi12:
3590 if (!hasV7Ops || !hasMP)
3604 uint64_t
Address,
const void* Decoder) {
3607 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3608 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3609 unsigned imm = fieldFromInstruction(Insn, 0, 8);
3643 uint64_t
Address,
const void* Decoder) {
3646 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3647 unsigned U = fieldFromInstruction(Insn, 23, 1);
3648 int imm = fieldFromInstruction(Insn, 0, 12);
3651 ((
const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
3653 bool hasV7Ops = featureBits[ARM::HasV7Ops];
3657 case ARM::t2LDRBpci:
3658 case ARM::t2LDRHpci:
3661 case ARM::t2LDRSBpci:
3664 case ARM::t2LDRSHpci:
3696 uint64_t
Address,
const void *Decoder) {
3700 int imm = Val & 0xFF;
3702 if (!(Val & 0x100)) imm *= -1;
3710 uint64_t
Address,
const void *Decoder) {
3713 unsigned Rn = fieldFromInstruction(Val, 9, 4);
3714 unsigned imm = fieldFromInstruction(Val, 0, 9);
3725 uint64_t
Address,
const void *Decoder) {
3728 unsigned Rn = fieldFromInstruction(Val, 8, 4);
3729 unsigned imm = fieldFromInstruction(Val, 0, 8);
3740 uint64_t
Address,
const void *Decoder) {
3741 int imm = Val & 0xFF;
3744 else if (!(Val & 0x100))
3752 uint64_t
Address,
const void *Decoder) {
3755 unsigned Rn = fieldFromInstruction(Val, 9, 4);
3756 unsigned imm = fieldFromInstruction(Val, 0, 9);
3798 uint64_t
Address,
const void *Decoder) {
3801 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3802 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3803 unsigned addr = fieldFromInstruction(Insn, 0, 8);
3804 addr |= fieldFromInstruction(Insn, 9, 1) << 8;
3806 unsigned load = fieldFromInstruction(Insn, 20, 1);
3810 case ARM::t2LDR_PRE:
3811 case ARM::t2LDR_POST:
3814 case ARM::t2LDRB_PRE:
3815 case ARM::t2LDRB_POST:
3818 case ARM::t2LDRH_PRE:
3819 case ARM::t2LDRH_POST:
3822 case ARM::t2LDRSB_PRE:
3823 case ARM::t2LDRSB_POST:
3829 case ARM::t2LDRSH_PRE:
3830 case ARM::t2LDRSH_POST:
3859 uint64_t
Address,
const void *Decoder) {
3862 unsigned Rn = fieldFromInstruction(Val, 13, 4);
3863 unsigned imm = fieldFromInstruction(Val, 0, 12);
3868 case ARM::t2STRBi12:
3869 case ARM::t2STRHi12:
3885 uint64_t
Address,
const void *Decoder) {
3886 unsigned imm = fieldFromInstruction(Insn, 0, 7);
3896 uint64_t
Address,
const void *Decoder) {
3900 unsigned Rdm = fieldFromInstruction(Insn, 0, 3);
3901 Rdm |= fieldFromInstruction(Insn, 7, 1) << 3;
3908 }
else if (Inst.
getOpcode() == ARM::tADDspr) {
3909 unsigned Rm = fieldFromInstruction(Insn, 3, 4);
3921 uint64_t
Address,
const void *Decoder) {
3922 unsigned imod = fieldFromInstruction(Insn, 4, 1) | 0x2;
3923 unsigned flags = fieldFromInstruction(Insn, 0, 3);
3932 uint64_t
Address,
const void *Decoder) {
3934 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3935 unsigned add = fieldFromInstruction(Insn, 4, 1);
3945 uint64_t
Address,
const void *Decoder) {
3953 unsigned S = (Val >> 23) & 1;
3954 unsigned J1 = (Val >> 22) & 1;
3955 unsigned J2 = (Val >> 21) & 1;
3956 unsigned I1 = !(J1 ^ S);
3957 unsigned I2 = !(J2 ^ S);
3958 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21);
3959 int imm32 = SignExtend32<25>(tmp << 1);
3962 (Address & ~2u) + imm32 + 4,
3963 true, 4, Inst, Decoder))
3969 uint64_t
Address,
const void *Decoder) {
3970 if (Val == 0xA || Val == 0xB)
3974 ((
const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
3976 if (featureBits[ARM::HasV8Ops] && !(Val == 14 || Val == 15))
3985 uint64_t
Address,
const void *Decoder) {
3988 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3989 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4001 uint64_t
Address,
const void *Decoder) {
4004 unsigned pred = fieldFromInstruction(Insn, 22, 4);
4005 if (pred == 0xE || pred == 0xF) {
4006 unsigned opc = fieldFromInstruction(Insn, 4, 28);
4021 unsigned imm = fieldFromInstruction(Insn, 0, 4);
4025 unsigned brtarget = fieldFromInstruction(Insn, 0, 11) << 1;
4026 brtarget |= fieldFromInstruction(Insn, 11, 1) << 19;
4027 brtarget |= fieldFromInstruction(Insn, 13, 1) << 18;
4028 brtarget |= fieldFromInstruction(Insn, 16, 6) << 12;
4029 brtarget |= fieldFromInstruction(Insn, 26, 1) << 20;
4043 uint64_t
Address,
const void *Decoder) {
4044 unsigned ctrl = fieldFromInstruction(Val, 10, 2);
4046 unsigned byte = fieldFromInstruction(Val, 8, 2);
4047 unsigned imm = fieldFromInstruction(Val, 0, 8);
4064 unsigned unrot = fieldFromInstruction(Val, 0, 7) | 0x80;
4065 unsigned rot = fieldFromInstruction(Val, 7, 5);
4066 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31));
4075 uint64_t
Address,
const void *Decoder) {
4077 true, 2, Inst, Decoder))
4084 const void *Decoder) {
4092 unsigned S = (Val >> 23) & 1;
4093 unsigned J1 = (Val >> 22) & 1;
4094 unsigned J2 = (Val >> 21) & 1;
4095 unsigned I1 = !(J1 ^ S);
4096 unsigned I2 = !(J2 ^ S);
4097 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21);
4098 int imm32 = SignExtend32<25>(tmp << 1);
4101 true, 4, Inst, Decoder))
4107 uint64_t
Address,
const void *Decoder) {
4116 uint64_t
Address,
const void *Decoder) {
4125 uint64_t
Address,
const void *Decoder) {
4128 ((
const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
4130 if (FeatureBits[ARM::FeatureMClass]) {
4131 unsigned ValLow = Val & 0xff;
4150 if (!(FeatureBits[ARM::HasV7Ops]))
4158 if (!(FeatureBits[ARM::HasV8MMainlineOps]))
4168 if (!(FeatureBits[ARM::Feature8MSecExt]))
4178 unsigned Mask = fieldFromInstruction(Val, 10, 2);
4179 if (!(FeatureBits[ARM::HasV7Ops])) {
4192 if (Mask == 0 || (Mask != 2 && ValLow > 3) ||
4193 (!(FeatureBits[ARM::FeatureDSP]) && (Mask & 1)))
4207 uint64_t
Address,
const void *Decoder) {
4208 unsigned R = fieldFromInstruction(Val, 5, 1);
4209 unsigned SysM = fieldFromInstruction(Val, 0, 5);
4214 if (!ARMBankedReg::lookupBankedRegByEncoding((R << 5) | SysM))
4222 uint64_t
Address,
const void *Decoder) {
4225 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4226 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4227 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4244 const void *Decoder) {
4247 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4248 unsigned Rt = fieldFromInstruction(Insn, 0, 4);
4249 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4250 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4255 if (Rn == 0xF || Rd == Rn || Rd == Rt || Rd == Rt+1)
4269 uint64_t
Address,
const void *Decoder) {
4272 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4273 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4274 unsigned imm = fieldFromInstruction(Insn, 0, 12);
4275 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
4276 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
4277 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4294 uint64_t
Address,
const void *Decoder) {
4297 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4298 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4299 unsigned imm = fieldFromInstruction(Insn, 0, 12);
4300 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
4301 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
4302 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4303 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4321 uint64_t
Address,
const void *Decoder) {
4324 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4325 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4326 unsigned imm = fieldFromInstruction(Insn, 0, 12);
4327 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
4328 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
4329 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4346 uint64_t
Address,
const void *Decoder) {
4349 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4350 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4351 unsigned imm = fieldFromInstruction(Insn, 0, 12);
4352 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
4353 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
4354 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4371 uint64_t
Address,
const void *Decoder) {
4374 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4375 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4376 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4377 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4378 unsigned size = fieldFromInstruction(Insn, 10, 2);
4386 if (fieldFromInstruction(Insn, 4, 1))
4388 index = fieldFromInstruction(Insn, 5, 3);
4391 if (fieldFromInstruction(Insn, 5, 1))
4393 index = fieldFromInstruction(Insn, 6, 2);
4394 if (fieldFromInstruction(Insn, 4, 1))
4398 if (fieldFromInstruction(Insn, 6, 1))
4400 index = fieldFromInstruction(Insn, 7, 1);
4402 switch (fieldFromInstruction(Insn, 4, 2)) {
4438 uint64_t
Address,
const void *Decoder) {
4441 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4442 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4443 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4444 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4445 unsigned size = fieldFromInstruction(Insn, 10, 2);
4453 if (fieldFromInstruction(Insn, 4, 1))
4455 index = fieldFromInstruction(Insn, 5, 3);
4458 if (fieldFromInstruction(Insn, 5, 1))
4460 index = fieldFromInstruction(Insn, 6, 2);
4461 if (fieldFromInstruction(Insn, 4, 1))
4465 if (fieldFromInstruction(Insn, 6, 1))
4467 index = fieldFromInstruction(Insn, 7, 1);
4469 switch (fieldFromInstruction(Insn, 4, 2)) {
4503 uint64_t
Address,
const void *Decoder) {
4506 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4507 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4508 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4509 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4510 unsigned size = fieldFromInstruction(Insn, 10, 2);
4519 index = fieldFromInstruction(Insn, 5, 3);
4520 if (fieldFromInstruction(Insn, 4, 1))
4524 index = fieldFromInstruction(Insn, 6, 2);
4525 if (fieldFromInstruction(Insn, 4, 1))
4527 if (fieldFromInstruction(Insn, 5, 1))
4531 if (fieldFromInstruction(Insn, 5, 1))
4533 index = fieldFromInstruction(Insn, 7, 1);
4534 if (fieldFromInstruction(Insn, 4, 1) != 0)
4536 if (fieldFromInstruction(Insn, 6, 1))
4570 uint64_t
Address,
const void *Decoder) {
4573 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4574 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4575 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4576 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4577 unsigned size = fieldFromInstruction(Insn, 10, 2);
4586 index = fieldFromInstruction(Insn, 5, 3);
4587 if (fieldFromInstruction(Insn, 4, 1))
4591 index = fieldFromInstruction(Insn, 6, 2);
4592 if (fieldFromInstruction(Insn, 4, 1))
4594 if (fieldFromInstruction(Insn, 5, 1))
4598 if (fieldFromInstruction(Insn, 5, 1))
4600 index = fieldFromInstruction(Insn, 7, 1);
4601 if (fieldFromInstruction(Insn, 4, 1) != 0)
4603 if (fieldFromInstruction(Insn, 6, 1))
4633 uint64_t
Address,
const void *Decoder) {
4636 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4637 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4638 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4639 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4640 unsigned size = fieldFromInstruction(Insn, 10, 2);
4649 if (fieldFromInstruction(Insn, 4, 1))
4651 index = fieldFromInstruction(Insn, 5, 3);
4654 if (fieldFromInstruction(Insn, 4, 1))
4656 index = fieldFromInstruction(Insn, 6, 2);
4657 if (fieldFromInstruction(Insn, 5, 1))
4661 if (fieldFromInstruction(Insn, 4, 2))
4663 index = fieldFromInstruction(Insn, 7, 1);
4664 if (fieldFromInstruction(Insn, 6, 1))
4703 uint64_t
Address,
const void *Decoder) {
4706 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4707 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4708 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4709 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4710 unsigned size = fieldFromInstruction(Insn, 10, 2);
4719 if (fieldFromInstruction(Insn, 4, 1))
4721 index = fieldFromInstruction(Insn, 5, 3);
4724 if (fieldFromInstruction(Insn, 4, 1))
4726 index = fieldFromInstruction(Insn, 6, 2);
4727 if (fieldFromInstruction(Insn, 5, 1))
4731 if (fieldFromInstruction(Insn, 4, 2))
4733 index = fieldFromInstruction(Insn, 7, 1);
4734 if (fieldFromInstruction(Insn, 6, 1))
4766 uint64_t
Address,
const void *Decoder) {
4769 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4770 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4771 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4772 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4773 unsigned size = fieldFromInstruction(Insn, 10, 2);
4782 if (fieldFromInstruction(Insn, 4, 1))
4784 index = fieldFromInstruction(Insn, 5, 3);
4787 if (fieldFromInstruction(Insn, 4, 1))
4789 index = fieldFromInstruction(Insn, 6, 2);
4790 if (fieldFromInstruction(Insn, 5, 1))
4794 switch (fieldFromInstruction(Insn, 4, 2)) {
4800 align = 4 << fieldFromInstruction(Insn, 4, 2);
break;
4803 index = fieldFromInstruction(Insn, 7, 1);
4804 if (fieldFromInstruction(Insn, 6, 1))
4847 uint64_t
Address,
const void *Decoder) {
4850 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4851 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4852 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4853 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4854 unsigned size = fieldFromInstruction(Insn, 10, 2);
4863 if (fieldFromInstruction(Insn, 4, 1))
4865 index = fieldFromInstruction(Insn, 5, 3);
4868 if (fieldFromInstruction(Insn, 4, 1))
4870 index = fieldFromInstruction(Insn, 6, 2);
4871 if (fieldFromInstruction(Insn, 5, 1))
4875 switch (fieldFromInstruction(Insn, 4, 2)) {
4881 align = 4 << fieldFromInstruction(Insn, 4, 2);
break;
4884 index = fieldFromInstruction(Insn, 7, 1);
4885 if (fieldFromInstruction(Insn, 6, 1))
4919 uint64_t
Address,
const void *Decoder) {
4921 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4922 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
4923 unsigned Rm = fieldFromInstruction(Insn, 5, 1);
4924 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4925 Rm |= fieldFromInstruction(Insn, 0, 4) << 1;
4927 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
4945 uint64_t
Address,
const void *Decoder) {
4947 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4948 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
4949 unsigned Rm = fieldFromInstruction(Insn, 5, 1);
4950 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4951 Rm |= fieldFromInstruction(Insn, 0, 4) << 1;
4953 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
4971 uint64_t
Address,
const void *Decoder) {
4973 unsigned pred = fieldFromInstruction(Insn, 4, 4);
4974 unsigned mask = fieldFromInstruction(Insn, 0, 4);
4991 uint64_t
Address,
const void *Decoder) {
4994 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4995 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4);
4996 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4997 unsigned addr = fieldFromInstruction(Insn, 0, 8);
4998 unsigned W = fieldFromInstruction(Insn, 21, 1);
4999 unsigned U = fieldFromInstruction(Insn, 23, 1);
5000 unsigned P = fieldFromInstruction(Insn, 24, 1);
5001 bool writeback = (W == 1) | (P == 0);
5003 addr |= (U << 8) | (Rn << 9);
5005 if (writeback && (Rn == Rt || Rn == Rt2))
5028 uint64_t
Address,
const void *Decoder) {
5031 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
5032 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4);
5033 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
5034 unsigned addr = fieldFromInstruction(Insn, 0, 8);
5035 unsigned W = fieldFromInstruction(Insn, 21, 1);
5036 unsigned U = fieldFromInstruction(Insn, 23, 1);
5037 unsigned P = fieldFromInstruction(Insn, 24, 1);
5038 bool writeback = (W == 1) | (P == 0);
5040 addr |= (U << 8) | (Rn << 9);
5042 if (writeback && (Rn == Rt || Rn == Rt2))
5062 uint64_t
Address,
const void *Decoder) {
5063 unsigned sign1 = fieldFromInstruction(Insn, 21, 1);
5064 unsigned sign2 = fieldFromInstruction(Insn, 23, 1);
5067 unsigned Val = fieldFromInstruction(Insn, 0, 8);
5068 Val |= fieldFromInstruction(Insn, 12, 3) << 8;
5069 Val |= fieldFromInstruction(Insn, 26, 1) << 11;
5078 const void *Decoder) {
5088 uint64_t
Address,
const void *Decoder) {
5089 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
5090 unsigned Rt2 = fieldFromInstruction(Insn, 0, 4);
5091 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
5092 unsigned pred = fieldFromInstruction(Insn, 28, 4);
5099 if (Rt == Rn || Rn == Rt2)
5115 uint64_t
Address,
const void *Decoder) {
5117 ((
const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits();
5118 bool hasFullFP16 = featureBits[ARM::FeatureFullFP16];
5120 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
5121 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4);
5122 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0);
5123 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4);
5124 unsigned imm = fieldFromInstruction(Insn, 16, 6);
5125 unsigned cmode = fieldFromInstruction(Insn, 8, 4);
5126 unsigned op = fieldFromInstruction(Insn, 5, 1);
5131 if (!(imm & 0x38)) {
5174 uint64_t
Address,
const void *Decoder) {
5176 ((
const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits();
5177 bool hasFullFP16 = featureBits[ARM::FeatureFullFP16];
5179 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
5180 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4);
5181 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0);
5182 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4);
5183 unsigned imm = fieldFromInstruction(Insn, 16, 6);
5184 unsigned cmode = fieldFromInstruction(Insn, 8, 4);
5185 unsigned op = fieldFromInstruction(Insn, 5, 1);
5190 if (!(imm & 0x38)) {
5235 const void *Decoder) {
5236 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
5237 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4);
5238 unsigned Vn = (fieldFromInstruction(Insn, 16, 4) << 0);
5239 Vn |= (fieldFromInstruction(Insn, 7, 1) << 4);
5240 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0);
5241 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4);
5242 unsigned q = (fieldFromInstruction(Insn, 6, 1) << 0);
5243 unsigned rotate = (fieldFromInstruction(Insn, 20, 2) << 0);
5249 if (!
Check(S, DestRegDecoder(Inst, Vd, Address, Decoder)))
5251 if (!
Check(S, DestRegDecoder(Inst, Vd, Address, Decoder)))
5253 if (!
Check(S, DestRegDecoder(Inst, Vn, Address, Decoder)))
5266 uint64_t
Address,
const void *Decoder) {
5269 unsigned Rn = fieldFromInstruction(Val, 16, 4);
5270 unsigned Rt = fieldFromInstruction(Val, 12, 4);
5271 unsigned Rm = fieldFromInstruction(Val, 0, 4);
5272 Rm |= (fieldFromInstruction(Val, 23, 1) << 4);
5273 unsigned Cond = fieldFromInstruction(Val, 28, 4);
5275 if (fieldFromInstruction(Val, 8, 4) != 0 || Rn == Rt)
5293 uint64_t
Address,
const void *Decoder) {
5296 unsigned CRm = fieldFromInstruction(Val, 0, 4);
5297 unsigned opc1 = fieldFromInstruction(Val, 4, 4);
5298 unsigned cop = fieldFromInstruction(Val, 8, 4);
5299 unsigned Rt = fieldFromInstruction(Val, 12, 4);
5300 unsigned Rt2 = fieldFromInstruction(Val, 16, 4);
5302 if ((cop & ~0x1) == 0xa)
5339 const void *Decoder) {
5341 ((
const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits();
5344 unsigned Rt = fieldFromInstruction(Val, 12, 4);
5346 if (featureBits[ARM::ModeThumb] && !featureBits[ARM::HasV8Ops]) {
5347 if (Rt == 13 || Rt == 15)
5353 if (featureBits[ARM::ModeThumb]) {
5357 unsigned pred = fieldFromInstruction(Val, 28, 4);
static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
static MCDisassembler * createARMDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
static const uint16_t GPRPairDecoderTable[]
static DecodeStatus DecodeNEONModImmInstruction(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
GCNRegPressure max(const GCNRegPressure &P1, const GCNRegPressure &P2)
static MCDisassembler * createThumbDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
This class represents lattice values for constants.
static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
DecodeStatus
Ternary decode status.
static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
Superclass for all disassemblers.
static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
bool tryAddingSymbolicOperand(MCInst &Inst, int64_t Value, uint64_t Address, bool IsBranch, uint64_t Offset, uint64_t InstSize) const
static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
Describe properties that are true of each instruction in the target description file.
static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static const uint16_t GPRDecoderTable[]
static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static void RegisterMCDisassembler(Target &T, Target::MCDisassemblerCtorTy Fn)
RegisterMCDisassembler - Register a MCDisassembler implementation for the given target.
static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Target & getTheThumbLETarget()
static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
amode Optimize addressing mode
static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
static MCOperand createReg(unsigned Reg)
static DecodeStatus DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
const FeatureBitset & getFeatureBits() const
static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static bool Check(DecodeStatus &Out, DecodeStatus In)
static const uint16_t DPairSpacedDecoderTable[]
const MCInstrDesc ARMInsts[]
static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
Target & getTheARMBETarget()
static DecodeStatus DecodeHPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
unsigned getReg() const
Returns the register number.
Context object for machine code objects.
static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
int decodeInstruction(InternalInstruction *insn, byteReader_t reader, const void *readerArg, dlog_t logger, void *loggerArg, const void *miiArg, uint64_t startLoc, DisassemblerMode mode)
Decode one instruction and store the decoding results in a buffer provided by the consumer...
Target & getTheThumbBETarget()
static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
static const uint16_t SPRDecoderTable[]
static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
iterator insert(iterator I, const MCOperand &Op)
static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
Instances of this class represent a single low-level machine instruction.
static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
unsigned short NumOperands
static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
void tryAddingPcLoadReferenceComment(int64_t Value, uint64_t Address) const
static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static const uint16_t DPRDecoderTable[]
static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
unsigned getAM5Opc(AddrOpc Opc, unsigned char Offset)
getAM5Opc - This function encodes the addrmode5 opc field.
static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Container class for subtarget features.
static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
static const uint16_t DPairDecoderTable[]
static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
size_t size() const
size - Get the array size.
static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static const uint16_t QPRDecoderTable[]
static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus checkDecodedInstruction(MCInst &MI, uint64_t &Size, uint64_t Address, raw_ostream &OS, raw_ostream &CS, uint32_t Insn, DecodeStatus Result)
static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeHINTInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
SmallVectorImpl< MCOperand >::iterator iterator
static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
void setOpcode(unsigned Op)
auto size(R &&Range, typename std::enable_if< std::is_same< typename std::iterator_traits< decltype(Range.begin())>::iterator_category, std::random_access_iterator_tag >::value, void >::type *=nullptr) -> decltype(std::distance(Range.begin(), Range.end()))
Get the size of a range.
static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
unsigned getAM5FP16Opc(AddrOpc Opc, unsigned char Offset)
getAM5FP16Opc - This function encodes the addrmode5fp16 opc field.
static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
unsigned getAM2Opc(AddrOpc Opc, unsigned Imm12, ShiftOpc SO, unsigned IdxMode=0)
static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
const MCOperand & getOperand(unsigned i) const
static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
Promote Memory to Register
static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst &Inst, unsigned Insn, uint64_t Adddress, const void *Decoder)
static DecodeStatus DecodeForVMRSandVMSR(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static void AddThumb1SBit(MCInst &MI, bool InITBlock)
void LLVMInitializeARMDisassembler()
static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
Target - Wrapper for Target specific information.
static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeNEONComplexLane64Instruction(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
int16_t RegClass
This specifies the register class enumeration of the operand if the operand is a register.
static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
Generic base class for all target subtargets.
static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static bool isBranch(unsigned Opcode)
static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Val, uint64_t Address, const void *Decoder)
LLVM Value Representation.
static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
const MCOperandInfo * OpInfo
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
const MCSubtargetInfo & getSubtargetInfo() const
static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
This class implements an extremely fast bulk output stream that can only output to a stream...
static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
void addOperand(const MCOperand &Op)
static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value, const void *Decoder)
tryAddingPcLoadReferenceComment - trys to add a comment as to what is being referenced by a load inst...
static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
Target & getTheARMLETarget()
This holds information about one operand of a machine instruction, indicating the register class for ...
unsigned getOpcode() const
static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
static MCOperand createImm(int64_t Val)
static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value, bool isBranch, uint64_t InstSize, MCInst &MI, const void *Decoder)
tryAddingSymbolicOperand - trys to add a symbolic operand in place of the immediate Value in the MCIn...
static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
