LLVM  8.0.1
HexagonAsmParser.cpp
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1 //===-- HexagonAsmParser.cpp - Parse Hexagon asm to MCInst instructions----===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
10 #define DEBUG_TYPE "mcasmparser"
11 
12 #include "Hexagon.h"
13 #include "HexagonTargetStreamer.h"
14 #include "MCTargetDesc/HexagonMCChecker.h"
15 #include "MCTargetDesc/HexagonMCELFStreamer.h"
16 #include "MCTargetDesc/HexagonMCExpr.h"
17 #include "MCTargetDesc/HexagonMCInstrInfo.h"
18 #include "MCTargetDesc/HexagonMCTargetDesc.h"
19 #include "MCTargetDesc/HexagonShuffler.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/ADT/SmallVector.h"
22 #include "llvm/ADT/StringExtras.h"
23 #include "llvm/ADT/StringRef.h"
24 #include "llvm/ADT/Twine.h"
25 #include "llvm/BinaryFormat/ELF.h"
26 #include "llvm/MC/MCAssembler.h"
27 #include "llvm/MC/MCContext.h"
28 #include "llvm/MC/MCDirectives.h"
29 #include "llvm/MC/MCELFStreamer.h"
30 #include "llvm/MC/MCExpr.h"
31 #include "llvm/MC/MCInst.h"
32 #include "llvm/MC/MCParser/MCAsmLexer.h"
33 #include "llvm/MC/MCParser/MCAsmParser.h"
34 #include "llvm/MC/MCParser/MCAsmParserExtension.h"
35 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
36 #include "llvm/MC/MCParser/MCTargetAsmParser.h"
37 #include "llvm/MC/MCRegisterInfo.h"
38 #include "llvm/MC/MCSectionELF.h"
39 #include "llvm/MC/MCStreamer.h"
40 #include "llvm/MC/MCSubtargetInfo.h"
41 #include "llvm/MC/MCSymbol.h"
42 #include "llvm/MC/MCValue.h"
43 #include "llvm/Support/Casting.h"
44 #include "llvm/Support/CommandLine.h"
45 #include "llvm/Support/Debug.h"
46 #include "llvm/Support/ErrorHandling.h"
47 #include "llvm/Support/Format.h"
48 #include "llvm/Support/MathExtras.h"
49 #include "llvm/Support/SMLoc.h"
50 #include "llvm/Support/SourceMgr.h"
51 #include "llvm/Support/TargetRegistry.h"
52 #include "llvm/Support/raw_ostream.h"
53 #include <algorithm>
54 #include <cassert>
55 #include <cctype>
56 #include <cstddef>
57 #include <cstdint>
58 #include <memory>
59 #include <string>
60 #include <utility>
61 
62 using namespace llvm;
63 
64 static cl::opt<bool> WarnMissingParenthesis(
65  "mwarn-missing-parenthesis",
66  cl::desc("Warn for missing parenthesis around predicate registers"),
67  cl::init(true));
68 static cl::opt<bool> ErrorMissingParenthesis(
69  "merror-missing-parenthesis",
70  cl::desc("Error for missing parenthesis around predicate registers"),
71  cl::init(false));
72 static cl::opt<bool> WarnSignedMismatch(
73  "mwarn-sign-mismatch",
74  cl::desc("Warn for mismatching a signed and unsigned value"),
75  cl::init(true));
76 static cl::opt<bool> WarnNoncontigiousRegister(
77  "mwarn-noncontigious-register",
78  cl::desc("Warn for register names that arent contigious"), cl::init(true));
79 static cl::opt<bool> ErrorNoncontigiousRegister(
80  "merror-noncontigious-register",
81  cl::desc("Error for register names that aren't contigious"),
82  cl::init(false));
83 
84 namespace {
85 
86 struct HexagonOperand;
87 
88 class HexagonAsmParser : public MCTargetAsmParser {
89 
90  HexagonTargetStreamer &getTargetStreamer() {
91  MCTargetStreamer &TS = *Parser.getStreamer().getTargetStreamer();
92  return static_cast<HexagonTargetStreamer &>(TS);
93  }
94 
95  MCAsmParser &Parser;
96  MCInst MCB;
97  bool InBrackets;
98 
99  MCAsmParser &getParser() const { return Parser; }
100  MCAssembler *getAssembler() const {
101  MCAssembler *Assembler = nullptr;
102  // FIXME: need better way to detect AsmStreamer (upstream removed getKind())
103  if (!Parser.getStreamer().hasRawTextSupport()) {
104  MCELFStreamer *MES = static_cast<MCELFStreamer *>(&Parser.getStreamer());
105  Assembler = &MES->getAssembler();
106  }
107  return Assembler;
108  }
109 
110  MCAsmLexer &getLexer() const { return Parser.getLexer(); }
111 
112  bool equalIsAsmAssignment() override { return false; }
113  bool isLabel(AsmToken &Token) override;
114 
115  void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); }
116  bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }
117  bool ParseDirectiveFalign(unsigned Size, SMLoc L);
118 
119  bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
120  bool ParseDirectiveSubsection(SMLoc L);
121  bool ParseDirectiveComm(bool IsLocal, SMLoc L);
122  bool RegisterMatchesArch(unsigned MatchNum) const;
123 
124  bool matchBundleOptions();
125  bool handleNoncontigiousRegister(bool Contigious, SMLoc &Loc);
126  bool finishBundle(SMLoc IDLoc, MCStreamer &Out);
127  void canonicalizeImmediates(MCInst &MCI);
128  bool matchOneInstruction(MCInst &MCB, SMLoc IDLoc,
129  OperandVector &InstOperands, uint64_t &ErrorInfo,
130  bool MatchingInlineAsm);
131  void eatToEndOfPacket();
132  bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
133  OperandVector &Operands, MCStreamer &Out,
134  uint64_t &ErrorInfo,
135  bool MatchingInlineAsm) override;
136 
137  unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
138  unsigned Kind) override;
139  bool OutOfRange(SMLoc IDLoc, long long Val, long long Max);
140  int processInstruction(MCInst &Inst, OperandVector const &Operands,
141  SMLoc IDLoc);
142 
143  // Check if we have an assembler and, if so, set the ELF e_header flags.
144  void chksetELFHeaderEFlags(unsigned flags) {
145  if (getAssembler())
146  getAssembler()->setELFHeaderEFlags(flags);
147  }
148 
149  unsigned matchRegister(StringRef Name);
150 
151 /// @name Auto-generated Match Functions
152 /// {
153 
154 #define GET_ASSEMBLER_HEADER
155 #include "HexagonGenAsmMatcher.inc"
156 
157  /// }
158 
159 public:
160  HexagonAsmParser(const MCSubtargetInfo &_STI, MCAsmParser &_Parser,
161  const MCInstrInfo &MII, const MCTargetOptions &Options)
162  : MCTargetAsmParser(Options, _STI, MII), Parser(_Parser),
163  InBrackets(false) {
164  MCB.setOpcode(Hexagon::BUNDLE);
165  setAvailableFeatures(ComputeAvailableFeatures(getSTI().getFeatureBits()));
166 
167  Parser.addAliasForDirective(".half", ".2byte");
168  Parser.addAliasForDirective(".hword", ".2byte");
169  Parser.addAliasForDirective(".word", ".4byte");
170 
171  MCAsmParserExtension::Initialize(_Parser);
172  }
173 
174  bool splitIdentifier(OperandVector &Operands);
175  bool parseOperand(OperandVector &Operands);
176  bool parseInstruction(OperandVector &Operands);
177  bool implicitExpressionLocation(OperandVector &Operands);
178  bool parseExpressionOrOperand(OperandVector &Operands);
179  bool parseExpression(MCExpr const *&Expr);
180 
181  bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
182  SMLoc NameLoc, OperandVector &Operands) override {
183  llvm_unreachable("Unimplemented");
184  }
185 
186  bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name, AsmToken ID,
187  OperandVector &Operands) override;
188 
189  bool ParseDirective(AsmToken DirectiveID) override;
190 };
191 
192 /// HexagonOperand - Instances of this class represent a parsed Hexagon machine
193 /// instruction.
194 struct HexagonOperand : public MCParsedAsmOperand {
195  enum KindTy { Token, Immediate, Register } Kind;
196  MCContext &Context;
197 
198  SMLoc StartLoc, EndLoc;
199 
200  struct TokTy {
201  const char *Data;
202  unsigned Length;
203  };
204 
205  struct RegTy {
206  unsigned RegNum;
207  };
208 
209  struct ImmTy {
210  const MCExpr *Val;
211  };
212 
213  struct InstTy {
214  OperandVector *SubInsts;
215  };
216 
217  union {
218  struct TokTy Tok;
219  struct RegTy Reg;
220  struct ImmTy Imm;
221  };
222 
223  HexagonOperand(KindTy K, MCContext &Context)
224  : MCParsedAsmOperand(), Kind(K), Context(Context) {}
225 
226 public:
227  HexagonOperand(const HexagonOperand &o)
228  : MCParsedAsmOperand(), Context(o.Context) {
229  Kind = o.Kind;
230  StartLoc = o.StartLoc;
231  EndLoc = o.EndLoc;
232  switch (Kind) {
233  case Register:
234  Reg = o.Reg;
235  break;
236  case Immediate:
237  Imm = o.Imm;
238  break;
239  case Token:
240  Tok = o.Tok;
241  break;
242  }
243  }
244 
245  /// getStartLoc - Get the location of the first token of this operand.
246  SMLoc getStartLoc() const override { return StartLoc; }
247 
248  /// getEndLoc - Get the location of the last token of this operand.
249  SMLoc getEndLoc() const override { return EndLoc; }
250 
251  unsigned getReg() const override {
252  assert(Kind == Register && "Invalid access!");
253  return Reg.RegNum;
254  }
255 
256  const MCExpr *getImm() const {
257  assert(Kind == Immediate && "Invalid access!");
258  return Imm.Val;
259  }
260 
261  bool isToken() const override { return Kind == Token; }
262  bool isImm() const override { return Kind == Immediate; }
263  bool isMem() const override { llvm_unreachable("No isMem"); }
264  bool isReg() const override { return Kind == Register; }
265 
266  bool CheckImmRange(int immBits, int zeroBits, bool isSigned,
267  bool isRelocatable, bool Extendable) const {
268  if (Kind == Immediate) {
269  const MCExpr *myMCExpr = &HexagonMCInstrInfo::getExpr(*getImm());
270  if (HexagonMCInstrInfo::mustExtend(*Imm.Val) && !Extendable)
271  return false;
272  int64_t Res;
273  if (myMCExpr->evaluateAsAbsolute(Res)) {
274  int bits = immBits + zeroBits;
275  // Field bit range is zerobits + bits
276  // zeroBits must be 0
277  if (Res & ((1 << zeroBits) - 1))
278  return false;
279  if (isSigned) {
280  if (Res < (1LL << (bits - 1)) && Res >= -(1LL << (bits - 1)))
281  return true;
282  } else {
283  if (bits == 64)
284  return true;
285  if (Res >= 0)
286  return ((uint64_t)Res < (uint64_t)(1ULL << bits));
287  else {
288  const int64_t high_bit_set = 1ULL << 63;
289  const uint64_t mask = (high_bit_set >> (63 - bits));
290  return (((uint64_t)Res & mask) == mask);
291  }
292  }
293  } else if (myMCExpr->getKind() == MCExpr::SymbolRef && isRelocatable)
294  return true;
295  else if (myMCExpr->getKind() == MCExpr::Binary ||
296  myMCExpr->getKind() == MCExpr::Unary)
297  return true;
298  }
299  return false;
300  }
301 
302  bool isa30_2Imm() const { return CheckImmRange(30, 2, true, true, true); }
303  bool isb30_2Imm() const { return CheckImmRange(30, 2, true, true, true); }
304  bool isb15_2Imm() const { return CheckImmRange(15, 2, true, true, false); }
305  bool isb13_2Imm() const { return CheckImmRange(13, 2, true, true, false); }
306 
307  bool ism32_0Imm() const { return true; }
308 
309  bool isf32Imm() const { return false; }
310  bool isf64Imm() const { return false; }
311  bool iss32_0Imm() const { return true; }
312  bool iss31_1Imm() const { return true; }
313  bool iss30_2Imm() const { return true; }
314  bool iss29_3Imm() const { return true; }
315  bool iss27_2Imm() const { return CheckImmRange(27, 2, true, true, false); }
316  bool iss9_0Imm() const { return CheckImmRange(9, 0, true, false, false); }
317  bool iss8_0Imm() const { return CheckImmRange(8, 0, true, false, false); }
318  bool iss8_0Imm64() const { return CheckImmRange(8, 0, true, true, false); }
319  bool iss7_0Imm() const { return CheckImmRange(7, 0, true, false, false); }
320  bool iss6_0Imm() const { return CheckImmRange(6, 0, true, false, false); }
321  bool iss6_3Imm() const { return CheckImmRange(6, 3, true, false, false); }
322  bool iss4_0Imm() const { return CheckImmRange(4, 0, true, false, false); }
323  bool iss4_1Imm() const { return CheckImmRange(4, 1, true, false, false); }
324  bool iss4_2Imm() const { return CheckImmRange(4, 2, true, false, false); }
325  bool iss4_3Imm() const { return CheckImmRange(4, 3, true, false, false); }
326  bool iss3_0Imm() const { return CheckImmRange(3, 0, true, false, false); }
327 
328  bool isu64_0Imm() const { return CheckImmRange(64, 0, false, true, true); }
329  bool isu32_0Imm() const { return true; }
330  bool isu31_1Imm() const { return true; }
331  bool isu30_2Imm() const { return true; }
332  bool isu29_3Imm() const { return true; }
333  bool isu26_6Imm() const { return CheckImmRange(26, 6, false, true, false); }
334  bool isu16_0Imm() const { return CheckImmRange(16, 0, false, true, false); }
335  bool isu16_1Imm() const { return CheckImmRange(16, 1, false, true, false); }
336  bool isu16_2Imm() const { return CheckImmRange(16, 2, false, true, false); }
337  bool isu16_3Imm() const { return CheckImmRange(16, 3, false, true, false); }
338  bool isu11_3Imm() const { return CheckImmRange(11, 3, false, false, false); }
339  bool isu10_0Imm() const { return CheckImmRange(10, 0, false, false, false); }
340  bool isu9_0Imm() const { return CheckImmRange(9, 0, false, false, false); }
341  bool isu8_0Imm() const { return CheckImmRange(8, 0, false, false, false); }
342  bool isu7_0Imm() const { return CheckImmRange(7, 0, false, false, false); }
343  bool isu6_0Imm() const { return CheckImmRange(6, 0, false, false, false); }
344  bool isu6_1Imm() const { return CheckImmRange(6, 1, false, false, false); }
345  bool isu6_2Imm() const { return CheckImmRange(6, 2, false, false, false); }
346  bool isu6_3Imm() const { return CheckImmRange(6, 3, false, false, false); }
347  bool isu5_0Imm() const { return CheckImmRange(5, 0, false, false, false); }
348  bool isu5_2Imm() const { return CheckImmRange(5, 2, false, false, false); }
349  bool isu5_3Imm() const { return CheckImmRange(5, 3, false, false, false); }
350  bool isu4_0Imm() const { return CheckImmRange(4, 0, false, false, false); }
351  bool isu4_2Imm() const { return CheckImmRange(4, 2, false, false, false); }
352  bool isu3_0Imm() const { return CheckImmRange(3, 0, false, false, false); }
353  bool isu3_1Imm() const { return CheckImmRange(3, 1, false, false, false); }
354  bool isu2_0Imm() const { return CheckImmRange(2, 0, false, false, false); }
355  bool isu1_0Imm() const { return CheckImmRange(1, 0, false, false, false); }
356 
357  bool isn1Const() const {
358  if (!isImm())
359  return false;
360  int64_t Value;
361  if (!getImm()->evaluateAsAbsolute(Value))
362  return false;
363  return Value == -1;
364  }
365  bool iss11_0Imm() const {
366  return CheckImmRange(11 + 26, 0, true, true, true);
367  }
368  bool iss11_1Imm() const {
369  return CheckImmRange(11 + 26, 1, true, true, true);
370  }
371  bool iss11_2Imm() const {
372  return CheckImmRange(11 + 26, 2, true, true, true);
373  }
374  bool iss11_3Imm() const {
375  return CheckImmRange(11 + 26, 3, true, true, true);
376  }
377  bool isu32_0MustExt() const { return isImm(); }
378 
379  void addRegOperands(MCInst &Inst, unsigned N) const {
380  assert(N == 1 && "Invalid number of operands!");
381  Inst.addOperand(MCOperand::createReg(getReg()));
382  }
383 
384  void addImmOperands(MCInst &Inst, unsigned N) const {
385  assert(N == 1 && "Invalid number of operands!");
386  Inst.addOperand(MCOperand::createExpr(getImm()));
387  }
388 
389  void addSignedImmOperands(MCInst &Inst, unsigned N) const {
390  assert(N == 1 && "Invalid number of operands!");
391  HexagonMCExpr *Expr =
392  const_cast<HexagonMCExpr *>(cast<HexagonMCExpr>(getImm()));
393  int64_t Value;
394  if (!Expr->evaluateAsAbsolute(Value)) {
395  Inst.addOperand(MCOperand::createExpr(Expr));
396  return;
397  }
398  int64_t Extended = SignExtend64(Value, 32);
399  HexagonMCExpr *NewExpr = HexagonMCExpr::create(
400  MCConstantExpr::create(Extended, Context), Context);
401  if ((Extended < 0) != (Value < 0))
402  NewExpr->setSignMismatch();
403  NewExpr->setMustExtend(Expr->mustExtend());
404  NewExpr->setMustNotExtend(Expr->mustNotExtend());
405  Inst.addOperand(MCOperand::createExpr(NewExpr));
406  }
407 
408  void addn1ConstOperands(MCInst &Inst, unsigned N) const {
409  addImmOperands(Inst, N);
410  }
411 
412  StringRef getToken() const {
413  assert(Kind == Token && "Invalid access!");
414  return StringRef(Tok.Data, Tok.Length);
415  }
416 
417  void print(raw_ostream &OS) const override;
418 
419  static std::unique_ptr<HexagonOperand> CreateToken(MCContext &Context,
420  StringRef Str, SMLoc S) {
421  HexagonOperand *Op = new HexagonOperand(Token, Context);
422  Op->Tok.Data = Str.data();
423  Op->Tok.Length = Str.size();
424  Op->StartLoc = S;
425  Op->EndLoc = S;
426  return std::unique_ptr<HexagonOperand>(Op);
427  }
428 
429  static std::unique_ptr<HexagonOperand>
430  CreateReg(MCContext &Context, unsigned RegNum, SMLoc S, SMLoc E) {
431  HexagonOperand *Op = new HexagonOperand(Register, Context);
432  Op->Reg.RegNum = RegNum;
433  Op->StartLoc = S;
434  Op->EndLoc = E;
435  return std::unique_ptr<HexagonOperand>(Op);
436  }
437 
438  static std::unique_ptr<HexagonOperand>
439  CreateImm(MCContext &Context, const MCExpr *Val, SMLoc S, SMLoc E) {
440  HexagonOperand *Op = new HexagonOperand(Immediate, Context);
441  Op->Imm.Val = Val;
442  Op->StartLoc = S;
443  Op->EndLoc = E;
444  return std::unique_ptr<HexagonOperand>(Op);
445  }
446 };
447 
448 } // end anonymous namespace
449 
450 void HexagonOperand::print(raw_ostream &OS) const {
451  switch (Kind) {
452  case Immediate:
453  getImm()->print(OS, nullptr);
454  break;
455  case Register:
456  OS << "<register R";
457  OS << getReg() << ">";
458  break;
459  case Token:
460  OS << "'" << getToken() << "'";
461  break;
462  }
463 }
464 
465 bool HexagonAsmParser::finishBundle(SMLoc IDLoc, MCStreamer &Out) {
466  LLVM_DEBUG(dbgs() << "Bundle:");
467  LLVM_DEBUG(MCB.dump_pretty(dbgs()));
468  LLVM_DEBUG(dbgs() << "--\n");
469 
470  MCB.setLoc(IDLoc);
471  // Check the bundle for errors.
472  const MCRegisterInfo *RI = getContext().getRegisterInfo();
473  HexagonMCChecker Check(getContext(), MII, getSTI(), MCB, *RI);
474 
475  bool CheckOk = HexagonMCInstrInfo::canonicalizePacket(MII, getSTI(),
476  getContext(), MCB,
477  &Check);
478 
479  if (CheckOk) {
480  if (HexagonMCInstrInfo::bundleSize(MCB) == 0) {
481  assert(!HexagonMCInstrInfo::isInnerLoop(MCB));
482  assert(!HexagonMCInstrInfo::isOuterLoop(MCB));
483  // Empty packets are valid yet aren't emitted
484  return false;
485  }
486  Out.EmitInstruction(MCB, getSTI());
487  } else {
488  // If compounding and duplexing didn't reduce the size below
489  // 4 or less we have a packet that is too big.
490  if (HexagonMCInstrInfo::bundleSize(MCB) > HEXAGON_PACKET_SIZE) {
491  Error(IDLoc, "invalid instruction packet: out of slots");
492  }
493  return true; // Error
494  }
495 
496  return false; // No error
497 }
498 
499 bool HexagonAsmParser::matchBundleOptions() {
500  MCAsmParser &Parser = getParser();
501  while (true) {
502  if (!Parser.getTok().is(AsmToken::Colon))
503  return false;
504  Lex();
505  char const *MemNoShuffMsg =
506  "invalid instruction packet: mem_noshuf specifier not "
507  "supported with this architecture";
508  StringRef Option = Parser.getTok().getString();
509  auto IDLoc = Parser.getTok().getLoc();
510  if (Option.compare_lower("endloop01") == 0) {
511  HexagonMCInstrInfo::setInnerLoop(MCB);
512  HexagonMCInstrInfo::setOuterLoop(MCB);
513  } else if (Option.compare_lower("endloop0") == 0) {
514  HexagonMCInstrInfo::setInnerLoop(MCB);
515  } else if (Option.compare_lower("endloop1") == 0) {
516  HexagonMCInstrInfo::setOuterLoop(MCB);
517  } else if (Option.compare_lower("mem_noshuf") == 0) {
518  if (getSTI().getFeatureBits()[Hexagon::FeatureMemNoShuf])
519  HexagonMCInstrInfo::setMemReorderDisabled(MCB);
520  else
521  return getParser().Error(IDLoc, MemNoShuffMsg);
522  } else
523  return getParser().Error(IDLoc, llvm::Twine("'") + Option +
524  "' is not a valid bundle option");
525  Lex();
526  }
527 }
528 
529 // For instruction aliases, immediates are generated rather than
530 // MCConstantExpr. Convert them for uniform MCExpr.
531 // Also check for signed/unsigned mismatches and warn
532 void HexagonAsmParser::canonicalizeImmediates(MCInst &MCI) {
533  MCInst NewInst;
534  NewInst.setOpcode(MCI.getOpcode());
535  for (MCOperand &I : MCI)
536  if (I.isImm()) {
537  int64_t Value(I.getImm());
538  NewInst.addOperand(MCOperand::createExpr(HexagonMCExpr::create(
539  MCConstantExpr::create(Value, getContext()), getContext())));
540  } else {
541  if (I.isExpr() && cast<HexagonMCExpr>(I.getExpr())->signMismatch() &&
542  WarnSignedMismatch)
543  Warning(MCI.getLoc(), "Signed/Unsigned mismatch");
544  NewInst.addOperand(I);
545  }
546  MCI = NewInst;
547 }
548 
549 bool HexagonAsmParser::matchOneInstruction(MCInst &MCI, SMLoc IDLoc,
550  OperandVector &InstOperands,
551  uint64_t &ErrorInfo,
552  bool MatchingInlineAsm) {
553  // Perform matching with tablegen asmmatcher generated function
554  int result =
555  MatchInstructionImpl(InstOperands, MCI, ErrorInfo, MatchingInlineAsm);
556  if (result == Match_Success) {
557  MCI.setLoc(IDLoc);
558  canonicalizeImmediates(MCI);
559  result = processInstruction(MCI, InstOperands, IDLoc);
560 
561  LLVM_DEBUG(dbgs() << "Insn:");
562  LLVM_DEBUG(MCI.dump_pretty(dbgs()));
563  LLVM_DEBUG(dbgs() << "\n\n");
564 
565  MCI.setLoc(IDLoc);
566  }
567 
568  // Create instruction operand for bundle instruction
569  // Break this into a separate function Code here is less readable
570  // Think about how to get an instruction error to report correctly.
571  // SMLoc will return the "{"
572  switch (result) {
573  default:
574  break;
575  case Match_Success:
576  return false;
577  case Match_MissingFeature:
578  return Error(IDLoc, "invalid instruction");
579  case Match_MnemonicFail:
580  return Error(IDLoc, "unrecognized instruction");
581  case Match_InvalidOperand:
582  case Match_InvalidTiedOperand:
583  SMLoc ErrorLoc = IDLoc;
584  if (ErrorInfo != ~0U) {
585  if (ErrorInfo >= InstOperands.size())
586  return Error(IDLoc, "too few operands for instruction");
587 
588  ErrorLoc = (static_cast<HexagonOperand *>(InstOperands[ErrorInfo].get()))
589  ->getStartLoc();
590  if (ErrorLoc == SMLoc())
591  ErrorLoc = IDLoc;
592  }
593  return Error(ErrorLoc, "invalid operand for instruction");
594  }
595  llvm_unreachable("Implement any new match types added!");
596 }
597 
598 void HexagonAsmParser::eatToEndOfPacket() {
599  assert(InBrackets);
600  MCAsmLexer &Lexer = getLexer();
601  while (!Lexer.is(AsmToken::RCurly))
602  Lexer.Lex();
603  Lexer.Lex();
604  InBrackets = false;
605 }
606 
607 bool HexagonAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
608  OperandVector &Operands,
609  MCStreamer &Out,
610  uint64_t &ErrorInfo,
611  bool MatchingInlineAsm) {
612  if (!InBrackets) {
613  MCB.clear();
614  MCB.addOperand(MCOperand::createImm(0));
615  }
616  HexagonOperand &FirstOperand = static_cast<HexagonOperand &>(*Operands[0]);
617  if (FirstOperand.isToken() && FirstOperand.getToken() == "{") {
618  assert(Operands.size() == 1 && "Brackets should be by themselves");
619  if (InBrackets) {
620  getParser().Error(IDLoc, "Already in a packet");
621  InBrackets = false;
622  return true;
623  }
624  InBrackets = true;
625  return false;
626  }
627  if (FirstOperand.isToken() && FirstOperand.getToken() == "}") {
628  assert(Operands.size() == 1 && "Brackets should be by themselves");
629  if (!InBrackets) {
630  getParser().Error(IDLoc, "Not in a packet");
631  return true;
632  }
633  InBrackets = false;
634  if (matchBundleOptions())
635  return true;
636  return finishBundle(IDLoc, Out);
637  }
638  MCInst *SubInst = new (getParser().getContext()) MCInst;
639  if (matchOneInstruction(*SubInst, IDLoc, Operands, ErrorInfo,
640  MatchingInlineAsm)) {
641  if (InBrackets)
642  eatToEndOfPacket();
643  return true;
644  }
645  HexagonMCInstrInfo::extendIfNeeded(
646  getParser().getContext(), MII, MCB, *SubInst);
647  MCB.addOperand(MCOperand::createInst(SubInst));
648  if (!InBrackets)
649  return finishBundle(IDLoc, Out);
650  return false;
651 }
652 
653 /// ParseDirective parses the Hexagon specific directives
654 bool HexagonAsmParser::ParseDirective(AsmToken DirectiveID) {
655  StringRef IDVal = DirectiveID.getIdentifier();
656  if (IDVal.lower() == ".falign")
657  return ParseDirectiveFalign(256, DirectiveID.getLoc());
658  if ((IDVal.lower() == ".lcomm") || (IDVal.lower() == ".lcommon"))
659  return ParseDirectiveComm(true, DirectiveID.getLoc());
660  if ((IDVal.lower() == ".comm") || (IDVal.lower() == ".common"))
661  return ParseDirectiveComm(false, DirectiveID.getLoc());
662  if (IDVal.lower() == ".subsection")
663  return ParseDirectiveSubsection(DirectiveID.getLoc());
664 
665  return true;
666 }
667 bool HexagonAsmParser::ParseDirectiveSubsection(SMLoc L) {
668  const MCExpr *Subsection = nullptr;
669  int64_t Res;
670 
671  assert((getLexer().isNot(AsmToken::EndOfStatement)) &&
672  "Invalid subsection directive");
673  getParser().parseExpression(Subsection);
674 
675  if (!Subsection->evaluateAsAbsolute(Res))
676  return Error(L, "Cannot evaluate subsection number");
677 
678  if (getLexer().isNot(AsmToken::EndOfStatement))
679  return TokError("unexpected token in directive");
680 
681  // 0-8192 is the hard-coded range in MCObjectStreamper.cpp, this keeps the
682  // negative subsections together and in the same order but at the opposite
683  // end of the section. Only legacy hexagon-gcc created assembly code
684  // used negative subsections.
685  if ((Res < 0) && (Res > -8193))
686  Subsection = HexagonMCExpr::create(
687  MCConstantExpr::create(8192 + Res, getContext()), getContext());
688 
689  getStreamer().SubSection(Subsection);
690  return false;
691 }
692 
693 /// ::= .falign [expression]
694 bool HexagonAsmParser::ParseDirectiveFalign(unsigned Size, SMLoc L) {
695 
696  int64_t MaxBytesToFill = 15;
697 
698  // if there is an argument
699  if (getLexer().isNot(AsmToken::EndOfStatement)) {
700  const MCExpr *Value;
701  SMLoc ExprLoc = L;
702 
703  // Make sure we have a number (false is returned if expression is a number)
704  if (!getParser().parseExpression(Value)) {
705  // Make sure this is a number that is in range
706  const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(Value);
707  uint64_t IntValue = MCE->getValue();
708  if (!isUIntN(Size, IntValue) && !isIntN(Size, IntValue))
709  return Error(ExprLoc, "literal value out of range (256) for falign");
710  MaxBytesToFill = IntValue;
711  Lex();
712  } else {
713  return Error(ExprLoc, "not a valid expression for falign directive");
714  }
715  }
716 
717  getTargetStreamer().emitFAlign(16, MaxBytesToFill);
718  Lex();
719 
720  return false;
721 }
722 
723 // This is largely a copy of AsmParser's ParseDirectiveComm extended to
724 // accept a 3rd argument, AccessAlignment which indicates the smallest
725 // memory access made to the symbol, expressed in bytes. If no
726 // AccessAlignment is specified it defaults to the Alignment Value.
727 // Hexagon's .lcomm:
728 // .lcomm Symbol, Length, Alignment, AccessAlignment
729 bool HexagonAsmParser::ParseDirectiveComm(bool IsLocal, SMLoc Loc) {
730  // FIXME: need better way to detect if AsmStreamer (upstream removed
731  // getKind())
732  if (getStreamer().hasRawTextSupport())
733  return true; // Only object file output requires special treatment.
734 
735  StringRef Name;
736  if (getParser().parseIdentifier(Name))
737  return TokError("expected identifier in directive");
738  // Handle the identifier as the key symbol.
739  MCSymbol *Sym = getContext().getOrCreateSymbol(Name);
740 
741  if (getLexer().isNot(AsmToken::Comma))
742  return TokError("unexpected token in directive");
743  Lex();
744 
745  int64_t Size;
746  SMLoc SizeLoc = getLexer().getLoc();
747  if (getParser().parseAbsoluteExpression(Size))
748  return true;
749 
750  int64_t ByteAlignment = 1;
751  SMLoc ByteAlignmentLoc;
752  if (getLexer().is(AsmToken::Comma)) {
753  Lex();
754  ByteAlignmentLoc = getLexer().getLoc();
755  if (getParser().parseAbsoluteExpression(ByteAlignment))
756  return true;
757  if (!isPowerOf2_64(ByteAlignment))
758  return Error(ByteAlignmentLoc, "alignment must be a power of 2");
759  }
760 
761  int64_t AccessAlignment = 0;
762  if (getLexer().is(AsmToken::Comma)) {
763  // The optional access argument specifies the size of the smallest memory
764  // access to be made to the symbol, expressed in bytes.
765  SMLoc AccessAlignmentLoc;
766  Lex();
767  AccessAlignmentLoc = getLexer().getLoc();
768  if (getParser().parseAbsoluteExpression(AccessAlignment))
769  return true;
770 
771  if (!isPowerOf2_64(AccessAlignment))
772  return Error(AccessAlignmentLoc, "access alignment must be a power of 2");
773  }
774 
775  if (getLexer().isNot(AsmToken::EndOfStatement))
776  return TokError("unexpected token in '.comm' or '.lcomm' directive");
777 
778  Lex();
779 
780  // NOTE: a size of zero for a .comm should create a undefined symbol
781  // but a size of .lcomm creates a bss symbol of size zero.
782  if (Size < 0)
783  return Error(SizeLoc, "invalid '.comm' or '.lcomm' directive size, can't "
784  "be less than zero");
785 
786  // NOTE: The alignment in the directive is a power of 2 value, the assembler
787  // may internally end up wanting an alignment in bytes.
788  // FIXME: Diagnose overflow.
789  if (ByteAlignment < 0)
790  return Error(ByteAlignmentLoc, "invalid '.comm' or '.lcomm' directive "
791  "alignment, can't be less than zero");
792 
793  if (!Sym->isUndefined())
794  return Error(Loc, "invalid symbol redefinition");
795 
796  HexagonMCELFStreamer &HexagonELFStreamer =
797  static_cast<HexagonMCELFStreamer &>(getStreamer());
798  if (IsLocal) {
799  HexagonELFStreamer.HexagonMCEmitLocalCommonSymbol(Sym, Size, ByteAlignment,
800  AccessAlignment);
801  return false;
802  }
803 
804  HexagonELFStreamer.HexagonMCEmitCommonSymbol(Sym, Size, ByteAlignment,
805  AccessAlignment);
806  return false;
807 }
808 
809 // validate register against architecture
810 bool HexagonAsmParser::RegisterMatchesArch(unsigned MatchNum) const {
811  if (HexagonMCRegisterClasses[Hexagon::V62RegsRegClassID].contains(MatchNum))
812  if (!getSTI().getFeatureBits()[Hexagon::ArchV62])
813  return false;
814  return true;
815 }
816 
817 // extern "C" void LLVMInitializeHexagonAsmLexer();
818 
819 /// Force static initialization.
820 extern "C" void LLVMInitializeHexagonAsmParser() {
821  RegisterMCAsmParser<HexagonAsmParser> X(getTheHexagonTarget());
822 }
823 
824 #define GET_MATCHER_IMPLEMENTATION
825 #define GET_REGISTER_MATCHER
826 #include "HexagonGenAsmMatcher.inc"
827 
828 static bool previousEqual(OperandVector &Operands, size_t Index,
829  StringRef String) {
830  if (Index >= Operands.size())
831  return false;
832  MCParsedAsmOperand &Operand = *Operands[Operands.size() - Index - 1];
833  if (!Operand.isToken())
834  return false;
835  return static_cast<HexagonOperand &>(Operand).getToken().equals_lower(String);
836 }
837 
838 static bool previousIsLoop(OperandVector &Operands, size_t Index) {
839  return previousEqual(Operands, Index, "loop0") ||
840  previousEqual(Operands, Index, "loop1") ||
841  previousEqual(Operands, Index, "sp1loop0") ||
842  previousEqual(Operands, Index, "sp2loop0") ||
843  previousEqual(Operands, Index, "sp3loop0");
844 }
845 
846 bool HexagonAsmParser::splitIdentifier(OperandVector &Operands) {
847  AsmToken const &Token = getParser().getTok();
848  StringRef String = Token.getString();
849  SMLoc Loc = Token.getLoc();
850  Lex();
851  do {
852  std::pair<StringRef, StringRef> HeadTail = String.split('.');
853  if (!HeadTail.first.empty())
854  Operands.push_back(
855  HexagonOperand::CreateToken(getContext(), HeadTail.first, Loc));
856  if (!HeadTail.second.empty())
857  Operands.push_back(HexagonOperand::CreateToken(
858  getContext(), String.substr(HeadTail.first.size(), 1), Loc));
859  String = HeadTail.second;
860  } while (!String.empty());
861  return false;
862 }
863 
864 bool HexagonAsmParser::parseOperand(OperandVector &Operands) {
865  unsigned Register;
866  SMLoc Begin;
867  SMLoc End;
868  MCAsmLexer &Lexer = getLexer();
869  if (!ParseRegister(Register, Begin, End)) {
870  if (!ErrorMissingParenthesis)
871  switch (Register) {
872  default:
873  break;
874  case Hexagon::P0:
875  case Hexagon::P1:
876  case Hexagon::P2:
877  case Hexagon::P3:
878  if (previousEqual(Operands, 0, "if")) {
879  if (WarnMissingParenthesis)
880  Warning(Begin, "Missing parenthesis around predicate register");
881  static char const *LParen = "(";
882  static char const *RParen = ")";
883  Operands.push_back(
884  HexagonOperand::CreateToken(getContext(), LParen, Begin));
885  Operands.push_back(
886  HexagonOperand::CreateReg(getContext(), Register, Begin, End));
887  const AsmToken &MaybeDotNew = Lexer.getTok();
888  if (MaybeDotNew.is(AsmToken::TokenKind::Identifier) &&
889  MaybeDotNew.getString().equals_lower(".new"))
890  splitIdentifier(Operands);
891  Operands.push_back(
892  HexagonOperand::CreateToken(getContext(), RParen, Begin));
893  return false;
894  }
895  if (previousEqual(Operands, 0, "!") &&
896  previousEqual(Operands, 1, "if")) {
897  if (WarnMissingParenthesis)
898  Warning(Begin, "Missing parenthesis around predicate register");
899  static char const *LParen = "(";
900  static char const *RParen = ")";
901  Operands.insert(Operands.end() - 1, HexagonOperand::CreateToken(
902  getContext(), LParen, Begin));
903  Operands.push_back(
904  HexagonOperand::CreateReg(getContext(), Register, Begin, End));
905  const AsmToken &MaybeDotNew = Lexer.getTok();
906  if (MaybeDotNew.is(AsmToken::TokenKind::Identifier) &&
907  MaybeDotNew.getString().equals_lower(".new"))
908  splitIdentifier(Operands);
909  Operands.push_back(
910  HexagonOperand::CreateToken(getContext(), RParen, Begin));
911  return false;
912  }
913  break;
914  }
915  Operands.push_back(
916  HexagonOperand::CreateReg(getContext(), Register, Begin, End));
917  return false;
918  }
919  return splitIdentifier(Operands);
920 }
921 
922 bool HexagonAsmParser::isLabel(AsmToken &Token) {
923  MCAsmLexer &Lexer = getLexer();
924  AsmToken const &Second = Lexer.getTok();
925  AsmToken Third = Lexer.peekTok();
926  StringRef String = Token.getString();
927  if (Token.is(AsmToken::TokenKind::LCurly) ||
928  Token.is(AsmToken::TokenKind::RCurly))
929  return false;
930  // special case for parsing vwhist256:sat
931  if (String.lower() == "vwhist256" && Second.is(AsmToken::Colon) &&
932  Third.getString().lower() == "sat")
933  return false;
934  if (!Token.is(AsmToken::TokenKind::Identifier))
935  return true;
936  if (!matchRegister(String.lower()))
937  return true;
938  assert(Second.is(AsmToken::Colon));
939  StringRef Raw(String.data(), Third.getString().data() - String.data() +
940  Third.getString().size());
941  std::string Collapsed = Raw;
942  Collapsed.erase(llvm::remove_if(Collapsed, isspace), Collapsed.end());
943  StringRef Whole = Collapsed;
944  std::pair<StringRef, StringRef> DotSplit = Whole.split('.');
945  if (!matchRegister(DotSplit.first.lower()))
946  return true;
947  return false;
948 }
949 
950 bool HexagonAsmParser::handleNoncontigiousRegister(bool Contigious,
951  SMLoc &Loc) {
952  if (!Contigious && ErrorNoncontigiousRegister) {
953  Error(Loc, "Register name is not contigious");
954  return true;
955  }
956  if (!Contigious && WarnNoncontigiousRegister)
957  Warning(Loc, "Register name is not contigious");
958  return false;
959 }
960 
961 bool HexagonAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
962  SMLoc &EndLoc) {
963  MCAsmLexer &Lexer = getLexer();
964  StartLoc = getLexer().getLoc();
965  SmallVector<AsmToken, 5> Lookahead;
966  StringRef RawString(Lexer.getTok().getString().data(), 0);
967  bool Again = Lexer.is(AsmToken::Identifier);
968  bool NeededWorkaround = false;
969  while (Again) {
970  AsmToken const &Token = Lexer.getTok();
971  RawString = StringRef(RawString.data(), Token.getString().data() -
972  RawString.data() +
973  Token.getString().size());
974  Lookahead.push_back(Token);
975  Lexer.Lex();
976  bool Contigious = Lexer.getTok().getString().data() ==
977  Lookahead.back().getString().data() +
978  Lookahead.back().getString().size();
979  bool Type = Lexer.is(AsmToken::Identifier) || Lexer.is(AsmToken::Dot) ||
980  Lexer.is(AsmToken::Integer) || Lexer.is(AsmToken::Real) ||
981  Lexer.is(AsmToken::Colon);
982  bool Workaround =
983  Lexer.is(AsmToken::Colon) || Lookahead.back().is(AsmToken::Colon);
984  Again = (Contigious && Type) || (Workaround && Type);
985  NeededWorkaround = NeededWorkaround || (Again && !(Contigious && Type));
986  }
987  std::string Collapsed = RawString;
988  Collapsed.erase(llvm::remove_if(Collapsed, isspace), Collapsed.end());
989  StringRef FullString = Collapsed;
990  std::pair<StringRef, StringRef> DotSplit = FullString.split('.');
991  unsigned DotReg = matchRegister(DotSplit.first.lower());
992  if (DotReg != Hexagon::NoRegister && RegisterMatchesArch(DotReg)) {
993  if (DotSplit.second.empty()) {
994  RegNo = DotReg;
995  EndLoc = Lexer.getLoc();
996  if (handleNoncontigiousRegister(!NeededWorkaround, StartLoc))
997  return true;
998  return false;
999  } else {
1000  RegNo = DotReg;
1001  size_t First = RawString.find('.');
1002  StringRef DotString (RawString.data() + First, RawString.size() - First);
1003  Lexer.UnLex(AsmToken(AsmToken::Identifier, DotString));
1004  EndLoc = Lexer.getLoc();
1005  if (handleNoncontigiousRegister(!NeededWorkaround, StartLoc))
1006  return true;
1007  return false;
1008  }
1009  }
1010  std::pair<StringRef, StringRef> ColonSplit = StringRef(FullString).split(':');
1011  unsigned ColonReg = matchRegister(ColonSplit.first.lower());
1012  if (ColonReg != Hexagon::NoRegister && RegisterMatchesArch(DotReg)) {
1013  do {
1014  Lexer.UnLex(Lookahead.back());
1015  Lookahead.pop_back();
1016  } while (!Lookahead.empty () && !Lexer.is(AsmToken::Colon));
1017  RegNo = ColonReg;
1018  EndLoc = Lexer.getLoc();
1019  if (handleNoncontigiousRegister(!NeededWorkaround, StartLoc))
1020  return true;
1021  return false;
1022  }
1023  while (!Lookahead.empty()) {
1024  Lexer.UnLex(Lookahead.back());
1025  Lookahead.pop_back();
1026  }
1027  return true;
1028 }
1029 
1030 bool HexagonAsmParser::implicitExpressionLocation(OperandVector &Operands) {
1031  if (previousEqual(Operands, 0, "call"))
1032  return true;
1033  if (previousEqual(Operands, 0, "jump"))
1034  if (!getLexer().getTok().is(AsmToken::Colon))
1035  return true;
1036  if (previousEqual(Operands, 0, "(") && previousIsLoop(Operands, 1))
1037  return true;
1038  if (previousEqual(Operands, 1, ":") && previousEqual(Operands, 2, "jump") &&
1039  (previousEqual(Operands, 0, "nt") || previousEqual(Operands, 0, "t")))
1040  return true;
1041  return false;
1042 }
1043 
1044 bool HexagonAsmParser::parseExpression(MCExpr const *&Expr) {
1045  SmallVector<AsmToken, 4> Tokens;
1046  MCAsmLexer &Lexer = getLexer();
1047  bool Done = false;
1048  static char const *Comma = ",";
1049  do {
1050  Tokens.emplace_back(Lexer.getTok());
1051  Lex();
1052  switch (Tokens.back().getKind()) {
1053  case AsmToken::TokenKind::Hash:
1054  if (Tokens.size() > 1)
1055  if ((Tokens.end() - 2)->getKind() == AsmToken::TokenKind::Plus) {
1056  Tokens.insert(Tokens.end() - 2,
1057  AsmToken(AsmToken::TokenKind::Comma, Comma));
1058  Done = true;
1059  }
1060  break;
1061  case AsmToken::TokenKind::RCurly:
1062  case AsmToken::TokenKind::EndOfStatement:
1063  case AsmToken::TokenKind::Eof:
1064  Done = true;
1065  break;
1066  default:
1067  break;
1068  }
1069  } while (!Done);
1070  while (!Tokens.empty()) {
1071  Lexer.UnLex(Tokens.back());
1072  Tokens.pop_back();
1073  }
1074  SMLoc Loc = Lexer.getLoc();
1075  return getParser().parseExpression(Expr, Loc);
1076 }
1077 
1078 bool HexagonAsmParser::parseExpressionOrOperand(OperandVector &Operands) {
1079  if (implicitExpressionLocation(Operands)) {
1080  MCAsmParser &Parser = getParser();
1081  SMLoc Loc = Parser.getLexer().getLoc();
1082  MCExpr const *Expr = nullptr;
1083  bool Error = parseExpression(Expr);
1084  Expr = HexagonMCExpr::create(Expr, getContext());
1085  if (!Error)
1086  Operands.push_back(
1087  HexagonOperand::CreateImm(getContext(), Expr, Loc, Loc));
1088  return Error;
1089  }
1090  return parseOperand(Operands);
1091 }
1092 
1093 /// Parse an instruction.
1094 bool HexagonAsmParser::parseInstruction(OperandVector &Operands) {
1095  MCAsmParser &Parser = getParser();
1096  MCAsmLexer &Lexer = getLexer();
1097  while (true) {
1098  AsmToken const &Token = Parser.getTok();
1099  switch (Token.getKind()) {
1100  case AsmToken::Eof:
1101  case AsmToken::EndOfStatement: {
1102  Lex();
1103  return false;
1104  }
1105  case AsmToken::LCurly: {
1106  if (!Operands.empty())
1107  return true;
1108  Operands.push_back(HexagonOperand::CreateToken(
1109  getContext(), Token.getString(), Token.getLoc()));
1110  Lex();
1111  return false;
1112  }
1113  case AsmToken::RCurly: {
1114  if (Operands.empty()) {
1115  Operands.push_back(HexagonOperand::CreateToken(
1116  getContext(), Token.getString(), Token.getLoc()));
1117  Lex();
1118  }
1119  return false;
1120  }
1121  case AsmToken::Comma: {
1122  Lex();
1123  continue;
1124  }
1125  case AsmToken::EqualEqual:
1126  case AsmToken::ExclaimEqual:
1127  case AsmToken::GreaterEqual:
1128  case AsmToken::GreaterGreater:
1129  case AsmToken::LessEqual:
1130  case AsmToken::LessLess: {
1131  Operands.push_back(HexagonOperand::CreateToken(
1132  getContext(), Token.getString().substr(0, 1), Token.getLoc()));
1133  Operands.push_back(HexagonOperand::CreateToken(
1134  getContext(), Token.getString().substr(1, 1), Token.getLoc()));
1135  Lex();
1136  continue;
1137  }
1138  case AsmToken::Hash: {
1139  bool MustNotExtend = false;
1140  bool ImplicitExpression = implicitExpressionLocation(Operands);
1141  SMLoc ExprLoc = Lexer.getLoc();
1142  if (!ImplicitExpression)
1143  Operands.push_back(HexagonOperand::CreateToken(
1144  getContext(), Token.getString(), Token.getLoc()));
1145  Lex();
1146  bool MustExtend = false;
1147  bool HiOnly = false;
1148  bool LoOnly = false;
1149  if (Lexer.is(AsmToken::Hash)) {
1150  Lex();
1151  MustExtend = true;
1152  } else if (ImplicitExpression)
1153  MustNotExtend = true;
1154  AsmToken const &Token = Parser.getTok();
1155  if (Token.is(AsmToken::Identifier)) {
1156  StringRef String = Token.getString();
1157  if (String.lower() == "hi") {
1158  HiOnly = true;
1159  } else if (String.lower() == "lo") {
1160  LoOnly = true;
1161  }
1162  if (HiOnly || LoOnly) {
1163  AsmToken LParen = Lexer.peekTok();
1164  if (!LParen.is(AsmToken::LParen)) {
1165  HiOnly = false;
1166  LoOnly = false;
1167  } else {
1168  Lex();
1169  }
1170  }
1171  }
1172  MCExpr const *Expr = nullptr;
1173  if (parseExpression(Expr))
1174  return true;
1175  int64_t Value;
1176  MCContext &Context = Parser.getContext();
1177  assert(Expr != nullptr);
1178  if (Expr->evaluateAsAbsolute(Value)) {
1179  if (HiOnly)
1180  Expr = MCBinaryExpr::createLShr(
1181  Expr, MCConstantExpr::create(16, Context), Context);
1182  if (HiOnly || LoOnly)
1183  Expr = MCBinaryExpr::createAnd(
1184  Expr, MCConstantExpr::create(0xffff, Context), Context);
1185  } else {
1186  MCValue Value;
1187  if (Expr->evaluateAsRelocatable(Value, nullptr, nullptr)) {
1188  if (!Value.isAbsolute()) {
1189  switch (Value.getAccessVariant()) {
1190  case MCSymbolRefExpr::VariantKind::VK_TPREL:
1191  case MCSymbolRefExpr::VariantKind::VK_DTPREL:
1192  // Don't lazy extend these expression variants
1193  MustNotExtend = !MustExtend;
1194  break;
1195  default:
1196  break;
1197  }
1198  }
1199  }
1200  }
1201  Expr = HexagonMCExpr::create(Expr, Context);
1202  HexagonMCInstrInfo::setMustNotExtend(*Expr, MustNotExtend);
1203  HexagonMCInstrInfo::setMustExtend(*Expr, MustExtend);
1204  std::unique_ptr<HexagonOperand> Operand =
1205  HexagonOperand::CreateImm(getContext(), Expr, ExprLoc, ExprLoc);
1206  Operands.push_back(std::move(Operand));
1207  continue;
1208  }
1209  default:
1210  break;
1211  }
1212  if (parseExpressionOrOperand(Operands))
1213  return true;
1214  }
1215 }
1216 
1217 bool HexagonAsmParser::ParseInstruction(ParseInstructionInfo &Info,
1218  StringRef Name, AsmToken ID,
1219  OperandVector &Operands) {
1220  getLexer().UnLex(ID);
1221  return parseInstruction(Operands);
1222 }
1223 
1224 static MCInst makeCombineInst(int opCode, MCOperand &Rdd, MCOperand &MO1,
1225  MCOperand &MO2) {
1226  MCInst TmpInst;
1227  TmpInst.setOpcode(opCode);
1228  TmpInst.addOperand(Rdd);
1229  TmpInst.addOperand(MO1);
1230  TmpInst.addOperand(MO2);
1231 
1232  return TmpInst;
1233 }
1234 
1235 // Define this matcher function after the auto-generated include so we
1236 // have the match class enum definitions.
1237 unsigned HexagonAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp,
1238  unsigned Kind) {
1239  HexagonOperand *Op = static_cast<HexagonOperand *>(&AsmOp);
1240 
1241  switch (Kind) {
1242  case MCK_0: {
1243  int64_t Value;
1244  return Op->isImm() && Op->Imm.Val->evaluateAsAbsolute(Value) && Value == 0
1245  ? Match_Success
1246  : Match_InvalidOperand;
1247  }
1248  case MCK_1: {
1249  int64_t Value;
1250  return Op->isImm() && Op->Imm.Val->evaluateAsAbsolute(Value) && Value == 1
1251  ? Match_Success
1252  : Match_InvalidOperand;
1253  }
1254  }
1255  if (Op->Kind == HexagonOperand::Token && Kind != InvalidMatchClass) {
1256  StringRef myStringRef = StringRef(Op->Tok.Data, Op->Tok.Length);
1257  if (matchTokenString(myStringRef.lower()) == (MatchClassKind)Kind)
1258  return Match_Success;
1259  if (matchTokenString(myStringRef.upper()) == (MatchClassKind)Kind)
1260  return Match_Success;
1261  }
1262 
1263  LLVM_DEBUG(dbgs() << "Unmatched Operand:");
1264  LLVM_DEBUG(Op->dump());
1265  LLVM_DEBUG(dbgs() << "\n");
1266 
1267  return Match_InvalidOperand;
1268 }
1269 
1270 // FIXME: Calls to OutOfRange shoudl propagate failure up to parseStatement.
1271 bool HexagonAsmParser::OutOfRange(SMLoc IDLoc, long long Val, long long Max) {
1272  std::string errStr;
1273  raw_string_ostream ES(errStr);
1274  ES << "value " << Val << "(" << format_hex(Val, 0) << ") out of range: ";
1275  if (Max >= 0)
1276  ES << "0-" << Max;
1277  else
1278  ES << Max << "-" << (-Max - 1);
1279  return Parser.printError(IDLoc, ES.str());
1280 }
1281 
1282 int HexagonAsmParser::processInstruction(MCInst &Inst,
1283  OperandVector const &Operands,
1284  SMLoc IDLoc) {
1285  MCContext &Context = getParser().getContext();
1286  const MCRegisterInfo *RI = getContext().getRegisterInfo();
1287  std::string r = "r";
1288  std::string v = "v";
1289  std::string Colon = ":";
1290 
1291  bool is32bit = false; // used to distinguish between CONST32 and CONST64
1292  switch (Inst.getOpcode()) {
1293  default:
1294  if (HexagonMCInstrInfo::getDesc(MII, Inst).isPseudo()) {
1295  SMDiagnostic Diag = getSourceManager().GetMessage(
1296  IDLoc, SourceMgr::DK_Error,
1297  "Found pseudo instruction with no expansion");
1298  Diag.print("", errs());
1299  report_fatal_error("Invalid pseudo instruction");
1300  }
1301  break;
1302 
1303  case Hexagon::J2_trap1:
1304  if (!getSTI().getFeatureBits()[Hexagon::ArchV65]) {
1305  MCOperand &Rx = Inst.getOperand(0);
1306  MCOperand &Ry = Inst.getOperand(1);
1307  if (Rx.getReg() != Hexagon::R0 || Ry.getReg() != Hexagon::R0) {
1308  Error(IDLoc, "trap1 can only have register r0 as operand");
1309  return Match_InvalidOperand;
1310  }
1311  }
1312  break;
1313 
1314  case Hexagon::A2_iconst: {
1315  Inst.setOpcode(Hexagon::A2_addi);
1316  MCOperand Reg = Inst.getOperand(0);
1317  MCOperand S27 = Inst.getOperand(1);
1318  HexagonMCInstrInfo::setMustNotExtend(*S27.getExpr());
1319  HexagonMCInstrInfo::setS27_2_reloc(*S27.getExpr());
1320  Inst.clear();
1321  Inst.addOperand(Reg);
1322  Inst.addOperand(MCOperand::createReg(Hexagon::R0));
1323  Inst.addOperand(S27);
1324  break;
1325  }
1326  case Hexagon::M4_mpyrr_addr:
1327  case Hexagon::S4_addi_asl_ri:
1328  case Hexagon::S4_addi_lsr_ri:
1329  case Hexagon::S4_andi_asl_ri:
1330  case Hexagon::S4_andi_lsr_ri:
1331  case Hexagon::S4_ori_asl_ri:
1332  case Hexagon::S4_ori_lsr_ri:
1333  case Hexagon::S4_or_andix:
1334  case Hexagon::S4_subi_asl_ri:
1335  case Hexagon::S4_subi_lsr_ri: {
1336  MCOperand &Ry = Inst.getOperand(0);
1337  MCOperand &src = Inst.getOperand(2);
1338  if (RI->getEncodingValue(Ry.getReg()) != RI->getEncodingValue(src.getReg()))
1339  return Match_InvalidOperand;
1340  break;
1341  }
1342 
1343  case Hexagon::C2_cmpgei: {
1344  MCOperand &MO = Inst.getOperand(2);
1345  MO.setExpr(HexagonMCExpr::create(
1346  MCBinaryExpr::createSub(MO.getExpr(),
1347  MCConstantExpr::create(1, Context), Context),
1348  Context));
1349  Inst.setOpcode(Hexagon::C2_cmpgti);
1350  break;
1351  }
1352 
1353  case Hexagon::C2_cmpgeui: {
1354  MCOperand &MO = Inst.getOperand(2);
1355  int64_t Value;
1356  bool Success = MO.getExpr()->evaluateAsAbsolute(Value);
1357  (void)Success;
1358  assert(Success && "Assured by matcher");
1359  if (Value == 0) {
1360  MCInst TmpInst;
1361  MCOperand &Pd = Inst.getOperand(0);
1362  MCOperand &Rt = Inst.getOperand(1);
1363  TmpInst.setOpcode(Hexagon::C2_cmpeq);
1364  TmpInst.addOperand(Pd);
1365  TmpInst.addOperand(Rt);
1366  TmpInst.addOperand(Rt);
1367  Inst = TmpInst;
1368  } else {
1369  MO.setExpr(HexagonMCExpr::create(
1370  MCBinaryExpr::createSub(MO.getExpr(),
1371  MCConstantExpr::create(1, Context), Context),
1372  Context));
1373  Inst.setOpcode(Hexagon::C2_cmpgtui);
1374  }
1375  break;
1376  }
1377 
1378  // Translate a "$Rdd = $Rss" to "$Rdd = combine($Rs, $Rt)"
1379  case Hexagon::A2_tfrp: {
1380  MCOperand &MO = Inst.getOperand(1);
1381  unsigned int RegPairNum = RI->getEncodingValue(MO.getReg());
1382  std::string R1 = r + utostr(RegPairNum + 1);
1383  StringRef Reg1(R1);
1384  MO.setReg(matchRegister(Reg1));
1385  // Add a new operand for the second register in the pair.
1386  std::string R2 = r + utostr(RegPairNum);
1387  StringRef Reg2(R2);
1388  Inst.addOperand(MCOperand::createReg(matchRegister(Reg2)));
1389  Inst.setOpcode(Hexagon::A2_combinew);
1390  break;
1391  }
1392 
1393  case Hexagon::A2_tfrpt:
1394  case Hexagon::A2_tfrpf: {
1395  MCOperand &MO = Inst.getOperand(2);
1396  unsigned int RegPairNum = RI->getEncodingValue(MO.getReg());
1397  std::string R1 = r + utostr(RegPairNum + 1);
1398  StringRef Reg1(R1);
1399  MO.setReg(matchRegister(Reg1));
1400  // Add a new operand for the second register in the pair.
1401  std::string R2 = r + utostr(RegPairNum);
1402  StringRef Reg2(R2);
1403  Inst.addOperand(MCOperand::createReg(matchRegister(Reg2)));
1404  Inst.setOpcode((Inst.getOpcode() == Hexagon::A2_tfrpt)
1405  ? Hexagon::C2_ccombinewt
1406  : Hexagon::C2_ccombinewf);
1407  break;
1408  }
1409  case Hexagon::A2_tfrptnew:
1410  case Hexagon::A2_tfrpfnew: {
1411  MCOperand &MO = Inst.getOperand(2);
1412  unsigned int RegPairNum = RI->getEncodingValue(MO.getReg());
1413  std::string R1 = r + utostr(RegPairNum + 1);
1414  StringRef Reg1(R1);
1415  MO.setReg(matchRegister(Reg1));
1416  // Add a new operand for the second register in the pair.
1417  std::string R2 = r + utostr(RegPairNum);
1418  StringRef Reg2(R2);
1419  Inst.addOperand(MCOperand::createReg(matchRegister(Reg2)));
1420  Inst.setOpcode((Inst.getOpcode() == Hexagon::A2_tfrptnew)
1421  ? Hexagon::C2_ccombinewnewt
1422  : Hexagon::C2_ccombinewnewf);
1423  break;
1424  }
1425 
1426  // Translate a "$Vdd = $Vss" to "$Vdd = vcombine($Vs, $Vt)"
1427  case Hexagon::V6_vassignp: {
1428  MCOperand &MO = Inst.getOperand(1);
1429  unsigned int RegPairNum = RI->getEncodingValue(MO.getReg());
1430  std::string R1 = v + utostr(RegPairNum + 1);
1431  MO.setReg(MatchRegisterName(R1));
1432  // Add a new operand for the second register in the pair.
1433  std::string R2 = v + utostr(RegPairNum);
1434  Inst.addOperand(MCOperand::createReg(MatchRegisterName(R2)));
1435  Inst.setOpcode(Hexagon::V6_vcombine);
1436  break;
1437  }
1438 
1439  // Translate a "$Rx = CONST32(#imm)" to "$Rx = memw(gp+#LABEL) "
1440  case Hexagon::CONST32:
1441  is32bit = true;
1442  LLVM_FALLTHROUGH;
1443  // Translate a "$Rx:y = CONST64(#imm)" to "$Rx:y = memd(gp+#LABEL) "
1444  case Hexagon::CONST64:
1445  // FIXME: need better way to detect AsmStreamer (upstream removed getKind())
1446  if (!Parser.getStreamer().hasRawTextSupport()) {
1447  MCELFStreamer *MES = static_cast<MCELFStreamer *>(&Parser.getStreamer());
1448  MCOperand &MO_1 = Inst.getOperand(1);
1449  MCOperand &MO_0 = Inst.getOperand(0);
1450 
1451  // push section onto section stack
1452  MES->PushSection();
1453 
1454  std::string myCharStr;
1455  MCSectionELF *mySection;
1456 
1457  // check if this as an immediate or a symbol
1458  int64_t Value;
1459  bool Absolute = MO_1.getExpr()->evaluateAsAbsolute(Value);
1460  if (Absolute) {
1461  // Create a new section - one for each constant
1462  // Some or all of the zeros are replaced with the given immediate.
1463  if (is32bit) {
1464  std::string myImmStr = utohexstr(static_cast<uint32_t>(Value));
1465  myCharStr = StringRef(".gnu.linkonce.l4.CONST_00000000")
1466  .drop_back(myImmStr.size())
1467  .str() +
1468  myImmStr;
1469  } else {
1470  std::string myImmStr = utohexstr(Value);
1471  myCharStr = StringRef(".gnu.linkonce.l8.CONST_0000000000000000")
1472  .drop_back(myImmStr.size())
1473  .str() +
1474  myImmStr;
1475  }
1476 
1477  mySection = getContext().getELFSection(myCharStr, ELF::SHT_PROGBITS,
1478  ELF::SHF_ALLOC | ELF::SHF_WRITE);
1479  } else if (MO_1.isExpr()) {
1480  // .lita - for expressions
1481  myCharStr = ".lita";
1482  mySection = getContext().getELFSection(myCharStr, ELF::SHT_PROGBITS,
1483  ELF::SHF_ALLOC | ELF::SHF_WRITE);
1484  } else
1485  llvm_unreachable("unexpected type of machine operand!");
1486 
1487  MES->SwitchSection(mySection);
1488  unsigned byteSize = is32bit ? 4 : 8;
1489  getStreamer().EmitCodeAlignment(byteSize, byteSize);
1490 
1491  MCSymbol *Sym;
1492 
1493  // for symbols, get rid of prepended ".gnu.linkonce.lx."
1494 
1495  // emit symbol if needed
1496  if (Absolute) {
1497  Sym = getContext().getOrCreateSymbol(StringRef(myCharStr.c_str() + 16));
1498  if (Sym->isUndefined()) {
1499  getStreamer().EmitLabel(Sym);
1500  getStreamer().EmitSymbolAttribute(Sym, MCSA_Global);
1501  getStreamer().EmitIntValue(Value, byteSize);
1502  }
1503  } else if (MO_1.isExpr()) {
1504  const char *StringStart = nullptr;
1505  const char *StringEnd = nullptr;
1506  if (*Operands[4]->getStartLoc().getPointer() == '#') {
1507  StringStart = Operands[5]->getStartLoc().getPointer();
1508  StringEnd = Operands[6]->getStartLoc().getPointer();
1509  } else { // no pound
1510  StringStart = Operands[4]->getStartLoc().getPointer();
1511  StringEnd = Operands[5]->getStartLoc().getPointer();
1512  }
1513 
1514  unsigned size = StringEnd - StringStart;
1515  std::string DotConst = ".CONST_";
1516  Sym = getContext().getOrCreateSymbol(DotConst +
1517  StringRef(StringStart, size));
1518 
1519  if (Sym->isUndefined()) {
1520  // case where symbol is not yet defined: emit symbol
1521  getStreamer().EmitLabel(Sym);
1522  getStreamer().EmitSymbolAttribute(Sym, MCSA_Local);
1523  getStreamer().EmitValue(MO_1.getExpr(), 4);
1524  }
1525  } else
1526  llvm_unreachable("unexpected type of machine operand!");
1527 
1528  MES->PopSection();
1529 
1530  if (Sym) {
1531  MCInst TmpInst;
1532  if (is32bit) // 32 bit
1533  TmpInst.setOpcode(Hexagon::L2_loadrigp);
1534  else // 64 bit
1535  TmpInst.setOpcode(Hexagon::L2_loadrdgp);
1536 
1537  TmpInst.addOperand(MO_0);
1538  TmpInst.addOperand(MCOperand::createExpr(HexagonMCExpr::create(
1539  MCSymbolRefExpr::create(Sym, getContext()), getContext())));
1540  Inst = TmpInst;
1541  }
1542  }
1543  break;
1544 
1545  // Translate a "$Rdd = #-imm" to "$Rdd = combine(#[-1,0], #-imm)"
1546  case Hexagon::A2_tfrpi: {
1547  MCOperand &Rdd = Inst.getOperand(0);
1548  MCOperand &MO = Inst.getOperand(1);
1549  int64_t Value;
1550  int sVal = (MO.getExpr()->evaluateAsAbsolute(Value) && Value < 0) ? -1 : 0;
1551  MCOperand imm(MCOperand::createExpr(
1552  HexagonMCExpr::create(MCConstantExpr::create(sVal, Context), Context)));
1553  Inst = makeCombineInst(Hexagon::A2_combineii, Rdd, imm, MO);
1554  break;
1555  }
1556 
1557  // Translate a "$Rdd = [#]#imm" to "$Rdd = combine(#, [#]#imm)"
1558  case Hexagon::TFRI64_V4: {
1559  MCOperand &Rdd = Inst.getOperand(0);
1560  MCOperand &MO = Inst.getOperand(1);
1561  int64_t Value;
1562  if (MO.getExpr()->evaluateAsAbsolute(Value)) {
1563  int s8 = Hi_32(Value);
1564  if (!isInt<8>(s8))
1565  OutOfRange(IDLoc, s8, -128);
1566  MCOperand imm(MCOperand::createExpr(HexagonMCExpr::create(
1567  MCConstantExpr::create(s8, Context), Context))); // upper 32
1568  auto Expr = HexagonMCExpr::create(
1569  MCConstantExpr::create(Lo_32(Value), Context), Context);
1570  HexagonMCInstrInfo::setMustExtend(
1571  *Expr, HexagonMCInstrInfo::mustExtend(*MO.getExpr()));
1572  MCOperand imm2(MCOperand::createExpr(Expr)); // lower 32
1573  Inst = makeCombineInst(Hexagon::A4_combineii, Rdd, imm, imm2);
1574  } else {
1575  MCOperand imm(MCOperand::createExpr(HexagonMCExpr::create(
1576  MCConstantExpr::create(0, Context), Context))); // upper 32
1577  Inst = makeCombineInst(Hexagon::A4_combineii, Rdd, imm, MO);
1578  }
1579  break;
1580  }
1581 
1582  // Handle $Rdd = combine(##imm, #imm)"
1583  case Hexagon::TFRI64_V2_ext: {
1584  MCOperand &Rdd = Inst.getOperand(0);
1585  MCOperand &MO1 = Inst.getOperand(1);
1586  MCOperand &MO2 = Inst.getOperand(2);
1587  int64_t Value;
1588  if (MO2.getExpr()->evaluateAsAbsolute(Value)) {
1589  int s8 = Value;
1590  if (s8 < -128 || s8 > 127)
1591  OutOfRange(IDLoc, s8, -128);
1592  }
1593  Inst = makeCombineInst(Hexagon::A2_combineii, Rdd, MO1, MO2);
1594  break;
1595  }
1596 
1597  // Handle $Rdd = combine(#imm, ##imm)"
1598  case Hexagon::A4_combineii: {
1599  MCOperand &Rdd = Inst.getOperand(0);
1600  MCOperand &MO1 = Inst.getOperand(1);
1601  int64_t Value;
1602  if (MO1.getExpr()->evaluateAsAbsolute(Value)) {
1603  int s8 = Value;
1604  if (s8 < -128 || s8 > 127)
1605  OutOfRange(IDLoc, s8, -128);
1606  }
1607  MCOperand &MO2 = Inst.getOperand(2);
1608  Inst = makeCombineInst(Hexagon::A4_combineii, Rdd, MO1, MO2);
1609  break;
1610  }
1611 
1612  case Hexagon::S2_tableidxb_goodsyntax:
1613  Inst.setOpcode(Hexagon::S2_tableidxb);
1614  break;
1615 
1616  case Hexagon::S2_tableidxh_goodsyntax: {
1617  MCInst TmpInst;
1618  MCOperand &Rx = Inst.getOperand(0);
1619  MCOperand &Rs = Inst.getOperand(2);
1620  MCOperand &Imm4 = Inst.getOperand(3);
1621  MCOperand &Imm6 = Inst.getOperand(4);
1622  Imm6.setExpr(HexagonMCExpr::create(
1623  MCBinaryExpr::createSub(Imm6.getExpr(),
1624  MCConstantExpr::create(1, Context), Context),
1625  Context));
1626  TmpInst.setOpcode(Hexagon::S2_tableidxh);
1627  TmpInst.addOperand(Rx);
1628  TmpInst.addOperand(Rx);
1629  TmpInst.addOperand(Rs);
1630  TmpInst.addOperand(Imm4);
1631  TmpInst.addOperand(Imm6);
1632  Inst = TmpInst;
1633  break;
1634  }
1635 
1636  case Hexagon::S2_tableidxw_goodsyntax: {
1637  MCInst TmpInst;
1638  MCOperand &Rx = Inst.getOperand(0);
1639  MCOperand &Rs = Inst.getOperand(2);
1640  MCOperand &Imm4 = Inst.getOperand(3);
1641  MCOperand &Imm6 = Inst.getOperand(4);
1642  Imm6.setExpr(HexagonMCExpr::create(
1643  MCBinaryExpr::createSub(Imm6.getExpr(),
1644  MCConstantExpr::create(2, Context), Context),
1645  Context));
1646  TmpInst.setOpcode(Hexagon::S2_tableidxw);
1647  TmpInst.addOperand(Rx);
1648  TmpInst.addOperand(Rx);
1649  TmpInst.addOperand(Rs);
1650  TmpInst.addOperand(Imm4);
1651  TmpInst.addOperand(Imm6);
1652  Inst = TmpInst;
1653  break;
1654  }
1655 
1656  case Hexagon::S2_tableidxd_goodsyntax: {
1657  MCInst TmpInst;
1658  MCOperand &Rx = Inst.getOperand(0);
1659  MCOperand &Rs = Inst.getOperand(2);
1660  MCOperand &Imm4 = Inst.getOperand(3);
1661  MCOperand &Imm6 = Inst.getOperand(4);
1662  Imm6.setExpr(HexagonMCExpr::create(
1663  MCBinaryExpr::createSub(Imm6.getExpr(),
1664  MCConstantExpr::create(3, Context), Context),
1665  Context));
1666  TmpInst.setOpcode(Hexagon::S2_tableidxd);
1667  TmpInst.addOperand(Rx);
1668  TmpInst.addOperand(Rx);
1669  TmpInst.addOperand(Rs);
1670  TmpInst.addOperand(Imm4);
1671  TmpInst.addOperand(Imm6);
1672  Inst = TmpInst;
1673  break;
1674  }
1675 
1676  case Hexagon::M2_mpyui:
1677  Inst.setOpcode(Hexagon::M2_mpyi);
1678  break;
1679  case Hexagon::M2_mpysmi: {
1680  MCInst TmpInst;
1681  MCOperand &Rd = Inst.getOperand(0);
1682  MCOperand &Rs = Inst.getOperand(1);
1683  MCOperand &Imm = Inst.getOperand(2);
1684  int64_t Value;
1685  MCExpr const &Expr = *Imm.getExpr();
1686  bool Absolute = Expr.evaluateAsAbsolute(Value);
1687  assert(Absolute);
1688  (void)Absolute;
1689  if (!HexagonMCInstrInfo::mustExtend(Expr) &&
1690  ((Value <= -256) || Value >= 256))
1691  return Match_InvalidOperand;
1692  if (Value < 0 && Value > -256) {
1693  Imm.setExpr(HexagonMCExpr::create(
1694  MCConstantExpr::create(Value * -1, Context), Context));
1695  TmpInst.setOpcode(Hexagon::M2_mpysin);
1696  } else
1697  TmpInst.setOpcode(Hexagon::M2_mpysip);
1698  TmpInst.addOperand(Rd);
1699  TmpInst.addOperand(Rs);
1700  TmpInst.addOperand(Imm);
1701  Inst = TmpInst;
1702  break;
1703  }
1704 
1705  case Hexagon::S2_asr_i_r_rnd_goodsyntax: {
1706  MCOperand &Imm = Inst.getOperand(2);
1707  MCInst TmpInst;
1708  int64_t Value;
1709  bool Absolute = Imm.getExpr()->evaluateAsAbsolute(Value);
1710  assert(Absolute);
1711  (void)Absolute;
1712  if (Value == 0) { // convert to $Rd = $Rs
1713  TmpInst.setOpcode(Hexagon::A2_tfr);
1714  MCOperand &Rd = Inst.getOperand(0);
1715  MCOperand &Rs = Inst.getOperand(1);
1716  TmpInst.addOperand(Rd);
1717  TmpInst.addOperand(Rs);
1718  } else {
1719  Imm.setExpr(HexagonMCExpr::create(
1720  MCBinaryExpr::createSub(Imm.getExpr(),
1721  MCConstantExpr::create(1, Context), Context),
1722  Context));
1723  TmpInst.setOpcode(Hexagon::S2_asr_i_r_rnd);
1724  MCOperand &Rd = Inst.getOperand(0);
1725  MCOperand &Rs = Inst.getOperand(1);
1726  TmpInst.addOperand(Rd);
1727  TmpInst.addOperand(Rs);
1728  TmpInst.addOperand(Imm);
1729  }
1730  Inst = TmpInst;
1731  break;
1732  }
1733 
1734  case Hexagon::S2_asr_i_p_rnd_goodsyntax: {
1735  MCOperand &Rdd = Inst.getOperand(0);
1736  MCOperand &Rss = Inst.getOperand(1);
1737  MCOperand &Imm = Inst.getOperand(2);
1738  int64_t Value;
1739  bool Absolute = Imm.getExpr()->evaluateAsAbsolute(Value);
1740  assert(Absolute);
1741  (void)Absolute;
1742  if (Value == 0) { // convert to $Rdd = combine ($Rs[0], $Rs[1])
1743  MCInst TmpInst;
1744  unsigned int RegPairNum = RI->getEncodingValue(Rss.getReg());
1745  std::string R1 = r + utostr(RegPairNum + 1);
1746  StringRef Reg1(R1);
1747  Rss.setReg(matchRegister(Reg1));
1748  // Add a new operand for the second register in the pair.
1749  std::string R2 = r + utostr(RegPairNum);
1750  StringRef Reg2(R2);
1751  TmpInst.setOpcode(Hexagon::A2_combinew);
1752  TmpInst.addOperand(Rdd);
1753  TmpInst.addOperand(Rss);
1754  TmpInst.addOperand(MCOperand::createReg(matchRegister(Reg2)));
1755  Inst = TmpInst;
1756  } else {
1757  Imm.setExpr(HexagonMCExpr::create(
1758  MCBinaryExpr::createSub(Imm.getExpr(),
1759  MCConstantExpr::create(1, Context), Context),
1760  Context));
1761  Inst.setOpcode(Hexagon::S2_asr_i_p_rnd);
1762  }
1763  break;
1764  }
1765 
1766  case Hexagon::A4_boundscheck: {
1767  MCOperand &Rs = Inst.getOperand(1);
1768  unsigned int RegNum = RI->getEncodingValue(Rs.getReg());
1769  if (RegNum & 1) { // Odd mapped to raw:hi, regpair is rodd:odd-1, like r3:2
1770  Inst.setOpcode(Hexagon::A4_boundscheck_hi);
1771  std::string Name = r + utostr(RegNum) + Colon + utostr(RegNum - 1);
1772  StringRef RegPair = Name;
1773  Rs.setReg(matchRegister(RegPair));
1774  } else { // raw:lo
1775  Inst.setOpcode(Hexagon::A4_boundscheck_lo);
1776  std::string Name = r + utostr(RegNum + 1) + Colon + utostr(RegNum);
1777  StringRef RegPair = Name;
1778  Rs.setReg(matchRegister(RegPair));
1779  }
1780  break;
1781  }
1782 
1783  case Hexagon::A2_addsp: {
1784  MCOperand &Rs = Inst.getOperand(1);
1785  unsigned int RegNum = RI->getEncodingValue(Rs.getReg());
1786  if (RegNum & 1) { // Odd mapped to raw:hi
1787  Inst.setOpcode(Hexagon::A2_addsph);
1788  std::string Name = r + utostr(RegNum) + Colon + utostr(RegNum - 1);
1789  StringRef RegPair = Name;
1790  Rs.setReg(matchRegister(RegPair));
1791  } else { // Even mapped raw:lo
1792  Inst.setOpcode(Hexagon::A2_addspl);
1793  std::string Name = r + utostr(RegNum + 1) + Colon + utostr(RegNum);
1794  StringRef RegPair = Name;
1795  Rs.setReg(matchRegister(RegPair));
1796  }
1797  break;
1798  }
1799 
1800  case Hexagon::M2_vrcmpys_s1: {
1801  MCOperand &Rt = Inst.getOperand(2);
1802  unsigned int RegNum = RI->getEncodingValue(Rt.getReg());
1803  if (RegNum & 1) { // Odd mapped to sat:raw:hi
1804  Inst.setOpcode(Hexagon::M2_vrcmpys_s1_h);
1805  std::string Name = r + utostr(RegNum) + Colon + utostr(RegNum - 1);
1806  StringRef RegPair = Name;
1807  Rt.setReg(matchRegister(RegPair));
1808  } else { // Even mapped sat:raw:lo
1809  Inst.setOpcode(Hexagon::M2_vrcmpys_s1_l);
1810  std::string Name = r + utostr(RegNum + 1) + Colon + utostr(RegNum);
1811  StringRef RegPair = Name;
1812  Rt.setReg(matchRegister(RegPair));
1813  }
1814  break;
1815  }
1816 
1817  case Hexagon::M2_vrcmpys_acc_s1: {
1818  MCInst TmpInst;
1819  MCOperand &Rxx = Inst.getOperand(0);
1820  MCOperand &Rss = Inst.getOperand(2);
1821  MCOperand &Rt = Inst.getOperand(3);
1822  unsigned int RegNum = RI->getEncodingValue(Rt.getReg());
1823  if (RegNum & 1) { // Odd mapped to sat:raw:hi
1824  TmpInst.setOpcode(Hexagon::M2_vrcmpys_acc_s1_h);
1825  std::string Name = r + utostr(RegNum) + Colon + utostr(RegNum - 1);
1826  StringRef RegPair = Name;
1827  Rt.setReg(matchRegister(RegPair));
1828  } else { // Even mapped sat:raw:lo
1829  TmpInst.setOpcode(Hexagon::M2_vrcmpys_acc_s1_l);
1830  std::string Name = r + utostr(RegNum + 1) + Colon + utostr(RegNum);
1831  StringRef RegPair = Name;
1832  Rt.setReg(matchRegister(RegPair));
1833  }
1834  // Registers are in different positions
1835  TmpInst.addOperand(Rxx);
1836  TmpInst.addOperand(Rxx);
1837  TmpInst.addOperand(Rss);
1838  TmpInst.addOperand(Rt);
1839  Inst = TmpInst;
1840  break;
1841  }
1842 
1843  case Hexagon::M2_vrcmpys_s1rp: {
1844  MCOperand &Rt = Inst.getOperand(2);
1845  unsigned int RegNum = RI->getEncodingValue(Rt.getReg());
1846  if (RegNum & 1) { // Odd mapped to rnd:sat:raw:hi
1847  Inst.setOpcode(Hexagon::M2_vrcmpys_s1rp_h);
1848  std::string Name = r + utostr(RegNum) + Colon + utostr(RegNum - 1);
1849  StringRef RegPair = Name;
1850  Rt.setReg(matchRegister(RegPair));
1851  } else { // Even mapped rnd:sat:raw:lo
1852  Inst.setOpcode(Hexagon::M2_vrcmpys_s1rp_l);
1853  std::string Name = r + utostr(RegNum + 1) + Colon + utostr(RegNum);
1854  StringRef RegPair = Name;
1855  Rt.setReg(matchRegister(RegPair));
1856  }
1857  break;
1858  }
1859 
1860  case Hexagon::S5_asrhub_rnd_sat_goodsyntax: {
1861  MCOperand &Imm = Inst.getOperand(2);
1862  int64_t Value;
1863  bool Absolute = Imm.getExpr()->evaluateAsAbsolute(Value);
1864  assert(Absolute);
1865  (void)Absolute;
1866  if (Value == 0)
1867  Inst.setOpcode(Hexagon::S2_vsathub);
1868  else {
1869  Imm.setExpr(HexagonMCExpr::create(
1870  MCBinaryExpr::createSub(Imm.getExpr(),
1871  MCConstantExpr::create(1, Context), Context),
1872  Context));
1873  Inst.setOpcode(Hexagon::S5_asrhub_rnd_sat);
1874  }
1875  break;
1876  }
1877 
1878  case Hexagon::S5_vasrhrnd_goodsyntax: {
1879  MCOperand &Rdd = Inst.getOperand(0);
1880  MCOperand &Rss = Inst.getOperand(1);
1881  MCOperand &Imm = Inst.getOperand(2);
1882  int64_t Value;
1883  bool Absolute = Imm.getExpr()->evaluateAsAbsolute(Value);
1884  assert(Absolute);
1885  (void)Absolute;
1886  if (Value == 0) {
1887  MCInst TmpInst;
1888  unsigned int RegPairNum = RI->getEncodingValue(Rss.getReg());
1889  std::string R1 = r + utostr(RegPairNum + 1);
1890  StringRef Reg1(R1);
1891  Rss.setReg(matchRegister(Reg1));
1892  // Add a new operand for the second register in the pair.
1893  std::string R2 = r + utostr(RegPairNum);
1894  StringRef Reg2(R2);
1895  TmpInst.setOpcode(Hexagon::A2_combinew);
1896  TmpInst.addOperand(Rdd);
1897  TmpInst.addOperand(Rss);
1898  TmpInst.addOperand(MCOperand::createReg(matchRegister(Reg2)));
1899  Inst = TmpInst;
1900  } else {
1901  Imm.setExpr(HexagonMCExpr::create(
1902  MCBinaryExpr::createSub(Imm.getExpr(),
1903  MCConstantExpr::create(1, Context), Context),
1904  Context));
1905  Inst.setOpcode(Hexagon::S5_vasrhrnd);
1906  }
1907  break;
1908  }
1909 
1910  case Hexagon::A2_not: {
1911  MCInst TmpInst;
1912  MCOperand &Rd = Inst.getOperand(0);
1913  MCOperand &Rs = Inst.getOperand(1);
1914  TmpInst.setOpcode(Hexagon::A2_subri);
1915  TmpInst.addOperand(Rd);
1916  TmpInst.addOperand(MCOperand::createExpr(
1917  HexagonMCExpr::create(MCConstantExpr::create(-1, Context), Context)));
1918  TmpInst.addOperand(Rs);
1919  Inst = TmpInst;
1920  break;
1921  }
1922  case Hexagon::PS_loadrubabs:
1923  if (!HexagonMCInstrInfo::mustExtend(*Inst.getOperand(1).getExpr()))
1924  Inst.setOpcode(Hexagon::L2_loadrubgp);
1925  break;
1926  case Hexagon::PS_loadrbabs:
1927  if (!HexagonMCInstrInfo::mustExtend(*Inst.getOperand(1).getExpr()))
1928  Inst.setOpcode(Hexagon::L2_loadrbgp);
1929  break;
1930  case Hexagon::PS_loadruhabs:
1931  if (!HexagonMCInstrInfo::mustExtend(*Inst.getOperand(1).getExpr()))
1932  Inst.setOpcode(Hexagon::L2_loadruhgp);
1933  break;
1934  case Hexagon::PS_loadrhabs:
1935  if (!HexagonMCInstrInfo::mustExtend(*Inst.getOperand(1).getExpr()))
1936  Inst.setOpcode(Hexagon::L2_loadrhgp);
1937  break;
1938  case Hexagon::PS_loadriabs:
1939  if (!HexagonMCInstrInfo::mustExtend(*Inst.getOperand(1).getExpr()))
1940  Inst.setOpcode(Hexagon::L2_loadrigp);
1941  break;
1942  case Hexagon::PS_loadrdabs:
1943  if (!HexagonMCInstrInfo::mustExtend(*Inst.getOperand(1).getExpr()))
1944  Inst.setOpcode(Hexagon::L2_loadrdgp);
1945  break;
1946  case Hexagon::PS_storerbabs:
1947  if (!HexagonMCInstrInfo::mustExtend(*Inst.getOperand(0).getExpr()))
1948  Inst.setOpcode(Hexagon::S2_storerbgp);
1949  break;
1950  case Hexagon::PS_storerhabs:
1951  if (!HexagonMCInstrInfo::mustExtend(*Inst.getOperand(0).getExpr()))
1952  Inst.setOpcode(Hexagon::S2_storerhgp);
1953  break;
1954  case Hexagon::PS_storerfabs:
1955  if (!HexagonMCInstrInfo::mustExtend(*Inst.getOperand(0).getExpr()))
1956  Inst.setOpcode(Hexagon::S2_storerfgp);
1957  break;
1958  case Hexagon::PS_storeriabs:
1959  if (!HexagonMCInstrInfo::mustExtend(*Inst.getOperand(0).getExpr()))
1960  Inst.setOpcode(Hexagon::S2_storerigp);
1961  break;
1962  case Hexagon::PS_storerdabs:
1963  if (!HexagonMCInstrInfo::mustExtend(*Inst.getOperand(0).getExpr()))
1964  Inst.setOpcode(Hexagon::S2_storerdgp);
1965  break;
1966  case Hexagon::PS_storerbnewabs:
1967  if (!HexagonMCInstrInfo::mustExtend(*Inst.getOperand(0).getExpr()))
1968  Inst.setOpcode(Hexagon::S2_storerbnewgp);
1969  break;
1970  case Hexagon::PS_storerhnewabs:
1971  if (!HexagonMCInstrInfo::mustExtend(*Inst.getOperand(0).getExpr()))
1972  Inst.setOpcode(Hexagon::S2_storerhnewgp);
1973  break;
1974  case Hexagon::PS_storerinewabs:
1975  if (!HexagonMCInstrInfo::mustExtend(*Inst.getOperand(0).getExpr()))
1976  Inst.setOpcode(Hexagon::S2_storerinewgp);
1977  break;
1978  case Hexagon::A2_zxtb: {
1979  Inst.setOpcode(Hexagon::A2_andir);
1980  Inst.addOperand(
1981  MCOperand::createExpr(MCConstantExpr::create(255, Context)));
1982  break;
1983  }
1984  } // switch
1985 
1986  return Match_Success;
1987 }
1988 
1989 unsigned HexagonAsmParser::matchRegister(StringRef Name) {
1990  if (unsigned Reg = MatchRegisterName(Name))
1991  return Reg;
1992  return MatchRegisterAltName(Name);
1993 }
isReg
static bool isReg(const MCInst &MI, unsigned OpNo)
Definition: MipsInstPrinter.cpp:32
Check
static bool Check(DecodeStatus &Out, DecodeStatus In)
Definition: AArch64Disassembler.cpp:228
llvm::MCAsmLexer::getTok
const AsmToken & getTok() const
Get the current (last) lexed token.
Definition: MCAsmLexer.h:101
llvm::msgpack::Type
Type
MessagePack types as defined in the standard, with the exception of Integer being divided into a sign...
Definition: MsgPackReader.h:49
llvm::HexagonMCExpr::setMustExtend
void setMustExtend(bool Val=true)
Definition: HexagonMCExpr.cpp:85
X
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
llvm::errs
raw_ostream & errs()
This returns a reference to a raw_ostream for standard error.
Definition: raw_ostream.cpp:854
llvm::AsmToken::getString
StringRef getString() const
Get the string for the current token, this includes all characters (for example, the quotes on string...
Definition: MCAsmMacro.h:111
Context
LLVMContext & Context
Definition: NVVMIntrRange.cpp:72
llvm::MCSymbolRefExpr::create
static const MCSymbolRefExpr * create(const MCSymbol *Symbol, MCContext &Ctx)
Definition: MCExpr.h:323
llvm::report_fatal_error
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:140
llvm
This class represents lattice values for constants.
Definition: AllocatorList.h:24
MatchRegisterName
static unsigned MatchRegisterName(StringRef Name)
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void print(const char *ProgName, raw_ostream &S, bool ShowColors=true, bool ShowKindLabel=true) const
Definition: SourceMgr.cpp:374
llvm::MCValue
This represents an "assembler immediate".
Definition: MCValue.h:40
llvm::MCAsmParser::Warning
virtual bool Warning(SMLoc L, const Twine &Msg, SMRange Range=None)=0
Emit a warning at the location L, with the message Msg.
llvm::MCInst::clear
void clear()
Definition: MCInst.h:191
llvm::MCAsmLexer::is
bool is(AsmToken::TokenKind K) const
Check if the current token has kind K.
Definition: MCAsmLexer.h:136
llvm::MCSymbol
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:42
llvm::StringRef::equals_lower
LLVM_NODISCARD bool equals_lower(StringRef RHS) const
equals_lower - Check for string equality, ignoring case.
Definition: StringRef.h:176
LLVM_FALLTHROUGH
#define LLVM_FALLTHROUGH
Definition: Compiler.h:86
llvm::MCAsmParser
Generic assembler parser interface, for use by target specific assembly parsers.
Definition: MCAsmParser.h:110
llvm::MCAsmParserExtension::Initialize
virtual void Initialize(MCAsmParser &Parser)
Initialize the extension for parsing using the given Parser.
Definition: MCAsmParserExtension.cpp:18
llvm::format_hex
FormattedNumber format_hex(uint64_t N, unsigned Width, bool Upper=false)
format_hex - Output N as a fixed width hexadecimal.
Definition: Format.h:186
llvm::MCOperand::createExpr
static MCOperand createExpr(const MCExpr *Val)
Definition: MCInst.h:137
llvm::Lo_32
constexpr uint32_t Lo_32(uint64_t Value)
Return the low 32 bits of a 64 bit value.
Definition: MathExtras.h:289
llvm::MCTargetAsmParser
MCTargetAsmParser - Generic interface to target specific assembly parsers.
Definition: MCTargetAsmParser.h:318
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void setMustNotExtend(bool Val=true)
Definition: HexagonMCExpr.cpp:91
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void push_back(const T &Elt)
Definition: SmallVector.h:218
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LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE size_t size() const
size - Get the string size.
Definition: StringRef.h:138
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virtual bool isToken() const =0
isToken - Is this a token operand?
llvm::MCInst::dump_pretty
void dump_pretty(raw_ostream &OS, const MCInstPrinter *Printer=nullptr, StringRef Separator=" ") const
Dump the MCInst as prettily as possible using the additional MC structures, if given.
Definition: MCInst.cpp:73
llvm::MCTargetStreamer
Target specific streamer interface.
Definition: MCStreamer.h:84
Reg
unsigned Reg
Definition: MachineSink.cpp:979
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constexpr bool isInt< 8 >(int64_t x)
Definition: MathExtras.h:303
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bool isAbsolute() const
Is this an absolute (as opposed to relocatable) value.
Definition: MCValue.h:53
llvm::MCStreamer::PushSection
void PushSection()
Save the current and previous section on the section stack.
Definition: MCStreamer.h:368
bits
demanded bits
Definition: DemandedBits.cpp:63
llvm::MCBinaryExpr::createAnd
static const MCBinaryExpr * createAnd(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Definition: MCExpr.h:466
llvm::MCInstrDesc::isPseudo
bool isPseudo() const
Return true if this is a pseudo instruction that doesn&#39;t correspond to a real machine instruction...
Definition: MCInstrDesc.h:243
R2
#define R2(n)
LLVMInitializeHexagonAsmParser
void LLVMInitializeHexagonAsmParser()
Force static initialization.
Definition: HexagonAsmParser.cpp:820
llvm::MCAsmParser::getTok
const AsmToken & getTok() const
Get the current AsmToken from the stream.
Definition: MCAsmParser.cpp:34
WarnSignedMismatch
static cl::opt< bool > WarnSignedMismatch("mwarn-sign-mismatch", cl::desc("Warn for mismatching a signed and unsigned value"), cl::init(true))
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bool isOuterLoop(MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:624
llvm::object::is32bit
static bool is32bit(MachineTypes Machine)
Definition: COFFImportFile.cpp:33
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MCSymbolRefExpr::VariantKind getAccessVariant() const
Definition: MCValue.cpp:47
llvm::StringRef::data
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE const char * data() const
data - Get a pointer to the start of the string (which may not be null terminated).
Definition: StringRef.h:128
llvm::MCStreamer::EmitInstruction
virtual void EmitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI, bool PrintSchedInfo=false)
Emit the given Instruction into the current section.
Definition: MCStreamer.cpp:956
contains
return AArch64::GPR64RegClass contains(Reg)
llvm::AsmToken::getIdentifier
StringRef getIdentifier() const
Get the identifier string for the current token, which should be an identifier or a string...
Definition: MCAsmMacro.h:100
llvm::MCAsmLexer::getLoc
SMLoc getLoc() const
Get the current source location.
Definition: MCAsmLexer.cpp:24
Name
amdgpu Simplify well known AMD library false Value Value const Twine & Name
Definition: AMDGPULibCalls.cpp:221
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static MCOperand createReg(unsigned Reg)
Definition: MCInst.h:116
llvm::Twine
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:81
llvm::MCAsmLexer
Generic assembler lexer interface, for use by target specific assembly lexers.
Definition: MCAsmLexer.h:40
WarnNoncontigiousRegister
static cl::opt< bool > WarnNoncontigiousRegister("mwarn-noncontigious-register", cl::desc("Warn for register names that arent contigious"), cl::init(true))
ErrorMissingParenthesis
static cl::opt< bool > ErrorMissingParenthesis("merror-missing-parenthesis", cl::desc("Error for missing parenthesis around predicate registers"), cl::init(false))
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This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
llvm::MCAsmParser::printError
virtual bool printError(SMLoc L, const Twine &Msg, SMRange Range=None)=0
Emit an error at the location L, with the message Msg.
llvm::MCExpr
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:36
llvm::AsmToken
Target independent representation for an assembler token.
Definition: MCAsmMacro.h:22
llvm::MCSA_Local
.local (ELF)
Definition: MCDirectives.h:35
llvm::isMem
static bool isMem(const MachineInstr &MI, unsigned Op)
Definition: X86InstrInfo.h:161
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Definition: MCParsedAsmOperand.h:25
llvm::MCOperand::getReg
unsigned getReg() const
Returns the register number.
Definition: MCInst.h:65
llvm::HexagonMCInstrInfo::setMemReorderDisabled
void setMemReorderDisabled(MCInst &MCI)
Definition: HexagonMCInstrInfo.cpp:861
llvm::MCContext
Context object for machine code objects.
Definition: MCContext.h:63
llvm::getToken
std::pair< StringRef, StringRef > getToken(StringRef Source, StringRef Delimiters=" \\\)
getToken - This function extracts one token from source, ignoring any leading characters that appear ...
Definition: StringExtras.cpp:38
llvm::MCBinaryExpr::createSub
static const MCBinaryExpr * createSub(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Definition: MCExpr.h:546
RegisterMCAsmParser
RegisterMCAsmParser - Helper template for registering a target specific assembly parser, for use in the target machine initialization function.
Definition: TargetRegistry.h:1144
llvm::MCExpr::evaluateAsRelocatable
bool evaluateAsRelocatable(MCValue &Res, const MCAsmLayout *Layout, const MCFixup *Fixup) const
Try to evaluate the expression to a relocatable value, i.e.
Definition: MCExpr.cpp:647
llvm::HexagonMCInstrInfo::canonicalizePacket
bool canonicalizePacket(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCContext &Context, MCInst &MCB, HexagonMCChecker *Checker)
Definition: HexagonMCInstrInfo.cpp:124
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LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:133
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SMLoc getLoc() const
Definition: MCAsmLexer.cpp:28
llvm::HexagonMCInstrInfo::extendIfNeeded
void extendIfNeeded(MCContext &Context, MCInstrInfo const &MCII, MCInst &MCB, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:204
llvm::HexagonMCInstrInfo::setMustExtend
void setMustExtend(MCExpr const &Expr, bool Val=true)
Definition: HexagonMCInstrInfo.cpp:778
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const MCExpr * getExpr() const
Definition: MCInst.h:96
llvm::StringRef::substr
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE StringRef substr(size_t Start, size_t N=npos) const
Return a reference to the substring from [Start, Start + N).
Definition: StringRef.h:598
llvm::StringRef::upper
LLVM_NODISCARD std::string upper() const
Convert the given ASCII string to uppercase.
Definition: StringRef.cpp:116
llvm::MCExpr::Unary
Unary expressions.
Definition: MCExpr.h:42
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Analysis containing CSE Info
Definition: CSEInfo.cpp:21
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:161
llvm::MCStreamer::hasRawTextSupport
virtual bool hasRawTextSupport() const
Return true if this asm streamer supports emitting unformatted text to the .s file with EmitRawText...
Definition: MCStreamer.h:293
llvm::MCRegisterInfo
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Definition: MCRegisterInfo.h:129
llvm::MCAsmParser::addAliasForDirective
virtual void addAliasForDirective(StringRef Directive, StringRef Alias)=0
llvm::MCConstantExpr::getValue
int64_t getValue() const
Definition: MCExpr.h:152
llvm::MCAsmParser::getContext
virtual MCContext & getContext()=0
llvm::cl::init
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:423
llvm::MCStreamer
Streaming machine code generation interface.
Definition: MCStreamer.h:189
llvm::HexagonMCExpr::create
static HexagonMCExpr * create(MCExpr const *Expr, MCContext &Ctx)
Definition: HexagonMCExpr.cpp:23
llvm::MCStreamer::getTargetStreamer
MCTargetStreamer * getTargetStreamer()
Definition: MCStreamer.h:258
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:46
llvm::HexagonMCInstrInfo::mustExtend
bool mustExtend(MCExpr const &Expr)
Definition: HexagonMCInstrInfo.cpp:783
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
llvm::MCStreamer::SwitchSection
virtual void SwitchSection(MCSection *Section, const MCExpr *Subsection=nullptr)
Set the current section where code is being emitted to Section.
Definition: MCStreamer.cpp:1040
llvm::HexagonMCExpr::setSignMismatch
void setSignMismatch(bool Val=true)
Definition: HexagonMCExpr.cpp:114
llvm::MCObjectStreamer::getAssembler
MCAssembler & getAssembler()
Definition: MCObjectStreamer.h:105
llvm::MCInstrInfo
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:24
llvm::MCAsmParser::getLexer
virtual MCAsmLexer & getLexer()=0
llvm::isPowerOf2_64
constexpr bool isPowerOf2_64(uint64_t Value)
Return true if the argument is a power of two > 0 (64 bit edition.)
Definition: MathExtras.h:434
llvm::HexagonMCInstrInfo::getDesc
MCInstrDesc const & getDesc(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:225
ErrorNoncontigiousRegister
static cl::opt< bool > ErrorNoncontigiousRegister("merror-noncontigious-register", cl::desc("Error for register names that aren't contigious"), cl::init(false))
llvm::MCOperand::isExpr
bool isExpr() const
Definition: MCInst.h:61
print
static void print(raw_ostream &Out, object::Archive::Kind Kind, T Val)
Definition: ArchiveWriter.cpp:145
llvm::MCAsmLexer::peekTok
const AsmToken peekTok(bool ShouldSkipSpace=true)
Look ahead at the next token to be lexed.
Definition: MCAsmLexer.h:106
llvm::MCAsmParser::Error
bool Error(SMLoc L, const Twine &Msg, SMRange Range=None)
Return an error at the location L, with the message Msg.
Definition: MCAsmParser.cpp:88
llvm::remove_if
auto remove_if(R &&Range, UnaryPredicate P) -> decltype(adl_begin(Range))
Provide wrappers to std::remove_if which take ranges instead of having to pass begin/end explicitly...
Definition: STLExtras.h:1226
llvm::isIntN
bool isIntN(unsigned N, int64_t x)
Checks if an signed integer fits into the given (dynamic) bit width.
Definition: MathExtras.h:398
llvm::SmallVectorBase::size
size_t size() const
Definition: SmallVector.h:53
llvm::HexagonMCExpr::mustNotExtend
bool mustNotExtend() const
Definition: HexagonMCExpr.cpp:95
llvm::MCInst::setLoc
void setLoc(SMLoc loc)
Definition: MCInst.h:179
llvm::raw_string_ostream::str
std::string & str()
Flushes the stream contents to the target string and returns the string&#39;s reference.
Definition: raw_ostream.h:499
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:136
llvm::MCBinaryExpr::createLShr
static const MCBinaryExpr * createLShr(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Definition: MCExpr.h:541
MatchRegisterAltName
static unsigned MatchRegisterAltName(StringRef Name)
Maps from the set of all alternative registernames to a register number.
llvm::StringRef::drop_back
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE StringRef drop_back(size_t N=1) const
Return a StringRef equal to &#39;this&#39; but with the last N elements dropped.
Definition: StringRef.h:654
llvm::StringRef::compare_lower
LLVM_NODISCARD int compare_lower(StringRef RHS) const
compare_lower - Compare two strings, ignoring case.
Definition: StringRef.cpp:38
llvm::HexagonMCELFStreamer::HexagonMCEmitLocalCommonSymbol
void HexagonMCEmitLocalCommonSymbol(MCSymbol *Symbol, uint64_t Size, unsigned ByteAlignment, unsigned AccessSize)
Definition: HexagonMCELFStreamer.cpp:140
llvm::MCTargetStreamer::getStreamer
MCStreamer & getStreamer()
Definition: MCStreamer.h:92
llvm::MCInst::setOpcode
void setOpcode(unsigned Op)
Definition: MCInst.h:173
llvm::size
auto size(R &&Range, typename std::enable_if< std::is_same< typename std::iterator_traits< decltype(Range.begin())>::iterator_category, std::random_access_iterator_tag >::value, void >::type *=nullptr) -> decltype(std::distance(Range.begin(), Range.end()))
Get the size of a range.
Definition: STLExtras.h:1167
llvm::MCAsmParser::getStreamer
virtual MCStreamer & getStreamer()=0
Return the output streamer for the assembler.
llvm::MCAsmLexer::UnLex
void UnLex(AsmToken const &Token)
Definition: MCAsmLexer.h:88
llvm::MCExpr::getKind
ExprKind getKind() const
Definition: MCExpr.h:73
llvm::MCSymbol::isUndefined
bool isUndefined(bool SetUsed=true) const
isUndefined - Check if this symbol undefined (i.e., implicitly defined).
Definition: MCSymbol.h:257
llvm::SmallVector
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:847
llvm::MCInst::getOperand
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:182
llvm::StringRef::split
LLVM_NODISCARD std::pair< StringRef, StringRef > split(char Separator) const
Split into two substrings around the first occurrence of a separator character.
Definition: StringRef.h:727
Register
Promote Memory to Register
Definition: Mem2Reg.cpp:110
previousIsLoop
static bool previousIsLoop(OperandVector &Operands, size_t Index)
Definition: HexagonAsmParser.cpp:838
previousEqual
static bool previousEqual(OperandVector &Operands, size_t Index, StringRef String)
Definition: HexagonAsmParser.cpp:828
llvm::utostr
std::string utostr(uint64_t X, bool isNeg=false)
Definition: StringExtras.h:224
llvm::MCAsmLexer::Lex
const AsmToken & Lex()
Consume the next token from the input stream and return it.
Definition: MCAsmLexer.h:74
llvm::dbgs
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:133
llvm::AsmToken::is
bool is(TokenKind K) const
Definition: MCAsmMacro.h:83
getReg
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
Definition: MipsDisassembler.cpp:581
llvm::MCExpr::evaluateAsAbsolute
bool evaluateAsAbsolute(int64_t &Res, const MCAsmLayout &Layout, const SectionAddrMap &Addrs) const
Try to evaluate the expression to an absolute value.
Definition: MCExpr.cpp:456
llvm::ErrorInfo
Base class for user error types.
Definition: Error.h:345
llvm::SmallVectorImpl::insert
iterator insert(iterator I, T &&Elt)
Definition: SmallVector.h:478
llvm::MCOperand::createInst
static MCOperand createInst(const MCInst *Val)
Definition: MCInst.h:144
Success
#define Success
Definition: AArch64Disassembler.cpp:246
llvm::SmallVectorTemplateCommon::end
LLVM_ATTRIBUTE_ALWAYS_INLINE iterator end()
Definition: SmallVector.h:133
llvm::MCRegisterInfo::getEncodingValue
uint16_t getEncodingValue(unsigned RegNo) const
Returns the encoding for RegNo.
Definition: MCRegisterInfo.h:443
llvm::SmallVectorImpl::emplace_back
void emplace_back(ArgTypes &&... Args)
Definition: SmallVector.h:652
llvm::HexagonMCInstrInfo::getExpr
MCExpr const & getExpr(MCExpr const &Expr)
Definition: HexagonMCInstrInfo.cpp:280
llvm::MCSA_Global
.type _foo,
Definition: MCDirectives.h:30
llvm::SmallVectorBase::empty
LLVM_NODISCARD bool empty() const
Definition: SmallVector.h:56
makeCombineInst
static MCInst makeCombineInst(int opCode, MCOperand &Rdd, MCOperand &MO1, MCOperand &MO2)
Definition: HexagonAsmParser.cpp:1224
I
#define I(x, y, z)
Definition: MD5.cpp:58
N
#define N
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition: MCSubtargetInfo.h:36
llvm::HexagonMCExpr::mustExtend
bool mustExtend() const
Definition: HexagonMCExpr.cpp:90
llvm::MCSectionELF
This represents a section on linux, lots of unix variants and some bare metal systems.
Definition: MCSectionELF.h:28
llvm::dyn_cast
LLVM_NODISCARD std::enable_if<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:323
llvm::MCExpr::SymbolRef
References to labels and assigned expressions.
Definition: MCExpr.h:41
Size
uint32_t Size
Definition: Profile.cpp:47
llvm::HexagonMCInstrInfo::setMustNotExtend
void setMustNotExtend(MCExpr const &Expr, bool Val=true)
Definition: HexagonMCInstrInfo.cpp:787
llvm::HexagonMCInstrInfo::bundleSize
size_t bundleSize(MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:117
llvm::SignExtend64
constexpr int64_t SignExtend64(uint64_t x)
Sign-extend the number in the bottom B bits of X to a 64-bit integer.
Definition: MathExtras.h:749
llvm::MCOperand::setReg
void setReg(unsigned Reg)
Set the register number.
Definition: MCInst.h:71
Kind
const unsigned Kind
Definition: ARMAsmParser.cpp:10586
llvm::StringRef::lower
LLVM_NODISCARD std::string lower() const
Definition: StringRef.cpp:108
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::HexagonMCInstrInfo::isInnerLoop
bool isInnerLoop(MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:596
llvm::raw_string_ostream
A raw_ostream that writes to an std::string.
Definition: raw_ostream.h:483
llvm::MCStreamer::PopSection
bool PopSection()
Restore the current and previous section from the section stack.
Definition: MCStreamer.h:377
HEXAGON_PACKET_SIZE
#define HEXAGON_PACKET_SIZE
Definition: HexagonMCTargetDesc.h:36
llvm::Hi_32
constexpr uint32_t Hi_32(uint64_t Value)
Return the high 32 bits of a 64 bit value.
Definition: MathExtras.h:284
llvm::Value
LLVM Value Representation.
Definition: Value.h:73
llvm::MCExpr::Binary
Binary expressions.
Definition: MCExpr.h:39
llvm::Error
Lightweight error class with error context and mandatory checking.
Definition: Error.h:158
llvm::HexagonMCChecker
Check for a valid bundle.
Definition: HexagonMCChecker.h:35
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:46
llvm::MCInst::addOperand
void addOperand(const MCOperand &Op)
Definition: MCInst.h:186
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
WarnMissingParenthesis
static cl::opt< bool > WarnMissingParenthesis("mwarn-missing-parenthesis", cl::desc("Warn for missing parenthesis around predicate registers"), cl::init(true))
raw_ostream.h
llvm::SMLoc
Represents a location in source code.
Definition: SMLoc.h:24
llvm::HexagonMCInstrInfo::setS27_2_reloc
void setS27_2_reloc(MCExpr const &Expr, bool Val=true)
Definition: HexagonMCInstrInfo.cpp:795
llvm::MCInst::getOpcode
unsigned getOpcode() const
Definition: MCInst.h:174
llvm::isUIntN
bool isUIntN(unsigned N, uint64_t x)
Checks if an unsigned integer fits into the given (dynamic) bit width.
Definition: MathExtras.h:393
LLVM_DEBUG
#define LLVM_DEBUG(X)
Definition: Debug.h:123
llvm::MCOperand
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:35
llvm::MCOperand::createImm
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:123
llvm::MCConstantExpr::create
static const MCConstantExpr * create(int64_t Value, MCContext &Ctx)
Definition: MCExpr.cpp:164
llvm::getTheHexagonTarget
Target & getTheHexagonTarget()
Definition: HexagonTargetInfo.cpp:15
llvm::HexagonMCELFStreamer::HexagonMCEmitCommonSymbol
void HexagonMCEmitCommonSymbol(MCSymbol *Symbol, uint64_t Size, unsigned ByteAlignment, unsigned AccessSize)
Definition: HexagonMCELFStreamer.cpp:88
llvm::utohexstr
std::string utohexstr(uint64_t X, bool LowerCase=false)
Definition: StringExtras.h:125
llvm::SMDiagnostic
Instances of this class encapsulate one diagnostic report, allowing printing to a raw_ostream as a ca...
Definition: SourceMgr.h:260
llvm::AsmToken::getKind
TokenKind getKind() const
Definition: MCAsmMacro.h:82
llvm::MCOperand::setExpr
void setExpr(const MCExpr *Val)
Definition: MCInst.h:101
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