40 #define DEBUG_TYPE "mccodeemitter" 43 using namespace Hexagon;
45 STATISTIC(MCNumEmitted,
"Number of MC instructions emitted");
49 #define _ fixup_Invalid 50 #define P(x) Hexagon::fixup_Hexagon##x 51 static const std::map<unsigned, std::vector<unsigned>>
ExtFixups = {
54 _,
_,
P(_DTPREL_16_X),
P(_DTPREL_11_X),
55 P(_DTPREL_11_X),
P(_9_X),
_,
P(_DTPREL_11_X),
56 P(_DTPREL_16_X),
_,
_,
_,
57 P(_DTPREL_16_X),
_,
_,
_,
64 _,
_,
P(_GOT_11_X), _ ,
65 _ ,
P(_9_X),
_,
P(_GOT_11_X),
66 P(_GOT_16_X),
_,
_,
_,
67 P(_GOT_16_X),
_,
_,
_,
74 _,
_,
P(_GOTREL_11_X),
P(_GOTREL_11_X),
75 P(_GOTREL_11_X),
P(_9_X),
_,
P(_GOTREL_11_X),
76 P(_GOTREL_16_X),
_,
_,
_,
77 P(_GOTREL_16_X),
_,
_,
_,
84 _,
_,
P(_TPREL_16_X),
P(_TPREL_11_X),
85 P(_TPREL_11_X),
P(_9_X),
_,
P(_TPREL_11_X),
86 P(_TPREL_16_X),
_,
_,
_,
87 P(_TPREL_16_X),
_,
_,
_,
94 _,
_,
P(_GD_GOT_16_X),
P(_GD_GOT_11_X),
95 P(_GD_GOT_11_X),
P(_9_X),
_,
P(_GD_GOT_11_X),
96 P(_GD_GOT_16_X),
_,
_,
_,
97 P(_GD_GOT_16_X),
_,
_,
_,
101 P(_GD_GOT_32_6_X) }},
105 _,
P(_9_X),
_,
P(_GD_PLT_B22_PCREL_X),
108 _,
_,
P(_GD_PLT_B22_PCREL_X),
_,
114 _,
_,
P(_IE_16_X),
_,
116 P(_IE_16_X),
_,
_,
_,
117 P(_IE_16_X),
_,
_,
_,
124 _,
_,
P(_IE_GOT_11_X),
P(_IE_GOT_11_X),
125 P(_IE_GOT_11_X),
P(_9_X),
_,
P(_IE_GOT_11_X),
126 P(_IE_GOT_16_X),
_,
_,
_,
127 P(_IE_GOT_16_X),
_,
_,
_,
131 P(_IE_GOT_32_6_X) }},
134 _,
_,
P(_LD_GOT_11_X),
P(_LD_GOT_11_X),
135 P(_LD_GOT_11_X),
P(_9_X),
_,
P(_LD_GOT_11_X),
136 P(_LD_GOT_16_X),
_,
_,
_,
137 P(_LD_GOT_16_X),
_,
_,
_,
141 P(_LD_GOT_32_6_X) }},
145 _,
P(_9_X),
_,
P(_LD_PLT_B22_PCREL_X),
148 _,
_,
P(_LD_PLT_B22_PCREL_X),
_,
154 _,
_,
P(_6_PCREL_X),
_,
164 _,
_,
P(_6_X),
P(_8_X),
165 P(_8_X),
P(_9_X),
P(_10_X),
P(_11_X),
166 P(_12_X),
P(_B13_PCREL),
_,
P(_B15_PCREL_X),
168 _,
_,
P(_B22_PCREL_X),
_,
175 static const std::map<unsigned, std::vector<unsigned>>
StdFixups = {
181 P(_DTPREL_16),
_,
_,
_,
212 _,
_,
P(_PLT_B22_PCREL),
_,
219 _,
_,
_,
P(_TPREL_11_X),
221 P(_TPREL_16),
_,
_,
_,
231 P(_GD_GOT_16),
_,
_,
_,
242 _,
_,
P(_GD_PLT_B22_PCREL),
_,
251 P(_GPREL16_0),
_,
_,
_,
281 P(_IE_GOT_16),
_,
_,
_,
291 P(_LD_GOT_16),
_,
_,
_,
302 _,
_,
P(_LD_PLT_B22_PCREL),
_,
330 _,
P(_B13_PCREL),
_,
P(_B15_PCREL),
332 _,
_,
P(_B22_PCREL),
_,
342 uint32_t HexagonMCCodeEmitter::parseBits(
size_t Last,
MCInst const &MCB,
343 MCInst const &MCI)
const {
345 if (State.Index == 0) {
348 assert(State.Index != Last);
352 if (State.Index == 1) {
355 assert(State.Index != Last);
360 assert(State.Index == Last);
363 if (State.Index == Last)
377 State.Extended =
false;
385 verifyInstructionPredicates(HMI, Features);
387 EncodeSingleInstruction(HMI, OS, Fixups, STI, parseBits(Last, HMB, HMI));
395 unsigned Producer2) {
396 if (Consumer == Producer)
398 if (Consumer == Producer2)
401 if (Producer >= Hexagon::W0 && Producer <= Hexagon::W15)
402 if (Consumer >= Hexagon::V0 && Consumer <= Hexagon::V31)
403 return ((Consumer - Hexagon::V0) >> 1) == (Producer - Hexagon::W0);
417 "pseudo-instruction found");
421 Binary = getBinaryCodeForInstr(MI, Fixups, STI);
426 if (!Binary && Opc != DuplexIClass0 && Opc != A4_ext) {
434 if (Opc >= Hexagon::DuplexIClass0 && Opc <= Hexagon::DuplexIClassF) {
436 "Emitting duplex without duplex parse bits");
437 unsigned DupIClass = MI.
getOpcode() - Hexagon::DuplexIClass0;
441 Binary = ((DupIClass & 0xE) << (29 - 1)) | ((DupIClass & 0x1) << 13);
447 unsigned SubBits0 = getBinaryCodeForInstr(*Sub0, Fixups, STI);
449 State.SubInst1 =
true;
450 unsigned SubBits1 = getBinaryCodeForInstr(*Sub1, Fixups, STI);
451 State.SubInst1 =
false;
453 Binary |= SubBits0 | (SubBits1 << 16);
463 Stream <<
"Unrecognized relocation combination: width=" << Width
475 using namespace Hexagon;
480 for (
auto I = Instrs.begin(),
N = Instrs.end();
I !=
N; ++
I) {
481 if (
I->getInst() != &
MI)
483 assert(
I+1 !=
N &&
"Extender cannot be last in packet");
484 const MCInst &NextI = *(
I+1)->getInst();
493 static const std::map<unsigned,unsigned> Relocs = {
507 auto F = Relocs.find(VarKind);
508 if (
F != Relocs.end())
516 static const std::map<unsigned,unsigned> RelocsLo = {
528 static const std::map<unsigned,unsigned> RelocsHi = {
542 case Hexagon::A2_tfril: {
543 auto F = RelocsLo.find(VarKind);
544 if (
F != RelocsLo.end())
549 case Hexagon::A2_tfrih: {
550 auto F = RelocsHi.find(VarKind);
551 if (
F != RelocsHi.end())
586 unsigned HexagonMCCodeEmitter::getExprOpValue(
const MCInst &MI,
589 if (isa<HexagonMCExpr>(ME))
592 if (ME->evaluateAsAbsolute(Value)) {
599 if (State.Extended && InstExtendable && !IsSub0) {
600 unsigned OpIdx = ~0u;
610 Value = (Value & 0x3f) << Shift;
635 <<
"\nOpcode: " << Opc <<
"\nRelocation bits: " 636 << FixupWidth <<
"\nAddend: " << State.Addend
637 <<
"\nVariant: " <<
unsigned(VarKind)
638 <<
"\n----------------------------------------\n");
643 if (FixupWidth == 16 && !State.Extended) {
657 for (
const MCPhysReg *U =
D.getImplicitUses(); U && *U; ++U)
658 if (*U == Hexagon::GP)
663 FixupKind = GPRelFixups[Shift];
674 switch (FixupWidth) {
686 else if (FixupWidth == 7 && BranchOrCR)
691 FixupKind = getFixupNoBits(MCII, MI, MO, VarKind);
696 if (FixupKind == fixup_Invalid) {
699 auto FindVK = FixupTable.find(VarKind);
700 if (FindVK != FixupTable.end())
701 FixupKind = FindVK->second[FixupWidth];
704 if (FixupKind == fixup_Invalid)
708 if (State.Addend != 0 &&
isPCRel(FixupKind)) {
725 size_t OperandNumber = ~0U;
731 assert((OperandNumber != ~0U) &&
"Operand not found");
737 unsigned SOffset = 0;
738 unsigned VOffset = 0;
740 unsigned DefReg1, DefReg2;
743 const MCOperand *
I = Instrs.begin() + State.Index - 1;
746 assert(I != Instrs.begin() - 1 &&
"Couldn't find producer");
751 DefReg1 = DefReg2 = 0;
770 "Unpredicated consumer depending on predicated producer");
790 return MCT.getRegisterInfo()->getEncodingValue(Reg);
802 #define ENABLE_INSTR_PREDICATE_VERIFIER 803 #include "HexagonGenMCCodeEmitter.inc" static LLVM_ATTRIBUTE_NORETURN void raise_relocation_error(unsigned Width, unsigned Kind)
bool isDuplex(MCInstrInfo const &MCII, MCInst const &MCI)
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
This class represents lattice values for constants.
VariantKind getKind() const
static const std::map< unsigned, std::vector< unsigned > > StdFixups
void push_back(const T &Elt)
Describe properties that are true of each instruction in the target description file.
MCOperand const & getNewValueOperand(MCInstrInfo const &MCII, MCInst const &MCI)
const FeatureBitset Features
bool isBundle(MCInst const &MCI)
const MCExpr * getLHS() const
Get the left-hand side expression of the binary operator.
#define HEXAGON_INSTR_SIZE
STATISTIC(NumFunctions, "Total number of functions")
bool isSubInstruction(MCInst const &MCI)
bool isOuterLoop(MCInst const &MCI)
static Lanai::Fixups FixupKind(const MCExpr *Expr)
bool isNewValue(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn expects newly produced value.
static const unsigned fixup_Invalid
bool isBranch() const
Returns true if this is a conditional, unconditional, or indirect branch.
Encode information on a single operation to perform on a byte sequence (e.g., an encoded instruction)...
MCCodeEmitter * createHexagonMCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, MCContext &MCT)
bool isImmext(MCInst const &MCI)
const FeatureBitset & getFeatureBits() const
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Base class for the full range of assembler expressions which are needed for parsing.
Represent a reference to a symbol from inside an expression.
iterator_range< Hexagon::PacketIterator > bundleInstructions(MCInstrInfo const &MCII, MCInst const &MCI)
bool s27_2_reloc(MCExpr const &Expr)
StringRef getName(MCInstrInfo const &MCII, MCInst const &MCI)
unsigned getReg() const
Returns the register number.
Context object for machine code objects.
const MCExpr * getRHS() const
Get the right-hand side expression of the binary operator.
const MCInst * getInst() const
bool hasNewValue2(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn produces a second value.
const MCExpr * getExpr() const
static const MCBinaryExpr * createAdd(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Instances of this class represent a single low-level machine instruction.
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
void encodeInstruction(MCInst const &MI, raw_ostream &OS, SmallVectorImpl< MCFixup > &Fixups, MCSubtargetInfo const &STI) const override
Emit the bundle.
unsigned const MachineRegisterInfo * MRI
bool isExtentSigned(MCInstrInfo const &MCII, MCInst const &MCI)
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
MCCodeEmitter - Generic instruction encoding interface.
MCOperand const & getNewValueOperand2(MCInstrInfo const &MCII, MCInst const &MCI)
Interface to description of machine instruction set.
MCFixupKind
Extensible enumeration to represent the type of a fixup.
MCInstrDesc const & getDesc(MCInstrInfo const &MCII, MCInst const &MCI)
unsigned getNumOperands() const
Definition for classes that emit Hexagon machine code from MCInsts.
Binary assembler expressions.
static MCFixup create(uint32_t Offset, const MCExpr *Value, MCFixupKind Kind, SMLoc Loc=SMLoc())
static const std::map< unsigned, std::vector< unsigned > > ExtFixups
unsigned SubregisterBit(unsigned Consumer, unsigned Producer, unsigned Producer2)
std::string & str()
Flushes the stream contents to the target string and returns the string's reference.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
unsigned short getExtendableOp(MCInstrInfo const &MCII, MCInst const &MCI)
PowerPC TLS Dynamic Call Fixup
bool isExtendable(MCInstrInfo const &MCII, MCInst const &MCI)
bool isVector(MCInstrInfo const &MCII, MCInst const &MCI)
const MCOperand & getOperand(unsigned i) const
constexpr size_t array_lengthof(T(&)[N])
Find the length of an array.
static GCRegistry::Add< StatepointGC > D("statepoint-example", "an example strategy for statepoint")
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
bool isPredicated(MCInstrInfo const &MCII, MCInst const &MCI)
bool isExtended(MCInstrInfo const &MCII, MCInst const &MCI)
#define LLVM_ATTRIBUTE_NORETURN
MCExpr const & getExpr(MCExpr const &Expr)
static unsigned UseReg(const MachineOperand &MO)
bool isCall() const
Return true if the instruction is a call.
Generic base class for all target subtargets.
References to labels and assigned expressions.
size_t bundleSize(MCInst const &MCI)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool isInnerLoop(MCInst const &MCI)
A raw_ostream that writes to an std::string.
LLVM Value Representation.
static bool RegisterMatches(unsigned Consumer, unsigned Producer, unsigned Producer2)
unsigned getOpcode() const
Return the opcode number for this descriptor.
This class implements an extremely fast bulk output stream that can only output to a stream...
void EncodeSingleInstruction(const MCInst &MI, raw_ostream &OS, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI, uint32_t Parse) const
EncodeSingleInstruction - Emit a single.
unsigned getDuplexRegisterNumbering(unsigned Reg)
bool hasNewValue(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn produces a value.
unsigned getType(MCInstrInfo const &MCII, MCInst const &MCI)
Return the Hexagon ISA class for the insn.
static bool isPCRel(unsigned Kind)
unsigned getMachineOpValue(MCInst const &MI, MCOperand const &MO, SmallVectorImpl< MCFixup > &Fixups, MCSubtargetInfo const &STI) const
Return binary encoding of operand.
unsigned getOpcode() const
unsigned getExtentAlignment(MCInstrInfo const &MCII, MCInst const &MCI)
Instances of this class represent operands of the MCInst class.
bool isPredicatedTrue(MCInstrInfo const &MCII, MCInst const &MCI)
static const MCConstantExpr * create(int64_t Value, MCContext &Ctx)
unsigned getExtentBits(MCInstrInfo const &MCII, MCInst const &MCI)