#include "Target/ARM/ARMISelLowering.h"

Inheritance diagram for llvm::ARMTargetLowering:

Collaboration diagram for llvm::ARMTargetLowering:

[legend]

Public Member Functions
	ARMTargetLowering (const TargetMachine &TM, const ARMSubtarget &STI)

unsigned	getJumpTableEncoding () const override
	Return the entry encoding for a jump table in the current function. More...

bool	useSoftFloat () const override

SDValue	LowerOperation (SDValue Op, SelectionDAG &DAG) const override
	This callback is invoked for operations that are unsupported by the target, which are registered to use 'custom' lowering, and whose defined values are all legal. More...

void	ReplaceNodeResults (SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
	ReplaceNodeResults - Replace the results of node with an illegal result type with new values built out of custom code. More...

const char *	getTargetNodeName (unsigned Opcode) const override
	This method returns the name of a target specific DAG node. More...

bool	isSelectSupported (SelectSupportKind Kind) const override

bool	isReadOnly (const GlobalValue *GV) const

EVT	getSetCCResultType (const DataLayout &DL, LLVMContext &Context, EVT VT) const override
	getSetCCResultType - Return the value type to use for ISD::SETCC. More...

MachineBasicBlock *	EmitInstrWithCustomInserter (MachineInstr &MI, MachineBasicBlock *MBB) const override
	This method should be implemented by targets that mark instructions with the 'usesCustomInserter' flag. More...

void	AdjustInstrPostInstrSelection (MachineInstr &MI, SDNode *Node) const override
	This method should be implemented by targets that mark instructions with the 'hasPostISelHook' flag. More...

SDValue	PerformCMOVCombine (SDNode *N, SelectionDAG &DAG) const
	PerformCMOVCombine - Target-specific DAG combining for ARMISD::CMOV. More...

SDValue	PerformBRCONDCombine (SDNode *N, SelectionDAG &DAG) const
	PerformBRCONDCombine - Target-specific DAG combining for ARMISD::BRCOND. More...

SDValue	PerformCMOVToBFICombine (SDNode *N, SelectionDAG &DAG) const

SDValue	PerformDAGCombine (SDNode *N, DAGCombinerInfo &DCI) const override
	This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for. More...

bool	isDesirableToTransformToIntegerOp (unsigned Opc, EVT VT) const override
	Return true if it is profitable for dag combiner to transform a floating point op of specified opcode to a equivalent op of an integer type. More...

bool	allowsMisalignedMemoryAccesses (EVT VT, unsigned AddrSpace, unsigned Align, bool *Fast) const override
	allowsMisalignedMemoryAccesses - Returns true if the target allows unaligned memory accesses of the specified type. More...

EVT	getOptimalMemOpType (uint64_t Size, unsigned DstAlign, unsigned SrcAlign, bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc, MachineFunction &MF) const override
	Returns the target specific optimal type for load and store operations as a result of memset, memcpy, and memmove lowering. More...

bool	isTruncateFree (Type SrcTy, Type DstTy) const override
	Return true if it's free to truncate a value of type FromTy to type ToTy. More...

bool	isTruncateFree (EVT SrcVT, EVT DstVT) const override

bool	isZExtFree (SDValue Val, EVT VT2) const override
	Return true if zero-extending the specific node Val to type VT2 is free (either because it's implicitly zero-extended such as ARM ldrb / ldrh or because it's folded such as X86 zero-extending loads). More...

bool	isFNegFree (EVT VT) const override
	Return true if an fneg operation is free to the point where it is never worthwhile to replace it with a bitwise operation. More...

bool	isVectorLoadExtDesirable (SDValue ExtVal) const override
	Return true if folding a vector load into ExtVal (a sign, zero, or any extend node) is profitable. More...

bool	allowTruncateForTailCall (Type Ty1, Type Ty2) const override
	Return true if a truncation from FromTy to ToTy is permitted when deciding whether a call is in tail position. More...

bool	isLegalAddressingMode (const DataLayout &DL, const AddrMode &AM, Type Ty, unsigned AS, Instruction I=nullptr) const override
	isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target, for a load/store of the specified type. More...

int	getScalingFactorCost (const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS) const override
	getScalingFactorCost - Return the cost of the scaling used in addressing mode represented by AM. More...

bool	isLegalT2ScaledAddressingMode (const AddrMode &AM, EVT VT) const

bool	isLegalT1ScaledAddressingMode (const AddrMode &AM, EVT VT) const
	Returns true if the addresing mode representing by AM is legal for the Thumb1 target, for a load/store of the specified type. More...

bool	isLegalICmpImmediate (int64_t Imm) const override
	isLegalICmpImmediate - Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructions which can compare a register against the immediate without having to materialize the immediate into a register. More...

bool	isLegalAddImmediate (int64_t Imm) const override
	isLegalAddImmediate - Return true if the specified immediate is legal add immediate, that is the target has add instructions which can add a register and the immediate without having to materialize the immediate into a register. More...

bool	getPreIndexedAddressParts (SDNode *N, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) const override
	getPreIndexedAddressParts - returns true by value, base pointer and offset pointer and addressing mode by reference if the node's address can be legally represented as pre-indexed load / store address. More...

bool	getPostIndexedAddressParts (SDNode N, SDNode Op, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) const override
	getPostIndexedAddressParts - returns true by value, base pointer and offset pointer and addressing mode by reference if this node can be combined with a load / store to form a post-indexed load / store. More...

void	computeKnownBitsForTargetNode (const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth) const override
	Determine which of the bits specified in Mask are known to be either zero or one and return them in the KnownZero/KnownOne bitsets. More...

bool	targetShrinkDemandedConstant (SDValue Op, const APInt &Demanded, TargetLoweringOpt &TLO) const override

bool	ExpandInlineAsm (CallInst *CI) const override
	This hook allows the target to expand an inline asm call to be explicit llvm code if it wants to. More...

ConstraintType	getConstraintType (StringRef Constraint) const override
	getConstraintType - Given a constraint letter, return the type of constraint it is for this target. More...

ConstraintWeight	getSingleConstraintMatchWeight (AsmOperandInfo &info, const char *constraint) const override
	Examine constraint string and operand type and determine a weight value. More...

std::pair< unsigned, const TargetRegisterClass * >	getRegForInlineAsmConstraint (const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
	Given a physical register constraint (e.g. More...

const char *	LowerXConstraint (EVT ConstraintVT) const override
	Try to replace an X constraint, which matches anything, with another that has more specific requirements based on the type of the corresponding operand. More...

void	LowerAsmOperandForConstraint (SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const override
	LowerAsmOperandForConstraint - Lower the specified operand into the Ops vector. More...

unsigned	getInlineAsmMemConstraint (StringRef ConstraintCode) const override

const ARMSubtarget *	getSubtarget () const

const TargetRegisterClass *	getRegClassFor (MVT VT) const override
	getRegClassFor - Return the register class that should be used for the specified value type. More...

bool	isNoopAddrSpaceCast (unsigned SrcAS, unsigned DestAS) const override
	Returns true if a cast between SrcAS and DestAS is a noop. More...

bool	shouldAlignPointerArgs (CallInst *CI, unsigned &MinSize, unsigned &PrefAlign) const override
	Return true if the pointer arguments to CI should be aligned by aligning the object whose address is being passed. More...

FastISel *	createFastISel (FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo) const override
	createFastISel - This method returns a target specific FastISel object, or null if the target does not support "fast" ISel. More...

Sched::Preference	getSchedulingPreference (SDNode *N) const override
	Some scheduler, e.g. More...

bool	isShuffleMaskLegal (ArrayRef< int > M, EVT VT) const override
	isShuffleMaskLegal - Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations, those with specific masks. More...

bool	isOffsetFoldingLegal (const GlobalAddressSDNode *GA) const override
	Return true if folding a constant offset with the given GlobalAddress is legal. More...

bool	isFPImmLegal (const APFloat &Imm, EVT VT) const override
	isFPImmLegal - Returns true if the target can instruction select the specified FP immediate natively. More...

bool	getTgtMemIntrinsic (IntrinsicInfo &Info, const CallInst &I, MachineFunction &MF, unsigned Intrinsic) const override
	getTgtMemIntrinsic - Represent NEON load and store intrinsics as MemIntrinsicNodes. More...

bool	shouldConvertConstantLoadToIntImm (const APInt &Imm, Type *Ty) const override
	Returns true if it is beneficial to convert a load of a constant to just the constant itself. More...

bool	isExtractSubvectorCheap (EVT ResVT, EVT SrcVT, unsigned Index) const override
	Return true if EXTRACT_SUBVECTOR is cheap for this result type with this index. More...

bool	functionArgumentNeedsConsecutiveRegisters (Type *Ty, CallingConv::ID CallConv, bool isVarArg) const override
	Returns true if an argument of type Ty needs to be passed in a contiguous block of registers in calling convention CallConv. More...

unsigned	getExceptionPointerRegister (const Constant *PersonalityFn) const override
	If a physical register, this returns the register that receives the exception address on entry to an EH pad. More...

unsigned	getExceptionSelectorRegister (const Constant *PersonalityFn) const override
	If a physical register, this returns the register that receives the exception typeid on entry to a landing pad. More...

Instruction *	makeDMB (IRBuilder<> &Builder, ARM_MB::MemBOpt Domain) const

Value *	emitLoadLinked (IRBuilder<> &Builder, Value *Addr, AtomicOrdering Ord) const override
	Perform a load-linked operation on Addr, returning a "Value *" with the corresponding pointee type. More...

Value *	emitStoreConditional (IRBuilder<> &Builder, Value Val, Value Addr, AtomicOrdering Ord) const override
	Perform a store-conditional operation to Addr. More...

void	emitAtomicCmpXchgNoStoreLLBalance (IRBuilder<> &Builder) const override

Instruction *	emitLeadingFence (IRBuilder<> &Builder, Instruction *Inst, AtomicOrdering Ord) const override
	Inserts in the IR a target-specific intrinsic specifying a fence. More...

Instruction *	emitTrailingFence (IRBuilder<> &Builder, Instruction *Inst, AtomicOrdering Ord) const override

unsigned	getMaxSupportedInterleaveFactor () const override
	Get the maximum supported factor for interleaved memory accesses. More...

bool	lowerInterleavedLoad (LoadInst LI, ArrayRef< ShuffleVectorInst > Shuffles, ArrayRef< unsigned > Indices, unsigned Factor) const override
	Lower an interleaved load into a vldN intrinsic. More...

bool	lowerInterleavedStore (StoreInst SI, ShuffleVectorInst SVI, unsigned Factor) const override
	Lower an interleaved store into a vstN intrinsic. More...

bool	shouldInsertFencesForAtomic (const Instruction *I) const override
	Whether AtomicExpandPass should automatically insert fences and reduce ordering for this atomic. More...

TargetLoweringBase::AtomicExpansionKind	shouldExpandAtomicLoadInIR (LoadInst *LI) const override
	Returns how the given (atomic) load should be expanded by the IR-level AtomicExpand pass. More...

bool	shouldExpandAtomicStoreInIR (StoreInst *SI) const override
	Returns true if the given (atomic) store should be expanded by the IR-level AtomicExpand pass into an "atomic xchg" which ignores its input. More...

TargetLoweringBase::AtomicExpansionKind	shouldExpandAtomicRMWInIR (AtomicRMWInst *AI) const override
	Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all. More...

TargetLoweringBase::AtomicExpansionKind	shouldExpandAtomicCmpXchgInIR (AtomicCmpXchgInst *AI) const override
	Returns how the given atomic cmpxchg should be expanded by the IR-level AtomicExpand pass. More...

bool	useLoadStackGuardNode () const override
	If this function returns true, SelectionDAGBuilder emits a LOAD_STACK_GUARD node when it is lowering Intrinsic::stackprotector. More...

bool	canCombineStoreAndExtract (Type VectorTy, Value Idx, unsigned &Cost) const override
	Return true if the target can combine store(extractelement VectorTy, Idx). More...

bool	canMergeStoresTo (unsigned AddressSpace, EVT MemVT, const SelectionDAG &DAG) const override
	Returns if it's reasonable to merge stores to MemVT size. More...

bool	isCheapToSpeculateCttz () const override
	Return true if it is cheap to speculate a call to intrinsic cttz. More...

bool	isCheapToSpeculateCtlz () const override
	Return true if it is cheap to speculate a call to intrinsic ctlz. More...

bool	convertSetCCLogicToBitwiseLogic (EVT VT) const override
	Use bitwise logic to make pairs of compares more efficient. More...

bool	supportSwiftError () const override
	Return true if the target supports swifterror attribute. More...

bool	hasStandaloneRem (EVT VT) const override
	Return true if the target can handle a standalone remainder operation. More...

CCAssignFn *	CCAssignFnForCall (CallingConv::ID CC, bool isVarArg) const

CCAssignFn *	CCAssignFnForReturn (CallingConv::ID CC, bool isVarArg) const

bool	isLegalInterleavedAccessType (VectorType *VecTy, const DataLayout &DL) const
	Returns true if `VecTy` is a legal interleaved access type. More...

bool	alignLoopsWithOptSize () const override
	Should loops be aligned even when the function is marked OptSize (but not MinSize). More...

unsigned	getNumInterleavedAccesses (VectorType *VecTy, const DataLayout &DL) const
	Returns the number of interleaved accesses that will be generated when lowering accesses of the given type. More...

void	finalizeLowering (MachineFunction &MF) const override
	Execute target specific actions to finalize target lowering. More...

unsigned	getABIAlignmentForCallingConv (Type *ArgTy, DataLayout DL) const override
	Return the correct alignment for the current calling convention. More...

bool	isDesirableToCommuteWithShift (const SDNode *N, CombineLevel Level) const override
	Return true if it is profitable to move this shift by a constant amount though its operand, adjusting any immediate operands as necessary to preserve semantics. More...

bool	shouldFoldShiftPairToMask (const SDNode *N, CombineLevel Level) const override
	Return true if it is profitable to fold a pair of shifts into a mask. More...

Public Member Functions inherited from llvm::TargetLowering
	TargetLowering (const TargetLowering &)=delete

TargetLowering &	operator= (const TargetLowering &)=delete

	TargetLowering (const TargetMachine &TM)
	NOTE: The TargetMachine owns TLOF. More...

bool	isPositionIndependent () const

virtual bool	isSDNodeSourceOfDivergence (const SDNode N, FunctionLoweringInfo FLI, LegacyDivergenceAnalysis *DA) const

virtual bool	isSDNodeAlwaysUniform (const SDNode *N) const

virtual const MCExpr *	LowerCustomJumpTableEntry (const MachineJumpTableInfo , const MachineBasicBlock , unsigned, MCContext &) const

virtual SDValue	getPICJumpTableRelocBase (SDValue Table, SelectionDAG &DAG) const
	Returns relocation base for the given PIC jumptable. More...

virtual const MCExpr *	getPICJumpTableRelocBaseExpr (const MachineFunction *MF, unsigned JTI, MCContext &Ctx) const
	This returns the relocation base for the given PIC jumptable, the same as getPICJumpTableRelocBase, but as an MCExpr. More...

bool	isInTailCallPosition (SelectionDAG &DAG, SDNode *Node, SDValue &Chain) const
	Check whether a given call node is in tail position within its function. More...

void	softenSetCCOperands (SelectionDAG &DAG, EVT VT, SDValue &NewLHS, SDValue &NewRHS, ISD::CondCode &CCCode, const SDLoc &DL) const
	Soften the operands of a comparison. More...

std::pair< SDValue, SDValue >	makeLibCall (SelectionDAG &DAG, RTLIB::Libcall LC, EVT RetVT, ArrayRef< SDValue > Ops, bool isSigned, const SDLoc &dl, bool doesNotReturn=false, bool isReturnValueUsed=true) const
	Returns a pair of (return value, chain). More...

bool	parametersInCSRMatch (const MachineRegisterInfo &MRI, const uint32_t *CallerPreservedMask, const SmallVectorImpl< CCValAssign > &ArgLocs, const SmallVectorImpl< SDValue > &OutVals) const
	Check whether parameters to a call that are passed in callee saved registers are the same as from the calling function. More...

bool	ShrinkDemandedConstant (SDValue Op, const APInt &Demanded, TargetLoweringOpt &TLO) const
	Check to see if the specified operand of the specified instruction is a constant integer. More...

bool	ShrinkDemandedOp (SDValue Op, unsigned BitWidth, const APInt &Demanded, TargetLoweringOpt &TLO) const
	Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the casts are free. More...

bool	SimplifyDemandedBits (SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, KnownBits &Known, TargetLoweringOpt &TLO, unsigned Depth=0, bool AssumeSingleUse=false) const
	Look at Op. More...

bool	SimplifyDemandedBits (SDValue Op, const APInt &DemandedBits, KnownBits &Known, TargetLoweringOpt &TLO, unsigned Depth=0, bool AssumeSingleUse=false) const
	Helper wrapper around SimplifyDemandedBits, demanding all elements. More...

bool	SimplifyDemandedBits (SDValue Op, const APInt &DemandedMask, DAGCombinerInfo &DCI) const
	Helper wrapper around SimplifyDemandedBits. More...

bool	SimplifyDemandedVectorElts (SDValue Op, const APInt &DemandedEltMask, APInt &KnownUndef, APInt &KnownZero, TargetLoweringOpt &TLO, unsigned Depth=0, bool AssumeSingleUse=false) const
	Look at Vector Op. More...

bool	SimplifyDemandedVectorElts (SDValue Op, const APInt &DemandedElts, APInt &KnownUndef, APInt &KnownZero, DAGCombinerInfo &DCI) const
	Helper wrapper around SimplifyDemandedVectorElts. More...

virtual void	computeKnownBitsForFrameIndex (const SDValue FIOp, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth=0) const
	Determine which of the bits of FrameIndex `FIOp` are known to be 0. More...

virtual unsigned	ComputeNumSignBitsForTargetNode (SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth=0) const
	This method can be implemented by targets that want to expose additional information about sign bits to the DAG Combiner. More...

virtual bool	SimplifyDemandedVectorEltsForTargetNode (SDValue Op, const APInt &DemandedElts, APInt &KnownUndef, APInt &KnownZero, TargetLoweringOpt &TLO, unsigned Depth=0) const
	Attempt to simplify any target nodes based on the demanded vector elements, returning true on success. More...

virtual bool	SimplifyDemandedBitsForTargetNode (SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, KnownBits &Known, TargetLoweringOpt &TLO, unsigned Depth=0) const
	Attempt to simplify any target nodes based on the demanded bits/elts, returning true on success. More...

virtual bool	isKnownNeverNaNForTargetNode (SDValue Op, const SelectionDAG &DAG, bool SNaN=false, unsigned Depth=0) const
	If `SNaN` is false,. More...

bool	isConstTrueVal (const SDNode *N) const
	Return if the N is a constant or constant vector equal to the true value from getBooleanContents(). More...

bool	isConstFalseVal (const SDNode *N) const
	Return if the N is a constant or constant vector equal to the false value from getBooleanContents(). More...

bool	isExtendedTrueVal (const ConstantSDNode *N, EVT VT, bool SExt) const
	Return if `N` is a True value when extended to `VT`. More...

SDValue	SimplifySetCC (EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, bool foldBooleans, DAGCombinerInfo &DCI, const SDLoc &dl) const
	Try to simplify a setcc built with the specified operands and cc. More...

virtual SDValue	unwrapAddress (SDValue N) const

virtual bool	isGAPlusOffset (SDNode N, const GlobalValue &GA, int64_t &Offset) const
	Returns true (and the GlobalValue and the offset) if the node is a GlobalAddress + offset. More...

virtual bool	isDesirableToCombineBuildVectorToShuffleTruncate (ArrayRef< int > ShuffleMask, EVT SrcVT, EVT TruncVT) const

virtual bool	isTypeDesirableForOp (unsigned, EVT VT) const
	Return true if the target has native support for the specified value type and it is 'desirable' to use the type for the given node type. More...

virtual bool	IsDesirableToPromoteOp (SDValue, EVT &) const
	This method query the target whether it is beneficial for dag combiner to promote the specified node. More...

std::pair< SDValue, SDValue >	LowerCallTo (CallLoweringInfo &CLI) const
	This function lowers an abstract call to a function into an actual call. More...

virtual const char *	getClearCacheBuiltinName () const
	Return the builtin name for the __builtin___clear_cache intrinsic Default is to invoke the clear cache library call. More...

virtual EVT	getTypeForExtReturn (LLVMContext &Context, EVT VT, ISD::NodeType) const
	Return the type that should be used to zero or sign extend a zeroext/signext integer return value. More...

virtual const MCPhysReg *	getScratchRegisters (CallingConv::ID CC) const
	Returns a 0 terminated array of registers that can be safely used as scratch registers. More...

virtual SDValue	prepareVolatileOrAtomicLoad (SDValue Chain, const SDLoc &DL, SelectionDAG &DAG) const
	This callback is used to prepare for a volatile or atomic load. More...

virtual MachineMemOperand::Flags	getMMOFlags (const Instruction &I) const
	This callback is used to inspect load/store instructions and add target-specific MachineMemOperand flags to them. More...

virtual void	LowerOperationWrapper (SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const
	This callback is invoked by the type legalizer to legalize nodes with an illegal operand type but legal result types. More...

bool	verifyReturnAddressArgumentIsConstant (SDValue Op, SelectionDAG &DAG) const

virtual AsmOperandInfoVector	ParseConstraints (const DataLayout &DL, const TargetRegisterInfo *TRI, ImmutableCallSite CS) const
	Split up the constraint string from the inline assembly value into the specific constraints and their prefixes, and also tie in the associated operand values. More...

virtual ConstraintWeight	getMultipleConstraintMatchWeight (AsmOperandInfo &info, int maIndex) const
	Examine constraint type and operand type and determine a weight value. More...

virtual void	ComputeConstraintToUse (AsmOperandInfo &OpInfo, SDValue Op, SelectionDAG *DAG=nullptr) const
	Determines the constraint code and constraint type to use for the specific AsmOperandInfo, setting OpInfo.ConstraintCode and OpInfo.ConstraintType. More...

SDValue	BuildSDIV (SDNode N, SelectionDAG &DAG, bool IsAfterLegalization, SmallVectorImpl< SDNode > &Created) const
	Given an ISD::SDIV node expressing a divide by constant, return a DAG expression to select that will generate the same value by multiplying by a magic number. More...

SDValue	BuildUDIV (SDNode N, SelectionDAG &DAG, bool IsAfterLegalization, SmallVectorImpl< SDNode > &Created) const
	Given an ISD::UDIV node expressing a divide by constant, return a DAG expression to select that will generate the same value by multiplying by a magic number. More...

virtual unsigned	combineRepeatedFPDivisors () const
	Indicate whether this target prefers to combine FDIVs with the same divisor. More...

virtual SDValue	getSqrtEstimate (SDValue Operand, SelectionDAG &DAG, int Enabled, int &RefinementSteps, bool &UseOneConstNR, bool Reciprocal) const
	Hooks for building estimates in place of slower divisions and square roots. More...

virtual SDValue	getRecipEstimate (SDValue Operand, SelectionDAG &DAG, int Enabled, int &RefinementSteps) const
	Return a reciprocal estimate value for the input operand. More...

bool	expandMUL_LOHI (unsigned Opcode, EVT VT, SDLoc dl, SDValue LHS, SDValue RHS, SmallVectorImpl< SDValue > &Result, EVT HiLoVT, SelectionDAG &DAG, MulExpansionKind Kind, SDValue LL=SDValue(), SDValue LH=SDValue(), SDValue RL=SDValue(), SDValue RH=SDValue()) const
	Expand a MUL or [US]MUL_LOHI of n-bit values into two or four nodes, respectively, each computing an n/2-bit part of the result. More...

bool	expandMUL (SDNode *N, SDValue &Lo, SDValue &Hi, EVT HiLoVT, SelectionDAG &DAG, MulExpansionKind Kind, SDValue LL=SDValue(), SDValue LH=SDValue(), SDValue RL=SDValue(), SDValue RH=SDValue()) const
	Expand a MUL into two nodes. More...

bool	expandFunnelShift (SDNode *N, SDValue &Result, SelectionDAG &DAG) const
	Expand funnel shift. More...

bool	expandROT (SDNode *N, SDValue &Result, SelectionDAG &DAG) const
	Expand rotations. More...

bool	expandFP_TO_SINT (SDNode *N, SDValue &Result, SelectionDAG &DAG) const
	Expand float(f32) to SINT(i64) conversion. More...

bool	expandFP_TO_UINT (SDNode *N, SDValue &Result, SelectionDAG &DAG) const
	Expand float to UINT conversion. More...

bool	expandUINT_TO_FP (SDNode *N, SDValue &Result, SelectionDAG &DAG) const
	Expand UINT(i64) to double(f64) conversion. More...

SDValue	expandFMINNUM_FMAXNUM (SDNode *N, SelectionDAG &DAG) const
	Expand fminnum/fmaxnum into fminnum_ieee/fmaxnum_ieee with quieted inputs. More...

bool	expandCTPOP (SDNode *N, SDValue &Result, SelectionDAG &DAG) const
	Expand CTPOP nodes. More...

bool	expandCTLZ (SDNode *N, SDValue &Result, SelectionDAG &DAG) const
	Expand CTLZ/CTLZ_ZERO_UNDEF nodes. More...

bool	expandCTTZ (SDNode *N, SDValue &Result, SelectionDAG &DAG) const
	Expand CTTZ/CTTZ_ZERO_UNDEF nodes. More...

bool	expandABS (SDNode *N, SDValue &Result, SelectionDAG &DAG) const
	Expand ABS nodes. More...

SDValue	scalarizeVectorLoad (LoadSDNode *LD, SelectionDAG &DAG) const
	Turn load of vector type into a load of the individual elements. More...

SDValue	scalarizeVectorStore (StoreSDNode *ST, SelectionDAG &DAG) const

std::pair< SDValue, SDValue >	expandUnalignedLoad (LoadSDNode *LD, SelectionDAG &DAG) const
	Expands an unaligned load to 2 half-size loads for an integer, and possibly more for vectors. More...

SDValue	expandUnalignedStore (StoreSDNode *ST, SelectionDAG &DAG) const
	Expands an unaligned store to 2 half-size stores for integer values, and possibly more for vectors. More...

SDValue	IncrementMemoryAddress (SDValue Addr, SDValue Mask, const SDLoc &DL, EVT DataVT, SelectionDAG &DAG, bool IsCompressedMemory) const
	Increments memory address `Addr` according to the type of the value `DataVT` that should be stored. More...

SDValue	getVectorElementPointer (SelectionDAG &DAG, SDValue VecPtr, EVT VecVT, SDValue Index) const
	Get a pointer to vector element `Idx` located in memory for a vector of type `VecVT` starting at a base address of `VecPtr`. More...

SDValue	expandAddSubSat (SDNode *Node, SelectionDAG &DAG) const
	Method for building the DAG expansion of ISD::[US][ADD\|SUB]SAT. More...

SDValue	getExpandedFixedPointMultiplication (SDNode *Node, SelectionDAG &DAG) const
	Method for building the DAG expansion of ISD::SMULFIX. More...

virtual SDValue	emitStackGuardXorFP (SelectionDAG &DAG, SDValue Val, const SDLoc &DL) const

virtual SDValue	LowerToTLSEmulatedModel (const GlobalAddressSDNode *GA, SelectionDAG &DAG) const
	Lower TLS global address SDNode for target independent emulated TLS model. More...

virtual SDValue	expandIndirectJTBranch (const SDLoc &dl, SDValue Value, SDValue Addr, SelectionDAG &DAG) const
	Expands target specific indirect branch for the case of JumpTable expanasion. More...

SDValue	lowerCmpEqZeroToCtlzSrl (SDValue Op, SelectionDAG &DAG) const

Public Member Functions inherited from llvm::TargetLoweringBase
virtual void	markLibCallAttributes (MachineFunction *MF, unsigned CC, ArgListTy &Args) const

	TargetLoweringBase (const TargetMachine &TM)
	NOTE: The TargetMachine owns TLOF. More...

	TargetLoweringBase (const TargetLoweringBase &)=delete

TargetLoweringBase &	operator= (const TargetLoweringBase &)=delete

virtual	~TargetLoweringBase ()=default

const TargetMachine &	getTargetMachine () const

MVT	getPointerTy (const DataLayout &DL, uint32_t AS=0) const
	Return the pointer type for the given address space, defaults to the pointer type from the data layout. More...

MVT	getFrameIndexTy (const DataLayout &DL) const
	Return the type for frame index, which is determined by the alloca address space specified through the data layout. More...

virtual MVT	getFenceOperandTy (const DataLayout &DL) const
	Return the type for operands of fence. More...

virtual MVT	getScalarShiftAmountTy (const DataLayout &, EVT) const
	EVT is not used in-tree, but is used by out-of-tree target. More...

EVT	getShiftAmountTy (EVT LHSTy, const DataLayout &DL, bool LegalTypes=true) const

virtual MVT	getVectorIdxTy (const DataLayout &DL) const
	Returns the type to be used for the index operand of: ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT, ISD::INSERT_SUBVECTOR, and ISD::EXTRACT_SUBVECTOR. More...

virtual bool	reduceSelectOfFPConstantLoads (bool IsFPSetCC) const
	Return true if it is profitable to convert a select of FP constants into a constant pool load whose address depends on the select condition. More...

bool	hasMultipleConditionRegisters () const
	Return true if multiple condition registers are available. More...

bool	hasExtractBitsInsn () const
	Return true if the target has BitExtract instructions. More...

virtual TargetLoweringBase::LegalizeTypeAction	getPreferredVectorAction (MVT VT) const
	Return the preferred vector type legalization action. More...

virtual bool	shouldExpandBuildVectorWithShuffles (EVT, unsigned DefinedValues) const

virtual bool	isIntDivCheap (EVT VT, AttributeList Attr) const
	Return true if integer divide is usually cheaper than a sequence of several shifts, adds, and multiplies for this target. More...

virtual bool	isFsqrtCheap (SDValue X, SelectionDAG &DAG) const
	Return true if SQRT(X) shouldn't be replaced with X*RSQRT(X). More...

int	getRecipEstimateSqrtEnabled (EVT VT, MachineFunction &MF) const
	Return a ReciprocalEstimate enum value for a square root of the given type based on the function's attributes. More...

int	getRecipEstimateDivEnabled (EVT VT, MachineFunction &MF) const
	Return a ReciprocalEstimate enum value for a division of the given type based on the function's attributes. More...

int	getSqrtRefinementSteps (EVT VT, MachineFunction &MF) const
	Return the refinement step count for a square root of the given type based on the function's attributes. More...

int	getDivRefinementSteps (EVT VT, MachineFunction &MF) const
	Return the refinement step count for a division of the given type based on the function's attributes. More...

bool	isSlowDivBypassed () const
	Returns true if target has indicated at least one type should be bypassed. More...

const DenseMap< unsigned int, unsigned int > &	getBypassSlowDivWidths () const
	Returns map of slow types for division or remainder with corresponding fast types. More...

bool	isJumpExpensive () const
	Return true if Flow Control is an expensive operation that should be avoided. More...

bool	isPredictableSelectExpensive () const
	Return true if selects are only cheaper than branches if the branch is unlikely to be predicted right. More...

virtual BranchProbability	getPredictableBranchThreshold () const
	If a branch or a select condition is skewed in one direction by more than this factor, it is very likely to be predicted correctly. More...

virtual bool	isLoadBitCastBeneficial (EVT LoadVT, EVT BitcastVT) const
	Return true if the following transform is beneficial: fold (conv (load x)) -> (load (conv*)x) On architectures that don't natively support some vector loads efficiently, casting the load to a smaller vector of larger types and loading is more efficient, however, this can be undone by optimizations in dag combiner. More...

virtual bool	isStoreBitCastBeneficial (EVT StoreVT, EVT BitcastVT) const
	Return true if the following transform is beneficial: (store (y (conv x)), y)) -> (store x, (x)) More...

virtual bool	storeOfVectorConstantIsCheap (EVT MemVT, unsigned NumElem, unsigned AddrSpace) const
	Return true if it is expected to be cheaper to do a store of a non-zero vector constant with the given size and type for the address space than to store the individual scalar element constants. More...

virtual bool	mergeStoresAfterLegalization () const
	Allow store merging after legalization in addition to before legalization. More...

virtual bool	isCtlzFast () const
	Return true if ctlz instruction is fast. More...

virtual bool	hasBitPreservingFPLogic (EVT VT) const
	Return true if it is safe to transform an integer-domain bitwise operation into the equivalent floating-point operation. More...

virtual bool	isMultiStoresCheaperThanBitsMerge (EVT LTy, EVT HTy) const
	Return true if it is cheaper to split the store of a merged int val from a pair of smaller values into multiple stores. More...

virtual bool	isMaskAndCmp0FoldingBeneficial (const Instruction &AndI) const
	Return if the target supports combining a chain like: More...

virtual MVT	hasFastEqualityCompare (unsigned NumBits) const
	Return the preferred operand type if the target has a quick way to compare integer values of the given size. More...

virtual bool	hasAndNotCompare (SDValue Y) const
	Return true if the target should transform: (X & Y) == Y —> (~X & Y) == 0 (X & Y) != Y —> (~X & Y) != 0. More...

virtual bool	hasAndNot (SDValue X) const
	Return true if the target has a bitwise and-not operation: X = ~A & B This can be used to simplify select or other instructions. More...

virtual bool	preferShiftsToClearExtremeBits (SDValue X) const
	There are two ways to clear extreme bits (either low or high): Mask: x & (-1 << y) (the instcombine canonical form) Shifts: x >> y << y Return true if the variant with 2 shifts is preferred. More...

virtual bool	shouldTransformSignedTruncationCheck (EVT XVT, unsigned KeptBits) const
	Should we tranform the IR-optimal check for whether given truncation down into KeptBits would be truncating or not: (add x, (1 << (KeptBits-1))) srccond (1 << KeptBits) Into it's more traditional form: ((x << C) a>> C) dstcond x Return true if we should transform. More...

bool	enableExtLdPromotion () const
	Return true if the target wants to use the optimization that turns ext(promotableInst1(...(promotableInstN(load)))) into promotedInst1(...(promotedInstN(ext(load)))). More...

virtual bool	shouldSplatInsEltVarIndex (EVT) const
	Return true if inserting a scalar into a variable element of an undef vector is more efficiently handled by splatting the scalar instead. More...

bool	hasFloatingPointExceptions () const
	Return true if target supports floating point exceptions. More...

virtual bool	enableAggressiveFMAFusion (EVT VT) const
	Return true if target always beneficiates from combining into FMA for a given value type. More...

virtual MVT::SimpleValueType	getCmpLibcallReturnType () const
	Return the ValueType for comparison libcalls. More...

BooleanContent	getBooleanContents (bool isVec, bool isFloat) const
	For targets without i1 registers, this gives the nature of the high-bits of boolean values held in types wider than i1. More...

BooleanContent	getBooleanContents (EVT Type) const

Sched::Preference	getSchedulingPreference () const
	Return target scheduling preference. More...

virtual const TargetRegisterClass *	getRepRegClassFor (MVT VT) const
	Return the 'representative' register class for the specified value type. More...

virtual uint8_t	getRepRegClassCostFor (MVT VT) const
	Return the cost of the 'representative' register class for the specified value type. More...

bool	isTypeLegal (EVT VT) const
	Return true if the target has native support for the specified value type. More...

const ValueTypeActionImpl &	getValueTypeActions () const

LegalizeTypeAction	getTypeAction (LLVMContext &Context, EVT VT) const
	Return how we should legalize values of this type, either it is already legal (return 'Legal') or we need to promote it to a larger type (return 'Promote'), or we need to expand it into multiple registers of smaller integer type (return 'Expand'). More...

LegalizeTypeAction	getTypeAction (MVT VT) const

EVT	getTypeToTransformTo (LLVMContext &Context, EVT VT) const
	For types supported by the target, this is an identity function. More...

EVT	getTypeToExpandTo (LLVMContext &Context, EVT VT) const
	For types supported by the target, this is an identity function. More...

unsigned	getVectorTypeBreakdown (LLVMContext &Context, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const
	Vector types are broken down into some number of legal first class types. More...

virtual unsigned	getVectorTypeBreakdownForCallingConv (LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const
	Certain targets such as MIPS require that some types such as vectors are always broken down into scalars in some contexts. More...

virtual bool	canOpTrap (unsigned Op, EVT VT) const
	Returns true if the operation can trap for the value type. More...

virtual bool	isVectorClearMaskLegal (ArrayRef< int >, EVT) const
	Similar to isShuffleMaskLegal. More...

LegalizeAction	getOperationAction (unsigned Op, EVT VT) const
	Return how this operation should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it. More...

virtual bool	isSupportedFixedPointOperation (unsigned Op, EVT VT, unsigned Scale) const
	Custom method defined by each target to indicate if an operation which may require a scale is supported natively by the target. More...

LegalizeAction	getFixedPointOperationAction (unsigned Op, EVT VT, unsigned Scale) const
	Some fixed point operations may be natively supported by the target but only for specific scales. More...

LegalizeAction	getStrictFPOperationAction (unsigned Op, EVT VT) const

bool	isOperationLegalOrCustom (unsigned Op, EVT VT) const
	Return true if the specified operation is legal on this target or can be made legal with custom lowering. More...

bool	isOperationLegalOrPromote (unsigned Op, EVT VT) const
	Return true if the specified operation is legal on this target or can be made legal using promotion. More...

bool	isOperationLegalOrCustomOrPromote (unsigned Op, EVT VT) const
	Return true if the specified operation is legal on this target or can be made legal with custom lowering or using promotion. More...

bool	isOperationCustom (unsigned Op, EVT VT) const
	Return true if the operation uses custom lowering, regardless of whether the type is legal or not. More...

virtual bool	areJTsAllowed (const Function *Fn) const
	Return true if lowering to a jump table is allowed. More...

bool	rangeFitsInWord (const APInt &Low, const APInt &High, const DataLayout &DL) const
	Check whether the range [Low,High] fits in a machine word. More...

virtual bool	isSuitableForJumpTable (const SwitchInst *SI, uint64_t NumCases, uint64_t Range) const
	Return true if lowering to a jump table is suitable for a set of case clusters which may contain `NumCases` cases, `Range` range of values. More...

bool	isSuitableForBitTests (unsigned NumDests, unsigned NumCmps, const APInt &Low, const APInt &High, const DataLayout &DL) const
	Return true if lowering to a bit test is suitable for a set of case clusters which contains `NumDests` unique destinations, `Low` and `High` as its lowest and highest case values, and expects `NumCmps` case value comparisons. More...

bool	isOperationExpand (unsigned Op, EVT VT) const
	Return true if the specified operation is illegal on this target or unlikely to be made legal with custom lowering. More...

bool	isOperationLegal (unsigned Op, EVT VT) const
	Return true if the specified operation is legal on this target. More...

LegalizeAction	getLoadExtAction (unsigned ExtType, EVT ValVT, EVT MemVT) const
	Return how this load with extension should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it. More...

bool	isLoadExtLegal (unsigned ExtType, EVT ValVT, EVT MemVT) const
	Return true if the specified load with extension is legal on this target. More...

bool	isLoadExtLegalOrCustom (unsigned ExtType, EVT ValVT, EVT MemVT) const
	Return true if the specified load with extension is legal or custom on this target. More...

LegalizeAction	getTruncStoreAction (EVT ValVT, EVT MemVT) const
	Return how this store with truncation should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it. More...

bool	isTruncStoreLegal (EVT ValVT, EVT MemVT) const
	Return true if the specified store with truncation is legal on this target. More...

bool	isTruncStoreLegalOrCustom (EVT ValVT, EVT MemVT) const
	Return true if the specified store with truncation has solution on this target. More...

LegalizeAction	getIndexedLoadAction (unsigned IdxMode, MVT VT) const
	Return how the indexed load should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it. More...

bool	isIndexedLoadLegal (unsigned IdxMode, EVT VT) const
	Return true if the specified indexed load is legal on this target. More...

LegalizeAction	getIndexedStoreAction (unsigned IdxMode, MVT VT) const
	Return how the indexed store should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it. More...

bool	isIndexedStoreLegal (unsigned IdxMode, EVT VT) const
	Return true if the specified indexed load is legal on this target. More...

LegalizeAction	getCondCodeAction (ISD::CondCode CC, MVT VT) const
	Return how the condition code should be treated: either it is legal, needs to be expanded to some other code sequence, or the target has a custom expander for it. More...

bool	isCondCodeLegal (ISD::CondCode CC, MVT VT) const
	Return true if the specified condition code is legal on this target. More...

bool	isCondCodeLegalOrCustom (ISD::CondCode CC, MVT VT) const
	Return true if the specified condition code is legal or custom on this target. More...

MVT	getTypeToPromoteTo (unsigned Op, MVT VT) const
	If the action for this operation is to promote, this method returns the ValueType to promote to. More...

EVT	getValueType (const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const
	Return the EVT corresponding to this LLVM type. More...

MVT	getSimpleValueType (const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const
	Return the MVT corresponding to this LLVM type. See getValueType. More...

virtual unsigned	getByValTypeAlignment (Type *Ty, const DataLayout &DL) const
	Return the desired alignment for ByVal or InAlloca aggregate function arguments in the caller parameter area. More...

MVT	getRegisterType (MVT VT) const
	Return the type of registers that this ValueType will eventually require. More...

MVT	getRegisterType (LLVMContext &Context, EVT VT) const
	Return the type of registers that this ValueType will eventually require. More...

unsigned	getNumRegisters (LLVMContext &Context, EVT VT) const
	Return the number of registers that this ValueType will eventually require. More...

virtual MVT	getRegisterTypeForCallingConv (LLVMContext &Context, CallingConv::ID CC, EVT VT) const
	Certain combinations of ABIs, Targets and features require that types are legal for some operations and not for other operations. More...

virtual unsigned	getNumRegistersForCallingConv (LLVMContext &Context, CallingConv::ID CC, EVT VT) const
	Certain targets require unusual breakdowns of certain types. More...

virtual bool	ShouldShrinkFPConstant (EVT) const
	If true, then instruction selection should seek to shrink the FP constant of the specified type to a smaller type in order to save space and / or reduce runtime. More...

virtual bool	shouldReduceLoadWidth (SDNode *Load, ISD::LoadExtType ExtTy, EVT NewVT) const
	Return true if it is profitable to reduce a load to a smaller type. More...

bool	hasBigEndianPartOrdering (EVT VT, const DataLayout &DL) const
	When splitting a value of the specified type into parts, does the Lo or Hi part come first? This usually follows the endianness, except for ppcf128, where the Hi part always comes first. More...

bool	hasTargetDAGCombine (ISD::NodeType NT) const
	If true, the target has custom DAG combine transformations that it can perform for the specified node. More...

unsigned	getGatherAllAliasesMaxDepth () const

virtual unsigned	getVaListSizeInBits (const DataLayout &DL) const
	Returns the size of the platform's va_list object. More...

unsigned	getMaxStoresPerMemset (bool OptSize) const
	Get maximum # of store operations permitted for llvm.memset. More...

unsigned	getMaxStoresPerMemcpy (bool OptSize) const
	Get maximum # of store operations permitted for llvm.memcpy. More...

virtual unsigned	getMaxGluedStoresPerMemcpy () const
	Get maximum # of store operations to be glued together. More...

unsigned	getMaxExpandSizeMemcmp (bool OptSize) const
	Get maximum # of load operations permitted for memcmp. More...

virtual unsigned	getMemcmpEqZeroLoadsPerBlock () const
	For memcmp expansion when the memcmp result is only compared equal or not-equal to 0, allow up to this number of load pairs per block. More...

unsigned	getMaxStoresPerMemmove (bool OptSize) const
	Get maximum # of store operations permitted for llvm.memmove. More...

bool	allowsMemoryAccess (LLVMContext &Context, const DataLayout &DL, EVT VT, unsigned AddrSpace=0, unsigned Alignment=1, bool *Fast=nullptr) const
	Return true if the target supports a memory access of this type for the given address space and alignment. More...

virtual bool	isSafeMemOpType (MVT) const
	Returns true if it's safe to use load / store of the specified type to expand memcpy / memset inline. More...

bool	usesUnderscoreSetJmp () const
	Determine if we should use _setjmp or setjmp to implement llvm.setjmp. More...

bool	usesUnderscoreLongJmp () const
	Determine if we should use _longjmp or longjmp to implement llvm.longjmp. More...

virtual unsigned	getMinimumJumpTableEntries () const
	Return lower limit for number of blocks in a jump table. More...

unsigned	getMinimumJumpTableDensity (bool OptForSize) const
	Return lower limit of the density in a jump table. More...

unsigned	getMaximumJumpTableSize () const
	Return upper limit for number of entries in a jump table. More...

virtual bool	isJumpTableRelative () const

unsigned	getStackPointerRegisterToSaveRestore () const
	If a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save and restore. More...

virtual bool	needsFixedCatchObjects () const

unsigned	getJumpBufSize () const
	Returns the target's jmp_buf size in bytes (if never set, the default is 200) More...

unsigned	getJumpBufAlignment () const
	Returns the target's jmp_buf alignment in bytes (if never set, the default is 0) More...

unsigned	getMinStackArgumentAlignment () const
	Return the minimum stack alignment of an argument. More...

unsigned	getMinFunctionAlignment () const
	Return the minimum function alignment. More...

unsigned	getPrefFunctionAlignment () const
	Return the preferred function alignment. More...

virtual unsigned	getPrefLoopAlignment (MachineLoop *ML=nullptr) const
	Return the preferred loop alignment. More...

virtual Value *	getIRStackGuard (IRBuilder<> &IRB) const
	If the target has a standard location for the stack protector guard, returns the address of that location. More...

virtual void	insertSSPDeclarations (Module &M) const
	Inserts necessary declarations for SSP (stack protection) purpose. More...

virtual Value *	getSDagStackGuard (const Module &M) const
	Return the variable that's previously inserted by insertSSPDeclarations, if any, otherwise return nullptr. More...

virtual bool	useStackGuardXorFP () const
	If this function returns true, stack protection checks should XOR the frame pointer (or whichever pointer is used to address locals) into the stack guard value before checking it. More...

virtual Value *	getSSPStackGuardCheck (const Module &M) const
	If the target has a standard stack protection check function that performs validation and error handling, returns the function. More...

virtual Value *	getSafeStackPointerLocation (IRBuilder<> &IRB) const
	Returns the target-specific address of the unsafe stack pointer. More...

virtual StringRef	getStackProbeSymbolName (MachineFunction &MF) const
	Returns the name of the symbol used to emit stack probes or the empty string if not applicable. More...

virtual bool	isCheapAddrSpaceCast (unsigned SrcAS, unsigned DestAS) const
	Returns true if a cast from SrcAS to DestAS is "cheap", such that e.g. More...

virtual bool	shouldSignExtendTypeInLibCall (EVT Type, bool IsSigned) const
	Returns true if arguments should be sign-extended in lib calls. More...

virtual LoadInst *	lowerIdempotentRMWIntoFencedLoad (AtomicRMWInst *RMWI) const
	On some platforms, an AtomicRMW that never actually modifies the value (such as fetch_add of 0) can be turned into a fence followed by an atomic load. More...

virtual ISD::NodeType	getExtendForAtomicOps () const
	Returns how the platform's atomic operations are extended (ZERO_EXTEND, SIGN_EXTEND, or ANY_EXTEND). More...

virtual bool	shouldNormalizeToSelectSequence (LLVMContext &Context, EVT VT) const
	Returns true if we should normalize select(N0&N1, X, Y) => select(N0, select(N1, X, Y), Y) and select(N0\|N1, X, Y) => select(N0, select(N1, X, Y, Y)) if it is likely that it saves us from materializing N0 and N1 in an integer register. More...

virtual bool	convertSelectOfConstantsToMath (EVT VT) const
	Return true if a select of constants (select Cond, C1, C2) should be transformed into simple math ops with the condition value. More...

virtual bool	decomposeMulByConstant (EVT VT, SDValue C) const
	Return true if it is profitable to transform an integer multiplication-by-constant into simpler operations like shifts and adds. More...

virtual bool	shouldUseStrictFP_TO_INT (EVT FpVT, EVT IntVT, bool IsSigned) const
	Return true if it is more correct/profitable to use strict FP_TO_INT conversion operations - canonicalizing the FP source value instead of converting all cases and then selecting based on value. More...

virtual bool	getAddrModeArguments (IntrinsicInst , SmallVectorImpl< Value > &, Type *&) const
	CodeGenPrepare sinks address calculations into the same BB as Load/Store instructions reading the address. More...

virtual bool	isLegalStoreImmediate (int64_t Value) const
	Return true if the specified immediate is legal for the value input of a store instruction. More...

virtual bool	isVectorShiftByScalarCheap (Type *Ty) const
	Return true if it's significantly cheaper to shift a vector by a uniform scalar than by an amount which will vary across each lane. More...

virtual bool	isCommutativeBinOp (unsigned Opcode) const
	Returns true if the opcode is a commutative binary operation. More...

virtual bool	isProfitableToHoist (Instruction *I) const

bool	isExtFree (const Instruction *I) const
	Return true if the extension represented by `I` is free. More...

bool	isExtLoad (const LoadInst Load, const Instruction Ext, const DataLayout &DL) const
	Return true if `Load` and `Ext` can form an ExtLoad. More...

virtual bool	isZExtFree (Type FromTy, Type ToTy) const
	Return true if any actual instruction that defines a value of type FromTy implicitly zero-extends the value to ToTy in the result register. More...

virtual bool	isZExtFree (EVT FromTy, EVT ToTy) const

virtual bool	isSExtCheaperThanZExt (EVT FromTy, EVT ToTy) const
	Return true if sign-extension from FromTy to ToTy is cheaper than zero-extension. More...

virtual bool	hasPairedLoad (EVT, unsigned &) const
	Return true if the target supplies and combines to a paired load two loaded values of type LoadedType next to each other in memory. More...

virtual bool	hasVectorBlend () const
	Return true if the target has a vector blend instruction. More...

virtual bool	isFPExtFree (EVT DestVT, EVT SrcVT) const
	Return true if an fpext operation is free (for instance, because single-precision floating-point numbers are implicitly extended to double-precision). More...

virtual bool	isFPExtFoldable (unsigned Opcode, EVT DestVT, EVT SrcVT) const
	Return true if an fpext operation input to an `Opcode` operation is free (for instance, because half-precision floating-point numbers are implicitly extended to float-precision) for an FMA instruction. More...

virtual bool	isFAbsFree (EVT VT) const
	Return true if an fabs operation is free to the point where it is never worthwhile to replace it with a bitwise operation. More...

virtual bool	isNarrowingProfitable (EVT, EVT) const
	Return true if it's profitable to narrow operations of type VT1 to VT2. More...

virtual bool	shouldScalarizeBinop (SDValue VecOp) const
	Try to convert an extract element of a vector binary operation into an extract element followed by a scalar operation. More...

virtual bool	aggressivelyPreferBuildVectorSources (EVT VecVT) const

void	setLibcallName (RTLIB::Libcall Call, const char *Name)
	Rename the default libcall routine name for the specified libcall. More...

const char *	getLibcallName (RTLIB::Libcall Call) const
	Get the libcall routine name for the specified libcall. More...

void	setCmpLibcallCC (RTLIB::Libcall Call, ISD::CondCode CC)
	Override the default CondCode to be used to test the result of the comparison libcall against zero. More...

ISD::CondCode	getCmpLibcallCC (RTLIB::Libcall Call) const
	Get the CondCode that's to be used to test the result of the comparison libcall against zero. More...

void	setLibcallCallingConv (RTLIB::Libcall Call, CallingConv::ID CC)
	Set the CallingConv that should be used for the specified libcall. More...

CallingConv::ID	getLibcallCallingConv (RTLIB::Libcall Call) const
	Get the CallingConv that should be used for the specified libcall. More...

int	InstructionOpcodeToISD (unsigned Opcode) const
	Get the ISD node that corresponds to the Instruction class opcode. More...

std::pair< int, MVT >	getTypeLegalizationCost (const DataLayout &DL, Type *Ty) const
	Estimate the cost of type-legalization and the legalized type. More...

unsigned	getMaxAtomicSizeInBitsSupported () const
	Returns the maximum atomic operation size (in bits) supported by the backend. More...

unsigned	getMinCmpXchgSizeInBits () const
	Returns the size of the smallest cmpxchg or ll/sc instruction the backend supports. More...

bool	supportsUnalignedAtomics () const
	Whether the target supports unaligned atomic operations. More...

virtual Value *	emitMaskedAtomicRMWIntrinsic (IRBuilder<> &Builder, AtomicRMWInst AI, Value AlignedAddr, Value Incr, Value Mask, Value *ShiftAmt, AtomicOrdering Ord) const
	Perform a masked atomicrmw using a target-specific intrinsic. More...

virtual Value *	emitMaskedAtomicCmpXchgIntrinsic (IRBuilder<> &Builder, AtomicCmpXchgInst CI, Value AlignedAddr, Value CmpVal, Value NewVal, Value *Mask, AtomicOrdering Ord) const
	Perform a masked cmpxchg using a target-specific intrinsic. More...

Protected Member Functions
std::pair< const TargetRegisterClass *, uint8_t >	findRepresentativeClass (const TargetRegisterInfo *TRI, MVT VT) const override
	Return the largest legal super-reg register class of the register class for the specified type and its associated "cost". More...

Protected Member Functions inherited from llvm::TargetLoweringBase
void	initActions ()
	Initialize all of the actions to default values. More...

Value *	getDefaultSafeStackPointerLocation (IRBuilder<> &IRB, bool UseTLS) const

void	setBooleanContents (BooleanContent Ty)
	Specify how the target extends the result of integer and floating point boolean values from i1 to a wider type. More...

void	setBooleanContents (BooleanContent IntTy, BooleanContent FloatTy)
	Specify how the target extends the result of integer and floating point boolean values from i1 to a wider type. More...

void	setBooleanVectorContents (BooleanContent Ty)
	Specify how the target extends the result of a vector boolean value from a vector of i1 to a wider type. More...

void	setSchedulingPreference (Sched::Preference Pref)
	Specify the target scheduling preference. More...

void	setUseUnderscoreSetJmp (bool Val)
	Indicate whether this target prefers to use _setjmp to implement llvm.setjmp or the version without _. More...

void	setUseUnderscoreLongJmp (bool Val)
	Indicate whether this target prefers to use _longjmp to implement llvm.longjmp or the version without _. More...

void	setMinimumJumpTableEntries (unsigned Val)
	Indicate the minimum number of blocks to generate jump tables. More...

void	setMaximumJumpTableSize (unsigned)
	Indicate the maximum number of entries in jump tables. More...

void	setStackPointerRegisterToSaveRestore (unsigned R)
	If set to a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save and restore. More...

void	setHasMultipleConditionRegisters (bool hasManyRegs=true)
	Tells the code generator that the target has multiple (allocatable) condition registers that can be used to store the results of comparisons for use by selects and conditional branches. More...

void	setHasExtractBitsInsn (bool hasExtractInsn=true)
	Tells the code generator that the target has BitExtract instructions. More...

void	setJumpIsExpensive (bool isExpensive=true)
	Tells the code generator not to expand logic operations on comparison predicates into separate sequences that increase the amount of flow control. More...

void	setHasFloatingPointExceptions (bool FPExceptions=true)
	Tells the code generator that this target supports floating point exceptions and cares about preserving floating point exception behavior. More...

void	addBypassSlowDiv (unsigned int SlowBitWidth, unsigned int FastBitWidth)
	Tells the code generator which bitwidths to bypass. More...

void	addRegisterClass (MVT VT, const TargetRegisterClass *RC)
	Add the specified register class as an available regclass for the specified value type. More...

void	computeRegisterProperties (const TargetRegisterInfo *TRI)
	Once all of the register classes are added, this allows us to compute derived properties we expose. More...

void	setOperationAction (unsigned Op, MVT VT, LegalizeAction Action)
	Indicate that the specified operation does not work with the specified type and indicate what to do about it. More...

void	setLoadExtAction (unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)
	Indicate that the specified load with extension does not work with the specified type and indicate what to do about it. More...

void	setTruncStoreAction (MVT ValVT, MVT MemVT, LegalizeAction Action)
	Indicate that the specified truncating store does not work with the specified type and indicate what to do about it. More...

void	setIndexedLoadAction (unsigned IdxMode, MVT VT, LegalizeAction Action)
	Indicate that the specified indexed load does or does not work with the specified type and indicate what to do abort it. More...

void	setIndexedStoreAction (unsigned IdxMode, MVT VT, LegalizeAction Action)
	Indicate that the specified indexed store does or does not work with the specified type and indicate what to do about it. More...

void	setCondCodeAction (ISD::CondCode CC, MVT VT, LegalizeAction Action)
	Indicate that the specified condition code is or isn't supported on the target and indicate what to do about it. More...

void	AddPromotedToType (unsigned Opc, MVT OrigVT, MVT DestVT)
	If Opc/OrigVT is specified as being promoted, the promotion code defaults to trying a larger integer/fp until it can find one that works. More...

void	setOperationPromotedToType (unsigned Opc, MVT OrigVT, MVT DestVT)
	Convenience method to set an operation to Promote and specify the type in a single call. More...

void	setTargetDAGCombine (ISD::NodeType NT)
	Targets should invoke this method for each target independent node that they want to provide a custom DAG combiner for by implementing the PerformDAGCombine virtual method. More...

void	setJumpBufSize (unsigned Size)
	Set the target's required jmp_buf buffer size (in bytes); default is 200. More...

void	setJumpBufAlignment (unsigned Align)
	Set the target's required jmp_buf buffer alignment (in bytes); default is 0. More...

void	setMinFunctionAlignment (unsigned Align)
	Set the target's minimum function alignment (in log2(bytes)) More...

void	setPrefFunctionAlignment (unsigned Align)
	Set the target's preferred function alignment. More...

void	setPrefLoopAlignment (unsigned Align)
	Set the target's preferred loop alignment. More...

void	setMinStackArgumentAlignment (unsigned Align)
	Set the minimum stack alignment of an argument (in log2(bytes)). More...

void	setMaxAtomicSizeInBitsSupported (unsigned SizeInBits)
	Set the maximum atomic operation size supported by the backend. More...

void	setMinCmpXchgSizeInBits (unsigned SizeInBits)
	Sets the minimum cmpxchg or ll/sc size supported by the backend. More...

void	setSupportsUnalignedAtomics (bool UnalignedSupported)
	Sets whether unaligned atomic operations are supported. More...

virtual bool	isExtFreeImpl (const Instruction *I) const
	Return true if the extension represented by `I` is free. More...

bool	isLegalRC (const TargetRegisterInfo &TRI, const TargetRegisterClass &RC) const
	Return true if the value types that can be represented by the specified register class are all legal. More...

MachineBasicBlock *	emitPatchPoint (MachineInstr &MI, MachineBasicBlock *MBB) const
	Replace/modify any TargetFrameIndex operands with a targte-dependent sequence of memory operands that is recognized by PrologEpilogInserter. More...

MachineBasicBlock *	emitXRayCustomEvent (MachineInstr &MI, MachineBasicBlock *MBB) const
	Replace/modify the XRay custom event operands with target-dependent details. More...

MachineBasicBlock *	emitXRayTypedEvent (MachineInstr &MI, MachineBasicBlock *MBB) const
	Replace/modify the XRay typed event operands with target-dependent details. More...

Additional Inherited Members
Public Types inherited from llvm::TargetLowering
enum	ConstraintType { C_Register, C_RegisterClass, C_Memory, C_Other, C_Unknown }

enum	ConstraintWeight { CW_Invalid = -1, CW_Okay = 0, CW_Good = 1, CW_Better = 2, CW_Best = 3, CW_SpecificReg = CW_Okay, CW_Register = CW_Good, CW_Memory = CW_Better, CW_Constant = CW_Best, CW_Default = CW_Okay }

using	AsmOperandInfoVector = std::vector< AsmOperandInfo >

Public Types inherited from llvm::TargetLoweringBase
enum	LegalizeAction : uint8_t { Legal, Promote, Expand, LibCall, Custom }
	This enum indicates whether operations are valid for a target, and if not, what action should be used to make them valid. More...

enum	LegalizeTypeAction : uint8_t { TypeLegal, TypePromoteInteger, TypeExpandInteger, TypeSoftenFloat, TypeExpandFloat, TypeScalarizeVector, TypeSplitVector, TypeWidenVector, TypePromoteFloat }
	This enum indicates whether a types are legal for a target, and if not, what action should be used to make them valid. More...

enum	BooleanContent { UndefinedBooleanContent, ZeroOrOneBooleanContent, ZeroOrNegativeOneBooleanContent }
	Enum that describes how the target represents true/false values. More...

enum	SelectSupportKind { ScalarValSelect, ScalarCondVectorVal, VectorMaskSelect }
	Enum that describes what type of support for selects the target has. More...

enum	AtomicExpansionKind { AtomicExpansionKind::None, AtomicExpansionKind::LLSC, AtomicExpansionKind::LLOnly, AtomicExpansionKind::CmpXChg, AtomicExpansionKind::MaskedIntrinsic }
	Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all. More...

enum	MulExpansionKind { MulExpansionKind::Always, MulExpansionKind::OnlyLegalOrCustom }
	Enum that specifies when a multiplication should be expanded. More...

enum	ReciprocalEstimate : int { Unspecified = -1, Disabled = 0, Enabled = 1 }
	Reciprocal estimate status values used by the functions below. More...

using	LegalizeKind = std::pair< LegalizeTypeAction, EVT >
	LegalizeKind holds the legalization kind that needs to happen to EVT in order to type-legalize it. More...

using	ArgListTy = std::vector< ArgListEntry >

Static Public Member Functions inherited from llvm::TargetLoweringBase
static ISD::NodeType	getExtendForContent (BooleanContent Content)

Protected Attributes inherited from llvm::TargetLoweringBase
ValueTypeActionImpl	ValueTypeActions

unsigned	GatherAllAliasesMaxDepth
	Depth that GatherAllAliases should should continue looking for chain dependencies when trying to find a more preferable chain. More...

unsigned	MaxStoresPerMemset
	Specify maximum number of store instructions per memset call. More...

unsigned	MaxStoresPerMemsetOptSize
	Maximum number of stores operations that may be substituted for the call to memset, used for functions with OptSize attribute. More...

unsigned	MaxStoresPerMemcpy
	Specify maximum bytes of store instructions per memcpy call. More...

unsigned	MaxGluedStoresPerMemcpy = 0
	Specify max number of store instructions to glue in inlined memcpy. More...

unsigned	MaxStoresPerMemcpyOptSize
	Maximum number of store operations that may be substituted for a call to memcpy, used for functions with OptSize attribute. More...

unsigned	MaxLoadsPerMemcmp

unsigned	MaxLoadsPerMemcmpOptSize

unsigned	MaxStoresPerMemmove
	Specify maximum bytes of store instructions per memmove call. More...

unsigned	MaxStoresPerMemmoveOptSize
	Maximum number of store instructions that may be substituted for a call to memmove, used for functions with OptSize attribute. More...

bool	PredictableSelectIsExpensive
	Tells the code generator that select is more expensive than a branch if the branch is usually predicted right. More...

bool	EnableExtLdPromotion

Detailed Description

Definition at line 278 of file ARMISelLowering.h.

Constructor & Destructor Documentation

◆ ARMTargetLowering()

ARMTargetLowering::ARMTargetLowering	(	const TargetMachine &	TM,
		const ARMSubtarget &	STI
	)

explicit

Definition at line 223 of file ARMISelLowering.cpp.

Member Function Documentation

◆ AdjustInstrPostInstrSelection()

void ARMTargetLowering::AdjustInstrPostInstrSelection	(	MachineInstr &	MI,
		SDNode *	Node
	)		const

overridevirtual

This method should be implemented by targets that mark instructions with the 'hasPostISelHook' flag.

These instructions must be adjusted after instruction selection by target hooks. e.g. To fill in optional defs for ARM 's' setting instructions.

Reimplemented from llvm::TargetLowering.

Definition at line 9540 of file ARMISelLowering.cpp.

◆ alignLoopsWithOptSize()

bool ARMTargetLowering::alignLoopsWithOptSize ( ) const

overridevirtual

Should loops be aligned even when the function is marked OptSize (but not MinSize).

Reimplemented from llvm::TargetLoweringBase.

Definition at line 14717 of file ARMISelLowering.cpp.

References llvm::ARMSubtarget::isMClass().

◆ allowsMisalignedMemoryAccesses()

bool ARMTargetLowering::allowsMisalignedMemoryAccesses	(	EVT	VT,
		unsigned	AddrSpace,
		unsigned	Align,
		bool *	Fast
	)		const

overridevirtual

allowsMisalignedMemoryAccesses - Returns true if the target allows unaligned memory accesses of the specified type.

Returns whether it is "fast" by reference in the second argument.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 12938 of file ARMISelLowering.cpp.

References llvm::ARMSubtarget::allowsUnalignedMem(), llvm::MVT::f64, llvm::EVT::getSimpleVT(), llvm::ARMSubtarget::hasNEON(), llvm::ARMSubtarget::hasV7Ops(), llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i8, llvm::ARMSubtarget::isLittle(), llvm::EVT::isSimple(), llvm::MVT::SimpleTy, and llvm::MVT::v2f64.

Referenced by getOptimalMemOpType().

◆ allowTruncateForTailCall()

bool ARMTargetLowering::allowTruncateForTailCall	(	Type *	FromTy,
		Type *	ToTy
	)		const

overridevirtual

Return true if a truncation from FromTy to ToTy is permitted when deciding whether a call is in tail position.

Typically this means that both results would be assigned to the same register or stack slot, but it could mean the target performs adequate checks of its own before proceeding with the tail call. Targets must return false when FromTy <= ToTy.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 13092 of file ARMISelLowering.cpp.

References assert(), llvm::EVT::getEVT(), llvm::Type::getPrimitiveSizeInBits(), llvm::Type::isIntegerTy(), and llvm::TargetLoweringBase::isTypeLegal().

◆ canCombineStoreAndExtract()

bool ARMTargetLowering::canCombineStoreAndExtract	(	Type *	VectorTy,
		Value *	Idx,
		unsigned &	Cost
	)		const

overridevirtual

Return true if the target can combine store(extractelement VectorTy, Idx).

Cost[out] gives the cost of that transformation when this is true.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 14602 of file ARMISelLowering.cpp.

References assert(), getBitWidth(), llvm::ARMSubtarget::hasNEON(), llvm::Type::isFPOrFPVectorTy(), and llvm::Type::isVectorTy().

◆ canMergeStoresTo()

bool llvm::ARMTargetLowering::canMergeStoresTo	(	unsigned	AS,
		EVT	MemVT,
		const SelectionDAG &	DAG
	)		const

inlineoverridevirtual

Returns if it's reasonable to merge stores to MemVT size.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 550 of file ARMISelLowering.h.

References llvm::EVT::getSizeInBits().

◆ CCAssignFnForCall()

CCAssignFn * ARMTargetLowering::CCAssignFnForCall	(	CallingConv::ID	CC,
		bool	isVarArg
	)		const

Definition at line 1635 of file ARMISelLowering.cpp.

Referenced by CCAssignFnForReturn(), LowerVASTART(), and MatchingStackOffset().

◆ CCAssignFnForReturn()

CCAssignFn * ARMTargetLowering::CCAssignFnForReturn	(	CallingConv::ID	CC,
		bool	isVarArg
	)		const

Definition at line 1640 of file ARMISelLowering.cpp.

Referenced by LowerInterruptReturn(), and MatchingStackOffset().

◆ computeKnownBitsForTargetNode()

void ARMTargetLowering::computeKnownBitsForTargetNode	(	const SDValue	Op,
		KnownBits &	Known,
		const APInt &	DemandedElts,
		const SelectionDAG &	DAG,
		unsigned	Depth
	)		const

overridevirtual

Determine which of the bits specified in Mask are known to be either zero or one and return them in the KnownZero/KnownOne bitsets.

Determine which of the bits specified in Mask are known to be either zero or one and return them in the Known.

The DemandedElts argument allows us to only collect the known bits that are shared by the requested vector elements.

Reimplemented from llvm::TargetLowering.

Definition at line 13551 of file ARMISelLowering.cpp.

References llvm::ARMISD::ADDC, llvm::ARMISD::ADDE, llvm::Intrinsic::arm_ldaex, llvm::Intrinsic::arm_ldrex, assert(), llvm::ARMISD::BFI, llvm::ARMISD::CMOV, llvm::SelectionDAG::computeKnownBits(), llvm::ConstantSDNode::getAPIntValue(), llvm::KnownBits::getBitWidth(), llvm::APInt::getHighBitsSet(), llvm::SDValue::getNode(), llvm::APInt::getOneBitSet(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::SDValue::getResNo(), llvm::EVT::getScalarSizeInBits(), llvm::EVT::getSizeInBits(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::ConstantSDNode::getZExtValue(), llvm::ISD::INTRINSIC_W_CHAIN, llvm::isNullConstant(), llvm::KnownBits::isUnknown(), llvm::EVT::isVector(), llvm::BitmaskEnumDetail::Mask(), llvm::KnownBits::One, llvm::KnownBits::resetAll(), llvm::APInt::setBitsFrom(), llvm::KnownBits::sext(), llvm::ARMISD::SUBC, llvm::ARMISD::SUBE, llvm::APInt::ult(), llvm::ARMISD::VGETLANEs, llvm::ARMISD::VGETLANEu, llvm::KnownBits::Zero, and llvm::KnownBits::zext().

◆ convertSetCCLogicToBitwiseLogic()

bool llvm::ARMTargetLowering::convertSetCCLogicToBitwiseLogic ( EVT VT ) const

inlineoverridevirtual

Use bitwise logic to make pairs of compares more efficient.

For example: and (seteq A, B), (seteq C, D) –> seteq (or (xor A, B), (xor C, D)), 0 This should be true when it takes more than one instruction to lower setcc (cmp+set on x86 scalar), when bitwise ops are faster than logic on condition bits (crand on PowerPC), and/or when reducing cmp+br is a win.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 559 of file ARMISelLowering.h.

References llvm::EVT::isScalarInteger().

◆ createFastISel()

FastISel * ARMTargetLowering::createFastISel	(	FunctionLoweringInfo &	funcInfo,
		const TargetLibraryInfo *	libInfo
	)		const

overridevirtual

createFastISel - This method returns a target specific FastISel object, or null if the target does not support "fast" ISel.

Reimplemented from llvm::TargetLowering.

Definition at line 1455 of file ARMISelLowering.cpp.

References llvm::ARM::createFastISel().

◆ emitAtomicCmpXchgNoStoreLLBalance()

void ARMTargetLowering::emitAtomicCmpXchgNoStoreLLBalance ( IRBuilder<> & Builder ) const

overridevirtual

Reimplemented from llvm::TargetLoweringBase.

Definition at line 14675 of file ARMISelLowering.cpp.

References llvm::Intrinsic::arm_clrex, llvm::IRBuilder< T, Inserter >::CreateCall(), llvm::Intrinsic::getDeclaration(), llvm::IRBuilderBase::GetInsertBlock(), llvm::BasicBlock::getParent(), llvm::GlobalValue::getParent(), and llvm::ARMSubtarget::hasV7Ops().

◆ EmitInstrWithCustomInserter()

MachineBasicBlock * ARMTargetLowering::EmitInstrWithCustomInserter	(	MachineInstr &	MI,
		MachineBasicBlock *	MBB
	)		const

overridevirtual

This method should be implemented by targets that mark instructions with the 'usesCustomInserter' flag.

These instructions are special in various ways, which require special support to insert. The specified MachineInstr is created but not inserted into any basic blocks, and this method is called to expand it into a sequence of instructions, potentially also creating new basic blocks and control flow. As long as the returned basic block is different (i.e., we created a new one), the custom inserter is free to modify the rest of MBB.

Reimplemented from llvm::TargetLowering.

Definition at line 9224 of file ARMISelLowering.cpp.

References llvm::ISD::ABS, llvm::ARM_AM::add, llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addImm(), llvm::MachineBasicBlock::addLiveIn(), llvm::MachineInstrBuilder::addMBB(), llvm::MachineInstrBuilder::addReg(), llvm::MachineBasicBlock::addSuccessor(), llvm::ARMCC::AL, B, llvm::MachineBasicBlock::begin(), llvm::BuildMI(), checkAndUpdateCPSRKill(), llvm::condCodeOp(), llvm::MachineFunction::CreateMachineBasicBlock(), llvm::MachineRegisterInfo::createVirtualRegister(), llvm::tgtok::Def, llvm::MachineBasicBlock::end(), llvm::ARMCC::EQ, llvm::MachineBasicBlock::erase(), llvm::MachineInstr::eraseFromParent(), llvm::errs(), F(), llvm::MCInstrInfo::get(), llvm::ARM_AM::getAM2Offset(), llvm::ARM_AM::getAM2Op(), llvm::MachineBasicBlock::getBasicBlock(), llvm::MachineInstr::getDebugLoc(), llvm::MachineOperand::getImm(), llvm::ARMSubtarget::getInstrInfo(), llvm::ilist_node_impl< OptionsT >::getIterator(), llvm::MachineOperand::getMBB(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::ARMCC::getOppositeCondition(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), llvm::ARMSubtarget::getRegisterInfo(), llvm::MachineFunction::insert(), llvm::MachineOperand::isKill(), llvm::ARMSubtarget::isThumb2(), llvm::RegState::Kill, llvm::MachineInstr::killsRegister(), llvm_unreachable, llvm::MachineInstr::memoperands_begin(), llvm::ARMCC::MI, MRI, llvm::ARMCC::NE, OtherSucc(), llvm::predOps(), llvm::MachineInstr::print(), llvm::MachineInstr::setDesc(), llvm::MachineBasicBlock::splice(), llvm::ARM_AM::sub, std::swap(), TII, llvm::MachineBasicBlock::transferSuccessorsAndUpdatePHIs(), TRI, llvm::ARMISD::WIN__CHKSTK, and llvm::ARMISD::WIN__DBZCHK.

◆ emitLeadingFence()

Instruction * ARMTargetLowering::emitLeadingFence	(	IRBuilder<> &	Builder,
		Instruction *	Inst,
		AtomicOrdering	Ord
	)		const

overridevirtual

Inserts in the IR a target-specific intrinsic specifying a fence.

It is called by AtomicExpandPass before expanding an AtomicRMW/AtomicCmpXchg/AtomicStore/AtomicLoad if shouldInsertFencesForAtomic returns true.

Inst is the original atomic instruction, prior to other expansions that may be performed.

This function should either return a nullptr, or a pointer to an IR-level Instruction*. Even complex fence sequences can be represented by a single Instruction* through an intrinsic to be lowered later. Backends should override this method to produce target-specific intrinsic for their fences. FIXME: Please note that the default implementation here in terms of IR-level fences exists for historical/compatibility reasons and is unsound ! Fences cannot, in general, be used to restore sequential consistency. For example, consider the following example: atomic<int> x = y = 0; int r1, r2, r3, r4; Thread 0: x.store(1); Thread 1: y.store(1); Thread 2: r1 = x.load(); r2 = y.load(); Thread 3: r3 = y.load(); r4 = x.load(); r1 = r3 = 1 and r2 = r4 = 0 is impossible as long as the accesses are all seq_cst. But if they are lowered to monotonic accesses, no amount of IR-level fences can prevent it.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 14501 of file ARMISelLowering.cpp.

References llvm::Acquire, llvm::AcquireRelease, llvm::Instruction::hasAtomicStore(), llvm::ARM_MB::ISH, llvm::ARM_MB::ISHST, LLVM_FALLTHROUGH, llvm_unreachable, makeDMB(), llvm::Monotonic, llvm::NotAtomic, llvm::ARMSubtarget::preferISHSTBarriers(), llvm::Release, llvm::SequentiallyConsistent, and llvm::Unordered.

◆ emitLoadLinked()

Value * ARMTargetLowering::emitLoadLinked	(	IRBuilder<> &	Builder,
		Value *	Addr,
		AtomicOrdering	Ord
	)		const

overridevirtual

Perform a load-linked operation on Addr, returning a "Value *" with the corresponding pointee type.

This may entail some non-trivial operations to truncate or reconstruct types that will be illegal in the backend. See ARMISelLowering for an example implementation.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 14639 of file ARMISelLowering.cpp.

References llvm::Intrinsic::arm_ldaex, llvm::Intrinsic::arm_ldaexd, llvm::Intrinsic::arm_ldrex, llvm::Intrinsic::arm_ldrexd, llvm::IRBuilder< T, Inserter >::CreateBitCast(), llvm::IRBuilder< T, Inserter >::CreateCall(), llvm::IRBuilder< T, Inserter >::CreateExtractValue(), llvm::IRBuilder< T, Inserter >::CreateOr(), llvm::IRBuilder< T, Inserter >::CreateShl(), llvm::IRBuilder< T, Inserter >::CreateTruncOrBitCast(), llvm::IRBuilder< T, Inserter >::CreateZExt(), llvm::ConstantInt::get(), llvm::Module::getContext(), llvm::Intrinsic::getDeclaration(), llvm::IRBuilderBase::GetInsertBlock(), llvm::Type::getInt8PtrTy(), llvm::BasicBlock::getParent(), llvm::GlobalValue::getParent(), llvm::Type::getPrimitiveSizeInBits(), llvm::Value::getType(), llvm::MipsISD::Hi, llvm::isAcquireOrStronger(), llvm::ARMSubtarget::isLittle(), llvm::MipsISD::Lo, and std::swap().

◆ emitStoreConditional()

Value * ARMTargetLowering::emitStoreConditional	(	IRBuilder<> &	Builder,
		Value *	Val,
		Value *	Addr,
		AtomicOrdering	Ord
	)		const

overridevirtual

Perform a store-conditional operation to Addr.

Return the status of the store. This should be 0 if the store succeeded, non-zero otherwise.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 14683 of file ARMISelLowering.cpp.

References llvm::Intrinsic::arm_stlex, llvm::Intrinsic::arm_stlexd, llvm::Intrinsic::arm_strex, llvm::Intrinsic::arm_strexd, llvm::IRBuilder< T, Inserter >::CreateBitCast(), llvm::IRBuilder< T, Inserter >::CreateCall(), llvm::IRBuilder< T, Inserter >::CreateLShr(), llvm::IRBuilder< T, Inserter >::CreateTrunc(), llvm::IRBuilder< T, Inserter >::CreateZExtOrBitCast(), llvm::Module::getContext(), llvm::Intrinsic::getDeclaration(), llvm::Function::getFunctionType(), llvm::IRBuilderBase::GetInsertBlock(), llvm::Type::getInt32Ty(), llvm::Type::getInt8PtrTy(), llvm::FunctionType::getParamType(), llvm::BasicBlock::getParent(), llvm::GlobalValue::getParent(), llvm::Type::getPrimitiveSizeInBits(), llvm::Value::getType(), llvm::MipsISD::Hi, Int32Ty, llvm::ARMSubtarget::isLittle(), llvm::isReleaseOrStronger(), llvm::MipsISD::Lo, and std::swap().

◆ emitTrailingFence()

Instruction * ARMTargetLowering::emitTrailingFence	(	IRBuilder<> &	Builder,
		Instruction *	Inst,
		AtomicOrdering	Ord
	)		const

overridevirtual

Reimplemented from llvm::TargetLoweringBase.

Definition at line 14526 of file ARMISelLowering.cpp.

References llvm::Acquire, llvm::AcquireRelease, llvm::ARM_MB::ISH, llvm_unreachable, makeDMB(), llvm::Monotonic, llvm::NotAtomic, llvm::Release, llvm::SequentiallyConsistent, and llvm::Unordered.

◆ ExpandInlineAsm()

bool ARMTargetLowering::ExpandInlineAsm ( CallInst * ) const

overridevirtual

This hook allows the target to expand an inline asm call to be explicit llvm code if it wants to.

This is useful for turning simple inline asms into LLVM intrinsics, which gives the compiler more information about the behavior of the code.

Reimplemented from llvm::TargetLowering.

Definition at line 13732 of file ARMISelLowering.cpp.

References llvm::SmallVectorImpl< T >::clear(), llvm::dyn_cast(), llvm::InlineAsm::getAsmString(), llvm::IntegerType::getBitWidth(), llvm::CallBase::getCalledValue(), llvm::InlineAsm::getConstraintString(), llvm::Value::getType(), llvm::ARMSubtarget::hasV6Ops(), llvm::IntrinsicLowering::LowerToByteSwap(), llvm::SmallVectorBase::size(), and llvm::SplitString().

◆ finalizeLowering()

void ARMTargetLowering::finalizeLowering ( MachineFunction & MF ) const

overridevirtual

Execute target specific actions to finalize target lowering.

This is used to set extra flags in MachineFrameInformation and freezing the set of reserved registers. The default implementation just freezes the set of reserved registers.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 15161 of file ARMISelLowering.cpp.

References llvm::MachineFrameInfo::computeMaxCallFrameSize(), llvm::TargetLoweringBase::finalizeLowering(), and llvm::MachineFunction::getFrameInfo().

◆ findRepresentativeClass()

std::pair< const TargetRegisterClass *, uint8_t > ARMTargetLowering::findRepresentativeClass	(	const TargetRegisterInfo *	TRI,
		MVT	VT
	)		const

overrideprotectedvirtual

Return the largest legal super-reg register class of the register class for the specified type and its associated "cost".

findRepresentativeClass - Return the largest legal super-reg register class of the register class for the specified type and its associated "cost".

Reimplemented from llvm::TargetLoweringBase.

Definition at line 1224 of file ARMISelLowering.cpp.

References llvm::MVT::f32, llvm::MVT::f64, llvm::TargetLoweringBase::findRepresentativeClass(), llvm::MSP430ISD::RRC, llvm::MVT::SimpleTy, llvm::ARMSubtarget::useNEONForSinglePrecisionFP(), llvm::MVT::v16i8, llvm::MVT::v1i64, llvm::MVT::v2f32, llvm::MVT::v2f64, llvm::MVT::v2i32, llvm::MVT::v2i64, llvm::MVT::v4f32, llvm::MVT::v4i16, llvm::MVT::v4i32, llvm::MVT::v4i64, llvm::MVT::v8i16, llvm::MVT::v8i64, and llvm::MVT::v8i8.

◆ functionArgumentNeedsConsecutiveRegisters()

bool ARMTargetLowering::functionArgumentNeedsConsecutiveRegisters	(	Type *	Ty,
		CallingConv::ID	CallConv,
		bool	isVarArg
	)		const

overridevirtual

Returns true if an argument of type Ty needs to be passed in a contiguous block of registers in calling convention CallConv.

Return true if a type is an AAPCS-VFP homogeneous aggregate or one of [N x i32] or [N x i64].

This allows front-ends to skip emitting padding when passing according to AAPCS rules.

Reimplemented from llvm::TargetLowering.

Definition at line 15085 of file ARMISelLowering.cpp.

References llvm::CallingConv::ARM_AAPCS_VFP, llvm::dbgs(), llvm::Type::dump(), llvm::Type::getArrayElementType(), HA_UNKNOWN, llvm::Type::isArrayTy(), isHomogeneousAggregate(), llvm::Type::isIntegerTy(), and LLVM_DEBUG.

Referenced by isSupportedType().

◆ getABIAlignmentForCallingConv()

unsigned ARMTargetLowering::getABIAlignmentForCallingConv	(	Type *	ArgTy,
		DataLayout	DL
	)		const

overridevirtual

Return the correct alignment for the current calling convention.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 15072 of file ARMISelLowering.cpp.

References llvm::DataLayout::getABITypeAlignment(), llvm::DataLayout::getStackAlignment(), and llvm::Type::isVectorTy().

◆ getConstraintType()

ARMTargetLowering::ConstraintType ARMTargetLowering::getConstraintType ( StringRef Constraint ) const

overridevirtual

getConstraintType - Given a constraint letter, return the type of constraint it is for this target.

Reimplemented from llvm::TargetLowering.

Definition at line 13786 of file ARMISelLowering.cpp.

References llvm::TargetLowering::C_Memory, llvm::TargetLowering::C_Other, llvm::TargetLowering::C_RegisterClass, llvm::TargetLowering::getConstraintType(), and llvm::StringRef::size().

◆ getExceptionPointerRegister()

unsigned ARMTargetLowering::getExceptionPointerRegister ( const Constant * PersonalityFn ) const

overridevirtual

If a physical register, this returns the register that receives the exception address on entry to an EH pad.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 15100 of file ARMISelLowering.cpp.

References llvm::ARMSubtarget::useSjLjEH().

◆ getExceptionSelectorRegister()

unsigned ARMTargetLowering::getExceptionSelectorRegister ( const Constant * PersonalityFn ) const

overridevirtual

If a physical register, this returns the register that receives the exception typeid on entry to a landing pad.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 15107 of file ARMISelLowering.cpp.

References llvm::MachineBasicBlock::addLiveIn(), assert(), llvm::MachineBasicBlock::begin(), llvm::BuildMI(), contains(), llvm::MachineRegisterInfo::createVirtualRegister(), llvm::MCInstrInfo::get(), llvm::ARMBaseRegisterInfo::getCalleeSavedRegsViaCopy(), llvm::MachineFunction::getFunction(), llvm::MachineFunction::getInfo(), llvm::ARMSubtarget::getInstrInfo(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), llvm::ARMSubtarget::getRegisterInfo(), llvm::Function::hasFnAttribute(), I, llvm_unreachable, MRI, llvm::Attribute::NoUnwind, llvm::ARMFunctionInfo::setIsSplitCSR(), TII, TRI, and llvm::ARMSubtarget::useSjLjEH().

◆ getInlineAsmMemConstraint()

unsigned llvm::ARMTargetLowering::getInlineAsmMemConstraint ( StringRef ConstraintCode ) const

inlineoverridevirtual

Reimplemented from llvm::TargetLowering.

Definition at line 421 of file ARMISelLowering.h.

References llvm::InlineAsm::Constraint_o, llvm::InlineAsm::Constraint_Q, llvm::InlineAsm::Constraint_Um, llvm::InlineAsm::Constraint_Un, llvm::InlineAsm::Constraint_Uq, llvm::InlineAsm::Constraint_Us, llvm::InlineAsm::Constraint_Ut, llvm::InlineAsm::Constraint_Uv, llvm::InlineAsm::Constraint_Uy, llvm::TargetLowering::getInlineAsmMemConstraint(), and llvm::StringRef::size().

◆ getJumpTableEncoding()

unsigned ARMTargetLowering::getJumpTableEncoding ( ) const

overridevirtual

Return the entry encoding for a jump table in the current function.

The returned value is a member of the MachineJumpTableInfo::JTEntryKind enum.

Reimplemented from llvm::TargetLowering.

Definition at line 2756 of file ARMISelLowering.cpp.

◆ getMaxSupportedInterleaveFactor()

unsigned llvm::ARMTargetLowering::getMaxSupportedInterleaveFactor ( ) const

inlineoverridevirtual

Get the maximum supported factor for interleaved memory accesses.

Default to be the minimum interleave factor: 2.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 527 of file ARMISelLowering.h.

References SI.

Referenced by lowerInterleavedLoad(), and lowerInterleavedStore().

◆ getNumInterleavedAccesses()

unsigned ARMTargetLowering::getNumInterleavedAccesses	(	VectorType *	VecTy,
		const DataLayout &	DL
	)		const

Returns the number of interleaved accesses that will be generated when lowering accesses of the given type.

A helper function for determining the number of interleaved accesses we will generate when lowering accesses of the given type.

Definition at line 14724 of file ARMISelLowering.cpp.

References llvm::DataLayout::getTypeSizeInBits().

Referenced by llvm::ARMTTIImpl::getInterleavedMemoryOpCost(), lowerInterleavedLoad(), and lowerInterleavedStore().

◆ getOptimalMemOpType()

EVT ARMTargetLowering::getOptimalMemOpType	(	uint64_t	,
		unsigned	,
		unsigned	,
		bool	,
		bool	,
		bool	,
		MachineFunction &
	)		const

overridevirtual

Returns the target specific optimal type for load and store operations as a result of memset, memcpy, and memmove lowering.

If DstAlign is zero that means it's safe to destination alignment can satisfy any constraint. Similarly if SrcAlign is zero it means there isn't a need to check it against alignment requirement, probably because the source does not need to be loaded. If 'IsMemset' is true, that means it's expanding a memset. If 'ZeroMemset' is true, that means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy source is constant so it does not need to be loaded. It returns EVT::Other if the type should be determined using generic target-independent logic.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 12984 of file ARMISelLowering.cpp.

References allowsMisalignedMemoryAccesses(), F(), llvm::MVT::f64, llvm::CallingConv::Fast, llvm::MachineFunction::getFunction(), llvm::Function::hasFnAttribute(), llvm::ARMSubtarget::hasNEON(), memOpAlign(), llvm::Attribute::NoImplicitFloat, llvm::MVT::Other, and llvm::MVT::v2f64.

◆ getPostIndexedAddressParts()

bool ARMTargetLowering::getPostIndexedAddressParts	(	SDNode *	N,
		SDNode *	Op,
		SDValue &	Base,
		SDValue &	Offset,
		ISD::MemIndexedMode &	AM,
		SelectionDAG &	DAG
	)		const

overridevirtual

getPostIndexedAddressParts - returns true by value, base pointer and offset pointer and addressing mode by reference if this node can be combined with a load / store to form a post-indexed load / store.

Reimplemented from llvm::TargetLowering.

Definition at line 13488 of file ARMISelLowering.cpp.

References llvm::ISD::ADD, assert(), llvm::dyn_cast(), getARMIndexedAddressParts(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), getT2IndexedAddressParts(), llvm::SDNode::getValueType(), llvm::MVT::i32, llvm::ISD::isSEXTLoad(), llvm::ARMSubtarget::isThumb1Only(), llvm::ARMSubtarget::isThumb2(), llvm::ARM_MB::LD, llvm::ISD::NON_EXTLOAD, llvm::ISD::POST_DEC, llvm::ISD::POST_INC, llvm::ISD::SEXTLOAD, and std::swap().

◆ getPreIndexedAddressParts()

bool ARMTargetLowering::getPreIndexedAddressParts	(	SDNode *	N,
		SDValue &	Base,
		SDValue &	Offset,
		ISD::MemIndexedMode &	AM,
		SelectionDAG &	DAG
	)		const

overridevirtual

getPreIndexedAddressParts - returns true by value, base pointer and offset pointer and addressing mode by reference if the node's address can be legally represented as pre-indexed load / store address.

Reimplemented from llvm::TargetLowering.

Definition at line 13450 of file ARMISelLowering.cpp.

References getARMIndexedAddressParts(), llvm::SDValue::getNode(), getT2IndexedAddressParts(), llvm::ISD::isSEXTLoad(), llvm::ARMSubtarget::isThumb1Only(), llvm::ARMSubtarget::isThumb2(), llvm::ARM_MB::LD, llvm::ISD::PRE_DEC, llvm::ISD::PRE_INC, and llvm::ISD::SEXTLOAD.

◆ getRegClassFor()

const TargetRegisterClass * ARMTargetLowering::getRegClassFor ( MVT VT ) const

overridevirtual

getRegClassFor - Return the register class that should be used for the specified value type.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 1426 of file ARMISelLowering.cpp.

References llvm::TargetLoweringBase::getRegClassFor(), llvm::ARMSubtarget::hasNEON(), llvm::MVT::v4i64, and llvm::MVT::v8i64.

Referenced by LowerVectorINT_TO_FP().

◆ getRegForInlineAsmConstraint()

RCPair ARMTargetLowering::getRegForInlineAsmConstraint	(	const TargetRegisterInfo *	TRI,
		StringRef	Constraint,
		MVT	VT
	)		const

overridevirtual

Given a physical register constraint (e.g.

{edx}), return the register number and the register class for the register.

Given a register class constraint, like 'r', if this corresponds directly to an LLVM register class, return a register of 0 and the register class pointer.

This should only be used for C_Register constraints. On error, this returns a register number of 0 and a null register class pointer.

Reimplemented from llvm::TargetLowering.

Definition at line 13846 of file ARMISelLowering.cpp.

References llvm::StringRef::equals_lower(), llvm::MVT::f32, llvm::TargetLowering::getRegForInlineAsmConstraint(), llvm::MVT::getSizeInBits(), llvm::MVT::i32, llvm::ARMSubtarget::isThumb(), llvm::ARMSubtarget::isThumb1Only(), llvm::MVT::Other, and llvm::StringRef::size().

◆ getScalingFactorCost()

int ARMTargetLowering::getScalingFactorCost	(	const DataLayout &	DL,
		const AddrMode &	AM,
		Type *	Ty,
		unsigned	AS
	)		const

overridevirtual

getScalingFactorCost - Return the cost of the scaling used in addressing mode represented by AM.

If the AM is supported, the return value must be >= 0. If the AM is not supported, the return value must be negative.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 13106 of file ARMISelLowering.cpp.

References llvm::ARMSubtarget::hasFPAO(), isLegalAddressingMode(), and llvm::TargetLoweringBase::AddrMode::Scale.

◆ getSchedulingPreference()

Sched::Preference ARMTargetLowering::getSchedulingPreference ( SDNode * ) const

overridevirtual

Some scheduler, e.g.

hybrid, can switch to different scheduling heuristics for different nodes. This function returns the preference (or none) for the given node.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 1460 of file ARMISelLowering.cpp.

References llvm::MCInstrInfo::get(), llvm::ARMSubtarget::getInstrInfo(), llvm::SDNode::getMachineOpcode(), llvm::MCInstrDesc::getNumDefs(), llvm::SDNode::getNumValues(), llvm::InstrItineraryData::getOperandCycle(), llvm::MCInstrDesc::getSchedClass(), llvm::SDNode::getValueType(), llvm::MVT::Glue, llvm::Sched::ILP, llvm::InstrItineraryData::isEmpty(), llvm::EVT::isFloatingPoint(), llvm::SDNode::isMachineOpcode(), llvm::EVT::isVector(), llvm::MVT::Other, llvm::Sched::RegPressure, and TII.

◆ getSetCCResultType()

EVT ARMTargetLowering::getSetCCResultType	(	const DataLayout &	DL,
		LLVMContext &	Context,
		EVT	VT
	)		const

overridevirtual

getSetCCResultType - Return the value type to use for ISD::SETCC.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 1417 of file ARMISelLowering.cpp.

References llvm::EVT::changeVectorElementTypeToInteger(), llvm::TargetLoweringBase::getPointerTy(), and llvm::EVT::isVector().

◆ getSingleConstraintMatchWeight()

TargetLowering::ConstraintWeight ARMTargetLowering::getSingleConstraintMatchWeight	(	AsmOperandInfo &	info,
		const char *	constraint
	)		const

overridevirtual

Examine constraint string and operand type and determine a weight value.

Examine constraint type and operand type and determine a weight value.

The operand object must already have been set up with the operand type.

This object must already have been set up with the operand type and the current alternative constraint selected.

Reimplemented from llvm::TargetLowering.

Definition at line 13814 of file ARMISelLowering.cpp.

References llvm::TargetLowering::AsmOperandInfo::CallOperandVal, llvm::TargetLowering::CW_Default, llvm::TargetLowering::CW_Invalid, llvm::TargetLowering::CW_Register, llvm::TargetLowering::CW_SpecificReg, llvm::TargetLowering::getSingleConstraintMatchWeight(), llvm::Value::getType(), llvm::Type::isFloatingPointTy(), llvm::Type::isIntegerTy(), and llvm::ARMSubtarget::isThumb().

◆ getSubtarget()

const ARMSubtarget* llvm::ARMTargetLowering::getSubtarget ( ) const

inline

Definition at line 451 of file ARMISelLowering.h.

Referenced by promoteToConstantPool().

◆ getTargetNodeName()

const char * ARMTargetLowering::getTargetNodeName ( unsigned Opcode ) const

overridevirtual

This method returns the name of a target specific DAG node.

Reimplemented from llvm::TargetLowering.

Definition at line 1261 of file ARMISelLowering.cpp.

◆ getTgtMemIntrinsic()

bool ARMTargetLowering::getTgtMemIntrinsic	(	IntrinsicInfo &	Info,
		const CallInst &	I,
		MachineFunction &	MF,
		unsigned	Intrinsic
	)		const

overridevirtual

getTgtMemIntrinsic - Represent NEON load and store intrinsics as MemIntrinsicNodes.

The associated MachineMemOperands record the alignment specified in the intrinsic calls.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 14310 of file ARMISelLowering.cpp.

◆ hasStandaloneRem()

bool llvm::ARMTargetLowering::hasStandaloneRem ( EVT VT ) const

inlineoverridevirtual

Return true if the target can handle a standalone remainder operation.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 567 of file ARMISelLowering.h.

References Arg, Callee, llvm::CallingConv::CXX_FAST_TLS, llvm::Function::getCallingConv(), llvm::MachineFunction::getFunction(), llvm::Function::hasFnAttribute(), llvm::MipsISD::Ins, LowerBR_CC(), LowerCallResult(), LowerDYNAMIC_STACKALLOC(), LowerFCOPYSIGN(), LowerFP_EXTEND(), LowerFRAMEADDR(), LowerFSINCOS(), LowerMemOpCallTo(), LowerRETURNADDR(), LowerSELECT_CC(), llvm::Attribute::NoUnwind, llvm::MCID::Return, Signed, and llvm::ARM_MB::ST.

◆ isCheapToSpeculateCtlz()

bool ARMTargetLowering::isCheapToSpeculateCtlz ( ) const

overridevirtual

Return true if it is cheap to speculate a call to intrinsic ctlz.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 14635 of file ARMISelLowering.cpp.

References llvm::ARMSubtarget::hasV6T2Ops().

◆ isCheapToSpeculateCttz()

bool ARMTargetLowering::isCheapToSpeculateCttz ( ) const

overridevirtual

Return true if it is cheap to speculate a call to intrinsic cttz.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 14631 of file ARMISelLowering.cpp.

References llvm::ARMSubtarget::hasV6T2Ops().

◆ isDesirableToCommuteWithShift()

bool ARMTargetLowering::isDesirableToCommuteWithShift	(	const SDNode *	N,
		CombineLevel	Level
	)		const

overridevirtual

Return true if it is profitable to move this shift by a constant amount though its operand, adjusting any immediate operands as necessary to preserve semantics.

This transformation may not be desirable if it disrupts a particularly auspicious target-specific tree (e.g. bitfield extraction in AArch64). By default, it returns true.

Parameters

N	the shift node
Level	the current DAGCombine legalization level.

Reimplemented from llvm::TargetLowering.

Definition at line 10395 of file ARMISelLowering.cpp.

References llvm::BeforeLegalizeTypes, llvm::SDNode::getOpcode(), llvm::ARMSubtarget::isThumb(), llvm::ARMSubtarget::isThumb1Only(), and llvm::ISD::SHL.

◆ isDesirableToTransformToIntegerOp()

bool ARMTargetLowering::isDesirableToTransformToIntegerOp	(	unsigned	,
		EVT
	)		const

overridevirtual

Return true if it is profitable for dag combiner to transform a floating point op of specified opcode to a equivalent op of an integer type.

e.g. f32 load -> i32 load can be profitable on ARM.

Reimplemented from llvm::TargetLowering.

Definition at line 12933 of file ARMISelLowering.cpp.

References llvm::MVT::f32, llvm::ISD::LOAD, and llvm::ISD::STORE.

◆ isExtractSubvectorCheap()

bool ARMTargetLowering::isExtractSubvectorCheap	(	EVT	ResVT,
		EVT	SrcVT,
		unsigned	Index
	)		const

overridevirtual

Return true if EXTRACT_SUBVECTOR is cheap for this result type with this index.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 14463 of file ARMISelLowering.cpp.

References llvm::ISD::EXTRACT_SUBVECTOR, llvm::EVT::getVectorNumElements(), and llvm::TargetLoweringBase::isOperationLegalOrCustom().

◆ isFNegFree()

bool ARMTargetLowering::isFNegFree ( EVT VT ) const

overridevirtual

Return true if an fneg operation is free to the point where it is never worthwhile to replace it with a bitwise operation.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 13052 of file ARMISelLowering.cpp.

References llvm::MVT::f16, llvm::EVT::getSimpleVT(), llvm::ARMSubtarget::hasFullFP16(), llvm::EVT::isSimple(), and llvm::MVT::SimpleTy.

◆ isFPImmLegal()

bool ARMTargetLowering::isFPImmLegal	(	const APFloat &	Imm,
		EVT	VT
	)		const

overridevirtual

isFPImmLegal - Returns true if the target can instruction select the specified FP immediate natively.

If false, the legalizer will materialize the FP immediate as a load from a constant pool.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 14295 of file ARMISelLowering.cpp.

References llvm::MVT::f16, llvm::MVT::f32, llvm::MVT::f64, llvm::ARM_AM::getFP16Imm(), llvm::ARM_AM::getFP32Imm(), llvm::ARM_AM::getFP64Imm(), llvm::ARMSubtarget::hasFullFP16(), llvm::ARMSubtarget::hasVFP3(), and llvm::ARMSubtarget::isFPOnlySP().

Referenced by isNEONModifiedImm().

◆ isLegalAddImmediate()

bool ARMTargetLowering::isLegalAddImmediate ( int64_t Imm ) const

overridevirtual

isLegalAddImmediate - Return true if the specified immediate is legal add immediate, that is the target has add instructions which can add a register and the immediate without having to materialize the immediate into a register.

isLegalAddImmediate - Return true if the specified immediate is a legal add or sub immediate, that is the target has add or sub instructions which can add a register with the immediate without having to materialize the immediate into a register.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 13351 of file ARMISelLowering.cpp.

References llvm::abs(), llvm::ARM_AM::getSOImmVal(), llvm::ARM_AM::getT2SOImmVal(), llvm::ARMSubtarget::isThumb(), and llvm::ARMSubtarget::isThumb2().

◆ isLegalAddressingMode()

bool ARMTargetLowering::isLegalAddressingMode	(	const DataLayout &	DL,
		const AddrMode &	AM,
		Type *	Ty,
		unsigned	AS,
		Instruction *	I = `nullptr`
	)		const

overridevirtual

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target, for a load/store of the specified type.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 13269 of file ARMISelLowering.cpp.

References llvm::TargetLoweringBase::AddrMode::BaseGV, llvm::TargetLoweringBase::AddrMode::BaseOffs, llvm::EVT::getSimpleVT(), llvm::TargetLoweringBase::getValueType(), llvm::TargetLoweringBase::AddrMode::HasBaseReg, llvm::MVT::i1, llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i64, llvm::MVT::i8, isLegalAddressImmediate(), isLegalT1ScaledAddressingMode(), isLegalT2ScaledAddressingMode(), llvm::isPowerOf2_32(), llvm::EVT::isSimple(), llvm::ARMSubtarget::isThumb1Only(), llvm::ARMSubtarget::isThumb2(), llvm::MVT::isVoid, llvm::TargetLoweringBase::AddrMode::Scale, and llvm::MVT::SimpleTy.

Referenced by getScalingFactorCost().

◆ isLegalICmpImmediate()

bool ARMTargetLowering::isLegalICmpImmediate ( int64_t Imm ) const

overridevirtual

isLegalICmpImmediate - Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructions which can compare a register against the immediate without having to materialize the immediate into a register.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 13335 of file ARMISelLowering.cpp.

References llvm::ARM_AM::getSOImmVal(), llvm::ARM_AM::getT2SOImmVal(), llvm::ARMSubtarget::isThumb(), and llvm::ARMSubtarget::isThumb2().

Referenced by isFloatingPointZero().

◆ isLegalInterleavedAccessType()

bool ARMTargetLowering::isLegalInterleavedAccessType	(	VectorType *	VecTy,
		const DataLayout &	DL
	)		const

Returns true if VecTy is a legal interleaved access type.

This function checks the vector element type and the overall width of the vector.

Definition at line 14729 of file ARMISelLowering.cpp.

References llvm::SequentialType::getElementType(), llvm::SequentialType::getNumElements(), llvm::DataLayout::getTypeSizeInBits(), and llvm::Type::isHalfTy().

Referenced by llvm::ARMTTIImpl::getInterleavedMemoryOpCost(), lowerInterleavedLoad(), and lowerInterleavedStore().

◆ isLegalT1ScaledAddressingMode()

bool ARMTargetLowering::isLegalT1ScaledAddressingMode	(	const AddrMode &	AM,
		EVT	VT
	)		const

Returns true if the addresing mode representing by AM is legal for the Thumb1 target, for a load/store of the specified type.

Definition at line 13252 of file ARMISelLowering.cpp.

References llvm::TargetLoweringBase::AddrMode::HasBaseReg, and llvm::TargetLoweringBase::AddrMode::Scale.

Referenced by isLegalAddressingMode().

◆ isLegalT2ScaledAddressingMode()

bool ARMTargetLowering::isLegalT2ScaledAddressingMode	(	const AddrMode &	AM,
		EVT	VT
	)		const

Definition at line 13214 of file ARMISelLowering.cpp.

References llvm::EVT::getSimpleVT(), llvm::TargetLoweringBase::AddrMode::HasBaseReg, llvm::MVT::i1, llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i64, llvm::MVT::i8, llvm::isPowerOf2_32(), llvm::MVT::isVoid, llvm::TargetLoweringBase::AddrMode::Scale, and llvm::MVT::SimpleTy.

Referenced by isLegalAddressingMode().

◆ isNoopAddrSpaceCast()

bool llvm::ARMTargetLowering::isNoopAddrSpaceCast	(	unsigned	SrcAS,
		unsigned	DestAS
	)		const

inlineoverridevirtual

Returns true if a cast between SrcAS and DestAS is a noop.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 460 of file ARMISelLowering.h.

References llvm::ARM::createFastISel(), I, and Info.

◆ isOffsetFoldingLegal()

bool ARMTargetLowering::isOffsetFoldingLegal ( const GlobalAddressSDNode * GA ) const

overridevirtual

Return true if folding a constant offset with the given GlobalAddress is legal.

It is frequently not legal in PIC relocation models.

Reimplemented from llvm::TargetLowering.

Definition at line 14278 of file ARMISelLowering.cpp.

◆ isReadOnly()

bool ARMTargetLowering::isReadOnly ( const GlobalValue * GV ) const

Definition at line 3153 of file ARMISelLowering.cpp.

References llvm::ISD::ABS, llvm::ISD::ADD, llvm::Intrinsic::arm_neon_vabs, llvm::Intrinsic::arm_neon_vmaxnm, llvm::Intrinsic::arm_neon_vmaxs, llvm::Intrinsic::arm_neon_vmaxu, llvm::Intrinsic::arm_neon_vminnm, llvm::Intrinsic::arm_neon_vmins, llvm::Intrinsic::arm_neon_vminu, llvm::Intrinsic::arm_neon_vmulls, llvm::Intrinsic::arm_neon_vmullu, llvm::Intrinsic::arm_neon_vtbl1, llvm::Intrinsic::arm_neon_vtbl2, assert(), llvm::Triple::COFF, llvm::ARMCP::CPLSDA, llvm::ARMConstantPoolConstant::Create(), llvm::ARMFunctionInfo::createPICLabelUId(), llvm::ARMISD::EH_SJLJ_LONGJMP, llvm::Intrinsic::eh_sjlj_lsda, llvm::ARMISD::EH_SJLJ_SETJMP, llvm::ARMISD::EH_SJLJ_SETUP_DISPATCH, llvm::Triple::ELF, llvm::ISD::FMAXIMUM, llvm::ISD::FMAXNUM, llvm::ISD::FMINIMUM, llvm::ISD::FMINNUM, G, llvm::ARMSubtarget::genExecuteOnly(), llvm::SelectionDAG::getConstant(), llvm::MachinePointerInfo::getConstantPool(), llvm::SelectionDAG::getCopyFromReg(), llvm::SelectionDAG::getDataLayout(), llvm::SelectionDAG::getEntryNode(), llvm::MachineFunction::getFunction(), llvm::MachinePointerInfo::getGOT(), llvm::MachineFunction::getInfo(), llvm::SelectionDAG::getLoad(), llvm::SelectionDAG::getMachineFunction(), llvm::SelectionDAG::getNode(), llvm::Triple::getObjectFormat(), llvm::SDValue::getOperand(), llvm::GlobalValue::getParent(), llvm::TargetLoweringBase::getPointerTy(), llvm::SelectionDAG::getTargetConstantPool(), llvm::SelectionDAG::getTargetGlobalAddress(), llvm::TargetLoweringBase::getTargetMachine(), llvm::ARMSubtarget::getTargetTriple(), llvm::SDValue::getValueType(), llvm::SelectionDAG::getVTList(), llvm::GlobalValue::hasDLLImportStorageClass(), llvm::MVT::i32, llvm::EVT::isFloatingPoint(), llvm::ARMSubtarget::isGVIndirectSymbol(), llvm::TargetLowering::isPositionIndependent(), llvm::ARMSubtarget::isROPI(), llvm::ARMSubtarget::isRWPI(), llvm::ARMSubtarget::isTargetWindows(), llvm::ARMSubtarget::isThumb(), llvm_unreachable, llvm::Triple::MachO, llvm::ARMII::MO_COFFSTUB, llvm::ARMII::MO_DLLIMPORT, llvm::ARMII::MO_GOT, llvm::ARMII::MO_NO_FLAG, llvm::ARMII::MO_NONLAZY, llvm::ARMII::MO_SBREL, llvm::MVT::Other, llvm::ARMISD::PIC_ADD, promoteToConstantPool(), llvm::ARMCP::SBREL, llvm::TargetMachine::shouldAssumeDSOLocal(), llvm::ISD::SMAX, llvm::ISD::SMIN, llvm::ARMISD::THREAD_POINTER, llvm::Intrinsic::thread_pointer, llvm::ISD::UMAX, llvm::ISD::UMIN, llvm::ARMSubtarget::useMovt(), llvm::ARMISD::VMULLs, llvm::ARMISD::VMULLu, llvm::ARMISD::VTBL1, llvm::ARMISD::VTBL2, Wrapper, llvm::ARMISD::Wrapper, and llvm::ARMISD::WrapperPIC.

◆ isSelectSupported()

bool llvm::ARMTargetLowering::isSelectSupported ( SelectSupportKind Kind ) const

inlineoverridevirtual

Reimplemented from llvm::TargetLoweringBase.

Definition at line 295 of file ARMISelLowering.h.

References Context, and MI.

◆ isShuffleMaskLegal()

bool ARMTargetLowering::isShuffleMaskLegal	(	ArrayRef< int >	M,
		EVT	VT
	)		const

overridevirtual

isShuffleMaskLegal - Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations, those with specific masks.

By default, if a target supports the VECTOR_SHUFFLE node, all mask values are assumed to be legal.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 6784 of file ARMISelLowering.cpp.

References llvm::EVT::getScalarSizeInBits(), llvm::EVT::getVectorNumElements(), llvm::EVT::is128BitVector(), llvm::EVT::is64BitVector(), isNEONTwoResultShuffleMask(), isReverseMask(), llvm::ShuffleVectorSDNode::isSplatMask(), isVEXTMask(), isVREVMask(), isVTBLMask(), PerfectShuffleTable, llvm::MVT::v16i8, and llvm::MVT::v8i16.

Referenced by IsSingleInstrConstant().

◆ isTruncateFree() [1/2]

bool ARMTargetLowering::isTruncateFree	(	Type *	FromTy,
		Type *	ToTy
	)		const

overridevirtual

Return true if it's free to truncate a value of type FromTy to type ToTy.

e.g. On x86 it's free to truncate a i32 value in register EAX to i16 by referencing its sub-register AX. Targets must return false when FromTy <= ToTy.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 13014 of file ARMISelLowering.cpp.

References llvm::Type::getPrimitiveSizeInBits(), and llvm::Type::isIntegerTy().

◆ isTruncateFree() [2/2]

bool ARMTargetLowering::isTruncateFree	(	EVT	SrcVT,
		EVT	DstVT
	)		const

overridevirtual

Reimplemented from llvm::TargetLoweringBase.

Definition at line 13022 of file ARMISelLowering.cpp.

References llvm::EVT::getSizeInBits(), llvm::EVT::isInteger(), and llvm::EVT::isVector().

◆ isVectorLoadExtDesirable()

bool ARMTargetLowering::isVectorLoadExtDesirable ( SDValue ExtVal ) const

overridevirtual

Return true if folding a vector load into ExtVal (a sign, zero, or any extend node) is profitable.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 13070 of file ARMISelLowering.cpp.

References llvm::ISD::ADD, llvm::SDValue::getNode(), llvm::SDNode::getOpcode(), llvm::SDValue::getValueType(), llvm::SDNode::isOnlyUserOf(), llvm::TargetLoweringBase::isTypeLegal(), llvm::ISD::SHL, llvm::ISD::SUB, llvm::SDNode::use_begin(), llvm::SDNode::use_empty(), and llvm::ARMISD::VSHL.

◆ isZExtFree()

bool ARMTargetLowering::isZExtFree	(	SDValue	Val,
		EVT	VT2
	)		const

overridevirtual

Return true if zero-extending the specific node Val to type VT2 is free (either because it's implicitly zero-extended such as ARM ldrb / ldrh or because it's folded such as X86 zero-extending loads).

Reimplemented from llvm::TargetLoweringBase.

Definition at line 13031 of file ARMISelLowering.cpp.

References llvm::SDValue::getOpcode(), llvm::EVT::getSimpleVT(), llvm::SDValue::getValueType(), llvm::MVT::i1, llvm::MVT::i16, llvm::MVT::i8, llvm::EVT::isInteger(), llvm::EVT::isSimple(), llvm::ISD::LOAD, and llvm::MVT::SimpleTy.

◆ LowerAsmOperandForConstraint()

void ARMTargetLowering::LowerAsmOperandForConstraint	(	SDValue	Op,
		std::string &	Constraint,
		std::vector< SDValue > &	Ops,
		SelectionDAG &	DAG
	)		const

overridevirtual

LowerAsmOperandForConstraint - Lower the specified operand into the Ops vector.

If it is invalid, don't add anything to Ops. If hasMemory is true it means one of the asm constraint of the inline asm instruction being processed is 'm'.

If it is invalid, don't add anything to Ops.

Reimplemented from llvm::TargetLowering.

Definition at line 13903 of file ARMISelLowering.cpp.

References C, llvm::dyn_cast(), llvm::SDValue::getNode(), llvm::ConstantSDNode::getSExtValue(), llvm::ARM_AM::getSOImmVal(), llvm::ARM_AM::getT2SOImmVal(), llvm::SelectionDAG::getTargetConstant(), llvm::SDValue::getValueType(), llvm::ARMSubtarget::hasV6T2Ops(), llvm::ARMSubtarget::isThumb(), llvm::ARMSubtarget::isThumb1Only(), llvm::ARMSubtarget::isThumb2(), llvm::ARM_AM::isThumbImmShiftedVal(), and llvm::TargetLowering::LowerAsmOperandForConstraint().

◆ lowerInterleavedLoad()

bool ARMTargetLowering::lowerInterleavedLoad	(	LoadInst *	LI,
		ArrayRef< ShuffleVectorInst *>	Shuffles,
		ArrayRef< unsigned >	Indices,
		unsigned	Factor
	)		const

overridevirtual

Lower an interleaved load into a vldN intrinsic.

E.g. Lower an interleaved load (Factor = 2): wide.vec = load <8 x i32>, <8 x i32>* ptr, align 4 v0 = shuffle wide.vec, undef, <0, 2, 4, 6> ; Extract even elements v1 = shuffle wide.vec, undef, <1, 3, 5, 7> ; Extract odd elements

Into: vld2 = { <4 x i32>, <4 x i32> } call llvm.arm.neon.vld2(ptr, 4) vec0 = extractelement { <4 x i32>, <4 x i32> } vld2, i32 0 vec1 = extractelement { <4 x i32>, <4 x i32> } vld2, i32 1

Reimplemented from llvm::TargetLoweringBase.

Definition at line 14765 of file ARMISelLowering.cpp.

References llvm::Intrinsic::arm_neon_vld2, llvm::Intrinsic::arm_neon_vld3, llvm::Intrinsic::arm_neon_vld4, assert(), llvm::concatenateVectors(), llvm::IRBuilder< T, Inserter >::CreateBitCast(), llvm::IRBuilder< T, Inserter >::CreateCall(), llvm::IRBuilder< T, Inserter >::CreateConstGEP1_32(), llvm::IRBuilder< T, Inserter >::CreateExtractValue(), llvm::IRBuilder< T, Inserter >::CreateIntToPtr(), llvm::ArrayRef< T >::empty(), llvm::VectorType::get(), llvm::LoadInst::getAlignment(), llvm::Module::getDataLayout(), llvm::Intrinsic::getDeclaration(), llvm::EVT::getEVT(), llvm::IRBuilderBase::getInt32(), llvm::IRBuilderBase::getInt8PtrTy(), llvm::DataLayout::getIntPtrType(), getMaxSupportedInterleaveFactor(), llvm::Instruction::getModule(), getNumInterleavedAccesses(), llvm::LoadInst::getPointerAddressSpace(), llvm::LoadInst::getPointerOperand(), llvm::ShuffleVectorInst::getType(), llvm::Type::getVectorElementType(), llvm::Type::getVectorNumElements(), llvm::ARMSubtarget::hasNEON(), isLegalInterleavedAccessType(), llvm::Type::isPointerTy(), llvm::TargetLoweringBase::isTypeLegal(), llvm::SmallVectorTemplateBase< T >::push_back(), and llvm::ArrayRef< T >::size().

◆ lowerInterleavedStore()

bool ARMTargetLowering::lowerInterleavedStore	(	StoreInst *	SI,
		ShuffleVectorInst *	SVI,
		unsigned	Factor
	)		const

overridevirtual

Lower an interleaved store into a vstN intrinsic.

E.g. Lower an interleaved store (Factor = 3): i.vec = shuffle <8 x i32> v0, <8 x i32> v1, <0, 4, 8, 1, 5, 9, 2, 6, 10, 3, 7, 11> store <12 x i32> i.vec, <12 x i32>* ptr, align 4

Into: sub.v0 = shuffle <8 x i32> v0, <8 x i32> v1, <0, 1, 2, 3> sub.v1 = shuffle <8 x i32> v0, <8 x i32> v1, <4, 5, 6, 7> sub.v2 = shuffle <8 x i32> v0, <8 x i32> v1, <8, 9, 10, 11> call void llvm.arm.neon.vst3(ptr, sub.v0, sub.v1, sub.v2, 4)

Note that the new shufflevectors will be removed and we'll only generate one vst3 instruction in CodeGen.

Example for a more general valid mask (Factor 3). Lower: i.vec = shuffle <32 x i32> v0, <32 x i32> v1, <4, 32, 16, 5, 33, 17, 6, 34, 18, 7, 35, 19> store <12 x i32> i.vec, <12 x i32>* ptr

Into: sub.v0 = shuffle <32 x i32> v0, <32 x i32> v1, <4, 5, 6, 7> sub.v1 = shuffle <32 x i32> v0, <32 x i32> v1, <32, 33, 34, 35> sub.v2 = shuffle <32 x i32> v0, <32 x i32> v1, <16, 17, 18, 19> call void llvm.arm.neon.vst3(ptr, sub.v0, sub.v1, sub.v2, 4)

Reimplemented from llvm::TargetLoweringBase.

Definition at line 14898 of file ARMISelLowering.cpp.

References llvm::Intrinsic::arm_neon_vst2, llvm::Intrinsic::arm_neon_vst3, llvm::Intrinsic::arm_neon_vst4, assert(), llvm::IRBuilder< T, Inserter >::CreateBitCast(), llvm::IRBuilder< T, Inserter >::CreateCall(), llvm::IRBuilder< T, Inserter >::CreateConstGEP1_32(), llvm::IRBuilder< T, Inserter >::CreatePtrToInt(), llvm::createSequentialMask(), llvm::IRBuilder< T, Inserter >::CreateShuffleVector(), llvm::VectorType::get(), llvm::StoreInst::getAlignment(), llvm::Module::getDataLayout(), llvm::Intrinsic::getDeclaration(), llvm::EVT::getEVT(), llvm::IRBuilderBase::getInt32(), llvm::IRBuilderBase::getInt8PtrTy(), llvm::DataLayout::getIntPtrType(), getMaxSupportedInterleaveFactor(), llvm::Instruction::getModule(), getNumInterleavedAccesses(), llvm::User::getOperand(), llvm::StoreInst::getPointerAddressSpace(), llvm::StoreInst::getPointerOperand(), llvm::Type::getPointerTo(), llvm::ShuffleVectorInst::getShuffleMask(), llvm::Value::getType(), llvm::ShuffleVectorInst::getType(), llvm::Type::getVectorElementType(), llvm::Type::getVectorNumElements(), llvm::ARMSubtarget::hasNEON(), isLegalInterleavedAccessType(), llvm::Type::isPointerTy(), llvm::TargetLoweringBase::isTypeLegal(), llvm::BitmaskEnumDetail::Mask(), and llvm::SmallVectorTemplateBase< T >::push_back().

◆ LowerOperation()

SDValue ARMTargetLowering::LowerOperation	(	SDValue	Op,
		SelectionDAG &	DAG
	)		const

overridevirtual

This callback is invoked for operations that are unsupported by the target, which are registered to use 'custom' lowering, and whose defined values are all legal.

If the target has no operations that require custom lowering, it need not implement this. The default implementation of this aborts.

Reimplemented from llvm::TargetLowering.

Definition at line 7999 of file ARMISelLowering.cpp.

References llvm::ISD::ADDCARRY, llvm::ISD::ATOMIC_FENCE, llvm::ISD::ATOMIC_LOAD, llvm::ISD::ATOMIC_STORE, llvm::ISD::BITCAST, llvm::ISD::BlockAddress, llvm::ISD::BR_CC, llvm::ISD::BR_JT, llvm::ISD::BRCOND, llvm::ISD::BUILD_VECTOR, llvm::ISD::CONCAT_VECTORS, llvm::ISD::ConstantFP, llvm::ISD::ConstantPool, llvm::ISD::CTPOP, llvm::ISD::CTTZ, llvm::ISD::CTTZ_ZERO_UNDEF, llvm::dbgs(), llvm::SDValue::dump(), llvm::ISD::DYNAMIC_STACKALLOC, llvm::ISD::EH_SJLJ_LONGJMP, llvm::ISD::EH_SJLJ_SETJMP, llvm::ISD::EH_SJLJ_SETUP_DISPATCH, ExpandBITCAST(), llvm::ISD::EXTRACT_VECTOR_ELT, llvm::ISD::FCOPYSIGN, llvm::ISD::FLT_ROUNDS_, llvm::ISD::FP_EXTEND, llvm::ISD::FP_ROUND, llvm::ISD::FP_TO_SINT, llvm::ISD::FP_TO_UINT, llvm::ISD::FPOWI, llvm::ISD::FRAMEADDR, llvm::ISD::FSINCOS, llvm::SDValue::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getValueType(), llvm::ISD::GlobalAddress, llvm::ISD::GlobalTLSAddress, llvm::ISD::INSERT_VECTOR_ELT, llvm::ISD::INTRINSIC_WO_CHAIN, llvm::ARMSubtarget::isTargetWindows(), llvm::EVT::isVector(), LLVM_DEBUG, llvm_unreachable, LowerADDSUBCARRY(), LowerATOMIC_FENCE(), LowerAtomicLoadStore(), LowerCONCAT_VECTORS(), LowerCTPOP(), LowerCTTZ(), LowerEXTRACT_VECTOR_ELT(), LowerFPOWI(), LowerINSERT_VECTOR_ELT(), LowerMUL(), LowerPREFETCH(), LowerSDIV(), LowerSETCCCARRY(), LowerShift(), LowerUDIV(), LowerVASTART(), LowerVECTOR_SHUFFLE(), LowerVSETCC(), LowerWRITE_REGISTER(), llvm::ISD::MUL, llvm::ISD::PREFETCH, llvm::ISD::RETURNADDR, llvm::ISD::SADDO, llvm::ISD::SDIV, llvm::ISD::SDIVREM, llvm::ISD::SELECT, llvm::ISD::SELECT_CC, llvm::ISD::SETCC, llvm::ISD::SETCCCARRY, llvm::ISD::SHL, llvm::ISD::SHL_PARTS, llvm::ISD::SINT_TO_FP, llvm::ISD::SRA, llvm::ISD::SRA_PARTS, llvm::ISD::SREM, llvm::ISD::SRL, llvm::ISD::SRL_PARTS, llvm::ISD::SSUBO, llvm::ISD::SUBCARRY, llvm::ISD::UADDO, llvm::ISD::UDIV, llvm::ISD::UDIVREM, llvm::ISD::UINT_TO_FP, llvm::ISD::UREM, llvm::ISD::USUBO, llvm::ISD::VASTART, llvm::ISD::VECTOR_SHUFFLE, llvm::ARMISD::WIN__DBZCHK, and llvm::ISD::WRITE_REGISTER.

◆ LowerXConstraint()

const char * ARMTargetLowering::LowerXConstraint ( EVT ConstraintVT ) const

overridevirtual

Try to replace an X constraint, which matches anything, with another that has more specific requirements based on the type of the corresponding operand.

This returns null if there is no replacement to make.

Reimplemented from llvm::TargetLowering.

Definition at line 13763 of file ARMISelLowering.cpp.

References llvm::EVT::getSizeInBits(), llvm::ARMSubtarget::hasNEON(), llvm::ARMSubtarget::hasVFP2(), llvm::EVT::isFloatingPoint(), and llvm::EVT::isVector().

◆ makeDMB()

Instruction * ARMTargetLowering::makeDMB	(	IRBuilder<> &	Builder,
		ARM_MB::MemBOpt	Domain
	)		const

Definition at line 14471 of file ARMISelLowering.cpp.

References llvm::Intrinsic::arm_dmb, llvm::Intrinsic::arm_mcr, llvm::IRBuilder< T, Inserter >::CreateCall(), llvm::Intrinsic::getDeclaration(), llvm::IRBuilderBase::GetInsertBlock(), llvm::IRBuilderBase::getInt32(), llvm::BasicBlock::getParent(), llvm::GlobalValue::getParent(), llvm::ARMSubtarget::hasDataBarrier(), llvm::ARMSubtarget::hasV6Ops(), llvm::ARMSubtarget::isMClass(), llvm::ARMSubtarget::isThumb(), llvm_unreachable, and llvm::ARM_MB::SY.

Referenced by emitLeadingFence(), and emitTrailingFence().

◆ PerformBRCONDCombine()

SDValue ARMTargetLowering::PerformBRCONDCombine	(	SDNode *	N,
		SelectionDAG &	DAG
	)		const

PerformBRCONDCombine - Target-specific DAG combining for ARMISD::BRCOND.

Definition at line 12589 of file ARMISelLowering.cpp.

References llvm::ISD::AND, llvm::ARMISD::BRCOND, llvm::ARMISD::CMOV, llvm::ARMISD::CMPZ, llvm::dyn_cast(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::SDNode::getValueType(), llvm::SDNode::hasOneUse(), and llvm::ARMCC::NE.

Referenced by PerformDAGCombine().

◆ PerformCMOVCombine()

SDValue ARMTargetLowering::PerformCMOVCombine	(	SDNode *	N,
		SelectionDAG &	DAG
	)		const

PerformCMOVCombine - Target-specific DAG combining for ARMISD::CMOV.

FIXME: Turn this into a target neutral optimization?

Definition at line 12629 of file ARMISelLowering.cpp.

References llvm::ISD::ADDCARRY, llvm::ISD::AssertZext, llvm::ARMISD::CMOV, llvm::ARMISD::CMPZ, llvm::SelectionDAG::computeKnownBits(), llvm::ISD::CTLZ, llvm::dyn_cast(), llvm::ARMCC::EQ, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getCopyToReg(), llvm::SelectionDAG::getEntryNode(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::SDValue::getValue(), llvm::SelectionDAG::getValueType(), llvm::SDNode::getValueType(), llvm::SelectionDAG::getVTList(), llvm::SDNode::hasOneUse(), llvm::ARMSubtarget::hasV5TOps(), llvm::ARMSubtarget::hasV6T2Ops(), llvm::MVT::i1, llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i8, llvm::EVT::isInteger(), llvm::isNullConstant(), llvm::isOneConstant(), isPowerOf2Constant(), llvm::ARMSubtarget::isThumb1Only(), llvm::APInt::logBase2(), llvm::ISD::MERGE_VALUES, llvm::ARMCC::NE, PerformCMOVToBFICombine(), llvm::ISD::SETNE, llvm::ISD::SHL, llvm::ISD::SRL, llvm::ISD::SUB, llvm::ISD::SUBCARRY, llvm::ARMISD::SUBS, llvm::ISD::USUBO, and llvm::KnownBits::Zero.

Referenced by PerformDAGCombine().

◆ PerformCMOVToBFICombine()

SDValue ARMTargetLowering::PerformCMOVToBFICombine	(	SDNode *	N,
		SelectionDAG &	DAG
	)		const

◆ PerformDAGCombine()

SDValue ARMTargetLowering::PerformDAGCombine	(	SDNode *	N,
		DAGCombinerInfo &	DCI
	)		const

overridevirtual

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for.

The semantics are as follows: Return Value: SDValue.Val == 0 - No change was made SDValue.Val == N - N was replaced, is dead, and is already handled. otherwise - N should be replaced by the returned Operand.

In addition, methods provided by DAGCombinerInfo may be used to perform more complex transformations.

Reimplemented from llvm::TargetLowering.

Definition at line 12803 of file ARMISelLowering.cpp.

◆ ReplaceNodeResults()

void ARMTargetLowering::ReplaceNodeResults	(	SDNode *	N,
		SmallVectorImpl< SDValue > &	Results,
		SelectionDAG &	DAG
	)		const

overridevirtual

ReplaceNodeResults - Replace the results of node with an illegal result type with new values built out of custom code.

Reimplemented from llvm::TargetLowering.

Definition at line 8115 of file ARMISelLowering.cpp.

◆ shouldAlignPointerArgs()

bool ARMTargetLowering::shouldAlignPointerArgs	(	CallInst *	,
		unsigned &	,
		unsigned &
	)		const

overridevirtual

Return true if the pointer arguments to CI should be aligned by aligning the object whose address is being passed.

If so then MinSize is set to the minimum size the object must be to be aligned and PrefAlign is set to the preferred alignment.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 1442 of file ARMISelLowering.cpp.

References llvm::ARMSubtarget::hasV6Ops(), and llvm::ARMSubtarget::isMClass().

◆ shouldConvertConstantLoadToIntImm()

bool ARMTargetLowering::shouldConvertConstantLoadToIntImm	(	const APInt &	Imm,
		Type *	Ty
	)		const

overridevirtual

Returns true if it is beneficial to convert a load of a constant to just the constant itself.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 14453 of file ARMISelLowering.cpp.

References assert(), llvm::tgtok::Bits, llvm::Type::getPrimitiveSizeInBits(), and llvm::Type::isIntegerTy().

◆ shouldExpandAtomicCmpXchgInIR()

TargetLowering::AtomicExpansionKind ARMTargetLowering::shouldExpandAtomicCmpXchgInIR ( AtomicCmpXchgInst * AI ) const

overridevirtual

Returns how the given atomic cmpxchg should be expanded by the IR-level AtomicExpand pass.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 14579 of file ARMISelLowering.cpp.

References llvm::TargetLoweringBase::getTargetMachine(), llvm::ARMSubtarget::hasV8MBaselineOps(), llvm::ARMSubtarget::isThumb(), llvm::TargetLoweringBase::LLSC, and llvm::TargetLoweringBase::None.

◆ shouldExpandAtomicLoadInIR()

TargetLowering::AtomicExpansionKind ARMTargetLowering::shouldExpandAtomicLoadInIR ( LoadInst * LI ) const

overridevirtual

Returns how the given (atomic) load should be expanded by the IR-level AtomicExpand pass.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 14561 of file ARMISelLowering.cpp.

References llvm::Type::getPrimitiveSizeInBits(), llvm::Value::getType(), llvm::ARMSubtarget::isMClass(), llvm::TargetLoweringBase::LLOnly, and llvm::TargetLoweringBase::None.

◆ shouldExpandAtomicRMWInIR()

TargetLowering::AtomicExpansionKind ARMTargetLowering::shouldExpandAtomicRMWInIR ( AtomicRMWInst * ) const

overridevirtual

Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all.

Default is to never expand.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 14570 of file ARMISelLowering.cpp.

References llvm::Type::getPrimitiveSizeInBits(), llvm::Value::getType(), llvm::ARMSubtarget::hasV8MBaselineOps(), llvm::ARMSubtarget::isMClass(), llvm::ARMSubtarget::isThumb(), llvm::TargetLoweringBase::LLSC, and llvm::TargetLoweringBase::None.

◆ shouldExpandAtomicStoreInIR()

bool ARMTargetLowering::shouldExpandAtomicStoreInIR ( StoreInst * SI ) const

overridevirtual

Returns true if the given (atomic) store should be expanded by the IR-level AtomicExpand pass into an "atomic xchg" which ignores its input.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 14548 of file ARMISelLowering.cpp.

References llvm::Type::getPrimitiveSizeInBits(), llvm::Value::getType(), llvm::StoreInst::getValueOperand(), and llvm::ARMSubtarget::isMClass().

◆ shouldFoldShiftPairToMask()

bool ARMTargetLowering::shouldFoldShiftPairToMask	(	const SDNode *	N,
		CombineLevel	Level
	)		const

overridevirtual

Return true if it is profitable to fold a pair of shifts into a mask.

This is usually true on most targets. But some targets, like Thumb1, have immediate shift instructions, but no immediate "and" instruction; this makes the fold unprofitable.

Reimplemented from llvm::TargetLowering.

Definition at line 10414 of file ARMISelLowering.cpp.

References llvm::BeforeLegalizeTypes, and llvm::ARMSubtarget::isThumb1Only().

◆ shouldInsertFencesForAtomic()

bool ARMTargetLowering::shouldInsertFencesForAtomic ( const Instruction * I ) const

overridevirtual

Whether AtomicExpandPass should automatically insert fences and reduce ordering for this atomic.

This should be true for most architectures with weak memory ordering. Defaults to false.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 14592 of file ARMISelLowering.cpp.

◆ supportSwiftError()

bool llvm::ARMTargetLowering::supportSwiftError ( ) const

inlineoverridevirtual

Return true if the target supports swifterror attribute.

It optimizes loads and stores to reading and writing a specific register.

Reimplemented from llvm::TargetLowering.

Definition at line 563 of file ARMISelLowering.h.

Referenced by llvm::ARMBaseRegisterInfo::getCalleeSavedRegs(), and llvm::ARMBaseRegisterInfo::getCallPreservedMask().

◆ targetShrinkDemandedConstant()

bool ARMTargetLowering::targetShrinkDemandedConstant	(	SDValue	Op,
		const APInt &	Demanded,
		TargetLoweringOpt &	TLO
	)		const

overridevirtual

◆ useLoadStackGuardNode()

bool ARMTargetLowering::useLoadStackGuardNode ( ) const

overridevirtual

If this function returns true, SelectionDAGBuilder emits a LOAD_STACK_GUARD node when it is lowering Intrinsic::stackprotector.

Reimplemented from llvm::TargetLowering.

Definition at line 14598 of file ARMISelLowering.cpp.

References llvm::ARMSubtarget::isTargetMachO().

◆ useSoftFloat()

bool ARMTargetLowering::useSoftFloat ( ) const

overridevirtual

Reimplemented from llvm::TargetLoweringBase.

Definition at line 1209 of file ARMISelLowering.cpp.

References llvm::ARMSubtarget::useSoftFloat().

The documentation for this class was generated from the following files:

lib/Target/ARM/ARMISelLowering.h
lib/Target/ARM/ARMISelLowering.cpp

Public Member Functions

Protected Member Functions

Additional Inherited Members

Detailed Description

Constructor & Destructor Documentation

◆ ARMTargetLowering()

Member Function Documentation

◆ AdjustInstrPostInstrSelection()

◆ alignLoopsWithOptSize()

◆ allowsMisalignedMemoryAccesses()

◆ allowTruncateForTailCall()

◆ canCombineStoreAndExtract()

◆ canMergeStoresTo()

◆ CCAssignFnForCall()

◆ CCAssignFnForReturn()

◆ computeKnownBitsForTargetNode()

◆ convertSetCCLogicToBitwiseLogic()

◆ createFastISel()

◆ emitAtomicCmpXchgNoStoreLLBalance()

◆ EmitInstrWithCustomInserter()

◆ emitLeadingFence()

◆ emitLoadLinked()

◆ emitStoreConditional()

◆ emitTrailingFence()

◆ ExpandInlineAsm()

◆ finalizeLowering()

◆ findRepresentativeClass()

◆ functionArgumentNeedsConsecutiveRegisters()

◆ getABIAlignmentForCallingConv()

◆ getConstraintType()

◆ getExceptionPointerRegister()

◆ getExceptionSelectorRegister()

◆ getInlineAsmMemConstraint()

◆ getJumpTableEncoding()

◆ getMaxSupportedInterleaveFactor()

◆ getNumInterleavedAccesses()

◆ getOptimalMemOpType()

◆ getPostIndexedAddressParts()

◆ getPreIndexedAddressParts()

◆ getRegClassFor()

◆ getRegForInlineAsmConstraint()

◆ getScalingFactorCost()

◆ getSchedulingPreference()

◆ getSetCCResultType()

◆ getSingleConstraintMatchWeight()

◆ getSubtarget()

◆ getTargetNodeName()

◆ getTgtMemIntrinsic()

◆ hasStandaloneRem()

◆ isCheapToSpeculateCtlz()

◆ isCheapToSpeculateCttz()

◆ isDesirableToCommuteWithShift()

◆ isDesirableToTransformToIntegerOp()

◆ isExtractSubvectorCheap()

◆ isFNegFree()

◆ isFPImmLegal()

◆ isLegalAddImmediate()

◆ isLegalAddressingMode()

◆ isLegalICmpImmediate()

◆ isLegalInterleavedAccessType()

◆ isLegalT1ScaledAddressingMode()

◆ isLegalT2ScaledAddressingMode()

◆ isNoopAddrSpaceCast()

◆ isOffsetFoldingLegal()

◆ isReadOnly()

◆ isSelectSupported()

◆ isShuffleMaskLegal()

◆ isTruncateFree() [1/2]

◆ isTruncateFree() [2/2]

◆ isVectorLoadExtDesirable()

◆ isZExtFree()

◆ LowerAsmOperandForConstraint()

◆ lowerInterleavedLoad()

◆ lowerInterleavedStore()

◆ LowerOperation()

◆ LowerXConstraint()

◆ makeDMB()

◆ PerformBRCONDCombine()

◆ PerformCMOVCombine()

◆ PerformCMOVToBFICombine()