#include "Target/ARM/ARMSubtarget.h"

Inheritance diagram for llvm::ARMSubtarget:

Collaboration diagram for llvm::ARMSubtarget:

[legend]

Public Types
enum	ARMLdStMultipleTiming { DoubleIssue, DoubleIssueCheckUnalignedAccess, SingleIssue, SingleIssuePlusExtras }
	What kind of timing do load multiple/store multiple instructions have. More...

Public Member Functions
	ARMSubtarget (const Triple &TT, const std::string &CPU, const std::string &FS, const ARMBaseTargetMachine &TM, bool IsLittle)
	This constructor initializes the data members to match that of the specified triple. More...

unsigned	getMaxInlineSizeThreshold () const
	getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size that still makes it profitable to inline the call. More...

void	ParseSubtargetFeatures (StringRef CPU, StringRef FS)
	ParseSubtargetFeatures - Parses features string setting specified subtarget options. More...

ARMSubtarget &	initializeSubtargetDependencies (StringRef CPU, StringRef FS)
	initializeSubtargetDependencies - Initializes using a CPU and feature string so that we can use initializer lists for subtarget initialization. More...

const ARMSelectionDAGInfo *	getSelectionDAGInfo () const override

const ARMBaseInstrInfo *	getInstrInfo () const override

const ARMTargetLowering *	getTargetLowering () const override

const ARMFrameLowering *	getFrameLowering () const override

const ARMBaseRegisterInfo *	getRegisterInfo () const override

const CallLowering *	getCallLowering () const override

const InstructionSelector *	getInstructionSelector () const override

const LegalizerInfo *	getLegalizerInfo () const override

const RegisterBankInfo *	getRegBankInfo () const override

void	computeIssueWidth ()

bool	hasV4TOps () const

bool	hasV5TOps () const

bool	hasV5TEOps () const

bool	hasV6Ops () const

bool	hasV6MOps () const

bool	hasV6KOps () const

bool	hasV6T2Ops () const

bool	hasV7Ops () const

bool	hasV8Ops () const

bool	hasV8_1aOps () const

bool	hasV8_2aOps () const

bool	hasV8_3aOps () const

bool	hasV8_4aOps () const

bool	hasV8_5aOps () const

bool	hasV8MBaselineOps () const

bool	hasV8MMainlineOps () const

bool	hasARMOps () const

bool	hasVFP2 () const

bool	hasVFP3 () const

bool	hasVFP4 () const

bool	hasFPARMv8 () const

bool	hasNEON () const

bool	hasSHA2 () const

bool	hasAES () const

bool	hasCrypto () const

bool	hasDotProd () const

bool	hasCRC () const

bool	hasRAS () const

bool	hasVirtualization () const

bool	useNEONForSinglePrecisionFP () const

bool	hasDivideInThumbMode () const

bool	hasDivideInARMMode () const

bool	hasDataBarrier () const

bool	hasFullDataBarrier () const

bool	hasV7Clrex () const

bool	hasAcquireRelease () const

bool	hasAnyDataBarrier () const

bool	useMulOps () const

bool	useFPVMLx () const

bool	hasVMLxForwarding () const

bool	isFPBrccSlow () const

bool	isFPOnlySP () const

bool	hasPerfMon () const

bool	hasTrustZone () const

bool	has8MSecExt () const

bool	hasZeroCycleZeroing () const

bool	hasFPAO () const

bool	isProfitableToUnpredicate () const

bool	hasSlowVGETLNi32 () const

bool	hasSlowVDUP32 () const

bool	preferVMOVSR () const

bool	preferISHSTBarriers () const

bool	expandMLx () const

bool	hasVMLxHazards () const

bool	hasSlowOddRegister () const

bool	hasSlowLoadDSubregister () const

bool	useWideStrideVFP () const

bool	hasMuxedUnits () const

bool	dontWidenVMOVS () const

bool	useSplatVFPToNeon () const

bool	useNEONForFPMovs () const

bool	checkVLDnAccessAlignment () const

bool	nonpipelinedVFP () const

bool	prefers32BitThumb () const

bool	avoidCPSRPartialUpdate () const

bool	cheapPredicableCPSRDef () const

bool	avoidMOVsShifterOperand () const

bool	hasRetAddrStack () const

bool	hasBranchPredictor () const

bool	hasMPExtension () const

bool	hasDSP () const

bool	useNaClTrap () const

bool	useSjLjEH () const

bool	hasSB () const

bool	genLongCalls () const

bool	genExecuteOnly () const

bool	hasFP16 () const

bool	hasD16 () const

bool	hasFullFP16 () const

bool	hasFP16FML () const

bool	hasFuseAES () const

bool	hasFuseLiterals () const

bool	hasFusion () const
	Return true if the CPU supports any kind of instruction fusion. More...

const Triple &	getTargetTriple () const

bool	isTargetDarwin () const

bool	isTargetIOS () const

bool	isTargetWatchOS () const

bool	isTargetWatchABI () const

bool	isTargetLinux () const

bool	isTargetNaCl () const

bool	isTargetNetBSD () const

bool	isTargetWindows () const

bool	isTargetCOFF () const

bool	isTargetELF () const

bool	isTargetMachO () const

bool	isTargetAEABI () const

bool	isTargetGNUAEABI () const

bool	isTargetMuslAEABI () const

bool	isTargetEHABICompatible () const

bool	isTargetHardFloat () const

bool	isTargetAndroid () const

bool	isXRaySupported () const override

bool	isAPCS_ABI () const

bool	isAAPCS_ABI () const

bool	isAAPCS16_ABI () const

bool	isROPI () const

bool	isRWPI () const

bool	useMachineScheduler () const

bool	disablePostRAScheduler () const

bool	useSoftFloat () const

bool	isThumb () const

bool	isThumb1Only () const

bool	isThumb2 () const

bool	hasThumb2 () const

bool	isMClass () const

bool	isRClass () const

bool	isAClass () const

bool	isReadTPHard () const

bool	isR9Reserved () const

bool	useR7AsFramePointer () const

bool	splitFramePushPop (const MachineFunction &MF) const
	Returns true if the frame setup is split into two separate pushes (first r0-r7,lr then r8-r11), principally so that the frame pointer is adjacent to lr. More...

bool	useStride4VFPs (const MachineFunction &MF) const

bool	useMovt (const MachineFunction &MF) const

bool	supportsTailCall () const

bool	allowsUnalignedMem () const

bool	restrictIT () const

const std::string &	getCPUString () const

bool	isLittle () const

unsigned	getMispredictionPenalty () const

bool	enableMachineScheduler () const override
	Returns true if machine scheduler should be enabled. More...

bool	enablePostRAScheduler () const override
	True for some subtargets at > -O0. More...

bool	useAA () const override
	Enable use of alias analysis during code generation (during MI scheduling, DAGCombine, etc.). More...

bool	enableAtomicExpand () const override

const InstrItineraryData *	getInstrItineraryData () const override
	getInstrItins - Return the instruction itineraries based on subtarget selection. More...

unsigned	getStackAlignment () const
	getStackAlignment - Returns the minimum alignment known to hold of the stack frame on entry to the function and which must be maintained by every function for this subtarget. More...

unsigned	getMaxInterleaveFactor () const

unsigned	getPartialUpdateClearance () const

ARMLdStMultipleTiming	getLdStMultipleTiming () const

int	getPreISelOperandLatencyAdjustment () const

bool	isGVIndirectSymbol (const GlobalValue *GV) const
	True if the GV will be accessed via an indirect symbol. More...

bool	isGVInGOT (const GlobalValue *GV) const
	Returns the constant pool modifier needed to access the GV. More...

bool	useFastISel () const
	True if fast-isel is used. More...

unsigned	getReturnOpcode () const
	Returns the correct return opcode for the current feature set. More...

bool	allowPositionIndependentMovt () const
	Allow movt+movw for PIC global address calculation. More...

unsigned	getPrefLoopAlignment () const


bool	isCortexA5 () const

bool	isCortexA7 () const

bool	isCortexA8 () const

bool	isCortexA9 () const

bool	isCortexA15 () const

bool	isSwift () const

bool	isCortexM3 () const

bool	isLikeA9 () const

bool	isCortexR5 () const

bool	isKrait () const

Protected Types
enum	ARMProcFamilyEnum { Others, CortexA12, CortexA15, CortexA17, CortexA32, CortexA35, CortexA5, CortexA53, CortexA55, CortexA57, CortexA7, CortexA72, CortexA73, CortexA75, CortexA8, CortexA9, CortexM3, CortexR4, CortexR4F, CortexR5, CortexR52, CortexR7, Exynos, Krait, Kryo, Swift }

enum	ARMProcClassEnum { None, AClass, MClass, RClass }

enum	ARMArchEnum { ARMv2, ARMv2a, ARMv3, ARMv3m, ARMv4, ARMv4t, ARMv5, ARMv5t, ARMv5te, ARMv5tej, ARMv6, ARMv6k, ARMv6kz, ARMv6m, ARMv6sm, ARMv6t2, ARMv7a, ARMv7em, ARMv7m, ARMv7r, ARMv7ve, ARMv81a, ARMv82a, ARMv83a, ARMv84a, ARMv85a, ARMv8a, ARMv8mBaseline, ARMv8mMainline, ARMv8r }

Protected Attributes
ARMProcFamilyEnum	ARMProcFamily = Others
	ARMProcFamily - ARM processor family: Cortex-A8, Cortex-A9, and others. More...

ARMProcClassEnum	ARMProcClass = None
	ARMProcClass - ARM processor class: None, AClass, RClass or MClass. More...

ARMArchEnum	ARMArch = ARMv4t
	ARMArch - ARM architecture. More...

bool	HasV4TOps = false
	HasV4TOps, HasV5TOps, HasV5TEOps, HasV6Ops, HasV6MOps, HasV6KOps, HasV6T2Ops, HasV7Ops, HasV8Ops - Specify whether target support specific ARM ISA variants. More...

bool	HasV5TOps = false

bool	HasV5TEOps = false

bool	HasV6Ops = false

bool	HasV6MOps = false

bool	HasV6KOps = false

bool	HasV6T2Ops = false

bool	HasV7Ops = false

bool	HasV8Ops = false

bool	HasV8_1aOps = false

bool	HasV8_2aOps = false

bool	HasV8_3aOps = false

bool	HasV8_4aOps = false

bool	HasV8_5aOps = false

bool	HasV8MBaselineOps = false

bool	HasV8MMainlineOps = false

bool	HasVFPv2 = false
	HasVFPv2, HasVFPv3, HasVFPv4, HasFPARMv8, HasNEON - Specify what floating point ISAs are supported. More...

bool	HasVFPv3 = false

bool	HasVFPv4 = false

bool	HasFPARMv8 = false

bool	HasNEON = false

bool	HasDotProd = false
	HasDotProd - True if the ARMv8.2A dot product instructions are supported. More...

bool	UseNEONForSinglePrecisionFP = false
	UseNEONForSinglePrecisionFP - if the NEONFP attribute has been specified. More...

bool	UseMulOps = false
	UseMulOps - True if non-microcoded fused integer multiply-add and multiply-subtract instructions should be used. More...

bool	SlowFPVMLx = false
	SlowFPVMLx - If the VFP2 / NEON instructions are available, indicates whether the FP VML[AS] instructions are slow (if so, don't use them). More...

bool	HasVMLxForwarding = false
	HasVMLxForwarding - If true, NEON has special multiplier accumulator forwarding to allow mul + mla being issued back to back. More...

bool	SlowFPBrcc = false
	SlowFPBrcc - True if floating point compare + branch is slow. More...

bool	InThumbMode = false
	InThumbMode - True if compiling for Thumb, false for ARM. More...

bool	UseSoftFloat = false
	UseSoftFloat - True if we're using software floating point features. More...

bool	UseMISched = false
	UseMISched - True if MachineScheduler should be used for this subtarget. More...

bool	DisablePostRAScheduler = false
	DisablePostRAScheduler - False if scheduling should happen again after register allocation. More...

bool	UseAA = false
	UseAA - True if using AA during codegen (DAGCombine, MISched, etc) More...

bool	HasThumb2 = false
	HasThumb2 - True if Thumb2 instructions are supported. More...

bool	NoARM = false
	NoARM - True if subtarget does not support ARM mode execution. More...

bool	ReserveR9 = false
	ReserveR9 - True if R9 is not available as a general purpose register. More...

bool	NoMovt = false
	NoMovt - True if MOVT / MOVW pairs are not used for materialization of 32-bit imms (including global addresses). More...

bool	SupportsTailCall = false
	SupportsTailCall - True if the OS supports tail call. More...

bool	HasFP16 = false
	HasFP16 - True if subtarget supports half-precision FP conversions. More...

bool	HasFullFP16 = false
	HasFullFP16 - True if subtarget supports half-precision FP operations. More...

bool	HasFP16FML = false
	HasFP16FML - True if subtarget supports half-precision FP fml operations. More...

bool	HasD16 = false
	HasD16 - True if subtarget is limited to 16 double precision FP registers for VFPv3. More...

bool	HasHardwareDivideInThumb = false
	HasHardwareDivide - True if subtarget supports [su]div in Thumb mode. More...

bool	HasHardwareDivideInARM = false
	HasHardwareDivideInARM - True if subtarget supports [su]div in ARM mode. More...

bool	HasDataBarrier = false
	HasDataBarrier - True if the subtarget supports DMB / DSB data barrier instructions. More...

bool	HasFullDataBarrier = false
	HasFullDataBarrier - True if the subtarget supports DFB data barrier instruction. More...

bool	HasV7Clrex = false
	HasV7Clrex - True if the subtarget supports CLREX instructions. More...

bool	HasAcquireRelease = false
	HasAcquireRelease - True if the subtarget supports v8 atomics (LDA/LDAEX etc) instructions. More...

bool	Pref32BitThumb = false
	Pref32BitThumb - If true, codegen would prefer 32-bit Thumb instructions over 16-bit ones. More...

bool	AvoidCPSRPartialUpdate = false
	AvoidCPSRPartialUpdate - If true, codegen would avoid using instructions that partially update CPSR and add false dependency on the previous CPSR setting instruction. More...

bool	CheapPredicableCPSRDef = false
	CheapPredicableCPSRDef - If true, disable +1 predication cost for instructions updating CPSR. More...

bool	AvoidMOVsShifterOperand = false
	AvoidMOVsShifterOperand - If true, codegen should avoid using flag setting movs with shifter operand (i.e. More...

bool	HasRetAddrStack = false
	HasRetAddrStack - Some processors perform return stack prediction. More...

bool	HasBranchPredictor = true
	HasBranchPredictor - True if the subtarget has a branch predictor. More...

bool	HasMPExtension = false
	HasMPExtension - True if the subtarget supports Multiprocessing extension (ARMv7 only). More...

bool	HasVirtualization = false
	HasVirtualization - True if the subtarget supports the Virtualization extension. More...

bool	FPOnlySP = false
	FPOnlySP - If true, the floating point unit only supports single precision. More...

bool	HasPerfMon = false
	If true, the processor supports the Performance Monitor Extensions. More...

bool	HasTrustZone = false
	HasTrustZone - if true, processor supports TrustZone security extensions. More...

bool	Has8MSecExt = false
	Has8MSecExt - if true, processor supports ARMv8-M Security Extensions. More...

bool	HasSHA2 = false
	HasSHA2 - if true, processor supports SHA1 and SHA256. More...

bool	HasAES = false
	HasAES - if true, processor supports AES. More...

bool	HasCrypto = false
	HasCrypto - if true, processor supports Cryptography extensions. More...

bool	HasCRC = false
	HasCRC - if true, processor supports CRC instructions. More...

bool	HasRAS = false
	HasRAS - if true, the processor supports RAS extensions. More...

bool	HasZeroCycleZeroing = false
	If true, the instructions "vmov.i32 d0, #0" and "vmov.i32 q0, #0" are particularly effective at zeroing a VFP register. More...

bool	HasFPAO = false
	HasFPAO - if true, processor does positive address offset computation faster. More...

bool	HasFuseAES = false
	HasFuseAES - if true, processor executes back to back AES instruction pairs faster. More...

bool	HasFuseLiterals = false
	HasFuseLiterals - if true, processor executes back to back bottom and top halves of literal generation faster. More...

bool	IsProfitableToUnpredicate = false
	If true, if conversion may decide to leave some instructions unpredicated. More...

bool	HasSlowVGETLNi32 = false
	If true, VMOV will be favored over VGETLNi32. More...

bool	HasSlowVDUP32 = false
	If true, VMOV will be favored over VDUP. More...

bool	PreferVMOVSR = false
	If true, VMOVSR will be favored over VMOVDRR. More...

bool	PreferISHST = false
	If true, ISHST barriers will be used for Release semantics. More...

bool	SlowOddRegister = false
	If true, a VLDM/VSTM starting with an odd register number is considered to take more microops than single VLDRS/VSTRS. More...

bool	SlowLoadDSubregister = false
	If true, loading into a D subregister will be penalized. More...

bool	UseWideStrideVFP = false
	If true, use a wider stride when allocating VFP registers. More...

bool	HasMuxedUnits = false
	If true, the AGU and NEON/FPU units are multiplexed. More...

bool	DontWidenVMOVS = false
	If true, VMOVS will never be widened to VMOVD. More...

bool	SplatVFPToNeon = false
	If true, splat a register between VFP and NEON instructions. More...

bool	ExpandMLx = false
	If true, run the MLx expansion pass. More...

bool	HasVMLxHazards = false
	If true, VFP/NEON VMLA/VMLS have special RAW hazards. More...

bool	ReadTPHard = false

bool	UseNEONForFPMovs = false
	If true, VMOVRS, VMOVSR and VMOVS will be converted from VFP to NEON. More...

bool	CheckVLDnAlign = false
	If true, VLDn instructions take an extra cycle for unaligned accesses. More...

bool	NonpipelinedVFP = false
	If true, VFP instructions are not pipelined. More...

bool	StrictAlign = false
	StrictAlign - If true, the subtarget disallows unaligned memory accesses for some types. More...

bool	RestrictIT = false
	RestrictIT - If true, the subtarget disallows generation of deprecated IT blocks to conform to ARMv8 rule. More...

bool	HasDSP = false
	HasDSP - If true, the subtarget supports the DSP (saturating arith and such) instructions. More...

bool	UseNaClTrap = false
	NaCl TRAP instruction is generated instead of the regular TRAP. More...

bool	GenLongCalls = false
	Generate calls via indirect call instructions. More...

bool	GenExecuteOnly = false
	Generate code that does not contain data access to code sections. More...

bool	UnsafeFPMath = false
	Target machine allowed unsafe FP math (such as use of NEON fp) More...

bool	UseSjLjEH = false
	UseSjLjEH - If true, the target uses SjLj exception handling (e.g. iOS). More...

bool	HasSB = false
	Has speculation barrier. More...

bool	NegativeImmediates = true
	Implicitly convert an instruction to a different one if its immediates cannot be encoded. More...

unsigned	stackAlignment = 4
	stackAlignment - The minimum alignment known to hold of the stack frame on entry to the function and which must be maintained by every function. More...

std::string	CPUString
	CPUString - String name of used CPU. More...

unsigned	MaxInterleaveFactor = 1

unsigned	PartialUpdateClearance = 0
	Clearance before partial register updates (in number of instructions) More...

ARMLdStMultipleTiming	LdStMultipleTiming = SingleIssue
	What kind of timing do load multiple/store multiple have (double issue, single issue etc). More...

int	PreISelOperandLatencyAdjustment = 2
	The adjustment that we need to apply to get the operand latency from the operand cycle returned by the itinerary data for pre-ISel operands. More...

unsigned	PrefLoopAlignment = 0
	What alignment is preferred for loop bodies, in log2(bytes). More...

bool	IsLittle
	IsLittle - The target is Little Endian. More...

Triple	TargetTriple
	TargetTriple - What processor and OS we're targeting. More...

MCSchedModel	SchedModel
	SchedModel - Processor specific instruction costs. More...

InstrItineraryData	InstrItins
	Selected instruction itineraries (one entry per itinerary class.) More...

const TargetOptions &	Options
	Options passed via command line that could influence the target. More...

const ARMBaseTargetMachine &	TM

Detailed Description

Definition at line 45 of file ARMSubtarget.h.

Member Enumeration Documentation

◆ ARMArchEnum

enum llvm::ARMSubtarget::ARMArchEnum

protected

Enumerator
ARMv2
ARMv2a
ARMv3
ARMv3m
ARMv4
ARMv4t
ARMv5
ARMv5t
ARMv5te
ARMv5tej
ARMv6
ARMv6k
ARMv6kz
ARMv6m
ARMv6sm
ARMv6t2
ARMv7a
ARMv7em
ARMv7m
ARMv7r
ARMv7ve
ARMv81a
ARMv82a
ARMv83a
ARMv84a
ARMv85a
ARMv8a
ARMv8mBaseline
ARMv8mMainline
ARMv8r

Definition at line 83 of file ARMSubtarget.h.

◆ ARMLdStMultipleTiming

enum llvm::ARMSubtarget::ARMLdStMultipleTiming

What kind of timing do load multiple/store multiple instructions have.

Enumerator
DoubleIssue	Can load/store 2 registers/cycle.
DoubleIssueCheckUnalignedAccess	Can load/store 2 registers/cycle, but needs an extra cycle if the access is not 64-bit aligned.
SingleIssue	Can load/store 1 register/cycle.
SingleIssuePlusExtras	Can load/store 1 register/cycle, but needs an extra cycle for address computation and potentially also for register writeback.

Definition at line 118 of file ARMSubtarget.h.

◆ ARMProcClassEnum

enum llvm::ARMSubtarget::ARMProcClassEnum

protected

Enumerator
None
AClass
MClass
RClass

Definition at line 76 of file ARMSubtarget.h.

◆ ARMProcFamilyEnum

enum llvm::ARMSubtarget::ARMProcFamilyEnum

protected

Enumerator
Others
CortexA12
CortexA15
CortexA17
CortexA32
CortexA35
CortexA5
CortexA53
CortexA55
CortexA57
CortexA7
CortexA72
CortexA73
CortexA75
CortexA8
CortexA9
CortexM3
CortexR4
CortexR4F
CortexR5
CortexR52
CortexR7
Exynos
Krait
Kryo
Swift

Definition at line 47 of file ARMSubtarget.h.

Constructor & Destructor Documentation

◆ ARMSubtarget()

ARMSubtarget::ARMSubtarget	(	const Triple &	TT,
		const std::string &	CPU,
		const std::string &	FS,
		const ARMBaseTargetMachine &	TM,
		bool	IsLittle
	)

This constructor initializes the data members to match that of the specified triple.

Definition at line 94 of file ARMSubtarget.cpp.

References llvm::createARMInstructionSelector(), getRegisterInfo(), and getTargetLowering().

Member Function Documentation

◆ allowPositionIndependentMovt()

bool llvm::ARMSubtarget::allowPositionIndependentMovt ( ) const

inline

Allow movt+movw for PIC global address calculation.

ELF does not have GOT relocations for movt+movw. ROPI does not use GOT.

Definition at line 814 of file ARMSubtarget.h.

References isROPI(), and isTargetELF().

◆ allowsUnalignedMem()

bool llvm::ARMSubtarget::allowsUnalignedMem ( ) const

inline

Definition at line 745 of file ARMSubtarget.h.

References StrictAlign.

Referenced by llvm::ARMTargetLowering::allowsMisalignedMemoryAccesses().

◆ avoidCPSRPartialUpdate()

bool llvm::ARMSubtarget::avoidCPSRPartialUpdate ( ) const

inline

Definition at line 622 of file ARMSubtarget.h.

References AvoidCPSRPartialUpdate.

Referenced by isHighLatencyCPSR().

◆ avoidMOVsShifterOperand()

bool llvm::ARMSubtarget::avoidMOVsShifterOperand ( ) const

inline

Definition at line 624 of file ARMSubtarget.h.

References AvoidMOVsShifterOperand.

Referenced by VerifyLowRegs().

◆ cheapPredicableCPSRDef()

bool llvm::ARMSubtarget::cheapPredicableCPSRDef ( ) const

inline

Definition at line 623 of file ARMSubtarget.h.

References CheapPredicableCPSRDef.

◆ checkVLDnAccessAlignment()

bool llvm::ARMSubtarget::checkVLDnAccessAlignment ( ) const

inline

Definition at line 619 of file ARMSubtarget.h.

References CheckVLDnAlign.

Referenced by adjustDefLatency().

◆ computeIssueWidth()

void llvm::ARMSubtarget::computeIssueWidth ( )

Referenced by getRegisterInfo().

◆ disablePostRAScheduler()

bool llvm::ARMSubtarget::disablePostRAScheduler ( ) const

inline

Definition at line 710 of file ARMSubtarget.h.

References DisablePostRAScheduler.

Referenced by enablePostRAScheduler().

◆ dontWidenVMOVS()

bool llvm::ARMSubtarget::dontWidenVMOVS ( ) const

inline

Definition at line 616 of file ARMSubtarget.h.

References DontWidenVMOVS.

◆ enableAtomicExpand()

bool ARMSubtarget::enableAtomicExpand ( ) const

override

Definition at line 375 of file ARMSubtarget.cpp.

References hasAnyDataBarrier().

Referenced by useAA().

◆ enableMachineScheduler()

bool ARMSubtarget::enableMachineScheduler ( ) const

override

Returns true if machine scheduler should be enabled.

Definition at line 361 of file ARMSubtarget.cpp.

References useMachineScheduler().

Referenced by isLittle().

◆ enablePostRAScheduler()

bool ARMSubtarget::enablePostRAScheduler ( ) const

override

True for some subtargets at > -O0.

Definition at line 368 of file ARMSubtarget.cpp.

References disablePostRAScheduler(), and isThumb1Only().

Referenced by isLittle().

◆ expandMLx()

bool llvm::ARMSubtarget::expandMLx ( ) const

inline

Definition at line 610 of file ARMSubtarget.h.

References ExpandMLx.

Referenced by isFpMulInstruction().

◆ genExecuteOnly()

bool llvm::ARMSubtarget::genExecuteOnly ( ) const

inline

Definition at line 633 of file ARMSubtarget.h.

References GenExecuteOnly.

Referenced by llvm::ThumbRegisterInfo::eliminateFrameIndex(), llvm::ARMAsmPrinter::EmitInstruction(), emitThumbRegPlusImmInReg(), isExecuteOnlyFunction(), isNEONModifiedImm(), llvm::ARMTargetLowering::isReadOnly(), isXRaySupported(), llvm::ARMAsmPrinter::lowerOperand(), LowerWRITE_REGISTER(), llvm::ARMAsmPrinter::printOperand(), and useMovt().

◆ genLongCalls()

bool llvm::ARMSubtarget::genLongCalls ( ) const

inline

Definition at line 632 of file ARMSubtarget.h.

References GenLongCalls.

Referenced by llvm::ARMTargetLowering::CCAssignFnForReturn().

◆ getCallLowering()

const CallLowering * ARMSubtarget::getCallLowering ( ) const

override

Definition at line 123 of file ARMSubtarget.cpp.

Referenced by getRegisterInfo().

◆ getCPUString()

const std::string& llvm::ARMSubtarget::getCPUString ( ) const

inline

Definition at line 749 of file ARMSubtarget.h.

References CPUString.

◆ getFrameLowering()

const ARMFrameLowering* llvm::ARMSubtarget::getFrameLowering ( ) const

inlineoverride

Definition at line 499 of file ARMSubtarget.h.

Referenced by llvm::ThumbRegisterInfo::eliminateFrameIndex(), and llvm::ARMFrameLowering::emitPrologue().

◆ getInstrInfo()

const ARMBaseInstrInfo* llvm::ARMSubtarget::getInstrInfo ( ) const

inlineoverride

Definition at line 491 of file ARMSubtarget.h.

Referenced by llvm::ARMLegalizerInfo::ARMLegalizerInfo(), llvm::Thumb1FrameLowering::eliminateCallFramePseudoInstr(), llvm::ThumbRegisterInfo::eliminateFrameIndex(), llvm::Thumb1FrameLowering::emitEpilogue(), llvm::ARMTargetLowering::EmitInstrWithCustomInserter(), emitPostSt(), llvm::Thumb1FrameLowering::emitPrologue(), llvm::ARMFrameLowering::emitPrologue(), emitThumb1LoadConstPool(), findTemporariesForLR(), llvm::ARMTargetLowering::getExceptionSelectorRegister(), llvm::ARMTargetLowering::getSchedulingPreference(), isCopy(), llvm::LowerARMMachineInstrToMCInst(), MatchingStackOffset(), llvm::ARMTargetLowering::ReplaceNodeResults(), llvm::ThumbRegisterInfo::resolveFrameIndex(), llvm::Thumb1FrameLowering::restoreCalleeSavedRegisters(), llvm::ThumbRegisterInfo::saveScavengerRegister(), llvm::Thumb1FrameLowering::spillCalleeSavedRegisters(), and UpdateCPSRUse().

◆ getInstrItineraryData()

const InstrItineraryData* llvm::ARMSubtarget::getInstrItineraryData ( ) const

inlineoverride

getInstrItins - Return the instruction itineraries based on subtarget selection.

Definition at line 770 of file ARMSubtarget.h.

References InstrItins.

Referenced by llvm::ARMTargetLowering::ARMTargetLowering().

◆ getInstructionSelector()

const InstructionSelector * ARMSubtarget::getInstructionSelector ( ) const

override

Definition at line 127 of file ARMSubtarget.cpp.

Referenced by getRegisterInfo().

◆ getLdStMultipleTiming()

ARMLdStMultipleTiming llvm::ARMSubtarget::getLdStMultipleTiming ( ) const

inline

Definition at line 783 of file ARMSubtarget.h.

References LdStMultipleTiming.

◆ getLegalizerInfo()

const LegalizerInfo * ARMSubtarget::getLegalizerInfo ( ) const

override

Definition at line 131 of file ARMSubtarget.cpp.

Referenced by getRegisterInfo().

◆ getMaxInlineSizeThreshold()

unsigned llvm::ARMSubtarget::getMaxInlineSizeThreshold ( ) const

inline

getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size that still makes it profitable to inline the call.

Definition at line 475 of file ARMSubtarget.h.

References initializeSubtargetDependencies(), and ParseSubtargetFeatures().

Referenced by llvm::ARMSelectionDAGInfo::EmitTargetCodeForMemcpy().

◆ getMaxInterleaveFactor()

unsigned llvm::ARMSubtarget::getMaxInterleaveFactor ( ) const

inline

Definition at line 779 of file ARMSubtarget.h.

References MaxInterleaveFactor.

Referenced by llvm::ARMTTIImpl::getMaxInterleaveFactor().

◆ getMispredictionPenalty()

unsigned ARMSubtarget::getMispredictionPenalty ( ) const

Definition at line 357 of file ARMSubtarget.cpp.

References llvm::MCSchedModel::MispredictPenalty, and SchedModel.

Referenced by isLittle().

◆ getPartialUpdateClearance()

unsigned llvm::ARMSubtarget::getPartialUpdateClearance ( ) const

inline

Definition at line 781 of file ARMSubtarget.h.

References PartialUpdateClearance.

◆ getPrefLoopAlignment()

unsigned llvm::ARMSubtarget::getPrefLoopAlignment ( ) const

inline

Definition at line 818 of file ARMSubtarget.h.

References PrefLoopAlignment.

Referenced by llvm::ARMTargetLowering::ARMTargetLowering().

◆ getPreISelOperandLatencyAdjustment()

int llvm::ARMSubtarget::getPreISelOperandLatencyAdjustment ( ) const

inline

Definition at line 787 of file ARMSubtarget.h.

References isGVIndirectSymbol(), isGVInGOT(), PreISelOperandLatencyAdjustment, and useFastISel().

◆ getRegBankInfo()

const RegisterBankInfo * ARMSubtarget::getRegBankInfo ( ) const

override

Definition at line 135 of file ARMSubtarget.cpp.

Referenced by getRegisterInfo().

◆ getRegisterInfo()

const ARMBaseRegisterInfo* llvm::ARMSubtarget::getRegisterInfo ( ) const

inlineoverride

◆ getReturnOpcode()

unsigned llvm::ARMSubtarget::getReturnOpcode ( ) const

inline

Returns the correct return opcode for the current feature set.

Use BX if available to allow mixing thumb/arm code, but fall back to plain mov pc,lr on ARMv4.

Definition at line 803 of file ARMSubtarget.h.

References hasV4TOps(), and isThumb().

Referenced by llvm::ARMFrameLowering::adjustForSegmentedStacks(), and llvm::ARMCallLowering::lowerReturn().

◆ getSelectionDAGInfo()

const ARMSelectionDAGInfo* llvm::ARMSubtarget::getSelectionDAGInfo ( ) const

inlineoverride

Definition at line 487 of file ARMSubtarget.h.

◆ getStackAlignment()

unsigned llvm::ARMSubtarget::getStackAlignment ( ) const

inline

getStackAlignment - Returns the minimum alignment known to hold of the stack frame on entry to the function and which must be maintained by every function for this subtarget.

Definition at line 777 of file ARMSubtarget.h.

References stackAlignment.

◆ getTargetLowering()

const ARMTargetLowering* llvm::ARMSubtarget::getTargetLowering ( ) const

inlineoverride

Definition at line 495 of file ARMSubtarget.h.

Referenced by ARMSubtarget(), llvm::ARMSelectionDAGInfo::EmitSpecializedLibcall(), llvm::ARMBaseRegisterInfo::getCalleeSavedRegs(), llvm::ARMBaseRegisterInfo::getCallPreservedMask(), and InsertLDR_STR().

◆ getTargetTriple()

const Triple& llvm::ARMSubtarget::getTargetTriple ( ) const

inline

Definition at line 645 of file ARMSubtarget.h.

References TargetTriple.

Referenced by llvm::ARMTargetLowering::ARMTargetLowering(), llvm::ARMTargetLowering::isReadOnly(), isXRaySupported(), and LowerFPOWI().

◆ has8MSecExt()

bool llvm::ARMSubtarget::has8MSecExt ( ) const

inline

Definition at line 602 of file ARMSubtarget.h.

References Has8MSecExt.

◆ hasAcquireRelease()

bool llvm::ARMSubtarget::hasAcquireRelease ( ) const

inline

Definition at line 589 of file ARMSubtarget.h.

References HasAcquireRelease.

Referenced by llvm::ARMTargetLowering::ARMTargetLowering().

◆ hasAES()

bool llvm::ARMSubtarget::hasAES ( ) const

inline

Definition at line 573 of file ARMSubtarget.h.

References HasAES.

◆ hasAnyDataBarrier()

bool llvm::ARMSubtarget::hasAnyDataBarrier ( ) const

inline

Definition at line 591 of file ARMSubtarget.h.

References hasV6Ops(), and isThumb().

Referenced by llvm::ARMTargetLowering::ARMTargetLowering(), and enableAtomicExpand().

◆ hasARMOps()

bool llvm::ARMSubtarget::hasARMOps ( ) const

inline

Definition at line 565 of file ARMSubtarget.h.

References NoARM.

Referenced by llvm::ARMTargetLowering::ARMTargetLowering(), and isXRaySupported().

◆ hasBranchPredictor()

bool llvm::ARMSubtarget::hasBranchPredictor ( ) const

inline

Definition at line 626 of file ARMSubtarget.h.

References HasBranchPredictor.

Referenced by llvm::ARMTTIImpl::getUnrollingPreferences().

◆ hasCRC()

bool llvm::ARMSubtarget::hasCRC ( ) const

inline

Definition at line 576 of file ARMSubtarget.h.

References HasCRC.

◆ hasCrypto()

bool llvm::ARMSubtarget::hasCrypto ( ) const

inline

Definition at line 574 of file ARMSubtarget.h.

References HasCrypto.

◆ hasD16()

bool llvm::ARMSubtarget::hasD16 ( ) const

inline

Definition at line 636 of file ARMSubtarget.h.

References HasD16.

Referenced by llvm::ARMBaseRegisterInfo::getReservedRegs().

◆ hasDataBarrier()

bool llvm::ARMSubtarget::hasDataBarrier ( ) const

inline

Definition at line 586 of file ARMSubtarget.h.

References HasDataBarrier.

Referenced by llvm::ARMTargetLowering::ARMTargetLowering(), LowerATOMIC_FENCE(), and llvm::ARMTargetLowering::makeDMB().

◆ hasDivideInARMMode()

bool llvm::ARMSubtarget::hasDivideInARMMode ( ) const

inline

Definition at line 585 of file ARMSubtarget.h.

References HasHardwareDivideInARM.

Referenced by llvm::ARMLegalizerInfo::ARMLegalizerInfo(), llvm::ARMTargetLowering::ARMTargetLowering(), getDivRemArgList(), and LowerADDSUBCARRY().

◆ hasDivideInThumbMode()

bool llvm::ARMSubtarget::hasDivideInThumbMode ( ) const

inline

Definition at line 584 of file ARMSubtarget.h.

References HasHardwareDivideInThumb.

Referenced by llvm::ARMTargetLowering::ARMTargetLowering(), getDivRemArgList(), and LowerADDSUBCARRY().

◆ hasDotProd()

bool llvm::ARMSubtarget::hasDotProd ( ) const

inline

Definition at line 575 of file ARMSubtarget.h.

References HasDotProd.

◆ hasDSP()

bool llvm::ARMSubtarget::hasDSP ( ) const

inline

Definition at line 628 of file ARMSubtarget.h.

References HasDSP.

Referenced by AddCombineTo64bitMLAL(), AddCombineTo64BitSMLAL16(), AddCombineTo64bitUMAAL(), llvm::ARMTargetLowering::ARMTargetLowering(), getContiguousRangeOfSetBits(), PerformORCombineToBFI(), PerformORCombineToSMULWBT(), and PerformUMLALCombine().

◆ hasFP16()

bool llvm::ARMSubtarget::hasFP16 ( ) const

inline

Definition at line 635 of file ARMSubtarget.h.

References HasFP16.

Referenced by llvm::ARMTargetLowering::ARMTargetLowering().

◆ hasFP16FML()

bool llvm::ARMSubtarget::hasFP16FML ( ) const

inline

Definition at line 638 of file ARMSubtarget.h.

References HasFP16FML.

◆ hasFPAO()

bool llvm::ARMSubtarget::hasFPAO ( ) const

inline

Definition at line 604 of file ARMSubtarget.h.

References HasFPAO.

Referenced by llvm::ARMTargetLowering::getScalingFactorCost().

◆ hasFPARMv8()

bool llvm::ARMSubtarget::hasFPARMv8 ( ) const

inline

Definition at line 570 of file ARMSubtarget.h.

References HasFPARMv8.

Referenced by llvm::ARMTargetLowering::ARMTargetLowering(), getARClassRegisterMask(), and isLowerSaturatingConditional().

◆ hasFullDataBarrier()

bool llvm::ARMSubtarget::hasFullDataBarrier ( ) const

inline

Definition at line 587 of file ARMSubtarget.h.

References HasFullDataBarrier.

◆ hasFullFP16()

bool llvm::ARMSubtarget::hasFullFP16 ( ) const

inline

Definition at line 637 of file ARMSubtarget.h.

References HasFullFP16.

Referenced by llvm::ARMTargetLowering::ARMTargetLowering(), ExpandBITCAST(), llvm::ARMTargetLowering::isFNegFree(), llvm::ARMTargetLowering::isFPImmLegal(), and LowerInterruptReturn().

◆ hasFuseAES()

bool llvm::ARMSubtarget::hasFuseAES ( ) const

inline

Definition at line 640 of file ARMSubtarget.h.

References HasFuseAES.

Referenced by hasFusion(), and llvm::shouldScheduleAdjacent().

◆ hasFuseLiterals()

bool llvm::ARMSubtarget::hasFuseLiterals ( ) const

inline

Definition at line 641 of file ARMSubtarget.h.

References HasFuseLiterals.

Referenced by hasFusion(), and llvm::shouldScheduleAdjacent().

◆ hasFusion()

bool llvm::ARMSubtarget::hasFusion ( ) const

inline

Return true if the CPU supports any kind of instruction fusion.

Definition at line 643 of file ARMSubtarget.h.

References hasFuseAES(), and hasFuseLiterals().

Referenced by llvm::ARMBETargetMachine::ARMBETargetMachine().

◆ hasMPExtension()

bool llvm::ARMSubtarget::hasMPExtension ( ) const

inline

Definition at line 627 of file ARMSubtarget.h.

References HasMPExtension.

Referenced by LowerPREFETCH().

◆ hasMuxedUnits()

bool llvm::ARMSubtarget::hasMuxedUnits ( ) const

inline

Definition at line 615 of file ARMSubtarget.h.

References HasMuxedUnits.

Referenced by llvm::ARMHazardRecognizer::getHazardType().

◆ hasNEON()

bool llvm::ARMSubtarget::hasNEON ( ) const

inline

Definition at line 571 of file ARMSubtarget.h.

References HasNEON.

◆ hasPerfMon()

bool llvm::ARMSubtarget::hasPerfMon ( ) const

inline

Definition at line 600 of file ARMSubtarget.h.

References HasPerfMon.

Referenced by llvm::ARMTargetLowering::ARMTargetLowering().

◆ hasRAS()

bool llvm::ARMSubtarget::hasRAS ( ) const

inline

Definition at line 577 of file ARMSubtarget.h.

References HasRAS.

◆ hasRetAddrStack()

bool llvm::ARMSubtarget::hasRetAddrStack ( ) const

inline

Definition at line 625 of file ARMSubtarget.h.

References HasRetAddrStack.

Referenced by llvm::ARMTargetLowering::CCAssignFnForReturn().

◆ hasSB()

bool llvm::ARMSubtarget::hasSB ( ) const

inline

Definition at line 631 of file ARMSubtarget.h.

References HasSB.

◆ hasSHA2()

bool llvm::ARMSubtarget::hasSHA2 ( ) const

inline

Definition at line 572 of file ARMSubtarget.h.

References HasSHA2.

◆ hasSlowLoadDSubregister()

bool llvm::ARMSubtarget::hasSlowLoadDSubregister ( ) const

inline

Definition at line 613 of file ARMSubtarget.h.

References SlowLoadDSubregister.

Referenced by llvm::ARMTTIImpl::getVectorInstrCost().

◆ hasSlowOddRegister()

bool llvm::ARMSubtarget::hasSlowOddRegister ( ) const

inline

Definition at line 612 of file ARMSubtarget.h.

References SlowOddRegister.

◆ hasSlowVDUP32()

bool llvm::ARMSubtarget::hasSlowVDUP32 ( ) const

inline

Definition at line 607 of file ARMSubtarget.h.

References HasSlowVDUP32.

◆ hasSlowVGETLNi32()

bool llvm::ARMSubtarget::hasSlowVGETLNi32 ( ) const

inline

Definition at line 606 of file ARMSubtarget.h.

References HasSlowVGETLNi32.

◆ hasThumb2()

bool llvm::ARMSubtarget::hasThumb2 ( ) const

inline

Definition at line 715 of file ARMSubtarget.h.

References HasThumb2.

Referenced by getContiguousRangeOfSetBits(), isXRaySupported(), and PerformORCombineToSMULWBT().

◆ hasTrustZone()

bool llvm::ARMSubtarget::hasTrustZone ( ) const

inline

Definition at line 601 of file ARMSubtarget.h.

References HasTrustZone.

◆ hasV4TOps()

bool llvm::ARMSubtarget::hasV4TOps ( ) const

inline

Definition at line 533 of file ARMSubtarget.h.

References HasV4TOps.

Referenced by llvm::ARMAsmPrinter::EmitInstruction(), getReturnOpcode(), and llvm::ARMCallLowering::lowerFormalArguments().

◆ hasV5TEOps()

bool llvm::ARMSubtarget::hasV5TEOps ( ) const

inline

Definition at line 535 of file ARMSubtarget.h.

References HasV5TEOps.

Referenced by AddCombineTo64BitSMLAL16(), and LowerPREFETCH().

◆ hasV5TOps()

bool llvm::ARMSubtarget::hasV5TOps ( ) const

inline

Definition at line 534 of file ARMSubtarget.h.

References HasV5TOps.

Referenced by llvm::ARMLegalizerInfo::ARMLegalizerInfo(), llvm::ARMTargetLowering::ARMTargetLowering(), llvm::ARMTargetLowering::CCAssignFnForReturn(), llvm::ARMAsmPrinter::EmitInstruction(), findTemporariesForLR(), llvm::ARMCallLowering::lowerFormalArguments(), llvm::ARMTargetLowering::PerformCMOVCombine(), llvm::ARMFrameLowering::ResolveFrameIndexReference(), and llvm::Thumb1FrameLowering::restoreCalleeSavedRegisters().

◆ hasV6KOps()

bool llvm::ARMSubtarget::hasV6KOps ( ) const

inline

Definition at line 538 of file ARMSubtarget.h.

References HasV6KOps.

◆ hasV6MOps()

bool llvm::ARMSubtarget::hasV6MOps ( ) const

inline

Definition at line 537 of file ARMSubtarget.h.

References HasV6MOps.

◆ hasV6Ops()

bool llvm::ARMSubtarget::hasV6Ops ( ) const

inline

Definition at line 536 of file ARMSubtarget.h.

References HasV6Ops.

Referenced by AddCombineTo64bitMLAL(), AddCombineTo64bitUMAAL(), llvm::ARMTargetLowering::ARMTargetLowering(), llvm::Thumb1InstrInfo::copyPhysReg(), llvm::ARMTargetLowering::ExpandInlineAsm(), getContiguousRangeOfSetBits(), hasAnyDataBarrier(), isLowerSaturatingConditional(), isXRaySupported(), LowerATOMIC_FENCE(), llvm::ARMTargetLowering::makeDMB(), PerformORCombineToSMULWBT(), PerformShiftCombine(), PerformUMLALCombine(), llvm::ARMTargetLowering::shouldAlignPointerArgs(), and useFastISel().

◆ hasV6T2Ops()

bool llvm::ARMSubtarget::hasV6T2Ops ( ) const

inline

Definition at line 539 of file ARMSubtarget.h.

References HasV6T2Ops.

Referenced by llvm::ARMTargetLowering::ARMTargetLowering(), emitAligningInstructions(), getContiguousRangeOfSetBits(), llvm::ARMTTIImpl::getIntImmCost(), llvm::ARMTargetLowering::isCheapToSpeculateCtlz(), llvm::ARMTargetLowering::isCheapToSpeculateCttz(), isPerfectIncrement(), isXRaySupported(), llvm::ARMTargetLowering::LowerAsmOperandForConstraint(), LowerCTTZ(), llvm::ARMTargetLowering::PerformCMOVCombine(), PerformORCombineToBFI(), and llvm::ARMTargetLowering::ReplaceNodeResults().

◆ hasV7Clrex()

bool llvm::ARMSubtarget::hasV7Clrex ( ) const

inline

Definition at line 588 of file ARMSubtarget.h.

References HasV7Clrex.

◆ hasV7Ops()

bool llvm::ARMSubtarget::hasV7Ops ( ) const

inline

Definition at line 540 of file ARMSubtarget.h.

References HasV7Ops.

Referenced by llvm::ARMTargetLowering::allowsMisalignedMemoryAccesses(), emitAligningInstructions(), llvm::ARMTargetLowering::emitAtomicCmpXchgNoStoreLLBalance(), and LowerPREFETCH().

◆ hasV8_1aOps()

bool llvm::ARMSubtarget::hasV8_1aOps ( ) const

inline

Definition at line 542 of file ARMSubtarget.h.

References HasV8_1aOps.

◆ hasV8_2aOps()

bool llvm::ARMSubtarget::hasV8_2aOps ( ) const

inline

Definition at line 543 of file ARMSubtarget.h.

References HasV8_2aOps.

◆ hasV8_3aOps()

bool llvm::ARMSubtarget::hasV8_3aOps ( ) const

inline

Definition at line 544 of file ARMSubtarget.h.

References HasV8_3aOps.

◆ hasV8_4aOps()

bool llvm::ARMSubtarget::hasV8_4aOps ( ) const

inline

Definition at line 545 of file ARMSubtarget.h.

References HasV8_4aOps.

◆ hasV8_5aOps()

bool llvm::ARMSubtarget::hasV8_5aOps ( ) const

inline

Definition at line 546 of file ARMSubtarget.h.

References HasV8_5aOps.

◆ hasV8MBaselineOps()

bool llvm::ARMSubtarget::hasV8MBaselineOps ( ) const

inline

Definition at line 547 of file ARMSubtarget.h.

References HasV8MBaselineOps.

Referenced by llvm::ARMTargetLowering::ARMTargetLowering(), expandf64Toi32(), getContiguousRangeOfSetBits(), isXRaySupported(), llvm::ARMTargetLowering::shouldExpandAtomicCmpXchgInIR(), llvm::ARMTargetLowering::shouldExpandAtomicRMWInIR(), and useMovt().

◆ hasV8MMainlineOps()

bool llvm::ARMSubtarget::hasV8MMainlineOps ( ) const

inline

Definition at line 548 of file ARMSubtarget.h.

References HasV8MMainlineOps.

◆ hasV8Ops()

bool llvm::ARMSubtarget::hasV8Ops ( ) const

inline

Definition at line 541 of file ARMSubtarget.h.

References HasV8Ops.

Referenced by isXRaySupported().

◆ hasVFP2()

bool llvm::ARMSubtarget::hasVFP2 ( ) const

inline

Definition at line 567 of file ARMSubtarget.h.

References HasVFPv2.

Referenced by llvm::ARMLegalizerInfo::ARMLegalizerInfo(), llvm::ARMTargetLowering::ARMTargetLowering(), llvm::ARMBaseInstrInfo::CreateTargetPostRAHazardRecognizer(), FPCCToARMCC(), getARClassRegisterMask(), llvm::ARMBaseRegisterInfo::getSjLjDispatchPreservedMask(), isLegalAddressImmediate(), isLegalT2AddressImmediate(), llvm::ARMTargetLowering::LowerXConstraint(), selectMergeValues(), and selectUnmergeValues().

◆ hasVFP3()

bool llvm::ARMSubtarget::hasVFP3 ( ) const

inline

Definition at line 568 of file ARMSubtarget.h.

References HasVFPv3.

Referenced by llvm::ARMBaseRegisterInfo::getReservedRegs(), llvm::ARMTargetLowering::isFPImmLegal(), and isNEONModifiedImm().

◆ hasVFP4()

bool llvm::ARMSubtarget::hasVFP4 ( ) const

inline

Definition at line 569 of file ARMSubtarget.h.

References HasVFPv4.

Referenced by llvm::ARMLegalizerInfo::ARMLegalizerInfo(), and llvm::ARMTargetLowering::ARMTargetLowering().

◆ hasVirtualization()

bool llvm::ARMSubtarget::hasVirtualization ( ) const

inline

Definition at line 578 of file ARMSubtarget.h.

References HasVirtualization.

◆ hasVMLxForwarding()

bool llvm::ARMSubtarget::hasVMLxForwarding ( ) const

inline

Definition at line 597 of file ARMSubtarget.h.

References HasVMLxForwarding.

Referenced by PerformVMULCombine().

◆ hasVMLxHazards()

bool llvm::ARMSubtarget::hasVMLxHazards ( ) const

inline

Definition at line 611 of file ARMSubtarget.h.

References HasVMLxHazards.

◆ hasZeroCycleZeroing()

bool llvm::ARMSubtarget::hasZeroCycleZeroing ( ) const

inline

Definition at line 603 of file ARMSubtarget.h.

References HasZeroCycleZeroing.

◆ initializeSubtargetDependencies()

ARMSubtarget & ARMSubtarget::initializeSubtargetDependencies	(	StringRef	CPU,
		StringRef	FS
	)

initializeSubtargetDependencies - Initializes using a CPU and feature string so that we can use initializer lists for subtarget initialization.

Definition at line 78 of file ARMSubtarget.cpp.

References isThumb1Only().

Referenced by getMaxInlineSizeThreshold().

◆ isAAPCS16_ABI()

bool ARMSubtarget::isAAPCS16_ABI ( ) const

Definition at line 324 of file ARMSubtarget.cpp.

References llvm::ARMBaseTargetMachine::ARM_ABI_AAPCS16, llvm::ARMBaseTargetMachine::ARM_ABI_UNKNOWN, assert(), llvm::ARMBaseTargetMachine::TargetABI, and TM.

Referenced by isTargetAndroid(), and isXRaySupported().

◆ isAAPCS_ABI()

bool ARMSubtarget::isAAPCS_ABI ( ) const

Definition at line 319 of file ARMSubtarget.cpp.

References llvm::ARMBaseTargetMachine::ARM_ABI_AAPCS, llvm::ARMBaseTargetMachine::ARM_ABI_AAPCS16, llvm::ARMBaseTargetMachine::ARM_ABI_UNKNOWN, assert(), llvm::ARMBaseTargetMachine::TargetABI, and TM.

Referenced by llvm::ARMTargetLowering::ARMTargetLowering(), FPCCToARMCC(), isTargetAndroid(), and isXRaySupported().

◆ isAClass()

bool llvm::ARMSubtarget::isAClass ( ) const

inline

Definition at line 718 of file ARMSubtarget.h.

References AClass.

◆ isAPCS_ABI()

bool ARMSubtarget::isAPCS_ABI ( ) const

Definition at line 315 of file ARMSubtarget.cpp.

References llvm::ARMBaseTargetMachine::ARM_ABI_APCS, llvm::ARMBaseTargetMachine::ARM_ABI_UNKNOWN, assert(), llvm::ARMBaseTargetMachine::TargetABI, and TM.

Referenced by isTargetAndroid(), and LowerADDSUBCARRY().

◆ isCortexA15()

bool llvm::ARMSubtarget::isCortexA15 ( ) const

inline

Definition at line 557 of file ARMSubtarget.h.

References CortexA15.

Referenced by isLikeA9().

◆ isCortexA5()

bool llvm::ARMSubtarget::isCortexA5 ( ) const

inline

These functions are obsolete, please consider adding subtarget features or properties instead of calling them.

Definition at line 553 of file ARMSubtarget.h.

References CortexA5.

◆ isCortexA7()

bool llvm::ARMSubtarget::isCortexA7 ( ) const

inline

Definition at line 554 of file ARMSubtarget.h.

References CortexA7.

Referenced by adjustDefLatency().

◆ isCortexA8()

bool llvm::ARMSubtarget::isCortexA8 ( ) const

inline

Definition at line 555 of file ARMSubtarget.h.

References CortexA8.

Referenced by adjustDefLatency().

◆ isCortexA9()

bool llvm::ARMSubtarget::isCortexA9 ( ) const

inline

Definition at line 556 of file ARMSubtarget.h.

References CortexA9.

Referenced by isLikeA9().

◆ isCortexM3()

bool llvm::ARMSubtarget::isCortexM3 ( ) const

inline

Definition at line 559 of file ARMSubtarget.h.

References CortexM3.

◆ isCortexR5()

bool llvm::ARMSubtarget::isCortexR5 ( ) const

inline

Definition at line 561 of file ARMSubtarget.h.

References CortexR5.

◆ isFPBrccSlow()

bool llvm::ARMSubtarget::isFPBrccSlow ( ) const

inline

Definition at line 598 of file ARMSubtarget.h.

References SlowFPBrcc.

Referenced by canChangeToInt().

◆ isFPOnlySP()

bool llvm::ARMSubtarget::isFPOnlySP ( ) const

inline

Definition at line 599 of file ARMSubtarget.h.

References FPOnlySP.

Referenced by llvm::ARMTargetLowering::ARMTargetLowering(), checkVSELConstraints(), expandf64Toi32(), getDivRemArgList(), isFloatingPointZero(), llvm::ARMTargetLowering::isFPImmLegal(), isLowerSaturatingConditional(), isNEONModifiedImm(), LowerVectorFP_TO_INT(), LowerVectorINT_TO_FP(), and PerformVMOVRRDCombine().

◆ isGVIndirectSymbol()

bool ARMSubtarget::isGVIndirectSymbol ( const GlobalValue * GV ) const

True if the GV will be accessed via an indirect symbol.

Definition at line 338 of file ARMSubtarget.cpp.

References llvm::GlobalValue::getParent(), llvm::GlobalValue::hasCommonLinkage(), llvm::GlobalValue::isDeclarationForLinker(), llvm::TargetMachine::isPositionIndependent(), isTargetMachO(), llvm::TargetMachine::shouldAssumeDSOLocal(), and TM.

Referenced by getModifierVariantKind(), getPreISelOperandLatencyAdjustment(), llvm::ARMInstrInfo::getUnindexedOpcode(), and llvm::ARMTargetLowering::isReadOnly().

◆ isGVInGOT()

bool ARMSubtarget::isGVInGOT ( const GlobalValue * GV ) const

Returns the constant pool modifier needed to access the GV.

Definition at line 352 of file ARMSubtarget.cpp.

References llvm::GlobalValue::getParent(), llvm::TargetMachine::isPositionIndependent(), isTargetELF(), llvm::TargetMachine::shouldAssumeDSOLocal(), and TM.

Referenced by getPreISelOperandLatencyAdjustment().

◆ isKrait()

bool llvm::ARMSubtarget::isKrait ( ) const

inline

Definition at line 562 of file ARMSubtarget.h.

References Krait.

Referenced by isLikeA9().

◆ isLikeA9()

bool llvm::ARMSubtarget::isLikeA9 ( ) const

inline

Definition at line 560 of file ARMSubtarget.h.

References isCortexA15(), isCortexA9(), and isKrait().

Referenced by adjustDefLatency(), and isFpMulInstruction().

◆ isLittle()

bool llvm::ARMSubtarget::isLittle ( ) const

inline

Definition at line 751 of file ARMSubtarget.h.

References enableMachineScheduler(), enablePostRAScheduler(), getMispredictionPenalty(), and IsLittle.

Referenced by llvm::ARMTargetLowering::allowsMisalignedMemoryAccesses(), llvm::ARMTargetLowering::CCAssignFnForReturn(), llvm::ARMTargetLowering::emitLoadLinked(), llvm::ARMTargetLowering::emitStoreConditional(), isNEONModifiedImm(), LowerInterruptReturn(), and LowerVASTART().

◆ isMClass()

bool llvm::ARMSubtarget::isMClass ( ) const

inline

Definition at line 716 of file ARMSubtarget.h.

References MClass.

◆ isProfitableToUnpredicate()

bool llvm::ARMSubtarget::isProfitableToUnpredicate ( ) const

inline

Definition at line 605 of file ARMSubtarget.h.

References IsProfitableToUnpredicate.

◆ isR9Reserved()

bool llvm::ARMSubtarget::isR9Reserved ( ) const

inline

Definition at line 721 of file ARMSubtarget.h.

References HasV6Ops, and isTargetMachO().

Referenced by llvm::ARMBaseRegisterInfo::getRegPressureLimit(), and llvm::ARMBaseRegisterInfo::getReservedRegs().

◆ isRClass()

bool llvm::ARMSubtarget::isRClass ( ) const

inline

Definition at line 717 of file ARMSubtarget.h.

References RClass.

◆ isReadTPHard()

bool llvm::ARMSubtarget::isReadTPHard ( ) const

inline

Definition at line 719 of file ARMSubtarget.h.

References ReadTPHard.

◆ isROPI()

bool ARMSubtarget::isROPI ( ) const

Definition at line 329 of file ARMSubtarget.cpp.

References llvm::TargetMachine::getRelocationModel(), llvm::Reloc::ROPI, llvm::Reloc::ROPI_RWPI, and TM.

Referenced by allowPositionIndependentMovt(), llvm::ARMAsmPrinter::EmitJumpTableAddrs(), expandf64Toi32(), llvm::ARMTargetLowering::getJumpTableEncoding(), llvm::ARMTargetLowering::isReadOnly(), isTargetAndroid(), promoteToConstantPool(), llvm::ARMTargetLowering::ReplaceNodeResults(), and llvm::ARMTTIImpl::shouldBuildLookupTablesForConstant().

◆ isRWPI()

bool ARMSubtarget::isRWPI ( ) const

Definition at line 333 of file ARMSubtarget.cpp.

References llvm::TargetMachine::getRelocationModel(), llvm::Reloc::ROPI_RWPI, llvm::Reloc::RWPI, and TM.

Referenced by llvm::ARMTargetLowering::isReadOnly(), isTargetAndroid(), isXRaySupported(), llvm::ARMTargetLowering::ReplaceNodeResults(), and llvm::ARMTTIImpl::shouldBuildLookupTablesForConstant().

◆ isSwift()

bool llvm::ARMSubtarget::isSwift ( ) const

inline

Definition at line 558 of file ARMSubtarget.h.

References Swift.

Referenced by adjustDefLatency(), and isFpMulInstruction().

◆ isTargetAEABI()

bool llvm::ARMSubtarget::isTargetAEABI ( ) const

inline

Definition at line 667 of file ARMSubtarget.h.

References llvm::Triple::EABI, llvm::Triple::EABIHF, llvm::Triple::getEnvironment(), isTargetDarwin(), and isTargetWindows().

Referenced by AEABI(), llvm::ARMTargetLowering::ARMTargetLowering(), llvm::ARMAsmPrinter::EmitEndOfAsmFile(), and getDivRemArgList().

◆ isTargetAndroid()

bool llvm::ARMSubtarget::isTargetAndroid ( ) const

inline

Definition at line 698 of file ARMSubtarget.h.

References isAAPCS16_ABI(), isAAPCS_ABI(), llvm::Triple::isAndroid(), isAPCS_ABI(), isROPI(), isRWPI(), and isXRaySupported().

Referenced by llvm::ARMFrameLowering::adjustForSegmentedStacks(), llvm::ARMTargetLowering::ARMTargetLowering(), getDivRemArgList(), and isTargetEHABICompatible().

◆ isTargetCOFF()

bool llvm::ARMSubtarget::isTargetCOFF ( ) const

inline

Definition at line 656 of file ARMSubtarget.h.

References llvm::Triple::isOSBinFormatCOFF().

Referenced by llvm::ARMTargetLowering::CCAssignFnForReturn(), getModifierVariantKind(), and llvm::ARMAsmPrinter::runOnMachineFunction().

◆ isTargetDarwin()

bool llvm::ARMSubtarget::isTargetDarwin ( ) const

inline

Definition at line 647 of file ARMSubtarget.h.

References llvm::Triple::isOSDarwin().

Referenced by llvm::ARMTargetLowering::ARMTargetLowering(), llvm::ARMAsmPrinter::EmitInstruction(), llvm::ARMBaseRegisterInfo::getCalleeSavedRegs(), llvm::ARMBaseRegisterInfo::getCallPreservedMask(), llvm::ARMTargetLowering::getJumpTableEncoding(), llvm::ARMBaseRegisterInfo::getThisReturnPreservedMask(), llvm::ARMBaseRegisterInfo::getTLSCallPreservedMask(), llvm::ARMTTIImpl::isFPVectorizationPotentiallyUnsafe(), isTargetAEABI(), isTargetEHABICompatible(), isTargetGNUAEABI(), isTargetMuslAEABI(), isXRaySupported(), LowerADDSUBCARRY(), and useR7AsFramePointer().

◆ isTargetEHABICompatible()

bool llvm::ARMSubtarget::isTargetEHABICompatible ( ) const

inline

Definition at line 685 of file ARMSubtarget.h.

References llvm::Triple::EABI, llvm::Triple::EABIHF, llvm::Triple::getEnvironment(), llvm::Triple::GNUEABI, llvm::Triple::GNUEABIHF, isTargetAndroid(), isTargetDarwin(), isTargetHardFloat(), isTargetWindows(), llvm::Triple::MuslEABI, and llvm::Triple::MuslEABIHF.

Referenced by llvm::ARMAsmPrinter::EmitInstruction().

◆ isTargetELF()

bool llvm::ARMSubtarget::isTargetELF ( ) const

inline

Definition at line 657 of file ARMSubtarget.h.

References llvm::Triple::isOSBinFormatELF().

Referenced by allowPositionIndependentMovt(), llvm::Thumb1FrameLowering::emitPrologue(), llvm::ARMFrameLowering::emitPrologue(), llvm::ARMAsmPrinter::EmitXXStructor(), llvm::ARMTargetLowering::getJumpTableEncoding(), getModifierVariantKind(), and isGVInGOT().

◆ isTargetGNUAEABI()

bool llvm::ARMSubtarget::isTargetGNUAEABI ( ) const

inline

Definition at line 672 of file ARMSubtarget.h.

References llvm::Triple::getEnvironment(), llvm::Triple::GNUEABI, llvm::Triple::GNUEABIHF, isTargetDarwin(), and isTargetWindows().

Referenced by AEABI(), llvm::ARMTargetLowering::ARMTargetLowering(), llvm::ARMAsmPrinter::EmitEndOfAsmFile(), and getDivRemArgList().

◆ isTargetHardFloat()

bool ARMSubtarget::isTargetHardFloat ( ) const

Definition at line 313 of file ARMSubtarget.cpp.

References llvm::ARMBaseTargetMachine::isTargetHardFloat(), and TM.

Referenced by isTargetEHABICompatible(), and LowerInterruptReturn().

◆ isTargetIOS()

bool llvm::ARMSubtarget::isTargetIOS ( ) const

inline

Definition at line 648 of file ARMSubtarget.h.

References llvm::Triple::isiOS().

Referenced by llvm::ARMTargetLowering::ARMTargetLowering(), and isXRaySupported().

◆ isTargetLinux()

bool llvm::ARMSubtarget::isTargetLinux ( ) const

inline

Definition at line 651 of file ARMSubtarget.h.

References llvm::Triple::isOSLinux().

Referenced by llvm::ARMFrameLowering::adjustForSegmentedStacks(), and useFastISel().

◆ isTargetMachO()

bool llvm::ARMSubtarget::isTargetMachO ( ) const

inline

Definition at line 658 of file ARMSubtarget.h.

References llvm::Triple::isOSBinFormatMachO().

Referenced by llvm::ARMTargetLowering::ARMTargetLowering(), llvm::ARMTargetLowering::CCAssignFnForReturn(), llvm::ARMAsmPrinter::EmitInstruction(), llvm::ARMAsmPrinter::EmitMachineConstantPoolValue(), getModifierVariantKind(), isGVIndirectSymbol(), isR9Reserved(), isXRaySupported(), useFastISel(), and llvm::ARMTargetLowering::useLoadStackGuardNode().

◆ isTargetMuslAEABI()

bool llvm::ARMSubtarget::isTargetMuslAEABI ( ) const

inline

Definition at line 677 of file ARMSubtarget.h.

References llvm::Triple::getEnvironment(), isTargetDarwin(), isTargetWindows(), llvm::Triple::MuslEABI, and llvm::Triple::MuslEABIHF.

Referenced by AEABI(), llvm::ARMTargetLowering::ARMTargetLowering(), llvm::ARMAsmPrinter::EmitEndOfAsmFile(), and getDivRemArgList().

◆ isTargetNaCl()

bool llvm::ARMSubtarget::isTargetNaCl ( ) const

inline

Definition at line 652 of file ARMSubtarget.h.

References llvm::Triple::isOSNaCl().

Referenced by isXRaySupported(), and useFastISel().

◆ isTargetNetBSD()

bool llvm::ARMSubtarget::isTargetNetBSD ( ) const

inline

Definition at line 653 of file ARMSubtarget.h.

References llvm::Triple::isOSNetBSD().

◆ isTargetWatchABI()

bool llvm::ARMSubtarget::isTargetWatchABI ( ) const

inline

Definition at line 650 of file ARMSubtarget.h.

References llvm::Triple::isWatchABI().

Referenced by llvm::ARMTargetLowering::ARMTargetLowering(), isXRaySupported(), and useStride4VFPs().

◆ isTargetWatchOS()

bool llvm::ARMSubtarget::isTargetWatchOS ( ) const

inline

Definition at line 649 of file ARMSubtarget.h.

References llvm::Triple::isWatchOS().

Referenced by llvm::ARMTargetLowering::ARMTargetLowering().

◆ isTargetWindows()

bool llvm::ARMSubtarget::isTargetWindows ( ) const

inline

◆ isThumb()

bool llvm::ARMSubtarget::isThumb ( ) const

inline

Definition at line 712 of file ARMSubtarget.h.

References InThumbMode.

◆ isThumb1Only()

bool llvm::ARMSubtarget::isThumb1Only ( ) const

inline

Definition at line 713 of file ARMSubtarget.h.

References HasThumb2.

◆ isThumb2()

bool llvm::ARMSubtarget::isThumb2 ( ) const

inline

Definition at line 714 of file ARMSubtarget.h.

References HasThumb2.

◆ isXRaySupported()

bool ARMSubtarget::isXRaySupported ( ) const

override

Definition at line 139 of file ARMSubtarget.cpp.

References ARMProcFamily, assert(), llvm::tgtok::Bits, CortexA12, CortexA15, CortexA17, CortexA32, CortexA35, CortexA5, CortexA53, CortexA55, CortexA57, CortexA7, CortexA72, CortexA73, CortexA75, CortexA8, CortexA9, CortexM3, CortexR4, CortexR4F, CortexR5, CortexR52, CortexR7, CPUString, DefaultIT, DoubleIssue, DoubleIssueCheckUnalignedAccess, llvm::StringRef::empty(), llvm::TargetOptions::ExceptionModel, Exynos, genExecuteOnly(), llvm::Triple::getArchName(), llvm::MCAsmInfo::getExceptionHandlingType(), llvm::TargetMachine::getMCAsmInfo(), getTargetTriple(), hasARMOps(), hasThumb2(), hasV6Ops(), hasV6T2Ops(), hasV8MBaselineOps(), hasV8Ops(), InstrItins, isAAPCS16_ABI(), isAAPCS_ABI(), isRWPI(), isTargetDarwin(), isTargetIOS(), isTargetMachO(), isTargetNaCl(), isTargetWatchABI(), isTargetWindows(), isThumb(), IT, Krait, Kryo, LdStMultipleTiming, MaxInterleaveFactor, NoARM, NoMovt, llvm::None, NoRestrictedIT, Options, Others, llvm::ARM::parseArch(), llvm::ARM_MC::ParseARMTriple(), ParseSubtargetFeatures(), PartialUpdateClearance, PrefLoopAlignment, PreISelOperandLatencyAdjustment, ReserveR9, RestrictedIT, RestrictIT, SchedModel, SingleIssuePlusExtras, llvm::SjLj, stackAlignment, SupportsTailCall, Swift, TargetTriple, TM, llvm::TargetOptions::UnsafeFPMath, UseNEONForSinglePrecisionFP, and UseSjLjEH.

Referenced by isTargetAndroid().

◆ nonpipelinedVFP()

bool llvm::ARMSubtarget::nonpipelinedVFP ( ) const

inline

Definition at line 620 of file ARMSubtarget.h.

References NonpipelinedVFP.

◆ ParseSubtargetFeatures()

void llvm::ARMSubtarget::ParseSubtargetFeatures	(	StringRef	CPU,
		StringRef	FS
	)

ParseSubtargetFeatures - Parses features string setting specified subtarget options.

Definition of function is auto generated by tblgen.

Referenced by getMaxInlineSizeThreshold(), and isXRaySupported().

◆ preferISHSTBarriers()

bool llvm::ARMSubtarget::preferISHSTBarriers ( ) const

inline

Definition at line 609 of file ARMSubtarget.h.

References PreferISHST.

Referenced by llvm::ARMTargetLowering::emitLeadingFence(), and LowerATOMIC_FENCE().

◆ prefers32BitThumb()

bool llvm::ARMSubtarget::prefers32BitThumb ( ) const

inline

Definition at line 621 of file ARMSubtarget.h.

References Pref32BitThumb.

Referenced by UpdateCPSRUse().

◆ preferVMOVSR()

bool llvm::ARMSubtarget::preferVMOVSR ( ) const

inline

Definition at line 608 of file ARMSubtarget.h.

References PreferVMOVSR.

◆ restrictIT()

bool llvm::ARMSubtarget::restrictIT ( ) const

inline

Definition at line 747 of file ARMSubtarget.h.

References RestrictIT.

Referenced by isCopy(), and llvm::ARMBaseInstrInfo::isPredicable().

◆ splitFramePushPop()

bool llvm::ARMSubtarget::splitFramePushPop ( const MachineFunction & MF ) const

inline

Returns true if the frame setup is split into two separate pushes (first r0-r7,lr then r8-r11), principally so that the frame pointer is adjacent to lr.

This is always required on Thumb1-only targets, as the push and pop instructions can't access the high registers.

Definition at line 733 of file ARMSubtarget.h.

References llvm::TargetOptions::DisableFramePointerElim(), llvm::MachineFunction::getTarget(), isThumb1Only(), llvm::TargetMachine::Options, useMovt(), useR7AsFramePointer(), and useStride4VFPs().

Referenced by llvm::ARMFrameLowering::determineCalleeSaves(), llvm::Thumb1FrameLowering::emitPrologue(), llvm::ARMFrameLowering::emitPrologue(), llvm::ARMBaseRegisterInfo::getCalleeSavedRegs(), and llvm::ARMFrameLowering::ResolveFrameIndexReference().

◆ supportsTailCall()

bool llvm::ARMSubtarget::supportsTailCall ( ) const

inline

Definition at line 743 of file ARMSubtarget.h.

References SupportsTailCall.

Referenced by llvm::ARMTargetLowering::CCAssignFnForReturn(), LowerInterruptReturn(), and MatchingStackOffset().

◆ useAA()

bool llvm::ARMSubtarget::useAA ( ) const

inlineoverride

Enable use of alias analysis during code generation (during MI scheduling, DAGCombine, etc.).

Definition at line 763 of file ARMSubtarget.h.

References enableAtomicExpand(), and UseAA.

◆ useFastISel()

bool ARMSubtarget::useFastISel ( ) const

True if fast-isel is used.

Definition at line 393 of file ARMSubtarget.cpp.

References llvm::TargetOptions::EnableFastISel, ForceFastISel, hasV6Ops(), isTargetLinux(), isTargetMachO(), isTargetNaCl(), isThumb(), isThumb1Only(), llvm::TargetMachine::Options, and TM.

Referenced by llvm::ARM::createFastISel(), and getPreISelOperandLatencyAdjustment().

◆ useFPVMLx()

bool llvm::ARMSubtarget::useFPVMLx ( ) const

inline

Definition at line 596 of file ARMSubtarget.h.

References SlowFPVMLx.

◆ useMachineScheduler()

bool llvm::ARMSubtarget::useMachineScheduler ( ) const

inline

Definition at line 709 of file ARMSubtarget.h.

References UseMISched.

Referenced by enableMachineScheduler().

◆ useMovt()

bool ARMSubtarget::useMovt ( const MachineFunction & MF ) const

Definition at line 385 of file ARMSubtarget.cpp.

References genExecuteOnly(), llvm::MachineFunction::getFunction(), hasV8MBaselineOps(), isTargetWindows(), NoMovt, and llvm::Function::optForMinSize().

Referenced by emitPostSt(), llvm::ARMInstrInfo::getUnindexedOpcode(), llvm::ARMTargetLowering::isReadOnly(), and splitFramePushPop().

◆ useMulOps()

bool llvm::ARMSubtarget::useMulOps ( ) const

inline

Definition at line 595 of file ARMSubtarget.h.

References UseMulOps.

Referenced by AddCombineTo64bitMLAL().

◆ useNaClTrap()

bool llvm::ARMSubtarget::useNaClTrap ( ) const

inline

Definition at line 629 of file ARMSubtarget.h.

References UseNaClTrap.

Referenced by llvm::ARMTargetLowering::ReplaceNodeResults().

◆ useNEONForFPMovs()

bool llvm::ARMSubtarget::useNEONForFPMovs ( ) const

inline

Definition at line 618 of file ARMSubtarget.h.

References UseNEONForFPMovs.

◆ useNEONForSinglePrecisionFP()

bool llvm::ARMSubtarget::useNEONForSinglePrecisionFP ( ) const

inline

Definition at line 580 of file ARMSubtarget.h.

References hasNEON(), and UseNEONForSinglePrecisionFP.

Referenced by llvm::ARMTargetLowering::findRepresentativeClass(), and isNEONModifiedImm().

◆ useR7AsFramePointer()

bool llvm::ARMSubtarget::useR7AsFramePointer ( ) const

inline

Definition at line 725 of file ARMSubtarget.h.

References isTargetDarwin(), isTargetWindows(), and isThumb().

Referenced by llvm::ARMAsmPrinter::EmitInstruction(), findTemporariesForLR(), getFramePointerReg(), and splitFramePushPop().

◆ useSjLjEH()

bool llvm::ARMSubtarget::useSjLjEH ( ) const

inline

Definition at line 630 of file ARMSubtarget.h.

References UseSjLjEH.

Referenced by llvm::ARMTargetLowering::ARMTargetLowering(), llvm::ARMTargetLowering::getExceptionPointerRegister(), and llvm::ARMTargetLowering::getExceptionSelectorRegister().

◆ useSoftFloat()

bool llvm::ARMSubtarget::useSoftFloat ( ) const

inline

Definition at line 711 of file ARMSubtarget.h.

References UseSoftFloat.

Referenced by llvm::ARMLegalizerInfo::ARMLegalizerInfo(), llvm::ARMTargetLowering::ARMTargetLowering(), llvm::ARMBaseRegisterInfo::getSjLjDispatchPreservedMask(), and llvm::ARMTargetLowering::useSoftFloat().

◆ useSplatVFPToNeon()

bool llvm::ARMSubtarget::useSplatVFPToNeon ( ) const

inline

Definition at line 617 of file ARMSubtarget.h.

References SplatVFPToNeon.

◆ useStride4VFPs()

bool ARMSubtarget::useStride4VFPs ( const MachineFunction & MF ) const

Definition at line 377 of file ARMSubtarget.cpp.

References llvm::MachineFunction::getFunction(), isTargetWatchABI(), llvm::Function::optForMinSize(), and useWideStrideVFP().

Referenced by splitFramePushPop().

◆ useWideStrideVFP()

bool llvm::ARMSubtarget::useWideStrideVFP ( ) const

inline

Definition at line 614 of file ARMSubtarget.h.

References UseWideStrideVFP.

Referenced by useStride4VFPs().

Member Data Documentation

◆ ARMArch

ARMArchEnum llvm::ARMSubtarget::ARMArch = ARMv4t

protected

ARMArch - ARM architecture.

Definition at line 139 of file ARMSubtarget.h.

◆ ARMProcClass

ARMProcClassEnum llvm::ARMSubtarget::ARMProcClass = None

protected

ARMProcClass - ARM processor class: None, AClass, RClass or MClass.

Definition at line 136 of file ARMSubtarget.h.

◆ ARMProcFamily

ARMProcFamilyEnum llvm::ARMSubtarget::ARMProcFamily = Others

protected

ARMProcFamily - ARM processor family: Cortex-A8, Cortex-A9, and others.

Definition at line 133 of file ARMSubtarget.h.

Referenced by isXRaySupported().

◆ AvoidCPSRPartialUpdate

bool llvm::ARMSubtarget::AvoidCPSRPartialUpdate = false

protected

AvoidCPSRPartialUpdate - If true, codegen would avoid using instructions that partially update CPSR and add false dependency on the previous CPSR setting instruction.

Definition at line 267 of file ARMSubtarget.h.

Referenced by avoidCPSRPartialUpdate().

◆ AvoidMOVsShifterOperand

bool llvm::ARMSubtarget::AvoidMOVsShifterOperand = false

protected

AvoidMOVsShifterOperand - If true, codegen should avoid using flag setting movs with shifter operand (i.e.

asr, lsl, lsr).

Definition at line 275 of file ARMSubtarget.h.

Referenced by avoidMOVsShifterOperand().

◆ CheapPredicableCPSRDef

bool llvm::ARMSubtarget::CheapPredicableCPSRDef = false

protected

CheapPredicableCPSRDef - If true, disable +1 predication cost for instructions updating CPSR.

Enabled for Cortex-A57.

Definition at line 271 of file ARMSubtarget.h.

Referenced by cheapPredicableCPSRDef().

◆ CheckVLDnAlign

bool llvm::ARMSubtarget::CheckVLDnAlign = false

protected

If true, VLDn instructions take an extra cycle for unaligned accesses.

Definition at line 386 of file ARMSubtarget.h.

Referenced by checkVLDnAccessAlignment().

◆ CPUString

std::string llvm::ARMSubtarget::CPUString

protected

CPUString - String name of used CPU.

Definition at line 431 of file ARMSubtarget.h.

Referenced by getCPUString(), and isXRaySupported().

◆ DisablePostRAScheduler

bool llvm::ARMSubtarget::DisablePostRAScheduler = false

protected

DisablePostRAScheduler - False if scheduling should happen again after register allocation.

Definition at line 203 of file ARMSubtarget.h.

Referenced by disablePostRAScheduler().

◆ DontWidenVMOVS

bool llvm::ARMSubtarget::DontWidenVMOVS = false

protected

If true, VMOVS will never be widened to VMOVD.

Definition at line 368 of file ARMSubtarget.h.

Referenced by dontWidenVMOVS().

◆ ExpandMLx

bool llvm::ARMSubtarget::ExpandMLx = false

protected

If true, run the MLx expansion pass.

Definition at line 374 of file ARMSubtarget.h.

Referenced by expandMLx().

◆ FPOnlySP

bool llvm::ARMSubtarget::FPOnlySP = false

protected

FPOnlySP - If true, the floating point unit only supports single precision.

Definition at line 296 of file ARMSubtarget.h.

Referenced by isFPOnlySP().

◆ GenExecuteOnly

bool llvm::ARMSubtarget::GenExecuteOnly = false

protected

Generate code that does not contain data access to code sections.

Definition at line 411 of file ARMSubtarget.h.

Referenced by genExecuteOnly().

◆ GenLongCalls

bool llvm::ARMSubtarget::GenLongCalls = false

protected

Generate calls via indirect call instructions.

Definition at line 408 of file ARMSubtarget.h.

Referenced by genLongCalls().

◆ Has8MSecExt

bool llvm::ARMSubtarget::Has8MSecExt = false

protected

Has8MSecExt - if true, processor supports ARMv8-M Security Extensions.

Definition at line 307 of file ARMSubtarget.h.

Referenced by has8MSecExt().

◆ HasAcquireRelease

bool llvm::ARMSubtarget::HasAcquireRelease = false

protected

HasAcquireRelease - True if the subtarget supports v8 atomics (LDA/LDAEX etc) instructions.

Definition at line 258 of file ARMSubtarget.h.

Referenced by hasAcquireRelease().

◆ HasAES

bool llvm::ARMSubtarget::HasAES = false

protected

HasAES - if true, processor supports AES.

Definition at line 313 of file ARMSubtarget.h.

Referenced by hasAES().

◆ HasBranchPredictor

bool llvm::ARMSubtarget::HasBranchPredictor = true

protected

HasBranchPredictor - True if the subtarget has a branch predictor.

Having a branch predictor or not changes the expected cost of taking a branch which affects the choice of whether to use predicated instructions.

Definition at line 284 of file ARMSubtarget.h.

Referenced by hasBranchPredictor().

◆ HasCRC

bool llvm::ARMSubtarget::HasCRC = false

protected

HasCRC - if true, processor supports CRC instructions.

Definition at line 319 of file ARMSubtarget.h.

Referenced by hasCRC().

◆ HasCrypto

bool llvm::ARMSubtarget::HasCrypto = false

protected

HasCrypto - if true, processor supports Cryptography extensions.

Definition at line 316 of file ARMSubtarget.h.

Referenced by hasCrypto().

◆ HasD16

bool llvm::ARMSubtarget::HasD16 = false

protected

HasD16 - True if subtarget is limited to 16 double precision FP registers for VFPv3.

Definition at line 237 of file ARMSubtarget.h.

Referenced by hasD16().

◆ HasDataBarrier

bool llvm::ARMSubtarget::HasDataBarrier = false

protected

HasDataBarrier - True if the subtarget supports DMB / DSB data barrier instructions.

Definition at line 247 of file ARMSubtarget.h.

Referenced by hasDataBarrier().

◆ HasDotProd

bool llvm::ARMSubtarget::HasDotProd = false

protected

HasDotProd - True if the ARMv8.2A dot product instructions are supported.

Definition at line 170 of file ARMSubtarget.h.

Referenced by hasDotProd().

◆ HasDSP

bool llvm::ARMSubtarget::HasDSP = false

protected

HasDSP - If true, the subtarget supports the DSP (saturating arith and such) instructions.

Definition at line 402 of file ARMSubtarget.h.

Referenced by hasDSP().

◆ HasFP16

bool llvm::ARMSubtarget::HasFP16 = false

protected

HasFP16 - True if subtarget supports half-precision FP conversions.

Definition at line 227 of file ARMSubtarget.h.

Referenced by hasFP16().

◆ HasFP16FML

bool llvm::ARMSubtarget::HasFP16FML = false

protected

HasFP16FML - True if subtarget supports half-precision FP fml operations.

Definition at line 233 of file ARMSubtarget.h.

Referenced by hasFP16FML().

◆ HasFPAO

bool llvm::ARMSubtarget::HasFPAO = false

protected

HasFPAO - if true, processor does positive address offset computation faster.

Definition at line 329 of file ARMSubtarget.h.

Referenced by hasFPAO().

◆ HasFPARMv8

bool llvm::ARMSubtarget::HasFPARMv8 = false

protected

Definition at line 166 of file ARMSubtarget.h.

Referenced by hasFPARMv8().

◆ HasFullDataBarrier

bool llvm::ARMSubtarget::HasFullDataBarrier = false

protected

HasFullDataBarrier - True if the subtarget supports DFB data barrier instruction.

Definition at line 251 of file ARMSubtarget.h.

Referenced by hasFullDataBarrier().

◆ HasFullFP16

bool llvm::ARMSubtarget::HasFullFP16 = false

protected

HasFullFP16 - True if subtarget supports half-precision FP operations.

Definition at line 230 of file ARMSubtarget.h.

Referenced by hasFullFP16().

◆ HasFuseAES

bool llvm::ARMSubtarget::HasFuseAES = false

protected

HasFuseAES - if true, processor executes back to back AES instruction pairs faster.

Definition at line 333 of file ARMSubtarget.h.

Referenced by hasFuseAES().

◆ HasFuseLiterals

bool llvm::ARMSubtarget::HasFuseLiterals = false

protected

HasFuseLiterals - if true, processor executes back to back bottom and top halves of literal generation faster.

Definition at line 337 of file ARMSubtarget.h.

Referenced by hasFuseLiterals().

◆ HasHardwareDivideInARM

bool llvm::ARMSubtarget::HasHardwareDivideInARM = false

protected

HasHardwareDivideInARM - True if subtarget supports [su]div in ARM mode.

Definition at line 243 of file ARMSubtarget.h.

Referenced by hasDivideInARMMode().

◆ HasHardwareDivideInThumb

bool llvm::ARMSubtarget::HasHardwareDivideInThumb = false

protected

HasHardwareDivide - True if subtarget supports [su]div in Thumb mode.

Definition at line 240 of file ARMSubtarget.h.

Referenced by hasDivideInThumbMode().

◆ HasMPExtension

bool llvm::ARMSubtarget::HasMPExtension = false

protected

HasMPExtension - True if the subtarget supports Multiprocessing extension (ARMv7 only).

Definition at line 288 of file ARMSubtarget.h.

Referenced by hasMPExtension().

◆ HasMuxedUnits

bool llvm::ARMSubtarget::HasMuxedUnits = false

protected

If true, the AGU and NEON/FPU units are multiplexed.

Definition at line 365 of file ARMSubtarget.h.

Referenced by hasMuxedUnits().

◆ HasNEON

bool llvm::ARMSubtarget::HasNEON = false

protected

Definition at line 167 of file ARMSubtarget.h.

Referenced by hasNEON().

◆ HasPerfMon

bool llvm::ARMSubtarget::HasPerfMon = false

protected

If true, the processor supports the Performance Monitor Extensions.

These include a generic cycle-counter as well as more fine-grained (often implementation-specific) events.

Definition at line 301 of file ARMSubtarget.h.

Referenced by hasPerfMon().

◆ HasRAS

bool llvm::ARMSubtarget::HasRAS = false

protected

HasRAS - if true, the processor supports RAS extensions.

Definition at line 322 of file ARMSubtarget.h.

Referenced by hasRAS().

◆ HasRetAddrStack

bool llvm::ARMSubtarget::HasRetAddrStack = false

protected

HasRetAddrStack - Some processors perform return stack prediction.

CodeGen should avoid issue "normal" call instructions to callees which do not return.

Definition at line 279 of file ARMSubtarget.h.

Referenced by hasRetAddrStack().

◆ HasSB

bool llvm::ARMSubtarget::HasSB = false

protected

Has speculation barrier.

Definition at line 420 of file ARMSubtarget.h.

Referenced by hasSB().

◆ HasSHA2

bool llvm::ARMSubtarget::HasSHA2 = false

protected

HasSHA2 - if true, processor supports SHA1 and SHA256.

Definition at line 310 of file ARMSubtarget.h.

Referenced by hasSHA2().

◆ HasSlowVDUP32

bool llvm::ARMSubtarget::HasSlowVDUP32 = false

protected

If true, VMOV will be favored over VDUP.

Definition at line 346 of file ARMSubtarget.h.

Referenced by hasSlowVDUP32().

◆ HasSlowVGETLNi32

bool llvm::ARMSubtarget::HasSlowVGETLNi32 = false

protected

If true, VMOV will be favored over VGETLNi32.

Definition at line 343 of file ARMSubtarget.h.

Referenced by hasSlowVGETLNi32().

◆ HasThumb2

bool llvm::ARMSubtarget::HasThumb2 = false

protected

HasThumb2 - True if Thumb2 instructions are supported.

Definition at line 209 of file ARMSubtarget.h.

Referenced by hasThumb2(), isThumb1Only(), and isThumb2().

◆ HasTrustZone

bool llvm::ARMSubtarget::HasTrustZone = false

protected

HasTrustZone - if true, processor supports TrustZone security extensions.

Definition at line 304 of file ARMSubtarget.h.

Referenced by hasTrustZone().

◆ HasV4TOps

bool llvm::ARMSubtarget::HasV4TOps = false

protected

HasV4TOps, HasV5TOps, HasV5TEOps, HasV6Ops, HasV6MOps, HasV6KOps, HasV6T2Ops, HasV7Ops, HasV8Ops - Specify whether target support specific ARM ISA variants.

Definition at line 144 of file ARMSubtarget.h.

Referenced by hasV4TOps().

◆ HasV5TEOps

bool llvm::ARMSubtarget::HasV5TEOps = false

protected

Definition at line 146 of file ARMSubtarget.h.

Referenced by hasV5TEOps().

◆ HasV5TOps

bool llvm::ARMSubtarget::HasV5TOps = false

protected

Definition at line 145 of file ARMSubtarget.h.

Referenced by hasV5TOps().

◆ HasV6KOps

bool llvm::ARMSubtarget::HasV6KOps = false

protected

Definition at line 149 of file ARMSubtarget.h.

Referenced by hasV6KOps().

◆ HasV6MOps

bool llvm::ARMSubtarget::HasV6MOps = false

protected

Definition at line 148 of file ARMSubtarget.h.

Referenced by hasV6MOps().

◆ HasV6Ops

bool llvm::ARMSubtarget::HasV6Ops = false

protected

Definition at line 147 of file ARMSubtarget.h.

Referenced by hasV6Ops(), and isR9Reserved().

◆ HasV6T2Ops

bool llvm::ARMSubtarget::HasV6T2Ops = false

protected

Definition at line 150 of file ARMSubtarget.h.

Referenced by hasV6T2Ops().

◆ HasV7Clrex

bool llvm::ARMSubtarget::HasV7Clrex = false

protected

HasV7Clrex - True if the subtarget supports CLREX instructions.

Definition at line 254 of file ARMSubtarget.h.

Referenced by hasV7Clrex().

◆ HasV7Ops

bool llvm::ARMSubtarget::HasV7Ops = false

protected

Definition at line 151 of file ARMSubtarget.h.

Referenced by hasV7Ops().

◆ HasV8_1aOps

bool llvm::ARMSubtarget::HasV8_1aOps = false

protected

Definition at line 153 of file ARMSubtarget.h.

Referenced by hasV8_1aOps().

◆ HasV8_2aOps

bool llvm::ARMSubtarget::HasV8_2aOps = false

protected

Definition at line 154 of file ARMSubtarget.h.

Referenced by hasV8_2aOps().

◆ HasV8_3aOps

bool llvm::ARMSubtarget::HasV8_3aOps = false

protected

Definition at line 155 of file ARMSubtarget.h.

Referenced by hasV8_3aOps().

◆ HasV8_4aOps

bool llvm::ARMSubtarget::HasV8_4aOps = false

protected

Definition at line 156 of file ARMSubtarget.h.

Referenced by hasV8_4aOps().

◆ HasV8_5aOps

bool llvm::ARMSubtarget::HasV8_5aOps = false

protected

Definition at line 157 of file ARMSubtarget.h.

Referenced by hasV8_5aOps().

◆ HasV8MBaselineOps

bool llvm::ARMSubtarget::HasV8MBaselineOps = false

protected

Definition at line 158 of file ARMSubtarget.h.

Referenced by hasV8MBaselineOps().

◆ HasV8MMainlineOps

bool llvm::ARMSubtarget::HasV8MMainlineOps = false

protected

Definition at line 159 of file ARMSubtarget.h.

Referenced by hasV8MMainlineOps().

◆ HasV8Ops

bool llvm::ARMSubtarget::HasV8Ops = false

protected

Definition at line 152 of file ARMSubtarget.h.

Referenced by hasV8Ops().

◆ HasVFPv2

bool llvm::ARMSubtarget::HasVFPv2 = false

protected

HasVFPv2, HasVFPv3, HasVFPv4, HasFPARMv8, HasNEON - Specify what floating point ISAs are supported.

Definition at line 163 of file ARMSubtarget.h.

Referenced by hasVFP2().

◆ HasVFPv3

bool llvm::ARMSubtarget::HasVFPv3 = false

protected

Definition at line 164 of file ARMSubtarget.h.

Referenced by hasVFP3().

◆ HasVFPv4

bool llvm::ARMSubtarget::HasVFPv4 = false

protected

Definition at line 165 of file ARMSubtarget.h.

Referenced by hasVFP4().

◆ HasVirtualization

bool llvm::ARMSubtarget::HasVirtualization = false

protected

HasVirtualization - True if the subtarget supports the Virtualization extension.

Definition at line 292 of file ARMSubtarget.h.

Referenced by hasVirtualization().

◆ HasVMLxForwarding

bool llvm::ARMSubtarget::HasVMLxForwarding = false

protected

HasVMLxForwarding - If true, NEON has special multiplier accumulator forwarding to allow mul + mla being issued back to back.

Definition at line 187 of file ARMSubtarget.h.

Referenced by hasVMLxForwarding().

◆ HasVMLxHazards

bool llvm::ARMSubtarget::HasVMLxHazards = false

protected

If true, VFP/NEON VMLA/VMLS have special RAW hazards.

Definition at line 377 of file ARMSubtarget.h.

Referenced by hasVMLxHazards().

◆ HasZeroCycleZeroing

bool llvm::ARMSubtarget::HasZeroCycleZeroing = false

protected

If true, the instructions "vmov.i32 d0, #0" and "vmov.i32 q0, #0" are particularly effective at zeroing a VFP register.

Definition at line 326 of file ARMSubtarget.h.

Referenced by hasZeroCycleZeroing().

◆ InstrItins

InstrItineraryData llvm::ARMSubtarget::InstrItins

protected

Selected instruction itineraries (one entry per itinerary class.)

Definition at line 459 of file ARMSubtarget.h.

Referenced by getInstrItineraryData(), and isXRaySupported().

◆ InThumbMode

bool llvm::ARMSubtarget::InThumbMode = false

protected

InThumbMode - True if compiling for Thumb, false for ARM.

Definition at line 193 of file ARMSubtarget.h.

Referenced by isThumb().

◆ IsLittle

bool llvm::ARMSubtarget::IsLittle

protected

IsLittle - The target is Little Endian.

Definition at line 450 of file ARMSubtarget.h.

Referenced by isLittle().

◆ IsProfitableToUnpredicate

bool llvm::ARMSubtarget::IsProfitableToUnpredicate = false

protected

If true, if conversion may decide to leave some instructions unpredicated.

Definition at line 340 of file ARMSubtarget.h.

Referenced by isProfitableToUnpredicate().

◆ LdStMultipleTiming

ARMLdStMultipleTiming llvm::ARMSubtarget::LdStMultipleTiming = SingleIssue

protected

What kind of timing do load multiple/store multiple have (double issue, single issue etc).

Definition at line 440 of file ARMSubtarget.h.

Referenced by getLdStMultipleTiming(), and isXRaySupported().

◆ MaxInterleaveFactor

unsigned llvm::ARMSubtarget::MaxInterleaveFactor = 1

protected

Definition at line 433 of file ARMSubtarget.h.

Referenced by getMaxInterleaveFactor(), and isXRaySupported().

◆ NegativeImmediates

bool llvm::ARMSubtarget::NegativeImmediates = true

protected

Implicitly convert an instruction to a different one if its immediates cannot be encoded.

For example, ADD r0, r1, #FFFFFFFF -> SUB r0, r1, #1.

Definition at line 424 of file ARMSubtarget.h.

◆ NoARM

bool llvm::ARMSubtarget::NoARM = false

protected

NoARM - True if subtarget does not support ARM mode execution.

Definition at line 212 of file ARMSubtarget.h.

Referenced by hasARMOps(), and isXRaySupported().

◆ NoMovt

bool llvm::ARMSubtarget::NoMovt = false

protected

NoMovt - True if MOVT / MOVW pairs are not used for materialization of 32-bit imms (including global addresses).

Definition at line 219 of file ARMSubtarget.h.

Referenced by isXRaySupported(), and useMovt().

◆ NonpipelinedVFP

bool llvm::ARMSubtarget::NonpipelinedVFP = false

protected

If true, VFP instructions are not pipelined.

Definition at line 389 of file ARMSubtarget.h.

Referenced by nonpipelinedVFP().

◆ Options

const TargetOptions& llvm::ARMSubtarget::Options

protected

Options passed via command line that could influence the target.

Definition at line 462 of file ARMSubtarget.h.

Referenced by isXRaySupported().

◆ PartialUpdateClearance

unsigned llvm::ARMSubtarget::PartialUpdateClearance = 0

protected

Clearance before partial register updates (in number of instructions)

Definition at line 436 of file ARMSubtarget.h.

Referenced by getPartialUpdateClearance(), and isXRaySupported().

◆ Pref32BitThumb

bool llvm::ARMSubtarget::Pref32BitThumb = false

protected

Pref32BitThumb - If true, codegen would prefer 32-bit Thumb instructions over 16-bit ones.

Definition at line 262 of file ARMSubtarget.h.

Referenced by prefers32BitThumb().

◆ PreferISHST

bool llvm::ARMSubtarget::PreferISHST = false

protected

If true, ISHST barriers will be used for Release semantics.

Definition at line 352 of file ARMSubtarget.h.

Referenced by preferISHSTBarriers().

◆ PreferVMOVSR

bool llvm::ARMSubtarget::PreferVMOVSR = false

protected

If true, VMOVSR will be favored over VMOVDRR.

Definition at line 349 of file ARMSubtarget.h.

Referenced by preferVMOVSR().

◆ PrefLoopAlignment

unsigned llvm::ARMSubtarget::PrefLoopAlignment = 0

protected

What alignment is preferred for loop bodies, in log2(bytes).

Definition at line 447 of file ARMSubtarget.h.

Referenced by getPrefLoopAlignment(), and isXRaySupported().

◆ PreISelOperandLatencyAdjustment

int llvm::ARMSubtarget::PreISelOperandLatencyAdjustment = 2

protected

The adjustment that we need to apply to get the operand latency from the operand cycle returned by the itinerary data for pre-ISel operands.

Definition at line 444 of file ARMSubtarget.h.

Referenced by getPreISelOperandLatencyAdjustment(), and isXRaySupported().

◆ ReadTPHard

bool llvm::ARMSubtarget::ReadTPHard = false

protected

Definition at line 380 of file ARMSubtarget.h.

Referenced by isReadTPHard().

◆ ReserveR9

bool llvm::ARMSubtarget::ReserveR9 = false

protected

ReserveR9 - True if R9 is not available as a general purpose register.

Definition at line 215 of file ARMSubtarget.h.

Referenced by isXRaySupported().

◆ RestrictIT

bool llvm::ARMSubtarget::RestrictIT = false

protected

RestrictIT - If true, the subtarget disallows generation of deprecated IT blocks to conform to ARMv8 rule.

Definition at line 398 of file ARMSubtarget.h.

Referenced by isXRaySupported(), and restrictIT().

◆ SchedModel

MCSchedModel llvm::ARMSubtarget::SchedModel

protected

SchedModel - Processor specific instruction costs.

Definition at line 456 of file ARMSubtarget.h.

Referenced by getMispredictionPenalty(), and isXRaySupported().

◆ SlowFPBrcc

bool llvm::ARMSubtarget::SlowFPBrcc = false

protected

SlowFPBrcc - True if floating point compare + branch is slow.

Definition at line 190 of file ARMSubtarget.h.

Referenced by isFPBrccSlow().

◆ SlowFPVMLx

bool llvm::ARMSubtarget::SlowFPVMLx = false

protected

SlowFPVMLx - If the VFP2 / NEON instructions are available, indicates whether the FP VML[AS] instructions are slow (if so, don't use them).

Definition at line 183 of file ARMSubtarget.h.

Referenced by useFPVMLx().

◆ SlowLoadDSubregister

bool llvm::ARMSubtarget::SlowLoadDSubregister = false

protected

If true, loading into a D subregister will be penalized.

Definition at line 359 of file ARMSubtarget.h.

Referenced by hasSlowLoadDSubregister().

◆ SlowOddRegister

bool llvm::ARMSubtarget::SlowOddRegister = false

protected

If true, a VLDM/VSTM starting with an odd register number is considered to take more microops than single VLDRS/VSTRS.

Definition at line 356 of file ARMSubtarget.h.

Referenced by hasSlowOddRegister().

◆ SplatVFPToNeon

bool llvm::ARMSubtarget::SplatVFPToNeon = false

protected

If true, splat a register between VFP and NEON instructions.

Definition at line 371 of file ARMSubtarget.h.

Referenced by useSplatVFPToNeon().

◆ stackAlignment

unsigned llvm::ARMSubtarget::stackAlignment = 4

protected

stackAlignment - The minimum alignment known to hold of the stack frame on entry to the function and which must be maintained by every function.

Definition at line 428 of file ARMSubtarget.h.

Referenced by getStackAlignment(), and isXRaySupported().

◆ StrictAlign

bool llvm::ARMSubtarget::StrictAlign = false

protected

StrictAlign - If true, the subtarget disallows unaligned memory accesses for some types.

For details, see ARMTargetLowering::allowsMisalignedMemoryAccesses().

Definition at line 394 of file ARMSubtarget.h.

Referenced by allowsUnalignedMem().

◆ SupportsTailCall

bool llvm::ARMSubtarget::SupportsTailCall = false

protected

SupportsTailCall - True if the OS supports tail call.

The dynamic linker must be able to synthesize call stubs for interworking between ARM and Thumb.

Definition at line 224 of file ARMSubtarget.h.

Referenced by isXRaySupported(), and supportsTailCall().

◆ TargetTriple

Triple llvm::ARMSubtarget::TargetTriple

protected

TargetTriple - What processor and OS we're targeting.

Definition at line 453 of file ARMSubtarget.h.

Referenced by getTargetTriple(), and isXRaySupported().

◆ TM

const ARMBaseTargetMachine& llvm::ARMSubtarget::TM

protected

Definition at line 464 of file ARMSubtarget.h.

Referenced by isAAPCS16_ABI(), isAAPCS_ABI(), isAPCS_ABI(), isGVIndirectSymbol(), isGVInGOT(), isROPI(), isRWPI(), isTargetHardFloat(), isXRaySupported(), and useFastISel().

◆ UnsafeFPMath

bool llvm::ARMSubtarget::UnsafeFPMath = false

protected

Target machine allowed unsafe FP math (such as use of NEON fp)

Definition at line 414 of file ARMSubtarget.h.

◆ UseAA

bool llvm::ARMSubtarget::UseAA = false

protected

UseAA - True if using AA during codegen (DAGCombine, MISched, etc)

Definition at line 206 of file ARMSubtarget.h.

Referenced by useAA().

◆ UseMISched

bool llvm::ARMSubtarget::UseMISched = false

protected

UseMISched - True if MachineScheduler should be used for this subtarget.

Definition at line 199 of file ARMSubtarget.h.

Referenced by useMachineScheduler().

◆ UseMulOps

bool llvm::ARMSubtarget::UseMulOps = false

protected

UseMulOps - True if non-microcoded fused integer multiply-add and multiply-subtract instructions should be used.

Definition at line 179 of file ARMSubtarget.h.

Referenced by useMulOps().

◆ UseNaClTrap

bool llvm::ARMSubtarget::UseNaClTrap = false

protected

NaCl TRAP instruction is generated instead of the regular TRAP.

Definition at line 405 of file ARMSubtarget.h.

Referenced by useNaClTrap().

◆ UseNEONForFPMovs

bool llvm::ARMSubtarget::UseNEONForFPMovs = false

protected

If true, VMOVRS, VMOVSR and VMOVS will be converted from VFP to NEON.

Definition at line 383 of file ARMSubtarget.h.

Referenced by useNEONForFPMovs().

◆ UseNEONForSinglePrecisionFP

bool llvm::ARMSubtarget::UseNEONForSinglePrecisionFP = false

protected

UseNEONForSinglePrecisionFP - if the NEONFP attribute has been specified.

Use the method useNEONForSinglePrecisionFP() to determine if NEON should actually be used.

Definition at line 175 of file ARMSubtarget.h.

Referenced by isXRaySupported(), and useNEONForSinglePrecisionFP().

◆ UseSjLjEH

bool llvm::ARMSubtarget::UseSjLjEH = false

protected

UseSjLjEH - If true, the target uses SjLj exception handling (e.g. iOS).

Definition at line 417 of file ARMSubtarget.h.

Referenced by isXRaySupported(), and useSjLjEH().

◆ UseSoftFloat

bool llvm::ARMSubtarget::UseSoftFloat = false

protected

UseSoftFloat - True if we're using software floating point features.

Definition at line 196 of file ARMSubtarget.h.

Referenced by useSoftFloat().

◆ UseWideStrideVFP

bool llvm::ARMSubtarget::UseWideStrideVFP = false

protected

If true, use a wider stride when allocating VFP registers.

Definition at line 362 of file ARMSubtarget.h.

Referenced by useWideStrideVFP().

The documentation for this class was generated from the following files:

lib/Target/ARM/ARMSubtarget.h
lib/Target/ARM/ARMSubtarget.cpp

Public Types

Public Member Functions

Protected Types

Protected Attributes

Detailed Description

Member Enumeration Documentation

◆ ARMArchEnum

◆ ARMLdStMultipleTiming

◆ ARMProcClassEnum

◆ ARMProcFamilyEnum

Constructor & Destructor Documentation

◆ ARMSubtarget()

Member Function Documentation

◆ allowPositionIndependentMovt()

◆ allowsUnalignedMem()

◆ avoidCPSRPartialUpdate()

◆ avoidMOVsShifterOperand()

◆ cheapPredicableCPSRDef()

◆ checkVLDnAccessAlignment()

◆ computeIssueWidth()

◆ disablePostRAScheduler()

◆ dontWidenVMOVS()

◆ enableAtomicExpand()

◆ enableMachineScheduler()

◆ enablePostRAScheduler()

◆ expandMLx()

◆ genExecuteOnly()

◆ genLongCalls()

◆ getCallLowering()

◆ getCPUString()

◆ getFrameLowering()

◆ getInstrInfo()

◆ getInstrItineraryData()

◆ getInstructionSelector()

◆ getLdStMultipleTiming()

◆ getLegalizerInfo()

◆ getMaxInlineSizeThreshold()

◆ getMaxInterleaveFactor()

◆ getMispredictionPenalty()

◆ getPartialUpdateClearance()

◆ getPrefLoopAlignment()

◆ getPreISelOperandLatencyAdjustment()

◆ getRegBankInfo()

◆ getRegisterInfo()

◆ getReturnOpcode()

◆ getSelectionDAGInfo()

◆ getStackAlignment()

◆ getTargetLowering()

◆ getTargetTriple()

◆ has8MSecExt()

◆ hasAcquireRelease()

◆ hasAES()

◆ hasAnyDataBarrier()

◆ hasARMOps()

◆ hasBranchPredictor()

◆ hasCRC()

◆ hasCrypto()

◆ hasD16()

◆ hasDataBarrier()

◆ hasDivideInARMMode()

◆ hasDivideInThumbMode()

◆ hasDotProd()

◆ hasDSP()

◆ hasFP16()

◆ hasFP16FML()

◆ hasFPAO()

◆ hasFPARMv8()

◆ hasFullDataBarrier()

◆ hasFullFP16()

◆ hasFuseAES()

◆ hasFuseLiterals()

◆ hasFusion()

◆ hasMPExtension()

◆ hasMuxedUnits()

◆ hasNEON()

◆ hasPerfMon()

◆ hasRAS()

◆ hasRetAddrStack()

◆ hasSB()

◆ hasSHA2()