#include "Target/ARM/ARMBaseRegisterInfo.h"

Inheritance diagram for llvm::ARMBaseRegisterInfo:

Collaboration diagram for llvm::ARMBaseRegisterInfo:

Public Member Functions
const MCPhysReg *	getCalleeSavedRegs (const MachineFunction *MF) const override
	Code Generation virtual methods... More...

const MCPhysReg *	getCalleeSavedRegsViaCopy (const MachineFunction *MF) const

const uint32_t *	getCallPreservedMask (const MachineFunction &MF, CallingConv::ID) const override

const uint32_t *	getNoPreservedMask () const override

const uint32_t *	getTLSCallPreservedMask (const MachineFunction &MF) const

const uint32_t *	getSjLjDispatchPreservedMask (const MachineFunction &MF) const

const uint32_t *	getThisReturnPreservedMask (const MachineFunction &MF, CallingConv::ID) const
	getThisReturnPreservedMask - Returns a call preserved mask specific to the case that 'returned' is on an i32 first argument if the calling convention is one that can (partially) model this attribute with a preserved mask (i.e. More...

BitVector	getReservedRegs (const MachineFunction &MF) const override

bool	isAsmClobberable (const MachineFunction &MF, unsigned PhysReg) const override

const TargetRegisterClass *	getPointerRegClass (const MachineFunction &MF, unsigned Kind=0) const override

const TargetRegisterClass *	getCrossCopyRegClass (const TargetRegisterClass *RC) const override

const TargetRegisterClass *	getLargestLegalSuperClass (const TargetRegisterClass *RC, const MachineFunction &MF) const override

unsigned	getRegPressureLimit (const TargetRegisterClass *RC, MachineFunction &MF) const override

bool	getRegAllocationHints (unsigned VirtReg, ArrayRef< MCPhysReg > Order, SmallVectorImpl< MCPhysReg > &Hints, const MachineFunction &MF, const VirtRegMap VRM, const LiveRegMatrix Matrix) const override

void	updateRegAllocHint (unsigned Reg, unsigned NewReg, MachineFunction &MF) const override

bool	hasBasePointer (const MachineFunction &MF) const

bool	canRealignStack (const MachineFunction &MF) const override

int64_t	getFrameIndexInstrOffset (const MachineInstr *MI, int Idx) const override

bool	needsFrameBaseReg (MachineInstr *MI, int64_t Offset) const override
	needsFrameBaseReg - Returns true if the instruction's frame index reference would be better served by a base register other than FP or SP. More...

void	materializeFrameBaseRegister (MachineBasicBlock *MBB, unsigned BaseReg, int FrameIdx, int64_t Offset) const override
	materializeFrameBaseRegister - Insert defining instruction(s) for BaseReg to be a pointer to FrameIdx at the beginning of the basic block. More...

void	resolveFrameIndex (MachineInstr &MI, unsigned BaseReg, int64_t Offset) const override

bool	isFrameOffsetLegal (const MachineInstr *MI, unsigned BaseReg, int64_t Offset) const override

bool	cannotEliminateFrame (const MachineFunction &MF) const

unsigned	getFrameRegister (const MachineFunction &MF) const override

unsigned	getBaseRegister () const

bool	isLowRegister (unsigned Reg) const

virtual void	emitLoadConstPool (MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, unsigned DestReg, unsigned SubIdx, int Val, ARMCC::CondCodes Pred=ARMCC::AL, unsigned PredReg=0, unsigned MIFlags=MachineInstr::NoFlags) const
	emitLoadConstPool - Emits a load from constpool to materialize the specified immediate. More...

bool	requiresRegisterScavenging (const MachineFunction &MF) const override
	Code Generation virtual methods... More...

bool	trackLivenessAfterRegAlloc (const MachineFunction &MF) const override

bool	requiresFrameIndexScavenging (const MachineFunction &MF) const override

bool	requiresVirtualBaseRegisters (const MachineFunction &MF) const override

void	eliminateFrameIndex (MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override

bool	shouldCoalesce (MachineInstr MI, const TargetRegisterClass SrcRC, unsigned SubReg, const TargetRegisterClass DstRC, unsigned DstSubReg, const TargetRegisterClass NewRC, LiveIntervals &LIS) const override
	SrcRC and DstRC will be morphed into NewRC if this returns true. More...

Protected Member Functions
	ARMBaseRegisterInfo ()

unsigned	getOpcode (int Op) const

Protected Attributes
unsigned	BasePtr = ARM::R6
	BasePtr - ARM physical register used as a base ptr in complex stack frames. More...

Detailed Description

Definition at line 98 of file ARMBaseRegisterInfo.h.

Constructor & Destructor Documentation

◆ ARMBaseRegisterInfo()

ARMBaseRegisterInfo::ARMBaseRegisterInfo ( )

explicitprotected

Definition at line 58 of file ARMBaseRegisterInfo.cpp.

Member Function Documentation

◆ cannotEliminateFrame()

bool ARMBaseRegisterInfo::cannotEliminateFrame ( const MachineFunction & MF ) const

Definition at line 420 of file ARMBaseRegisterInfo.cpp.

References llvm::MachineFrameInfo::adjustsStack(), llvm::TargetOptions::DisableFramePointerElim(), llvm::MachineFunction::getFrameInfo(), llvm::MachineFunction::getTarget(), llvm::MachineFrameInfo::hasVarSizedObjects(), llvm::MachineFrameInfo::isFrameAddressTaken(), and llvm::TargetMachine::Options.

Referenced by canRealignStack(), and llvm::ARMFrameLowering::determineCalleeSaves().

◆ canRealignStack()

bool ARMBaseRegisterInfo::canRealignStack ( const MachineFunction & MF ) const

override

Definition at line 398 of file ARMBaseRegisterInfo.cpp.

References BasePtr, cannotEliminateFrame(), llvm::TargetRegisterInfo::canRealignStack(), llvm::MachineRegisterInfo::canReserveReg(), getFramePointerReg(), llvm::MachineFunction::getRegInfo(), llvm::MachineFunction::getSubtarget(), llvm::ARMFrameLowering::hasReservedCallFrame(), and MRI.

Referenced by needsFrameBaseReg().

◆ eliminateFrameIndex()

void ARMBaseRegisterInfo::eliminateFrameIndex	(	MachineBasicBlock::iterator	II,
		int	SPAdj,
		unsigned	FIOperandNum,
		RegScavenger *	RS = `nullptr`
	)		const

override

Definition at line 731 of file ARMBaseRegisterInfo.cpp.

References llvm::ARMII::AddrMode4, llvm::ARMII::AddrMode6, llvm::ARMII::AddrModeMask, llvm::ARMCC::AL, assert(), llvm::MachineOperand::ChangeToRegister(), llvm::MachineRegisterInfo::createVirtualRegister(), llvm::emitARMRegPlusImmediate(), llvm::emitT2RegPlusImmediate(), llvm::MachineInstr::findFirstPredOperandIdx(), llvm::ISD::FrameIndex, llvm::MachineInstr::getDebugLoc(), llvm::MachineInstr::getDesc(), llvm::MachineFunction::getFrameInfo(), llvm::MachineOperand::getImm(), llvm::MachineOperand::getIndex(), llvm::MachineFunction::getInfo(), llvm::TargetSubtargetInfo::getInstrInfo(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), llvm::MachineFunction::getSubtarget(), llvm::ARMFrameLowering::hasReservedCallFrame(), llvm::MachineFrameInfo::hasVarSizedObjects(), llvm::MachineInstr::isDebugValue(), llvm::RegScavenger::isScavengingFrameIndex(), llvm::ARMFunctionInfo::isThumb1OnlyFunction(), llvm::ARMFunctionInfo::isThumb2Function(), llvm::ARMFunctionInfo::isThumbFunction(), MI, llvm::ARMFrameLowering::ResolveFrameIndexReference(), llvm::rewriteARMFrameIndex(), llvm::rewriteT2FrameIndex(), TII, and llvm::MCInstrDesc::TSFlags.

Referenced by llvm::ThumbRegisterInfo::eliminateFrameIndex().

◆ emitLoadConstPool()

void ARMBaseRegisterInfo::emitLoadConstPool	(	MachineBasicBlock &	MBB,
		MachineBasicBlock::iterator &	MBBI,
		const DebugLoc &	dl,
		unsigned	DestReg,
		unsigned	SubIdx,
		int	Val,
		ARMCC::CondCodes	Pred = `ARMCC::AL`,
		unsigned	PredReg = `0`,
		unsigned	MIFlags = `MachineInstr::NoFlags`
	)		const

virtual

emitLoadConstPool - Emits a load from constpool to materialize the specified immediate.

Reimplemented in llvm::ThumbRegisterInfo.

Definition at line 440 of file ARMBaseRegisterInfo.cpp.

References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addImm(), llvm::BuildMI(), C, llvm::MCInstrInfo::get(), llvm::ConstantInt::get(), llvm::MachineFunction::getConstantPool(), llvm::MachineConstantPool::getConstantPoolIndex(), llvm::Function::getContext(), llvm::getDefRegState(), llvm::MachineFunction::getFunction(), llvm::TargetSubtargetInfo::getInstrInfo(), llvm::Type::getInt32Ty(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getSubtarget(), llvm::predOps(), requiresRegisterScavenging(), llvm::MachineInstrBuilder::setMIFlags(), and TII.

Referenced by emitThumbRegPlusImmInReg().

◆ getBaseRegister()

unsigned llvm::ARMBaseRegisterInfo::getBaseRegister ( ) const

inline

Definition at line 178 of file ARMBaseRegisterInfo.h.

References llvm::ARMCC::AL, MI, llvm::MachineInstr::NoFlags, Reg, and SubReg.

Referenced by llvm::ARMFrameLowering::determineCalleeSaves(), llvm::Thumb1FrameLowering::emitPrologue(), llvm::ARMFrameLowering::emitPrologue(), and llvm::ARMFrameLowering::ResolveFrameIndexReference().

◆ getCalleeSavedRegs()

const MCPhysReg * ARMBaseRegisterInfo::getCalleeSavedRegs ( const MachineFunction * MF ) const

override

Code Generation virtual methods...

Definition at line 66 of file ARMBaseRegisterInfo.cpp.

References llvm::CallingConv::CXX_FAST_TLS, F(), llvm::Function::getAttributes(), llvm::Function::getCallingConv(), llvm::Function::getFnAttribute(), llvm::MachineFunction::getFunction(), llvm::MachineFunction::getInfo(), llvm::MachineFunction::getSubtarget(), llvm::ARMSubtarget::getTargetLowering(), llvm::Attribute::getValueAsString(), llvm::CallingConv::GHC, llvm::AttributeList::hasAttrSomewhere(), llvm::Function::hasFnAttribute(), llvm::ARMSubtarget::isMClass(), llvm::ARMFunctionInfo::isSplitCSR(), llvm::ARMSubtarget::isTargetDarwin(), llvm::ARMSubtarget::splitFramePushPop(), llvm::ARMTargetLowering::supportSwiftError(), and llvm::Attribute::SwiftError.

Referenced by llvm::ARMFrameLowering::determineCalleeSaves(), and llvm::ARMTargetLowering::ReplaceNodeResults().

◆ getCalleeSavedRegsViaCopy()

const MCPhysReg * ARMBaseRegisterInfo::getCalleeSavedRegsViaCopy ( const MachineFunction * MF ) const

Definition at line 111 of file ARMBaseRegisterInfo.cpp.

References assert(), llvm::CallingConv::CXX_FAST_TLS, llvm::Function::getCallingConv(), llvm::MachineFunction::getFunction(), and llvm::MachineFunction::getInfo().

Referenced by llvm::ARMTargetLowering::getExceptionSelectorRegister(), and LowerInterruptReturn().

◆ getCallPreservedMask()

const uint32_t * ARMBaseRegisterInfo::getCallPreservedMask	(	const MachineFunction &	MF,
		CallingConv::ID	CC
	)		const

override

Definition at line 121 of file ARMBaseRegisterInfo.cpp.

References llvm::CallingConv::CXX_FAST_TLS, llvm::Function::getAttributes(), llvm::MachineFunction::getFunction(), llvm::MachineFunction::getSubtarget(), llvm::ARMSubtarget::getTargetLowering(), llvm::CallingConv::GHC, llvm::AttributeList::hasAttrSomewhere(), llvm::ARMSubtarget::isTargetDarwin(), llvm::ARMTargetLowering::supportSwiftError(), and llvm::Attribute::SwiftError.

Referenced by llvm::ARMTargetLowering::CCAssignFnForReturn(), and MatchingStackOffset().

◆ getCrossCopyRegClass()

const TargetRegisterClass * ARMBaseRegisterInfo::getCrossCopyRegClass ( const TargetRegisterClass * RC ) const

override

Definition at line 245 of file ARMBaseRegisterInfo.cpp.

◆ getFrameIndexInstrOffset()

int64_t ARMBaseRegisterInfo::getFrameIndexInstrOffset	(	const MachineInstr *	MI,
		int	Idx
	)		const

override

◆ getFrameRegister()

unsigned ARMBaseRegisterInfo::getFrameRegister ( const MachineFunction & MF ) const

override

Definition at line 429 of file ARMBaseRegisterInfo.cpp.

References getFramePointerReg(), and llvm::MachineFunction::getSubtarget().

Referenced by addExclusiveRegPair(), llvm::ARMFrameLowering::determineCalleeSaves(), llvm::Thumb1FrameLowering::emitPrologue(), llvm::ARMFrameLowering::emitPrologue(), getComparePred(), LowerVectorINT_TO_FP(), needsFrameBaseReg(), llvm::ARMFrameLowering::ResolveFrameIndexReference(), llvm::Thumb1FrameLowering::restoreCalleeSavedRegisters(), and llvm::Thumb1FrameLowering::spillCalleeSavedRegisters().

◆ getLargestLegalSuperClass()

const TargetRegisterClass * ARMBaseRegisterInfo::getLargestLegalSuperClass	(	const TargetRegisterClass *	RC,
		const MachineFunction &	MF
	)		const

override

Definition at line 218 of file ARMBaseRegisterInfo.cpp.

References llvm::TargetRegisterClass::getID(), llvm::TargetRegisterClass::getSuperClasses(), and I.

Referenced by llvm::ThumbRegisterInfo::getLargestLegalSuperClass().

◆ getNoPreservedMask()

const uint32_t * ARMBaseRegisterInfo::getNoPreservedMask ( ) const

override

Definition at line 139 of file ARMBaseRegisterInfo.cpp.

◆ getOpcode()

unsigned llvm::ARMBaseRegisterInfo::getOpcode ( int Op ) const

protected

◆ getPointerRegClass()

const TargetRegisterClass * ARMBaseRegisterInfo::getPointerRegClass	(	const MachineFunction &	MF,
		unsigned	Kind = `0`
	)		const

override

Definition at line 239 of file ARMBaseRegisterInfo.cpp.

Referenced by llvm::ThumbRegisterInfo::getPointerRegClass().

◆ getRegAllocationHints()

bool ARMBaseRegisterInfo::getRegAllocationHints	(	unsigned	VirtReg,
		ArrayRef< MCPhysReg >	Order,
		SmallVectorImpl< MCPhysReg > &	Hints,
		const MachineFunction &	MF,
		const VirtRegMap *	VRM,
		const LiveRegMatrix *	Matrix
	)		const

override

Definition at line 289 of file ARMBaseRegisterInfo.cpp.

References getPairedGPR(), llvm::VirtRegMap::getPhys(), llvm::MachineRegisterInfo::getRegAllocationHint(), llvm::TargetRegisterInfo::getRegAllocationHints(), llvm::MachineFunction::getRegInfo(), llvm::VirtRegMap::hasPhys(), llvm::is_contained(), llvm::TargetRegisterInfo::isPhysicalRegister(), llvm::MachineRegisterInfo::isReserved(), MRI, llvm::SmallVectorTemplateBase< T, bool >::push_back(), Reg, llvm::ARMRI::RegPairEven, and llvm::ARMRI::RegPairOdd.

◆ getRegPressureLimit()

unsigned ARMBaseRegisterInfo::getRegPressureLimit	(	const TargetRegisterClass *	RC,
		MachineFunction &	MF
	)		const

override

Definition at line 252 of file ARMBaseRegisterInfo.cpp.

References llvm::MachineFunction::getFrameInfo(), llvm::TargetRegisterClass::getID(), llvm::MachineFunction::getSubtarget(), llvm::MachineFrameInfo::isMaxCallFrameSizeComputed(), and llvm::ARMSubtarget::isR9Reserved().

◆ getReservedRegs()

BitVector ARMBaseRegisterInfo::getReservedRegs ( const MachineFunction & MF ) const

override

Definition at line 179 of file ARMBaseRegisterInfo.cpp.

References assert(), BasePtr, getFramePointerReg(), llvm::MachineFunction::getSubtarget(), hasBasePointer(), llvm::ARMSubtarget::hasD16(), llvm::ARMSubtarget::hasVFP3(), isAsmClobberable(), llvm::ARMSubtarget::isR9Reserved(), Reg, SI, and llvm::BitVector::test().

Referenced by getThisReturnPreservedMask(), and isAsmClobberable().

◆ getSjLjDispatchPreservedMask()

const uint32_t * ARMBaseRegisterInfo::getSjLjDispatchPreservedMask ( const MachineFunction & MF ) const

Definition at line 151 of file ARMBaseRegisterInfo.cpp.

References llvm::MachineFunction::getSubtarget(), llvm::ARMSubtarget::hasVFP2(), llvm::ARMSubtarget::isThumb1Only(), and llvm::ARMSubtarget::useSoftFloat().

Referenced by llvm::ARMTargetLowering::ReplaceNodeResults().

◆ getThisReturnPreservedMask()

const uint32_t * ARMBaseRegisterInfo::getThisReturnPreservedMask	(	const MachineFunction &	MF,
		CallingConv::ID	CC
	)		const

getThisReturnPreservedMask - Returns a call preserved mask specific to the case that 'returned' is on an i32 first argument if the calling convention is one that can (partially) model this attribute with a preserved mask (i.e.

it is a calling convention that uses the same register for the first i32 argument and an i32 return value)

Should return NULL in the case that the calling convention does not have this property

Definition at line 160 of file ARMBaseRegisterInfo.cpp.

References getReservedRegs(), llvm::MachineFunction::getSubtarget(), llvm::CallingConv::GHC, and llvm::ARMSubtarget::isTargetDarwin().

Referenced by llvm::ARMTargetLowering::CCAssignFnForReturn().

◆ getTLSCallPreservedMask()

const uint32_t * ARMBaseRegisterInfo::getTLSCallPreservedMask ( const MachineFunction & MF ) const

Definition at line 144 of file ARMBaseRegisterInfo.cpp.

References assert(), llvm::MachineFunction::getSubtarget(), and llvm::ARMSubtarget::isTargetDarwin().

◆ hasBasePointer()

bool ARMBaseRegisterInfo::hasBasePointer ( const MachineFunction & MF ) const

Definition at line 367 of file ARMBaseRegisterInfo.cpp.

References llvm::MachineFunction::getFrameInfo(), llvm::MachineFunction::getInfo(), llvm::MachineFrameInfo::getLocalFrameSize(), llvm::MachineFrameInfo::hasVarSizedObjects(), llvm::ARMFunctionInfo::isThumb2Function(), and llvm::ARMFunctionInfo::isThumbFunction().

Referenced by addExclusiveRegPair(), llvm::ARMFrameLowering::determineCalleeSaves(), llvm::Thumb1FrameLowering::emitPrologue(), llvm::ARMFrameLowering::emitPrologue(), getReservedRegs(), and llvm::ARMFrameLowering::ResolveFrameIndexReference().

◆ isAsmClobberable()

bool ARMBaseRegisterInfo::isAsmClobberable	(	const MachineFunction &	MF,
		unsigned	PhysReg
	)		const

override

Definition at line 213 of file ARMBaseRegisterInfo.cpp.

References getReservedRegs(), and llvm::BitVector::test().

Referenced by getReservedRegs().

◆ isFrameOffsetLegal()

bool ARMBaseRegisterInfo::isFrameOffsetLegal	(	const MachineInstr *	MI,
		unsigned	BaseReg,
		int64_t	Offset
	)		const

override

◆ isLowRegister()

bool llvm::ARMBaseRegisterInfo::isLowRegister ( unsigned Reg ) const

◆ materializeFrameBaseRegister()

void ARMBaseRegisterInfo::materializeFrameBaseRegister	(	MachineBasicBlock *	MBB,
		unsigned	BaseReg,
		int	FrameIdx,
		int64_t	Offset
	)		const

override

materializeFrameBaseRegister - Insert defining instruction(s) for BaseReg to be a pointer to FrameIdx at the beginning of the basic block.

Definition at line 612 of file ARMBaseRegisterInfo.cpp.

References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addFrameIndex(), llvm::MachineInstrBuilder::addImm(), llvm::ARMCC::AL, llvm::MachineBasicBlock::begin(), llvm::BuildMI(), llvm::condCodeOp(), llvm::MachineRegisterInfo::constrainRegClass(), llvm::MachineBasicBlock::end(), llvm::MCInstrInfo::get(), llvm::MachineFunction::getInfo(), llvm::TargetSubtargetInfo::getInstrInfo(), llvm::MachineBasicBlock::getParent(), llvm::TargetInstrInfo::getRegClass(), llvm::MachineFunction::getRegInfo(), llvm::MachineFunction::getSubtarget(), llvm::MipsISD::Ins, llvm::ARMFunctionInfo::isThumb1OnlyFunction(), llvm::ARMFunctionInfo::isThumbFunction(), MRI, llvm::predOps(), and TII.

Referenced by needsFrameBaseReg().

◆ needsFrameBaseReg()

bool ARMBaseRegisterInfo::needsFrameBaseReg	(	MachineInstr *	MI,
		int64_t	Offset
	)		const

override

needsFrameBaseReg - Returns true if the instruction's frame index reference would be better served by a base register other than FP or SP.

Used by LocalStackFrameAllocation to determine which frame index references it should create new base registers for.

Definition at line 531 of file ARMBaseRegisterInfo.cpp.

References assert(), canRealignStack(), llvm::MachineFunction::getFrameInfo(), getFrameRegister(), llvm::MachineFunction::getInfo(), llvm::MachineFrameInfo::getLocalFrameMaxAlign(), llvm::MachineFrameInfo::getLocalFrameSize(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), llvm::TargetFrameLowering::getStackAlignment(), llvm::ARMFrameLowering::hasFP(), llvm::MachineFrameInfo::hasVarSizedObjects(), llvm::MachineOperand::isFI(), isFrameOffsetLegal(), llvm::ARMFunctionInfo::isThumb1OnlyFunction(), llvm::ARMFunctionInfo::isThumbFunction(), and materializeFrameBaseRegister().

Referenced by getFrameIndexInstrOffset().

◆ requiresFrameIndexScavenging()

bool ARMBaseRegisterInfo::requiresFrameIndexScavenging ( const MachineFunction & MF ) const

override

Definition at line 470 of file ARMBaseRegisterInfo.cpp.

References requiresVirtualBaseRegisters().

Referenced by trackLivenessAfterRegAlloc().

◆ requiresRegisterScavenging()

bool ARMBaseRegisterInfo::requiresRegisterScavenging ( const MachineFunction & MF ) const

override

Code Generation virtual methods...

Definition at line 460 of file ARMBaseRegisterInfo.cpp.

References trackLivenessAfterRegAlloc().

Referenced by emitLoadConstPool().

◆ requiresVirtualBaseRegisters()

bool ARMBaseRegisterInfo::requiresVirtualBaseRegisters ( const MachineFunction & MF ) const

override

Definition at line 475 of file ARMBaseRegisterInfo.cpp.

References getFrameIndexInstrOffset().

Referenced by requiresFrameIndexScavenging().

◆ resolveFrameIndex()

void ARMBaseRegisterInfo::resolveFrameIndex	(	MachineInstr &	MI,
		unsigned	BaseReg,
		int64_t	Offset
	)		const

override

Definition at line 637 of file ARMBaseRegisterInfo.cpp.

References assert(), llvm::MachineFunction::getInfo(), llvm::TargetSubtargetInfo::getInstrInfo(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), llvm::MachineFunction::getSubtarget(), llvm::MachineOperand::isFI(), llvm::ARMFunctionInfo::isThumb1OnlyFunction(), llvm::ARMFunctionInfo::isThumb2Function(), llvm::ARMFunctionInfo::isThumbFunction(), llvm::rewriteARMFrameIndex(), llvm::rewriteT2FrameIndex(), and TII.

Referenced by llvm::ThumbRegisterInfo::resolveFrameIndex().

◆ shouldCoalesce()

bool ARMBaseRegisterInfo::shouldCoalesce	(	MachineInstr *	MI,
		const TargetRegisterClass *	SrcRC,
		unsigned	SubReg,
		const TargetRegisterClass *	DstRC,
		unsigned	DstSubReg,
		const TargetRegisterClass *	NewRC,
		LiveIntervals &	LIS
	)		const

override

SrcRC and DstRC will be morphed into NewRC if this returns true.

Definition at line 807 of file ARMBaseRegisterInfo.cpp.

References llvm::dbgs(), llvm::ARMFunctionInfo::getCoalescedWeight(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), llvm::TargetRegisterInfo::getRegClassWeight(), llvm::MachineRegisterInfo::getTargetRegisterInfo(), LLVM_DEBUG, and MRI.

◆ trackLivenessAfterRegAlloc()

bool ARMBaseRegisterInfo::trackLivenessAfterRegAlloc ( const MachineFunction & MF ) const

override

Definition at line 465 of file ARMBaseRegisterInfo.cpp.

References requiresFrameIndexScavenging().

Referenced by requiresRegisterScavenging().

◆ updateRegAllocHint()

void ARMBaseRegisterInfo::updateRegAllocHint	(	unsigned	Reg,
		unsigned	NewReg,
		MachineFunction &	MF
	)		const

override

Definition at line 343 of file ARMBaseRegisterInfo.cpp.

References llvm::MachineRegisterInfo::getRegAllocationHint(), llvm::MachineFunction::getRegInfo(), llvm::TargetRegisterInfo::isVirtualRegister(), MRI, llvm::ARMRI::RegPairEven, llvm::ARMRI::RegPairOdd, and llvm::MachineRegisterInfo::setRegAllocationHint().

Member Data Documentation

◆ BasePtr

unsigned llvm::ARMBaseRegisterInfo::BasePtr = ARM::R6

protected

BasePtr - ARM physical register used as a base ptr in complex stack frames.

I.e., when we need a 3rd base, not just SP and FP, due to variable size stack objects.

Definition at line 103 of file ARMBaseRegisterInfo.h.

Referenced by canRealignStack(), and getReservedRegs().

The documentation for this class was generated from the following files:

lib/Target/ARM/ARMBaseRegisterInfo.h
lib/Target/ARM/ARMBaseRegisterInfo.cpp

Public Member Functions

Protected Member Functions

Protected Attributes

Detailed Description

Constructor & Destructor Documentation

◆ ARMBaseRegisterInfo()

Member Function Documentation

◆ cannotEliminateFrame()

◆ canRealignStack()

◆ eliminateFrameIndex()

◆ emitLoadConstPool()

◆ getBaseRegister()

◆ getCalleeSavedRegs()

◆ getCalleeSavedRegsViaCopy()

◆ getCallPreservedMask()

◆ getCrossCopyRegClass()

◆ getFrameIndexInstrOffset()

◆ getFrameRegister()

◆ getLargestLegalSuperClass()

◆ getNoPreservedMask()

◆ getOpcode()

◆ getPointerRegClass()

◆ getRegAllocationHints()

◆ getRegPressureLimit()

◆ getReservedRegs()

◆ getSjLjDispatchPreservedMask()

◆ getThisReturnPreservedMask()

◆ getTLSCallPreservedMask()

◆ hasBasePointer()

◆ isAsmClobberable()

◆ isFrameOffsetLegal()

◆ isLowRegister()

◆ materializeFrameBaseRegister()

◆ needsFrameBaseReg()

◆ requiresFrameIndexScavenging()

◆ requiresRegisterScavenging()

◆ requiresVirtualBaseRegisters()

◆ resolveFrameIndex()

◆ shouldCoalesce()

◆ trackLivenessAfterRegAlloc()

◆ updateRegAllocHint()

Member Data Documentation

◆ BasePtr