#include "Target/AMDGPU/AMDGPUISelLowering.h"

Inheritance diagram for llvm::AMDGPUTargetLowering:

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Collaboration diagram for llvm::AMDGPUTargetLowering:

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Public Types
enum	ImplicitParameter { FIRST_IMPLICIT, GRID_DIM = FIRST_IMPLICIT, GRID_OFFSET }

Public Types inherited from llvm::TargetLowering
enum	ConstraintType { C_Register, C_RegisterClass, C_Memory, C_Other, C_Unknown }

enum	ConstraintWeight { CW_Invalid = -1, CW_Okay = 0, CW_Good = 1, CW_Better = 2, CW_Best = 3, CW_SpecificReg = CW_Okay, CW_Register = CW_Good, CW_Memory = CW_Better, CW_Constant = CW_Best, CW_Default = CW_Okay }

using	AsmOperandInfoVector = std::vector< AsmOperandInfo >

Public Types inherited from llvm::TargetLoweringBase
enum	LegalizeAction : uint8_t { Legal, Promote, Expand, LibCall, Custom }
	This enum indicates whether operations are valid for a target, and if not, what action should be used to make them valid. More...

enum	LegalizeTypeAction : uint8_t { TypeLegal, TypePromoteInteger, TypeExpandInteger, TypeSoftenFloat, TypeExpandFloat, TypeScalarizeVector, TypeSplitVector, TypeWidenVector, TypePromoteFloat }
	This enum indicates whether a types are legal for a target, and if not, what action should be used to make them valid. More...

enum	BooleanContent { UndefinedBooleanContent, ZeroOrOneBooleanContent, ZeroOrNegativeOneBooleanContent }
	Enum that describes how the target represents true/false values. More...

enum	SelectSupportKind { ScalarValSelect, ScalarCondVectorVal, VectorMaskSelect }
	Enum that describes what type of support for selects the target has. More...

enum	AtomicExpansionKind { AtomicExpansionKind::None, AtomicExpansionKind::LLSC, AtomicExpansionKind::LLOnly, AtomicExpansionKind::CmpXChg, AtomicExpansionKind::MaskedIntrinsic }
	Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all. More...

enum	MulExpansionKind { MulExpansionKind::Always, MulExpansionKind::OnlyLegalOrCustom }
	Enum that specifies when a multiplication should be expanded. More...

enum	ReciprocalEstimate : int { Unspecified = -1, Disabled = 0, Enabled = 1 }
	Reciprocal estimate status values used by the functions below. More...

using	LegalizeKind = std::pair< LegalizeTypeAction, EVT >
	LegalizeKind holds the legalization kind that needs to happen to EVT in order to type-legalize it. More...

using	ArgListTy = std::vector< ArgListEntry >

Public Member Functions
	AMDGPUTargetLowering (const TargetMachine &TM, const AMDGPUSubtarget &STI)

bool	mayIgnoreSignedZero (SDValue Op) const

bool	isFAbsFree (EVT VT) const override
	Return true if an fabs operation is free to the point where it is never worthwhile to replace it with a bitwise operation. More...

bool	isFNegFree (EVT VT) const override
	Return true if an fneg operation is free to the point where it is never worthwhile to replace it with a bitwise operation. More...

bool	isTruncateFree (EVT Src, EVT Dest) const override

bool	isTruncateFree (Type Src, Type Dest) const override
	Return true if it's free to truncate a value of type FromTy to type ToTy. More...

bool	isZExtFree (Type Src, Type Dest) const override
	Return true if any actual instruction that defines a value of type FromTy implicitly zero-extends the value to ToTy in the result register. More...

bool	isZExtFree (EVT Src, EVT Dest) const override

bool	isZExtFree (SDValue Val, EVT VT2) const override
	Return true if zero-extending the specific node Val to type VT2 is free (either because it's implicitly zero-extended such as ARM ldrb / ldrh or because it's folded such as X86 zero-extending loads). More...

bool	isNarrowingProfitable (EVT VT1, EVT VT2) const override
	Return true if it's profitable to narrow operations of type VT1 to VT2. More...

MVT	getVectorIdxTy (const DataLayout &) const override
	Returns the type to be used for the index operand of: ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT, ISD::INSERT_SUBVECTOR, and ISD::EXTRACT_SUBVECTOR. More...

bool	isSelectSupported (SelectSupportKind) const override

bool	isFPImmLegal (const APFloat &Imm, EVT VT) const override
	Returns true if the target can instruction select the specified FP immediate natively. More...

bool	ShouldShrinkFPConstant (EVT VT) const override
	If true, then instruction selection should seek to shrink the FP constant of the specified type to a smaller type in order to save space and / or reduce runtime. More...

bool	shouldReduceLoadWidth (SDNode *Load, ISD::LoadExtType ExtType, EVT ExtVT) const override
	Return true if it is profitable to reduce a load to a smaller type. More...

bool	isLoadBitCastBeneficial (EVT, EVT) const final
	Return true if the following transform is beneficial: fold (conv (load x)) -> (load (conv*)x) On architectures that don't natively support some vector loads efficiently, casting the load to a smaller vector of larger types and loading is more efficient, however, this can be undone by optimizations in dag combiner. More...

bool	storeOfVectorConstantIsCheap (EVT MemVT, unsigned NumElem, unsigned AS) const override
	Return true if it is expected to be cheaper to do a store of a non-zero vector constant with the given size and type for the address space than to store the individual scalar element constants. More...

bool	aggressivelyPreferBuildVectorSources (EVT VecVT) const override

bool	isCheapToSpeculateCttz () const override
	Return true if it is cheap to speculate a call to intrinsic cttz. More...

bool	isCheapToSpeculateCtlz () const override
	Return true if it is cheap to speculate a call to intrinsic ctlz. More...

bool	isSDNodeAlwaysUniform (const SDNode *N) const override

SDValue	LowerReturn (SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SDLoc &DL, SelectionDAG &DAG) const override
	This hook must be implemented to lower outgoing return values, described by the Outs array, into the specified DAG. More...

SDValue	addTokenForArgument (SDValue Chain, SelectionDAG &DAG, MachineFrameInfo &MFI, int ClobberedFI) const

SDValue	lowerUnhandledCall (CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals, StringRef Reason) const

SDValue	LowerCall (CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals) const override
	This hook must be implemented to lower calls into the specified DAG. More...

SDValue	LowerDYNAMIC_STACKALLOC (SDValue Op, SelectionDAG &DAG) const

SDValue	LowerOperation (SDValue Op, SelectionDAG &DAG) const override
	This callback is invoked for operations that are unsupported by the target, which are registered to use 'custom' lowering, and whose defined values are all legal. More...

SDValue	PerformDAGCombine (SDNode *N, DAGCombinerInfo &DCI) const override
	This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for. More...

void	ReplaceNodeResults (SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
	This callback is invoked when a node result type is illegal for the target, and the operation was registered to use 'custom' lowering for that result type. More...

SDValue	combineFMinMaxLegacy (const SDLoc &DL, EVT VT, SDValue LHS, SDValue RHS, SDValue True, SDValue False, SDValue CC, DAGCombinerInfo &DCI) const
	Generate Min/Max node. More...

const char *	getTargetNodeName (unsigned Opcode) const override
	This method returns the name of a target specific DAG node. More...

bool	mergeStoresAfterLegalization () const override
	Allow store merging after legalization in addition to before legalization. More...

bool	isFsqrtCheap (SDValue Operand, SelectionDAG &DAG) const override
	Return true if SQRT(X) shouldn't be replaced with X*RSQRT(X). More...

SDValue	getSqrtEstimate (SDValue Operand, SelectionDAG &DAG, int Enabled, int &RefinementSteps, bool &UseOneConstNR, bool Reciprocal) const override
	Hooks for building estimates in place of slower divisions and square roots. More...

SDValue	getRecipEstimate (SDValue Operand, SelectionDAG &DAG, int Enabled, int &RefinementSteps) const override
	Return a reciprocal estimate value for the input operand. More...

virtual SDNode *	PostISelFolding (MachineSDNode *N, SelectionDAG &DAG) const =0

void	computeKnownBitsForTargetNode (const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth=0) const override
	Determine which of the bits specified in `Mask` are known to be either zero or one and return them in the `KnownZero` and `KnownOne` bitsets. More...

unsigned	ComputeNumSignBitsForTargetNode (SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth=0) const override
	This method can be implemented by targets that want to expose additional information about sign bits to the DAG Combiner. More...

bool	isKnownNeverNaNForTargetNode (SDValue Op, const SelectionDAG &DAG, bool SNaN=false, unsigned Depth=0) const override
	If `SNaN` is false,. More...

SDValue	CreateLiveInRegister (SelectionDAG &DAG, const TargetRegisterClass *RC, unsigned Reg, EVT VT, const SDLoc &SL, bool RawReg=false) const
	Helper function that adds Reg to the LiveIn list of the DAG's MachineFunction. More...

SDValue	CreateLiveInRegister (SelectionDAG &DAG, const TargetRegisterClass *RC, unsigned Reg, EVT VT) const

SDValue	CreateLiveInRegisterRaw (SelectionDAG &DAG, const TargetRegisterClass *RC, unsigned Reg, EVT VT) const

SDValue	loadStackInputValue (SelectionDAG &DAG, EVT VT, const SDLoc &SL, int64_t Offset) const
	Similar to CreateLiveInRegister, except value maybe loaded from a stack slot rather than passed in a register. More...

SDValue	storeStackInputValue (SelectionDAG &DAG, const SDLoc &SL, SDValue Chain, SDValue ArgVal, int64_t Offset) const

SDValue	loadInputValue (SelectionDAG &DAG, const TargetRegisterClass *RC, EVT VT, const SDLoc &SL, const ArgDescriptor &Arg) const

uint32_t	getImplicitParameterOffset (const MachineFunction &MF, const ImplicitParameter Param) const
	Helper function that returns the byte offset of the given type of implicit parameter. More...

MVT	getFenceOperandTy (const DataLayout &DL) const override
	Return the type for operands of fence. More...

AtomicExpansionKind	shouldExpandAtomicRMWInIR (AtomicRMWInst *) const override
	Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all. More...

Public Member Functions inherited from llvm::TargetLowering
	TargetLowering (const TargetLowering &)=delete

TargetLowering &	operator= (const TargetLowering &)=delete

	TargetLowering (const TargetMachine &TM)
	NOTE: The TargetMachine owns TLOF. More...

bool	isPositionIndependent () const

virtual bool	isSDNodeSourceOfDivergence (const SDNode N, FunctionLoweringInfo FLI, LegacyDivergenceAnalysis *DA) const

virtual bool	getPreIndexedAddressParts (SDNode *, SDValue &, SDValue &, ISD::MemIndexedMode &, SelectionDAG &) const
	Returns true by value, base pointer and offset pointer and addressing mode by reference if the node's address can be legally represented as pre-indexed load / store address. More...

virtual bool	getPostIndexedAddressParts (SDNode , SDNode , SDValue &, SDValue &, ISD::MemIndexedMode &, SelectionDAG &) const
	Returns true by value, base pointer and offset pointer and addressing mode by reference if this node can be combined with a load / store to form a post-indexed load / store. More...

virtual unsigned	getJumpTableEncoding () const
	Return the entry encoding for a jump table in the current function. More...

virtual const MCExpr *	LowerCustomJumpTableEntry (const MachineJumpTableInfo , const MachineBasicBlock , unsigned, MCContext &) const

virtual SDValue	getPICJumpTableRelocBase (SDValue Table, SelectionDAG &DAG) const
	Returns relocation base for the given PIC jumptable. More...

virtual const MCExpr *	getPICJumpTableRelocBaseExpr (const MachineFunction *MF, unsigned JTI, MCContext &Ctx) const
	This returns the relocation base for the given PIC jumptable, the same as getPICJumpTableRelocBase, but as an MCExpr. More...

virtual bool	isOffsetFoldingLegal (const GlobalAddressSDNode *GA) const
	Return true if folding a constant offset with the given GlobalAddress is legal. More...

bool	isInTailCallPosition (SelectionDAG &DAG, SDNode *Node, SDValue &Chain) const
	Check whether a given call node is in tail position within its function. More...

void	softenSetCCOperands (SelectionDAG &DAG, EVT VT, SDValue &NewLHS, SDValue &NewRHS, ISD::CondCode &CCCode, const SDLoc &DL) const
	Soften the operands of a comparison. More...

std::pair< SDValue, SDValue >	makeLibCall (SelectionDAG &DAG, RTLIB::Libcall LC, EVT RetVT, ArrayRef< SDValue > Ops, bool isSigned, const SDLoc &dl, bool doesNotReturn=false, bool isReturnValueUsed=true) const
	Returns a pair of (return value, chain). More...

bool	parametersInCSRMatch (const MachineRegisterInfo &MRI, const uint32_t *CallerPreservedMask, const SmallVectorImpl< CCValAssign > &ArgLocs, const SmallVectorImpl< SDValue > &OutVals) const
	Check whether parameters to a call that are passed in callee saved registers are the same as from the calling function. More...

bool	ShrinkDemandedConstant (SDValue Op, const APInt &Demanded, TargetLoweringOpt &TLO) const
	Check to see if the specified operand of the specified instruction is a constant integer. More...

virtual bool	targetShrinkDemandedConstant (SDValue Op, const APInt &Demanded, TargetLoweringOpt &TLO) const

bool	ShrinkDemandedOp (SDValue Op, unsigned BitWidth, const APInt &Demanded, TargetLoweringOpt &TLO) const
	Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the casts are free. More...

bool	SimplifyDemandedBits (SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, KnownBits &Known, TargetLoweringOpt &TLO, unsigned Depth=0, bool AssumeSingleUse=false) const
	Look at Op. More...

bool	SimplifyDemandedBits (SDValue Op, const APInt &DemandedBits, KnownBits &Known, TargetLoweringOpt &TLO, unsigned Depth=0, bool AssumeSingleUse=false) const
	Helper wrapper around SimplifyDemandedBits, demanding all elements. More...

bool	SimplifyDemandedBits (SDValue Op, const APInt &DemandedMask, DAGCombinerInfo &DCI) const
	Helper wrapper around SimplifyDemandedBits. More...

bool	SimplifyDemandedVectorElts (SDValue Op, const APInt &DemandedEltMask, APInt &KnownUndef, APInt &KnownZero, TargetLoweringOpt &TLO, unsigned Depth=0, bool AssumeSingleUse=false) const
	Look at Vector Op. More...

bool	SimplifyDemandedVectorElts (SDValue Op, const APInt &DemandedElts, APInt &KnownUndef, APInt &KnownZero, DAGCombinerInfo &DCI) const
	Helper wrapper around SimplifyDemandedVectorElts. More...

virtual void	computeKnownBitsForFrameIndex (const SDValue FIOp, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth=0) const
	Determine which of the bits of FrameIndex `FIOp` are known to be 0. More...

virtual bool	SimplifyDemandedVectorEltsForTargetNode (SDValue Op, const APInt &DemandedElts, APInt &KnownUndef, APInt &KnownZero, TargetLoweringOpt &TLO, unsigned Depth=0) const
	Attempt to simplify any target nodes based on the demanded vector elements, returning true on success. More...

virtual bool	SimplifyDemandedBitsForTargetNode (SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, KnownBits &Known, TargetLoweringOpt &TLO, unsigned Depth=0) const
	Attempt to simplify any target nodes based on the demanded bits/elts, returning true on success. More...

bool	isConstTrueVal (const SDNode *N) const
	Return if the N is a constant or constant vector equal to the true value from getBooleanContents(). More...

bool	isConstFalseVal (const SDNode *N) const
	Return if the N is a constant or constant vector equal to the false value from getBooleanContents(). More...

bool	isExtendedTrueVal (const ConstantSDNode *N, EVT VT, bool SExt) const
	Return if `N` is a True value when extended to `VT`. More...

SDValue	SimplifySetCC (EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, bool foldBooleans, DAGCombinerInfo &DCI, const SDLoc &dl) const
	Try to simplify a setcc built with the specified operands and cc. More...

virtual SDValue	unwrapAddress (SDValue N) const

virtual bool	isGAPlusOffset (SDNode N, const GlobalValue &GA, int64_t &Offset) const
	Returns true (and the GlobalValue and the offset) if the node is a GlobalAddress + offset. More...

virtual bool	isDesirableToCommuteWithShift (const SDNode *N, CombineLevel Level) const
	Return true if it is profitable to move this shift by a constant amount though its operand, adjusting any immediate operands as necessary to preserve semantics. More...

virtual bool	shouldFoldShiftPairToMask (const SDNode *N, CombineLevel Level) const
	Return true if it is profitable to fold a pair of shifts into a mask. More...

virtual bool	isDesirableToCombineBuildVectorToShuffleTruncate (ArrayRef< int > ShuffleMask, EVT SrcVT, EVT TruncVT) const

virtual bool	isTypeDesirableForOp (unsigned, EVT VT) const
	Return true if the target has native support for the specified value type and it is 'desirable' to use the type for the given node type. More...

virtual bool	isDesirableToTransformToIntegerOp (unsigned, EVT) const
	Return true if it is profitable for dag combiner to transform a floating point op of specified opcode to a equivalent op of an integer type. More...

virtual bool	IsDesirableToPromoteOp (SDValue, EVT &) const
	This method query the target whether it is beneficial for dag combiner to promote the specified node. More...

virtual bool	supportSwiftError () const
	Return true if the target supports swifterror attribute. More...

virtual bool	supportSplitCSR (MachineFunction *MF) const
	Return true if the target supports that a subset of CSRs for the given machine function is handled explicitly via copies. More...

virtual void	initializeSplitCSR (MachineBasicBlock *Entry) const
	Perform necessary initialization to handle a subset of CSRs explicitly via copies. More...

virtual void	insertCopiesSplitCSR (MachineBasicBlock Entry, const SmallVectorImpl< MachineBasicBlock > &Exits) const
	Insert explicit copies in entry and exit blocks. More...

virtual SDValue	LowerFormalArguments (SDValue, CallingConv::ID, bool, const SmallVectorImpl< ISD::InputArg > &, const SDLoc &, SelectionDAG &, SmallVectorImpl< SDValue > &) const
	This hook must be implemented to lower the incoming (formal) arguments, described by the Ins array, into the specified DAG. More...

std::pair< SDValue, SDValue >	LowerCallTo (CallLoweringInfo &CLI) const
	This function lowers an abstract call to a function into an actual call. More...

virtual void	HandleByVal (CCState *, unsigned &, unsigned) const
	Target-specific cleanup for formal ByVal parameters. More...

virtual bool	CanLowerReturn (CallingConv::ID, MachineFunction &, bool, const SmallVectorImpl< ISD::OutputArg > &, LLVMContext &) const
	This hook should be implemented to check whether the return values described by the Outs array can fit into the return registers. More...

virtual bool	isUsedByReturnOnly (SDNode *, SDValue &) const
	Return true if result of the specified node is used by a return node only. More...

virtual bool	mayBeEmittedAsTailCall (const CallInst *) const
	Return true if the target may be able emit the call instruction as a tail call. More...

virtual const char *	getClearCacheBuiltinName () const
	Return the builtin name for the __builtin___clear_cache intrinsic Default is to invoke the clear cache library call. More...

virtual unsigned	getRegisterByName (const char *RegName, EVT VT, SelectionDAG &DAG) const
	Return the register ID of the name passed in. More...

virtual EVT	getTypeForExtReturn (LLVMContext &Context, EVT VT, ISD::NodeType) const
	Return the type that should be used to zero or sign extend a zeroext/signext integer return value. More...

virtual bool	functionArgumentNeedsConsecutiveRegisters (Type *Ty, CallingConv::ID CallConv, bool isVarArg) const
	For some targets, an LLVM struct type must be broken down into multiple simple types, but the calling convention specifies that the entire struct must be passed in a block of consecutive registers. More...

virtual const MCPhysReg *	getScratchRegisters (CallingConv::ID CC) const
	Returns a 0 terminated array of registers that can be safely used as scratch registers. More...

virtual SDValue	prepareVolatileOrAtomicLoad (SDValue Chain, const SDLoc &DL, SelectionDAG &DAG) const
	This callback is used to prepare for a volatile or atomic load. More...

virtual MachineMemOperand::Flags	getMMOFlags (const Instruction &I) const
	This callback is used to inspect load/store instructions and add target-specific MachineMemOperand flags to them. More...

virtual void	LowerOperationWrapper (SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const
	This callback is invoked by the type legalizer to legalize nodes with an illegal operand type but legal result types. More...

virtual FastISel *	createFastISel (FunctionLoweringInfo &, const TargetLibraryInfo *) const
	This method returns a target specific FastISel object, or null if the target does not support "fast" ISel. More...

bool	verifyReturnAddressArgumentIsConstant (SDValue Op, SelectionDAG &DAG) const

virtual bool	ExpandInlineAsm (CallInst *) const
	This hook allows the target to expand an inline asm call to be explicit llvm code if it wants to. More...

virtual AsmOperandInfoVector	ParseConstraints (const DataLayout &DL, const TargetRegisterInfo *TRI, ImmutableCallSite CS) const
	Split up the constraint string from the inline assembly value into the specific constraints and their prefixes, and also tie in the associated operand values. More...

virtual ConstraintWeight	getMultipleConstraintMatchWeight (AsmOperandInfo &info, int maIndex) const
	Examine constraint type and operand type and determine a weight value. More...

virtual ConstraintWeight	getSingleConstraintMatchWeight (AsmOperandInfo &info, const char *constraint) const
	Examine constraint string and operand type and determine a weight value. More...

virtual void	ComputeConstraintToUse (AsmOperandInfo &OpInfo, SDValue Op, SelectionDAG *DAG=nullptr) const
	Determines the constraint code and constraint type to use for the specific AsmOperandInfo, setting OpInfo.ConstraintCode and OpInfo.ConstraintType. More...

virtual ConstraintType	getConstraintType (StringRef Constraint) const
	Given a constraint, return the type of constraint it is for this target. More...

virtual std::pair< unsigned, const TargetRegisterClass * >	getRegForInlineAsmConstraint (const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const
	Given a physical register constraint (e.g. More...

virtual unsigned	getInlineAsmMemConstraint (StringRef ConstraintCode) const

virtual const char *	LowerXConstraint (EVT ConstraintVT) const
	Try to replace an X constraint, which matches anything, with another that has more specific requirements based on the type of the corresponding operand. More...

virtual void	LowerAsmOperandForConstraint (SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const
	Lower the specified operand into the Ops vector. More...

SDValue	BuildSDIV (SDNode N, SelectionDAG &DAG, bool IsAfterLegalization, SmallVectorImpl< SDNode > &Created) const
	Given an ISD::SDIV node expressing a divide by constant, return a DAG expression to select that will generate the same value by multiplying by a magic number. More...

SDValue	BuildUDIV (SDNode N, SelectionDAG &DAG, bool IsAfterLegalization, SmallVectorImpl< SDNode > &Created) const
	Given an ISD::UDIV node expressing a divide by constant, return a DAG expression to select that will generate the same value by multiplying by a magic number. More...

virtual SDValue	BuildSDIVPow2 (SDNode N, const APInt &Divisor, SelectionDAG &DAG, SmallVectorImpl< SDNode > &Created) const
	Targets may override this function to provide custom SDIV lowering for power-of-2 denominators. More...

virtual unsigned	combineRepeatedFPDivisors () const
	Indicate whether this target prefers to combine FDIVs with the same divisor. More...

bool	expandMUL_LOHI (unsigned Opcode, EVT VT, SDLoc dl, SDValue LHS, SDValue RHS, SmallVectorImpl< SDValue > &Result, EVT HiLoVT, SelectionDAG &DAG, MulExpansionKind Kind, SDValue LL=SDValue(), SDValue LH=SDValue(), SDValue RL=SDValue(), SDValue RH=SDValue()) const
	Expand a MUL or [US]MUL_LOHI of n-bit values into two or four nodes, respectively, each computing an n/2-bit part of the result. More...

bool	expandMUL (SDNode *N, SDValue &Lo, SDValue &Hi, EVT HiLoVT, SelectionDAG &DAG, MulExpansionKind Kind, SDValue LL=SDValue(), SDValue LH=SDValue(), SDValue RL=SDValue(), SDValue RH=SDValue()) const
	Expand a MUL into two nodes. More...

bool	expandFunnelShift (SDNode *N, SDValue &Result, SelectionDAG &DAG) const
	Expand funnel shift. More...

bool	expandROT (SDNode *N, SDValue &Result, SelectionDAG &DAG) const
	Expand rotations. More...

bool	expandFP_TO_SINT (SDNode *N, SDValue &Result, SelectionDAG &DAG) const
	Expand float(f32) to SINT(i64) conversion. More...

bool	expandFP_TO_UINT (SDNode *N, SDValue &Result, SelectionDAG &DAG) const
	Expand float to UINT conversion. More...

bool	expandUINT_TO_FP (SDNode *N, SDValue &Result, SelectionDAG &DAG) const
	Expand UINT(i64) to double(f64) conversion. More...

SDValue	expandFMINNUM_FMAXNUM (SDNode *N, SelectionDAG &DAG) const
	Expand fminnum/fmaxnum into fminnum_ieee/fmaxnum_ieee with quieted inputs. More...

bool	expandCTPOP (SDNode *N, SDValue &Result, SelectionDAG &DAG) const
	Expand CTPOP nodes. More...

bool	expandCTLZ (SDNode *N, SDValue &Result, SelectionDAG &DAG) const
	Expand CTLZ/CTLZ_ZERO_UNDEF nodes. More...

bool	expandCTTZ (SDNode *N, SDValue &Result, SelectionDAG &DAG) const
	Expand CTTZ/CTTZ_ZERO_UNDEF nodes. More...

bool	expandABS (SDNode *N, SDValue &Result, SelectionDAG &DAG) const
	Expand ABS nodes. More...

SDValue	scalarizeVectorLoad (LoadSDNode *LD, SelectionDAG &DAG) const
	Turn load of vector type into a load of the individual elements. More...

SDValue	scalarizeVectorStore (StoreSDNode *ST, SelectionDAG &DAG) const

std::pair< SDValue, SDValue >	expandUnalignedLoad (LoadSDNode *LD, SelectionDAG &DAG) const
	Expands an unaligned load to 2 half-size loads for an integer, and possibly more for vectors. More...

SDValue	expandUnalignedStore (StoreSDNode *ST, SelectionDAG &DAG) const
	Expands an unaligned store to 2 half-size stores for integer values, and possibly more for vectors. More...

SDValue	IncrementMemoryAddress (SDValue Addr, SDValue Mask, const SDLoc &DL, EVT DataVT, SelectionDAG &DAG, bool IsCompressedMemory) const
	Increments memory address `Addr` according to the type of the value `DataVT` that should be stored. More...

SDValue	getVectorElementPointer (SelectionDAG &DAG, SDValue VecPtr, EVT VecVT, SDValue Index) const
	Get a pointer to vector element `Idx` located in memory for a vector of type `VecVT` starting at a base address of `VecPtr`. More...

SDValue	expandAddSubSat (SDNode *Node, SelectionDAG &DAG) const
	Method for building the DAG expansion of ISD::[US][ADD\|SUB]SAT. More...

SDValue	getExpandedFixedPointMultiplication (SDNode *Node, SelectionDAG &DAG) const
	Method for building the DAG expansion of ISD::SMULFIX. More...

virtual MachineBasicBlock *	EmitInstrWithCustomInserter (MachineInstr &MI, MachineBasicBlock *MBB) const
	This method should be implemented by targets that mark instructions with the 'usesCustomInserter' flag. More...

virtual void	AdjustInstrPostInstrSelection (MachineInstr &MI, SDNode *Node) const
	This method should be implemented by targets that mark instructions with the 'hasPostISelHook' flag. More...

virtual bool	useLoadStackGuardNode () const
	If this function returns true, SelectionDAGBuilder emits a LOAD_STACK_GUARD node when it is lowering Intrinsic::stackprotector. More...

virtual SDValue	emitStackGuardXorFP (SelectionDAG &DAG, SDValue Val, const SDLoc &DL) const

virtual SDValue	LowerToTLSEmulatedModel (const GlobalAddressSDNode *GA, SelectionDAG &DAG) const
	Lower TLS global address SDNode for target independent emulated TLS model. More...

virtual SDValue	expandIndirectJTBranch (const SDLoc &dl, SDValue Value, SDValue Addr, SelectionDAG &DAG) const
	Expands target specific indirect branch for the case of JumpTable expanasion. More...

SDValue	lowerCmpEqZeroToCtlzSrl (SDValue Op, SelectionDAG &DAG) const

Public Member Functions inherited from llvm::TargetLoweringBase
virtual void	markLibCallAttributes (MachineFunction *MF, unsigned CC, ArgListTy &Args) const

	TargetLoweringBase (const TargetMachine &TM)
	NOTE: The TargetMachine owns TLOF. More...

	TargetLoweringBase (const TargetLoweringBase &)=delete

TargetLoweringBase &	operator= (const TargetLoweringBase &)=delete

virtual	~TargetLoweringBase ()=default

const TargetMachine &	getTargetMachine () const

virtual bool	useSoftFloat () const

MVT	getPointerTy (const DataLayout &DL, uint32_t AS=0) const
	Return the pointer type for the given address space, defaults to the pointer type from the data layout. More...

MVT	getFrameIndexTy (const DataLayout &DL) const
	Return the type for frame index, which is determined by the alloca address space specified through the data layout. More...

virtual MVT	getScalarShiftAmountTy (const DataLayout &, EVT) const
	EVT is not used in-tree, but is used by out-of-tree target. More...

EVT	getShiftAmountTy (EVT LHSTy, const DataLayout &DL, bool LegalTypes=true) const

virtual bool	reduceSelectOfFPConstantLoads (bool IsFPSetCC) const
	Return true if it is profitable to convert a select of FP constants into a constant pool load whose address depends on the select condition. More...

bool	hasMultipleConditionRegisters () const
	Return true if multiple condition registers are available. More...

bool	hasExtractBitsInsn () const
	Return true if the target has BitExtract instructions. More...

virtual TargetLoweringBase::LegalizeTypeAction	getPreferredVectorAction (MVT VT) const
	Return the preferred vector type legalization action. More...

virtual bool	shouldExpandBuildVectorWithShuffles (EVT, unsigned DefinedValues) const

virtual bool	isIntDivCheap (EVT VT, AttributeList Attr) const
	Return true if integer divide is usually cheaper than a sequence of several shifts, adds, and multiplies for this target. More...

virtual bool	hasStandaloneRem (EVT VT) const
	Return true if the target can handle a standalone remainder operation. More...

int	getRecipEstimateSqrtEnabled (EVT VT, MachineFunction &MF) const
	Return a ReciprocalEstimate enum value for a square root of the given type based on the function's attributes. More...

int	getRecipEstimateDivEnabled (EVT VT, MachineFunction &MF) const
	Return a ReciprocalEstimate enum value for a division of the given type based on the function's attributes. More...

int	getSqrtRefinementSteps (EVT VT, MachineFunction &MF) const
	Return the refinement step count for a square root of the given type based on the function's attributes. More...

int	getDivRefinementSteps (EVT VT, MachineFunction &MF) const
	Return the refinement step count for a division of the given type based on the function's attributes. More...

bool	isSlowDivBypassed () const
	Returns true if target has indicated at least one type should be bypassed. More...

const DenseMap< unsigned int, unsigned int > &	getBypassSlowDivWidths () const
	Returns map of slow types for division or remainder with corresponding fast types. More...

bool	isJumpExpensive () const
	Return true if Flow Control is an expensive operation that should be avoided. More...

bool	isPredictableSelectExpensive () const
	Return true if selects are only cheaper than branches if the branch is unlikely to be predicted right. More...

virtual BranchProbability	getPredictableBranchThreshold () const
	If a branch or a select condition is skewed in one direction by more than this factor, it is very likely to be predicted correctly. More...

virtual bool	isStoreBitCastBeneficial (EVT StoreVT, EVT BitcastVT) const
	Return true if the following transform is beneficial: (store (y (conv x)), y)) -> (store x, (x)) More...

virtual bool	canMergeStoresTo (unsigned AS, EVT MemVT, const SelectionDAG &DAG) const
	Returns if it's reasonable to merge stores to MemVT size. More...

virtual bool	isCtlzFast () const
	Return true if ctlz instruction is fast. More...

virtual bool	hasBitPreservingFPLogic (EVT VT) const
	Return true if it is safe to transform an integer-domain bitwise operation into the equivalent floating-point operation. More...

virtual bool	isMultiStoresCheaperThanBitsMerge (EVT LTy, EVT HTy) const
	Return true if it is cheaper to split the store of a merged int val from a pair of smaller values into multiple stores. More...

virtual bool	isMaskAndCmp0FoldingBeneficial (const Instruction &AndI) const
	Return if the target supports combining a chain like: More...

virtual bool	convertSetCCLogicToBitwiseLogic (EVT VT) const
	Use bitwise logic to make pairs of compares more efficient. More...

virtual MVT	hasFastEqualityCompare (unsigned NumBits) const
	Return the preferred operand type if the target has a quick way to compare integer values of the given size. More...

virtual bool	hasAndNotCompare (SDValue Y) const
	Return true if the target should transform: (X & Y) == Y —> (~X & Y) == 0 (X & Y) != Y —> (~X & Y) != 0. More...

virtual bool	hasAndNot (SDValue X) const
	Return true if the target has a bitwise and-not operation: X = ~A & B This can be used to simplify select or other instructions. More...

virtual bool	preferShiftsToClearExtremeBits (SDValue X) const
	There are two ways to clear extreme bits (either low or high): Mask: x & (-1 << y) (the instcombine canonical form) Shifts: x >> y << y Return true if the variant with 2 shifts is preferred. More...

virtual bool	shouldTransformSignedTruncationCheck (EVT XVT, unsigned KeptBits) const
	Should we tranform the IR-optimal check for whether given truncation down into KeptBits would be truncating or not: (add x, (1 << (KeptBits-1))) srccond (1 << KeptBits) Into it's more traditional form: ((x << C) a>> C) dstcond x Return true if we should transform. More...

bool	enableExtLdPromotion () const
	Return true if the target wants to use the optimization that turns ext(promotableInst1(...(promotableInstN(load)))) into promotedInst1(...(promotedInstN(ext(load)))). More...

virtual bool	canCombineStoreAndExtract (Type VectorTy, Value Idx, unsigned &Cost) const
	Return true if the target can combine store(extractelement VectorTy, Idx). More...

virtual bool	shouldSplatInsEltVarIndex (EVT) const
	Return true if inserting a scalar into a variable element of an undef vector is more efficiently handled by splatting the scalar instead. More...

bool	hasFloatingPointExceptions () const
	Return true if target supports floating point exceptions. More...

virtual bool	enableAggressiveFMAFusion (EVT VT) const
	Return true if target always beneficiates from combining into FMA for a given value type. More...

virtual EVT	getSetCCResultType (const DataLayout &DL, LLVMContext &Context, EVT VT) const
	Return the ValueType of the result of SETCC operations. More...

virtual MVT::SimpleValueType	getCmpLibcallReturnType () const
	Return the ValueType for comparison libcalls. More...

BooleanContent	getBooleanContents (bool isVec, bool isFloat) const
	For targets without i1 registers, this gives the nature of the high-bits of boolean values held in types wider than i1. More...

BooleanContent	getBooleanContents (EVT Type) const

Sched::Preference	getSchedulingPreference () const
	Return target scheduling preference. More...

virtual Sched::Preference	getSchedulingPreference (SDNode *) const
	Some scheduler, e.g. More...

virtual const TargetRegisterClass *	getRegClassFor (MVT VT) const
	Return the register class that should be used for the specified value type. More...

virtual const TargetRegisterClass *	getRepRegClassFor (MVT VT) const
	Return the 'representative' register class for the specified value type. More...

virtual uint8_t	getRepRegClassCostFor (MVT VT) const
	Return the cost of the 'representative' register class for the specified value type. More...

bool	isTypeLegal (EVT VT) const
	Return true if the target has native support for the specified value type. More...

const ValueTypeActionImpl &	getValueTypeActions () const

LegalizeTypeAction	getTypeAction (LLVMContext &Context, EVT VT) const
	Return how we should legalize values of this type, either it is already legal (return 'Legal') or we need to promote it to a larger type (return 'Promote'), or we need to expand it into multiple registers of smaller integer type (return 'Expand'). More...

LegalizeTypeAction	getTypeAction (MVT VT) const

EVT	getTypeToTransformTo (LLVMContext &Context, EVT VT) const
	For types supported by the target, this is an identity function. More...

EVT	getTypeToExpandTo (LLVMContext &Context, EVT VT) const
	For types supported by the target, this is an identity function. More...

unsigned	getVectorTypeBreakdown (LLVMContext &Context, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const
	Vector types are broken down into some number of legal first class types. More...

virtual unsigned	getVectorTypeBreakdownForCallingConv (LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const
	Certain targets such as MIPS require that some types such as vectors are always broken down into scalars in some contexts. More...

virtual bool	getTgtMemIntrinsic (IntrinsicInfo &, const CallInst &, MachineFunction &, unsigned) const
	Given an intrinsic, checks if on the target the intrinsic will need to map to a MemIntrinsicNode (touches memory). More...

virtual bool	isShuffleMaskLegal (ArrayRef< int >, EVT) const
	Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations, those with specific masks. More...

virtual bool	canOpTrap (unsigned Op, EVT VT) const
	Returns true if the operation can trap for the value type. More...

virtual bool	isVectorClearMaskLegal (ArrayRef< int >, EVT) const
	Similar to isShuffleMaskLegal. More...

LegalizeAction	getOperationAction (unsigned Op, EVT VT) const
	Return how this operation should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it. More...

virtual bool	isSupportedFixedPointOperation (unsigned Op, EVT VT, unsigned Scale) const
	Custom method defined by each target to indicate if an operation which may require a scale is supported natively by the target. More...

LegalizeAction	getFixedPointOperationAction (unsigned Op, EVT VT, unsigned Scale) const
	Some fixed point operations may be natively supported by the target but only for specific scales. More...

LegalizeAction	getStrictFPOperationAction (unsigned Op, EVT VT) const

bool	isOperationLegalOrCustom (unsigned Op, EVT VT) const
	Return true if the specified operation is legal on this target or can be made legal with custom lowering. More...

bool	isOperationLegalOrPromote (unsigned Op, EVT VT) const
	Return true if the specified operation is legal on this target or can be made legal using promotion. More...

bool	isOperationLegalOrCustomOrPromote (unsigned Op, EVT VT) const
	Return true if the specified operation is legal on this target or can be made legal with custom lowering or using promotion. More...

bool	isOperationCustom (unsigned Op, EVT VT) const
	Return true if the operation uses custom lowering, regardless of whether the type is legal or not. More...

virtual bool	areJTsAllowed (const Function *Fn) const
	Return true if lowering to a jump table is allowed. More...

bool	rangeFitsInWord (const APInt &Low, const APInt &High, const DataLayout &DL) const
	Check whether the range [Low,High] fits in a machine word. More...

virtual bool	isSuitableForJumpTable (const SwitchInst *SI, uint64_t NumCases, uint64_t Range) const
	Return true if lowering to a jump table is suitable for a set of case clusters which may contain `NumCases` cases, `Range` range of values. More...

bool	isSuitableForBitTests (unsigned NumDests, unsigned NumCmps, const APInt &Low, const APInt &High, const DataLayout &DL) const
	Return true if lowering to a bit test is suitable for a set of case clusters which contains `NumDests` unique destinations, `Low` and `High` as its lowest and highest case values, and expects `NumCmps` case value comparisons. More...

bool	isOperationExpand (unsigned Op, EVT VT) const
	Return true if the specified operation is illegal on this target or unlikely to be made legal with custom lowering. More...

bool	isOperationLegal (unsigned Op, EVT VT) const
	Return true if the specified operation is legal on this target. More...

LegalizeAction	getLoadExtAction (unsigned ExtType, EVT ValVT, EVT MemVT) const
	Return how this load with extension should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it. More...

bool	isLoadExtLegal (unsigned ExtType, EVT ValVT, EVT MemVT) const
	Return true if the specified load with extension is legal on this target. More...

bool	isLoadExtLegalOrCustom (unsigned ExtType, EVT ValVT, EVT MemVT) const
	Return true if the specified load with extension is legal or custom on this target. More...

LegalizeAction	getTruncStoreAction (EVT ValVT, EVT MemVT) const
	Return how this store with truncation should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it. More...

bool	isTruncStoreLegal (EVT ValVT, EVT MemVT) const
	Return true if the specified store with truncation is legal on this target. More...

bool	isTruncStoreLegalOrCustom (EVT ValVT, EVT MemVT) const
	Return true if the specified store with truncation has solution on this target. More...

LegalizeAction	getIndexedLoadAction (unsigned IdxMode, MVT VT) const
	Return how the indexed load should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it. More...

bool	isIndexedLoadLegal (unsigned IdxMode, EVT VT) const
	Return true if the specified indexed load is legal on this target. More...

LegalizeAction	getIndexedStoreAction (unsigned IdxMode, MVT VT) const
	Return how the indexed store should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it. More...

bool	isIndexedStoreLegal (unsigned IdxMode, EVT VT) const
	Return true if the specified indexed load is legal on this target. More...

LegalizeAction	getCondCodeAction (ISD::CondCode CC, MVT VT) const
	Return how the condition code should be treated: either it is legal, needs to be expanded to some other code sequence, or the target has a custom expander for it. More...

bool	isCondCodeLegal (ISD::CondCode CC, MVT VT) const
	Return true if the specified condition code is legal on this target. More...

bool	isCondCodeLegalOrCustom (ISD::CondCode CC, MVT VT) const
	Return true if the specified condition code is legal or custom on this target. More...

MVT	getTypeToPromoteTo (unsigned Op, MVT VT) const
	If the action for this operation is to promote, this method returns the ValueType to promote to. More...

EVT	getValueType (const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const
	Return the EVT corresponding to this LLVM type. More...

MVT	getSimpleValueType (const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const
	Return the MVT corresponding to this LLVM type. See getValueType. More...

virtual unsigned	getByValTypeAlignment (Type *Ty, const DataLayout &DL) const
	Return the desired alignment for ByVal or InAlloca aggregate function arguments in the caller parameter area. More...

MVT	getRegisterType (MVT VT) const
	Return the type of registers that this ValueType will eventually require. More...

MVT	getRegisterType (LLVMContext &Context, EVT VT) const
	Return the type of registers that this ValueType will eventually require. More...

unsigned	getNumRegisters (LLVMContext &Context, EVT VT) const
	Return the number of registers that this ValueType will eventually require. More...

virtual MVT	getRegisterTypeForCallingConv (LLVMContext &Context, CallingConv::ID CC, EVT VT) const
	Certain combinations of ABIs, Targets and features require that types are legal for some operations and not for other operations. More...

virtual unsigned	getNumRegistersForCallingConv (LLVMContext &Context, CallingConv::ID CC, EVT VT) const
	Certain targets require unusual breakdowns of certain types. More...

virtual unsigned	getABIAlignmentForCallingConv (Type *ArgTy, DataLayout DL) const
	Certain targets have context senstive alignment requirements, where one type has the alignment requirement of another type. More...

bool	hasBigEndianPartOrdering (EVT VT, const DataLayout &DL) const
	When splitting a value of the specified type into parts, does the Lo or Hi part come first? This usually follows the endianness, except for ppcf128, where the Hi part always comes first. More...

bool	hasTargetDAGCombine (ISD::NodeType NT) const
	If true, the target has custom DAG combine transformations that it can perform for the specified node. More...

unsigned	getGatherAllAliasesMaxDepth () const

virtual unsigned	getVaListSizeInBits (const DataLayout &DL) const
	Returns the size of the platform's va_list object. More...

unsigned	getMaxStoresPerMemset (bool OptSize) const
	Get maximum # of store operations permitted for llvm.memset. More...

unsigned	getMaxStoresPerMemcpy (bool OptSize) const
	Get maximum # of store operations permitted for llvm.memcpy. More...

virtual unsigned	getMaxGluedStoresPerMemcpy () const
	Get maximum # of store operations to be glued together. More...

unsigned	getMaxExpandSizeMemcmp (bool OptSize) const
	Get maximum # of load operations permitted for memcmp. More...

virtual unsigned	getMemcmpEqZeroLoadsPerBlock () const
	For memcmp expansion when the memcmp result is only compared equal or not-equal to 0, allow up to this number of load pairs per block. More...

unsigned	getMaxStoresPerMemmove (bool OptSize) const
	Get maximum # of store operations permitted for llvm.memmove. More...

virtual bool	allowsMisalignedMemoryAccesses (EVT, unsigned AddrSpace=0, unsigned Align=1, bool *=nullptr) const
	Determine if the target supports unaligned memory accesses. More...

bool	allowsMemoryAccess (LLVMContext &Context, const DataLayout &DL, EVT VT, unsigned AddrSpace=0, unsigned Alignment=1, bool *Fast=nullptr) const
	Return true if the target supports a memory access of this type for the given address space and alignment. More...

virtual EVT	getOptimalMemOpType (uint64_t, unsigned, unsigned, bool, bool, bool, MachineFunction &) const
	Returns the target specific optimal type for load and store operations as a result of memset, memcpy, and memmove lowering. More...

virtual bool	isSafeMemOpType (MVT) const
	Returns true if it's safe to use load / store of the specified type to expand memcpy / memset inline. More...

bool	usesUnderscoreSetJmp () const
	Determine if we should use _setjmp or setjmp to implement llvm.setjmp. More...

bool	usesUnderscoreLongJmp () const
	Determine if we should use _longjmp or longjmp to implement llvm.longjmp. More...

virtual unsigned	getMinimumJumpTableEntries () const
	Return lower limit for number of blocks in a jump table. More...

unsigned	getMinimumJumpTableDensity (bool OptForSize) const
	Return lower limit of the density in a jump table. More...

unsigned	getMaximumJumpTableSize () const
	Return upper limit for number of entries in a jump table. More...

virtual bool	isJumpTableRelative () const

unsigned	getStackPointerRegisterToSaveRestore () const
	If a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save and restore. More...

virtual unsigned	getExceptionPointerRegister (const Constant *PersonalityFn) const
	If a physical register, this returns the register that receives the exception address on entry to an EH pad. More...

virtual unsigned	getExceptionSelectorRegister (const Constant *PersonalityFn) const
	If a physical register, this returns the register that receives the exception typeid on entry to a landing pad. More...

virtual bool	needsFixedCatchObjects () const

unsigned	getJumpBufSize () const
	Returns the target's jmp_buf size in bytes (if never set, the default is 200) More...

unsigned	getJumpBufAlignment () const
	Returns the target's jmp_buf alignment in bytes (if never set, the default is 0) More...

unsigned	getMinStackArgumentAlignment () const
	Return the minimum stack alignment of an argument. More...

unsigned	getMinFunctionAlignment () const
	Return the minimum function alignment. More...

unsigned	getPrefFunctionAlignment () const
	Return the preferred function alignment. More...

virtual unsigned	getPrefLoopAlignment (MachineLoop *ML=nullptr) const
	Return the preferred loop alignment. More...

virtual bool	alignLoopsWithOptSize () const
	Should loops be aligned even when the function is marked OptSize (but not MinSize). More...

virtual Value *	getIRStackGuard (IRBuilder<> &IRB) const
	If the target has a standard location for the stack protector guard, returns the address of that location. More...

virtual void	insertSSPDeclarations (Module &M) const
	Inserts necessary declarations for SSP (stack protection) purpose. More...

virtual Value *	getSDagStackGuard (const Module &M) const
	Return the variable that's previously inserted by insertSSPDeclarations, if any, otherwise return nullptr. More...

virtual bool	useStackGuardXorFP () const
	If this function returns true, stack protection checks should XOR the frame pointer (or whichever pointer is used to address locals) into the stack guard value before checking it. More...

virtual Value *	getSSPStackGuardCheck (const Module &M) const
	If the target has a standard stack protection check function that performs validation and error handling, returns the function. More...

virtual Value *	getSafeStackPointerLocation (IRBuilder<> &IRB) const
	Returns the target-specific address of the unsafe stack pointer. More...

virtual StringRef	getStackProbeSymbolName (MachineFunction &MF) const
	Returns the name of the symbol used to emit stack probes or the empty string if not applicable. More...

virtual bool	isNoopAddrSpaceCast (unsigned SrcAS, unsigned DestAS) const
	Returns true if a cast between SrcAS and DestAS is a noop. More...

virtual bool	isCheapAddrSpaceCast (unsigned SrcAS, unsigned DestAS) const
	Returns true if a cast from SrcAS to DestAS is "cheap", such that e.g. More...

virtual bool	shouldAlignPointerArgs (CallInst *, unsigned &, unsigned &) const
	Return true if the pointer arguments to CI should be aligned by aligning the object whose address is being passed. More...

virtual void	emitAtomicCmpXchgNoStoreLLBalance (IRBuilder<> &Builder) const

virtual bool	shouldExpandAtomicStoreInIR (StoreInst *SI) const
	Returns true if the given (atomic) store should be expanded by the IR-level AtomicExpand pass into an "atomic xchg" which ignores its input. More...

virtual bool	shouldSignExtendTypeInLibCall (EVT Type, bool IsSigned) const
	Returns true if arguments should be sign-extended in lib calls. More...

virtual AtomicExpansionKind	shouldExpandAtomicLoadInIR (LoadInst *LI) const
	Returns how the given (atomic) load should be expanded by the IR-level AtomicExpand pass. More...

virtual AtomicExpansionKind	shouldExpandAtomicCmpXchgInIR (AtomicCmpXchgInst *AI) const
	Returns how the given atomic cmpxchg should be expanded by the IR-level AtomicExpand pass. More...

virtual LoadInst *	lowerIdempotentRMWIntoFencedLoad (AtomicRMWInst *RMWI) const
	On some platforms, an AtomicRMW that never actually modifies the value (such as fetch_add of 0) can be turned into a fence followed by an atomic load. More...

virtual ISD::NodeType	getExtendForAtomicOps () const
	Returns how the platform's atomic operations are extended (ZERO_EXTEND, SIGN_EXTEND, or ANY_EXTEND). More...

virtual bool	shouldNormalizeToSelectSequence (LLVMContext &Context, EVT VT) const
	Returns true if we should normalize select(N0&N1, X, Y) => select(N0, select(N1, X, Y), Y) and select(N0\|N1, X, Y) => select(N0, select(N1, X, Y, Y)) if it is likely that it saves us from materializing N0 and N1 in an integer register. More...

virtual bool	convertSelectOfConstantsToMath (EVT VT) const
	Return true if a select of constants (select Cond, C1, C2) should be transformed into simple math ops with the condition value. More...

virtual bool	decomposeMulByConstant (EVT VT, SDValue C) const
	Return true if it is profitable to transform an integer multiplication-by-constant into simpler operations like shifts and adds. More...

virtual bool	shouldUseStrictFP_TO_INT (EVT FpVT, EVT IntVT, bool IsSigned) const
	Return true if it is more correct/profitable to use strict FP_TO_INT conversion operations - canonicalizing the FP source value instead of converting all cases and then selecting based on value. More...

virtual bool	getAddrModeArguments (IntrinsicInst , SmallVectorImpl< Value > &, Type *&) const
	CodeGenPrepare sinks address calculations into the same BB as Load/Store instructions reading the address. More...

virtual bool	isLegalAddressingMode (const DataLayout &DL, const AddrMode &AM, Type Ty, unsigned AddrSpace, Instruction I=nullptr) const
	Return true if the addressing mode represented by AM is legal for this target, for a load/store of the specified type. More...

virtual int	getScalingFactorCost (const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS=0) const
	Return the cost of the scaling factor used in the addressing mode represented by AM for this target, for a load/store of the specified type. More...

virtual bool	isLegalICmpImmediate (int64_t) const
	Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructions which can compare a register against the immediate without having to materialize the immediate into a register. More...

virtual bool	isLegalAddImmediate (int64_t) const
	Return true if the specified immediate is legal add immediate, that is the target has add instructions which can add a register with the immediate without having to materialize the immediate into a register. More...

virtual bool	isLegalStoreImmediate (int64_t Value) const
	Return true if the specified immediate is legal for the value input of a store instruction. More...

virtual bool	isVectorShiftByScalarCheap (Type *Ty) const
	Return true if it's significantly cheaper to shift a vector by a uniform scalar than by an amount which will vary across each lane. More...

virtual bool	isCommutativeBinOp (unsigned Opcode) const
	Returns true if the opcode is a commutative binary operation. More...

virtual bool	allowTruncateForTailCall (Type FromTy, Type ToTy) const
	Return true if a truncation from FromTy to ToTy is permitted when deciding whether a call is in tail position. More...

virtual bool	isProfitableToHoist (Instruction *I) const

bool	isExtFree (const Instruction *I) const
	Return true if the extension represented by `I` is free. More...

bool	isExtLoad (const LoadInst Load, const Instruction Ext, const DataLayout &DL) const
	Return true if `Load` and `Ext` can form an ExtLoad. More...

virtual bool	isSExtCheaperThanZExt (EVT FromTy, EVT ToTy) const
	Return true if sign-extension from FromTy to ToTy is cheaper than zero-extension. More...

virtual bool	hasPairedLoad (EVT, unsigned &) const
	Return true if the target supplies and combines to a paired load two loaded values of type LoadedType next to each other in memory. More...

virtual bool	hasVectorBlend () const
	Return true if the target has a vector blend instruction. More...

virtual unsigned	getMaxSupportedInterleaveFactor () const
	Get the maximum supported factor for interleaved memory accesses. More...

virtual bool	lowerInterleavedLoad (LoadInst LI, ArrayRef< ShuffleVectorInst > Shuffles, ArrayRef< unsigned > Indices, unsigned Factor) const
	Lower an interleaved load to target specific intrinsics. More...

virtual bool	lowerInterleavedStore (StoreInst SI, ShuffleVectorInst SVI, unsigned Factor) const
	Lower an interleaved store to target specific intrinsics. More...

virtual bool	isFPExtFree (EVT DestVT, EVT SrcVT) const
	Return true if an fpext operation is free (for instance, because single-precision floating-point numbers are implicitly extended to double-precision). More...

virtual bool	isFPExtFoldable (unsigned Opcode, EVT DestVT, EVT SrcVT) const
	Return true if an fpext operation input to an `Opcode` operation is free (for instance, because half-precision floating-point numbers are implicitly extended to float-precision) for an FMA instruction. More...

virtual bool	isVectorLoadExtDesirable (SDValue ExtVal) const
	Return true if folding a vector load into ExtVal (a sign, zero, or any extend node) is profitable. More...

virtual bool	isFMAFasterThanFMulAndFAdd (EVT) const
	Return true if an FMA operation is faster than a pair of fmul and fadd instructions. More...

virtual bool	shouldConvertConstantLoadToIntImm (const APInt &Imm, Type *Ty) const
	Return true if it is beneficial to convert a load of a constant to just the constant itself. More...

virtual bool	isExtractSubvectorCheap (EVT ResVT, EVT SrcVT, unsigned Index) const
	Return true if EXTRACT_SUBVECTOR is cheap for extracting this result type from this source type with this index. More...

virtual bool	shouldScalarizeBinop (SDValue VecOp) const
	Try to convert an extract element of a vector binary operation into an extract element followed by a scalar operation. More...

virtual bool	shouldConsiderGEPOffsetSplit () const

void	setLibcallName (RTLIB::Libcall Call, const char *Name)
	Rename the default libcall routine name for the specified libcall. More...

const char *	getLibcallName (RTLIB::Libcall Call) const
	Get the libcall routine name for the specified libcall. More...

void	setCmpLibcallCC (RTLIB::Libcall Call, ISD::CondCode CC)
	Override the default CondCode to be used to test the result of the comparison libcall against zero. More...

ISD::CondCode	getCmpLibcallCC (RTLIB::Libcall Call) const
	Get the CondCode that's to be used to test the result of the comparison libcall against zero. More...

void	setLibcallCallingConv (RTLIB::Libcall Call, CallingConv::ID CC)
	Set the CallingConv that should be used for the specified libcall. More...

CallingConv::ID	getLibcallCallingConv (RTLIB::Libcall Call) const
	Get the CallingConv that should be used for the specified libcall. More...

virtual void	finalizeLowering (MachineFunction &MF) const
	Execute target specific actions to finalize target lowering. More...

int	InstructionOpcodeToISD (unsigned Opcode) const
	Get the ISD node that corresponds to the Instruction class opcode. More...

std::pair< int, MVT >	getTypeLegalizationCost (const DataLayout &DL, Type *Ty) const
	Estimate the cost of type-legalization and the legalized type. More...

unsigned	getMaxAtomicSizeInBitsSupported () const
	Returns the maximum atomic operation size (in bits) supported by the backend. More...

unsigned	getMinCmpXchgSizeInBits () const
	Returns the size of the smallest cmpxchg or ll/sc instruction the backend supports. More...

bool	supportsUnalignedAtomics () const
	Whether the target supports unaligned atomic operations. More...

virtual bool	shouldInsertFencesForAtomic (const Instruction *I) const
	Whether AtomicExpandPass should automatically insert fences and reduce ordering for this atomic. More...

virtual Value *	emitLoadLinked (IRBuilder<> &Builder, Value *Addr, AtomicOrdering Ord) const
	Perform a load-linked operation on Addr, returning a "Value *" with the corresponding pointee type. More...

virtual Value *	emitStoreConditional (IRBuilder<> &Builder, Value Val, Value Addr, AtomicOrdering Ord) const
	Perform a store-conditional operation to Addr. More...

virtual Value *	emitMaskedAtomicRMWIntrinsic (IRBuilder<> &Builder, AtomicRMWInst AI, Value AlignedAddr, Value Incr, Value Mask, Value *ShiftAmt, AtomicOrdering Ord) const
	Perform a masked atomicrmw using a target-specific intrinsic. More...

virtual Value *	emitMaskedAtomicCmpXchgIntrinsic (IRBuilder<> &Builder, AtomicCmpXchgInst CI, Value AlignedAddr, Value CmpVal, Value NewVal, Value *Mask, AtomicOrdering Ord) const
	Perform a masked cmpxchg using a target-specific intrinsic. More...

virtual Instruction *	emitLeadingFence (IRBuilder<> &Builder, Instruction *Inst, AtomicOrdering Ord) const
	Inserts in the IR a target-specific intrinsic specifying a fence. More...

virtual Instruction *	emitTrailingFence (IRBuilder<> &Builder, Instruction *Inst, AtomicOrdering Ord) const

Static Public Member Functions
static unsigned	numBitsUnsigned (SDValue Op, SelectionDAG &DAG)

static unsigned	numBitsSigned (SDValue Op, SelectionDAG &DAG)

static SDValue	stripBitcast (SDValue Val)

static bool	allUsesHaveSourceMods (const SDNode *N, unsigned CostThreshold=4)

static CCAssignFn *	CCAssignFnForCall (CallingConv::ID CC, bool IsVarArg)
	Selects the correct CCAssignFn for a given CallingConvention value. More...

static CCAssignFn *	CCAssignFnForReturn (CallingConv::ID CC, bool IsVarArg)

Static Public Member Functions inherited from llvm::TargetLoweringBase
static ISD::NodeType	getExtendForContent (BooleanContent Content)

Protected Member Functions
SDValue	LowerEXTRACT_SUBVECTOR (SDValue Op, SelectionDAG &DAG) const

SDValue	LowerCONCAT_VECTORS (SDValue Op, SelectionDAG &DAG) const

SDValue	LowerFREM (SDValue Op, SelectionDAG &DAG) const
	Split a vector store into multiple scalar stores. More...

SDValue	LowerFCEIL (SDValue Op, SelectionDAG &DAG) const

SDValue	LowerFTRUNC (SDValue Op, SelectionDAG &DAG) const

SDValue	LowerFRINT (SDValue Op, SelectionDAG &DAG) const

SDValue	LowerFNEARBYINT (SDValue Op, SelectionDAG &DAG) const

SDValue	LowerFROUND32_16 (SDValue Op, SelectionDAG &DAG) const

SDValue	LowerFROUND64 (SDValue Op, SelectionDAG &DAG) const

SDValue	LowerFROUND (SDValue Op, SelectionDAG &DAG) const

SDValue	LowerFFLOOR (SDValue Op, SelectionDAG &DAG) const

SDValue	LowerFLOG (SDValue Op, SelectionDAG &DAG, double Log2BaseInverted) const

SDValue	lowerFEXP (SDValue Op, SelectionDAG &DAG) const

SDValue	LowerCTLZ_CTTZ (SDValue Op, SelectionDAG &DAG) const

SDValue	LowerINT_TO_FP32 (SDValue Op, SelectionDAG &DAG, bool Signed) const

SDValue	LowerINT_TO_FP64 (SDValue Op, SelectionDAG &DAG, bool Signed) const

SDValue	LowerUINT_TO_FP (SDValue Op, SelectionDAG &DAG) const

SDValue	LowerSINT_TO_FP (SDValue Op, SelectionDAG &DAG) const

SDValue	LowerFP64_TO_INT (SDValue Op, SelectionDAG &DAG, bool Signed) const

SDValue	LowerFP_TO_FP16 (SDValue Op, SelectionDAG &DAG) const

SDValue	LowerFP_TO_UINT (SDValue Op, SelectionDAG &DAG) const

SDValue	LowerFP_TO_SINT (SDValue Op, SelectionDAG &DAG) const

SDValue	LowerSIGN_EXTEND_INREG (SDValue Op, SelectionDAG &DAG) const

bool	shouldCombineMemoryType (EVT VT) const

SDValue	performLoadCombine (SDNode *N, DAGCombinerInfo &DCI) const

SDValue	performStoreCombine (SDNode *N, DAGCombinerInfo &DCI) const

SDValue	performAssertSZExtCombine (SDNode *N, DAGCombinerInfo &DCI) const

SDValue	splitBinaryBitConstantOpImpl (DAGCombinerInfo &DCI, const SDLoc &SL, unsigned Opc, SDValue LHS, uint32_t ValLo, uint32_t ValHi) const
	Split the 64-bit value `LHS` into two 32-bit components, and perform the binary operation `Opc` to it with the corresponding constant operands. More...

SDValue	performShlCombine (SDNode *N, DAGCombinerInfo &DCI) const

SDValue	performSraCombine (SDNode *N, DAGCombinerInfo &DCI) const

SDValue	performSrlCombine (SDNode *N, DAGCombinerInfo &DCI) const

SDValue	performTruncateCombine (SDNode *N, DAGCombinerInfo &DCI) const

SDValue	performMulCombine (SDNode *N, DAGCombinerInfo &DCI) const

SDValue	performMulhsCombine (SDNode *N, DAGCombinerInfo &DCI) const

SDValue	performMulhuCombine (SDNode *N, DAGCombinerInfo &DCI) const

SDValue	performMulLoHi24Combine (SDNode *N, DAGCombinerInfo &DCI) const

SDValue	performCtlz_CttzCombine (const SDLoc &SL, SDValue Cond, SDValue LHS, SDValue RHS, DAGCombinerInfo &DCI) const

SDValue	performSelectCombine (SDNode *N, DAGCombinerInfo &DCI) const

bool	isConstantCostlierToNegate (SDValue N) const

SDValue	performFNegCombine (SDNode *N, DAGCombinerInfo &DCI) const

SDValue	performFAbsCombine (SDNode *N, DAGCombinerInfo &DCI) const

SDValue	performRcpCombine (SDNode *N, DAGCombinerInfo &DCI) const

virtual SDValue	LowerGlobalAddress (AMDGPUMachineFunction *MFI, SDValue Op, SelectionDAG &DAG) const

std::pair< SDValue, SDValue >	split64BitValue (SDValue Op, SelectionDAG &DAG) const
	Return 64-bit value Op as two 32-bit integers. More...

SDValue	getLoHalf64 (SDValue Op, SelectionDAG &DAG) const

SDValue	getHiHalf64 (SDValue Op, SelectionDAG &DAG) const

SDValue	SplitVectorLoad (SDValue Op, SelectionDAG &DAG) const
	Split a vector load into 2 loads of half the vector. More...

SDValue	SplitVectorStore (SDValue Op, SelectionDAG &DAG) const
	Split a vector store into 2 stores of half the vector. More...

SDValue	LowerSTORE (SDValue Op, SelectionDAG &DAG) const

SDValue	LowerSDIVREM (SDValue Op, SelectionDAG &DAG) const

SDValue	LowerUDIVREM (SDValue Op, SelectionDAG &DAG) const

SDValue	LowerDIVREM24 (SDValue Op, SelectionDAG &DAG, bool sign) const

void	LowerUDIVREM64 (SDValue Op, SelectionDAG &DAG, SmallVectorImpl< SDValue > &Results) const

void	analyzeFormalArgumentsCompute (CCState &State, const SmallVectorImpl< ISD::InputArg > &Ins) const
	The SelectionDAGBuilder will automatically promote function arguments with illegal types. More...

Protected Member Functions inherited from llvm::TargetLoweringBase
void	initActions ()
	Initialize all of the actions to default values. More...

Value *	getDefaultSafeStackPointerLocation (IRBuilder<> &IRB, bool UseTLS) const

void	setBooleanContents (BooleanContent Ty)
	Specify how the target extends the result of integer and floating point boolean values from i1 to a wider type. More...

void	setBooleanContents (BooleanContent IntTy, BooleanContent FloatTy)
	Specify how the target extends the result of integer and floating point boolean values from i1 to a wider type. More...

void	setBooleanVectorContents (BooleanContent Ty)
	Specify how the target extends the result of a vector boolean value from a vector of i1 to a wider type. More...

void	setSchedulingPreference (Sched::Preference Pref)
	Specify the target scheduling preference. More...

void	setUseUnderscoreSetJmp (bool Val)
	Indicate whether this target prefers to use _setjmp to implement llvm.setjmp or the version without _. More...

void	setUseUnderscoreLongJmp (bool Val)
	Indicate whether this target prefers to use _longjmp to implement llvm.longjmp or the version without _. More...

void	setMinimumJumpTableEntries (unsigned Val)
	Indicate the minimum number of blocks to generate jump tables. More...

void	setMaximumJumpTableSize (unsigned)
	Indicate the maximum number of entries in jump tables. More...

void	setStackPointerRegisterToSaveRestore (unsigned R)
	If set to a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save and restore. More...

void	setHasMultipleConditionRegisters (bool hasManyRegs=true)
	Tells the code generator that the target has multiple (allocatable) condition registers that can be used to store the results of comparisons for use by selects and conditional branches. More...

void	setHasExtractBitsInsn (bool hasExtractInsn=true)
	Tells the code generator that the target has BitExtract instructions. More...

void	setJumpIsExpensive (bool isExpensive=true)
	Tells the code generator not to expand logic operations on comparison predicates into separate sequences that increase the amount of flow control. More...

void	setHasFloatingPointExceptions (bool FPExceptions=true)
	Tells the code generator that this target supports floating point exceptions and cares about preserving floating point exception behavior. More...

void	addBypassSlowDiv (unsigned int SlowBitWidth, unsigned int FastBitWidth)
	Tells the code generator which bitwidths to bypass. More...

void	addRegisterClass (MVT VT, const TargetRegisterClass *RC)
	Add the specified register class as an available regclass for the specified value type. More...

virtual std::pair< const TargetRegisterClass *, uint8_t >	findRepresentativeClass (const TargetRegisterInfo *TRI, MVT VT) const
	Return the largest legal super-reg register class of the register class for the specified type and its associated "cost". More...

void	computeRegisterProperties (const TargetRegisterInfo *TRI)
	Once all of the register classes are added, this allows us to compute derived properties we expose. More...

void	setOperationAction (unsigned Op, MVT VT, LegalizeAction Action)
	Indicate that the specified operation does not work with the specified type and indicate what to do about it. More...

void	setLoadExtAction (unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)
	Indicate that the specified load with extension does not work with the specified type and indicate what to do about it. More...

void	setTruncStoreAction (MVT ValVT, MVT MemVT, LegalizeAction Action)
	Indicate that the specified truncating store does not work with the specified type and indicate what to do about it. More...

void	setIndexedLoadAction (unsigned IdxMode, MVT VT, LegalizeAction Action)
	Indicate that the specified indexed load does or does not work with the specified type and indicate what to do abort it. More...

void	setIndexedStoreAction (unsigned IdxMode, MVT VT, LegalizeAction Action)
	Indicate that the specified indexed store does or does not work with the specified type and indicate what to do about it. More...

void	setCondCodeAction (ISD::CondCode CC, MVT VT, LegalizeAction Action)
	Indicate that the specified condition code is or isn't supported on the target and indicate what to do about it. More...

void	AddPromotedToType (unsigned Opc, MVT OrigVT, MVT DestVT)
	If Opc/OrigVT is specified as being promoted, the promotion code defaults to trying a larger integer/fp until it can find one that works. More...

void	setOperationPromotedToType (unsigned Opc, MVT OrigVT, MVT DestVT)
	Convenience method to set an operation to Promote and specify the type in a single call. More...

void	setTargetDAGCombine (ISD::NodeType NT)
	Targets should invoke this method for each target independent node that they want to provide a custom DAG combiner for by implementing the PerformDAGCombine virtual method. More...

void	setJumpBufSize (unsigned Size)
	Set the target's required jmp_buf buffer size (in bytes); default is 200. More...

void	setJumpBufAlignment (unsigned Align)
	Set the target's required jmp_buf buffer alignment (in bytes); default is 0. More...

void	setMinFunctionAlignment (unsigned Align)
	Set the target's minimum function alignment (in log2(bytes)) More...

void	setPrefFunctionAlignment (unsigned Align)
	Set the target's preferred function alignment. More...

void	setPrefLoopAlignment (unsigned Align)
	Set the target's preferred loop alignment. More...

void	setMinStackArgumentAlignment (unsigned Align)
	Set the minimum stack alignment of an argument (in log2(bytes)). More...

void	setMaxAtomicSizeInBitsSupported (unsigned SizeInBits)
	Set the maximum atomic operation size supported by the backend. More...

void	setMinCmpXchgSizeInBits (unsigned SizeInBits)
	Sets the minimum cmpxchg or ll/sc size supported by the backend. More...

void	setSupportsUnalignedAtomics (bool UnalignedSupported)
	Sets whether unaligned atomic operations are supported. More...

virtual bool	isExtFreeImpl (const Instruction *I) const
	Return true if the extension represented by `I` is free. More...

bool	isLegalRC (const TargetRegisterInfo &TRI, const TargetRegisterClass &RC) const
	Return true if the value types that can be represented by the specified register class are all legal. More...

MachineBasicBlock *	emitPatchPoint (MachineInstr &MI, MachineBasicBlock *MBB) const
	Replace/modify any TargetFrameIndex operands with a targte-dependent sequence of memory operands that is recognized by PrologEpilogInserter. More...

MachineBasicBlock *	emitXRayCustomEvent (MachineInstr &MI, MachineBasicBlock *MBB) const
	Replace/modify the XRay custom event operands with target-dependent details. More...

MachineBasicBlock *	emitXRayTypedEvent (MachineInstr &MI, MachineBasicBlock *MBB) const
	Replace/modify the XRay typed event operands with target-dependent details. More...

Static Protected Member Functions
static EVT	getEquivalentMemType (LLVMContext &Context, EVT VT)

Additional Inherited Members
Protected Attributes inherited from llvm::TargetLoweringBase
ValueTypeActionImpl	ValueTypeActions

unsigned	GatherAllAliasesMaxDepth
	Depth that GatherAllAliases should should continue looking for chain dependencies when trying to find a more preferable chain. More...

unsigned	MaxStoresPerMemset
	Specify maximum number of store instructions per memset call. More...

unsigned	MaxStoresPerMemsetOptSize
	Maximum number of stores operations that may be substituted for the call to memset, used for functions with OptSize attribute. More...

unsigned	MaxStoresPerMemcpy
	Specify maximum bytes of store instructions per memcpy call. More...

unsigned	MaxGluedStoresPerMemcpy = 0
	Specify max number of store instructions to glue in inlined memcpy. More...

unsigned	MaxStoresPerMemcpyOptSize
	Maximum number of store operations that may be substituted for a call to memcpy, used for functions with OptSize attribute. More...

unsigned	MaxLoadsPerMemcmp

unsigned	MaxLoadsPerMemcmpOptSize

unsigned	MaxStoresPerMemmove
	Specify maximum bytes of store instructions per memmove call. More...

unsigned	MaxStoresPerMemmoveOptSize
	Maximum number of store instructions that may be substituted for a call to memmove, used for functions with OptSize attribute. More...

bool	PredictableSelectIsExpensive
	Tells the code generator that select is more expensive than a branch if the branch is usually predicted right. More...

bool	EnableExtLdPromotion

Detailed Description

Definition at line 29 of file AMDGPUISelLowering.h.

Member Enumeration Documentation

◆ ImplicitParameter

enum llvm::AMDGPUTargetLowering::ImplicitParameter

Enumerator
FIRST_IMPLICIT
GRID_DIM
GRID_OFFSET

Definition at line 296 of file AMDGPUISelLowering.h.

Constructor & Destructor Documentation

◆ AMDGPUTargetLowering()

AMDGPUTargetLowering::AMDGPUTargetLowering	(	const TargetMachine &	TM,
		const AMDGPUSubtarget &	STI
	)

Definition at line 144 of file AMDGPUISelLowering.cpp.

Member Function Documentation

◆ addTokenForArgument()

SDValue AMDGPUTargetLowering::addTokenForArgument	(	SDValue	Chain,
		SelectionDAG &	DAG,
		MachineFrameInfo &	MFI,
		int	ClobberedFI
	)		const

Definition at line 1058 of file AMDGPUISelLowering.cpp.

References llvm::SelectionDAG::getEntryNode(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::MachineFrameInfo::getObjectOffset(), llvm::MachineFrameInfo::getObjectSize(), llvm::MVT::Other, llvm::SmallVectorTemplateBase< T >::push_back(), llvm::ISD::TokenFactor, llvm::SDNode::use_begin(), and llvm::SDNode::use_end().

Referenced by llvm::SITargetLowering::LowerCall(), and stripBitcast().

◆ aggressivelyPreferBuildVectorSources()

bool AMDGPUTargetLowering::aggressivelyPreferBuildVectorSources ( EVT VecVT ) const

overridevirtual

Reimplemented from llvm::TargetLoweringBase.

Definition at line 776 of file AMDGPUISelLowering.cpp.

Referenced by stripBitcast().

◆ allUsesHaveSourceMods()

bool AMDGPUTargetLowering::allUsesHaveSourceMods	(	const SDNode *	N,
		unsigned	CostThreshold = `4`
	)

static

Definition at line 609 of file AMDGPUISelLowering.cpp.

References llvm::EVT::getScalarType(), llvm::EVT::getSimpleVT(), llvm::SDNode::getValueType(), hasSourceMods(), opMustUseVOP3Encoding(), and llvm::SDNode::uses().

Referenced by isClampZeroToOne(), performFNegCombine(), and stripBitcast().

◆ analyzeFormalArgumentsCompute()

void AMDGPUTargetLowering::analyzeFormalArgumentsCompute	(	CCState &	State,
		const SmallVectorImpl< ISD::InputArg > &	Ins
	)		const

protected

The SelectionDAGBuilder will automatically promote function arguments with illegal types.

However, this does not work for the AMDGPU targets since the function arguments are stored in memory as these illegal types. In order to handle this properly we need to get the original types sizes from the LLVM IR Function and fixup the ISD:InputArg values before passing them to AnalyzeFormalArguments() When the SelectionDAGBuilder computes the Ins, it takes care of splitting input values across multiple registers. Each item in the Ins array represents a single value that will be stored in registers. Ins[x].VT is the value type of the value that will be stored in the register, so whatever SDNode we lower the argument to needs to be this type.

In order to correctly lower the arguments we need to know the size of each argument. Since Ins[x].VT gives us the size of the register that will hold the value, we need to look at Ins[x].ArgVT to see the 'real' type for the orignal function argument so that we can deduce the correct memory type to use for Ins[x]. In most cases the correct memory type will be Ins[x].ArgVT. However, this will not always be the case. If, for example, we have a kernel argument of type v8i8, this argument will be split into 8 parts and each part will be represented by its own item in the Ins array. For each part the Ins[x].ArgVT will be the v8i8, which is the full type of the argument before it was split. From this, we deduce that the memory type for each individual part is i8. We pass the memory type as LocVT to the calling convention analysis function and the register type (Ins[x].VT) as the ValVT.

Definition at line 921 of file AMDGPUISelLowering.cpp.

References llvm::CCState::addLoc(), llvm::AMDGPU::HSAMD::Kernel::Arg::Key::Align, llvm::alignTo(), Arg, llvm::Function::args(), assert(), llvm::ComputeValueVTs(), llvm::CCValAssign::Full, llvm::AMDGPUSubtarget::get(), llvm::DataLayout::getABITypeAlignment(), llvm::Function::getCallingConv(), llvm::Module::getContext(), llvm::CCState::getContext(), llvm::CCValAssign::getCustomMem(), llvm::Module::getDataLayout(), llvm::AMDGPUSubtarget::getExplicitKernelArgOffset(), llvm::MachineFunction::getFunction(), llvm::EVT::getIntegerVT(), llvm::CCState::getMachineFunction(), llvm::TargetLoweringBase::getNumRegistersForCallingConv(), llvm::GlobalValue::getParent(), llvm::EVT::getPow2VectorType(), llvm::TargetLoweringBase::getRegisterTypeForCallingConv(), llvm::EVT::getScalarType(), llvm::MVT::getScalarType(), llvm::EVT::getSimpleVT(), llvm::EVT::getStoreSize(), llvm::EVT::getStoreSizeInBits(), llvm::Value::getType(), llvm::DataLayout::getTypeAllocSize(), llvm::EVT::getVectorNumElements(), llvm::MVT::getVectorNumElements(), llvm::EVT::getVectorVT(), llvm::EVT::isExtended(), llvm::MVT::isFloatingPoint(), llvm::MVT::isInteger(), llvm::EVT::isVector(), llvm::MVT::isVector(), llvm_unreachable, llvm::max(), llvm::SmallVectorBase::size(), and llvm::ARM_MB::ST.

Referenced by llvm::R600TargetLowering::LowerFormalArguments(), and llvm::SITargetLowering::LowerFormalArguments().

◆ CCAssignFnForCall()

CCAssignFn * AMDGPUTargetLowering::CCAssignFnForCall	(	CallingConv::ID	CC,
		bool	IsVarArg
	)

static

Selects the correct CCAssignFn for a given CallingConvention value.

Definition at line 1048 of file AMDGPUISelLowering.cpp.

References llvm::AMDGPUCallLowering::CCAssignFnForCall().

Referenced by llvm::SITargetLowering::isEligibleForTailCallOptimization(), llvm::SITargetLowering::LowerCall(), llvm::SITargetLowering::LowerFormalArguments(), and stripBitcast().

◆ CCAssignFnForReturn()

CCAssignFn * AMDGPUTargetLowering::CCAssignFnForReturn	(	CallingConv::ID	CC,
		bool	IsVarArg
	)

static

Definition at line 1053 of file AMDGPUISelLowering.cpp.

References llvm::AMDGPUCallLowering::CCAssignFnForReturn().

Referenced by llvm::SITargetLowering::CanLowerReturn(), llvm::SITargetLowering::LowerCallResult(), llvm::SITargetLowering::LowerReturn(), and stripBitcast().

◆ combineFMinMaxLegacy()

SDValue AMDGPUTargetLowering::combineFMinMaxLegacy	(	const SDLoc &	DL,
		EVT	VT,
		SDValue	LHS,
		SDValue	RHS,
		SDValue	True,
		SDValue	False,
		SDValue	CC,
		DAGCombinerInfo &	DCI
	)		const

Generate Min/Max node.

Definition at line 1271 of file AMDGPUISelLowering.cpp.

References llvm::AfterLegalizeDAG, llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::AMDGPUISD::FMAX_LEGACY, llvm::AMDGPUISD::FMIN_LEGACY, llvm::TargetLowering::DAGCombinerInfo::getDAGCombineLevel(), llvm::SelectionDAG::getNode(), llvm::TargetLowering::DAGCombinerInfo::isCalledByLegalizer(), llvm_unreachable, llvm::ISD::SETCC_INVALID, llvm::ISD::SETEQ, llvm::ISD::SETFALSE, llvm::ISD::SETFALSE2, llvm::ISD::SETGE, llvm::ISD::SETGT, llvm::ISD::SETLE, llvm::ISD::SETLT, llvm::ISD::SETNE, llvm::ISD::SETO, llvm::ISD::SETOEQ, llvm::ISD::SETOGE, llvm::ISD::SETOGT, llvm::ISD::SETOLE, llvm::ISD::SETOLT, llvm::ISD::SETONE, llvm::ISD::SETTRUE, llvm::ISD::SETTRUE2, llvm::ISD::SETUEQ, llvm::ISD::SETUGE, llvm::ISD::SETUGT, llvm::ISD::SETULE, llvm::ISD::SETULT, llvm::ISD::SETUNE, and llvm::ISD::SETUO.

Referenced by performSelectCombine(), llvm::R600TargetLowering::ReplaceNodeResults(), and stripBitcast().

◆ computeKnownBitsForTargetNode()

void AMDGPUTargetLowering::computeKnownBitsForTargetNode	(	const SDValue	Op,
		KnownBits &	Known,
		const APInt &	DemandedElts,
		const SelectionDAG &	DAG,
		unsigned	Depth = `0`
	)		const

overridevirtual

Determine which of the bits specified in Mask are known to be either zero or one and return them in the KnownZero and KnownOne bitsets.

Reimplemented from llvm::TargetLowering.

Definition at line 4265 of file AMDGPUISelLowering.cpp.

References llvm::Intrinsic::amdgcn_mbcnt_hi, llvm::Intrinsic::amdgcn_mbcnt_lo, llvm::AMDGPUISD::BFE_I32, llvm::AMDGPUISD::BFE_U32, llvm::AMDGPUISD::BORROW, llvm::AMDGPUISD::CARRY, llvm::SelectionDAG::computeKnownBits(), llvm::KnownBits::countMinLeadingZeros(), llvm::KnownBits::countMinSignBits(), llvm::KnownBits::countMinTrailingZeros(), llvm::dyn_cast(), llvm::AMDGPUISD::FP16_ZEXT, llvm::AMDGPUISD::FP_TO_FP16, llvm::KnownBits::getBitWidth(), llvm::APInt::getHighBitsSet(), llvm::SelectionDAG::getMachineFunction(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getSizeInBits(), llvm::MachineFunction::getSubtarget(), llvm::SDValue::getValueType(), llvm::GCNSubtarget::getWavefrontSizeLog2(), llvm::ConstantSDNode::getZExtValue(), llvm::APInt::getZExtValue(), I, llvm::ISD::INTRINSIC_WO_CHAIN, llvm::KnownBits::isNegative(), llvm::KnownBits::isNonNegative(), llvm::AMDGPUISD::MUL_I24, llvm::AMDGPUISD::MUL_U24, llvm::KnownBits::One, llvm::AMDGPUISD::PERM, llvm::KnownBits::resetAll(), llvm::APInt::setHighBits(), llvm::APInt::setLowBits(), Size, llvm::ARM_MB::ST, llvm::KnownBits::trunc(), and llvm::KnownBits::Zero.

Referenced by isFsqrtCheap().

◆ ComputeNumSignBitsForTargetNode()

unsigned AMDGPUTargetLowering::ComputeNumSignBitsForTargetNode	(	SDValue	Op,
		const APInt &	DemandedElts,
		const SelectionDAG &	DAG,
		unsigned	Depth = `0`
	)		const

overridevirtual

This method can be implemented by targets that want to expose additional information about sign bits to the DAG Combiner.

The DemandedElts argument allows us to only collect the minimum sign bits that are shared by the requested vector elements.

Reimplemented from llvm::TargetLowering.

Definition at line 4390 of file AMDGPUISelLowering.cpp.

References llvm::AMDGPUISD::BFE_I32, llvm::AMDGPUISD::BFE_U32, llvm::AMDGPUISD::BORROW, llvm::AMDGPUISD::CARRY, llvm::SelectionDAG::ComputeNumSignBits(), llvm::dyn_cast(), llvm::AMDGPUISD::FP16_ZEXT, llvm::AMDGPUISD::FP_TO_FP16, llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::ConstantSDNode::getZExtValue(), llvm::isNullConstant(), and llvm::max().

Referenced by isFsqrtCheap().

◆ CreateLiveInRegister() [1/2]

SDValue AMDGPUTargetLowering::CreateLiveInRegister	(	SelectionDAG &	DAG,
		const TargetRegisterClass *	RC,
		unsigned	Reg,
		EVT	VT,
		const SDLoc &	SL,
		bool	RawReg = `false`
	)		const

Helper function that adds Reg to the LiveIn list of the DAG's MachineFunction.

Returns: a RegisterSDNode representing Reg if RawReg is true, otherwise a copy from the register.

Definition at line 3996 of file AMDGPUISelLowering.cpp.

References llvm::MachineRegisterInfo::addLiveIn(), llvm::MachineRegisterInfo::createVirtualRegister(), llvm::SelectionDAG::getCopyFromReg(), llvm::SelectionDAG::getEntryNode(), llvm::MachineRegisterInfo::getLiveInVirtReg(), llvm::SelectionDAG::getMachineFunction(), llvm::MachineFunction::getRegInfo(), llvm::SelectionDAG::getRegister(), llvm::MachineRegisterInfo::isLiveIn(), and MRI.

Referenced by CreateLiveInRegister(), CreateLiveInRegisterRaw(), findUser(), isFsqrtCheap(), llvm::SITargetLowering::isTypeDesirableForOp(), loadInputValue(), llvm::SITargetLowering::LowerCall(), and llvm::SITargetLowering::LowerReturn().

◆ CreateLiveInRegister() [2/2]

SDValue llvm::AMDGPUTargetLowering::CreateLiveInRegister	(	SelectionDAG &	DAG,
		const TargetRegisterClass *	RC,
		unsigned	Reg,
		EVT	VT
	)		const

inline

Definition at line 265 of file AMDGPUISelLowering.h.

References CreateLiveInRegister(), and llvm::SelectionDAG::getEntryNode().

◆ CreateLiveInRegisterRaw()

SDValue llvm::AMDGPUTargetLowering::CreateLiveInRegisterRaw	(	SelectionDAG &	DAG,
		const TargetRegisterClass *	RC,
		unsigned	Reg,
		EVT	VT
	)		const

inline

Definition at line 272 of file AMDGPUISelLowering.h.

References Arg, CreateLiveInRegister(), llvm::SelectionDAG::getEntryNode(), loadInputValue(), loadStackInputValue(), and storeStackInputValue().

Referenced by llvm::R600TargetLowering::LowerOperation().

◆ getEquivalentMemType()

EVT AMDGPUTargetLowering::getEquivalentMemType	(	LLVMContext &	Context,
		EVT	VT
	)

staticprotected

Definition at line 121 of file AMDGPUISelLowering.cpp.

References assert(), llvm::EVT::getIntegerVT(), llvm::EVT::getStoreSizeInBits(), llvm::EVT::getVectorVT(), and llvm::MVT::i32.

Referenced by isClampZeroToOne(), performLoadCombine(), performStoreCombine(), and llvm::SITargetLowering::ReplaceNodeResults().

◆ getFenceOperandTy()

MVT llvm::AMDGPUTargetLowering::getFenceOperandTy ( const DataLayout & DL ) const

inlineoverridevirtual

Return the type for operands of fence.

TODO: Let fence operands be of i32 type and remove this.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 307 of file AMDGPUISelLowering.h.

References llvm::MVT::i32, and shouldExpandAtomicRMWInIR().

◆ getHiHalf64()

SDValue AMDGPUTargetLowering::getHiHalf64	(	SDValue	Op,
		SelectionDAG &	DAG
	)		const

protected

Definition at line 1367 of file AMDGPUISelLowering.cpp.

References llvm::ISD::BITCAST, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::MVT::i32, and llvm::MVT::v2i32.

Referenced by performSraCombine().

◆ getImplicitParameterOffset()

uint32_t AMDGPUTargetLowering::getImplicitParameterOffset	(	const MachineFunction &	MF,
		const ImplicitParameter	Param
	)		const

Helper function that returns the byte offset of the given type of implicit parameter.

Definition at line 4059 of file AMDGPUISelLowering.cpp.

References llvm::alignTo(), llvm::AMDGPUSubtarget::get(), llvm::AMDGPUMachineFunction::getExplicitKernArgSize(), llvm::AMDGPUSubtarget::getExplicitKernelArgOffset(), llvm::MachineFunction::getFunction(), llvm::MachineFunction::getInfo(), llvm::TargetLoweringBase::getTargetMachine(), GRID_DIM, GRID_OFFSET, llvm_unreachable, and llvm::ARM_MB::ST.

Referenced by llvm::SITargetLowering::isTypeDesirableForOp(), and llvm::R600TargetLowering::LowerOperation().

◆ getLoHalf64()

SDValue AMDGPUTargetLowering::getLoHalf64	(	SDValue	Op,
		SelectionDAG &	DAG
	)		const

protected

Definition at line 1359 of file AMDGPUISelLowering.cpp.

References llvm::ISD::BITCAST, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::MVT::i32, and llvm::MVT::v2i32.

◆ getRecipEstimate()

SDValue AMDGPUTargetLowering::getRecipEstimate	(	SDValue	Operand,
		SelectionDAG &	DAG,
		int	Enabled,
		int &	RefinementSteps
	)		const

overridevirtual

Return a reciprocal estimate value for the input operand.

Enabled is a ReciprocalEstimate enum with value either 'Unspecified' or 'Enabled' as set by a potential default override attribute. If RefinementSteps is 'Unspecified', the number of Newton-Raphson refinement iterations required to generate a sufficient (though not necessarily IEEE-754 compliant) estimate is returned in that parameter. A target may choose to implement its own refinement within this function. If that's true, then return '0' as the number of RefinementSteps to avoid any further refinement of the estimate. An empty SDValue return means no estimate sequence can be created.

Reimplemented from llvm::TargetLowering.

Definition at line 4244 of file AMDGPUISelLowering.cpp.

References llvm::MVT::f32, llvm::SelectionDAG::getNode(), llvm::SDValue::getValueType(), and llvm::AMDGPUISD::RCP.

Referenced by isFsqrtCheap().

◆ getSqrtEstimate()

SDValue AMDGPUTargetLowering::getSqrtEstimate	(	SDValue	Operand,
		SelectionDAG &	DAG,
		int	Enabled,
		int &	RefinementSteps,
		bool &	UseOneConstNR,
		bool	Reciprocal
	)		const

overridevirtual

Hooks for building estimates in place of slower divisions and square roots.

Return either a square root or its reciprocal estimate value for the input operand. Enabled is a ReciprocalEstimate enum with value either 'Unspecified' or 'Enabled' as set by a potential default override attribute. If RefinementSteps is 'Unspecified', the number of Newton-Raphson refinement iterations required to generate a sufficient (though not necessarily IEEE-754 compliant) estimate is returned in that parameter. The boolean UseOneConstNR output is used to select a Newton-Raphson algorithm implementation that uses either one or two constants. The boolean Reciprocal is used to select whether the estimate is for the square root of the input operand or the reciprocal of its square root. A target may choose to implement its own refinement within this function. If that's true, then return '0' as the number of RefinementSteps to avoid any further refinement of the estimate. An empty SDValue return means no estimate sequence can be created.

Reimplemented from llvm::TargetLowering.

Definition at line 4226 of file AMDGPUISelLowering.cpp.

References llvm::MVT::f32, llvm::SelectionDAG::getNode(), llvm::SDValue::getValueType(), and llvm::AMDGPUISD::RSQ.

Referenced by isFsqrtCheap().

◆ getTargetNodeName()

const char * AMDGPUTargetLowering::getTargetNodeName ( unsigned Opcode ) const

overridevirtual

This method returns the name of a target specific DAG node.

Reimplemented from llvm::TargetLowering.

Definition at line 4079 of file AMDGPUISelLowering.cpp.

Referenced by stripBitcast().

◆ getVectorIdxTy()

MVT AMDGPUTargetLowering::getVectorIdxTy ( const DataLayout & DL ) const

overridevirtual

Returns the type to be used for the index operand of: ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT, ISD::INSERT_SUBVECTOR, and ISD::EXTRACT_SUBVECTOR.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 633 of file AMDGPUISelLowering.cpp.

References llvm::MVT::i32.

Referenced by llvm::R600TargetLowering::ReplaceNodeResults(), and stripBitcast().

◆ isCheapToSpeculateCtlz()

bool AMDGPUTargetLowering::isCheapToSpeculateCtlz ( ) const

overridevirtual

Return true if it is cheap to speculate a call to intrinsic ctlz.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 716 of file AMDGPUISelLowering.cpp.

Referenced by stripBitcast().

◆ isCheapToSpeculateCttz()

bool AMDGPUTargetLowering::isCheapToSpeculateCttz ( ) const

overridevirtual

Return true if it is cheap to speculate a call to intrinsic cttz.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 712 of file AMDGPUISelLowering.cpp.

Referenced by stripBitcast().

◆ isConstantCostlierToNegate()

bool AMDGPUTargetLowering::isConstantCostlierToNegate ( SDValue N ) const

protected

Definition at line 3522 of file AMDGPUISelLowering.cpp.

References C, llvm::AMDGPUSubtarget::hasInv2PiInlineImm(), llvm::isConstOrConstSplatFP(), and isInv2Pi().

Referenced by performFNegCombine().

◆ isFAbsFree()

bool AMDGPUTargetLowering::isFAbsFree ( EVT VT ) const

overridevirtual

Return true if an fabs operation is free to the point where it is never worthwhile to replace it with a bitwise operation.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 755 of file AMDGPUISelLowering.cpp.

References assert(), llvm::MVT::f16, llvm::MVT::f32, llvm::MVT::f64, llvm::AMDGPUSubtarget::has16BitInsts(), and llvm::EVT::isFloatingPoint().

Referenced by stripBitcast().

◆ isFNegFree()

bool AMDGPUTargetLowering::isFNegFree ( EVT VT ) const

overridevirtual

Return true if an fneg operation is free to the point where it is never worthwhile to replace it with a bitwise operation.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 763 of file AMDGPUISelLowering.cpp.

References assert(), llvm::MVT::f16, llvm::MVT::f32, llvm::MVT::f64, llvm::AMDGPUSubtarget::has16BitInsts(), llvm::AMDGPUSubtarget::hasVOP3PInsts(), llvm::EVT::isFloatingPoint(), and llvm::MVT::v2f16.

Referenced by stripBitcast().

◆ isFPImmLegal()

bool AMDGPUTargetLowering::isFPImmLegal	(	const APFloat &	,
		EVT
	)		const

overridevirtual

Returns true if the target can instruction select the specified FP immediate natively.

If false, the legalizer will materialize the FP immediate as a load from a constant pool.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 643 of file AMDGPUISelLowering.cpp.

References llvm::MVT::f16, llvm::MVT::f32, llvm::MVT::f64, llvm::EVT::getScalarType(), and llvm::AMDGPUSubtarget::has16BitInsts().

Referenced by stripBitcast().

◆ isFsqrtCheap()

bool llvm::AMDGPUTargetLowering::isFsqrtCheap	(	SDValue	X,
		SelectionDAG &	DAG
	)		const

inlineoverridevirtual

Return true if SQRT(X) shouldn't be replaced with X*RSQRT(X).

Reimplemented from llvm::TargetLoweringBase.

Definition at line 225 of file AMDGPUISelLowering.h.

References computeKnownBitsForTargetNode(), ComputeNumSignBitsForTargetNode(), CreateLiveInRegister(), llvm::Depth, llvm::TargetLoweringBase::Enabled, getRecipEstimate(), getSqrtEstimate(), isKnownNeverNaNForTargetNode(), PostISelFolding(), and Reg.

◆ isKnownNeverNaNForTargetNode()

bool AMDGPUTargetLowering::isKnownNeverNaNForTargetNode	(	SDValue	Op,
		const SelectionDAG &	DAG,
		bool	SNaN = `false`,
		unsigned	Depth = `0`
	)		const

overridevirtual

If SNaN is false,.

Returns: true if Op is known to never be any NaN. If sNaN is true, returns if Op is known to never be a signaling NaN.

Reimplemented from llvm::TargetLowering.

Reimplemented in llvm::SITargetLowering.

Definition at line 4424 of file AMDGPUISelLowering.cpp.

References llvm::Intrinsic::amdgcn_cubeid, llvm::Intrinsic::amdgcn_cvt_pkrtz, llvm::Intrinsic::amdgcn_fdot2, llvm::Intrinsic::amdgcn_frexp_mant, llvm::AMDGPUISD::COS_HW, llvm::AMDGPUISD::CVT_F32_UBYTE0, llvm::AMDGPUISD::CVT_F32_UBYTE1, llvm::AMDGPUISD::CVT_F32_UBYTE2, llvm::AMDGPUISD::CVT_F32_UBYTE3, llvm::AMDGPUISD::CVT_PKRTZ_F16_F32, llvm::AMDGPUISD::DIV_FIXUP, llvm::AMDGPUISD::DIV_FMAS, llvm::AMDGPUISD::DIV_SCALE, llvm::AMDGPUISD::FMAD_FTZ, llvm::AMDGPUISD::FMAX3, llvm::AMDGPUISD::FMAX_LEGACY, llvm::AMDGPUISD::FMED3, llvm::AMDGPUISD::FMIN3, llvm::AMDGPUISD::FMIN_LEGACY, llvm::AMDGPUISD::FMUL_LEGACY, llvm::AMDGPUISD::FRACT, llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::ISD::INTRINSIC_WO_CHAIN, llvm::SelectionDAG::isKnownNeverNaN(), llvm::AMDGPUISD::LDEXP, llvm::AMDGPUISD::RCP, llvm::AMDGPUISD::RCP_LEGACY, llvm::AMDGPUISD::RSQ, llvm::AMDGPUISD::RSQ_CLAMP, llvm::AMDGPUISD::RSQ_LEGACY, llvm::AMDGPUISD::SIN_HW, and llvm::AMDGPUISD::TRIG_PREOP.

Referenced by isFsqrtCheap(), and llvm::SITargetLowering::isKnownNeverNaNForTargetNode().

◆ isLoadBitCastBeneficial()

bool AMDGPUTargetLowering::isLoadBitCastBeneficial	(	EVT	LoadVT,
		EVT	BitcastVT
	)		const

finalvirtual

Return true if the following transform is beneficial: fold (conv (load x)) -> (load (conv*)x) On architectures that don't natively support some vector loads efficiently, casting the load to a smaller vector of larger types and loading is more efficient, however, this can be undone by optimizations in dag combiner.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 693 of file AMDGPUISelLowering.cpp.

References assert(), llvm::EVT::getScalarSizeInBits(), llvm::EVT::getScalarType(), llvm::EVT::getSizeInBits(), and llvm::MVT::i32.

Referenced by stripBitcast().

◆ isNarrowingProfitable()

bool AMDGPUTargetLowering::isNarrowingProfitable	(	EVT	,
		EVT
	)		const

overridevirtual

Return true if it's profitable to narrow operations of type VT1 to VT2.

e.g. on x86, it's profitable to narrow from i32 to i8 but not from i32 to i16.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 835 of file AMDGPUISelLowering.cpp.

References llvm::EVT::getSizeInBits().

Referenced by stripBitcast().

◆ isSDNodeAlwaysUniform()

bool AMDGPUTargetLowering::isSDNodeAlwaysUniform ( const SDNode * N ) const

overridevirtual

Reimplemented from llvm::TargetLowering.

Definition at line 720 of file AMDGPUISelLowering.cpp.

References llvm::Intrinsic::amdgcn_readfirstlane, llvm::Intrinsic::amdgcn_readlane, AMDGPUAS::CONSTANT_ADDRESS_32BIT, llvm::dyn_cast(), llvm::ISD::EntryToken, llvm::MachineMemOperand::getAddrSpace(), llvm::MemSDNode::getMemOperand(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::ISD::INTRINSIC_WO_CHAIN, llvm::ISD::LOAD, N, and llvm::ISD::TokenFactor.

Referenced by stripBitcast().

◆ isSelectSupported()

bool AMDGPUTargetLowering::isSelectSupported ( SelectSupportKind SelType ) const

overridevirtual

Reimplemented from llvm::TargetLoweringBase.

Definition at line 637 of file AMDGPUISelLowering.cpp.

Referenced by stripBitcast().

◆ isTruncateFree() [1/2]

bool AMDGPUTargetLowering::isTruncateFree	(	EVT	Src,
		EVT	Dest
	)		const

overridevirtual

Reimplemented from llvm::TargetLoweringBase.

Definition at line 788 of file AMDGPUISelLowering.cpp.

References llvm::EVT::getSizeInBits().

Referenced by stripBitcast().

◆ isTruncateFree() [2/2]

bool AMDGPUTargetLowering::isTruncateFree	(	Type *	FromTy,
		Type *	ToTy
	)		const

overridevirtual

Return true if it's free to truncate a value of type FromTy to type ToTy.

e.g. On x86 it's free to truncate a i32 value in register EAX to i16 by referencing its sub-register AX. Targets must return false when FromTy <= ToTy.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 797 of file AMDGPUISelLowering.cpp.

References llvm::Type::getScalarSizeInBits(), and llvm::AMDGPUSubtarget::has16BitInsts().

◆ isZExtFree() [1/3]

bool AMDGPUTargetLowering::isZExtFree	(	Type *	FromTy,
		Type *	ToTy
	)		const

overridevirtual

Return true if any actual instruction that defines a value of type FromTy implicitly zero-extends the value to ToTy in the result register.

The function should return true when it is likely that the truncate can be freely folded with an instruction defining a value of FromTy. If the defining instruction is unknown (because you're looking at a function argument, PHI, etc.) then the target may require an explicit truncate, which is not necessarily free, but this function does not deal with those cases. Targets must return false when FromTy >= ToTy.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 809 of file AMDGPUISelLowering.cpp.

References llvm::Type::getScalarSizeInBits(), and llvm::AMDGPUSubtarget::has16BitInsts().

Referenced by isZExtFree(), and stripBitcast().

◆ isZExtFree() [2/3]

bool AMDGPUTargetLowering::isZExtFree	(	EVT	Src,
		EVT	Dest
	)		const

overridevirtual

Reimplemented from llvm::TargetLoweringBase.

Definition at line 819 of file AMDGPUISelLowering.cpp.

References llvm::MVT::i16, llvm::MVT::i32, and llvm::MVT::i64.

◆ isZExtFree() [3/3]

bool AMDGPUTargetLowering::isZExtFree	(	SDValue	Val,
		EVT	VT2
	)		const

overridevirtual

Return true if zero-extending the specific node Val to type VT2 is free (either because it's implicitly zero-extended such as ARM ldrb / ldrh or because it's folded such as X86 zero-extending loads).

Reimplemented from llvm::TargetLoweringBase.

Definition at line 831 of file AMDGPUISelLowering.cpp.

References llvm::SDValue::getValueType(), and isZExtFree().

◆ loadInputValue()

SDValue AMDGPUTargetLowering::loadInputValue	(	SelectionDAG &	DAG,
		const TargetRegisterClass *	RC,
		EVT	VT,
		const SDLoc &	SL,
		const ArgDescriptor &	Arg
	)		const

Definition at line 4048 of file AMDGPUISelLowering.cpp.

References assert(), CreateLiveInRegister(), llvm::ArgDescriptor::getRegister(), llvm::ArgDescriptor::getStackOffset(), llvm::ArgDescriptor::isRegister(), and loadStackInputValue().

Referenced by CreateLiveInRegisterRaw(), parseTexFail(), and llvm::SITargetLowering::passSpecialInputs().

◆ loadStackInputValue()

SDValue AMDGPUTargetLowering::loadStackInputValue	(	SelectionDAG &	DAG,
		EVT	VT,
		const SDLoc &	SL,
		int64_t	Offset
	)		const

Similar to CreateLiveInRegister, except value maybe loaded from a stack slot rather than passed in a register.

Definition at line 4018 of file AMDGPUISelLowering.cpp.

References llvm::MachineFrameInfo::CreateFixedObject(), llvm::SelectionDAG::getEntryNode(), llvm::SelectionDAG::getFrameIndex(), llvm::MachineFunction::getFrameInfo(), llvm::SelectionDAG::getLoad(), llvm::SelectionDAG::getMachineFunction(), llvm::MachinePointerInfo::getStack(), llvm::EVT::getStoreSize(), llvm::MVT::i32, llvm::MachineMemOperand::MODereferenceable, and llvm::MachineMemOperand::MOInvariant.

Referenced by CreateLiveInRegisterRaw(), and loadInputValue().

◆ LowerCall()

SDValue AMDGPUTargetLowering::LowerCall	(	CallLoweringInfo &	,
		SmallVectorImpl< SDValue > &
	)		const

overridevirtual

This hook must be implemented to lower calls into the specified DAG.

The outgoing arguments to the call are described by the Outs array, and the values to be returned by the call are described by the Ins array. The implementation should fill in the InVals array with legal-type return values from the call, and return the resulting token chain value.

Reimplemented from llvm::TargetLowering.

Reimplemented in llvm::SITargetLowering.

Definition at line 1121 of file AMDGPUISelLowering.cpp.

References lowerUnhandledCall().

Referenced by stripBitcast().

◆ LowerCONCAT_VECTORS()

SDValue AMDGPUTargetLowering::LowerCONCAT_VECTORS	(	SDValue	Op,
		SelectionDAG &	DAG
	)		const

protected

Definition at line 1238 of file AMDGPUISelLowering.cpp.

References llvm::AMDGPU::HSAMD::Kernel::Key::Args, llvm::ISD::BITCAST, llvm::SelectionDAG::ExtractVectorElements(), llvm::SelectionDAG::getBuildVector(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOperand(), llvm::SDValue::getValueType(), llvm::MipsISD::Hi, llvm::MVT::i32, llvm::MipsISD::Lo, llvm::SDNode::ops(), llvm::MVT::v2i32, llvm::MVT::v4f16, and llvm::MVT::v4i16.

Referenced by LowerOperation().

◆ LowerCTLZ_CTTZ()

SDValue AMDGPUTargetLowering::LowerCTLZ_CTTZ	(	SDValue	Op,
		SelectionDAG &	DAG
	)		const

protected

◆ LowerDIVREM24()

SDValue AMDGPUTargetLowering::LowerDIVREM24	(	SDValue	Op,
		SelectionDAG &	DAG,
		bool	sign
	)		const

protected

Definition at line 1466 of file AMDGPUISelLowering.cpp.

Referenced by LowerSDIVREM(), and LowerUDIVREM().

◆ LowerDYNAMIC_STACKALLOC()

SDValue AMDGPUTargetLowering::LowerDYNAMIC_STACKALLOC	(	SDValue	Op,
		SelectionDAG &	DAG
	)		const

Definition at line 1126 of file AMDGPUISelLowering.cpp.

References llvm::LLVMContext::diagnose(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), getDebugLoc(), llvm::MachineFunction::getFunction(), llvm::SelectionDAG::getMachineFunction(), llvm::SelectionDAG::getMergeValues(), llvm::SDValue::getOperand(), and llvm::SDValue::getValueType().

Referenced by LowerOperation(), and stripBitcast().

◆ LowerEXTRACT_SUBVECTOR()

SDValue AMDGPUTargetLowering::LowerEXTRACT_SUBVECTOR	(	SDValue	Op,
		SelectionDAG &	DAG
	)		const

protected

Definition at line 1258 of file AMDGPUISelLowering.cpp.

References llvm::AMDGPU::HSAMD::Kernel::Key::Args.

Referenced by LowerOperation().

◆ LowerFCEIL()

SDValue AMDGPUTargetLowering::LowerFCEIL	(	SDValue	Op,
		SelectionDAG &	DAG
	)		const

protected

Definition at line 1973 of file AMDGPUISelLowering.cpp.

References llvm::MCID::Add, llvm::ISD::AND, llvm::MVT::f64, llvm::ISD::FADD, llvm::ISD::FTRUNC, llvm::SelectionDAG::getConstantFP(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getDataLayout(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getSetCC(), llvm::TargetLoweringBase::getSetCCResultType(), llvm::ISD::SELECT, llvm::ISD::SETOGT, and llvm::ISD::SETONE.

Referenced by LowerOperation().

◆ lowerFEXP()

SDValue AMDGPUTargetLowering::lowerFEXP	(	SDValue	Op,
		SelectionDAG &	DAG
	)		const

protected

Definition at line 2254 of file AMDGPUISelLowering.cpp.

References llvm::ISD::FEXP2, llvm::ISD::FMUL, llvm::SDNode::getFlags(), getLog2EVal(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOperand(), and llvm::SDValue::getValueType().

Referenced by LowerOperation().

◆ LowerFFLOOR()

SDValue AMDGPUTargetLowering::LowerFFLOOR	(	SDValue	Op,
		SelectionDAG &	DAG
	)		const

protected

Definition at line 2199 of file AMDGPUISelLowering.cpp.

References llvm::MCID::Add, llvm::ISD::AND, llvm::MVT::f64, llvm::ISD::FADD, llvm::ISD::FTRUNC, llvm::SelectionDAG::getConstantFP(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getDataLayout(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getSetCC(), llvm::TargetLoweringBase::getSetCCResultType(), llvm::ISD::SELECT, llvm::ISD::SETOLT, and llvm::ISD::SETONE.

Referenced by LowerOperation().

◆ LowerFLOG()

SDValue AMDGPUTargetLowering::LowerFLOG	(	SDValue	Op,
		SelectionDAG &	DAG,
		double	Log2BaseInverted
	)		const

protected

Definition at line 2224 of file AMDGPUISelLowering.cpp.

References llvm::ISD::FLOG2, llvm::ISD::FMUL, llvm::SelectionDAG::getConstantFP(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOperand(), and llvm::SDValue::getValueType().

Referenced by LowerOperation().

◆ LowerFNEARBYINT()

SDValue AMDGPUTargetLowering::LowerFNEARBYINT	(	SDValue	Op,
		SelectionDAG &	DAG
	)		const

protected

Definition at line 2089 of file AMDGPUISelLowering.cpp.

References llvm::ISD::FRINT, llvm::SelectionDAG::getNode(), llvm::SDValue::getOperand(), and llvm::SDValue::getValueType().

Referenced by LowerOperation().

◆ LowerFP64_TO_INT()

SDValue AMDGPUTargetLowering::LowerFP64_TO_INT	(	SDValue	Op,
		SelectionDAG &	DAG,
		bool	Signed
	)		const

protected

◆ LowerFP_TO_FP16()

SDValue AMDGPUTargetLowering::LowerFP_TO_FP16	(	SDValue	Op,
		SelectionDAG &	DAG
	)		const

protected

◆ LowerFP_TO_SINT()

SDValue AMDGPUTargetLowering::LowerFP_TO_SINT	(	SDValue	Op,
		SelectionDAG &	DAG
	)		const

protected

Definition at line 2636 of file AMDGPUISelLowering.cpp.

References llvm::MVT::f16, llvm::MVT::f32, llvm::MVT::f64, llvm::ISD::FP_EXTEND, llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getValueType(), llvm::AMDGPUSubtarget::has16BitInsts(), llvm::MVT::i64, and LowerFP64_TO_INT().

Referenced by LowerOperation().

◆ LowerFP_TO_UINT()

SDValue AMDGPUTargetLowering::LowerFP_TO_UINT	(	SDValue	Op,
		SelectionDAG &	DAG
	)		const

protected

Definition at line 2659 of file AMDGPUISelLowering.cpp.

References llvm::MVT::f16, llvm::MVT::f32, llvm::MVT::f64, llvm::ISD::FP_EXTEND, llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getValueType(), llvm::AMDGPUSubtarget::has16BitInsts(), llvm::MVT::i64, and LowerFP64_TO_INT().

Referenced by LowerOperation().

◆ LowerFREM()

SDValue AMDGPUTargetLowering::LowerFREM	(	SDValue	Op,
		SelectionDAG &	DAG
	)		const

protected

Split a vector store into multiple scalar stores.

Returns: The resulting chain.

Definition at line 1958 of file AMDGPUISelLowering.cpp.

References llvm::ISD::FDIV, llvm::ISD::FMUL, llvm::ISD::FSUB, llvm::ISD::FTRUNC, llvm::SelectionDAG::getNode(), llvm::SDValue::getOperand(), llvm::SDValue::getValueType(), X, and Y.

Referenced by LowerOperation().

◆ LowerFRINT()

SDValue AMDGPUTargetLowering::LowerFRINT	(	SDValue	Op,
		SelectionDAG &	DAG
	)		const

protected

◆ LowerFROUND()

SDValue AMDGPUTargetLowering::LowerFROUND	(	SDValue	Op,
		SelectionDAG &	DAG
	)		const

protected

Definition at line 2187 of file AMDGPUISelLowering.cpp.

References llvm::MVT::f16, llvm::MVT::f32, llvm::MVT::f64, llvm::SDValue::getValueType(), llvm_unreachable, LowerFROUND32_16(), and LowerFROUND64().

Referenced by LowerOperation().

◆ LowerFROUND32_16()

SDValue AMDGPUTargetLowering::LowerFROUND32_16	(	SDValue	Op,
		SelectionDAG &	DAG
	)		const

protected

Definition at line 2101 of file AMDGPUISelLowering.cpp.

References llvm::ISD::FABS, llvm::ISD::FADD, llvm::ISD::FCOPYSIGN, llvm::ISD::FSUB, llvm::ISD::FTRUNC, llvm::SelectionDAG::getConstantFP(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getDataLayout(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getSetCC(), llvm::TargetLoweringBase::getSetCCResultType(), llvm::SDValue::getValueType(), llvm::ISD::SELECT, llvm::ISD::SETOGE, and X.

Referenced by LowerFROUND().

◆ LowerFROUND64()

SDValue AMDGPUTargetLowering::LowerFROUND64	(	SDValue	Op,
		SelectionDAG &	DAG
	)		const

protected

◆ LowerFTRUNC()

SDValue AMDGPUTargetLowering::LowerFTRUNC	(	SDValue	Op,
		SelectionDAG &	DAG
	)		const

protected

◆ LowerGlobalAddress()

SDValue AMDGPUTargetLowering::LowerGlobalAddress	(	AMDGPUMachineFunction *	MFI,
		SDValue	Op,
		SelectionDAG &	DAG
	)		const

protectedvirtual

◆ LowerINT_TO_FP32()

SDValue AMDGPUTargetLowering::LowerINT_TO_FP32	(	SDValue	Op,
		SelectionDAG &	DAG,
		bool	Signed
	)		const

protected

◆ LowerINT_TO_FP64()

SDValue AMDGPUTargetLowering::LowerINT_TO_FP64	(	SDValue	Op,
		SelectionDAG &	DAG,
		bool	Signed
	)		const

protected

Definition at line 2431 of file AMDGPUISelLowering.cpp.

References llvm::ISD::BITCAST, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::MVT::f64, llvm::ISD::FADD, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOperand(), llvm::MipsISD::Hi, llvm::MVT::i32, llvm::AMDGPUISD::LDEXP, llvm::MipsISD::Lo, llvm::ISD::SINT_TO_FP, llvm::ISD::UINT_TO_FP, and llvm::MVT::v2i32.

Referenced by LowerSINT_TO_FP(), and LowerUINT_TO_FP().

◆ LowerOperation()

SDValue AMDGPUTargetLowering::LowerOperation	(	SDValue	Op,
		SelectionDAG &	DAG
	)		const

overridevirtual

This callback is invoked for operations that are unsupported by the target, which are registered to use 'custom' lowering, and whose defined values are all legal.

If the target has no operations that require custom lowering, it need not implement this. The default implementation of this aborts.

Reimplemented from llvm::TargetLowering.

Reimplemented in llvm::SITargetLowering, and llvm::R600TargetLowering.

Definition at line 1137 of file AMDGPUISelLowering.cpp.

References AMDGPU_LN10_F, AMDGPU_LN2_F, AMDGPU_LOG2E_F, llvm::ISD::CONCAT_VECTORS, llvm::ISD::CTLZ, llvm::ISD::CTLZ_ZERO_UNDEF, llvm::ISD::CTTZ, llvm::ISD::CTTZ_ZERO_UNDEF, llvm::ISD::DYNAMIC_STACKALLOC, llvm::errs(), llvm::ISD::EXTRACT_SUBVECTOR, llvm::ISD::FCEIL, llvm::ISD::FEXP, llvm::ISD::FFLOOR, llvm::ISD::FLOG, llvm::ISD::FLOG10, llvm::ISD::FNEARBYINT, llvm::ISD::FP_TO_FP16, llvm::ISD::FP_TO_SINT, llvm::ISD::FP_TO_UINT, llvm::ISD::FREM, llvm::ISD::FRINT, llvm::ISD::FROUND, llvm::ISD::FTRUNC, llvm::SDValue::getOpcode(), llvm_unreachable, LowerCONCAT_VECTORS(), LowerCTLZ_CTTZ(), LowerDYNAMIC_STACKALLOC(), LowerEXTRACT_SUBVECTOR(), LowerFCEIL(), lowerFEXP(), LowerFFLOOR(), LowerFLOG(), LowerFNEARBYINT(), LowerFP_TO_FP16(), LowerFP_TO_SINT(), LowerFP_TO_UINT(), LowerFREM(), LowerFRINT(), LowerFROUND(), LowerFTRUNC(), LowerSDIVREM(), LowerSIGN_EXTEND_INREG(), LowerSINT_TO_FP(), LowerUDIVREM(), LowerUINT_TO_FP(), llvm::SDNode::print(), llvm::ISD::SDIVREM, llvm::ISD::SIGN_EXTEND_INREG, llvm::ISD::SINT_TO_FP, llvm::ISD::UDIVREM, and llvm::ISD::UINT_TO_FP.

Referenced by llvm::R600TargetLowering::LowerOperation(), llvm::SITargetLowering::LowerOperation(), and stripBitcast().

◆ LowerReturn()

SDValue AMDGPUTargetLowering::LowerReturn	(	SDValue	,
		CallingConv::ID	,
		bool	,
		const SmallVectorImpl< ISD::OutputArg > &	,
		const SmallVectorImpl< SDValue > &	,
		const SDLoc &	,
		SelectionDAG &
	)		const

overridevirtual

This hook must be implemented to lower outgoing return values, described by the Outs array, into the specified DAG.

The implementation should return the resulting token chain value.

Reimplemented from llvm::TargetLowering.

Reimplemented in llvm::SITargetLowering.

Definition at line 1031 of file AMDGPUISelLowering.cpp.

References llvm::AMDGPUISD::ENDPGM, llvm::SelectionDAG::getNode(), and llvm::MVT::Other.

Referenced by llvm::SITargetLowering::LowerReturn(), and stripBitcast().

◆ LowerSDIVREM()

SDValue AMDGPUTargetLowering::LowerSDIVREM	(	SDValue	Op,
		SelectionDAG &	DAG
	)		const

protected

◆ LowerSIGN_EXTEND_INREG()

SDValue AMDGPUTargetLowering::LowerSIGN_EXTEND_INREG	(	SDValue	Op,
		SelectionDAG &	DAG
	)		const

protected

Definition at line 2682 of file AMDGPUISelLowering.cpp.

References llvm::AMDGPU::HSAMD::Kernel::Key::Args, assert(), llvm::SelectionDAG::ExtractVectorElements(), llvm::SelectionDAG::getBuildVector(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOperand(), llvm::EVT::getScalarType(), llvm::MVT::getScalarType(), llvm::SDValue::getSimpleValueType(), llvm::SelectionDAG::getValueType(), llvm::MVT::getVectorNumElements(), I, llvm::MVT::isVector(), and llvm::ISD::SIGN_EXTEND_INREG.

Referenced by LowerOperation().

◆ LowerSINT_TO_FP()

SDValue AMDGPUTargetLowering::LowerSINT_TO_FP	(	SDValue	Op,
		SelectionDAG &	DAG
	)		const

protected

Definition at line 2481 of file AMDGPUISelLowering.cpp.

References assert(), llvm::MVT::f16, llvm::MVT::f32, llvm::MVT::f64, llvm::ISD::FP_ROUND, llvm::SelectionDAG::getIntPtrConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getValueType(), llvm::AMDGPUSubtarget::has16BitInsts(), llvm::MVT::i64, LowerINT_TO_FP32(), and LowerINT_TO_FP64().

Referenced by LowerOperation().

◆ LowerSTORE()

SDValue llvm::AMDGPUTargetLowering::LowerSTORE	(	SDValue	Op,
		SelectionDAG &	DAG
	)		const

protected

◆ LowerUDIVREM()

SDValue AMDGPUTargetLowering::LowerUDIVREM	(	SDValue	Op,
		SelectionDAG &	DAG
	)		const

protected

◆ LowerUDIVREM64()

void AMDGPUTargetLowering::LowerUDIVREM64	(	SDValue	Op,
		SelectionDAG &	DAG,
		SmallVectorImpl< SDValue > &	Results
	)		const

protected

Definition at line 1572 of file AMDGPUISelLowering.cpp.

Referenced by LowerUDIVREM(), and llvm::R600TargetLowering::ReplaceNodeResults().

◆ LowerUINT_TO_FP()

SDValue AMDGPUTargetLowering::LowerUINT_TO_FP	(	SDValue	Op,
		SelectionDAG &	DAG
	)		const

protected

Definition at line 2454 of file AMDGPUISelLowering.cpp.

References assert(), llvm::MVT::f16, llvm::MVT::f32, llvm::MVT::f64, llvm::ISD::FP_ROUND, llvm::SelectionDAG::getIntPtrConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getValueType(), llvm::AMDGPUSubtarget::has16BitInsts(), llvm::MVT::i64, LowerINT_TO_FP32(), and LowerINT_TO_FP64().

Referenced by LowerOperation().

◆ lowerUnhandledCall()

SDValue AMDGPUTargetLowering::lowerUnhandledCall	(	CallLoweringInfo &	CLI,
		SmallVectorImpl< SDValue > &	InVals,
		StringRef	Reason
	)		const

◆ mayIgnoreSignedZero()

bool llvm::AMDGPUTargetLowering::mayIgnoreSignedZero ( SDValue Op ) const

inline

Definition at line 134 of file AMDGPUISelLowering.h.

References llvm::SDNode::getFlags(), llvm::SDValue::getNode(), llvm::TargetLoweringBase::getTargetMachine(), and llvm::SDNodeFlags::hasNoSignedZeros().

Referenced by performFNegCombine().

◆ mergeStoresAfterLegalization()

bool llvm::AMDGPUTargetLowering::mergeStoresAfterLegalization ( ) const

inlineoverridevirtual

Allow store merging after legalization in addition to before legalization.

This may catch stores that do not exist earlier (eg, stores created from intrinsics).

Reimplemented from llvm::TargetLoweringBase.

Definition at line 223 of file AMDGPUISelLowering.h.

◆ numBitsSigned()

unsigned AMDGPUTargetLowering::numBitsSigned	(	SDValue	Op,
		SelectionDAG &	DAG
	)

static

Definition at line 136 of file AMDGPUISelLowering.cpp.

References llvm::SelectionDAG::ComputeNumSignBits(), llvm::EVT::getSizeInBits(), and llvm::SDValue::getValueType().

Referenced by getMad64_32(), and isI24().

◆ numBitsUnsigned()

unsigned AMDGPUTargetLowering::numBitsUnsigned	(	SDValue	Op,
		SelectionDAG &	DAG
	)

static

Definition at line 130 of file AMDGPUISelLowering.cpp.

References llvm::SelectionDAG::computeKnownBits(), llvm::KnownBits::countMinLeadingZeros(), llvm::EVT::getSizeInBits(), and llvm::SDValue::getValueType().

Referenced by getMad64_32(), and isU24().

◆ performAssertSZExtCombine()

SDValue AMDGPUTargetLowering::performAssertSZExtCombine	(	SDNode *	N,
		DAGCombinerInfo &	DCI
	)		const

protected

Definition at line 2900 of file AMDGPUISelLowering.cpp.

References llvm::EVT::bitsGE(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), and llvm::ISD::TRUNCATE.

Referenced by PerformDAGCombine().

◆ performCtlz_CttzCombine()

SDValue AMDGPUTargetLowering::performCtlz_CttzCombine	(	const SDLoc &	SL,
		SDValue	Cond,
		SDValue	LHS,
		SDValue	RHS,
		DAGCombinerInfo &	DCI
	)		const

protected

Definition at line 3345 of file AMDGPUISelLowering.cpp.

References llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::dyn_cast(), llvm::AMDGPUISD::FFBH_U32, llvm::AMDGPUISD::FFBL_B32, llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), isCtlzOpc(), isCttzOpc(), isNegativeOne(), llvm::ConstantSDNode::isNullValue(), llvm::ISD::SETEQ, and llvm::ISD::SETNE.

Referenced by performSelectCombine().

◆ PerformDAGCombine()

SDValue AMDGPUTargetLowering::PerformDAGCombine	(	SDNode *	N,
		DAGCombinerInfo &	DCI
	)		const

overridevirtual

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for.

The semantics are as follows: Return Value: SDValue.Val == 0 - No change was made SDValue.Val == N - N was replaced, is dead, and is already handled. otherwise - N should be replaced by the returned Operand.

In addition, methods provided by DAGCombinerInfo may be used to perform more complex transformations.

Reimplemented from llvm::TargetLowering.

Reimplemented in llvm::SITargetLowering, and llvm::R600TargetLowering.

Definition at line 3782 of file AMDGPUISelLowering.cpp.

Referenced by llvm::R600TargetLowering::PerformDAGCombine(), llvm::SITargetLowering::PerformDAGCombine(), and stripBitcast().

◆ performFAbsCombine()

SDValue AMDGPUTargetLowering::performFAbsCombine	(	SDNode *	N,
		DAGCombinerInfo &	DCI
	)		const

protected

Definition at line 3745 of file AMDGPUISelLowering.cpp.

References llvm::ISD::AND, assert(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::ISD::FP16_TO_FP, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::AMDGPUSubtarget::has16BitInsts(), and llvm::SDValue::hasOneUse().

Referenced by PerformDAGCombine().

◆ performFNegCombine()

SDValue AMDGPUTargetLowering::performFNegCombine	(	SDNode *	N,
		DAGCombinerInfo &	DCI
	)		const

protected

Definition at line 3553 of file AMDGPUISelLowering.cpp.

References allUsesHaveSourceMods(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::ISD::FADD, llvm::ISD::FCANONICALIZE, llvm::ISD::FMA, llvm::ISD::FMAD, llvm::AMDGPUISD::FMAX_LEGACY, llvm::ISD::FMAXNUM, llvm::ISD::FMAXNUM_IEEE, llvm::AMDGPUISD::FMED3, llvm::AMDGPUISD::FMIN_LEGACY, llvm::ISD::FMINNUM, llvm::ISD::FMINNUM_IEEE, llvm::ISD::FMUL, llvm::AMDGPUISD::FMUL_LEGACY, llvm::ISD::FNEARBYINT, llvm::ISD::FNEG, fnegFoldsIntoOp(), llvm::ISD::FP16_TO_FP, llvm::ISD::FP_EXTEND, llvm::ISD::FP_ROUND, llvm::ISD::FRINT, llvm::ISD::FSIN, llvm::ISD::FTRUNC, llvm::SelectionDAG::getConstant(), llvm::SDNode::getFlags(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::SDValue::hasOneUse(), I, inverseMinMax(), isConstantCostlierToNegate(), mayIgnoreSignedZero(), llvm::AMDGPUISD::RCP, llvm::AMDGPUISD::RCP_IFLAG, llvm::AMDGPUISD::RCP_LEGACY, llvm::SelectionDAG::ReplaceAllUsesWith(), llvm::AMDGPUISD::SIN_HW, and llvm::ISD::XOR.

Referenced by PerformDAGCombine().

◆ performLoadCombine()

SDValue AMDGPUTargetLowering::performLoadCombine	(	SDNode *	N,
		DAGCombinerInfo &	DCI
	)		const

protected

Definition at line 2793 of file AMDGPUISelLowering.cpp.

References llvm::AMDGPU::HSAMD::Kernel::Arg::Key::Align, llvm::TargetLoweringBase::allowsMisalignedMemoryAccesses(), llvm::ISD::BITCAST, llvm::TargetLowering::DAGCombinerInfo::CombineTo(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::TargetLowering::expandUnalignedLoad(), llvm::MemSDNode::getAddressSpace(), llvm::MemSDNode::getAlignment(), llvm::LoadSDNode::getBasePtr(), llvm::MemSDNode::getChain(), llvm::SelectionDAG::getContext(), getEquivalentMemType(), llvm::SelectionDAG::getLoad(), llvm::MemSDNode::getMemOperand(), llvm::MemSDNode::getMemoryVT(), llvm::SelectionDAG::getMergeValues(), llvm::SelectionDAG::getNode(), llvm::EVT::getStoreSize(), llvm::SDValue::getValue(), hasVolatileUser(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalize(), llvm::ISD::isNormalLoad(), llvm::TargetLoweringBase::isTypeLegal(), llvm::EVT::isVector(), llvm::MemSDNode::isVolatile(), N, llvm::TargetLowering::scalarizeVectorLoad(), shouldCombineMemoryType(), and Size.

Referenced by PerformDAGCombine().

◆ performMulCombine()

SDValue AMDGPUTargetLowering::performMulCombine	(	SDNode *	N,
		DAGCombinerInfo &	DCI
	)		const

protected

◆ performMulhsCombine()

SDValue AMDGPUTargetLowering::performMulhsCombine	(	SDNode *	N,
		DAGCombinerInfo &	DCI
	)		const

protected

Definition at line 3241 of file AMDGPUISelLowering.cpp.

References llvm::TargetLowering::DAGCombinerInfo::AddToWorklist(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getSExtOrTrunc(), llvm::SDNode::getValueType(), llvm::AMDGPUSubtarget::hasMulI24(), llvm::MVT::i32, isI24(), llvm::EVT::isVector(), and llvm::AMDGPUISD::MULHI_I24.

Referenced by PerformDAGCombine().

◆ performMulhuCombine()

SDValue AMDGPUTargetLowering::performMulhuCombine	(	SDNode *	N,
		DAGCombinerInfo &	DCI
	)		const

protected

Definition at line 3265 of file AMDGPUISelLowering.cpp.

References llvm::TargetLowering::DAGCombinerInfo::AddToWorklist(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::EVT::getSizeInBits(), llvm::SDNode::getValueType(), llvm::SelectionDAG::getZExtOrTrunc(), llvm::AMDGPUSubtarget::hasMulU24(), llvm::MVT::i32, isU24(), llvm::EVT::isVector(), and llvm::AMDGPUISD::MULHI_U24.

Referenced by PerformDAGCombine().

◆ performMulLoHi24Combine()

SDValue AMDGPUTargetLowering::performMulLoHi24Combine	(	SDNode *	N,
		DAGCombinerInfo &	DCI
	)		const

protected

Definition at line 3289 of file AMDGPUISelLowering.cpp.

References llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::SelectionDAG::getMergeValues(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::MVT::i32, llvm::AMDGPUISD::MUL_I24, llvm::AMDGPUISD::MUL_LOHI_I24, llvm::AMDGPUISD::MUL_U24, llvm::AMDGPUISD::MULHI_I24, llvm::AMDGPUISD::MULHI_U24, Signed, and simplifyI24().

Referenced by PerformDAGCombine().

◆ performRcpCombine()

SDValue AMDGPUTargetLowering::performRcpCombine	(	SDNode *	N,
		DAGCombinerInfo &	DCI
	)		const

protected

Definition at line 3770 of file AMDGPUISelLowering.cpp.

References llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::dyn_cast(), llvm::SelectionDAG::getConstantFP(), llvm::SDNode::getOperand(), llvm::APFloat::getSemantics(), and llvm::SDNode::getValueType().

Referenced by fp16SrcZerosHighBits(), and PerformDAGCombine().

◆ performSelectCombine()

SDValue AMDGPUTargetLowering::performSelectCombine	(	SDNode *	N,
		DAGCombinerInfo &	DCI
	)		const

protected

◆ performShlCombine()

SDValue AMDGPUTargetLowering::performShlCombine	(	SDNode *	N,
		DAGCombinerInfo &	DCI
	)		const

protected

Definition at line 2947 of file AMDGPUISelLowering.cpp.

References llvm::ISD::ANY_EXTEND, llvm::ISD::BITCAST, llvm::ISD::BUILD_VECTOR, llvm::SelectionDAG::computeKnownBits(), llvm::KnownBits::countMinLeadingZeros(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::dyn_cast(), llvm::SelectionDAG::getBuildVector(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::SelectionDAG::getZExtOrTrunc(), llvm::ConstantSDNode::getZExtValue(), llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i64, llvm::TargetLoweringBase::isOperationLegal(), llvm::MipsISD::Lo, llvm::ISD::SHL, llvm::ISD::SIGN_EXTEND, llvm::ISD::TRUNCATE, llvm::MVT::v2i16, llvm::MVT::v2i32, X, and llvm::ISD::ZERO_EXTEND.

Referenced by PerformDAGCombine().

◆ performSraCombine()

SDValue AMDGPUTargetLowering::performSraCombine	(	SDNode *	N,
		DAGCombinerInfo &	DCI
	)		const

protected

Definition at line 3015 of file AMDGPUISelLowering.cpp.

References llvm::ISD::BITCAST, llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::dyn_cast(), llvm::SelectionDAG::getBuildVector(), llvm::SelectionDAG::getConstant(), getHiHalf64(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::SDNode::getValueType(), llvm::ConstantSDNode::getZExtValue(), llvm::MipsISD::Hi, llvm::MVT::i32, llvm::MVT::i64, llvm::ISD::SRA, and llvm::MVT::v2i32.

Referenced by PerformDAGCombine().

◆ performSrlCombine()

SDValue AMDGPUTargetLowering::performSrlCombine	(	SDNode *	N,
		DAGCombinerInfo &	DCI
	)		const

protected

Definition at line 3050 of file AMDGPUISelLowering.cpp.

References llvm::ISD::BITCAST, llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::dyn_cast(), llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SelectionDAG::getBuildVector(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::SDNode::getValueType(), llvm::ConstantSDNode::getZExtValue(), llvm::MipsISD::Hi, llvm::MVT::i32, llvm::MVT::i64, llvm::ISD::SRL, and llvm::MVT::v2i32.

Referenced by PerformDAGCombine().

◆ performStoreCombine()

SDValue AMDGPUTargetLowering::performStoreCombine	(	SDNode *	N,
		DAGCombinerInfo &	DCI
	)		const

protected

Definition at line 2844 of file AMDGPUISelLowering.cpp.

References llvm::AMDGPU::HSAMD::Kernel::Arg::Key::Align, llvm::TargetLoweringBase::allowsMisalignedMemoryAccesses(), llvm::ISD::BITCAST, llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::TargetLowering::expandUnalignedStore(), llvm::MemSDNode::getAddressSpace(), llvm::MemSDNode::getAlignment(), llvm::StoreSDNode::getBasePtr(), llvm::MemSDNode::getChain(), llvm::SelectionDAG::getContext(), getEquivalentMemType(), llvm::MemSDNode::getMemOperand(), llvm::MemSDNode::getMemoryVT(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getStore(), llvm::EVT::getStoreSize(), llvm::StoreSDNode::getValue(), llvm::SDValue::hasOneUse(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalize(), llvm::ISD::isNormalStore(), llvm::TargetLoweringBase::isTypeLegal(), llvm::EVT::isVector(), llvm::MemSDNode::isVolatile(), N, llvm::SelectionDAG::ReplaceAllUsesOfValueWith(), llvm::TargetLowering::scalarizeVectorStore(), shouldCombineMemoryType(), and Size.

Referenced by PerformDAGCombine().

◆ performTruncateCombine()

SDValue AMDGPUTargetLowering::performTruncateCombine	(	SDNode *	N,
		DAGCombinerInfo &	DCI
	)		const

protected

Definition at line 3085 of file AMDGPUISelLowering.cpp.

References llvm::TargetLowering::DAGCombinerInfo::AddToWorklist(), llvm::ISD::BITCAST, llvm::ISD::BUILD_VECTOR, llvm::EVT::changeTypeToInteger(), llvm::SelectionDAG::computeKnownBits(), llvm::KnownBits::countMinLeadingZeros(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::KnownBits::getBitWidth(), llvm::KnownBits::getConstant(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getDataLayout(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::TargetLoweringBase::getShiftAmountTy(), llvm::EVT::getSizeInBits(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::EVT::getVectorNumElements(), llvm::EVT::getVectorVT(), llvm::SelectionDAG::getZExtOrTrunc(), llvm::MVT::i32, llvm::KnownBits::isConstant(), llvm::isConstOrConstSplat(), llvm::EVT::isFloatingPoint(), llvm::EVT::isVector(), llvm::Log2_32(), llvm::ISD::SHL, Size, llvm::ISD::SRA, llvm::ISD::SRL, stripBitcast(), llvm::ISD::TRUNCATE, and llvm::APInt::ule().

Referenced by PerformDAGCombine().

◆ PostISelFolding()

virtual SDNode* llvm::AMDGPUTargetLowering::PostISelFolding	(	MachineSDNode *	N,
		SelectionDAG &	DAG
	)		const

pure virtual

Implemented in llvm::SITargetLowering.

Referenced by isFsqrtCheap().

◆ ReplaceNodeResults()

void AMDGPUTargetLowering::ReplaceNodeResults	(	SDNode *	,
		SmallVectorImpl< SDValue > &	,
		SelectionDAG &
	)		const

overridevirtual

This callback is invoked when a node result type is illegal for the target, and the operation was registered to use 'custom' lowering for that result type.

The target places new result values for the node in Results (their number and types must exactly match those of the original return values of the node), or leaves Results empty, which indicates that the node is not to be custom lowered after all.

If the target has no operations that require custom lowering, it need not implement this. The default implementation aborts.

Reimplemented from llvm::TargetLowering.

Reimplemented in llvm::SITargetLowering, and llvm::R600TargetLowering.

Definition at line 1178 of file AMDGPUISelLowering.cpp.

References llvm::SDNode::getOpcode(), and llvm::ISD::SIGN_EXTEND_INREG.

Referenced by llvm::R600TargetLowering::ReplaceNodeResults(), and stripBitcast().

◆ shouldCombineMemoryType()

bool AMDGPUTargetLowering::shouldCombineMemoryType ( EVT VT ) const

protected

Definition at line 2772 of file AMDGPUISelLowering.cpp.

References llvm::EVT::getScalarType(), llvm::EVT::getStoreSize(), llvm::MVT::i32, llvm::EVT::isByteSized(), llvm::TargetLoweringBase::isTypeLegal(), llvm::EVT::isVector(), and Size.

Referenced by performLoadCombine(), and performStoreCombine().

◆ shouldExpandAtomicRMWInIR()

TargetLowering::AtomicExpansionKind AMDGPUTargetLowering::shouldExpandAtomicRMWInIR ( AtomicRMWInst * ) const

overridevirtual

Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all.

Default is to never expand.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 4522 of file AMDGPUISelLowering.cpp.

References llvm::TargetLoweringBase::CmpXChg, llvm::AtomicRMWInst::getOperation(), llvm::AtomicRMWInst::Nand, and llvm::TargetLoweringBase::None.

Referenced by getFenceOperandTy().

◆ shouldReduceLoadWidth()

bool AMDGPUTargetLowering::shouldReduceLoadWidth	(	SDNode *	Load,
		ISD::LoadExtType	ExtTy,
		EVT	NewVT
	)		const

overridevirtual

Return true if it is profitable to reduce a load to a smaller type.

Example: (i16 (trunc (i32 (load x))) -> i16 load x

Reimplemented from llvm::TargetLoweringBase.

Definition at line 655 of file AMDGPUISelLowering.cpp.

References AMDGPUAS::CONSTANT_ADDRESS, AMDGPUAS::CONSTANT_ADDRESS_32BIT, llvm::MemSDNode::getAddressSpace(), getAlignment(), llvm::MemSDNode::getMemOperand(), llvm::EVT::getStoreSizeInBits(), llvm::SDNode::getValueType(), AMDGPUAS::GLOBAL_ADDRESS, llvm::MemSDNode::isInvariant(), llvm::AMDGPUInstrInfo::isUniformMMO(), N, and llvm::TargetLoweringBase::shouldReduceLoadWidth().

Referenced by stripBitcast().

◆ ShouldShrinkFPConstant()

bool AMDGPUTargetLowering::ShouldShrinkFPConstant ( EVT ) const

overridevirtual

If true, then instruction selection should seek to shrink the FP constant of the specified type to a smaller type in order to save space and / or reduce runtime.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 650 of file AMDGPUISelLowering.cpp.

References llvm::MVT::f32, llvm::MVT::f64, and llvm::EVT::getScalarType().

Referenced by stripBitcast().

◆ split64BitValue()

std::pair< SDValue, SDValue > AMDGPUTargetLowering::split64BitValue	(	SDValue	Op,
		SelectionDAG &	DAG
	)		const

protected

Return 64-bit value Op as two 32-bit integers.

Definition at line 1345 of file AMDGPUISelLowering.cpp.

References llvm::ISD::BITCAST, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::MipsISD::Hi, llvm::MVT::i32, llvm::MipsISD::Lo, and llvm::MVT::v2i32.

Referenced by getPermuteMask(), and splitBinaryBitConstantOpImpl().

◆ splitBinaryBitConstantOpImpl()

SDValue AMDGPUTargetLowering::splitBinaryBitConstantOpImpl	(	DAGCombinerInfo &	DCI,
		const SDLoc &	SL,
		unsigned	Opc,
		SDValue	LHS,
		uint32_t	ValLo,
		uint32_t	ValHi
	)		const

protected

Split the 64-bit value LHS into two 32-bit components, and perform the binary operation Opc to it with the corresponding constant operands.

Definition at line 2924 of file AMDGPUISelLowering.cpp.

References llvm::TargetLowering::DAGCombinerInfo::AddToWorklist(), llvm::ISD::BITCAST, llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::SelectionDAG::getBuildVector(), llvm::SelectionDAG::getConstant(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::MipsISD::Hi, llvm::MVT::i32, llvm::MVT::i64, llvm::MipsISD::Lo, split64BitValue(), and llvm::MVT::v2i32.

Referenced by bitOpWithConstantIsReducible().

◆ SplitVectorLoad()

SDValue AMDGPUTargetLowering::SplitVectorLoad	(	SDValue	Op,
		SelectionDAG &	DAG
	)		const

protected

Split a vector load into 2 loads of half the vector.

Definition at line 1375 of file AMDGPUISelLowering.cpp.

References llvm::ISD::CONCAT_VECTORS, llvm::MemSDNode::getAlignment(), llvm::LoadSDNode::getBasePtr(), llvm::MemSDNode::getChain(), llvm::LoadSDNode::getExtensionType(), llvm::SelectionDAG::getExtLoad(), llvm::MachineMemOperand::getFlags(), llvm::MemSDNode::getMemOperand(), llvm::MemSDNode::getMemoryVT(), llvm::SelectionDAG::getMergeValues(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getObjectPtrOffset(), llvm::MachineMemOperand::getPointerInfo(), llvm::SelectionDAG::GetSplitDestVTs(), llvm::EVT::getStoreSize(), llvm::SDValue::getValue(), llvm::SDValue::getValueType(), llvm::MipsISD::Hi, llvm::MipsISD::Lo, llvm::SPII::Load, llvm::MinAlign(), llvm::MVT::Other, llvm::TargetLowering::scalarizeVectorLoad(), Size, llvm::SelectionDAG::SplitVector(), and llvm::ISD::TokenFactor.

Referenced by getLoadExtOrTrunc().

◆ SplitVectorStore()

SDValue AMDGPUTargetLowering::SplitVectorStore	(	SDValue	Op,
		SelectionDAG &	DAG
	)		const

protected

Split a vector store into 2 stores of half the vector.

Definition at line 1422 of file AMDGPUISelLowering.cpp.

References llvm::MemSDNode::getAlignment(), llvm::StoreSDNode::getBasePtr(), llvm::MemSDNode::getChain(), llvm::MachineMemOperand::getFlags(), llvm::MemSDNode::getMemOperand(), llvm::MemSDNode::getMemoryVT(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getObjectPtrOffset(), llvm::MachineMemOperand::getPointerInfo(), llvm::SelectionDAG::GetSplitDestVTs(), llvm::EVT::getStoreSize(), llvm::SelectionDAG::getTruncStore(), llvm::StoreSDNode::getValue(), llvm::EVT::getVectorNumElements(), llvm::MachinePointerInfo::getWithOffset(), llvm::MipsISD::Hi, llvm::MipsISD::Lo, llvm::MinAlign(), llvm::MVT::Other, llvm::TargetLowering::scalarizeVectorStore(), Size, llvm::SelectionDAG::SplitVector(), llvm::SPII::Store, and llvm::ISD::TokenFactor.

Referenced by getFPTernOp().

◆ storeOfVectorConstantIsCheap()

bool AMDGPUTargetLowering::storeOfVectorConstantIsCheap	(	EVT	MemVT,
		unsigned	NumElem,
		unsigned	AddrSpace
	)		const

overridevirtual

Return true if it is expected to be cheaper to do a store of a non-zero vector constant with the given size and type for the address space than to store the individual scalar element constants.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 770 of file AMDGPUISelLowering.cpp.

Referenced by stripBitcast().

◆ storeStackInputValue()

SDValue AMDGPUTargetLowering::storeStackInputValue	(	SelectionDAG &	DAG,
		const SDLoc &	SL,
		SDValue	Chain,
		SDValue	ArgVal,
		int64_t	Offset
	)		const

Definition at line 4034 of file AMDGPUISelLowering.cpp.

References llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getMachineFunction(), llvm::MachinePointerInfo::getStack(), llvm::SelectionDAG::getStore(), llvm::MVT::i32, llvm::MachineMemOperand::MODereferenceable, and llvm::SPII::Store.

Referenced by CreateLiveInRegisterRaw(), and llvm::SITargetLowering::passSpecialInputs().

◆ stripBitcast()

static SDValue llvm::AMDGPUTargetLowering::stripBitcast ( SDValue Val )

inlinestatic

Definition at line 145 of file AMDGPUISelLowering.h.

References addTokenForArgument(), aggressivelyPreferBuildVectorSources(), allUsesHaveSourceMods(), llvm::ISD::BITCAST, CCAssignFnForCall(), CCAssignFnForReturn(), combineFMinMaxLegacy(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), getTargetNodeName(), getVectorIdxTy(), isCheapToSpeculateCtlz(), isCheapToSpeculateCttz(), isFAbsFree(), isFNegFree(), isFPImmLegal(), isLoadBitCastBeneficial(), isNarrowingProfitable(), isSDNodeAlwaysUniform(), isSelectSupported(), isTruncateFree(), isZExtFree(), llvm::SPII::Load, LowerCall(), LowerDYNAMIC_STACKALLOC(), LowerOperation(), LowerReturn(), lowerUnhandledCall(), PerformDAGCombine(), ReplaceNodeResults(), shouldReduceLoadWidth(), ShouldShrinkFPConstant(), and storeOfVectorConstantIsCheap().

Referenced by performTruncateCombine().

The documentation for this class was generated from the following files:

lib/Target/AMDGPU/AMDGPUISelLowering.h
lib/Target/AMDGPU/AMDGPUISelLowering.cpp

Public Types

Public Member Functions

Static Public Member Functions

Protected Member Functions

Static Protected Member Functions

Additional Inherited Members

Detailed Description

Member Enumeration Documentation

◆ ImplicitParameter

Constructor & Destructor Documentation

◆ AMDGPUTargetLowering()

Member Function Documentation

◆ addTokenForArgument()

◆ aggressivelyPreferBuildVectorSources()

◆ allUsesHaveSourceMods()

◆ analyzeFormalArgumentsCompute()

◆ CCAssignFnForCall()

◆ CCAssignFnForReturn()

◆ combineFMinMaxLegacy()

◆ computeKnownBitsForTargetNode()

◆ ComputeNumSignBitsForTargetNode()

◆ CreateLiveInRegister() [1/2]

◆ CreateLiveInRegister() [2/2]

◆ CreateLiveInRegisterRaw()

◆ getEquivalentMemType()

◆ getFenceOperandTy()

◆ getHiHalf64()

◆ getImplicitParameterOffset()

◆ getLoHalf64()

◆ getRecipEstimate()

◆ getSqrtEstimate()

◆ getTargetNodeName()

◆ getVectorIdxTy()

◆ isCheapToSpeculateCtlz()

◆ isCheapToSpeculateCttz()

◆ isConstantCostlierToNegate()

◆ isFAbsFree()

◆ isFNegFree()

◆ isFPImmLegal()

◆ isFsqrtCheap()

◆ isKnownNeverNaNForTargetNode()

◆ isLoadBitCastBeneficial()

◆ isNarrowingProfitable()

◆ isSDNodeAlwaysUniform()

◆ isSelectSupported()

◆ isTruncateFree() [1/2]

◆ isTruncateFree() [2/2]

◆ isZExtFree() [1/3]

◆ isZExtFree() [2/3]

◆ isZExtFree() [3/3]

◆ loadInputValue()

◆ loadStackInputValue()

◆ LowerCall()

◆ LowerCONCAT_VECTORS()

◆ LowerCTLZ_CTTZ()

◆ LowerDIVREM24()

◆ LowerDYNAMIC_STACKALLOC()

◆ LowerEXTRACT_SUBVECTOR()

◆ LowerFCEIL()

◆ lowerFEXP()

◆ LowerFFLOOR()

◆ LowerFLOG()

◆ LowerFNEARBYINT()

◆ LowerFP64_TO_INT()

◆ LowerFP_TO_FP16()

◆ LowerFP_TO_SINT()

◆ LowerFP_TO_UINT()

◆ LowerFREM()

◆ LowerFRINT()

◆ LowerFROUND()

◆ LowerFROUND32_16()

◆ LowerFROUND64()

◆ LowerFTRUNC()

◆ LowerGlobalAddress()

◆ LowerINT_TO_FP32()

◆ LowerINT_TO_FP64()

◆ LowerOperation()

◆ LowerReturn()

◆ LowerSDIVREM()

◆ LowerSIGN_EXTEND_INREG()