#include "Target/AMDGPU/SIISelLowering.h"
Public Member Functions | |
| MVT | getRegisterTypeForCallingConv (LLVMContext &Context, CallingConv::ID CC, EVT VT) const override |
| Certain combinations of ABIs, Targets and features require that types are legal for some operations and not for other operations. More... | |
| unsigned | getNumRegistersForCallingConv (LLVMContext &Context, CallingConv::ID CC, EVT VT) const override |
| Certain targets require unusual breakdowns of certain types. More... | |
| unsigned | getVectorTypeBreakdownForCallingConv (LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const override |
| Certain targets such as MIPS require that some types such as vectors are always broken down into scalars in some contexts. More... | |
| SITargetLowering (const TargetMachine &tm, const GCNSubtarget &STI) | |
| const GCNSubtarget * | getSubtarget () const |
| bool | isFPExtFoldable (unsigned Opcode, EVT DestVT, EVT SrcVT) const override |
Return true if an fpext operation input to an Opcode operation is free (for instance, because half-precision floating-point numbers are implicitly extended to float-precision) for an FMA instruction. More... | |
| bool | isShuffleMaskLegal (ArrayRef< int >, EVT) const override |
| Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations, those with specific masks. More... | |
| bool | getTgtMemIntrinsic (IntrinsicInfo &, const CallInst &, MachineFunction &MF, unsigned IntrinsicID) const override |
| Given an intrinsic, checks if on the target the intrinsic will need to map to a MemIntrinsicNode (touches memory). More... | |
| bool | getAddrModeArguments (IntrinsicInst *, SmallVectorImpl< Value *> &, Type *&) const override |
| CodeGenPrepare sinks address calculations into the same BB as Load/Store instructions reading the address. More... | |
| bool | isLegalGlobalAddressingMode (const AddrMode &AM) const |
| bool | isLegalAddressingMode (const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS, Instruction *I=nullptr) const override |
| Return true if the addressing mode represented by AM is legal for this target, for a load/store of the specified type. More... | |
| bool | canMergeStoresTo (unsigned AS, EVT MemVT, const SelectionDAG &DAG) const override |
| Returns if it's reasonable to merge stores to MemVT size. More... | |
| bool | allowsMisalignedMemoryAccesses (EVT VT, unsigned AS, unsigned Align, bool *IsFast) const override |
| Determine if the target supports unaligned memory accesses. More... | |
| EVT | getOptimalMemOpType (uint64_t Size, unsigned DstAlign, unsigned SrcAlign, bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc, MachineFunction &MF) const override |
| Returns the target specific optimal type for load and store operations as a result of memset, memcpy, and memmove lowering. More... | |
| bool | isMemOpUniform (const SDNode *N) const |
| bool | isMemOpHasNoClobberedMemOperand (const SDNode *N) const |
| bool | isNoopAddrSpaceCast (unsigned SrcAS, unsigned DestAS) const override |
| Returns true if a cast between SrcAS and DestAS is a noop. More... | |
| bool | isCheapAddrSpaceCast (unsigned SrcAS, unsigned DestAS) const override |
| Returns true if a cast from SrcAS to DestAS is "cheap", such that e.g. More... | |
| TargetLoweringBase::LegalizeTypeAction | getPreferredVectorAction (MVT VT) const override |
| Return the preferred vector type legalization action. More... | |
| bool | shouldConvertConstantLoadToIntImm (const APInt &Imm, Type *Ty) const override |
| Return true if it is beneficial to convert a load of a constant to just the constant itself. More... | |
| bool | isTypeDesirableForOp (unsigned Op, EVT VT) const override |
| Return true if the target has native support for the specified value type and it is 'desirable' to use the type for the given node type. More... | |
| bool | isOffsetFoldingLegal (const GlobalAddressSDNode *GA) const override |
| Return true if folding a constant offset with the given GlobalAddress is legal. More... | |
| bool | supportSplitCSR (MachineFunction *MF) const override |
| Return true if the target supports that a subset of CSRs for the given machine function is handled explicitly via copies. More... | |
| void | initializeSplitCSR (MachineBasicBlock *Entry) const override |
| Perform necessary initialization to handle a subset of CSRs explicitly via copies. More... | |
| void | insertCopiesSplitCSR (MachineBasicBlock *Entry, const SmallVectorImpl< MachineBasicBlock *> &Exits) const override |
| Insert explicit copies in entry and exit blocks. More... | |
| SDValue | LowerFormalArguments (SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, const SDLoc &DL, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const override |
| This hook must be implemented to lower the incoming (formal) arguments, described by the Ins array, into the specified DAG. More... | |
| bool | CanLowerReturn (CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, LLVMContext &Context) const override |
| This hook should be implemented to check whether the return values described by the Outs array can fit into the return registers. More... | |
| SDValue | LowerReturn (SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SDLoc &DL, SelectionDAG &DAG) const override |
| This hook must be implemented to lower outgoing return values, described by the Outs array, into the specified DAG. More... | |
| void | passSpecialInputs (CallLoweringInfo &CLI, CCState &CCInfo, const SIMachineFunctionInfo &Info, SmallVectorImpl< std::pair< unsigned, SDValue >> &RegsToPass, SmallVectorImpl< SDValue > &MemOpChains, SDValue Chain) const |
| SDValue | LowerCallResult (SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, const SDLoc &DL, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals, bool isThisReturn, SDValue ThisVal) const |
| bool | mayBeEmittedAsTailCall (const CallInst *) const override |
| Return true if the target may be able emit the call instruction as a tail call. More... | |
| bool | isEligibleForTailCallOptimization (SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SmallVectorImpl< ISD::InputArg > &Ins, SelectionDAG &DAG) const |
| SDValue | LowerCall (CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals) const override |
| This hook must be implemented to lower calls into the specified DAG. More... | |
| unsigned | getRegisterByName (const char *RegName, EVT VT, SelectionDAG &DAG) const override |
| Return the register ID of the name passed in. More... | |
| MachineBasicBlock * | splitKillBlock (MachineInstr &MI, MachineBasicBlock *BB) const |
| MachineBasicBlock * | EmitInstrWithCustomInserter (MachineInstr &MI, MachineBasicBlock *BB) const override |
| This method should be implemented by targets that mark instructions with the 'usesCustomInserter' flag. More... | |
| bool | hasBitPreservingFPLogic (EVT VT) const override |
| Return true if it is safe to transform an integer-domain bitwise operation into the equivalent floating-point operation. More... | |
| bool | enableAggressiveFMAFusion (EVT VT) const override |
| Return true if target always beneficiates from combining into FMA for a given value type. More... | |
| EVT | getSetCCResultType (const DataLayout &DL, LLVMContext &Context, EVT VT) const override |
| Return the ValueType of the result of SETCC operations. More... | |
| MVT | getScalarShiftAmountTy (const DataLayout &, EVT) const override |
| EVT is not used in-tree, but is used by out-of-tree target. More... | |
| bool | isFMAFasterThanFMulAndFAdd (EVT VT) const override |
| Return true if an FMA operation is faster than a pair of fmul and fadd instructions. More... | |
| SDValue | splitUnaryVectorOp (SDValue Op, SelectionDAG &DAG) const |
| SDValue | splitBinaryVectorOp (SDValue Op, SelectionDAG &DAG) const |
| SDValue | LowerOperation (SDValue Op, SelectionDAG &DAG) const override |
| This callback is invoked for operations that are unsupported by the target, which are registered to use 'custom' lowering, and whose defined values are all legal. More... | |
| void | ReplaceNodeResults (SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override |
| This callback is invoked when a node result type is illegal for the target, and the operation was registered to use 'custom' lowering for that result type. More... | |
| SDValue | PerformDAGCombine (SDNode *N, DAGCombinerInfo &DCI) const override |
| This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for. More... | |
| SDNode * | PostISelFolding (MachineSDNode *N, SelectionDAG &DAG) const override |
| Fold the instructions after selecting them. More... | |
| void | AdjustInstrPostInstrSelection (MachineInstr &MI, SDNode *Node) const override |
| Assign the register class depending on the number of bits set in the writemask. More... | |
| SDNode * | legalizeTargetIndependentNode (SDNode *Node, SelectionDAG &DAG) const |
| Legalize target independent instructions (e.g. More... | |
| MachineSDNode * | wrapAddr64Rsrc (SelectionDAG &DAG, const SDLoc &DL, SDValue Ptr) const |
| MachineSDNode * | buildRSRC (SelectionDAG &DAG, const SDLoc &DL, SDValue Ptr, uint32_t RsrcDword1, uint64_t RsrcDword2And3) const |
| Return a resource descriptor with the 'Add TID' bit enabled The TID (Thread ID) is multiplied by the stride value (bits [61:48] of the resource descriptor) to create an offset, which is added to the resource pointer. More... | |
| std::pair< unsigned, const TargetRegisterClass * > | getRegForInlineAsmConstraint (const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override |
| Given a physical register constraint (e.g. More... | |
| ConstraintType | getConstraintType (StringRef Constraint) const override |
| Given a constraint, return the type of constraint it is for this target. More... | |
| SDValue | copyToM0 (SelectionDAG &DAG, SDValue Chain, const SDLoc &DL, SDValue V) const |
| void | finalizeLowering (MachineFunction &MF) const override |
| Execute target specific actions to finalize target lowering. More... | |
| void | computeKnownBitsForFrameIndex (const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth=0) const override |
Determine which of the bits of FrameIndex FIOp are known to be 0. More... | |
| bool | isSDNodeSourceOfDivergence (const SDNode *N, FunctionLoweringInfo *FLI, LegacyDivergenceAnalysis *DA) const override |
| bool | isCanonicalized (SelectionDAG &DAG, SDValue Op, unsigned MaxDepth=5) const |
| bool | denormalsEnabledForType (EVT VT) const |
| bool | isKnownNeverNaNForTargetNode (SDValue Op, const SelectionDAG &DAG, bool SNaN=false, unsigned Depth=0) const override |
If SNaN is false,. More... | |
 Public Member Functions inherited from llvm::AMDGPUTargetLowering | |
| AMDGPUTargetLowering (const TargetMachine &TM, const AMDGPUSubtarget &STI) | |
| bool | mayIgnoreSignedZero (SDValue Op) const |
| bool | isFAbsFree (EVT VT) const override |
| Return true if an fabs operation is free to the point where it is never worthwhile to replace it with a bitwise operation. More... | |
| bool | isFNegFree (EVT VT) const override |
| Return true if an fneg operation is free to the point where it is never worthwhile to replace it with a bitwise operation. More... | |
| bool | isTruncateFree (EVT Src, EVT Dest) const override |
| bool | isTruncateFree (Type *Src, Type *Dest) const override |
| Return true if it's free to truncate a value of type FromTy to type ToTy. More... | |
| bool | isZExtFree (Type *Src, Type *Dest) const override |
| Return true if any actual instruction that defines a value of type FromTy implicitly zero-extends the value to ToTy in the result register. More... | |
| bool | isZExtFree (EVT Src, EVT Dest) const override |
| bool | isZExtFree (SDValue Val, EVT VT2) const override |
| Return true if zero-extending the specific node Val to type VT2 is free (either because it's implicitly zero-extended such as ARM ldrb / ldrh or because it's folded such as X86 zero-extending loads). More... | |
| bool | isNarrowingProfitable (EVT VT1, EVT VT2) const override |
| Return true if it's profitable to narrow operations of type VT1 to VT2. More... | |
| MVT | getVectorIdxTy (const DataLayout &) const override |
| Returns the type to be used for the index operand of: ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT, ISD::INSERT_SUBVECTOR, and ISD::EXTRACT_SUBVECTOR. More... | |
| bool | isSelectSupported (SelectSupportKind) const override |
| bool | isFPImmLegal (const APFloat &Imm, EVT VT) const override |
| Returns true if the target can instruction select the specified FP immediate natively. More... | |
| bool | ShouldShrinkFPConstant (EVT VT) const override |
| If true, then instruction selection should seek to shrink the FP constant of the specified type to a smaller type in order to save space and / or reduce runtime. More... | |
| bool | shouldReduceLoadWidth (SDNode *Load, ISD::LoadExtType ExtType, EVT ExtVT) const override |
| Return true if it is profitable to reduce a load to a smaller type. More... | |
| bool | isLoadBitCastBeneficial (EVT, EVT) const final |
| Return true if the following transform is beneficial: fold (conv (load x)) -> (load (conv*)x) On architectures that don't natively support some vector loads efficiently, casting the load to a smaller vector of larger types and loading is more efficient, however, this can be undone by optimizations in dag combiner. More... | |
| bool | storeOfVectorConstantIsCheap (EVT MemVT, unsigned NumElem, unsigned AS) const override |
| Return true if it is expected to be cheaper to do a store of a non-zero vector constant with the given size and type for the address space than to store the individual scalar element constants. More... | |
| bool | aggressivelyPreferBuildVectorSources (EVT VecVT) const override |
| bool | isCheapToSpeculateCttz () const override |
| Return true if it is cheap to speculate a call to intrinsic cttz. More... | |
| bool | isCheapToSpeculateCtlz () const override |
| Return true if it is cheap to speculate a call to intrinsic ctlz. More... | |
| bool | isSDNodeAlwaysUniform (const SDNode *N) const override |
| SDValue | addTokenForArgument (SDValue Chain, SelectionDAG &DAG, MachineFrameInfo &MFI, int ClobberedFI) const |
| SDValue | lowerUnhandledCall (CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals, StringRef Reason) const |
| SDValue | LowerDYNAMIC_STACKALLOC (SDValue Op, SelectionDAG &DAG) const |
| SDValue | combineFMinMaxLegacy (const SDLoc &DL, EVT VT, SDValue LHS, SDValue RHS, SDValue True, SDValue False, SDValue CC, DAGCombinerInfo &DCI) const |
| Generate Min/Max node. More... | |
| const char * | getTargetNodeName (unsigned Opcode) const override |
| This method returns the name of a target specific DAG node. More... | |
| bool | mergeStoresAfterLegalization () const override |
| Allow store merging after legalization in addition to before legalization. More... | |
| bool | isFsqrtCheap (SDValue Operand, SelectionDAG &DAG) const override |
| Return true if SQRT(X) shouldn't be replaced with X*RSQRT(X). More... | |
| SDValue | getSqrtEstimate (SDValue Operand, SelectionDAG &DAG, int Enabled, int &RefinementSteps, bool &UseOneConstNR, bool Reciprocal) const override |
| Hooks for building estimates in place of slower divisions and square roots. More... | |
| SDValue | getRecipEstimate (SDValue Operand, SelectionDAG &DAG, int Enabled, int &RefinementSteps) const override |
| Return a reciprocal estimate value for the input operand. More... | |
| void | computeKnownBitsForTargetNode (const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth=0) const override |
Determine which of the bits specified in Mask are known to be either zero or one and return them in the KnownZero and KnownOne bitsets. More... | |
| unsigned | ComputeNumSignBitsForTargetNode (SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth=0) const override |
| This method can be implemented by targets that want to expose additional information about sign bits to the DAG Combiner. More... | |
| SDValue | CreateLiveInRegister (SelectionDAG &DAG, const TargetRegisterClass *RC, unsigned Reg, EVT VT, const SDLoc &SL, bool RawReg=false) const |
| Helper function that adds Reg to the LiveIn list of the DAG's MachineFunction. More... | |
| SDValue | CreateLiveInRegister (SelectionDAG &DAG, const TargetRegisterClass *RC, unsigned Reg, EVT VT) const |
| SDValue | CreateLiveInRegisterRaw (SelectionDAG &DAG, const TargetRegisterClass *RC, unsigned Reg, EVT VT) const |
| SDValue | loadStackInputValue (SelectionDAG &DAG, EVT VT, const SDLoc &SL, int64_t Offset) const |
| Similar to CreateLiveInRegister, except value maybe loaded from a stack slot rather than passed in a register. More... | |
| SDValue | storeStackInputValue (SelectionDAG &DAG, const SDLoc &SL, SDValue Chain, SDValue ArgVal, int64_t Offset) const |
| SDValue | loadInputValue (SelectionDAG &DAG, const TargetRegisterClass *RC, EVT VT, const SDLoc &SL, const ArgDescriptor &Arg) const |
| uint32_t | getImplicitParameterOffset (const MachineFunction &MF, const ImplicitParameter Param) const |
| Helper function that returns the byte offset of the given type of implicit parameter. More... | |
| MVT | getFenceOperandTy (const DataLayout &DL) const override |
| Return the type for operands of fence. More... | |
| AtomicExpansionKind | shouldExpandAtomicRMWInIR (AtomicRMWInst *) const override |
| Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all. More... | |
| Public Member Functions inherited from llvm::TargetLowering | |
| TargetLowering (const TargetLowering &)=delete | |
| TargetLowering & | operator= (const TargetLowering &)=delete |
| TargetLowering (const TargetMachine &TM) | |
| NOTE: The TargetMachine owns TLOF. More... | |
| bool | isPositionIndependent () const |
| virtual bool | getPreIndexedAddressParts (SDNode *, SDValue &, SDValue &, ISD::MemIndexedMode &, SelectionDAG &) const |
| Returns true by value, base pointer and offset pointer and addressing mode by reference if the node's address can be legally represented as pre-indexed load / store address. More... | |
| virtual bool | getPostIndexedAddressParts (SDNode *, SDNode *, SDValue &, SDValue &, ISD::MemIndexedMode &, SelectionDAG &) const |
| Returns true by value, base pointer and offset pointer and addressing mode by reference if this node can be combined with a load / store to form a post-indexed load / store. More... | |
| virtual unsigned | getJumpTableEncoding () const |
| Return the entry encoding for a jump table in the current function. More... | |
| virtual const MCExpr * | LowerCustomJumpTableEntry (const MachineJumpTableInfo *, const MachineBasicBlock *, unsigned, MCContext &) const |
| virtual SDValue | getPICJumpTableRelocBase (SDValue Table, SelectionDAG &DAG) const |
| Returns relocation base for the given PIC jumptable. More... | |
| virtual const MCExpr * | getPICJumpTableRelocBaseExpr (const MachineFunction *MF, unsigned JTI, MCContext &Ctx) const |
| This returns the relocation base for the given PIC jumptable, the same as getPICJumpTableRelocBase, but as an MCExpr. More... | |
| bool | isInTailCallPosition (SelectionDAG &DAG, SDNode *Node, SDValue &Chain) const |
| Check whether a given call node is in tail position within its function. More... | |
| void | softenSetCCOperands (SelectionDAG &DAG, EVT VT, SDValue &NewLHS, SDValue &NewRHS, ISD::CondCode &CCCode, const SDLoc &DL) const |
| Soften the operands of a comparison. More... | |
| std::pair< SDValue, SDValue > | makeLibCall (SelectionDAG &DAG, RTLIB::Libcall LC, EVT RetVT, ArrayRef< SDValue > Ops, bool isSigned, const SDLoc &dl, bool doesNotReturn=false, bool isReturnValueUsed=true) const |
| Returns a pair of (return value, chain). More... | |
| bool | parametersInCSRMatch (const MachineRegisterInfo &MRI, const uint32_t *CallerPreservedMask, const SmallVectorImpl< CCValAssign > &ArgLocs, const SmallVectorImpl< SDValue > &OutVals) const |
| Check whether parameters to a call that are passed in callee saved registers are the same as from the calling function. More... | |
| bool | ShrinkDemandedConstant (SDValue Op, const APInt &Demanded, TargetLoweringOpt &TLO) const |
| Check to see if the specified operand of the specified instruction is a constant integer. More... | |
| virtual bool | targetShrinkDemandedConstant (SDValue Op, const APInt &Demanded, TargetLoweringOpt &TLO) const |
| bool | ShrinkDemandedOp (SDValue Op, unsigned BitWidth, const APInt &Demanded, TargetLoweringOpt &TLO) const |
| Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the casts are free. More... | |
| bool | SimplifyDemandedBits (SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, KnownBits &Known, TargetLoweringOpt &TLO, unsigned Depth=0, bool AssumeSingleUse=false) const |
| Look at Op. More... | |
| bool | SimplifyDemandedBits (SDValue Op, const APInt &DemandedBits, KnownBits &Known, TargetLoweringOpt &TLO, unsigned Depth=0, bool AssumeSingleUse=false) const |
| Helper wrapper around SimplifyDemandedBits, demanding all elements. More... | |
| bool | SimplifyDemandedBits (SDValue Op, const APInt &DemandedMask, DAGCombinerInfo &DCI) const |
| Helper wrapper around SimplifyDemandedBits. More... | |
| bool | SimplifyDemandedVectorElts (SDValue Op, const APInt &DemandedEltMask, APInt &KnownUndef, APInt &KnownZero, TargetLoweringOpt &TLO, unsigned Depth=0, bool AssumeSingleUse=false) const |
| Look at Vector Op. More... | |
| bool | SimplifyDemandedVectorElts (SDValue Op, const APInt &DemandedElts, APInt &KnownUndef, APInt &KnownZero, DAGCombinerInfo &DCI) const |
| Helper wrapper around SimplifyDemandedVectorElts. More... | |
| virtual bool | SimplifyDemandedVectorEltsForTargetNode (SDValue Op, const APInt &DemandedElts, APInt &KnownUndef, APInt &KnownZero, TargetLoweringOpt &TLO, unsigned Depth=0) const |
| Attempt to simplify any target nodes based on the demanded vector elements, returning true on success. More... | |
| virtual bool | SimplifyDemandedBitsForTargetNode (SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, KnownBits &Known, TargetLoweringOpt &TLO, unsigned Depth=0) const |
| Attempt to simplify any target nodes based on the demanded bits/elts, returning true on success. More... | |
| bool | isConstTrueVal (const SDNode *N) const |
| Return if the N is a constant or constant vector equal to the true value from getBooleanContents(). More... | |
| bool | isConstFalseVal (const SDNode *N) const |
| Return if the N is a constant or constant vector equal to the false value from getBooleanContents(). More... | |
| bool | isExtendedTrueVal (const ConstantSDNode *N, EVT VT, bool SExt) const |
Return if N is a True value when extended to VT. More... | |
| SDValue | SimplifySetCC (EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, bool foldBooleans, DAGCombinerInfo &DCI, const SDLoc &dl) const |
| Try to simplify a setcc built with the specified operands and cc. More... | |
| virtual SDValue | unwrapAddress (SDValue N) const |
| virtual bool | isGAPlusOffset (SDNode *N, const GlobalValue *&GA, int64_t &Offset) const |
| Returns true (and the GlobalValue and the offset) if the node is a GlobalAddress + offset. More... | |
| virtual bool | isDesirableToCommuteWithShift (const SDNode *N, CombineLevel Level) const |
| Return true if it is profitable to move this shift by a constant amount though its operand, adjusting any immediate operands as necessary to preserve semantics. More... | |
| virtual bool | shouldFoldShiftPairToMask (const SDNode *N, CombineLevel Level) const |
| Return true if it is profitable to fold a pair of shifts into a mask. More... | |
| virtual bool | isDesirableToCombineBuildVectorToShuffleTruncate (ArrayRef< int > ShuffleMask, EVT SrcVT, EVT TruncVT) const |
| virtual bool | isDesirableToTransformToIntegerOp (unsigned, EVT) const |
| Return true if it is profitable for dag combiner to transform a floating point op of specified opcode to a equivalent op of an integer type. More... | |
| virtual bool | IsDesirableToPromoteOp (SDValue, EVT &) const |
| This method query the target whether it is beneficial for dag combiner to promote the specified node. More... | |
| virtual bool | supportSwiftError () const |
| Return true if the target supports swifterror attribute. More... | |
| std::pair< SDValue, SDValue > | LowerCallTo (CallLoweringInfo &CLI) const |
| This function lowers an abstract call to a function into an actual call. More... | |
| virtual void | HandleByVal (CCState *, unsigned &, unsigned) const |
| Target-specific cleanup for formal ByVal parameters. More... | |
| virtual bool | isUsedByReturnOnly (SDNode *, SDValue &) const |
| Return true if result of the specified node is used by a return node only. More... | |
| virtual const char * | getClearCacheBuiltinName () const |
| Return the builtin name for the __builtin___clear_cache intrinsic Default is to invoke the clear cache library call. More... | |
| virtual EVT | getTypeForExtReturn (LLVMContext &Context, EVT VT, ISD::NodeType) const |
| Return the type that should be used to zero or sign extend a zeroext/signext integer return value. More... | |
| virtual bool | functionArgumentNeedsConsecutiveRegisters (Type *Ty, CallingConv::ID CallConv, bool isVarArg) const |
| For some targets, an LLVM struct type must be broken down into multiple simple types, but the calling convention specifies that the entire struct must be passed in a block of consecutive registers. More... | |
| virtual const MCPhysReg * | getScratchRegisters (CallingConv::ID CC) const |
| Returns a 0 terminated array of registers that can be safely used as scratch registers. More... | |
| virtual SDValue | prepareVolatileOrAtomicLoad (SDValue Chain, const SDLoc &DL, SelectionDAG &DAG) const |
| This callback is used to prepare for a volatile or atomic load. More... | |
| virtual MachineMemOperand::Flags | getMMOFlags (const Instruction &I) const |
| This callback is used to inspect load/store instructions and add target-specific MachineMemOperand flags to them. More... | |
| virtual void | LowerOperationWrapper (SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const |
| This callback is invoked by the type legalizer to legalize nodes with an illegal operand type but legal result types. More... | |
| virtual FastISel * | createFastISel (FunctionLoweringInfo &, const TargetLibraryInfo *) const |
| This method returns a target specific FastISel object, or null if the target does not support "fast" ISel. More... | |
| bool | verifyReturnAddressArgumentIsConstant (SDValue Op, SelectionDAG &DAG) const |
| virtual bool | ExpandInlineAsm (CallInst *) const |
| This hook allows the target to expand an inline asm call to be explicit llvm code if it wants to. More... | |
| virtual AsmOperandInfoVector | ParseConstraints (const DataLayout &DL, const TargetRegisterInfo *TRI, ImmutableCallSite CS) const |
| Split up the constraint string from the inline assembly value into the specific constraints and their prefixes, and also tie in the associated operand values. More... | |
| virtual ConstraintWeight | getMultipleConstraintMatchWeight (AsmOperandInfo &info, int maIndex) const |
| Examine constraint type and operand type and determine a weight value. More... | |
| virtual ConstraintWeight | getSingleConstraintMatchWeight (AsmOperandInfo &info, const char *constraint) const |
| Examine constraint string and operand type and determine a weight value. More... | |
| virtual void | ComputeConstraintToUse (AsmOperandInfo &OpInfo, SDValue Op, SelectionDAG *DAG=nullptr) const |
| Determines the constraint code and constraint type to use for the specific AsmOperandInfo, setting OpInfo.ConstraintCode and OpInfo.ConstraintType. More... | |
| virtual unsigned | getInlineAsmMemConstraint (StringRef ConstraintCode) const |
| virtual const char * | LowerXConstraint (EVT ConstraintVT) const |
| Try to replace an X constraint, which matches anything, with another that has more specific requirements based on the type of the corresponding operand. More... | |
| virtual void | LowerAsmOperandForConstraint (SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const |
| Lower the specified operand into the Ops vector. More... | |
| SDValue | BuildSDIV (SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization, SmallVectorImpl< SDNode *> &Created) const |
| Given an ISD::SDIV node expressing a divide by constant, return a DAG expression to select that will generate the same value by multiplying by a magic number. More... | |
| SDValue | BuildUDIV (SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization, SmallVectorImpl< SDNode *> &Created) const |
| Given an ISD::UDIV node expressing a divide by constant, return a DAG expression to select that will generate the same value by multiplying by a magic number. More... | |
| virtual SDValue | BuildSDIVPow2 (SDNode *N, const APInt &Divisor, SelectionDAG &DAG, SmallVectorImpl< SDNode *> &Created) const |
| Targets may override this function to provide custom SDIV lowering for power-of-2 denominators. More... | |
| virtual unsigned | combineRepeatedFPDivisors () const |
| Indicate whether this target prefers to combine FDIVs with the same divisor. More... | |
| bool | expandMUL_LOHI (unsigned Opcode, EVT VT, SDLoc dl, SDValue LHS, SDValue RHS, SmallVectorImpl< SDValue > &Result, EVT HiLoVT, SelectionDAG &DAG, MulExpansionKind Kind, SDValue LL=SDValue(), SDValue LH=SDValue(), SDValue RL=SDValue(), SDValue RH=SDValue()) const |
| Expand a MUL or [US]MUL_LOHI of n-bit values into two or four nodes, respectively, each computing an n/2-bit part of the result. More... | |
| bool | expandMUL (SDNode *N, SDValue &Lo, SDValue &Hi, EVT HiLoVT, SelectionDAG &DAG, MulExpansionKind Kind, SDValue LL=SDValue(), SDValue LH=SDValue(), SDValue RL=SDValue(), SDValue RH=SDValue()) const |
| Expand a MUL into two nodes. More... | |
| bool | expandFunnelShift (SDNode *N, SDValue &Result, SelectionDAG &DAG) const |
| Expand funnel shift. More... | |
| bool | expandROT (SDNode *N, SDValue &Result, SelectionDAG &DAG) const |
| Expand rotations. More... | |
| bool | expandFP_TO_SINT (SDNode *N, SDValue &Result, SelectionDAG &DAG) const |
| Expand float(f32) to SINT(i64) conversion. More... | |
| bool | expandFP_TO_UINT (SDNode *N, SDValue &Result, SelectionDAG &DAG) const |
| Expand float to UINT conversion. More... | |
| bool | expandUINT_TO_FP (SDNode *N, SDValue &Result, SelectionDAG &DAG) const |
| Expand UINT(i64) to double(f64) conversion. More... | |
| SDValue | expandFMINNUM_FMAXNUM (SDNode *N, SelectionDAG &DAG) const |
| Expand fminnum/fmaxnum into fminnum_ieee/fmaxnum_ieee with quieted inputs. More... | |
| bool | expandCTPOP (SDNode *N, SDValue &Result, SelectionDAG &DAG) const |
| Expand CTPOP nodes. More... | |
| bool | expandCTLZ (SDNode *N, SDValue &Result, SelectionDAG &DAG) const |
| Expand CTLZ/CTLZ_ZERO_UNDEF nodes. More... | |
| bool | expandCTTZ (SDNode *N, SDValue &Result, SelectionDAG &DAG) const |
| Expand CTTZ/CTTZ_ZERO_UNDEF nodes. More... | |
| bool | expandABS (SDNode *N, SDValue &Result, SelectionDAG &DAG) const |
| Expand ABS nodes. More... | |
| SDValue | scalarizeVectorLoad (LoadSDNode *LD, SelectionDAG &DAG) const |
| Turn load of vector type into a load of the individual elements. More... | |
| SDValue | scalarizeVectorStore (StoreSDNode *ST, SelectionDAG &DAG) const |
| std::pair< SDValue, SDValue > | expandUnalignedLoad (LoadSDNode *LD, SelectionDAG &DAG) const |
| Expands an unaligned load to 2 half-size loads for an integer, and possibly more for vectors. More... | |
| SDValue | expandUnalignedStore (StoreSDNode *ST, SelectionDAG &DAG) const |
| Expands an unaligned store to 2 half-size stores for integer values, and possibly more for vectors. More... | |
| SDValue | IncrementMemoryAddress (SDValue Addr, SDValue Mask, const SDLoc &DL, EVT DataVT, SelectionDAG &DAG, bool IsCompressedMemory) const |
Increments memory address Addr according to the type of the value DataVT that should be stored. More... | |
| SDValue | getVectorElementPointer (SelectionDAG &DAG, SDValue VecPtr, EVT VecVT, SDValue Index) const |
Get a pointer to vector element Idx located in memory for a vector of type VecVT starting at a base address of VecPtr. More... | |
| SDValue | expandAddSubSat (SDNode *Node, SelectionDAG &DAG) const |
| Method for building the DAG expansion of ISD::[US][ADD|SUB]SAT. More... | |
| SDValue | getExpandedFixedPointMultiplication (SDNode *Node, SelectionDAG &DAG) const |
| Method for building the DAG expansion of ISD::SMULFIX. More... | |
| virtual bool | useLoadStackGuardNode () const |
| If this function returns true, SelectionDAGBuilder emits a LOAD_STACK_GUARD node when it is lowering Intrinsic::stackprotector. More... | |
| virtual SDValue | emitStackGuardXorFP (SelectionDAG &DAG, SDValue Val, const SDLoc &DL) const |
| virtual SDValue | LowerToTLSEmulatedModel (const GlobalAddressSDNode *GA, SelectionDAG &DAG) const |
| Lower TLS global address SDNode for target independent emulated TLS model. More... | |
| virtual SDValue | expandIndirectJTBranch (const SDLoc &dl, SDValue Value, SDValue Addr, SelectionDAG &DAG) const |
| Expands target specific indirect branch for the case of JumpTable expanasion. More... | |
| SDValue | lowerCmpEqZeroToCtlzSrl (SDValue Op, SelectionDAG &DAG) const |
| Public Member Functions inherited from llvm::TargetLoweringBase | |
| virtual void | markLibCallAttributes (MachineFunction *MF, unsigned CC, ArgListTy &Args) const |
| TargetLoweringBase (const TargetMachine &TM) | |
| NOTE: The TargetMachine owns TLOF. More... | |
| TargetLoweringBase (const TargetLoweringBase &)=delete | |
| TargetLoweringBase & | operator= (const TargetLoweringBase &)=delete |
| virtual | ~TargetLoweringBase ()=default |
| const TargetMachine & | getTargetMachine () const |
| virtual bool | useSoftFloat () const |
| MVT | getPointerTy (const DataLayout &DL, uint32_t AS=0) const |
| Return the pointer type for the given address space, defaults to the pointer type from the data layout. More... | |
| MVT | getFrameIndexTy (const DataLayout &DL) const |
| Return the type for frame index, which is determined by the alloca address space specified through the data layout. More... | |
| EVT | getShiftAmountTy (EVT LHSTy, const DataLayout &DL, bool LegalTypes=true) const |
| virtual bool | reduceSelectOfFPConstantLoads (bool IsFPSetCC) const |
| Return true if it is profitable to convert a select of FP constants into a constant pool load whose address depends on the select condition. More... | |
| bool | hasMultipleConditionRegisters () const |
| Return true if multiple condition registers are available. More... | |
| bool | hasExtractBitsInsn () const |
| Return true if the target has BitExtract instructions. More... | |
| virtual bool | shouldExpandBuildVectorWithShuffles (EVT, unsigned DefinedValues) const |
| virtual bool | isIntDivCheap (EVT VT, AttributeList Attr) const |
| Return true if integer divide is usually cheaper than a sequence of several shifts, adds, and multiplies for this target. More... | |
| virtual bool | hasStandaloneRem (EVT VT) const |
| Return true if the target can handle a standalone remainder operation. More... | |
| int | getRecipEstimateSqrtEnabled (EVT VT, MachineFunction &MF) const |
| Return a ReciprocalEstimate enum value for a square root of the given type based on the function's attributes. More... | |
| int | getRecipEstimateDivEnabled (EVT VT, MachineFunction &MF) const |
| Return a ReciprocalEstimate enum value for a division of the given type based on the function's attributes. More... | |
| int | getSqrtRefinementSteps (EVT VT, MachineFunction &MF) const |
| Return the refinement step count for a square root of the given type based on the function's attributes. More... | |
| int | getDivRefinementSteps (EVT VT, MachineFunction &MF) const |
| Return the refinement step count for a division of the given type based on the function's attributes. More... | |
| bool | isSlowDivBypassed () const |
| Returns true if target has indicated at least one type should be bypassed. More... | |
| const DenseMap< unsigned int, unsigned int > & | getBypassSlowDivWidths () const |
| Returns map of slow types for division or remainder with corresponding fast types. More... | |
| bool | isJumpExpensive () const |
| Return true if Flow Control is an expensive operation that should be avoided. More... | |
| bool | isPredictableSelectExpensive () const |
| Return true if selects are only cheaper than branches if the branch is unlikely to be predicted right. More... | |
| virtual BranchProbability | getPredictableBranchThreshold () const |
| If a branch or a select condition is skewed in one direction by more than this factor, it is very likely to be predicted correctly. More... | |
| virtual bool | isStoreBitCastBeneficial (EVT StoreVT, EVT BitcastVT) const |
| Return true if the following transform is beneficial: (store (y (conv x)), y*)) -> (store x, (x*)) More... | |
| virtual bool | isCtlzFast () const |
| Return true if ctlz instruction is fast. More... | |
| virtual bool | isMultiStoresCheaperThanBitsMerge (EVT LTy, EVT HTy) const |
| Return true if it is cheaper to split the store of a merged int val from a pair of smaller values into multiple stores. More... | |
| virtual bool | isMaskAndCmp0FoldingBeneficial (const Instruction &AndI) const |
| Return if the target supports combining a chain like: More... | |
| virtual bool | convertSetCCLogicToBitwiseLogic (EVT VT) const |
| Use bitwise logic to make pairs of compares more efficient. More... | |
| virtual MVT | hasFastEqualityCompare (unsigned NumBits) const |
| Return the preferred operand type if the target has a quick way to compare integer values of the given size. More... | |
| virtual bool | hasAndNotCompare (SDValue Y) const |
| Return true if the target should transform: (X & Y) == Y —> (~X & Y) == 0 (X & Y) != Y —> (~X & Y) != 0. More... | |
| virtual bool | hasAndNot (SDValue X) const |
| Return true if the target has a bitwise and-not operation: X = ~A & B This can be used to simplify select or other instructions. More... | |
| virtual bool | preferShiftsToClearExtremeBits (SDValue X) const |
| There are two ways to clear extreme bits (either low or high): Mask: x & (-1 << y) (the instcombine canonical form) Shifts: x >> y << y Return true if the variant with 2 shifts is preferred. More... | |
| virtual bool | shouldTransformSignedTruncationCheck (EVT XVT, unsigned KeptBits) const |
| Should we tranform the IR-optimal check for whether given truncation down into KeptBits would be truncating or not: (add x, (1 << (KeptBits-1))) srccond (1 << KeptBits) Into it's more traditional form: ((x << C) a>> C) dstcond x Return true if we should transform. More... | |
| bool | enableExtLdPromotion () const |
| Return true if the target wants to use the optimization that turns ext(promotableInst1(...(promotableInstN(load)))) into promotedInst1(...(promotedInstN(ext(load)))). More... | |
| virtual bool | canCombineStoreAndExtract (Type *VectorTy, Value *Idx, unsigned &Cost) const |
| Return true if the target can combine store(extractelement VectorTy, Idx). More... | |
| virtual bool | shouldSplatInsEltVarIndex (EVT) const |
| Return true if inserting a scalar into a variable element of an undef vector is more efficiently handled by splatting the scalar instead. More... | |
| bool | hasFloatingPointExceptions () const |
| Return true if target supports floating point exceptions. More... | |
| virtual MVT::SimpleValueType | getCmpLibcallReturnType () const |
| Return the ValueType for comparison libcalls. More... | |
| BooleanContent | getBooleanContents (bool isVec, bool isFloat) const |
| For targets without i1 registers, this gives the nature of the high-bits of boolean values held in types wider than i1. More... | |
| BooleanContent | getBooleanContents (EVT Type) const |
| Sched::Preference | getSchedulingPreference () const |
| Return target scheduling preference. More... | |
| virtual Sched::Preference | getSchedulingPreference (SDNode *) const |
| Some scheduler, e.g. More... | |
| virtual const TargetRegisterClass * | getRegClassFor (MVT VT) const |
| Return the register class that should be used for the specified value type. More... | |
| virtual const TargetRegisterClass * | getRepRegClassFor (MVT VT) const |
| Return the 'representative' register class for the specified value type. More... | |
| virtual uint8_t | getRepRegClassCostFor (MVT VT) const |
| Return the cost of the 'representative' register class for the specified value type. More... | |
| bool | isTypeLegal (EVT VT) const |
| Return true if the target has native support for the specified value type. More... | |
| const ValueTypeActionImpl & | getValueTypeActions () const |
| LegalizeTypeAction | getTypeAction (LLVMContext &Context, EVT VT) const |
| Return how we should legalize values of this type, either it is already legal (return 'Legal') or we need to promote it to a larger type (return 'Promote'), or we need to expand it into multiple registers of smaller integer type (return 'Expand'). More... | |
| LegalizeTypeAction | getTypeAction (MVT VT) const |
| EVT | getTypeToTransformTo (LLVMContext &Context, EVT VT) const |
| For types supported by the target, this is an identity function. More... | |
| EVT | getTypeToExpandTo (LLVMContext &Context, EVT VT) const |
| For types supported by the target, this is an identity function. More... | |
| unsigned | getVectorTypeBreakdown (LLVMContext &Context, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const |
| Vector types are broken down into some number of legal first class types. More... | |
| virtual bool | canOpTrap (unsigned Op, EVT VT) const |
| Returns true if the operation can trap for the value type. More... | |
| virtual bool | isVectorClearMaskLegal (ArrayRef< int >, EVT) const |
| Similar to isShuffleMaskLegal. More... | |
| LegalizeAction | getOperationAction (unsigned Op, EVT VT) const |
| Return how this operation should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it. More... | |
| virtual bool | isSupportedFixedPointOperation (unsigned Op, EVT VT, unsigned Scale) const |
| Custom method defined by each target to indicate if an operation which may require a scale is supported natively by the target. More... | |
| LegalizeAction | getFixedPointOperationAction (unsigned Op, EVT VT, unsigned Scale) const |
| Some fixed point operations may be natively supported by the target but only for specific scales. More... | |
| LegalizeAction | getStrictFPOperationAction (unsigned Op, EVT VT) const |
| bool | isOperationLegalOrCustom (unsigned Op, EVT VT) const |
| Return true if the specified operation is legal on this target or can be made legal with custom lowering. More... | |
| bool | isOperationLegalOrPromote (unsigned Op, EVT VT) const |
| Return true if the specified operation is legal on this target or can be made legal using promotion. More... | |
| bool | isOperationLegalOrCustomOrPromote (unsigned Op, EVT VT) const |
| Return true if the specified operation is legal on this target or can be made legal with custom lowering or using promotion. More... | |
| bool | isOperationCustom (unsigned Op, EVT VT) const |
| Return true if the operation uses custom lowering, regardless of whether the type is legal or not. More... | |
| virtual bool | areJTsAllowed (const Function *Fn) const |
| Return true if lowering to a jump table is allowed. More... | |
| bool | rangeFitsInWord (const APInt &Low, const APInt &High, const DataLayout &DL) const |
| Check whether the range [Low,High] fits in a machine word. More... | |
| virtual bool | isSuitableForJumpTable (const SwitchInst *SI, uint64_t NumCases, uint64_t Range) const |
Return true if lowering to a jump table is suitable for a set of case clusters which may contain NumCases cases, Range range of values. More... | |
| bool | isSuitableForBitTests (unsigned NumDests, unsigned NumCmps, const APInt &Low, const APInt &High, const DataLayout &DL) const |
Return true if lowering to a bit test is suitable for a set of case clusters which contains NumDests unique destinations, Low and High as its lowest and highest case values, and expects NumCmps case value comparisons. More... | |
| bool | isOperationExpand (unsigned Op, EVT VT) const |
| Return true if the specified operation is illegal on this target or unlikely to be made legal with custom lowering. More... | |
| bool | isOperationLegal (unsigned Op, EVT VT) const |
| Return true if the specified operation is legal on this target. More... | |
| LegalizeAction | getLoadExtAction (unsigned ExtType, EVT ValVT, EVT MemVT) const |
| Return how this load with extension should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it. More... | |
| bool | isLoadExtLegal (unsigned ExtType, EVT ValVT, EVT MemVT) const |
| Return true if the specified load with extension is legal on this target. More... | |
| bool | isLoadExtLegalOrCustom (unsigned ExtType, EVT ValVT, EVT MemVT) const |
| Return true if the specified load with extension is legal or custom on this target. More... | |
| LegalizeAction | getTruncStoreAction (EVT ValVT, EVT MemVT) const |
| Return how this store with truncation should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it. More... | |
| bool | isTruncStoreLegal (EVT ValVT, EVT MemVT) const |
| Return true if the specified store with truncation is legal on this target. More... | |
| bool | isTruncStoreLegalOrCustom (EVT ValVT, EVT MemVT) const |
| Return true if the specified store with truncation has solution on this target. More... | |
| LegalizeAction | getIndexedLoadAction (unsigned IdxMode, MVT VT) const |
| Return how the indexed load should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it. More... | |
| bool | isIndexedLoadLegal (unsigned IdxMode, EVT VT) const |
| Return true if the specified indexed load is legal on this target. More... | |
| LegalizeAction | getIndexedStoreAction (unsigned IdxMode, MVT VT) const |
| Return how the indexed store should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it. More... | |
| bool | isIndexedStoreLegal (unsigned IdxMode, EVT VT) const |
| Return true if the specified indexed load is legal on this target. More... | |
| LegalizeAction | getCondCodeAction (ISD::CondCode CC, MVT VT) const |
| Return how the condition code should be treated: either it is legal, needs to be expanded to some other code sequence, or the target has a custom expander for it. More... | |
| bool | isCondCodeLegal (ISD::CondCode CC, MVT VT) const |
| Return true if the specified condition code is legal on this target. More... | |
| bool | isCondCodeLegalOrCustom (ISD::CondCode CC, MVT VT) const |
| Return true if the specified condition code is legal or custom on this target. More... | |
| MVT | getTypeToPromoteTo (unsigned Op, MVT VT) const |
| If the action for this operation is to promote, this method returns the ValueType to promote to. More... | |
| EVT | getValueType (const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const |
| Return the EVT corresponding to this LLVM type. More... | |
| MVT | getSimpleValueType (const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const |
| Return the MVT corresponding to this LLVM type. See getValueType. More... | |
| virtual unsigned | getByValTypeAlignment (Type *Ty, const DataLayout &DL) const |
| Return the desired alignment for ByVal or InAlloca aggregate function arguments in the caller parameter area. More... | |
| MVT | getRegisterType (MVT VT) const |
| Return the type of registers that this ValueType will eventually require. More... | |
| MVT | getRegisterType (LLVMContext &Context, EVT VT) const |
| Return the type of registers that this ValueType will eventually require. More... | |
| unsigned | getNumRegisters (LLVMContext &Context, EVT VT) const |
| Return the number of registers that this ValueType will eventually require. More... | |
| virtual unsigned | getABIAlignmentForCallingConv (Type *ArgTy, DataLayout DL) const |
| Certain targets have context senstive alignment requirements, where one type has the alignment requirement of another type. More... | |
| bool | hasBigEndianPartOrdering (EVT VT, const DataLayout &DL) const |
| When splitting a value of the specified type into parts, does the Lo or Hi part come first? This usually follows the endianness, except for ppcf128, where the Hi part always comes first. More... | |
| bool | hasTargetDAGCombine (ISD::NodeType NT) const |
| If true, the target has custom DAG combine transformations that it can perform for the specified node. More... | |
| unsigned | getGatherAllAliasesMaxDepth () const |
| virtual unsigned | getVaListSizeInBits (const DataLayout &DL) const |
| Returns the size of the platform's va_list object. More... | |
| unsigned | getMaxStoresPerMemset (bool OptSize) const |
| Get maximum # of store operations permitted for llvm.memset. More... | |
| unsigned | getMaxStoresPerMemcpy (bool OptSize) const |
| Get maximum # of store operations permitted for llvm.memcpy. More... | |
| virtual unsigned | getMaxGluedStoresPerMemcpy () const |
| Get maximum # of store operations to be glued together. More... | |
| unsigned | getMaxExpandSizeMemcmp (bool OptSize) const |
| Get maximum # of load operations permitted for memcmp. More... | |
| virtual unsigned | getMemcmpEqZeroLoadsPerBlock () const |
| For memcmp expansion when the memcmp result is only compared equal or not-equal to 0, allow up to this number of load pairs per block. More... | |
| unsigned | getMaxStoresPerMemmove (bool OptSize) const |
| Get maximum # of store operations permitted for llvm.memmove. More... | |
| bool | allowsMemoryAccess (LLVMContext &Context, const DataLayout &DL, EVT VT, unsigned AddrSpace=0, unsigned Alignment=1, bool *Fast=nullptr) const |
| Return true if the target supports a memory access of this type for the given address space and alignment. More... | |
| virtual bool | isSafeMemOpType (MVT) const |
| Returns true if it's safe to use load / store of the specified type to expand memcpy / memset inline. More... | |
| bool | usesUnderscoreSetJmp () const |
| Determine if we should use _setjmp or setjmp to implement llvm.setjmp. More... | |
| bool | usesUnderscoreLongJmp () const |
| Determine if we should use _longjmp or longjmp to implement llvm.longjmp. More... | |
| virtual unsigned | getMinimumJumpTableEntries () const |
| Return lower limit for number of blocks in a jump table. More... | |
| unsigned | getMinimumJumpTableDensity (bool OptForSize) const |
| Return lower limit of the density in a jump table. More... | |
| unsigned | getMaximumJumpTableSize () const |
| Return upper limit for number of entries in a jump table. More... | |
| virtual bool | isJumpTableRelative () const |
| unsigned | getStackPointerRegisterToSaveRestore () const |
| If a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save and restore. More... | |
| virtual unsigned | getExceptionPointerRegister (const Constant *PersonalityFn) const |
| If a physical register, this returns the register that receives the exception address on entry to an EH pad. More... | |
| virtual unsigned | getExceptionSelectorRegister (const Constant *PersonalityFn) const |
| If a physical register, this returns the register that receives the exception typeid on entry to a landing pad. More... | |
| virtual bool | needsFixedCatchObjects () const |
| unsigned | getJumpBufSize () const |
| Returns the target's jmp_buf size in bytes (if never set, the default is 200) More... | |
| unsigned | getJumpBufAlignment () const |
| Returns the target's jmp_buf alignment in bytes (if never set, the default is 0) More... | |
| unsigned | getMinStackArgumentAlignment () const |
| Return the minimum stack alignment of an argument. More... | |
| unsigned | getMinFunctionAlignment () const |
| Return the minimum function alignment. More... | |
| unsigned | getPrefFunctionAlignment () const |
| Return the preferred function alignment. More... | |
| virtual unsigned | getPrefLoopAlignment (MachineLoop *ML=nullptr) const |
| Return the preferred loop alignment. More... | |
| virtual bool | alignLoopsWithOptSize () const |
| Should loops be aligned even when the function is marked OptSize (but not MinSize). More... | |
| virtual Value * | getIRStackGuard (IRBuilder<> &IRB) const |
| If the target has a standard location for the stack protector guard, returns the address of that location. More... | |
| virtual void | insertSSPDeclarations (Module &M) const |
| Inserts necessary declarations for SSP (stack protection) purpose. More... | |
| virtual Value * | getSDagStackGuard (const Module &M) const |
| Return the variable that's previously inserted by insertSSPDeclarations, if any, otherwise return nullptr. More... | |
| virtual bool | useStackGuardXorFP () const |
| If this function returns true, stack protection checks should XOR the frame pointer (or whichever pointer is used to address locals) into the stack guard value before checking it. More... | |
| virtual Value * | getSSPStackGuardCheck (const Module &M) const |
| If the target has a standard stack protection check function that performs validation and error handling, returns the function. More... | |
| virtual Value * | getSafeStackPointerLocation (IRBuilder<> &IRB) const |
| Returns the target-specific address of the unsafe stack pointer. More... | |
| virtual StringRef | getStackProbeSymbolName (MachineFunction &MF) const |
| Returns the name of the symbol used to emit stack probes or the empty string if not applicable. More... | |
| virtual bool | shouldAlignPointerArgs (CallInst *, unsigned &, unsigned &) const |
| Return true if the pointer arguments to CI should be aligned by aligning the object whose address is being passed. More... | |
| virtual void | emitAtomicCmpXchgNoStoreLLBalance (IRBuilder<> &Builder) const |
| virtual bool | shouldExpandAtomicStoreInIR (StoreInst *SI) const |
| Returns true if the given (atomic) store should be expanded by the IR-level AtomicExpand pass into an "atomic xchg" which ignores its input. More... | |
| virtual bool | shouldSignExtendTypeInLibCall (EVT Type, bool IsSigned) const |
| Returns true if arguments should be sign-extended in lib calls. More... | |
| virtual AtomicExpansionKind | shouldExpandAtomicLoadInIR (LoadInst *LI) const |
| Returns how the given (atomic) load should be expanded by the IR-level AtomicExpand pass. More... | |
| virtual AtomicExpansionKind | shouldExpandAtomicCmpXchgInIR (AtomicCmpXchgInst *AI) const |
| Returns how the given atomic cmpxchg should be expanded by the IR-level AtomicExpand pass. More... | |
| virtual LoadInst * | lowerIdempotentRMWIntoFencedLoad (AtomicRMWInst *RMWI) const |
| On some platforms, an AtomicRMW that never actually modifies the value (such as fetch_add of 0) can be turned into a fence followed by an atomic load. More... | |
| virtual ISD::NodeType | getExtendForAtomicOps () const |
| Returns how the platform's atomic operations are extended (ZERO_EXTEND, SIGN_EXTEND, or ANY_EXTEND). More... | |
| virtual bool | shouldNormalizeToSelectSequence (LLVMContext &Context, EVT VT) const |
| Returns true if we should normalize select(N0&N1, X, Y) => select(N0, select(N1, X, Y), Y) and select(N0|N1, X, Y) => select(N0, select(N1, X, Y, Y)) if it is likely that it saves us from materializing N0 and N1 in an integer register. More... | |
| virtual bool | convertSelectOfConstantsToMath (EVT VT) const |
| Return true if a select of constants (select Cond, C1, C2) should be transformed into simple math ops with the condition value. More... | |
| virtual bool | decomposeMulByConstant (EVT VT, SDValue C) const |
| Return true if it is profitable to transform an integer multiplication-by-constant into simpler operations like shifts and adds. More... | |
| virtual bool | shouldUseStrictFP_TO_INT (EVT FpVT, EVT IntVT, bool IsSigned) const |
| Return true if it is more correct/profitable to use strict FP_TO_INT conversion operations - canonicalizing the FP source value instead of converting all cases and then selecting based on value. More... | |
| virtual int | getScalingFactorCost (const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS=0) const |
| Return the cost of the scaling factor used in the addressing mode represented by AM for this target, for a load/store of the specified type. More... | |
| virtual bool | isLegalICmpImmediate (int64_t) const |
| Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructions which can compare a register against the immediate without having to materialize the immediate into a register. More... | |
| virtual bool | isLegalAddImmediate (int64_t) const |
| Return true if the specified immediate is legal add immediate, that is the target has add instructions which can add a register with the immediate without having to materialize the immediate into a register. More... | |
| virtual bool | isLegalStoreImmediate (int64_t Value) const |
| Return true if the specified immediate is legal for the value input of a store instruction. More... | |
| virtual bool | isVectorShiftByScalarCheap (Type *Ty) const |
| Return true if it's significantly cheaper to shift a vector by a uniform scalar than by an amount which will vary across each lane. More... | |
| virtual bool | isCommutativeBinOp (unsigned Opcode) const |
| Returns true if the opcode is a commutative binary operation. More... | |
| virtual bool | allowTruncateForTailCall (Type *FromTy, Type *ToTy) const |
| Return true if a truncation from FromTy to ToTy is permitted when deciding whether a call is in tail position. More... | |
| virtual bool | isProfitableToHoist (Instruction *I) const |
| bool | isExtFree (const Instruction *I) const |
Return true if the extension represented by I is free. More... | |
| bool | isExtLoad (const LoadInst *Load, const Instruction *Ext, const DataLayout &DL) const |
Return true if Load and Ext can form an ExtLoad. More... | |
| virtual bool | isSExtCheaperThanZExt (EVT FromTy, EVT ToTy) const |
| Return true if sign-extension from FromTy to ToTy is cheaper than zero-extension. More... | |
| virtual bool | hasPairedLoad (EVT, unsigned &) const |
| Return true if the target supplies and combines to a paired load two loaded values of type LoadedType next to each other in memory. More... | |
| virtual bool | hasVectorBlend () const |
| Return true if the target has a vector blend instruction. More... | |
| virtual unsigned | getMaxSupportedInterleaveFactor () const |
| Get the maximum supported factor for interleaved memory accesses. More... | |
| virtual bool | lowerInterleavedLoad (LoadInst *LI, ArrayRef< ShuffleVectorInst *> Shuffles, ArrayRef< unsigned > Indices, unsigned Factor) const |
| Lower an interleaved load to target specific intrinsics. More... | |
| virtual bool | lowerInterleavedStore (StoreInst *SI, ShuffleVectorInst *SVI, unsigned Factor) const |
| Lower an interleaved store to target specific intrinsics. More... | |
| virtual bool | isFPExtFree (EVT DestVT, EVT SrcVT) const |
| Return true if an fpext operation is free (for instance, because single-precision floating-point numbers are implicitly extended to double-precision). More... | |
| virtual bool | isVectorLoadExtDesirable (SDValue ExtVal) const |
| Return true if folding a vector load into ExtVal (a sign, zero, or any extend node) is profitable. More... | |
| virtual bool | isExtractSubvectorCheap (EVT ResVT, EVT SrcVT, unsigned Index) const |
| Return true if EXTRACT_SUBVECTOR is cheap for extracting this result type from this source type with this index. More... | |
| virtual bool | shouldScalarizeBinop (SDValue VecOp) const |
| Try to convert an extract element of a vector binary operation into an extract element followed by a scalar operation. More... | |
| virtual bool | shouldConsiderGEPOffsetSplit () const |
| void | setLibcallName (RTLIB::Libcall Call, const char *Name) |
| Rename the default libcall routine name for the specified libcall. More... | |
| const char * | getLibcallName (RTLIB::Libcall Call) const |
| Get the libcall routine name for the specified libcall. More... | |
| void | setCmpLibcallCC (RTLIB::Libcall Call, ISD::CondCode CC) |
| Override the default CondCode to be used to test the result of the comparison libcall against zero. More... | |
| ISD::CondCode | getCmpLibcallCC (RTLIB::Libcall Call) const |
| Get the CondCode that's to be used to test the result of the comparison libcall against zero. More... | |
| void | setLibcallCallingConv (RTLIB::Libcall Call, CallingConv::ID CC) |
| Set the CallingConv that should be used for the specified libcall. More... | |
| CallingConv::ID | getLibcallCallingConv (RTLIB::Libcall Call) const |
| Get the CallingConv that should be used for the specified libcall. More... | |
| int | InstructionOpcodeToISD (unsigned Opcode) const |
| Get the ISD node that corresponds to the Instruction class opcode. More... | |
| std::pair< int, MVT > | getTypeLegalizationCost (const DataLayout &DL, Type *Ty) const |
| Estimate the cost of type-legalization and the legalized type. More... | |
| unsigned | getMaxAtomicSizeInBitsSupported () const |
| Returns the maximum atomic operation size (in bits) supported by the backend. More... | |
| unsigned | getMinCmpXchgSizeInBits () const |
| Returns the size of the smallest cmpxchg or ll/sc instruction the backend supports. More... | |
| bool | supportsUnalignedAtomics () const |
| Whether the target supports unaligned atomic operations. More... | |
| virtual bool | shouldInsertFencesForAtomic (const Instruction *I) const |
| Whether AtomicExpandPass should automatically insert fences and reduce ordering for this atomic. More... | |
| virtual Value * | emitLoadLinked (IRBuilder<> &Builder, Value *Addr, AtomicOrdering Ord) const |
| Perform a load-linked operation on Addr, returning a "Value *" with the corresponding pointee type. More... | |
| virtual Value * | emitStoreConditional (IRBuilder<> &Builder, Value *Val, Value *Addr, AtomicOrdering Ord) const |
| Perform a store-conditional operation to Addr. More... | |
| virtual Value * | emitMaskedAtomicRMWIntrinsic (IRBuilder<> &Builder, AtomicRMWInst *AI, Value *AlignedAddr, Value *Incr, Value *Mask, Value *ShiftAmt, AtomicOrdering Ord) const |
| Perform a masked atomicrmw using a target-specific intrinsic. More... | |
| virtual Value * | emitMaskedAtomicCmpXchgIntrinsic (IRBuilder<> &Builder, AtomicCmpXchgInst *CI, Value *AlignedAddr, Value *CmpVal, Value *NewVal, Value *Mask, AtomicOrdering Ord) const |
| Perform a masked cmpxchg using a target-specific intrinsic. More... | |
| virtual Instruction * | emitLeadingFence (IRBuilder<> &Builder, Instruction *Inst, AtomicOrdering Ord) const |
| Inserts in the IR a target-specific intrinsic specifying a fence. More... | |
| virtual Instruction * | emitTrailingFence (IRBuilder<> &Builder, Instruction *Inst, AtomicOrdering Ord) const |
Additional Inherited Members | |
| Public Types inherited from llvm::AMDGPUTargetLowering | |
| enum | ImplicitParameter { FIRST_IMPLICIT, GRID_DIM = FIRST_IMPLICIT, GRID_OFFSET } |
| Public Types inherited from llvm::TargetLowering | |
| enum | ConstraintType { C_Register, C_RegisterClass, C_Memory, C_Other, C_Unknown } |
| enum | ConstraintWeight { CW_Invalid = -1, CW_Okay = 0, CW_Good = 1, CW_Better = 2, CW_Best = 3, CW_SpecificReg = CW_Okay, CW_Register = CW_Good, CW_Memory = CW_Better, CW_Constant = CW_Best, CW_Default = CW_Okay } |
| using | AsmOperandInfoVector = std::vector< AsmOperandInfo > |
| Public Types inherited from llvm::TargetLoweringBase | |
| enum | LegalizeAction : uint8_t { Legal, Promote, Expand, LibCall, Custom } |
| This enum indicates whether operations are valid for a target, and if not, what action should be used to make them valid. More... | |
| enum | LegalizeTypeAction : uint8_t { TypeLegal, TypePromoteInteger, TypeExpandInteger, TypeSoftenFloat, TypeExpandFloat, TypeScalarizeVector, TypeSplitVector, TypeWidenVector, TypePromoteFloat } |
| This enum indicates whether a types are legal for a target, and if not, what action should be used to make them valid. More... | |
| enum | BooleanContent { UndefinedBooleanContent, ZeroOrOneBooleanContent, ZeroOrNegativeOneBooleanContent } |
| Enum that describes how the target represents true/false values. More... | |
| enum | SelectSupportKind { ScalarValSelect, ScalarCondVectorVal, VectorMaskSelect } |
| Enum that describes what type of support for selects the target has. More... | |
| enum | AtomicExpansionKind { AtomicExpansionKind::None, AtomicExpansionKind::LLSC, AtomicExpansionKind::LLOnly, AtomicExpansionKind::CmpXChg, AtomicExpansionKind::MaskedIntrinsic } |
| Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all. More... | |
| enum | MulExpansionKind { MulExpansionKind::Always, MulExpansionKind::OnlyLegalOrCustom } |
| Enum that specifies when a multiplication should be expanded. More... | |
| enum | ReciprocalEstimate : int { Unspecified = -1, Disabled = 0, Enabled = 1 } |
| Reciprocal estimate status values used by the functions below. More... | |
| using | LegalizeKind = std::pair< LegalizeTypeAction, EVT > |
| LegalizeKind holds the legalization kind that needs to happen to EVT in order to type-legalize it. More... | |
| using | ArgListTy = std::vector< ArgListEntry > |
| Static Public Member Functions inherited from llvm::AMDGPUTargetLowering | |
| static unsigned | numBitsUnsigned (SDValue Op, SelectionDAG &DAG) |
| static unsigned | numBitsSigned (SDValue Op, SelectionDAG &DAG) |
| static SDValue | stripBitcast (SDValue Val) |
| static bool | allUsesHaveSourceMods (const SDNode *N, unsigned CostThreshold=4) |
| static CCAssignFn * | CCAssignFnForCall (CallingConv::ID CC, bool IsVarArg) |
| Selects the correct CCAssignFn for a given CallingConvention value. More... | |
| static CCAssignFn * | CCAssignFnForReturn (CallingConv::ID CC, bool IsVarArg) |
| Static Public Member Functions inherited from llvm::TargetLoweringBase | |
| static ISD::NodeType | getExtendForContent (BooleanContent Content) |
| Protected Member Functions inherited from llvm::AMDGPUTargetLowering | |
| SDValue | LowerEXTRACT_SUBVECTOR (SDValue Op, SelectionDAG &DAG) const |
| SDValue | LowerCONCAT_VECTORS (SDValue Op, SelectionDAG &DAG) const |
| SDValue | LowerFREM (SDValue Op, SelectionDAG &DAG) const |
| Split a vector store into multiple scalar stores. More... | |
| SDValue | LowerFCEIL (SDValue Op, SelectionDAG &DAG) const |
| SDValue | LowerFTRUNC (SDValue Op, SelectionDAG &DAG) const |
| SDValue | LowerFRINT (SDValue Op, SelectionDAG &DAG) const |
| SDValue | LowerFNEARBYINT (SDValue Op, SelectionDAG &DAG) const |
| SDValue | LowerFROUND32_16 (SDValue Op, SelectionDAG &DAG) const |
| SDValue | LowerFROUND64 (SDValue Op, SelectionDAG &DAG) const |
| SDValue | LowerFROUND (SDValue Op, SelectionDAG &DAG) const |
| SDValue | LowerFFLOOR (SDValue Op, SelectionDAG &DAG) const |
| SDValue | LowerFLOG (SDValue Op, SelectionDAG &DAG, double Log2BaseInverted) const |
| SDValue | lowerFEXP (SDValue Op, SelectionDAG &DAG) const |
| SDValue | LowerCTLZ_CTTZ (SDValue Op, SelectionDAG &DAG) const |
| SDValue | LowerINT_TO_FP32 (SDValue Op, SelectionDAG &DAG, bool Signed) const |
| SDValue | LowerINT_TO_FP64 (SDValue Op, SelectionDAG &DAG, bool Signed) const |
| SDValue | LowerUINT_TO_FP (SDValue Op, SelectionDAG &DAG) const |
| SDValue | LowerSINT_TO_FP (SDValue Op, SelectionDAG &DAG) const |
| SDValue | LowerFP64_TO_INT (SDValue Op, SelectionDAG &DAG, bool Signed) const |
| SDValue | LowerFP_TO_FP16 (SDValue Op, SelectionDAG &DAG) const |
| SDValue | LowerFP_TO_UINT (SDValue Op, SelectionDAG &DAG) const |
| SDValue | LowerFP_TO_SINT (SDValue Op, SelectionDAG &DAG) const |
| SDValue | LowerSIGN_EXTEND_INREG (SDValue Op, SelectionDAG &DAG) const |
| bool | shouldCombineMemoryType (EVT VT) const |
| SDValue | performLoadCombine (SDNode *N, DAGCombinerInfo &DCI) const |
| SDValue | performStoreCombine (SDNode *N, DAGCombinerInfo &DCI) const |
| SDValue | performAssertSZExtCombine (SDNode *N, DAGCombinerInfo &DCI) const |
| SDValue | splitBinaryBitConstantOpImpl (DAGCombinerInfo &DCI, const SDLoc &SL, unsigned Opc, SDValue LHS, uint32_t ValLo, uint32_t ValHi) const |
Split the 64-bit value LHS into two 32-bit components, and perform the binary operation Opc to it with the corresponding constant operands. More... | |
| SDValue | performShlCombine (SDNode *N, DAGCombinerInfo &DCI) const |
| SDValue | performSraCombine (SDNode *N, DAGCombinerInfo &DCI) const |
| SDValue | performSrlCombine (SDNode *N, DAGCombinerInfo &DCI) const |
| SDValue | performTruncateCombine (SDNode *N, DAGCombinerInfo &DCI) const |
| SDValue | performMulCombine (SDNode *N, DAGCombinerInfo &DCI) const |
| SDValue | performMulhsCombine (SDNode *N, DAGCombinerInfo &DCI) const |
| SDValue | performMulhuCombine (SDNode *N, DAGCombinerInfo &DCI) const |
| SDValue | performMulLoHi24Combine (SDNode *N, DAGCombinerInfo &DCI) const |
| SDValue | performCtlz_CttzCombine (const SDLoc &SL, SDValue Cond, SDValue LHS, SDValue RHS, DAGCombinerInfo &DCI) const |
| SDValue | performSelectCombine (SDNode *N, DAGCombinerInfo &DCI) const |
| bool | isConstantCostlierToNegate (SDValue N) const |
| SDValue | performFNegCombine (SDNode *N, DAGCombinerInfo &DCI) const |
| SDValue | performFAbsCombine (SDNode *N, DAGCombinerInfo &DCI) const |
| SDValue | performRcpCombine (SDNode *N, DAGCombinerInfo &DCI) const |
| std::pair< SDValue, SDValue > | split64BitValue (SDValue Op, SelectionDAG &DAG) const |
| Return 64-bit value Op as two 32-bit integers. More... | |
| SDValue | getLoHalf64 (SDValue Op, SelectionDAG &DAG) const |
| SDValue | getHiHalf64 (SDValue Op, SelectionDAG &DAG) const |
| SDValue | SplitVectorLoad (SDValue Op, SelectionDAG &DAG) const |
| Split a vector load into 2 loads of half the vector. More... | |
| SDValue | SplitVectorStore (SDValue Op, SelectionDAG &DAG) const |
| Split a vector store into 2 stores of half the vector. More... | |
| SDValue | LowerSTORE (SDValue Op, SelectionDAG &DAG) const |
| SDValue | LowerSDIVREM (SDValue Op, SelectionDAG &DAG) const |
| SDValue | LowerUDIVREM (SDValue Op, SelectionDAG &DAG) const |
| SDValue | LowerDIVREM24 (SDValue Op, SelectionDAG &DAG, bool sign) const |
| void | LowerUDIVREM64 (SDValue Op, SelectionDAG &DAG, SmallVectorImpl< SDValue > &Results) const |
| void | analyzeFormalArgumentsCompute (CCState &State, const SmallVectorImpl< ISD::InputArg > &Ins) const |
| The SelectionDAGBuilder will automatically promote function arguments with illegal types. More... | |
| Protected Member Functions inherited from llvm::TargetLoweringBase | |
| void | initActions () |
| Initialize all of the actions to default values. More... | |
| Value * | getDefaultSafeStackPointerLocation (IRBuilder<> &IRB, bool UseTLS) const |
| void | setBooleanContents (BooleanContent Ty) |
| Specify how the target extends the result of integer and floating point boolean values from i1 to a wider type. More... | |
| void | setBooleanContents (BooleanContent IntTy, BooleanContent FloatTy) |
| Specify how the target extends the result of integer and floating point boolean values from i1 to a wider type. More... | |
| void | setBooleanVectorContents (BooleanContent Ty) |
| Specify how the target extends the result of a vector boolean value from a vector of i1 to a wider type. More... | |
| void | setSchedulingPreference (Sched::Preference Pref) |
| Specify the target scheduling preference. More... | |
| void | setUseUnderscoreSetJmp (bool Val) |
| Indicate whether this target prefers to use _setjmp to implement llvm.setjmp or the version without _. More... | |
| void | setUseUnderscoreLongJmp (bool Val) |
| Indicate whether this target prefers to use _longjmp to implement llvm.longjmp or the version without _. More... | |
| void | setMinimumJumpTableEntries (unsigned Val) |
| Indicate the minimum number of blocks to generate jump tables. More... | |
| void | setMaximumJumpTableSize (unsigned) |
| Indicate the maximum number of entries in jump tables. More... | |
| void | setStackPointerRegisterToSaveRestore (unsigned R) |
| If set to a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save and restore. More... | |
| void | setHasMultipleConditionRegisters (bool hasManyRegs=true) |
| Tells the code generator that the target has multiple (allocatable) condition registers that can be used to store the results of comparisons for use by selects and conditional branches. More... | |
| void | setHasExtractBitsInsn (bool hasExtractInsn=true) |
| Tells the code generator that the target has BitExtract instructions. More... | |
| void | setJumpIsExpensive (bool isExpensive=true) |
| Tells the code generator not to expand logic operations on comparison predicates into separate sequences that increase the amount of flow control. More... | |
| void | setHasFloatingPointExceptions (bool FPExceptions=true) |
| Tells the code generator that this target supports floating point exceptions and cares about preserving floating point exception behavior. More... | |
| void | addBypassSlowDiv (unsigned int SlowBitWidth, unsigned int FastBitWidth) |
| Tells the code generator which bitwidths to bypass. More... | |
| void | addRegisterClass (MVT VT, const TargetRegisterClass *RC) |
| Add the specified register class as an available regclass for the specified value type. More... | |
| virtual std::pair< const TargetRegisterClass *, uint8_t > | findRepresentativeClass (const TargetRegisterInfo *TRI, MVT VT) const |
| Return the largest legal super-reg register class of the register class for the specified type and its associated "cost". More... | |
| void | computeRegisterProperties (const TargetRegisterInfo *TRI) |
| Once all of the register classes are added, this allows us to compute derived properties we expose. More... | |
| void | setOperationAction (unsigned Op, MVT VT, LegalizeAction Action) |
| Indicate that the specified operation does not work with the specified type and indicate what to do about it. More... | |
| void | setLoadExtAction (unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action) |
| Indicate that the specified load with extension does not work with the specified type and indicate what to do about it. More... | |
| void | setTruncStoreAction (MVT ValVT, MVT MemVT, LegalizeAction Action) |
| Indicate that the specified truncating store does not work with the specified type and indicate what to do about it. More... | |
| void | setIndexedLoadAction (unsigned IdxMode, MVT VT, LegalizeAction Action) |
| Indicate that the specified indexed load does or does not work with the specified type and indicate what to do abort it. More... | |
| void | setIndexedStoreAction (unsigned IdxMode, MVT VT, LegalizeAction Action) |
| Indicate that the specified indexed store does or does not work with the specified type and indicate what to do about it. More... | |
| void | setCondCodeAction (ISD::CondCode CC, MVT VT, LegalizeAction Action) |
| Indicate that the specified condition code is or isn't supported on the target and indicate what to do about it. More... | |
| void | AddPromotedToType (unsigned Opc, MVT OrigVT, MVT DestVT) |
| If Opc/OrigVT is specified as being promoted, the promotion code defaults to trying a larger integer/fp until it can find one that works. More... | |
| void | setOperationPromotedToType (unsigned Opc, MVT OrigVT, MVT DestVT) |
| Convenience method to set an operation to Promote and specify the type in a single call. More... | |
| void | setTargetDAGCombine (ISD::NodeType NT) |
| Targets should invoke this method for each target independent node that they want to provide a custom DAG combiner for by implementing the PerformDAGCombine virtual method. More... | |
| void | setJumpBufSize (unsigned Size) |
| Set the target's required jmp_buf buffer size (in bytes); default is 200. More... | |
| void | setJumpBufAlignment (unsigned Align) |
| Set the target's required jmp_buf buffer alignment (in bytes); default is 0. More... | |
| void | setMinFunctionAlignment (unsigned Align) |
| Set the target's minimum function alignment (in log2(bytes)) More... | |
| void | setPrefFunctionAlignment (unsigned Align) |
| Set the target's preferred function alignment. More... | |
| void | setPrefLoopAlignment (unsigned Align) |
| Set the target's preferred loop alignment. More... | |
| void | setMinStackArgumentAlignment (unsigned Align) |
| Set the minimum stack alignment of an argument (in log2(bytes)). More... | |
| void | setMaxAtomicSizeInBitsSupported (unsigned SizeInBits) |
| Set the maximum atomic operation size supported by the backend. More... | |
| void | setMinCmpXchgSizeInBits (unsigned SizeInBits) |
| Sets the minimum cmpxchg or ll/sc size supported by the backend. More... | |
| void | setSupportsUnalignedAtomics (bool UnalignedSupported) |
| Sets whether unaligned atomic operations are supported. More... | |
| virtual bool | isExtFreeImpl (const Instruction *I) const |
Return true if the extension represented by I is free. More... | |
| bool | isLegalRC (const TargetRegisterInfo &TRI, const TargetRegisterClass &RC) const |
| Return true if the value types that can be represented by the specified register class are all legal. More... | |
| MachineBasicBlock * | emitPatchPoint (MachineInstr &MI, MachineBasicBlock *MBB) const |
| Replace/modify any TargetFrameIndex operands with a targte-dependent sequence of memory operands that is recognized by PrologEpilogInserter. More... | |
| MachineBasicBlock * | emitXRayCustomEvent (MachineInstr &MI, MachineBasicBlock *MBB) const |
| Replace/modify the XRay custom event operands with target-dependent details. More... | |
| MachineBasicBlock * | emitXRayTypedEvent (MachineInstr &MI, MachineBasicBlock *MBB) const |
| Replace/modify the XRay typed event operands with target-dependent details. More... | |
| Static Protected Member Functions inherited from llvm::AMDGPUTargetLowering | |
| static EVT | getEquivalentMemType (LLVMContext &Context, EVT VT) |
| Protected Attributes inherited from llvm::TargetLoweringBase | |
| ValueTypeActionImpl | ValueTypeActions |
| unsigned | GatherAllAliasesMaxDepth |
| Depth that GatherAllAliases should should continue looking for chain dependencies when trying to find a more preferable chain. More... | |
| unsigned | MaxStoresPerMemset |
| Specify maximum number of store instructions per memset call. More... | |
| unsigned | MaxStoresPerMemsetOptSize |
| Maximum number of stores operations that may be substituted for the call to memset, used for functions with OptSize attribute. More... | |
| unsigned | MaxStoresPerMemcpy |
| Specify maximum bytes of store instructions per memcpy call. More... | |
| unsigned | MaxGluedStoresPerMemcpy = 0 |
| Specify max number of store instructions to glue in inlined memcpy. More... | |
| unsigned | MaxStoresPerMemcpyOptSize |
| Maximum number of store operations that may be substituted for a call to memcpy, used for functions with OptSize attribute. More... | |
| unsigned | MaxLoadsPerMemcmp |
| unsigned | MaxLoadsPerMemcmpOptSize |
| unsigned | MaxStoresPerMemmove |
| Specify maximum bytes of store instructions per memmove call. More... | |
| unsigned | MaxStoresPerMemmoveOptSize |
| Maximum number of store instructions that may be substituted for a call to memmove, used for functions with OptSize attribute. More... | |
| bool | PredictableSelectIsExpensive |
| Tells the code generator that select is more expensive than a branch if the branch is usually predicted right. More... | |
| bool | EnableExtLdPromotion |
Detailed Description
Definition at line 24 of file SIISelLowering.h.
Constructor & Destructor Documentation
◆ SITargetLowering()
| SITargetLowering::SITargetLowering | ( | const TargetMachine & | tm, |
| const GCNSubtarget & | STI | ||
| ) |
Definition at line 114 of file SIISelLowering.cpp.
References llvm::ISD::ADD, llvm::ISD::ADDCARRY, llvm::TargetLoweringBase::AddPromotedToType(), llvm::TargetLoweringBase::addRegisterClass(), llvm::ISD::ADDRSPACECAST, llvm::ISD::AND, llvm::ISD::ANY_EXTEND, llvm::ISD::ATOMIC_CMP_SWAP, llvm::ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, llvm::ISD::ATOMIC_LOAD, llvm::ISD::ATOMIC_LOAD_ADD, llvm::ISD::ATOMIC_LOAD_AND, llvm::ISD::ATOMIC_LOAD_MAX, llvm::ISD::ATOMIC_LOAD_MIN, llvm::ISD::ATOMIC_LOAD_NAND, llvm::ISD::ATOMIC_LOAD_OR, llvm::ISD::ATOMIC_LOAD_SUB, llvm::ISD::ATOMIC_LOAD_UMAX, llvm::ISD::ATOMIC_LOAD_UMIN, llvm::ISD::ATOMIC_LOAD_XOR, llvm::ISD::ATOMIC_STORE, llvm::ISD::ATOMIC_SWAP, llvm::ISD::BITCAST, llvm::ISD::BITREVERSE, llvm::ISD::BR_CC, llvm::ISD::BRCOND, llvm::ISD::BSWAP, llvm::ISD::BUILD_VECTOR, llvm::ISD::BUILTIN_OP_END, llvm::TargetLoweringBase::computeRegisterProperties(), llvm::ISD::CONCAT_VECTORS, llvm::ISD::Constant, llvm::ISD::ConstantFP, llvm::ISD::CTLZ, llvm::ISD::CTLZ_ZERO_UNDEF, llvm::ISD::CTPOP, llvm::ISD::CTTZ, llvm::ISD::CTTZ_ZERO_UNDEF, llvm::TargetLoweringBase::Custom, llvm::ISD::DEBUGTRAP, llvm::TargetLoweringBase::Expand, llvm::ISD::EXTRACT_SUBVECTOR, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::MVT::f16, llvm::MVT::f32, llvm::MVT::f64, llvm::ISD::FABS, llvm::ISD::FADD, llvm::ISD::FCANONICALIZE, llvm::ISD::FCEIL, llvm::ISD::FCOPYSIGN, llvm::ISD::FCOS, llvm::ISD::FDIV, llvm::ISD::FEXP, llvm::ISD::FFLOOR, llvm::ISD::FLOG, llvm::ISD::FLOG10, llvm::ISD::FMA, llvm::ISD::FMAD, llvm::ISD::FMAXNUM, llvm::ISD::FMAXNUM_IEEE, llvm::ISD::FMINNUM, llvm::ISD::FMINNUM_IEEE, llvm::ISD::FMUL, llvm::ISD::FNEG, llvm::ISD::FP16_TO_FP, llvm::ISD::FP_EXTEND, llvm::ISD::FP_ROUND, llvm::ISD::FP_TO_FP16, llvm::ISD::FP_TO_SINT, llvm::ISD::FP_TO_UINT, llvm::ISD::FRINT, llvm::ISD::FROUND, llvm::ISD::FSIN, llvm::ISD::FSUB, llvm::ISD::FTRUNC, llvm::GCNSubtarget::getGeneration(), llvm::GCNSubtarget::getRegisterInfo(), llvm::ISD::GlobalAddress, llvm::AMDGPUSubtarget::has16BitInsts(), llvm::GCNSubtarget::hasBCNT(), llvm::GCNSubtarget::hasBFE(), llvm::GCNSubtarget::hasBFI(), llvm::GCNSubtarget::hasFFBH(), llvm::GCNSubtarget::hasFFBL(), llvm::GCNSubtarget::hasFlatAddressSpace(), llvm::GCNSubtarget::hasFP16Denormals(), llvm::AMDGPUSubtarget::hasFP32Denormals(), llvm::AMDGPUSubtarget::hasFPExceptions(), llvm::AMDGPUSubtarget::hasVOP3PInsts(), llvm::MVT::i1, llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i64, llvm::ISD::INSERT_SUBVECTOR, llvm::ISD::INSERT_VECTOR_ELT, llvm::ISD::INTRINSIC_VOID, llvm::ISD::INTRINSIC_W_CHAIN, llvm::ISD::INTRINSIC_WO_CHAIN, llvm::TargetLoweringBase::Legal, llvm::ISD::LOAD, llvm::ISD::MUL, llvm::ISD::OR, llvm::MVT::Other, llvm::TargetLoweringBase::Promote, llvm::ISD::READCYCLECOUNTER, llvm::Sched::RegPressure, llvm::ISD::ROTL, llvm::ISD::ROTR, llvm::ISD::SCALAR_TO_VECTOR, llvm::ISD::SDIV, llvm::AMDGPUSubtarget::SEA_ISLANDS, llvm::ISD::SELECT, llvm::ISD::SELECT_CC, llvm::ISD::SETCC, llvm::TargetLoweringBase::setHasExtractBitsInsn(), llvm::TargetLoweringBase::setHasFloatingPointExceptions(), llvm::TargetLoweringBase::setOperationAction(), llvm::TargetLoweringBase::setSchedulingPreference(), llvm::TargetLoweringBase::setTargetDAGCombine(), llvm::TargetLoweringBase::setTruncStoreAction(), llvm::ISD::SHL, llvm::ISD::SHL_PARTS, llvm::ISD::SIGN_EXTEND, llvm::ISD::SIGN_EXTEND_INREG, llvm::ISD::SINT_TO_FP, llvm::ISD::SMAX, llvm::ISD::SMIN, llvm::ISD::SRA, llvm::ISD::SRA_PARTS, llvm::ISD::SREM, llvm::ISD::SRL, llvm::ISD::SRL_PARTS, llvm::ISD::STORE, llvm::ISD::SUB, llvm::ISD::SUBCARRY, llvm::ISD::TRAP, llvm::ISD::TRUNCATE, llvm::ISD::UADDO, llvm::ISD::UDIV, llvm::ISD::UINT_TO_FP, llvm::ISD::UMAX, llvm::ISD::UMIN, llvm::ISD::UNDEF, llvm::ISD::UREM, llvm::ISD::USUBO, llvm::MVT::v16f32, llvm::MVT::v16i16, llvm::MVT::v16i32, llvm::MVT::v16i8, llvm::MVT::v2f16, llvm::MVT::v2f32, llvm::MVT::v2f64, llvm::MVT::v2i1, llvm::MVT::v2i16, llvm::MVT::v2i32, llvm::MVT::v2i64, llvm::MVT::v2i8, llvm::MVT::v32i16, llvm::MVT::v32i32, llvm::MVT::v32i8, llvm::MVT::v4f16, llvm::MVT::v4f32, llvm::MVT::v4i1, llvm::MVT::v4i16, llvm::MVT::v4i32, llvm::MVT::v4i8, llvm::MVT::v8f16, llvm::MVT::v8f32, llvm::MVT::v8i16, llvm::MVT::v8i32, llvm::MVT::v8i8, llvm::ISD::VECTOR_SHUFFLE, llvm::ISD::XOR, and llvm::ISD::ZERO_EXTEND.
Member Function Documentation
◆ AdjustInstrPostInstrSelection()
|
overridevirtual |
Assign the register class depending on the number of bits set in the writemask.
Reimplemented from llvm::TargetLowering.
Definition at line 9311 of file SIISelLowering.cpp.
References llvm::BuildMI(), llvm::tgtok::Def, llvm::AMDGPU::getAtomicNoRetOp(), llvm::MachineInstr::getDebugLoc(), llvm::GCNSubtarget::getInstrInfo(), llvm::SDNode::getMachineOpcode(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), getSubtarget(), llvm::SDNode::hasAnyUseOfValue(), llvm::SDNode::hasNUsesOfValue(), llvm::SDNode::isMachineOpcode(), llvm::SIInstrInfo::isVOP3(), llvm::SIInstrInfo::legalizeOperandsVOP3(), MI, MRI, llvm::MachineInstr::RemoveOperand(), llvm::MachineInstr::setDesc(), TII, and llvm::SDNode::use_begin().
◆ allowsMisalignedMemoryAccesses()
|
overridevirtual |
Determine if the target supports unaligned memory accesses.
This function returns true if the target allows unaligned memory accesses of the specified type in the given address space. If true, it also returns whether the unaligned memory access is "fast" in the last argument by reference. This is used, for example, in situations where an array copy/move/set is converted to a sequence of store operations. Its use helps to ensure that such replacements don't generate code that causes an alignment error (trap) on the target machine.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 1119 of file SIISelLowering.cpp.
References llvm::EVT::bitsGT(), llvm::EVT::bitsLT(), AMDGPUAS::CONSTANT_ADDRESS, AMDGPUAS::CONSTANT_ADDRESS_32BIT, AMDGPUAS::FLAT_ADDRESS, llvm::EVT::getSizeInBits(), llvm::EVT::getStoreSize(), llvm::GCNSubtarget::hasUnalignedBufferAccess(), llvm::GCNSubtarget::hasUnalignedScratchAccess(), llvm::MVT::i32, AMDGPUAS::LOCAL_ADDRESS, llvm::MVT::Other, AMDGPUAS::PRIVATE_ADDRESS, and AMDGPUAS::REGION_ADDRESS.
◆ buildRSRC()
| MachineSDNode * SITargetLowering::buildRSRC | ( | SelectionDAG & | DAG, |
| const SDLoc & | DL, | ||
| SDValue | Ptr, | ||
| uint32_t | RsrcDword1, | ||
| uint64_t | RsrcDword2And3 | ||
| ) | const |
Return a resource descriptor with the 'Add TID' bit enabled The TID (Thread ID) is multiplied by the stride value (bits [61:48] of the resource descriptor) to create an offset, which is added to the resource pointer.
Definition at line 9400 of file SIISelLowering.cpp.
References buildSMovImm32(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getMachineNode(), llvm::SelectionDAG::getTargetConstant(), llvm::SelectionDAG::getTargetExtractSubreg(), llvm::MVT::i32, and llvm::MVT::v4i32.
Referenced by isStackPtrRelative().
◆ CanLowerReturn()
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overridevirtual |
This hook should be implemented to check whether the return values described by the Outs array can fit into the return registers.
If false is returned, an sret-demotion is performed.
Reimplemented from llvm::TargetLowering.
Definition at line 2077 of file SIISelLowering.cpp.
References llvm::AMDGPUTargetLowering::CCAssignFnForReturn(), llvm::CCState::CheckReturn(), and llvm::AMDGPU::isEntryFunctionCC().
◆ canMergeStoresTo()
|
overridevirtual |
Returns if it's reasonable to merge stores to MemVT size.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 1106 of file SIISelLowering.cpp.
References AMDGPUAS::FLAT_ADDRESS, llvm::GCNSubtarget::getMaxPrivateElementSize(), llvm::EVT::getSizeInBits(), getSubtarget(), AMDGPUAS::GLOBAL_ADDRESS, AMDGPUAS::LOCAL_ADDRESS, and AMDGPUAS::PRIVATE_ADDRESS.
◆ computeKnownBitsForFrameIndex()
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overridevirtual |
Determine which of the bits of FrameIndex FIOp are known to be 0.
Default implementation computes low bits based on alignment information. This should preserve known bits passed into it.
Reimplemented from llvm::TargetLowering.
Definition at line 9571 of file SIISelLowering.cpp.
References AssumeFrameIndexHighZeroBits, llvm::TargetLowering::computeKnownBitsForFrameIndex(), getSubtarget(), LLVM_ATTRIBUTE_UNUSED, llvm::APInt::setHighBits(), and llvm::KnownBits::Zero.
◆ copyToM0()
| SDValue SITargetLowering::copyToM0 | ( | SelectionDAG & | DAG, |
| SDValue | Chain, | ||
| const SDLoc & | DL, | ||
| SDValue | V | ||
| ) | const |
Definition at line 4562 of file SIISelLowering.cpp.
References llvm::ISD::AssertZext, llvm::SelectionDAG::getEntryNode(), llvm::SelectionDAG::getMachineNode(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getValueType(), llvm::MVT::Glue, llvm::MVT::i32, and llvm::MVT::Other.
Referenced by llvm::createR600ISelDag(), and parseTexFail().
◆ denormalsEnabledForType()
Definition at line 9662 of file SIISelLowering.cpp.
References llvm::MVT::f16, llvm::MVT::f32, llvm::MVT::f64, llvm::EVT::getScalarType(), llvm::EVT::getSimpleVT(), llvm::GCNSubtarget::hasFP16Denormals(), llvm::AMDGPUSubtarget::hasFP32Denormals(), llvm::GCNSubtarget::hasFP64Denormals(), and llvm::MVT::SimpleTy.
Referenced by isCanonicalized().
◆ EmitInstrWithCustomInserter()
|
overridevirtual |
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' flag.
These instructions are special in various ways, which require special support to insert. The specified MachineInstr is created but not inserted into any basic blocks, and this method is called to expand it into a sequence of instructions, potentially also creating new basic blocks and control flow. As long as the returned basic block is different (i.e., we created a new one), the custom inserter is free to modify the rest of MBB.
Reimplemented from llvm::TargetLowering.
Definition at line 3260 of file SIISelLowering.cpp.
References llvm::ARM_AM::add, llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::MachineBasicBlock::begin(), llvm::SIInstrInfo::buildExtractSubRegOrImm(), llvm::BuildMI(), llvm::MachineInstrBuilder::cloneMemRefs(), llvm::MachineRegisterInfo::createVirtualRegister(), E, emitIndirectDst(), emitIndirectSrc(), llvm::TargetLowering::EmitInstrWithCustomInserter(), llvm::MachineInstr::eraseFromParent(), G, llvm::MachineInstr::getDebugLoc(), llvm::SIMachineFunctionInfo::getFrameOffsetReg(), llvm::MachineOperand::getGlobal(), llvm::MachineOperand::getImm(), llvm::MachineFunction::getInfo(), llvm::GCNSubtarget::getInstrInfo(), llvm::ilist_node_impl< OptionsT >::getIterator(), llvm::AMDGPUMachineFunction::getLDSSize(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), llvm::SIInstrInfo::getRegisterInfo(), llvm::SIRegisterInfo::getReturnAddressReg(), llvm::SIMachineFunctionInfo::getStackPtrOffsetReg(), getSubtarget(), llvm::MachineRegisterInfo::getVRegDef(), I, llvm::RegState::Implicit, llvm::RegState::ImplicitDefine, Info, llvm::MachineBasicBlock::insert(), llvm::SIInstrInfo::isMIMG(), llvm::RegState::Kill, llvm::MachineInstr::mayLoadOrStore(), llvm::MachineInstr::memoperands_empty(), MI, MRI, llvm::report_fatal_error(), llvm::MachineOperand::setIsUndef(), splitKillBlock(), and TII.
◆ enableAggressiveFMAFusion()
Return true if target always beneficiates from combining into FMA for a given value type.
This must typically return false on targets where FMA takes more cycles to execute than FADD.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 3507 of file SIISelLowering.cpp.
◆ finalizeLowering()
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overridevirtual |
Execute target specific actions to finalize target lowering.
This is used to set extra flags in MachineFrameInformation and freezing the set of reserved registers. The default implementation just freezes the set of reserved registers.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 9532 of file SIISelLowering.cpp.
References assert(), llvm::TargetLoweringBase::finalizeLowering(), llvm::MachineFunction::getFrameInfo(), llvm::SIMachineFunctionInfo::getFrameOffsetReg(), llvm::MachineFunction::getInfo(), llvm::MachineFunction::getRegInfo(), llvm::GCNSubtarget::getRegisterInfo(), llvm::SIMachineFunctionInfo::getScratchRSrcReg(), llvm::SIMachineFunctionInfo::getScratchWaveOffsetReg(), llvm::SIMachineFunctionInfo::getStackPtrOffsetReg(), llvm::TargetLoweringBase::getTargetMachine(), Info, llvm::AMDGPUMachineFunction::isEntryFunction(), llvm::SIMachineFunctionInfo::limitOccupancy(), MRI, llvm::MachineRegisterInfo::replaceRegWith(), llvm::SIRegisterInfo::reservedStackPtrOffsetReg(), reservePrivateMemoryRegs(), llvm::SIMachineFunctionInfo::setStackPtrOffsetReg(), and TRI.
◆ getAddrModeArguments()
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overridevirtual |
CodeGenPrepare sinks address calculations into the same BB as Load/Store instructions reading the address.
This allows as much computation as possible to be done in the address mode for that operand. This hook lets targets also pass back when this should be done on intrinsics which load/store.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 936 of file SIISelLowering.cpp.
References llvm::Intrinsic::amdgcn_atomic_dec, llvm::Intrinsic::amdgcn_atomic_inc, llvm::Intrinsic::amdgcn_ds_fadd, llvm::Intrinsic::amdgcn_ds_fmax, llvm::Intrinsic::amdgcn_ds_fmin, llvm::Intrinsic::amdgcn_ds_ordered_add, llvm::Intrinsic::amdgcn_ds_ordered_swap, llvm::TargetLoweringBase::AddrMode::BaseOffs, llvm::CallBase::getArgOperand(), llvm::IntrinsicInst::getIntrinsicID(), llvm::Value::getType(), llvm::GCNSubtarget::hasFlatInstOffsets(), llvm::SmallVectorTemplateBase< T, bool >::push_back(), and llvm::TargetLoweringBase::AddrMode::Scale.
◆ getConstraintType()
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overridevirtual |
Given a constraint, return the type of constraint it is for this target.
Reimplemented from llvm::TargetLowering.
Definition at line 9517 of file SIISelLowering.cpp.
References llvm::TargetLowering::C_RegisterClass, llvm::TargetLowering::getConstraintType(), and llvm::StringRef::size().
◆ getNumRegistersForCallingConv()
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overridevirtual |
Certain targets require unusual breakdowns of certain types.
For MIPS, this occurs when a vector type is used, as vector are passed through the integer register set.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 759 of file SIISelLowering.cpp.
References llvm::CallingConv::AMDGPU_KERNEL, llvm::TargetLoweringBase::getNumRegistersForCallingConv(), llvm::EVT::getScalarType(), llvm::EVT::getSizeInBits(), llvm::EVT::getVectorNumElements(), llvm::AMDGPUSubtarget::has16BitInsts(), llvm::EVT::isVector(), and Size.
◆ getOptimalMemOpType()
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overridevirtual |
Returns the target specific optimal type for load and store operations as a result of memset, memcpy, and memmove lowering.
If DstAlign is zero that means it's safe to destination alignment can satisfy any constraint. Similarly if SrcAlign is zero it means there isn't a need to check it against alignment requirement, probably because the source does not need to be loaded. If 'IsMemset' is true, that means it's expanding a memset. If 'ZeroMemset' is true, that means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy source is constant so it does not need to be loaded. It returns EVT::Other if the type should be determined using generic target-independent logic.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 1185 of file SIISelLowering.cpp.
References llvm::MVT::Other, llvm::MVT::v2i32, and llvm::MVT::v4i32.
◆ getPreferredVectorAction()
|
overridevirtual |
Return the preferred vector type legalization action.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 1240 of file SIISelLowering.cpp.
References llvm::MVT::bitsLE(), llvm::TargetLoweringBase::getPreferredVectorAction(), llvm::MVT::getScalarType(), llvm::MVT::getVectorNumElements(), llvm::MVT::i16, and llvm::TargetLoweringBase::TypeSplitVector.
◆ getRegForInlineAsmConstraint()
|
overridevirtual |
Given a physical register constraint (e.g.
{edx}), return the register number and the register class for the register.
Given a register class constraint, like 'r', if this corresponds directly to an LLVM register class, return a register of 0 and the register class pointer.
This should only be used for C_Register constraints. On error, this returns a register number of 0 and a null register class pointer.
Reimplemented from llvm::TargetLowering.
Definition at line 9435 of file SIISelLowering.cpp.
References llvm::MVT::f16, llvm::Failed(), llvm::StringRef::getAsInteger(), llvm::TargetLowering::getRegForInlineAsmConstraint(), llvm::TargetRegisterClass::getRegister(), llvm::MVT::getSizeInBits(), llvm::MVT::i128, llvm::MVT::i16, llvm::TargetLoweringBase::isTypeLegal(), llvm::MVT::SimpleTy, llvm::StringRef::size(), and llvm::StringRef::substr().
◆ getRegisterByName()
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overridevirtual |
Return the register ID of the name passed in.
Used by named register global variables extension. There is no target-independent behaviour so the default action is to bail.
Reimplemented from llvm::TargetLowering.
Definition at line 2762 of file SIISelLowering.cpp.
References llvm::StringSwitch< T, R >::Case(), llvm::StringSwitch< T, R >::Default(), llvm::GCNSubtarget::getGeneration(), llvm::GCNSubtarget::getRegisterInfo(), llvm::EVT::getSizeInBits(), llvm_unreachable, Reg, llvm::report_fatal_error(), and llvm::AMDGPUSubtarget::SOUTHERN_ISLANDS.
◆ getRegisterTypeForCallingConv()
|
overridevirtual |
Certain combinations of ABIs, Targets and features require that types are legal for some operations and not for other operations.
For MIPS all vector types must be passed through the integer register set.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 739 of file SIISelLowering.cpp.
References llvm::CallingConv::AMDGPU_KERNEL, llvm::TargetLoweringBase::getRegisterTypeForCallingConv(), llvm::EVT::getScalarType(), llvm::EVT::getSimpleVT(), llvm::EVT::getSizeInBits(), llvm::AMDGPUSubtarget::has16BitInsts(), llvm::MVT::i32, llvm::EVT::isInteger(), llvm::EVT::isVector(), Size, llvm::MVT::v2f16, and llvm::MVT::v2i16.
◆ getScalarShiftAmountTy()
|
overridevirtual |
EVT is not used in-tree, but is used by out-of-tree target.
A documentation for this function would be nice...
Reimplemented from llvm::TargetLoweringBase.
Definition at line 3526 of file SIISelLowering.cpp.
References llvm::MVT::i16, and llvm::MVT::i32.
◆ getSetCCResultType()
|
overridevirtual |
Return the ValueType of the result of SETCC operations.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 3518 of file SIISelLowering.cpp.
References llvm::EVT::getVectorNumElements(), llvm::EVT::getVectorVT(), llvm::MVT::i1, and llvm::EVT::isVector().
Referenced by getFPTernOp().
◆ getSubtarget()
| const GCNSubtarget * SITargetLowering::getSubtarget | ( | ) | const |
Definition at line 713 of file SIISelLowering.cpp.
Referenced by AdjustInstrPostInstrSelection(), bitOpWithConstantIsReducible(), canMergeStoresTo(), computeKnownBitsForFrameIndex(), EmitInstrWithCustomInserter(), getPermuteMask(), getSplatConstantFP(), insertCopiesSplitCSR(), isEligibleForTailCallOptimization(), LowerCall(), LowerFormalArguments(), LowerReturn(), parseTexFail(), PostISelFolding(), splitKillBlock(), and wrapAddr64Rsrc().
◆ getTgtMemIntrinsic()
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overridevirtual |
Given an intrinsic, checks if on the target the intrinsic will need to map to a MemIntrinsicNode (touches memory).
If this is the case, it returns true and store the intrinsic information into the IntrinsicInfo that was passed to the function.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 858 of file SIISelLowering.cpp.
References llvm::TargetLoweringBase::IntrinsicInfo::align, llvm::Intrinsic::amdgcn_atomic_dec, llvm::Intrinsic::amdgcn_atomic_inc, llvm::Intrinsic::amdgcn_ds_fadd, llvm::Intrinsic::amdgcn_ds_fmax, llvm::Intrinsic::amdgcn_ds_fmin, llvm::Intrinsic::amdgcn_ds_ordered_add, llvm::Intrinsic::amdgcn_ds_ordered_swap, llvm::dyn_cast(), llvm::TargetLoweringBase::IntrinsicInfo::flags, llvm::CallBase::getArgOperand(), llvm::Intrinsic::getAttributes(), llvm::SIMachineFunctionInfo::getBufferPSV(), llvm::Value::getContext(), llvm::SIMachineFunctionInfo::getImagePSV(), llvm::MachineFunction::getInfo(), llvm::GCNSubtarget::getInstrInfo(), llvm::User::getOperand(), llvm::MachineFunction::getSubtarget(), llvm::Value::getType(), llvm::MVT::getVT(), llvm::AttributeList::hasFnAttribute(), llvm::ISD::INTRINSIC_VOID, llvm::ISD::INTRINSIC_W_CHAIN, llvm::ConstantInt::isZero(), llvm::AMDGPU::lookupRsrcIntrinsic(), llvm::TargetLoweringBase::IntrinsicInfo::memVT, memVTFromAggregate(), llvm::MachineMemOperand::MODereferenceable, llvm::MachineMemOperand::MOLoad, llvm::MachineMemOperand::MOStore, llvm::MachineMemOperand::MOVolatile, llvm::TargetLoweringBase::IntrinsicInfo::opc, llvm::MVT::Other, llvm::TargetLoweringBase::IntrinsicInfo::ptrVal, llvm::Attribute::ReadNone, llvm::Attribute::ReadOnly, and llvm::Attribute::WriteOnly.
◆ getVectorTypeBreakdownForCallingConv()
|
overridevirtual |
Certain targets such as MIPS require that some types such as vectors are always broken down into scalars in some contexts.
This occurs even if the vector type is legal.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 780 of file SIISelLowering.cpp.
References llvm::CallingConv::AMDGPU_KERNEL, llvm::EVT::getScalarType(), llvm::EVT::getSimpleVT(), llvm::EVT::getSizeInBits(), llvm::EVT::getVectorNumElements(), llvm::TargetLoweringBase::getVectorTypeBreakdownForCallingConv(), llvm::AMDGPUSubtarget::has16BitInsts(), llvm::MVT::i32, llvm::EVT::isInteger(), llvm::EVT::isVector(), Size, llvm::MVT::v2f16, and llvm::MVT::v2i16.
◆ hasBitPreservingFPLogic()
Return true if it is safe to transform an integer-domain bitwise operation into the equivalent floating-point operation.
This should be set to true if the target has IEEE-754-compliant fabs/fneg operations for the input type.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 3503 of file SIISelLowering.cpp.
References llvm::EVT::getScalarType(), and llvm::TargetLoweringBase::isTypeLegal().
◆ initializeSplitCSR()
|
overridevirtual |
Perform necessary initialization to handle a subset of CSRs explicitly via copies.
This function is called at the beginning of instruction selection.
Reimplemented from llvm::TargetLowering.
Definition at line 1803 of file SIISelLowering.cpp.
◆ insertCopiesSplitCSR()
|
overridevirtual |
Insert explicit copies in entry and exit blocks.
We copy a subset of CSRs to virtual registers in the entry block, and copy them back to physical registers in the exit blocks. This function is called at the end of instruction selection.
Reimplemented from llvm::TargetLowering.
Definition at line 1807 of file SIISelLowering.cpp.
References llvm::MachineBasicBlock::addLiveIn(), llvm::MachineBasicBlock::begin(), llvm::BuildMI(), contains(), llvm::MachineRegisterInfo::createVirtualRegister(), llvm::MCInstrInfo::get(), llvm::SIRegisterInfo::getCalleeSavedRegsViaCopy(), llvm::GCNSubtarget::getInstrInfo(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), llvm::GCNSubtarget::getRegisterInfo(), getSubtarget(), I, llvm_unreachable, MRI, TII, and TRI.
◆ isCanonicalized()
| bool SITargetLowering::isCanonicalized | ( | SelectionDAG & | DAG, |
| SDValue | Op, | ||
| unsigned | MaxDepth = 5 |
||
| ) | const |
Definition at line 7712 of file SIISelLowering.cpp.
References llvm::Intrinsic::amdgcn_cubeid, llvm::Intrinsic::amdgcn_cvt_pkrtz, llvm::Intrinsic::amdgcn_fdot2, llvm::Intrinsic::amdgcn_frexp_mant, llvm::ISD::BITCAST, llvm::APFloat::bitcastToAPInt(), llvm::ISD::BUILD_VECTOR, C, llvm::AMDGPUISD::CLAMP, llvm::AMDGPUISD::CVT_F32_UBYTE0, llvm::AMDGPUISD::CVT_F32_UBYTE1, llvm::AMDGPUISD::CVT_F32_UBYTE2, llvm::AMDGPUISD::CVT_F32_UBYTE3, llvm::AMDGPUISD::CVT_PKRTZ_F16_F32, denormalsEnabledForType(), llvm::AMDGPUISD::DIV_FIXUP, llvm::AMDGPUISD::DIV_FMAS, llvm::AMDGPUISD::DIV_SCALE, E, llvm::ISD::EXTRACT_SUBVECTOR, llvm::ISD::EXTRACT_VECTOR_ELT, F(), llvm::MVT::f16, llvm::ISD::FABS, llvm::ISD::FADD, llvm::ISD::FCANONICALIZE, llvm::ISD::FCEIL, llvm::ISD::FCOPYSIGN, llvm::ISD::FCOS, llvm::ISD::FDIV, llvm::ISD::FFLOOR, llvm::ISD::FMA, llvm::ISD::FMAD, llvm::AMDGPUISD::FMAD_FTZ, llvm::AMDGPUISD::FMAX3, llvm::ISD::FMAXNUM, llvm::ISD::FMAXNUM_IEEE, llvm::AMDGPUISD::FMED3, llvm::AMDGPUISD::FMIN3, llvm::ISD::FMINNUM, llvm::ISD::FMINNUM_IEEE, llvm::ISD::FMUL, llvm::AMDGPUISD::FMUL_LEGACY, llvm::ISD::FNEG, llvm::ISD::FP_EXTEND, llvm::ISD::FP_ROUND, llvm::AMDGPUISD::FRACT, llvm::ISD::FREM, llvm::ISD::FSIN, llvm::ISD::FSINCOS, llvm::ISD::FSQRT, llvm::ISD::FSUB, llvm::SelectionDAG::getConstantFP(), llvm::SDValue::getNumOperands(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::APFloat::getQNaN(), llvm::EVT::getScalarType(), llvm::APFloat::getSemantics(), llvm::SDValue::getValueType(), I, llvm::MVT::i16, llvm::MVT::i32, llvm::ISD::INSERT_VECTOR_ELT, llvm::ISD::INTRINSIC_WO_CHAIN, llvm::APFloat::isDenormal(), llvm::SelectionDAG::isKnownNeverSNaN(), llvm::APFloat::isNaN(), llvm::APFloat::isSignaling(), llvm::AMDGPUISD::LDEXP, LLVM_FALLTHROUGH, llvm_unreachable, llvm::AMDGPUISD::RCP, llvm::AMDGPUISD::RCP_IFLAG, llvm::AMDGPUISD::RCP_LEGACY, llvm::AMDGPUISD::RSQ, llvm::AMDGPUISD::RSQ_CLAMP, llvm::AMDGPUISD::RSQ_LEGACY, llvm::ISD::SELECT, llvm::GCNSubtarget::supportsMinMaxDenormModes(), llvm::AMDGPUISD::TRIG_PREOP, llvm::ISD::TRUNCATE, llvm::ISD::UNDEF, and llvm::MVT::v2f16.
Referenced by vectorEltWillFoldAway().
◆ isCheapAddrSpaceCast()
|
overridevirtual |
Returns true if a cast from SrcAS to DestAS is "cheap", such that e.g.
we are happy to sink it into basic blocks.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 1223 of file SIISelLowering.cpp.
References AMDGPUAS::FLAT_ADDRESS, and isNoopAddrSpaceCast().
◆ isEligibleForTailCallOptimization()
| bool SITargetLowering::isEligibleForTailCallOptimization | ( | SDValue | Callee, |
| CallingConv::ID | CalleeCC, | ||
| bool | isVarArg, | ||
| const SmallVectorImpl< ISD::OutputArg > & | Outs, | ||
| const SmallVectorImpl< SDValue > & | OutVals, | ||
| const SmallVectorImpl< ISD::InputArg > & | Ins, | ||
| SelectionDAG & | DAG | ||
| ) | const |
Definition at line 2360 of file SIISelLowering.cpp.
References llvm::CCState::AnalyzeCallOperands(), llvm::Function::args(), canGuaranteeTCO(), llvm::AMDGPUTargetLowering::CCAssignFnForCall(), llvm::SmallVectorBase::empty(), llvm::SIMachineFunctionInfo::getBytesInStackArgArea(), llvm::Function::getCallingConv(), llvm::SIRegisterInfo::getCallPreservedMask(), llvm::SelectionDAG::getContext(), llvm::MachineFunction::getFunction(), llvm::MachineFunction::getInfo(), llvm::SelectionDAG::getMachineFunction(), llvm::CCState::getNextStackOffset(), llvm::MachineFunction::getRegInfo(), llvm::GCNSubtarget::getRegisterInfo(), getSubtarget(), llvm::SelectionDAG::getTarget(), llvm::TargetOptions::GuaranteedTailCallOpt, mayTailCallThisCC(), MRI, llvm::TargetMachine::Options, llvm::TargetLowering::parametersInCSRMatch(), llvm::CCState::resultsCompatible(), and TRI.
Referenced by LowerCall().
◆ isFMAFasterThanFMulAndFAdd()
Return true if an FMA operation is faster than a pair of fmul and fadd instructions.
fmuladd intrinsics will be expanded to FMAs when this method returns true, otherwise fmuladd is expanded to fmul + fadd.
NOTE: This may be called before legalization on types for which FMAs are not legal, but should return true if those types will eventually legalize to types that support FMAs. After legalization, it will only be called on types that support FMAs (via Legal or Custom actions)
Reimplemented from llvm::TargetLoweringBase.
Definition at line 3547 of file SIISelLowering.cpp.
References llvm::MVT::f16, llvm::MVT::f32, llvm::MVT::f64, llvm::EVT::getScalarType(), llvm::EVT::getSimpleVT(), llvm::AMDGPUSubtarget::has16BitInsts(), llvm::GCNSubtarget::hasDLInsts(), llvm::GCNSubtarget::hasFastFMAF32(), llvm::GCNSubtarget::hasFP16Denormals(), llvm::AMDGPUSubtarget::hasFP32Denormals(), and llvm::MVT::SimpleTy.
Referenced by isClampZeroToOne().
◆ isFPExtFoldable()
|
overridevirtual |
Return true if an fpext operation input to an Opcode operation is free (for instance, because half-precision floating-point numbers are implicitly extended to float-precision) for an FMA instruction.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 725 of file SIISelLowering.cpp.
References llvm::MVT::f16, llvm::MVT::f32, llvm::ISD::FMA, llvm::ISD::FMAD, llvm::EVT::getScalarType(), llvm::GCNSubtarget::hasFmaMixInsts(), llvm::AMDGPUSubtarget::hasFP32Denormals(), and llvm::AMDGPUSubtarget::hasMadMixInsts().
◆ isKnownNeverNaNForTargetNode()
|
overridevirtual |
If SNaN is false,.
- Returns
- true if
Opis known to never be any NaN. IfsNaNis true, returns ifOpis known to never be a signaling NaN.
Reimplemented from llvm::AMDGPUTargetLowering.
Definition at line 9675 of file SIISelLowering.cpp.
References llvm::AMDGPUISD::CLAMP, llvm::GCNSubtarget::enableDX10Clamp(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SelectionDAG::isKnownNeverNaN(), and llvm::AMDGPUTargetLowering::isKnownNeverNaNForTargetNode().
◆ isLegalAddressingMode()
|
overridevirtual |
Return true if the addressing mode represented by AM is legal for this target, for a load/store of the specified type.
isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target, for a load/store of the specified type.
The type may be VoidTy, in which case only return true if the addressing mode is legal for a load/store of any legal type. TODO: Handle pre/postinc as well.
If the address space cannot be determined, it will be -1.
TODO: Remove default argument
Reimplemented from llvm::TargetLoweringBase.
Definition at line 1026 of file SIISelLowering.cpp.
References llvm::TargetLoweringBase::AddrMode::BaseGV, llvm::TargetLoweringBase::AddrMode::BaseOffs, AMDGPUAS::CONSTANT_ADDRESS, AMDGPUAS::CONSTANT_ADDRESS_32BIT, AMDGPUAS::FLAT_ADDRESS, llvm::GCNSubtarget::getGeneration(), llvm::DataLayout::getTypeStoreSize(), AMDGPUAS::GLOBAL_ADDRESS, llvm::TargetLoweringBase::AddrMode::HasBaseReg, isLegalGlobalAddressingMode(), llvm::Type::isSized(), llvm::isUInt< 16 >(), llvm::isUInt< 32 >(), llvm::isUInt< 8 >(), llvm_unreachable, AMDGPUAS::LOCAL_ADDRESS, AMDGPUAS::PRIVATE_ADDRESS, AMDGPUAS::REGION_ADDRESS, llvm::TargetLoweringBase::AddrMode::Scale, llvm::AMDGPUSubtarget::SEA_ISLANDS, llvm::AMDGPUSubtarget::SOUTHERN_ISLANDS, AMDGPUAS::UNKNOWN_ADDRESS_SPACE, and llvm::AMDGPUSubtarget::VOLCANIC_ISLANDS.
Referenced by getFPTernOp().
◆ isLegalGlobalAddressingMode()
Definition at line 971 of file SIISelLowering.cpp.
References llvm::TargetLoweringBase::AddrMode::BaseOffs, llvm::GCNSubtarget::hasAddr64(), llvm::TargetLoweringBase::AddrMode::HasBaseReg, llvm::GCNSubtarget::hasFlatGlobalInsts(), llvm::TargetLoweringBase::AddrMode::Scale, and llvm::GCNSubtarget::useFlatForGlobal().
Referenced by canMoveInstsAcrossMemOp(), and isLegalAddressingMode().
◆ isMemOpHasNoClobberedMemOperand()
Definition at line 1216 of file SIISelLowering.cpp.
References llvm::MemSDNode::getMemOperand(), llvm::Instruction::getMetadata(), llvm::MachineMemOperand::getValue(), I, and N.
Referenced by getLoadExtOrTrunc().
◆ isMemOpUniform()
Definition at line 1233 of file SIISelLowering.cpp.
References llvm::MemSDNode::getMemOperand(), llvm::AMDGPUInstrInfo::isUniformMMO(), and N.
◆ isNoopAddrSpaceCast()
|
overridevirtual |
Returns true if a cast between SrcAS and DestAS is a noop.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 1211 of file SIISelLowering.cpp.
References isFlatGlobalAddrSpace().
Referenced by isCheapAddrSpaceCast().
◆ isOffsetFoldingLegal()
|
overridevirtual |
Return true if folding a constant offset with the given GlobalAddress is legal.
It is frequently not legal in PIC relocation models.
Reimplemented from llvm::TargetLowering.
Definition at line 4477 of file SIISelLowering.cpp.
References AMDGPUAS::CONSTANT_ADDRESS, AMDGPUAS::CONSTANT_ADDRESS_32BIT, llvm::GlobalAddressSDNode::getAddressSpace(), llvm::GlobalAddressSDNode::getGlobal(), and AMDGPUAS::GLOBAL_ADDRESS.
◆ isSDNodeSourceOfDivergence()
|
overridevirtual |
Reimplemented from llvm::TargetLowering.
Definition at line 9601 of file SIISelLowering.cpp.
References assert(), llvm::ISD::CALLSEQ_END, llvm::ISD::CopyFromReg, llvm::FunctionLoweringInfo::DemoteRegister, AMDGPUAS::FLAT_ADDRESS, llvm::FunctionLoweringInfo::Fn, llvm::MemSDNode::getAddressSpace(), llvm::Function::getCallingConv(), llvm::GCNSubtarget::getInstrInfo(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::RegisterSDNode::getReg(), llvm::SIInstrInfo::getRegisterInfo(), llvm::FunctionLoweringInfo::getValueFromVirtualReg(), llvm::AMDGPUISD::INTERP_MOV, llvm::AMDGPUISD::INTERP_P1, llvm::AMDGPUISD::INTERP_P2, llvm::ISD::INTRINSIC_W_CHAIN, llvm::ISD::INTRINSIC_WO_CHAIN, isCopyFromRegOfInlineAsm(), llvm::LegacyDivergenceAnalysis::isDivergent(), llvm::AMDGPU::isEntryFunctionCC(), llvm::AMDGPU::isIntrinsicSourceOfDivergence(), llvm::SIRegisterInfo::isSGPRReg(), llvm::ISD::LOAD, llvm::FunctionLoweringInfo::MF, MRI, N, AMDGPUAS::PRIVATE_ADDRESS, Reg, llvm::ARM_MB::ST, and TRI.
◆ isShuffleMaskLegal()
Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations, those with specific masks.
By default, if a target supports the VECTOR_SHUFFLE node, all mask values are assumed to be legal.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 733 of file SIISelLowering.cpp.
◆ isTypeDesirableForOp()
Return true if the target has native support for the specified value type and it is 'desirable' to use the type for the given node type.
e.g. On x86 i16 is legal, but undesirable since i16 instruction encodings are longer and some i16 instructions are slow.
Reimplemented from llvm::TargetLowering.
Definition at line 1253 of file SIISelLowering.cpp.
References llvm::CCValAssign::AExt, llvm::AMDGPU::HSAMD::Kernel::Arg::Key::Align, llvm::alignDown(), llvm::ISD::AND, Arg, llvm::ISD::AssertSext, llvm::ISD::AssertZext, llvm::CCValAssign::BCvt, llvm::ISD::BITCAST, llvm::EVT::bitsLT(), llvm::EVT::changeTypeToInteger(), AMDGPUAS::CONSTANT_ADDRESS, llvm::MachineFrameInfo::CreateFixedObject(), llvm::AMDGPUTargetLowering::CreateLiveInRegister(), llvm::ISD::EXTLOAD, llvm::AMDGPUTargetLowering::FIRST_IMPLICIT, llvm::ISD::InputArg::Flags, llvm::PointerType::get(), llvm::UndefValue::get(), llvm::ISD::ArgFlagsTy::getByValSize(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getCopyFromReg(), llvm::SelectionDAG::getDataLayout(), llvm::SelectionDAG::getEntryNode(), llvm::SelectionDAG::getExtLoad(), llvm::MachinePointerInfo::getFixedStack(), llvm::SelectionDAG::getFrameIndex(), llvm::MachineFunction::getFrameInfo(), llvm::AMDGPUTargetLowering::getImplicitParameterOffset(), llvm::MachineFunction::getInfo(), llvm::MachineRegisterInfo::getLiveInVirtReg(), llvm::SelectionDAG::getLoad(), llvm::CCValAssign::getLocInfo(), llvm::CCValAssign::getLocMemOffset(), llvm::CCValAssign::getLocVT(), llvm::SelectionDAG::getMachineFunction(), llvm::SelectionDAG::getMergeValues(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getObjectPtrOffset(), llvm::TargetLoweringBase::getPointerTy(), llvm::SIMachineFunctionInfo::getPreloadedValue(), llvm::MachineFunction::getRegInfo(), llvm::ArgDescriptor::getRegister(), llvm::SelectionDAG::getSExtOrTrunc(), llvm::EVT::getStoreSize(), llvm::MVT::getStoreSize(), llvm::EVT::getTypeForEVT(), llvm::SDValue::getValue(), llvm::SelectionDAG::getValueType(), llvm::CCValAssign::getValVT(), llvm::SelectionDAG::getZExtOrTrunc(), llvm::AMDGPUSubtarget::has16BitInsts(), llvm::MVT::i1, llvm::MVT::i16, llvm::MVT::i32, Info, llvm::ISD::ArgFlagsTy::isByVal(), llvm::EVT::isFloatingPoint(), llvm::ISD::ArgFlagsTy::isSExt(), llvm::TargetLowering::isTypeDesirableForOp(), llvm::ISD::ArgFlagsTy::isZExt(), llvm::AMDGPUFunctionArgInfo::KERNARG_SEGMENT_PTR, llvm::SPII::Load, llvm::ISD::LOAD, llvm::MachineMemOperand::MODereferenceable, llvm::MachineMemOperand::MOInvariant, MRI, llvm::ISD::NON_EXTLOAD, llvm::ISD::OR, Reg, llvm::ISD::SELECT, llvm::ISD::SETCC, llvm::CCValAssign::SExt, llvm::ISD::SEXTLOAD, Signed, Size, llvm::ISD::SRL, llvm::ISD::STORE, llvm::ISD::TRUNCATE, llvm::ISD::XOR, llvm::CCValAssign::ZExt, and llvm::ISD::ZEXTLOAD.
◆ legalizeTargetIndependentNode()
| SDNode * SITargetLowering::legalizeTargetIndependentNode | ( | SDNode * | Node, |
| SelectionDAG & | DAG | ||
| ) | const |
Legalize target independent instructions (e.g.
INSERT_SUBREG) with frame index operands. LLVM assumes that inputs are to these instructions are registers.
Definition at line 9191 of file SIISelLowering.cpp.
References llvm::ISD::CopyToReg, llvm::MachineRegisterInfo::createVirtualRegister(), llvm::SelectionDAG::getCopyToReg(), llvm::SDNode::getGluedNode(), llvm::SelectionDAG::getMachineFunction(), llvm::SelectionDAG::getMachineNode(), llvm::SDValue::getNode(), llvm::SDNode::getNumOperands(), llvm::SDNode::getNumValues(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::RegisterSDNode::getReg(), llvm::MachineFunction::getRegInfo(), llvm::SelectionDAG::getRegister(), llvm::SDValue::getValue(), llvm::SDValue::getValueType(), llvm::MVT::i1, isFrameIndexOp(), llvm::TargetRegisterInfo::isPhysicalRegister(), MRI, llvm::SmallVectorTemplateBase< T >::push_back(), llvm::SelectionDAG::RemoveDeadNode(), llvm::SelectionDAG::ReplaceAllUsesWith(), and llvm::SelectionDAG::UpdateNodeOperands().
Referenced by getConstantValue(), and PostISelFolding().
◆ LowerCall()
|
overridevirtual |
This hook must be implemented to lower calls into the specified DAG.
The outgoing arguments to the call are described by the Outs array, and the values to be returned by the call are described by the Ins array. The implementation should fill in the InVals array with legal-type return values from the call, and return the resulting token chain value.
Reimplemented from llvm::AMDGPUTargetLowering.
Definition at line 2444 of file SIISelLowering.cpp.
References llvm::AMDGPUTargetLowering::addTokenForArgument(), llvm::CCValAssign::AExt, llvm::ISD::ANY_EXTEND, Arg, assert(), llvm::CCValAssign::BCvt, llvm::ISD::BITCAST, llvm::AMDGPUISD::CALL, llvm::TargetLowering::CallLoweringInfo::CallConv, Callee, llvm::TargetLowering::CallLoweringInfo::Callee, llvm::AMDGPUTargetLowering::CCAssignFnForCall(), llvm::TargetLowering::CallLoweringInfo::Chain, llvm::MachineFrameInfo::CreateFixedObject(), llvm::AMDGPUTargetLowering::CreateLiveInRegister(), llvm::TargetLowering::CallLoweringInfo::CS, llvm::TargetLowering::CallLoweringInfo::DAG, llvm::TargetLowering::CallLoweringInfo::DL, llvm::SmallVectorImpl< T >::emplace_back(), llvm::SmallVectorBase::empty(), llvm::ISD::FP_EXTEND, llvm::CCValAssign::FPExt, llvm::CCValAssign::Full, llvm::UndefValue::get(), llvm::ISD::ArgFlagsTy::getByValAlign(), llvm::ISD::ArgFlagsTy::getByValSize(), llvm::CallSiteBase< FunTy, BBTy, ValTy, UserTy, UseTy, InstrTy, CallTy, InvokeTy, IterTy >::getCalledFunction(), llvm::Function::getCallingConv(), llvm::SelectionDAG::getCALLSEQ_END(), llvm::SelectionDAG::getCALLSEQ_START(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getCopyFromReg(), llvm::SelectionDAG::getCopyToReg(), llvm::MachinePointerInfo::getFixedStack(), llvm::SelectionDAG::getFrameIndex(), llvm::MachineFunction::getFrameInfo(), llvm::SIMachineFunctionInfo::getFrameOffsetReg(), llvm::MachineFunction::getFunction(), llvm::MachineFunction::getInfo(), llvm::CallSiteBase< FunTy, BBTy, ValTy, UserTy, UseTy, InstrTy, CallTy, InvokeTy, IterTy >::getInstruction(), llvm::Type::getInt8PtrTy(), llvm::CCValAssign::getLocInfo(), llvm::CCValAssign::getLocMemOffset(), llvm::CCValAssign::getLocReg(), llvm::CCValAssign::getLocVT(), llvm::SelectionDAG::getMachineFunction(), llvm::SelectionDAG::getMemcpy(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getRegister(), llvm::GCNSubtarget::getRegisterInfo(), llvm::SelectionDAG::getRegisterMask(), llvm::SIRegisterInfo::getReturnAddressReg(), llvm::SIMachineFunctionInfo::getScratchRSrcReg(), llvm::SIMachineFunctionInfo::getScratchWaveOffsetReg(), llvm::MachinePointerInfo::getStack(), llvm::GCNSubtarget::getStackAlignment(), llvm::SelectionDAG::getStore(), llvm::MVT::getStoreSize(), getSubtarget(), llvm::MachineFunction::getTarget(), llvm::SelectionDAG::getTargetConstant(), llvm::SDValue::getValue(), llvm::CCValAssign::getValVT(), llvm::SelectionDAG::getVTList(), llvm::MVT::Glue, llvm::TargetOptions::GuaranteedTailCallOpt, llvm::MVT::i32, llvm::MVT::i64, Info, llvm::MipsISD::Ins, llvm::TargetLowering::CallLoweringInfo::Ins, llvm::ISD::ArgFlagsTy::isByVal(), isEligibleForTailCallOptimization(), llvm::AMDGPUMachineFunction::isEntryFunction(), llvm::CCValAssign::isMemLoc(), llvm::CallSiteBase< FunTy, BBTy, ValTy, UserTy, UseTy, InstrTy, CallTy, InvokeTy, IterTy >::isMustTailCall(), llvm::CCValAssign::isRegLoc(), llvm::AMDGPU::isShader(), llvm::TargetLowering::CallLoweringInfo::IsTailCall, llvm::TargetLowering::CallLoweringInfo::IsVarArg, llvm_unreachable, LowerCallResult(), llvm::AMDGPUTargetLowering::lowerUnhandledCall(), llvm::BitmaskEnumDetail::Mask(), llvm::MinAlign(), llvm::TargetMachine::Options, llvm::MVT::Other, llvm::TargetLowering::CallLoweringInfo::Outs, llvm::TargetLowering::CallLoweringInfo::OutVals, passSpecialInputs(), AMDGPUAS::PRIVATE_ADDRESS, llvm::SmallVectorTemplateBase< T >::push_back(), llvm::report_fatal_error(), llvm::MachineFrameInfo::setHasTailCall(), llvm::CCValAssign::SExt, llvm::ISD::SIGN_EXTEND, llvm::SPII::Store, llvm::AMDGPUISD::TC_RETURN, llvm::ISD::TokenFactor, TRI, llvm::MVT::v4i32, llvm::ISD::ZERO_EXTEND, and llvm::CCValAssign::ZExt.
◆ LowerCallResult()
| SDValue SITargetLowering::LowerCallResult | ( | SDValue | Chain, |
| SDValue | InFlag, | ||
| CallingConv::ID | CallConv, | ||
| bool | isVarArg, | ||
| const SmallVectorImpl< ISD::InputArg > & | Ins, | ||
| const SDLoc & | DL, | ||
| SelectionDAG & | DAG, | ||
| SmallVectorImpl< SDValue > & | InVals, | ||
| bool | isThisReturn, | ||
| SDValue | ThisVal | ||
| ) | const |
Definition at line 2206 of file SIISelLowering.cpp.
References llvm::CCValAssign::AExt, llvm::CCState::AnalyzeCallResult(), llvm::ISD::AssertSext, llvm::ISD::AssertZext, llvm::CCValAssign::BCvt, llvm::ISD::BITCAST, llvm::AMDGPUTargetLowering::CCAssignFnForReturn(), llvm::CCValAssign::Full, llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getCopyFromReg(), llvm::CCValAssign::getLocInfo(), llvm::CCValAssign::getLocReg(), llvm::CCValAssign::getLocVT(), llvm::SelectionDAG::getMachineFunction(), llvm::SelectionDAG::getNode(), llvm::SDValue::getValue(), llvm::SelectionDAG::getValueType(), llvm::CCValAssign::getValVT(), llvm::CCValAssign::isMemLoc(), llvm::CCValAssign::isRegLoc(), llvm_unreachable, llvm::SmallVectorTemplateBase< T >::push_back(), llvm::report_fatal_error(), llvm::CCValAssign::SExt, llvm::SmallVectorBase::size(), llvm::ISD::TRUNCATE, and llvm::CCValAssign::ZExt.
Referenced by LowerCall().
◆ LowerFormalArguments()
|
overridevirtual |
This hook must be implemented to lower the incoming (formal) arguments, described by the Ins array, into the specified DAG.
The implementation should fill in the InVals array with legal-type argument values, and return the resulting token chain value.
Reimplemented from llvm::TargetLowering.
Definition at line 1842 of file SIISelLowering.cpp.
References llvm::MachineFunction::addLiveIn(), llvm::CCValAssign::AExt, allocateHSAUserSGPRs(), allocateSpecialEntryInputVGPRs(), allocateSpecialInputSGPRs(), allocateSpecialInputVGPRs(), allocateSystemSGPRs(), llvm::CallingConv::AMDGPU_PS, llvm::AMDGPUTargetLowering::analyzeFormalArgumentsCompute(), llvm::SmallVectorImpl< T >::append(), Arg, assert(), llvm::ISD::AssertSext, llvm::ISD::AssertZext, AssumeFrameIndexHighZeroBits, llvm::CCValAssign::BCvt, llvm::SmallVectorTemplateCommon< T >::begin(), llvm::ISD::BITCAST, llvm::AMDGPUTargetLowering::CCAssignFnForCall(), llvm::countTrailingZeros(), llvm::LLVMContext::diagnose(), llvm::dyn_cast(), llvm::SmallVectorBase::empty(), llvm::GCNSubtarget::enableHugePrivateBuffer(), llvm::SmallVectorTemplateCommon< T >::end(), llvm::ISD::InputArg::Flags, llvm::CCValAssign::Full, llvm::Pass::getAnalysis(), llvm::SIMachineFunctionInfo::getArgInfo(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getCopyFromReg(), llvm::SDLoc::getDebugLoc(), llvm::SelectionDAG::getEntryNode(), llvm::SIMachineFunctionInfo::getFrameOffsetReg(), llvm::MachineFunction::getFunction(), llvm::Function::getFunctionType(), llvm::GCNSubtarget::getGeneration(), llvm::MachineFunction::getInfo(), llvm::EVT::getIntegerVT(), llvm::CCValAssign::getLocInfo(), llvm::CCValAssign::getLocMemOffset(), llvm::CCValAssign::getLocReg(), llvm::CCValAssign::getLocVT(), llvm::SelectionDAG::getMachineFunction(), llvm::SelectionDAG::getNode(), llvm::ISD::InputArg::getOrigArgIndex(), llvm::FunctionType::getParamType(), llvm::SelectionDAG::getPass(), llvm::SIMachineFunctionInfo::getPSInputAddr(), llvm::SIMachineFunctionInfo::getPSInputEnable(), llvm::GCNSubtarget::getRegisterInfo(), llvm::SIMachineFunctionInfo::getScratchRSrcReg(), llvm::SIMachineFunctionInfo::getScratchWaveOffsetReg(), getSubtarget(), llvm::MachineFunction::getSubtarget(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValue(), llvm::SDValue::getValueType(), llvm::SelectionDAG::getValueType(), llvm::CCValAssign::getValVT(), llvm::SIMachineFunctionInfo::hasDispatchPtr(), llvm::SIMachineFunctionInfo::hasFlatScratchInit(), llvm::SIMachineFunctionInfo::hasKernargSegmentPtr(), llvm::SIMachineFunctionInfo::hasWorkGroupIDX(), llvm::SIMachineFunctionInfo::hasWorkGroupIDY(), llvm::SIMachineFunctionInfo::hasWorkGroupIDZ(), llvm::SIMachineFunctionInfo::hasWorkGroupInfo(), llvm::SIMachineFunctionInfo::hasWorkItemIDX(), llvm::SIMachineFunctionInfo::hasWorkItemIDY(), llvm::SIMachineFunctionInfo::hasWorkItemIDZ(), llvm::MVT::i16, Info, llvm::AMDGPUSubtarget::isAmdHsaOS(), llvm::AMDGPUSubtarget::isAmdPalOS(), llvm::ISD::ArgFlagsTy::isByVal(), llvm::AMDGPU::isEntryFunctionCC(), llvm::AMDGPU::isKernel(), llvm::CCValAssign::isMemLoc(), llvm::ISD::InputArg::isOrigArg(), llvm::SIMachineFunctionInfo::isPSInputAllocated(), llvm::CCValAssign::isRegLoc(), llvm::AMDGPU::isShader(), llvm::ISD::ArgFlagsTy::isSRet(), llvm_unreachable, AMDGPUAS::LOCAL_ADDRESS, llvm::SIMachineFunctionInfo::markPSInputAllocated(), llvm::SIMachineFunctionInfo::markPSInputEnabled(), llvm::MinAlign(), llvm::MVT::Other, processShaderInputArgs(), llvm::SmallVectorTemplateBase< T >::push_back(), Reg, llvm::SIMachineFunctionInfo::setBytesInStackArgArea(), llvm::AMDGPUArgumentUsageInfo::setFuncArgInfo(), llvm::CCValAssign::SExt, llvm::SmallVectorBase::size(), llvm::AMDGPUSubtarget::SOUTHERN_ISLANDS, llvm::ARM_MB::ST, llvm::ISD::TokenFactor, TRI, llvm::ISD::TRUNCATE, llvm::ISD::InputArg::VT, llvm::ZB_Undefined, and llvm::CCValAssign::ZExt.
◆ LowerOperation()
|
overridevirtual |
This callback is invoked for operations that are unsupported by the target, which are registered to use 'custom' lowering, and whose defined values are all legal.
If the target has no operations that require custom lowering, it need not implement this. The default implementation of this aborts.
Reimplemented from llvm::AMDGPUTargetLowering.
Definition at line 3620 of file SIISelLowering.cpp.
References llvm::ISD::ADD, llvm::ISD::ADDRSPACECAST, assert(), llvm::ISD::ATOMIC_CMP_SWAP, llvm::ISD::BRCOND, llvm::ISD::BUILD_VECTOR, llvm::ISD::DEBUGTRAP, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::ISD::FABS, llvm::ISD::FADD, llvm::ISD::FCANONICALIZE, llvm::ISD::FCOS, llvm::ISD::FDIV, llvm::ISD::FMAXNUM, llvm::ISD::FMAXNUM_IEEE, llvm::ISD::FMINNUM, llvm::ISD::FMINNUM_IEEE, llvm::ISD::FMUL, llvm::ISD::FNEG, llvm::ISD::FP_ROUND, llvm::ISD::FSIN, llvm::MachineFunction::getInfo(), llvm::SelectionDAG::getMachineFunction(), llvm::SDValue::getNode(), llvm::SDNode::getNumValues(), llvm::SDValue::getOpcode(), llvm::ISD::GlobalAddress, llvm::ISD::INSERT_VECTOR_ELT, llvm::ISD::INTRINSIC_VOID, llvm::ISD::INTRINSIC_W_CHAIN, llvm::ISD::INTRINSIC_WO_CHAIN, llvm::ISD::LOAD, llvm::AMDGPUTargetLowering::LowerOperation(), llvm::ISD::MUL, llvm::ISD::SELECT, llvm::ISD::SHL, llvm::ISD::SMAX, llvm::ISD::SMIN, splitBinaryVectorOp(), splitUnaryVectorOp(), llvm::ISD::SRA, llvm::ISD::SRL, llvm::ISD::STORE, llvm::ISD::SUB, llvm::ISD::TRAP, llvm::ISD::UMAX, and llvm::ISD::UMIN.
◆ LowerReturn()
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overridevirtual |
This hook must be implemented to lower outgoing return values, described by the Outs array, into the specified DAG.
The implementation should return the resulting token chain value.
Reimplemented from llvm::AMDGPUTargetLowering.
Definition at line 2094 of file SIISelLowering.cpp.
References llvm::CCValAssign::AExt, llvm::CCState::AnalyzeReturn(), llvm::ISD::ANY_EXTEND, Arg, assert(), llvm::CCValAssign::BCvt, llvm::ISD::BITCAST, llvm::AMDGPUTargetLowering::CCAssignFnForReturn(), contains(), llvm::AMDGPUTargetLowering::CreateLiveInRegister(), E, llvm::SmallVectorBase::empty(), llvm::AMDGPUISD::ENDPGM, llvm::CCValAssign::Full, llvm::SIRegisterInfo::getCalleeSavedRegsViaCopy(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getCopyToReg(), llvm::MachineFunction::getInfo(), llvm::CCValAssign::getLocInfo(), llvm::CCValAssign::getLocReg(), llvm::CCValAssign::getLocVT(), llvm::SelectionDAG::getMachineFunction(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getRegister(), llvm::GCNSubtarget::getRegisterInfo(), llvm::SIRegisterInfo::getReturnAddressReg(), getSubtarget(), llvm::SDValue::getValue(), I, llvm::MVT::i32, llvm::MVT::i64, Info, llvm::AMDGPUMachineFunction::isEntryFunction(), llvm::AMDGPU::isKernel(), llvm::CCValAssign::isRegLoc(), llvm::AMDGPU::isShader(), llvm_unreachable, llvm::AMDGPUTargetLowering::LowerReturn(), llvm::MVT::Other, llvm::SmallVectorTemplateBase< T >::push_back(), llvm::AMDGPUISD::RET_FLAG, llvm::AMDGPUISD::RETURN_TO_EPILOG, llvm::SIMachineFunctionInfo::returnsVoid(), llvm::SIMachineFunctionInfo::setIfReturnsVoid(), llvm::CCValAssign::SExt, llvm::ISD::SIGN_EXTEND, llvm::SmallVectorBase::size(), TRI, llvm::ISD::ZERO_EXTEND, and llvm::CCValAssign::ZExt.
◆ mayBeEmittedAsTailCall()
Return true if the target may be able emit the call instruction as a tail call.
This is used by optimization passes to determine if it's profitable to duplicate return instructions to enable tailcall optimization.
Reimplemented from llvm::TargetLowering.
Definition at line 2431 of file SIISelLowering.cpp.
References llvm::Function::getCallingConv(), llvm::Function::getFnAttribute(), llvm::Instruction::getParent(), llvm::BasicBlock::getParent(), llvm::AMDGPU::isEntryFunctionCC(), and llvm::CallInst::isTailCall().
◆ passSpecialInputs()
| void SITargetLowering::passSpecialInputs | ( | CallLoweringInfo & | CLI, |
| CCState & | CCInfo, | ||
| const SIMachineFunctionInfo & | Info, | ||
| SmallVectorImpl< std::pair< unsigned, SDValue >> & | RegsToPass, | ||
| SmallVectorImpl< SDValue > & | MemOpChains, | ||
| SDValue | Chain | ||
| ) | const |
Definition at line 2264 of file SIISelLowering.cpp.
References llvm::CCState::AllocateStack(), assert(), llvm::TargetLowering::CallLoweringInfo::CS, llvm::TargetLowering::CallLoweringInfo::DAG, llvm::AMDGPUFunctionArgInfo::DISPATCH_ID, llvm::AMDGPUFunctionArgInfo::DISPATCH_PTR, llvm::TargetLowering::CallLoweringInfo::DL, llvm::Pass::getAnalysis(), llvm::SIMachineFunctionInfo::getArgInfo(), llvm::CallSiteBase< FunTy, BBTy, ValTy, UserTy, UseTy, InstrTy, CallTy, InvokeTy, IterTy >::getCalledFunction(), llvm::SelectionDAG::getPass(), llvm::AMDGPUFunctionArgInfo::getPreloadedValue(), llvm::ArgDescriptor::getRegister(), llvm::GCNSubtarget::getRegisterInfo(), llvm::EVT::getStoreSize(), llvm::MVT::i32, llvm::MVT::i64, llvm::AMDGPUFunctionArgInfo::IMPLICIT_ARG_PTR, llvm::ArgDescriptor::isRegister(), llvm::AMDGPUFunctionArgInfo::KERNARG_SEGMENT_PTR, llvm::AMDGPUTargetLowering::loadInputValue(), llvm::SmallVectorTemplateBase< T >::push_back(), llvm::AMDGPUFunctionArgInfo::QUEUE_PTR, llvm::AMDGPUTargetLowering::storeStackInputValue(), TRI, llvm::AMDGPUFunctionArgInfo::WORKGROUP_ID_X, llvm::AMDGPUFunctionArgInfo::WORKGROUP_ID_Y, llvm::AMDGPUFunctionArgInfo::WORKGROUP_ID_Z, llvm::AMDGPUFunctionArgInfo::WORKITEM_ID_X, llvm::AMDGPUFunctionArgInfo::WORKITEM_ID_Y, and llvm::AMDGPUFunctionArgInfo::WORKITEM_ID_Z.
Referenced by LowerCall().
◆ PerformDAGCombine()
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overridevirtual |
This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for.
The semantics are as follows: Return Value: SDValue.Val == 0 - No change was made SDValue.Val == N - N was replaced, is dead, and is already handled. otherwise - N should be replaced by the returned Operand.
In addition, methods provided by DAGCombinerInfo may be used to perform more complex transformations.
Reimplemented from llvm::AMDGPUTargetLowering.
Definition at line 8882 of file SIISelLowering.cpp.
References llvm::ISD::ADD, llvm::ISD::ADDCARRY, llvm::ISD::AND, llvm::ISD::ANY_EXTEND, llvm::ISD::ATOMIC_CMP_SWAP, llvm::ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, llvm::AMDGPUISD::ATOMIC_DEC, llvm::AMDGPUISD::ATOMIC_INC, llvm::ISD::ATOMIC_LOAD, llvm::ISD::ATOMIC_LOAD_ADD, llvm::ISD::ATOMIC_LOAD_AND, llvm::AMDGPUISD::ATOMIC_LOAD_FADD, llvm::AMDGPUISD::ATOMIC_LOAD_FMAX, llvm::AMDGPUISD::ATOMIC_LOAD_FMIN, llvm::ISD::ATOMIC_LOAD_MAX, llvm::ISD::ATOMIC_LOAD_MIN, llvm::ISD::ATOMIC_LOAD_NAND, llvm::ISD::ATOMIC_LOAD_OR, llvm::ISD::ATOMIC_LOAD_SUB, llvm::ISD::ATOMIC_LOAD_UMAX, llvm::ISD::ATOMIC_LOAD_UMIN, llvm::ISD::ATOMIC_LOAD_XOR, llvm::ISD::ATOMIC_STORE, llvm::ISD::ATOMIC_SWAP, llvm::ISD::BITCAST, llvm::AMDGPUISD::CLAMP, llvm::AMDGPUISD::CVT_F32_UBYTE0, llvm::AMDGPUISD::CVT_F32_UBYTE1, llvm::AMDGPUISD::CVT_F32_UBYTE2, llvm::AMDGPUISD::CVT_F32_UBYTE3, llvm::AMDGPUISD::CVT_PKRTZ_F16_F32, llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::MipsISD::Ext, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::MVT::f16, llvm::ISD::FADD, llvm::ISD::FCANONICALIZE, llvm::ISD::FMA, llvm::AMDGPUISD::FMAX_LEGACY, llvm::ISD::FMAXNUM, llvm::ISD::FMAXNUM_IEEE, llvm::AMDGPUISD::FMED3, llvm::AMDGPUISD::FMIN_LEGACY, llvm::ISD::FMINNUM, llvm::ISD::FMINNUM_IEEE, llvm::AMDGPUISD::FP_CLASS, llvm::AMDGPUISD::FRACT, llvm::ISD::FSUB, llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::TargetLoweringBase::getTargetMachine(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::MVT::i16, llvm::MVT::i32, llvm::ISD::INSERT_VECTOR_ELT, llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalize(), llvm::SDValue::isUndef(), llvm::AMDGPUISD::LDEXP, LLVM_FALLTHROUGH, llvm::ISD::LOAD, llvm::CodeGenOpt::None, llvm::ISD::OR, llvm::AMDGPUTargetLowering::PerformDAGCombine(), llvm::AMDGPUISD::RCP, llvm::AMDGPUISD::RCP_IFLAG, llvm::AMDGPUISD::RCP_LEGACY, llvm::AMDGPUISD::RSQ, llvm::AMDGPUISD::RSQ_CLAMP, llvm::AMDGPUISD::RSQ_LEGACY, llvm::ISD::SCALAR_TO_VECTOR, llvm::ISD::SETCC, llvm::ISD::SINT_TO_FP, llvm::ISD::SMAX, llvm::ISD::SMIN, llvm::ISD::STORE, llvm::ISD::SUB, llvm::ISD::SUBCARRY, llvm::ISD::UINT_TO_FP, llvm::ISD::UMAX, llvm::ISD::UMIN, llvm::MVT::v2f16, llvm::MVT::v2i16, llvm::ISD::XOR, and llvm::ISD::ZERO_EXTEND.
◆ PostISelFolding()
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overridevirtual |
Fold the instructions after selecting them.
Returns null if users were already updated.
Implements llvm::AMDGPUTargetLowering.
Definition at line 9237 of file SIISelLowering.cpp.
References llvm::GCNSubtarget::getInstrInfo(), llvm::SDNode::getMachineOpcode(), getSubtarget(), llvm::SIInstrInfo::isGather4(), llvm::SIInstrInfo::isMIMG(), legalizeTargetIndependentNode(), and TII.
◆ ReplaceNodeResults()
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overridevirtual |
This callback is invoked when a node result type is illegal for the target, and the operation was registered to use 'custom' lowering for that result type.
The target places new result values for the node in Results (their number and types must exactly match those of the original return values of the node), or leaves Results empty, which indicates that the node is not to be custom lowered after all.
If the target has no operations that require custom lowering, it need not implement this. The default implementation aborts.
Reimplemented from llvm::AMDGPUTargetLowering.
Definition at line 3809 of file SIISelLowering.cpp.
References llvm::Intrinsic::amdgcn_cvt_pk_i16, llvm::Intrinsic::amdgcn_cvt_pk_u16, llvm::Intrinsic::amdgcn_cvt_pknorm_i16, llvm::Intrinsic::amdgcn_cvt_pknorm_u16, llvm::Intrinsic::amdgcn_cvt_pkrtz, llvm::ISD::AND, llvm::ISD::ANY_EXTEND, llvm::ISD::BITCAST, llvm::EVT::bitsLT(), llvm::AMDGPUISD::CVT_PK_I16_I32, llvm::AMDGPUISD::CVT_PK_U16_U32, llvm::AMDGPUISD::CVT_PKNORM_I16_F32, llvm::AMDGPUISD::CVT_PKNORM_U16_F32, llvm::AMDGPUISD::CVT_PKRTZ_F16_F32, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::ISD::FABS, llvm::ISD::FNEG, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::AMDGPUTargetLowering::getEquivalentMemType(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::SDNode::getValueType(), llvm::MVT::i32, llvm::ISD::INSERT_VECTOR_ELT, llvm::ISD::INTRINSIC_W_CHAIN, llvm::ISD::INTRINSIC_WO_CHAIN, llvm::TargetLoweringBase::isTypeLegal(), llvm::SmallVectorTemplateBase< T >::push_back(), llvm::ISD::SELECT, llvm::ISD::TRUNCATE, llvm::MVT::v2f16, llvm::MVT::v2i16, and llvm::ISD::XOR.
◆ shouldConvertConstantLoadToIntImm()
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overridevirtual |
Return true if it is beneficial to convert a load of a constant to just the constant itself.
On some targets it might be more efficient to use a combination of arithmetic instructions to materialize the constant instead of loading it from a constant pool.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 1247 of file SIISelLowering.cpp.
◆ splitBinaryVectorOp()
| SDValue SITargetLowering::splitBinaryVectorOp | ( | SDValue | Op, |
| SelectionDAG & | DAG | ||
| ) | const |
Definition at line 3599 of file SIISelLowering.cpp.
References assert(), llvm::ISD::CONCAT_VECTORS, llvm::SDNode::getFlags(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getValueType(), llvm::SelectionDAG::SplitVectorOperand(), llvm::MVT::v4f16, and llvm::MVT::v4i16.
Referenced by findUser(), and LowerOperation().
◆ splitKillBlock()
| MachineBasicBlock * SITargetLowering::splitKillBlock | ( | MachineInstr & | MI, |
| MachineBasicBlock * | BB | ||
| ) | const |
Definition at line 2810 of file SIISelLowering.cpp.
References llvm::MachineBasicBlock::addSuccessor(), llvm::MachineBasicBlock::begin(), llvm::MachineFunction::CreateMachineBasicBlock(), llvm::MachineBasicBlock::end(), llvm::MachineBasicBlock::getBasicBlock(), llvm::GCNSubtarget::getInstrInfo(), llvm::SIInstrInfo::getKillTerminatorFromPseudo(), llvm::MachineInstr::getOpcode(), llvm::MachineBasicBlock::getParent(), getSubtarget(), llvm::MachineFunction::insert(), llvm::MachineInstr::setDesc(), llvm::MachineBasicBlock::splice(), TII, and llvm::MachineBasicBlock::transferSuccessorsAndUpdatePHIs().
Referenced by EmitInstrWithCustomInserter().
◆ splitUnaryVectorOp()
| SDValue SITargetLowering::splitUnaryVectorOp | ( | SDValue | Op, |
| SelectionDAG & | DAG | ||
| ) | const |
Definition at line 3579 of file SIISelLowering.cpp.
References assert(), llvm::ISD::CONCAT_VECTORS, llvm::SDNode::getFlags(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getValueType(), llvm::MipsISD::Hi, llvm::MipsISD::Lo, llvm::SelectionDAG::SplitVectorOperand(), and llvm::MVT::v4f16.
Referenced by LowerOperation().
◆ supportSplitCSR()
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overridevirtual |
Return true if the target supports that a subset of CSRs for the given machine function is handled explicitly via copies.
Reimplemented from llvm::TargetLowering.
Definition at line 1798 of file SIISelLowering.cpp.
References llvm::MachineFunction::getInfo(), Info, and llvm::AMDGPUMachineFunction::isEntryFunction().
◆ wrapAddr64Rsrc()
| MachineSDNode * SITargetLowering::wrapAddr64Rsrc | ( | SelectionDAG & | DAG, |
| const SDLoc & | DL, | ||
| SDValue | Ptr | ||
| ) | const |
Definition at line 9365 of file SIISelLowering.cpp.
References buildSMovImm32(), llvm::SIInstrInfo::getDefaultRsrcDataFormat(), llvm::GCNSubtarget::getInstrInfo(), llvm::SelectionDAG::getMachineNode(), getSubtarget(), llvm::SelectionDAG::getTargetConstant(), llvm::MVT::i32, TII, llvm::MVT::v2i32, and llvm::MVT::v4i32.
Referenced by getConstantValue().
The documentation for this class was generated from the following files:
- lib/Target/AMDGPU/SIISelLowering.h
- lib/Target/AMDGPU/SIISelLowering.cpp
