#include "Target/X86/X86InstrInfo.h"
Public Member Functions | |
| X86InstrInfo (X86Subtarget &STI) | |
| const X86RegisterInfo & | getRegisterInfo () const |
| getRegisterInfo - TargetInstrInfo is a superset of MRegister info. More... | |
| int64_t | getFrameAdjustment (const MachineInstr &I) const |
| Returns the stack pointer adjustment that happens inside the frame setup..destroy sequence (e.g. More... | |
| void | setFrameAdjustment (MachineInstr &I, int64_t V) const |
| Sets the stack pointer adjustment made inside the frame made up by this instruction. More... | |
| int | getSPAdjust (const MachineInstr &MI) const override |
| getSPAdjust - This returns the stack pointer adjustment made by this instruction. More... | |
| bool | isCoalescableExtInstr (const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg, unsigned &SubIdx) const override |
| isCoalescableExtInstr - Return true if the instruction is a "coalescable" extension instruction. More... | |
| unsigned | isLoadFromStackSlot (const MachineInstr &MI, int &FrameIndex) const override |
| unsigned | isLoadFromStackSlot (const MachineInstr &MI, int &FrameIndex, unsigned &MemBytes) const override |
| unsigned | isLoadFromStackSlotPostFE (const MachineInstr &MI, int &FrameIndex) const override |
| isLoadFromStackSlotPostFE - Check for post-frame ptr elimination stack locations as well. More... | |
| unsigned | isStoreToStackSlot (const MachineInstr &MI, int &FrameIndex) const override |
| unsigned | isStoreToStackSlot (const MachineInstr &MI, int &FrameIndex, unsigned &MemBytes) const override |
| unsigned | isStoreToStackSlotPostFE (const MachineInstr &MI, int &FrameIndex) const override |
| isStoreToStackSlotPostFE - Check for post-frame ptr elimination stack locations as well. More... | |
| bool | isReallyTriviallyReMaterializable (const MachineInstr &MI, AliasAnalysis *AA) const override |
| void | reMaterialize (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, unsigned SubIdx, const MachineInstr &Orig, const TargetRegisterInfo &TRI) const override |
| bool | classifyLEAReg (MachineInstr &MI, const MachineOperand &Src, unsigned LEAOpcode, bool AllowSP, unsigned &NewSrc, bool &isKill, MachineOperand &ImplicitOp, LiveVariables *LV) const |
| Given an operand within a MachineInstr, insert preceding code to put it into the right format for a particular kind of LEA instruction. More... | |
| MachineInstr * | convertToThreeAddress (MachineFunction::iterator &MFI, MachineInstr &MI, LiveVariables *LV) const override |
| convertToThreeAddress - This method must be implemented by targets that set the M_CONVERTIBLE_TO_3_ADDR flag. More... | |
| bool | findCommutedOpIndices (MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const override |
| Returns true iff the routine could find two commutable operands in the given machine instruction. More... | |
| unsigned | getFMA3OpcodeToCommuteOperands (const MachineInstr &MI, unsigned SrcOpIdx1, unsigned SrcOpIdx2, const X86InstrFMA3Group &FMA3Group) const |
Returns an adjusted FMA opcode that must be used in FMA instruction that performs the same computations as the given MI but which has the operands SrcOpIdx1 and SrcOpIdx2 commuted. More... | |
| bool | isUnpredicatedTerminator (const MachineInstr &MI) const override |
| bool | isUnconditionalTailCall (const MachineInstr &MI) const override |
| bool | canMakeTailCallConditional (SmallVectorImpl< MachineOperand > &Cond, const MachineInstr &TailCall) const override |
| void | replaceBranchWithTailCall (MachineBasicBlock &MBB, SmallVectorImpl< MachineOperand > &Cond, const MachineInstr &TailCall) const override |
| bool | analyzeBranch (MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override |
| bool | getMemOperandWithOffset (MachineInstr &LdSt, MachineOperand *&BaseOp, int64_t &Offset, const TargetRegisterInfo *TRI) const override |
| bool | analyzeBranchPredicate (MachineBasicBlock &MBB, TargetInstrInfo::MachineBranchPredicate &MBP, bool AllowModify=false) const override |
| unsigned | removeBranch (MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override |
| unsigned | insertBranch (MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override |
| bool | canInsertSelect (const MachineBasicBlock &, ArrayRef< MachineOperand > Cond, unsigned, unsigned, int &, int &, int &) const override |
| void | insertSelect (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, unsigned DstReg, ArrayRef< MachineOperand > Cond, unsigned TrueReg, unsigned FalseReg) const override |
| void | copyPhysReg (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override |
| void | storeRegToStackSlot (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override |
| void | storeRegToAddr (MachineFunction &MF, unsigned SrcReg, bool isKill, SmallVectorImpl< MachineOperand > &Addr, const TargetRegisterClass *RC, ArrayRef< MachineMemOperand *> MMOs, SmallVectorImpl< MachineInstr *> &NewMIs) const |
| void | loadRegFromStackSlot (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override |
| void | loadRegFromAddr (MachineFunction &MF, unsigned DestReg, SmallVectorImpl< MachineOperand > &Addr, const TargetRegisterClass *RC, ArrayRef< MachineMemOperand *> MMOs, SmallVectorImpl< MachineInstr *> &NewMIs) const |
| bool | expandPostRAPseudo (MachineInstr &MI) const override |
| bool | isSubregFoldable () const override |
| Check whether the target can fold a load that feeds a subreg operand (or a subreg operand that feeds a store). More... | |
| MachineInstr * | foldMemoryOperandImpl (MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex, LiveIntervals *LIS=nullptr) const override |
| foldMemoryOperand - If this target supports it, fold a load or store of the specified stack slot into the specified machine instruction for the specified operand(s). More... | |
| MachineInstr * | foldMemoryOperandImpl (MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI, LiveIntervals *LIS=nullptr) const override |
| foldMemoryOperand - Same as the previous version except it allows folding of any load and store from / to any address, not just from a specific stack slot. More... | |
| bool | unfoldMemoryOperand (MachineFunction &MF, MachineInstr &MI, unsigned Reg, bool UnfoldLoad, bool UnfoldStore, SmallVectorImpl< MachineInstr *> &NewMIs) const override |
| unfoldMemoryOperand - Separate a single instruction which folded a load or a store or a load and a store into two or more instruction. More... | |
| bool | unfoldMemoryOperand (SelectionDAG &DAG, SDNode *N, SmallVectorImpl< SDNode *> &NewNodes) const override |
| unsigned | getOpcodeAfterMemoryUnfold (unsigned Opc, bool UnfoldLoad, bool UnfoldStore, unsigned *LoadRegIndex=nullptr) const override |
| getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new instruction after load / store are unfolded from an instruction of the specified opcode. More... | |
| bool | areLoadsFromSameBasePtr (SDNode *Load1, SDNode *Load2, int64_t &Offset1, int64_t &Offset2) const override |
| areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to determine if two loads are loading from the same base address. More... | |
| bool | shouldScheduleLoadsNear (SDNode *Load1, SDNode *Load2, int64_t Offset1, int64_t Offset2, unsigned NumLoads) const override |
| shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to determine (in conjunction with areLoadsFromSameBasePtr) if two loads should be scheduled togther. More... | |
| void | getNoop (MCInst &NopInst) const override |
| Return the noop instruction to use for a noop. More... | |
| bool | reverseBranchCondition (SmallVectorImpl< MachineOperand > &Cond) const override |
| bool | isSafeToMoveRegClassDefs (const TargetRegisterClass *RC) const override |
| isSafeToMoveRegClassDefs - Return true if it's safe to move a machine instruction that defines the specified register class. More... | |
| bool | isSafeToClobberEFLAGS (MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const |
| isSafeToClobberEFLAGS - Return true if it's safe insert an instruction tha would clobber the EFLAGS condition register. More... | |
| bool | hasLiveCondCodeDef (MachineInstr &MI) const |
| True if MI has a condition code def, e.g. More... | |
| unsigned | getGlobalBaseReg (MachineFunction *MF) const |
| getGlobalBaseReg - Return a virtual register initialized with the the global base register value. More... | |
| std::pair< uint16_t, uint16_t > | getExecutionDomain (const MachineInstr &MI) const override |
| uint16_t | getExecutionDomainCustom (const MachineInstr &MI) const |
| void | setExecutionDomain (MachineInstr &MI, unsigned Domain) const override |
| bool | setExecutionDomainCustom (MachineInstr &MI, unsigned Domain) const |
| unsigned | getPartialRegUpdateClearance (const MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) const override |
| Inform the BreakFalseDeps pass how many idle instructions we would like before a partial register update. More... | |
| unsigned | getUndefRegClearance (const MachineInstr &MI, unsigned &OpNum, const TargetRegisterInfo *TRI) const override |
| Inform the BreakFalseDeps pass how many idle instructions we would like before certain undef register reads. More... | |
| void | breakPartialRegDependency (MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) const override |
| MachineInstr * | foldMemoryOperandImpl (MachineFunction &MF, MachineInstr &MI, unsigned OpNum, ArrayRef< MachineOperand > MOs, MachineBasicBlock::iterator InsertPt, unsigned Size, unsigned Alignment, bool AllowCommute) const |
| bool | isHighLatencyDef (int opc) const override |
| bool | hasHighOperandLatency (const TargetSchedModel &SchedModel, const MachineRegisterInfo *MRI, const MachineInstr &DefMI, unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const override |
| bool | useMachineCombiner () const override |
| bool | isAssociativeAndCommutative (const MachineInstr &Inst) const override |
| bool | hasReassociableOperands (const MachineInstr &Inst, const MachineBasicBlock *MBB) const override |
| void | setSpecialOperandAttr (MachineInstr &OldMI1, MachineInstr &OldMI2, MachineInstr &NewMI1, MachineInstr &NewMI2) const override |
| This is an architecture-specific helper function of reassociateOps. More... | |
| bool | analyzeCompare (const MachineInstr &MI, unsigned &SrcReg, unsigned &SrcReg2, int &CmpMask, int &CmpValue) const override |
| analyzeCompare - For a comparison instruction, return the source registers in SrcReg and SrcReg2 if having two register operands, and the value it compares against in CmpValue. More... | |
| bool | optimizeCompareInstr (MachineInstr &CmpInstr, unsigned SrcReg, unsigned SrcReg2, int CmpMask, int CmpValue, const MachineRegisterInfo *MRI) const override |
| optimizeCompareInstr - Check if there exists an earlier instruction that operates on the same source operands and sets flags in the same way as Compare; remove Compare if possible. More... | |
| MachineInstr * | optimizeLoadInstr (MachineInstr &MI, const MachineRegisterInfo *MRI, unsigned &FoldAsLoadDefReg, MachineInstr *&DefMI) const override |
| optimizeLoadInstr - Try to remove the load by folding it to a register operand at the use. More... | |
| std::pair< unsigned, unsigned > | decomposeMachineOperandsTargetFlags (unsigned TF) const override |
| ArrayRef< std::pair< unsigned, const char * > > | getSerializableDirectMachineOperandTargetFlags () const override |
| virtual outliner::OutlinedFunction | getOutliningCandidateInfo (std::vector< outliner::Candidate > &RepeatedSequenceLocs) const override |
| bool | isFunctionSafeToOutlineFrom (MachineFunction &MF, bool OutlineFromLinkOnceODRs) const override |
| outliner::InstrType | getOutliningType (MachineBasicBlock::iterator &MIT, unsigned Flags) const override |
| void | buildOutlinedFrame (MachineBasicBlock &MBB, MachineFunction &MF, const outliner::OutlinedFunction &OF) const override |
| MachineBasicBlock::iterator | insertOutlinedCall (Module &M, MachineBasicBlock &MBB, MachineBasicBlock::iterator &It, MachineFunction &MF, const outliner::Candidate &C) const override |
Protected Member Functions | |
| MachineInstr * | commuteInstructionImpl (MachineInstr &MI, bool NewMI, unsigned CommuteOpIdx1, unsigned CommuteOpIdx2) const override |
| Commutes the operands in the given instruction by changing the operands order and/or changing the instruction's opcode and/or the immediate value operand. More... | |
| bool | isCopyInstrImpl (const MachineInstr &MI, const MachineOperand *&Source, const MachineOperand *&Destination) const override |
| If the specific machine instruction is a instruction that moves/copies value from one register to another register return true along with machine operand and machine operand. More... | |
Detailed Description
Definition at line 168 of file X86InstrInfo.h.
Constructor & Destructor Documentation
◆ X86InstrInfo()
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explicit |
Definition at line 80 of file X86InstrInfo.cpp.
Member Function Documentation
◆ analyzeBranch()
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override |
Definition at line 2711 of file X86InstrInfo.cpp.
◆ analyzeBranchPredicate()
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override |
Definition at line 2720 of file X86InstrInfo.cpp.
References assert(), llvm::X86::COND_E, llvm::X86::COND_NE, llvm::MachineOperand::CreateImm(), E, llvm::ilist_node_with_parent< NodeTy, ParentTy, Options >::getNextNode(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), getRegisterInfo(), I, llvm::MachineOperand::isIdenticalTo(), llvm::PPC::PRED_EQ, llvm::PPC::PRED_NE, llvm::MachineBasicBlock::rbegin(), llvm::MachineBasicBlock::rend(), llvm::SmallVectorBase::size(), llvm::MachineBasicBlock::successors(), and TRI.
◆ analyzeCompare()
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override |
analyzeCompare - For a comparison instruction, return the source registers in SrcReg and SrcReg2 if having two register operands, and the value it compares against in CmpValue.
Return true if the comparison instruction can be analyzed.
Definition at line 3337 of file X86InstrInfo.cpp.
References llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), and llvm::MachineOperand::isImm().
◆ areLoadsFromSameBasePtr()
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override |
areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to determine if two loads are loading from the same base address.
It should only return true if the base pointers are the same and the only differences between the two addresses are the offset. It also returns the offsets by reference.
Definition at line 5655 of file X86InstrInfo.cpp.
References llvm::X86::AddrBaseReg, llvm::X86::AddrDisp, llvm::X86::AddrIndexReg, llvm::X86::AddrScaleAmt, llvm::X86::AddrSegmentReg, llvm::dyn_cast(), llvm::SDNode::getMachineOpcode(), llvm::SDNode::getOperand(), llvm::ConstantSDNode::getSExtValue(), I, and llvm::SDNode::isMachineOpcode().
◆ breakPartialRegDependency()
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override |
Definition at line 4583 of file X86InstrInfo.cpp.
References llvm::MachineInstrBuilder::addReg(), llvm::MachineInstr::addRegisterKilled(), llvm::BuildMI(), contains(), llvm::MachineInstr::getDebugLoc(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), llvm::MCRegisterInfo::getSubReg(), llvm::RegState::ImplicitDefine, llvm::MachineInstr::killsRegister(), MI, Reg, and llvm::RegState::Undef.
◆ buildOutlinedFrame()
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override |
Definition at line 7777 of file X86InstrInfo.cpp.
References llvm::BuildMI(), llvm::MachineBasicBlock::end(), llvm::outliner::OutlinedFunction::FrameConstructionID, llvm::MachineBasicBlock::insert(), and MachineOutlinerTailCall.
◆ canInsertSelect()
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override |
Definition at line 2873 of file X86InstrInfo.cpp.
References llvm::X86::COND_S, llvm::MachineBasicBlock::getParent(), llvm::MachineRegisterInfo::getRegClass(), llvm::MachineFunction::getRegInfo(), MRI, and llvm::ArrayRef< T >::size().
Referenced by insertBranch().
◆ canMakeTailCallConditional()
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override |
Definition at line 2449 of file X86InstrInfo.cpp.
References assert(), llvm::MachineOperand::getImm(), llvm::MachineFunction::getInfo(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), llvm::X86MachineFunctionInfo::getTCReturnAddrDelta(), llvm::MachineFunction::hasWinCFI(), llvm::X86Subtarget::isTargetWin64(), llvm::X86::LAST_VALID_COND, and llvm::SmallVectorBase::size().
Referenced by replaceBranchWithTailCall().
◆ classifyLEAReg()
| bool X86InstrInfo::classifyLEAReg | ( | MachineInstr & | MI, |
| const MachineOperand & | Src, | ||
| unsigned | LEAOpcode, | ||
| bool | AllowSP, | ||
| unsigned & | NewSrc, | ||
| bool & | isKill, | ||
| MachineOperand & | ImplicitOp, | ||
| LiveVariables * | LV | ||
| ) | const |
Given an operand within a MachineInstr, insert preceding code to put it into the right format for a particular kind of LEA instruction.
This may involve using an appropriate super-register instead (with an implicit use of the original) or creating a new virtual register and inserting COPY instructions to get the data into the right class.
Reference parameters are set to indicate how caller should add this operand to the LEA instruction.
Definition at line 740 of file X86InstrInfo.cpp.
References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::addRegOffset(), llvm::addRegReg(), assert(), llvm::BuildMI(), llvm::MachineRegisterInfo::constrainRegClass(), llvm::MachineRegisterInfo::createVirtualRegister(), llvm::RegState::Define, llvm::getDeadRegState(), llvm::MachineInstr::getDebugLoc(), llvm::MachineOperand::getImm(), llvm::ilist_node_impl< OptionsT >::getIterator(), llvm::getKillRegState(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), llvm::MachineRegisterInfo::getRegClass(), llvm::MachineFunction::getRegInfo(), llvm::TargetRegisterInfo::getRegSizeInBits(), llvm::MachineRegisterInfo::getTargetRegisterInfo(), llvm::LiveVariables::getVarInfo(), llvm::getX86SubSuperRegister(), llvm::X86Subtarget::is64Bit(), IsDead, llvm::MachineOperand::isDead(), llvm::MachineOperand::isKill(), llvm::TargetRegisterInfo::isPhysicalRegister(), llvm::MachineOperand::isUndef(), llvm::TargetRegisterInfo::isVirtualRegister(), llvm::RegState::Kill, llvm::LiveVariables::VarInfo::Kills, llvm_unreachable, MI, llvm::LiveVariables::replaceKillInstruction(), llvm::MachineOperand::setImplicit(), SubReg, and llvm::RegState::Undef.
Referenced by convertToThreeAddress().
◆ commuteInstructionImpl()
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overrideprotected |
Commutes the operands in the given instruction by changing the operands order and/or changing the instruction's opcode and/or the immediate value operand.
The arguments 'CommuteOpIdx1' and 'CommuteOpIdx2' specify the operands to be commuted.
Do not call this method for a non-commutable instruction or non-commutable operands. Even though the instruction is commutable, the method may still fail to commute the operands, null pointer is returned in such cases.
Definition at line 1475 of file X86InstrInfo.cpp.
References assert(), llvm::MachineFunction::CloneMachineInstr(), llvm::TargetInstrInfo::commuteInstructionImpl(), commuteVPTERNLOG(), llvm::MachineOperand::CreateImm(), getCommutedVPERMV3Opcode(), llvm::MachineInstr::getDesc(), llvm::getFMA3Group(), getFMA3OpcodeToCommuteOperands(), llvm::MachineFunction::getFunction(), llvm::MachineOperand::getImm(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), llvm::X86::getSwappedVPCMPImm(), llvm::X86::getSwappedVPCOMImm(), llvm::X86Subtarget::hasSSE2(), llvm::X86Subtarget::hasSSE41(), isCommutableVPERMV3Instruction(), llvm::X86II::isKMasked(), llvm::X86II::isKMergeMasked(), llvm::isMem(), LLVM_FALLTHROUGH, llvm_unreachable, llvm::BitmaskEnumDetail::Mask(), MI, llvm::Function::optForSize(), Size, and llvm::MCInstrDesc::TSFlags.
◆ convertToThreeAddress()
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override |
convertToThreeAddress - This method must be implemented by targets that set the M_CONVERTIBLE_TO_3_ADDR flag.
This method must be implemented by targets that set the M_CONVERTIBLE_TO_3_ADDR flag.
When this flag is set, the target may be able to convert a two-address instruction into a true three-address instruction on demand. This allows the X86 target (for example) to convert ADD and SHL instructions into LEA instructions if they would require register copies due to two-addressness.
This method returns a null pointer if the transformation cannot be performed, otherwise it returns the new instruction.
Definition at line 925 of file X86InstrInfo.cpp.
References llvm::ARM_AM::add, llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addImm(), llvm::addOffset(), llvm::MachineInstrBuilder::addReg(), llvm::addRegReg(), assert(), llvm::BuildMI(), classifyLEAReg(), llvm::MachineRegisterInfo::constrainRegClass(), llvm::MachineOperand::CreateReg(), llvm::MachineInstr::getDebugLoc(), llvm::ilist_node_impl< OptionsT >::getIterator(), llvm::getKillRegState(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), getTruncatedShiftCount(), hasLiveCondCodeDef(), llvm::X86Subtarget::is64Bit(), llvm::MachineOperand::isDead(), llvm::MachineOperand::isKill(), llvm::MachineOperand::isReg(), isTruncatedShiftCountForLEA(), llvm::MachineOperand::isUndef(), llvm::TargetRegisterInfo::isVirtualRegister(), llvm_unreachable, MI, and llvm::LiveVariables::replaceKillInstruction().
◆ copyPhysReg()
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override |
Definition at line 3006 of file X86InstrInfo.cpp.
References llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), contains(), CopyToFromAsymmetricReg(), llvm::dbgs(), llvm::getKillRegState(), llvm::TargetRegisterInfo::getMatchingSuperReg(), getRegisterInfo(), isHReg(), LLVM_DEBUG, llvm::report_fatal_error(), and TRI.
Referenced by tryOptimizeLEAtoMOV().
◆ decomposeMachineOperandsTargetFlags()
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override |
Definition at line 7369 of file X86InstrInfo.cpp.
◆ expandPostRAPseudo()
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override |
Definition at line 4131 of file X86InstrInfo.cpp.
References assert(), Expand2AddrKreg(), Expand2AddrUndef(), expandLoadStackGuard(), expandMOV32r1(), ExpandMOVImmSExti8(), expandNOVLXLoad(), expandNOVLXStore(), expandXorFP(), llvm::MCRegisterInfo::getEncodingValue(), llvm::TargetRegisterInfo::getMatchingSuperReg(), llvm::MachineInstr::getOpcode(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), getRegisterInfo(), llvm::getRegState(), llvm::MCRegisterInfo::getSubReg(), llvm::RegState::ImplicitDefine, MI, Reg, llvm::MachineInstr::RemoveOperand(), llvm::MachineInstr::setDesc(), TRI, and llvm::RegState::Undef.
◆ findCommutedOpIndices()
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override |
Returns true iff the routine could find two commutable operands in the given machine instruction.
The 'SrcOpIdx1' and 'SrcOpIdx2' are INPUT and OUTPUT arguments. Their input values can be re-defined in this method only if the input values are not pre-defined, which is designated by the special value 'CommuteAnyOperandIndex' assigned to it. If both of indices are pre-defined and refer to some operands, then the method simply returns true if the corresponding operands are commutable and returns false otherwise.
For example, calling this method this way: unsigned Op1 = 1, Op2 = CommuteAnyOperandIndex; findCommutedOpIndices(MI, Op1, Op2); can be interpreted as a query asking to find an operand that would be commutable with the operand#1.
Definition at line 1925 of file X86InstrInfo.cpp.
References llvm::TargetInstrInfo::findCommutedOpIndices(), llvm::MachineInstr::getDesc(), llvm::getFMA3Group(), llvm::MachineOperand::getImm(), llvm::MCInstrDesc::getNumDefs(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MCInstrDesc::getOperandConstraint(), llvm::X86Subtarget::hasSSE2(), llvm::X86Subtarget::hasSSE41(), llvm::MCInstrDesc::isCommutable(), llvm::X86InstrFMA3Group::isIntrinsic(), llvm::X86II::isKMasked(), llvm::X86II::isKMergeMasked(), llvm::MachineOperand::isReg(), llvm::MCOI::TIED_TO, and llvm::MCInstrDesc::TSFlags.
Referenced by foldMemoryOperandImpl().
◆ foldMemoryOperandImpl() [1/3]
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override |
foldMemoryOperand - If this target supports it, fold a load or store of the specified stack slot into the specified machine instruction for the specified operand(s).
If this is possible, the target should perform the folding and return true, otherwise it should return false. If it folds the instruction, it is likely that the MachineInstruction the iterator references has been changed.
Definition at line 4997 of file X86InstrInfo.cpp.
References llvm::MachineOperand::ChangeToImmediate(), llvm::MachineOperand::CreateFI(), llvm::MachineFunction::getFrameInfo(), llvm::MachineFunction::getFunction(), llvm::MachineFrameInfo::getObjectAlignment(), llvm::MachineFrameInfo::getObjectSize(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getSubReg(), hasPartialRegUpdate(), llvm::MachineOperand::isDef(), NoFusing, llvm::Function::optForSize(), llvm::MachineInstr::setDesc(), shouldPreventUndefRegUpdateMemFold(), and SubReg.
Referenced by computeBytesPoppedByCalleeForSRet(), and foldMemoryOperandImpl().
◆ foldMemoryOperandImpl() [2/3]
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override |
foldMemoryOperand - Same as the previous version except it allows folding of any load and store from / to any address, not just from a specific stack slot.
Definition at line 5181 of file X86InstrInfo.cpp.
References llvm::X86::AddrNumOperands, llvm::SmallVectorImpl< T >::append(), C, llvm::MachineOperand::ChangeToImmediate(), llvm::MachineOperand::CreateCPI(), llvm::MachineOperand::CreateImm(), llvm::MachineOperand::CreateReg(), foldMemoryOperandImpl(), llvm::ISD::FrameIndex, llvm::VectorType::get(), getAlignment(), llvm::Constant::getAllOnesValue(), llvm::TargetMachine::getCodeModel(), llvm::MachineFunction::getConstantPool(), llvm::MachineConstantPool::getConstantPoolIndex(), llvm::Function::getContext(), llvm::MachineInstr::getDesc(), llvm::Type::getDoubleTy(), llvm::Type::getFloatTy(), llvm::MachineFunction::getFunction(), llvm::Type::getInt32Ty(), llvm::Constant::getNullValue(), llvm::MCInstrDesc::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getSubReg(), llvm::MachineFunction::getTarget(), llvm::MachineInstr::hasOneMemOperand(), hasPartialRegUpdate(), isLoadFromStackSlot(), isNonFoldablePartialRegisterLoad(), llvm::TargetMachine::isPositionIndependent(), llvm::CodeModel::Kernel, llvm::MachineInstr::memoperands_begin(), NoFusing, llvm::MachineInstr::operands_begin(), llvm::Function::optForSize(), llvm::SmallVectorTemplateBase< T >::push_back(), llvm::MachineInstr::setDesc(), shouldPreventUndefRegUpdateMemFold(), and llvm::CodeModel::Small.
◆ foldMemoryOperandImpl() [3/3]
| MachineInstr * X86InstrInfo::foldMemoryOperandImpl | ( | MachineFunction & | MF, |
| MachineInstr & | MI, | ||
| unsigned | OpNum, | ||
| ArrayRef< MachineOperand > | MOs, | ||
| MachineBasicBlock::iterator | InsertPt, | ||
| unsigned | Size, | ||
| unsigned | Alignment, | ||
| bool | AllowCommute | ||
| ) | const |
Definition at line 4821 of file X86InstrInfo.cpp.
References llvm::X86::AddrDisp, llvm::X86::AddrNumOperands, llvm::dbgs(), llvm::X86MemoryFoldTableEntry::DstOp, llvm::MachineInstr::eraseFromParent(), findCommutedOpIndices(), llvm::X86MemoryFoldTableEntry::Flags, foldMemoryOperandImpl(), FuseInst(), FuseTwoAddrInst(), llvm::MachineInstr::getDesc(), llvm::MachineFunction::getFunction(), llvm::MCInstrDesc::getNumDefs(), llvm::MCInstrDesc::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MCInstrDesc::getOperandConstraint(), llvm::MachineOperand::getReg(), getRegClass(), llvm::TargetSubtargetInfo::getRegisterInfo(), llvm::TargetRegisterInfo::getRegSizeInBits(), llvm::MachineOperand::getSubReg(), llvm::MachineFunction::getSubtarget(), llvm::MachineOperand::getTargetFlags(), hasPartialRegUpdate(), I, llvm::MachineInstr::isCopy(), llvm::TargetRegisterInfo::isPhysicalRegister(), llvm::MachineOperand::isReg(), llvm::lookupFoldTable(), llvm::lookupTwoAddrFoldTable(), MakeM0Inst(), MI, llvm::MinAlign(), llvm::X86II::MO_GOT_ABSOLUTE_ADDRESS, llvm::X86II::MO_GOTTPOFF, llvm::Function::optForMinSize(), llvm::Function::optForSize(), PrintFailedFusing, llvm::MachineOperand::setReg(), llvm::MachineOperand::setSubReg(), shouldPreventUndefRegUpdateMemFold(), llvm::ArrayRef< T >::size(), llvm::TB_ALIGN_MASK, llvm::TB_ALIGN_SHIFT, llvm::MCOI::TIED_TO, and TRI.
◆ getExecutionDomain()
|
override |
Definition at line 6680 of file X86InstrInfo.cpp.
References llvm::MachineInstr::getDesc(), getExecutionDomainCustom(), llvm::MachineInstr::getOpcode(), lookup(), lookupAVX512(), llvm::X86II::SSEDomainShift, and llvm::MCInstrDesc::TSFlags.
◆ getExecutionDomainCustom()
| uint16_t X86InstrInfo::getExecutionDomainCustom | ( | const MachineInstr & | MI | ) | const |
Definition at line 6463 of file X86InstrInfo.cpp.
References AdjustBlendMask(), llvm::MachineInstr::getDesc(), llvm::MachineOperand::getImm(), llvm::MCInstrDesc::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::getSubReg(), and llvm::MachineOperand::isImm().
Referenced by getExecutionDomain().
◆ getFMA3OpcodeToCommuteOperands()
| unsigned X86InstrInfo::getFMA3OpcodeToCommuteOperands | ( | const MachineInstr & | MI, |
| unsigned | SrcOpIdx1, | ||
| unsigned | SrcOpIdx2, | ||
| const X86InstrFMA3Group & | FMA3Group | ||
| ) | const |
Returns an adjusted FMA opcode that must be used in FMA instruction that performs the same computations as the given MI but which has the operands SrcOpIdx1 and SrcOpIdx2 commuted.
It may return 0 if it is unsafe to commute the operands. Note that a machine instruction (instead of its opcode) is passed as the first parameter to make it possible to analyze the instruction's uses and commute the first operand of FMA even when it seems unsafe when you look at the opcode. For example, it is Ok to commute the first operand of VFMADD*SD_Int, if ONLY the lowest 64-bit element of the result is used.
The returned FMA opcode may differ from the opcode in the given MI. For example, commuting the operands #1 and #3 in the following FMA FMA213 #1, #2, #3 results into instruction with adjusted opcode: FMA231 #3, #2, #1
Definition at line 1305 of file X86InstrInfo.cpp.
References assert(), llvm::X86InstrFMA3Group::get132Opcode(), llvm::X86InstrFMA3Group::get213Opcode(), llvm::X86InstrFMA3Group::get231Opcode(), llvm::MachineInstr::getDesc(), llvm::MachineInstr::getOpcode(), getThreeSrcCommuteCase(), llvm::X86InstrFMA3Group::isIntrinsic(), and llvm::MCInstrDesc::TSFlags.
Referenced by commuteInstructionImpl().
◆ getFrameAdjustment()
|
inline |
Returns the stack pointer adjustment that happens inside the frame setup..destroy sequence (e.g.
by pushes, or inside the callee).
Definition at line 191 of file X86InstrInfo.h.
References assert(), llvm::MachineOperand::getImm(), and llvm::MachineInstr::getOperand().
Referenced by llvm::X86FrameLowering::eliminateCallFramePseudoInstr(), and getSPAdjust().
◆ getGlobalBaseReg()
| unsigned X86InstrInfo::getGlobalBaseReg | ( | MachineFunction * | MF | ) | const |
getGlobalBaseReg - Return a virtual register initialized with the the global base register value.
Return a virtual register initialized with the the global base register value.
Output instructions required to initialize the register in the function entry block, if necessary.
Output instructions required to initialize the register in the function entry block, if necessary.
TODO: Eliminate this and move the code to X86MachineFunctionInfo.
Definition at line 5912 of file X86InstrInfo.cpp.
References assert(), llvm::MachineRegisterInfo::createVirtualRegister(), llvm::TargetMachine::getCodeModel(), llvm::X86MachineFunctionInfo::getGlobalBaseReg(), llvm::MachineFunction::getInfo(), llvm::MachineFunction::getRegInfo(), llvm::MachineFunction::getTarget(), llvm::PPCISD::GlobalBaseReg, llvm::CodeModel::Large, llvm::CodeModel::Medium, and llvm::X86MachineFunctionInfo::setGlobalBaseReg().
Referenced by createPHIsForCMOVsInSinkBB(), getRetpolineSymbol(), and llvm::X86TargetLowering::needsFixedCatchObjects().
◆ getMemOperandWithOffset()
|
override |
Definition at line 3221 of file X86InstrInfo.cpp.
References llvm::X86::AddrBaseReg, llvm::X86::AddrDisp, llvm::X86::AddrIndexReg, llvm::X86::AddrScaleAmt, assert(), llvm::MachineInstr::getDesc(), llvm::MachineOperand::getImm(), llvm::X86II::getMemoryOperandNo(), llvm::MachineInstr::getOperand(), llvm::X86II::getOperandBias(), llvm::MachineOperand::getReg(), llvm::MachineOperand::isImm(), llvm::MachineOperand::isReg(), and llvm::MCInstrDesc::TSFlags.
◆ getNoop()
|
override |
Return the noop instruction to use for a noop.
Definition at line 6764 of file X86InstrInfo.cpp.
References llvm::MCInst::setOpcode().
◆ getOpcodeAfterMemoryUnfold()
|
override |
getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new instruction after load / store are unfolded from an instruction of the specified opcode.
It returns zero if the specified unfolding is not possible. If LoadRegIndex is non-null, it is filled in with the operand index of the operand which will hold the register holding the loaded value.
Definition at line 5637 of file X86InstrInfo.cpp.
References llvm::X86MemoryFoldTableEntry::DstOp, llvm::X86MemoryFoldTableEntry::Flags, I, llvm::lookupUnfoldTable(), llvm::TB_FOLDED_LOAD, llvm::TB_FOLDED_STORE, and llvm::TB_INDEX_MASK.
Referenced by getRegClassForUnfoldedLoad().
◆ getOutliningCandidateInfo()
|
overridevirtual |
Definition at line 7663 of file X86InstrInfo.cpp.
References C, llvm::MachineInstr::isDebugInstr(), llvm::MachineInstr::isKill(), MachineOutlinerDefault, and MachineOutlinerTailCall.
◆ getOutliningType()
|
override |
Definition at line 7718 of file X86InstrInfo.cpp.
References llvm::MachineInstr::getDesc(), llvm::MachineInstr::getParent(), llvm::MCInstrDesc::hasImplicitDefOfPhysReg(), llvm::MCInstrDesc::hasImplicitUseOfPhysReg(), llvm::outliner::Illegal, llvm::outliner::Invisible, llvm::MachineInstr::isDebugInstr(), llvm::MachineInstr::isIndirectDebugValue(), llvm::MachineInstr::isKill(), llvm::MachineInstr::isPosition(), llvm::MachineInstr::isReturn(), llvm::MachineInstr::isTerminator(), llvm::LegalizeActions::Legal, llvm::MachineInstr::modifiesRegister(), llvm::MachineInstr::operands(), llvm::MachineInstr::readsRegister(), and llvm::MachineBasicBlock::succ_empty().
◆ getPartialRegUpdateClearance()
|
override |
Inform the BreakFalseDeps pass how many idle instructions we would like before a partial register update.
Definition at line 4367 of file X86InstrInfo.cpp.
References llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), hasPartialRegUpdate(), llvm::TargetRegisterInfo::isVirtualRegister(), PartialRegUpdateClearance, llvm::MachineOperand::readsReg(), llvm::MachineInstr::readsRegister(), llvm::MachineInstr::readsVirtualRegister(), and Reg.
◆ getRegisterInfo()
|
inline |
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
As such, whenever a client has an instance of instruction info, it should always be able to get register info as well (through this method).
Definition at line 187 of file X86InstrInfo.h.
Referenced by analyzeBranchPredicate(), copyPhysReg(), expandPostRAPseudo(), getRegClassForUnfoldedLoad(), getRetpolineSymbol(), optimizeCompareInstr(), and replaceBranchWithTailCall().
◆ getSerializableDirectMachineOperandTargetFlags()
|
override |
Definition at line 7374 of file X86InstrInfo.cpp.
References llvm::MachineInstrBuilder::addExternalSymbol(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::MachineInstrBuilder::addSym(), llvm::MachineBasicBlock::begin(), llvm::BuildMI(), llvm::MachineRegisterInfo::createVirtualRegister(), llvm::MachineBasicBlock::findDebugLoc(), llvm::MachineFunction::front(), llvm::MachineFunctionPass::getAnalysisUsage(), llvm::TargetMachine::getCodeModel(), llvm::X86MachineFunctionInfo::getGlobalBaseReg(), llvm::MachineFunction::getInfo(), llvm::X86Subtarget::getInstrInfo(), llvm::MachineFunction::getPICBaseSymbol(), llvm::MachineFunction::getRegInfo(), llvm::MachineFunction::getSubtarget(), llvm::MachineFunction::getTarget(), llvm::PPCISD::GlobalBaseReg, llvm::X86Subtarget::is64Bit(), llvm::X86Subtarget::isPICStyleGOT(), llvm::TargetMachine::isPositionIndependent(), llvm::CodeModel::Kernel, llvm::RegState::Kill, llvm::CodeModel::Large, llvm_unreachable, llvm::makeArrayRef(), llvm::CodeModel::Medium, llvm::AArch64II::MO_COFFSTUB, llvm::X86II::MO_DARWIN_NONLAZY, llvm::X86II::MO_DARWIN_NONLAZY_PIC_BASE, llvm::AArch64II::MO_DLLIMPORT, llvm::X86II::MO_DTPOFF, llvm::AArch64II::MO_GOT, llvm::X86II::MO_GOT_ABSOLUTE_ADDRESS, llvm::X86II::MO_GOTNTPOFF, llvm::X86II::MO_GOTOFF, llvm::X86II::MO_GOTPCREL, llvm::X86II::MO_GOTTPOFF, llvm::SystemZII::MO_INDNTPOFF, llvm::X86II::MO_NTPOFF, llvm::X86II::MO_PIC_BASE_OFFSET, llvm::PPCII::MO_PLT, llvm::ARMII::MO_SECREL, llvm::MipsII::MO_TLSGD, llvm::X86II::MO_TLSLD, llvm::MipsII::MO_TLSLDM, llvm::X86II::MO_TLVP, llvm::X86II::MO_TLVP_PIC_BASE, llvm::X86II::MO_TPOFF, llvm::MachineInstr::setPreInstrSymbol(), llvm::AnalysisUsage::setPreservesCFG(), llvm::CodeModel::Small, TII, and llvm::SystemZISD::TM.
◆ getSPAdjust()
|
override |
getSPAdjust - This returns the stack pointer adjustment made by this instruction.
For x86, we need to handle more complex call sequences involving PUSHes.
Definition at line 139 of file X86InstrInfo.cpp.
References llvm::X86::AddrBaseReg, llvm::X86::AddrDisp, llvm::X86::AddrIndexReg, llvm::X86::AddrScaleAmt, llvm::alignTo(), E, llvm::MachineBasicBlock::end(), llvm::ISD::FrameIndex, getFrameAdjustment(), llvm::TargetSubtargetInfo::getFrameLowering(), llvm::MachineOperand::getImm(), llvm::MachineOperand::getIndex(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), llvm::TargetFrameLowering::getStackAlignment(), llvm::MachineFunction::getSubtarget(), I, llvm::MachineInstr::isCall(), llvm::MachineOperand::isFI(), llvm::MachineOperand::isImm(), llvm::MachineOperand::isReg(), and MI.
◆ getUndefRegClearance()
|
override |
Inform the BreakFalseDeps pass how many idle instructions we would like before certain undef register reads.
This catches the VCVTSI2SD family of instructions:
vcvtsi2sdq rax, undef xmm0, xmm14
We should to be careful not to catch VXOR idioms which are presumably handled specially in the pipeline:
vxorps undef xmm1, undef xmm1, xmm1
Like getPartialRegUpdateClearance, this makes a strong assumption that the high bits that are passed-through are not live.
Definition at line 4568 of file X86InstrInfo.cpp.
References llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), hasUndefRegUpdate(), llvm::TargetRegisterInfo::isPhysicalRegister(), llvm::MachineOperand::isUndef(), and UndefRegClearance.
◆ hasHighOperandLatency()
|
override |
Definition at line 7078 of file X86InstrInfo.cpp.
References llvm::MachineInstr::getOpcode(), and isHighLatencyDef().
◆ hasLiveCondCodeDef()
| bool X86InstrInfo::hasLiveCondCodeDef | ( | MachineInstr & | MI | ) | const |
True if MI has a condition code def, e.g.
True if MI has a condition code def, e.g. EFLAGS, that is not marked dead.
EFLAGS, that is not marked dead.
Definition at line 709 of file X86InstrInfo.cpp.
References llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::isDead(), llvm::MachineOperand::isDef(), and llvm::MachineOperand::isReg().
Referenced by convertToThreeAddress().
◆ hasReassociableOperands()
|
override |
◆ insertBranch()
|
override |
Definition at line 2812 of file X86InstrInfo.cpp.
References llvm::MachineInstrBuilder::addMBB(), assert(), llvm::BuildMI(), canInsertSelect(), llvm::X86::COND_E_AND_NP, llvm::X86::COND_NE_OR_P, llvm::ArrayRef< T >::empty(), GetCondBranchFromCond(), getFallThroughMBB(), and llvm::ArrayRef< T >::size().
Referenced by splitEdge().
◆ insertOutlinedCall()
|
override |
Definition at line 7792 of file X86InstrInfo.cpp.
References llvm::BuildMI(), llvm::outliner::Candidate::CallConstructionID, llvm::MachineFunction::getName(), llvm::Module::getNamedValue(), llvm::MachineBasicBlock::insert(), and MachineOutlinerTailCall.
◆ insertSelect()
|
override |
Definition at line 2909 of file X86InstrInfo.cpp.
References llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), llvm::X86::getCMovFromCond(), llvm::MachineBasicBlock::getParent(), llvm::MachineRegisterInfo::getRegClass(), llvm::MachineFunction::getRegInfo(), llvm::TargetRegisterInfo::getRegSizeInBits(), llvm::MachineRegisterInfo::getTargetRegisterInfo(), MRI, llvm::ArrayRef< T >::size(), and TRI.
◆ isAssociativeAndCommutative()
|
override |
Definition at line 7113 of file X86InstrInfo.cpp.
References llvm::MachineInstr::getOpcode(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), llvm::MachineFunction::getTarget(), llvm::TargetMachine::Options, and llvm::TargetOptions::UnsafeFPMath.
◆ isCoalescableExtInstr()
|
override |
isCoalescableExtInstr - Return true if the instruction is a "coalescable" extension instruction.
That is, it's like a copy where it's legal for the source to overlap the destination. e.g. X86::MOVSX64rr32. If this returns true, then it's expected the pre-extension value is available as a subreg of the result register. This also returns the sub-register index in SubIdx.
Definition at line 91 of file X86InstrInfo.cpp.
References llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::getSubReg(), llvm::X86Subtarget::is64Bit(), LLVM_FALLTHROUGH, and llvm_unreachable.
◆ isCopyInstrImpl()
|
overrideprotected |
If the specific machine instruction is a instruction that moves/copies value from one register to another register return true along with machine operand and machine operand.
Definition at line 3091 of file X86InstrInfo.cpp.
References llvm::MachineInstr::getOperand(), and llvm::MachineInstr::isMoveReg().
◆ isFunctionSafeToOutlineFrom()
|
override |
◆ isHighLatencyDef()
|
override |
Definition at line 6768 of file X86InstrInfo.cpp.
Referenced by hasHighOperandLatency().
◆ isLoadFromStackSlot() [1/2]
|
override |
Definition at line 391 of file X86InstrInfo.cpp.
References llvm::NVPTXISD::Dummy.
Referenced by foldMemoryOperandImpl(), isLoadFromStackSlotPostFE(), and MatchingStackOffset().
◆ isLoadFromStackSlot() [2/2]
|
override |
Definition at line 397 of file X86InstrInfo.cpp.
References llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::getSubReg(), and isFrameLoadOpcode().
◆ isLoadFromStackSlotPostFE()
|
override |
isLoadFromStackSlotPostFE - Check for post-frame ptr elimination stack locations as well.
This uses a heuristic so it isn't reliable for correctness.
Definition at line 406 of file X86InstrInfo.cpp.
References llvm::NVPTXISD::Dummy, llvm::SmallVectorTemplateCommon< T >::front(), llvm::MachineInstr::getOpcode(), llvm::MachineMemOperand::getPseudoValue(), isFrameLoadOpcode(), isLoadFromStackSlot(), and Reg.
◆ isReallyTriviallyReMaterializable()
|
override |
Definition at line 477 of file X86InstrInfo.cpp.
References llvm::X86::AddrBaseReg, llvm::X86::AddrDisp, llvm::X86::AddrIndexReg, llvm::X86::AddrScaleAmt, llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), llvm::MachineInstr::isDereferenceableInvariantLoad(), llvm::MachineOperand::isGlobal(), llvm::MachineOperand::isImm(), llvm::MachineOperand::isReg(), MRI, regIsPICBase(), and ReMatPICStubLoad.
◆ isSafeToClobberEFLAGS()
| bool X86InstrInfo::isSafeToClobberEFLAGS | ( | MachineBasicBlock & | MBB, |
| MachineBasicBlock::iterator | I | ||
| ) | const |
isSafeToClobberEFLAGS - Return true if it's safe insert an instruction tha would clobber the EFLAGS condition register.
Note the result may be conservative. If it cannot definitely determine the safety after visiting a few instructions in each direction it assumes it's not safe.
Definition at line 593 of file X86InstrInfo.cpp.
References B, llvm::MachineBasicBlock::begin(), llvm::MachineOperand::clobbersPhysReg(), E, llvm::MachineBasicBlock::end(), llvm::MachineOperand::getReg(), I, llvm::MachineOperand::isDead(), llvm::MachineOperand::isDef(), llvm::MachineOperand::isKill(), llvm::MachineBasicBlock::isLiveIn(), llvm::MachineOperand::isReg(), llvm::MachineOperand::isRegMask(), llvm::MachineOperand::isUse(), and llvm::MachineBasicBlock::successors().
Referenced by reMaterialize().
◆ isSafeToMoveRegClassDefs()
|
override |
isSafeToMoveRegClassDefs - Return true if it's safe to move a machine instruction that defines the specified register class.
Definition at line 5898 of file X86InstrInfo.cpp.
Referenced by reverseBranchCondition().
◆ isStoreToStackSlot() [1/2]
|
override |
Definition at line 425 of file X86InstrInfo.cpp.
References llvm::NVPTXISD::Dummy.
Referenced by isStoreToStackSlotPostFE().
◆ isStoreToStackSlot() [2/2]
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override |
Definition at line 431 of file X86InstrInfo.cpp.
References llvm::X86::AddrNumOperands, llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::getSubReg(), and isFrameStoreOpcode().
◆ isStoreToStackSlotPostFE()
|
override |
isStoreToStackSlotPostFE - Check for post-frame ptr elimination stack locations as well.
This uses a heuristic so it isn't reliable for correctness.
Definition at line 441 of file X86InstrInfo.cpp.
References llvm::NVPTXISD::Dummy, llvm::SmallVectorTemplateCommon< T >::front(), llvm::MachineInstr::getOpcode(), llvm::MachineMemOperand::getPseudoValue(), isFrameStoreOpcode(), isStoreToStackSlot(), and Reg.
◆ isSubregFoldable()
|
inlineoverride |
◆ isUnconditionalTailCall()
|
override |
Definition at line 2435 of file X86InstrInfo.cpp.
References llvm::MachineInstr::getOpcode().
◆ isUnpredicatedTerminator()
|
override |
Definition at line 2424 of file X86InstrInfo.cpp.
References llvm::MachineInstr::isBarrier(), llvm::MachineInstr::isBranch(), llvm::MachineInstr::isPredicable(), llvm::HexagonMCInstrInfo::isPredicated(), and llvm::MachineInstr::isTerminator().
Referenced by getFallThroughMBB().
◆ loadRegFromAddr()
| void X86InstrInfo::loadRegFromAddr | ( | MachineFunction & | MF, |
| unsigned | DestReg, | ||
| SmallVectorImpl< MachineOperand > & | Addr, | ||
| const TargetRegisterClass * | RC, | ||
| ArrayRef< MachineMemOperand *> | MMOs, | ||
| SmallVectorImpl< MachineInstr *> & | NewMIs | ||
| ) | const |
Definition at line 3320 of file X86InstrInfo.cpp.
References llvm::MachineInstrBuilder::add(), llvm::BuildMI(), llvm::ArrayRef< T >::empty(), llvm::ArrayRef< T >::front(), llvm::MachineMemOperand::getAlignment(), getLoadRegOpcode(), llvm::TargetSubtargetInfo::getRegisterInfo(), llvm::TargetRegisterInfo::getSpillSize(), llvm::MachineFunction::getSubtarget(), isAligned(), llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::MachineInstrBuilder::setMemRefs(), llvm::SmallVectorBase::size(), and TRI.
Referenced by unfoldMemoryOperand().
◆ loadRegFromStackSlot()
|
override |
Definition at line 3306 of file X86InstrInfo.cpp.
References llvm::addFrameReference(), llvm::BuildMI(), getLoadRegOpcode(), llvm::MachineBasicBlock::getParent(), llvm::TargetRegisterInfo::getSpillSize(), and isAligned().
Referenced by llvm::X86FrameLowering::restoreCalleeSavedRegisters().
◆ optimizeCompareInstr()
|
override |
optimizeCompareInstr - Check if there exists an earlier instruction that operates on the same source operands and sets flags in the same way as Compare; remove Compare if possible.
Check if there exists an earlier instruction that operates on the same source operands and sets flags in the same way as Compare; remove Compare if possible.
Definition at line 3600 of file X86InstrInfo.cpp.
References assert(), llvm::X86::COND_A, llvm::X86::COND_AE, llvm::X86::COND_B, llvm::X86::COND_BE, llvm::X86::COND_E, llvm::X86::COND_G, llvm::X86::COND_GE, llvm::X86::COND_INVALID, llvm::X86::COND_L, llvm::X86::COND_LE, llvm::X86::COND_NE, llvm::X86::COND_NO, llvm::X86::COND_NS, llvm::X86::COND_O, llvm::X86::COND_S, llvm::tgtok::Def, E, llvm::MachineBasicBlock::end(), llvm::MachineInstr::eraseFromParent(), llvm::X86::getCMovFromCond(), GetCondBranchFromCond(), llvm::X86::getCondFromBranchOpc(), llvm::X86::getCondFromCMovOpc(), llvm::X86::getCondFromSETOpc(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), GetOppositeBranchCondition(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), llvm::MachineRegisterInfo::getRegClass(), getRegisterInfo(), llvm::TargetRegisterInfo::getRegSizeInBits(), llvm::MachineInstrBundleIterator< Ty, IsReverse >::getReverse(), llvm::X86::getSETFromCond(), getSwappedCondition(), llvm::MachineRegisterInfo::getUniqueVRegDef(), llvm::MachineInstr::hasOneMemOperand(), I, llvm::MachineBasicBlock::insert(), llvm::MachineInstr::isBranch(), llvm::MachineOperand::isDef(), isDefConvertible(), isRedundantFlagInstr(), llvm::MachineOperand::isReg(), isUseDefConvertible(), llvm::MachineInstr::killsRegister(), llvm_unreachable, MI, llvm::MachineInstr::modifiesRegister(), llvm::MachineInstr::readsRegister(), llvm::MachineInstr::registerDefIsDead(), llvm::MachineBasicBlock::remove(), llvm::MachineInstr::RemoveOperand(), llvm::MachineBasicBlock::rend(), llvm::MachineInstr::setDesc(), llvm::MachineOperand::setIsDead(), llvm::Successor, llvm::MachineBasicBlock::successors(), TRI, and llvm::MachineRegisterInfo::use_nodbg_empty().
◆ optimizeLoadInstr()
|
override |
optimizeLoadInstr - Try to remove the load by folding it to a register operand at the use.
Try to remove the load by folding it to a register operand at the use.
We fold the load instructions if and only if the def and use are in the same BB. We only look at one load and see whether it can be folded into MI. FoldAsLoadDefReg is the virtual register defined by the load we are trying to fold. DefMI returns the machine instruction that defines FoldAsLoadDefReg, and the function returns the machine instruction generated due to folding.
We fold the load instructions if load defines a virtual register, the virtual register is used once in the same BB, and the instructions in-between do not load or store, and have no side effects.
Definition at line 3901 of file X86InstrInfo.cpp.
References assert(), llvm::SmallVectorBase::empty(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::getSubReg(), llvm::MachineRegisterInfo::getVRegDef(), llvm::MachineOperand::isDef(), llvm::MachineOperand::isReg(), llvm::MachineInstr::isSafeToMove(), llvm::SmallVectorTemplateBase< T >::push_back(), and Reg.
◆ reMaterialize()
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override |
Definition at line 670 of file X86InstrInfo.cpp.
References llvm::MachineInstrBuilder::add(), llvm::BuildMI(), llvm::MachineFunction::CloneMachineInstr(), llvm::MachineInstr::getDebugLoc(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getReg(), llvm::MachineBasicBlock::insert(), isSafeToClobberEFLAGS(), llvm_unreachable, llvm::MachineInstr::operands(), llvm::MachineInstr::substituteRegister(), and TRI.
◆ removeBranch()
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override |
Definition at line 2789 of file X86InstrInfo.cpp.
References assert(), llvm::MachineBasicBlock::begin(), llvm::X86::COND_INVALID, llvm::MachineBasicBlock::end(), llvm::X86::getCondFromBranchOpc(), and I.
◆ replaceBranchWithTailCall()
|
override |
Definition at line 2480 of file X86InstrInfo.cpp.
References llvm::LivePhysRegs::addLiveOuts(), assert(), llvm::MachineBasicBlock::begin(), llvm::BuildMI(), C, canMakeTailCallConditional(), llvm::RegState::Define, llvm::MachineBasicBlock::end(), llvm::MachineBasicBlock::findDebugLoc(), llvm::X86::getCondFromBranchOpc(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), getRegisterInfo(), I, llvm::RegState::Implicit, llvm::SmallVectorBase::size(), and llvm::LivePhysRegs::stepForward().
◆ reverseBranchCondition()
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override |
Definition at line 5890 of file X86InstrInfo.cpp.
References assert(), GetOppositeBranchCondition(), isSafeToMoveRegClassDefs(), and llvm::SmallVectorBase::size().
Referenced by shouldScheduleLoadsNear().
◆ setExecutionDomain()
|
override |
Definition at line 6718 of file X86InstrInfo.cpp.
References assert(), llvm::MachineInstr::getDesc(), llvm::MachineInstr::getOpcode(), lookup(), lookupAVX512(), ReplaceableInstrs, ReplaceableInstrsAVX2, ReplaceableInstrsAVX2InsertExtract, ReplaceableInstrsAVX512, ReplaceableInstrsAVX512DQ, ReplaceableInstrsAVX512DQMasked, llvm::MachineInstr::setDesc(), setExecutionDomainCustom(), llvm::X86II::SSEDomainShift, and llvm::MCInstrDesc::TSFlags.
◆ setExecutionDomainCustom()
| bool X86InstrInfo::setExecutionDomainCustom | ( | MachineInstr & | MI, |
| unsigned | Domain | ||
| ) | const |
Definition at line 6559 of file X86InstrInfo.cpp.
References AdjustBlendMask(), assert(), llvm::MachineInstr::getDesc(), llvm::MachineOperand::getImm(), llvm::MCInstrDesc::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::getSubReg(), llvm::MachineOperand::isImm(), lookup(), lookupAVX512(), ReplaceableCustomAVX512LogicInstrs, llvm::MachineInstr::setDesc(), llvm::MachineOperand::setImm(), llvm::X86II::SSEDomainShift, and llvm::MCInstrDesc::TSFlags.
Referenced by setExecutionDomain().
◆ setFrameAdjustment()
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inline |
Sets the stack pointer adjustment made inside the frame made up by this instruction.
Definition at line 200 of file X86InstrInfo.h.
References assert(), llvm::ISD::FrameIndex, llvm::MachineInstr::getOperand(), MI, llvm::MachineOperand::setImm(), llvm::MipsISD::TailCall, and TRI.
◆ setSpecialOperandAttr()
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override |
This is an architecture-specific helper function of reassociateOps.
Set special operand attributes for new instructions after reassociation.
Definition at line 7330 of file X86InstrInfo.cpp.
References assert(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::isDead(), llvm::MachineOperand::isReg(), and llvm::MachineOperand::setIsDead().
◆ shouldScheduleLoadsNear()
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override |
shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to determine (in conjunction with areLoadsFromSameBasePtr) if two loads should be scheduled togther.
On some targets if two loads are loading from addresses in the same cache line, it's better if they are scheduled together. This function takes two integers that represent the load offsets from the common base address. It returns true if it decides it's desirable to schedule the two loads together. "NumLoads" is the number of loads that have already been scheduled after Load1.
Definition at line 5841 of file X86InstrInfo.cpp.
References assert(), llvm::MVT::f32, llvm::MVT::f64, llvm::SDNode::getMachineOpcode(), llvm::EVT::getSimpleVT(), llvm::SDNode::getValueType(), llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i64, llvm::MVT::i8, reverseBranchCondition(), and llvm::MVT::SimpleTy.
◆ storeRegToAddr()
| void X86InstrInfo::storeRegToAddr | ( | MachineFunction & | MF, |
| unsigned | SrcReg, | ||
| bool | isKill, | ||
| SmallVectorImpl< MachineOperand > & | Addr, | ||
| const TargetRegisterClass * | RC, | ||
| ArrayRef< MachineMemOperand *> | MMOs, | ||
| SmallVectorImpl< MachineInstr *> & | NewMIs | ||
| ) | const |
Definition at line 3287 of file X86InstrInfo.cpp.
References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::ArrayRef< T >::empty(), llvm::ArrayRef< T >::front(), llvm::MachineMemOperand::getAlignment(), llvm::getKillRegState(), llvm::TargetSubtargetInfo::getRegisterInfo(), llvm::TargetRegisterInfo::getSpillSize(), getStoreRegOpcode(), llvm::MachineFunction::getSubtarget(), isAligned(), llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::MachineInstrBuilder::setMemRefs(), llvm::SmallVectorBase::size(), and TRI.
Referenced by unfoldMemoryOperand().
◆ storeRegToStackSlot()
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override |
Definition at line 3270 of file X86InstrInfo.cpp.
References llvm::addFrameReference(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), llvm::MachineFunction::getFrameInfo(), llvm::getKillRegState(), llvm::MachineFrameInfo::getObjectSize(), llvm::MachineBasicBlock::getParent(), llvm::TargetRegisterInfo::getSpillSize(), getStoreRegOpcode(), and isAligned().
Referenced by llvm::X86FrameLowering::spillCalleeSavedRegisters().
◆ unfoldMemoryOperand() [1/2]
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override |
unfoldMemoryOperand - Separate a single instruction which folded a load or a store or a load and a store into two or more instruction.
If this is possible, returns true as well as the new instructions by reference.
Definition at line 5396 of file X86InstrInfo.cpp.
References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addReg(), llvm::X86::AddrNumOperands, llvm::MachineOperand::ChangeToRegister(), llvm::MachineFunction::CreateMachineInstr(), llvm::RegState::Define, llvm::X86MemoryFoldTableEntry::DstOp, extractLoadMMOs(), extractStoreMMOs(), llvm::X86MemoryFoldTableEntry::Flags, llvm::getDeadRegState(), llvm::MachineInstr::getDebugLoc(), llvm::getDefRegState(), llvm::MachineOperand::getImm(), llvm::getKillRegState(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), getRegClass(), llvm::getUndefRegState(), llvm::MachineInstr::hasOneMemOperand(), I, llvm::RegState::Implicit, llvm::MachineOperand::isImplicit(), llvm::MachineOperand::isReg(), llvm_unreachable, loadRegFromAddr(), llvm::lookupUnfoldTable(), llvm::MachineInstr::memoperands(), llvm::SmallVectorTemplateBase< T >::push_back(), llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::MachineInstr::setDesc(), llvm::MachineOperand::setIsKill(), storeRegToAddr(), llvm::TB_FOLDED_LOAD, llvm::TB_FOLDED_STORE, and llvm::TB_INDEX_MASK.
◆ unfoldMemoryOperand() [2/2]
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override |
Definition at line 5514 of file X86InstrInfo.cpp.
References llvm::X86::AddrNumOperands, llvm::X86MemoryFoldTableEntry::DstOp, extractLoadMMOs(), extractStoreMMOs(), llvm::X86MemoryFoldTableEntry::Flags, getLoadRegOpcode(), llvm::SelectionDAG::getMachineFunction(), llvm::SelectionDAG::getMachineNode(), llvm::SDNode::getMachineOpcode(), llvm::MCInstrDesc::getNumDefs(), llvm::SDNode::getNumOperands(), llvm::SDNode::getNumValues(), llvm::SDNode::getOperand(), getRegClass(), llvm::TargetSubtargetInfo::getRegisterInfo(), llvm::TargetRegisterInfo::getSpillSize(), getStoreRegOpcode(), llvm::MachineFunction::getSubtarget(), llvm::SDNode::getValueType(), I, isAligned(), llvm::SDNode::isMachineOpcode(), llvm::isNullConstant(), llvm::TargetRegisterInfo::legalclasstypes_begin(), llvm_unreachable, llvm::SPII::Load, llvm::lookupUnfoldTable(), llvm::MCInstrDesc::NumDefs, llvm::MVT::Other, llvm::SmallVectorTemplateBase< T >::push_back(), llvm::SelectionDAG::setNodeMemRefs(), llvm::SPII::Store, llvm::TB_FOLDED_LOAD, llvm::TB_FOLDED_STORE, llvm::TB_INDEX_MASK, and TRI.
◆ useMachineCombiner()
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inlineoverride |
Definition at line 500 of file X86InstrInfo.h.
References C.
The documentation for this class was generated from the following files:
- lib/Target/X86/X86InstrInfo.h
- lib/Target/X86/X86InstrInfo.cpp
