#include "ARM.h"#include "ARMBaseInstrInfo.h"#include "ARMBaseRegisterInfo.h"#include "ARMConstantPoolValue.h"#include "ARMMachineFunctionInfo.h"#include "ARMSubtarget.h"#include "MCTargetDesc/ARMAddressingModes.h"#include "llvm/CodeGen/LivePhysRegs.h"#include "llvm/CodeGen/MachineFrameInfo.h"#include "llvm/CodeGen/MachineFunctionPass.h"
Go to the source code of this file.
Macros | |
| #define | DEBUG_TYPE "arm-pseudo" |
| #define | ARM_EXPAND_PSEUDO_NAME "ARM pseudo instruction expansion pass" |
Enumerations | |
| enum | NEONRegSpacing |
Functions | |
| INITIALIZE_PASS (ARMExpandPseudo, DEBUG_TYPE, ARM_EXPAND_PSEUDO_NAME, false, false) void ARMExpandPseudo | |
| TransferImpOps - Transfer implicit operands on the pseudo instruction to the instructions created from the expansion. More... | |
| static const NEONLdStTableEntry * | LookupNEONLdSt (unsigned Opcode) |
| LookupNEONLdSt - Search the NEONLdStTable for information about a NEON load or store pseudo instruction. More... | |
| static void | GetDSubRegs (unsigned Reg, NEONRegSpacing RegSpc, const TargetRegisterInfo *TRI, unsigned &D0, unsigned &D1, unsigned &D2, unsigned &D3) |
| GetDSubRegs - Get 4 D subregisters of a Q, QQ, or QQQQ register, corresponding to the specified register spacing. More... | |
| static bool | IsAnAddressOperand (const MachineOperand &MO) |
| static MachineOperand | makeImplicit (const MachineOperand &MO) |
| static void | addExclusiveRegPair (MachineInstrBuilder &MIB, MachineOperand &Reg, unsigned Flags, bool IsThumb, const TargetRegisterInfo *TRI) |
| ARM's ldrexd/strexd take a consecutive register pair (represented as a single GPRPair register), Thumb's take two separate registers so we need to extract the subregs from the pair. More... | |
Variables | |
| static cl::opt< bool > | VerifyARMPseudo ("verify-arm-pseudo-expand", cl::Hidden, cl::desc("Verify machine code after expanding ARM pseudos")) |
| static const NEONLdStTableEntry | NEONLdStTable [] |
Macro Definition Documentation
◆ ARM_EXPAND_PSEUDO_NAME
| #define ARM_EXPAND_PSEUDO_NAME "ARM pseudo instruction expansion pass" |
Definition at line 36 of file ARMExpandPseudoInsts.cpp.
◆ DEBUG_TYPE
| #define DEBUG_TYPE "arm-pseudo" |
Definition at line 30 of file ARMExpandPseudoInsts.cpp.
Enumeration Type Documentation
◆ NEONRegSpacing
| enum NEONRegSpacing |
Definition at line 111 of file ARMExpandPseudoInsts.cpp.
Function Documentation
◆ addExclusiveRegPair()
|
static |
ARM's ldrexd/strexd take a consecutive register pair (represented as a single GPRPair register), Thumb's take two separate registers so we need to extract the subregs from the pair.
Definition at line 1027 of file ARMExpandPseudoInsts.cpp.
References llvm::ARM_AM::add, llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addExternalSymbol(), llvm::MachineInstrBuilder::addGlobalAddress(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::MachineInstr::addRegisterKilled(), llvm::MachineBasicBlock::addSuccessor(), llvm::ARMCC::AL, llvm::ARM_AM::asr, assert(), llvm::MachineBasicBlock::begin(), llvm::ARCISD::BL, llvm::BuildMI(), llvm::MachineInstrBuilder::cloneMemRefs(), llvm::computeAndAddLiveIns(), llvm::condCodeOp(), llvm::ARMCP::CPValue, llvm::ARMConstantPoolConstant::Create(), llvm::ARMConstantPoolSymbol::Create(), llvm::MachineFunction::CreateMachineBasicBlock(), llvm::RegState::Define, E, llvm::emitARMRegPlusImmediate(), llvm::emitT2RegPlusImmediate(), llvm::emitThumbRegPlusImmediate(), llvm::MachineBasicBlock::end(), llvm::ARMCC::EQ, llvm::MachineBasicBlock::erase(), llvm::MachineInstr::eraseFromParent(), llvm::MachineBasicBlock::getBasicBlock(), llvm::MachineFunction::getConstantPool(), llvm::MachineConstantPool::getConstantPoolIndex(), llvm::Function::getContext(), llvm::getDeadRegState(), llvm::MachineInstr::getDebugLoc(), llvm::MachineFunction::getFrameInfo(), llvm::TargetSubtargetInfo::getFrameLowering(), llvm::ARMBaseRegisterInfo::getFrameRegister(), llvm::MachineFunction::getFunction(), llvm::MachineOperand::getGlobal(), llvm::MachineOperand::getImm(), llvm::MachineFunction::getInfo(), llvm::TargetSubtargetInfo::getInstrInfo(), llvm::ilist_node_impl< OptionsT >::getIterator(), llvm::getKillRegState(), llvm::MachineBasicBlock::getLastNonDebugInstr(), llvm::MachineFrameInfo::getMaxAlignment(), llvm::MachineOperand::getOffset(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), llvm::ARMBaseInstrInfo::getRegisterInfo(), llvm::ARM_AM::getSORegOpc(), llvm::MCRegisterInfo::getSubReg(), llvm::MachineFunction::getSubtarget(), llvm::MachineOperand::getSymbolName(), llvm::MachineOperand::getTargetFlags(), llvm::ARMCP::GOT_PREL, llvm::ARMBaseRegisterInfo::hasBasePointer(), llvm::TargetFrameLowering::hasFP(), llvm::RegState::ImplicitDefine, llvm::MachineFunction::insert(), llvm::MachineOperand::isDead(), llvm::MachineOperand::isGlobal(), llvm::MachineOperand::isKill(), llvm::MachineOperand::isSymbol(), llvm::MachineOperand::isUndef(), llvm::RegState::Kill, llvm_unreachable, llvm::ARM_AM::lsr, makeImplicit(), MI, llvm::ARMII::MO_GOT, llvm::ARMII::MO_HI16, llvm::ARMII::MO_LO16, Modified, llvm::ARMCC::NE, llvm::ARMCP::no_modifier, llvm::predOps(), R6, Reg, llvm::ARM_AM::rrx, llvm::ARMISD::RRX, llvm::MachineOperand::setIsKill(), TII, TRI, llvm::RegState::Undef, llvm::AArch64_AM::UXTB, llvm::AArch64_AM::UXTH, and VerifyARMPseudo.
◆ GetDSubRegs()
|
static |
GetDSubRegs - Get 4 D subregisters of a Q, QQ, or QQQQ register, corresponding to the specified register spacing.
Not all of the results are necessarily valid, e.g., a Q register only has 2 D subregisters.
Definition at line 436 of file ARMExpandPseudoInsts.cpp.
References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), llvm::RegState::Define, llvm::MachineInstr::eraseFromParent(), llvm::getDeadRegState(), llvm::MachineInstr::getDebugLoc(), llvm::MachineInstr::getDesc(), llvm::getKillRegState(), llvm::MCInstrDesc::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), llvm::MCRegisterInfo::getSubReg(), llvm::getUndefRegState(), llvm::RegState::Implicit, llvm::RegState::ImplicitDefine, llvm::MachineOperand::isDead(), llvm::MachineOperand::isKill(), llvm::MachineOperand::isUndef(), LookupNEONLdSt(), MI, llvm::MachineOperand::setImplicit(), SubReg, TII, and TRI.
◆ INITIALIZE_PASS()
| INITIALIZE_PASS | ( | ARMExpandPseudo | , |
| DEBUG_TYPE | , | ||
| ARM_EXPAND_PSEUDO_NAME | , | ||
| false | , | ||
| false | |||
| ) |
TransferImpOps - Transfer implicit operands on the pseudo instruction to the instructions created from the expansion.
Definition at line 86 of file ARMExpandPseudoInsts.cpp.
References assert(), llvm::MCInstrDesc::getNumOperands(), llvm::MachineOperand::getReg(), llvm::MachineOperand::isReg(), and llvm::MachineOperand::isUse().
◆ IsAnAddressOperand()
|
static |
Definition at line 779 of file ARMExpandPseudoInsts.cpp.
References llvm::MachineOperand::getType(), llvm_unreachable, llvm::MachineOperand::MO_BlockAddress, llvm::MachineOperand::MO_CFIIndex, llvm::MachineOperand::MO_CImmediate, llvm::MachineOperand::MO_ConstantPoolIndex, llvm::MachineOperand::MO_ExternalSymbol, llvm::MachineOperand::MO_FPImmediate, llvm::MachineOperand::MO_FrameIndex, llvm::MachineOperand::MO_GlobalAddress, llvm::MachineOperand::MO_Immediate, llvm::MachineOperand::MO_IntrinsicID, llvm::MachineOperand::MO_JumpTableIndex, llvm::MachineOperand::MO_MachineBasicBlock, llvm::MachineOperand::MO_MCSymbol, llvm::MachineOperand::MO_Metadata, llvm::MachineOperand::MO_Predicate, llvm::MachineOperand::MO_Register, llvm::MachineOperand::MO_RegisterLiveOut, llvm::MachineOperand::MO_RegisterMask, and llvm::MachineOperand::MO_TargetIndex.
Referenced by makeImplicit().
◆ LookupNEONLdSt()
LookupNEONLdSt - Search the NEONLdStTable for information about a NEON load or store pseudo instruction.
Definition at line 415 of file ARMExpandPseudoInsts.cpp.
References assert(), llvm::sys::path::begin(), llvm::sys::path::end(), I, and llvm::lower_bound().
Referenced by GetDSubRegs().
◆ makeImplicit()
|
static |
Definition at line 815 of file ARMExpandPseudoInsts.cpp.
References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addExternalSymbol(), llvm::MachineInstrBuilder::addGlobalAddress(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::MachineBasicBlock::addSuccessor(), llvm::ARMCC::AL, assert(), llvm::BuildMI(), llvm::MachineInstrBuilder::cloneMemRefs(), llvm::computeAndAddLiveIns(), llvm::condCodeOp(), llvm::MachineFunction::CreateMachineBasicBlock(), llvm::RegState::Define, llvm::MachineBasicBlock::end(), llvm::MachineInstr::eraseFromParent(), llvm::finalizeBundle(), llvm::MachineBasicBlock::getBasicBlock(), llvm::getDeadRegState(), llvm::MachineInstr::getDebugLoc(), llvm::MachineOperand::getGlobal(), llvm::MachineOperand::getImm(), llvm::getInstrPredicate(), llvm::ilist_node_impl< OptionsT >::getIterator(), llvm::getKillRegState(), llvm::MachineOperand::getOffset(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getReg(), llvm::ARM_AM::getSOImmTwoPartFirst(), llvm::ARM_AM::getSOImmTwoPartSecond(), llvm::MachineOperand::getSymbolName(), llvm::MachineOperand::getTargetFlags(), llvm::MachineOperand::getType(), llvm::MachineFunction::insert(), IsAnAddressOperand(), llvm::MachineOperand::isDead(), llvm::MachineOperand::isImm(), llvm::MachineOperand::isUndef(), llvm::RegState::Kill, MI, llvm::MachineOperand::MO_ExternalSymbol, llvm::ARMII::MO_HI16, llvm::MachineOperand::MO_Immediate, llvm::ARMII::MO_LO16, llvm::ARMCC::NE, llvm::predOps(), llvm::MachineOperand::setImplicit(), and TII.
Referenced by addExclusiveRegPair().
Variable Documentation
◆ NEONLdStTable
|
static |
Definition at line 152 of file ARMExpandPseudoInsts.cpp.
◆ VerifyARMPseudo
|
static |
Referenced by addExclusiveRegPair().
