LLVM  8.0.1
Public Member Functions | Static Public Member Functions | Protected Member Functions | List of all members
llvm::PPCInstrInfo Class Reference

#include "Target/PowerPC/PPCInstrInfo.h"

Inheritance diagram for llvm::PPCInstrInfo:
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Collaboration diagram for llvm::PPCInstrInfo:
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Public Member Functions

 PPCInstrInfo (PPCSubtarget &STI)
 
const PPCRegisterInfo & getRegisterInfo () const
 getRegisterInfo - TargetInstrInfo is a superset of MRegister info. More...
 
bool isXFormMemOp (unsigned Opcode) const
 
ScheduleHazardRecognizer * CreateTargetHazardRecognizer (const TargetSubtargetInfo *STI, const ScheduleDAG *DAG) const override
 CreateTargetHazardRecognizer - Return the hazard recognizer to use for this target when scheduling the DAG. More...
 
ScheduleHazardRecognizer * CreateTargetPostRAHazardRecognizer (const InstrItineraryData *II, const ScheduleDAG *DAG) const override
 CreateTargetPostRAHazardRecognizer - Return the postRA hazard recognizer to use for this target when scheduling the DAG. More...
 
unsigned getInstrLatency (const InstrItineraryData *ItinData, const MachineInstr &MI, unsigned *PredCost=nullptr) const override
 
int getOperandLatency (const InstrItineraryData *ItinData, const MachineInstr &DefMI, unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const override
 
int getOperandLatency (const InstrItineraryData *ItinData, SDNode *DefNode, unsigned DefIdx, SDNode *UseNode, unsigned UseIdx) const override
 
bool hasLowDefLatency (const TargetSchedModel &SchedModel, const MachineInstr &DefMI, unsigned DefIdx) const override
 
bool useMachineCombiner () const override
 
bool getMachineCombinerPatterns (MachineInstr &Root, SmallVectorImpl< MachineCombinerPattern > &P) const override
 Return true when there is potentially a faster code sequence for an instruction chain ending in <Root>. More...
 
bool isAssociativeAndCommutative (const MachineInstr &Inst) const override
 
bool isCoalescableExtInstr (const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg, unsigned &SubIdx) const override
 
unsigned isLoadFromStackSlot (const MachineInstr &MI, int &FrameIndex) const override
 
bool isReallyTriviallyReMaterializable (const MachineInstr &MI, AliasAnalysis *AA) const override
 
unsigned isStoreToStackSlot (const MachineInstr &MI, int &FrameIndex) const override
 
bool findCommutedOpIndices (MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const override
 
void insertNoop (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override
 
bool analyzeBranch (MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
 
unsigned removeBranch (MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
 
unsigned insertBranch (MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
 
bool canInsertSelect (const MachineBasicBlock &, ArrayRef< MachineOperand > Cond, unsigned, unsigned, int &, int &, int &) const override
 
void insertSelect (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, unsigned DstReg, ArrayRef< MachineOperand > Cond, unsigned TrueReg, unsigned FalseReg) const override
 
void copyPhysReg (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
 
void storeRegToStackSlot (MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
 
void loadRegFromStackSlot (MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
 
unsigned getStoreOpcodeForSpill (unsigned Reg, const TargetRegisterClass *RC=nullptr) const
 
unsigned getLoadOpcodeForSpill (unsigned Reg, const TargetRegisterClass *RC=nullptr) const
 
bool reverseBranchCondition (SmallVectorImpl< MachineOperand > &Cond) const override
 
bool FoldImmediate (MachineInstr &UseMI, MachineInstr &DefMI, unsigned Reg, MachineRegisterInfo *MRI) const override
 
bool isProfitableToIfCvt (MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, BranchProbability Probability) const override
 
bool isProfitableToIfCvt (MachineBasicBlock &TMBB, unsigned NumT, unsigned ExtraT, MachineBasicBlock &FMBB, unsigned NumF, unsigned ExtraF, BranchProbability Probability) const override
 
bool isProfitableToDupForIfCvt (MachineBasicBlock &MBB, unsigned NumCycles, BranchProbability Probability) const override
 
bool isProfitableToUnpredicate (MachineBasicBlock &TMBB, MachineBasicBlock &FMBB) const override
 
bool isPredicated (const MachineInstr &MI) const override
 
bool isUnpredicatedTerminator (const MachineInstr &MI) const override
 
bool PredicateInstruction (MachineInstr &MI, ArrayRef< MachineOperand > Pred) const override
 
bool SubsumesPredicate (ArrayRef< MachineOperand > Pred1, ArrayRef< MachineOperand > Pred2) const override
 
bool DefinesPredicate (MachineInstr &MI, std::vector< MachineOperand > &Pred) const override
 
bool isPredicable (const MachineInstr &MI) const override
 
bool analyzeCompare (const MachineInstr &MI, unsigned &SrcReg, unsigned &SrcReg2, int &Mask, int &Value) const override
 
bool optimizeCompareInstr (MachineInstr &CmpInstr, unsigned SrcReg, unsigned SrcReg2, int Mask, int Value, const MachineRegisterInfo *MRI) const override
 
unsigned getInstSizeInBytes (const MachineInstr &MI) const override
 GetInstSize - Return the number of bytes of code the specified instruction may be. More...
 
void getNoop (MCInst &NopInst) const override
 Return the noop instruction to use for a noop. More...
 
std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags (unsigned TF) const override
 
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags () const override
 
ArrayRef< std::pair< unsigned, const char * > > getSerializableBitmaskMachineOperandTargetFlags () const override
 
bool expandVSXMemPseudo (MachineInstr &MI) const
 
bool expandPostRAPseudo (MachineInstr &MI) const override
 
const TargetRegisterClass * updatedRC (const TargetRegisterClass *RC) const
 
bool isTOCSaveMI (const MachineInstr &MI) const
 
bool isSignOrZeroExtended (const MachineInstr &MI, bool SignExt, const unsigned PhiDepth) const
 
bool isSignExtended (const MachineInstr &MI, const unsigned depth=0) const
 Return true if the output of the instruction is always a sign-extended, i.e. More...
 
bool isZeroExtended (const MachineInstr &MI, const unsigned depth=0) const
 Return true if the output of the instruction is always zero-extended, i.e. More...
 
bool convertToImmediateForm (MachineInstr &MI, MachineInstr **KilledDef=nullptr) const
 
void replaceInstrWithLI (MachineInstr &MI, const LoadImmediateInfo &LII) const
 
void replaceInstrOperandWithImm (MachineInstr &MI, unsigned OpNo, int64_t Imm) const
 
bool instrHasImmForm (const MachineInstr &MI, ImmInstrInfo &III, bool PostRA) const
 

Static Public Member Functions

static bool isSameClassPhysRegCopy (unsigned Opcode)
 
static bool isVFRegister (unsigned Reg)
 
static bool isVRRegister (unsigned Reg)
 
static int getRecordFormOpcode (unsigned Opcode)
 
static unsigned getRegNumForOperand (const MCInstrDesc &Desc, unsigned Reg, unsigned OpNo)
 getRegNumForOperand - some operands use different numbering schemes for the same registers. More...
 

Protected Member Functions

MachineInstr * commuteInstructionImpl (MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const override
 Commutes the operands in the given instruction. More...
 

Detailed Description

Definition at line 117 of file PPCInstrInfo.h.

Constructor & Destructor Documentation

◆ PPCInstrInfo()

PPCInstrInfo::PPCInstrInfo ( PPCSubtarget &  STI)
explicit

Definition at line 101 of file PPCInstrInfo.cpp.

Member Function Documentation

◆ analyzeBranch()

bool PPCInstrInfo::analyzeBranch ( MachineBasicBlock &  MBB,
MachineBasicBlock *&  TBB,
MachineBasicBlock *&  FBB,
SmallVectorImpl< MachineOperand > &  Cond,
bool  AllowModify 
) const
override

Definition at line 483 of file PPCInstrInfo.cpp.

References B, llvm::PPCISD::BDNZ, llvm::PPCISD::BDZ, llvm::MachineBasicBlock::begin(), llvm::MachineOperand::CreateImm(), llvm::MachineOperand::CreateReg(), DisableCTRLoopAnal, llvm::MachineBasicBlock::end(), llvm::MachineBasicBlock::getLastNonDebugInstr(), llvm::MachineOperand::getMBB(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), I, llvm::MachineBasicBlock::isLayoutSuccessor(), llvm::MachineOperand::isMBB(), llvm::PPCSubtarget::isPPC64(), isUnpredicatedTerminator(), llvm::PPC::PRED_BIT_SET, llvm::PPC::PRED_BIT_UNSET, and llvm::SmallVectorTemplateBase< T >::push_back().

◆ analyzeCompare()

bool PPCInstrInfo::analyzeCompare ( const MachineInstr &  MI,
unsigned &  SrcReg,
unsigned &  SrcReg2,
int &  Mask,
int &  Value 
) const
override

Definition at line 1591 of file PPCInstrInfo.cpp.

References llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), and llvm::MachineOperand::getReg().

◆ canInsertSelect()

bool PPCInstrInfo::canInsertSelect ( const MachineBasicBlock &  MBB,
ArrayRef< MachineOperand >  Cond,
unsigned  TrueReg,
unsigned  FalseReg,
int &  CondCycles,
int &  TrueCycles,
int &  FalseCycles 
) const
override

Definition at line 743 of file PPCInstrInfo.cpp.

References llvm::MachineBasicBlock::getParent(), getReg(), llvm::MachineRegisterInfo::getRegClass(), llvm::MachineFunction::getRegInfo(), MRI, and llvm::ArrayRef< T >::size().

◆ commuteInstructionImpl()

MachineInstr * PPCInstrInfo::commuteInstructionImpl ( MachineInstr &  MI,
bool  NewMI,
unsigned  OpIdx1,
unsigned  OpIdx2 
) const
overrideprotected

Commutes the operands in the given instruction.

The commutable operands are specified by their indices OpIdx1 and OpIdx2.

Do not call this method for a non-commutable instruction or for non-commutable pair of operand indices OpIdx1 and OpIdx2. Even though the instruction is commutable, the method may still fail to commute the operands, null pointer is returned in such cases.

For example, we can commute rlwimi instructions, but only if the rotate amt is zero. We also have to munge the immediates a bit.

Definition at line 357 of file PPCInstrInfo.cpp.

References assert(), llvm::BuildMI(), llvm::TargetInstrInfo::commuteInstructionImpl(), llvm::RegState::Define, llvm::getDeadRegState(), llvm::MachineInstr::getDebugLoc(), llvm::MachineInstr::getDesc(), llvm::MachineOperand::getImm(), llvm::getKillRegState(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MCInstrDesc::getOperandConstraint(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), llvm::MachineOperand::getSubReg(), llvm::MachineOperand::isDead(), llvm::MachineOperand::isKill(), MI, llvm::MachineOperand::setImm(), llvm::MachineOperand::setIsKill(), llvm::MachineOperand::setReg(), llvm::MachineOperand::setSubReg(), and llvm::MCOI::TIED_TO.

◆ convertToImmediateForm()

bool PPCInstrInfo::convertToImmediateForm ( MachineInstr &  MI,
MachineInstr **  KilledDef = nullptr 
) const

Definition at line 2430 of file PPCInstrInfo.cpp.

References assert(), llvm::dbgs(), DefMI, llvm::MachineInstr::dump(), llvm::MachineOperand::getImm(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), llvm::APInt::getSExtValue(), llvm::MachineRegisterInfo::hasOneUse(), llvm::LoadImmediateInfo::Imm, instrHasImmForm(), llvm::MachineOperand::isImm(), llvm::isInt< 16 >(), llvm::MachineOperand::isKill(), llvm::MachineRegisterInfo::isSSA(), llvm::isUInt< 16 >(), LLVM_DEBUG, llvm::BitmaskEnumDetail::Mask(), MRI, replaceInstrOperandWithImm(), replaceInstrWithLI(), llvm::APInt::rotl(), selectReg(), llvm::MachineOperand::setImm(), llvm::MachineRegisterInfo::use_empty(), and llvm::MachineRegisterInfo::use_instructions().

◆ copyPhysReg()

void PPCInstrInfo::copyPhysReg ( MachineBasicBlock &  MBB,
MachineBasicBlock::iterator  I,
const DebugLoc &  DL,
unsigned  DestReg,
unsigned  SrcReg,
bool  KillSrc 
) const
override

Definition at line 892 of file PPCInstrInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), contains(), getCRBitValue(), llvm::getCRFromCRBit(), llvm::MCRegisterInfo::getEncodingValue(), llvm::getKillRegState(), llvm::TargetRegisterInfo::getMatchingSuperReg(), llvm::MCInstrDesc::getNumOperands(), getRegisterInfo(), llvm::PPCSubtarget::hasP9Vector(), llvm::RegState::Kill, llvm_unreachable, llvm::PPCISD::MFOCRF, OR, TRI, and VSXSelfCopyCrash.

◆ CreateTargetHazardRecognizer()

ScheduleHazardRecognizer * PPCInstrInfo::CreateTargetHazardRecognizer ( const TargetSubtargetInfo *  STI,
const ScheduleDAG *  DAG 
) const
override

CreateTargetHazardRecognizer - Return the hazard recognizer to use for this target when scheduling the DAG.

Definition at line 110 of file PPCInstrInfo.cpp.

References llvm::TargetInstrInfo::CreateTargetHazardRecognizer(), llvm::PPC::DIR_440, llvm::PPC::DIR_A2, llvm::PPC::DIR_E500mc, and llvm::PPC::DIR_E5500.

◆ CreateTargetPostRAHazardRecognizer()

ScheduleHazardRecognizer * PPCInstrInfo::CreateTargetPostRAHazardRecognizer ( const InstrItineraryData *  II,
const ScheduleDAG *  DAG 
) const
override

CreateTargetPostRAHazardRecognizer - Return the postRA hazard recognizer to use for this target when scheduling the DAG.

Definition at line 127 of file PPCInstrInfo.cpp.

References assert(), llvm::PPC::DIR_440, llvm::PPC::DIR_A2, llvm::PPC::DIR_E500mc, llvm::PPC::DIR_E5500, llvm::PPC::DIR_PWR7, llvm::PPC::DIR_PWR8, llvm::MachineFunction::getSubtarget(), llvm::ScheduleDAG::MF, and llvm::ScheduleDAG::TII.

◆ decomposeMachineOperandsTargetFlags()

std::pair< unsigned, unsigned > PPCInstrInfo::decomposeMachineOperandsTargetFlags ( unsigned  TF) const
override

Definition at line 2011 of file PPCInstrInfo.cpp.

References llvm::BitmaskEnumDetail::Mask(), and llvm::PPCII::MO_ACCESS_MASK.

◆ DefinesPredicate()

bool PPCInstrInfo::DefinesPredicate ( MachineInstr &  MI,
std::vector< MachineOperand > &  Pred 
) const
override

Definition at line 1539 of file PPCInstrInfo.cpp.

References llvm::array_lengthof(), llvm::TargetRegisterClass::begin(), llvm::MachineOperand::clobbersPhysReg(), llvm::TargetRegisterClass::contains(), llvm::TargetRegisterClass::end(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), I, llvm::ARM_PROC::IE, llvm::MachineOperand::isDef(), llvm::MachineOperand::isReg(), and llvm::MachineOperand::isRegMask().

◆ expandPostRAPseudo()

bool PPCInstrInfo::expandPostRAPseudo ( MachineInstr &  MI) const
override

Definition at line 2114 of file PPCInstrInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), contains(), expandVSXMemPseudo(), llvm::MachineInstr::getDebugLoc(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), isAnImmediateOperand(), llvm::MachineOperand::isReg(), llvm::ARM_MB::LD, MI, llvm::PPC::PRED_NE_MINUS, R2, Reg, llvm::MachineInstr::RemoveOperand(), and llvm::MachineInstr::setDesc().

◆ expandVSXMemPseudo()

bool PPCInstrInfo::expandVSXMemPseudo ( MachineInstr &  MI) const

Definition at line 2048 of file PPCInstrInfo.cpp.

References llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::PPCISD::LFIWAX, llvm::PPCISD::LFIWZX, llvm_unreachable, llvm::MachineInstr::setDesc(), and llvm::PPCISD::STFIWX.

Referenced by expandPostRAPseudo().

◆ findCommutedOpIndices()

bool PPCInstrInfo::findCommutedOpIndices ( MachineInstr &  MI,
unsigned &  SrcOpIdx1,
unsigned &  SrcOpIdx2 
) const
override

Definition at line 441 of file PPCInstrInfo.cpp.

References llvm::TargetInstrInfo::findCommutedOpIndices(), llvm::PPC::getAltVSXFMAOpcode(), and llvm::MachineInstr::getOpcode().

◆ FoldImmediate()

bool PPCInstrInfo::FoldImmediate ( MachineInstr &  UseMI,
MachineInstr &  DefMI,
unsigned  Reg,
MachineRegisterInfo *  MRI 
) const
override

Definition at line 1309 of file PPCInstrInfo.cpp.

References assert(), llvm::MachineInstr::eraseFromParent(), llvm::MachineInstr::getDesc(), llvm::MachineOperand::getImm(), llvm::MCInstrDesc::getNumOperands(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineRegisterInfo::hasOneNonDBGUse(), llvm::MachineOperand::isImm(), llvm::PPCSubtarget::isPPC64(), llvm::MCInstrDesc::isPseudo(), llvm::MachineOperand::isReg(), llvm::MCInstrDesc::OpInfo, Reg, and llvm::MachineOperand::setReg().

◆ getInstrLatency()

unsigned PPCInstrInfo::getInstrLatency ( const InstrItineraryData *  ItinData,
const MachineInstr &  MI,
unsigned *  PredCost = nullptr 
) const
override

Definition at line 147 of file PPCInstrInfo.cpp.

References llvm::MachineInstr::getDesc(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOperand(), llvm::InstrItineraryData::getOperandCycle(), llvm::MCInstrDesc::getSchedClass(), llvm::MachineOperand::isDef(), llvm::MachineOperand::isImplicit(), llvm::MachineOperand::isReg(), llvm::Latency, llvm::max(), and UseOldLatencyCalc.

Referenced by getOperandLatency().

◆ getInstSizeInBytes()

unsigned PPCInstrInfo::getInstSizeInBytes ( const MachineInstr &  MI) const
override

GetInstSize - Return the number of bytes of code the specified instruction may be.

This returns the maximum number of bytes.

Definition at line 1992 of file PPCInstrInfo.cpp.

References llvm::TargetMachine::getMCAsmInfo(), llvm::StackMapOpers::getNumPatchBytes(), llvm::PatchPointOpers::getNumPatchBytes(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getSymbolName(), llvm::MachineFunction::getTarget(), and llvm::ISD::INLINEASM.

Referenced by llvm::PPCTargetLowering::getPrefLoopAlignment(), and INITIALIZE_PASS().

◆ getLoadOpcodeForSpill()

unsigned PPCInstrInfo::getLoadOpcodeForSpill ( unsigned  Reg,
const TargetRegisterClass *  RC = nullptr 
) const

Definition at line 1099 of file PPCInstrInfo.cpp.

References llvm::addFrameReference(), llvm::BuildMI(), contains(), llvm::MachineFunction::getInfo(), llvm::getKillRegState(), getStoreOpcodeForSpill(), isXFormMemOp(), llvm_unreachable, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::PPCFunctionInfo::setHasNonRISpills(), llvm::PPCFunctionInfo::setHasSpills(), llvm::PPCFunctionInfo::setSpillsCR(), llvm::PPCFunctionInfo::setSpillsVRSAVE(), SOK_CRBitSpill, SOK_CRSpill, SOK_Float4Spill, SOK_Float8Spill, SOK_Int4Spill, SOK_Int8Spill, SOK_QuadBitSpill, SOK_QuadFloat4Spill, SOK_QuadFloat8Spill, SOK_SPE4Spill, SOK_SPESpill, SOK_SpillToVSR, SOK_VectorFloat4Spill, SOK_VectorFloat8Spill, SOK_VRSaveSpill, SOK_VRVectorSpill, and SOK_VSXVectorSpill.

Referenced by storeRegToStackSlot().

◆ getMachineCombinerPatterns()

bool PPCInstrInfo::getMachineCombinerPatterns ( MachineInstr &  Root,
SmallVectorImpl< MachineCombinerPattern > &  P 
) const
override

Return true when there is potentially a faster code sequence for an instruction chain ending in <Root>.

All potential patterns are output in the <Pattern> array.

Definition at line 269 of file PPCInstrInfo.cpp.

References llvm::CodeGenOpt::Aggressive, llvm::TargetInstrInfo::getMachineCombinerPatterns(), llvm::TargetMachine::getOptLevel(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), llvm::MachineFunction::getTarget(), llvm::PPCSubtarget::getTargetMachine(), llvm::TargetMachine::Options, and llvm::TargetOptions::UnsafeFPMath.

◆ getNoop()

void PPCInstrInfo::getNoop ( MCInst &  NopInst) const
override

Return the noop instruction to use for a noop.

Definition at line 476 of file PPCInstrInfo.cpp.

References llvm::MCInst::setOpcode().

◆ getOperandLatency() [1/2]

int PPCInstrInfo::getOperandLatency ( const InstrItineraryData *  ItinData,
const MachineInstr &  DefMI,
unsigned  DefIdx,
const MachineInstr &  UseMI,
unsigned  UseIdx 
) const
override

Definition at line 177 of file PPCInstrInfo.cpp.

References llvm::PPC::DIR_7400, llvm::PPC::DIR_750, llvm::PPC::DIR_970, llvm::PPC::DIR_E5500, llvm::PPC::DIR_PWR4, llvm::PPC::DIR_PWR5, llvm::PPC::DIR_PWR5X, llvm::PPC::DIR_PWR6, llvm::PPC::DIR_PWR6X, llvm::PPC::DIR_PWR7, llvm::PPC::DIR_PWR8, llvm::PPCSubtarget::getDarwinDirective(), getInstrLatency(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), llvm::MachineRegisterInfo::getRegClass(), llvm::MachineFunction::getRegInfo(), llvm::TargetRegisterClass::hasSuperClassEq(), llvm::MachineInstr::isBranch(), llvm::TargetRegisterInfo::isVirtualRegister(), llvm::Latency, MRI, and Reg.

◆ getOperandLatency() [2/2]

int llvm::PPCInstrInfo::getOperandLatency ( const InstrItineraryData *  ItinData,
SDNode *  DefNode,
unsigned  DefIdx,
SDNode *  UseNode,
unsigned  UseIdx 
) const
inlineoverride

Definition at line 221 of file PPCInstrInfo.h.

◆ getRecordFormOpcode()

int PPCInstrInfo::getRecordFormOpcode ( unsigned  Opcode)
static

Definition at line 3496 of file PPCInstrInfo.cpp.

Referenced by selectI64Imm().

◆ getRegisterInfo()

const PPCRegisterInfo& llvm::PPCInstrInfo::getRegisterInfo ( ) const
inline

getRegisterInfo - TargetInstrInfo is a superset of MRegister info.

As such, whenever a client has an instance of instruction info, it should always be able to get register info as well (through this method).

Definition at line 190 of file PPCInstrInfo.h.

Referenced by copyPhysReg(), optimizeCompareInstr(), replaceInstrOperandWithImm(), replaceInstrWithLI(), and swapMIOperands().

◆ getRegNumForOperand()

static unsigned llvm::PPCInstrInfo::getRegNumForOperand ( const MCInstrDesc &  Desc,
unsigned  Reg,
unsigned  OpNo 
)
inlinestatic

getRegNumForOperand - some operands use different numbering schemes for the same registers.

For example, a VSX instruction may have any of vs0-vs63 allocated whereas an Altivec instruction could only have vs32-vs63 allocated (numbered as v0-v31). This function returns the actual register number needed for the opcode/operand number combination. The operand number argument will be useful when we need to extend this to instructions that use both Altivec and VSX numbering (for different operands).

Definition at line 430 of file PPCInstrInfo.h.

References Reg, llvm::MCInstrDesc::TSFlags, and llvm::PPCII::UseVSXReg.

Referenced by llvm::PPCMCCodeEmitter::getMachineOpValue(), and llvm::PPCInstPrinter::printOperand().

◆ getSerializableBitmaskMachineOperandTargetFlags()

ArrayRef< std::pair< unsigned, const char * > > PPCInstrInfo::getSerializableBitmaskMachineOperandTargetFlags ( ) const
override

Definition at line 2032 of file PPCInstrInfo.cpp.

References llvm::makeArrayRef(), llvm::PPCII::MO_NLP_FLAG, llvm::PPCII::MO_NLP_HIDDEN_FLAG, llvm::PPCII::MO_PIC_FLAG, and llvm::PPCII::MO_PLT.

◆ getSerializableDirectMachineOperandTargetFlags()

ArrayRef< std::pair< unsigned, const char * > > PPCInstrInfo::getSerializableDirectMachineOperandTargetFlags ( ) const
override

Definition at line 2017 of file PPCInstrInfo.cpp.

References llvm::makeArrayRef(), llvm::MipsII::MO_DTPREL_LO, llvm::PPCII::MO_HA, llvm::AVRII::MO_LO, llvm::AArch64II::MO_TLS, llvm::PPCII::MO_TLSLD_LO, llvm::PPCII::MO_TOC_LO, llvm::PPCII::MO_TPREL_HA, and llvm::MipsII::MO_TPREL_LO.

◆ getStoreOpcodeForSpill()

unsigned PPCInstrInfo::getStoreOpcodeForSpill ( unsigned  Reg,
const TargetRegisterClass *  RC = nullptr 
) const

Definition at line 1012 of file PPCInstrInfo.cpp.

References contains(), llvm_unreachable, SOK_CRBitSpill, SOK_CRSpill, SOK_Float4Spill, SOK_Float8Spill, SOK_Int4Spill, SOK_Int8Spill, SOK_QuadBitSpill, SOK_QuadFloat4Spill, SOK_QuadFloat8Spill, SOK_SPE4Spill, SOK_SPESpill, SOK_SpillToVSR, SOK_VectorFloat4Spill, SOK_VectorFloat8Spill, SOK_VRSaveSpill, SOK_VRVectorSpill, and SOK_VSXVectorSpill.

Referenced by getLoadOpcodeForSpill().

◆ hasLowDefLatency()

bool llvm::PPCInstrInfo::hasLowDefLatency ( const TargetSchedModel &  SchedModel,
const MachineInstr &  DefMI,
unsigned  DefIdx 
) const
inlineoverride

Definition at line 228 of file PPCInstrInfo.h.

◆ insertBranch()

unsigned PPCInstrInfo::insertBranch ( MachineBasicBlock &  MBB,
MachineBasicBlock *  TBB,
MachineBasicBlock *  FBB,
ArrayRef< MachineOperand >  Cond,
const DebugLoc &  DL,
int *  BytesAdded = nullptr 
) const
override

Definition at line 690 of file PPCInstrInfo.cpp.

References llvm::ARM_AM::add, llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMBB(), assert(), B, llvm::PPCISD::BDNZ, llvm::PPCISD::BDZ, llvm::BuildMI(), llvm::ArrayRef< T >::empty(), getReg(), llvm::PPCSubtarget::isPPC64(), llvm::PPC::PRED_BIT_SET, llvm::PPC::PRED_BIT_UNSET, and llvm::ArrayRef< T >::size().

◆ insertNoop()

void PPCInstrInfo::insertNoop ( MachineBasicBlock &  MBB,
MachineBasicBlock::iterator  MI 
) const
override

Definition at line 456 of file PPCInstrInfo.cpp.

References llvm::BuildMI(), llvm::PPC::DIR_PWR6, llvm::PPC::DIR_PWR7, llvm::PPC::DIR_PWR8, llvm::PPC::DIR_PWR9, and llvm::PPCSubtarget::getDarwinDirective().

◆ insertSelect()

void PPCInstrInfo::insertSelect ( MachineBasicBlock &  MBB,
MachineBasicBlock::iterator  MI,
const DebugLoc &  DL,
unsigned  DstReg,
ArrayRef< MachineOperand >  Cond,
unsigned  TrueReg,
unsigned  FalseReg 
) const
override

Definition at line 780 of file PPCInstrInfo.cpp.

References llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), llvm::TargetRegisterClass::contains(), llvm::MachineBasicBlock::getParent(), getReg(), llvm::MachineFunction::getRegInfo(), MRI, llvm::PPC::PRED_BIT_SET, llvm::PPC::PRED_BIT_UNSET, llvm::PPC::PRED_EQ, llvm::PPC::PRED_EQ_MINUS, llvm::PPC::PRED_EQ_PLUS, llvm::PPC::PRED_GE, llvm::PPC::PRED_GE_MINUS, llvm::PPC::PRED_GE_PLUS, llvm::PPC::PRED_GT, llvm::PPC::PRED_GT_MINUS, llvm::PPC::PRED_GT_PLUS, llvm::PPC::PRED_LE, llvm::PPC::PRED_LE_MINUS, llvm::PPC::PRED_LE_PLUS, llvm::PPC::PRED_LT, llvm::PPC::PRED_LT_MINUS, llvm::PPC::PRED_LT_PLUS, llvm::PPC::PRED_NE, llvm::PPC::PRED_NE_MINUS, llvm::PPC::PRED_NE_PLUS, llvm::PPC::PRED_NU, llvm::PPC::PRED_NU_MINUS, llvm::PPC::PRED_NU_PLUS, llvm::PPC::PRED_UN, llvm::PPC::PRED_UN_MINUS, llvm::PPC::PRED_UN_PLUS, and llvm::ArrayRef< T >::size().

◆ instrHasImmForm()

bool PPCInstrInfo::instrHasImmForm ( const MachineInstr &  MI,
ImmInstrInfo &  III,
bool  PostRA 
) const

Definition at line 2676 of file PPCInstrInfo.cpp.

References llvm::ISD::ADDC, llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::ImmInstrInfo::ImmMustBeMultipleOf, llvm::ImmInstrInfo::ImmOpcode, llvm::ImmInstrInfo::ImmOpNo, llvm::ImmInstrInfo::ImmWidth, llvm::ImmInstrInfo::IsCommutative, llvm::ImmInstrInfo::IsSummingOperands, isVFReg(), llvm::ARM_MB::LD, LLVM_FALLTHROUGH, llvm_unreachable, llvm::ImmInstrInfo::OpNoForForwarding, OR, llvm::ImmInstrInfo::SignedImm, llvm::ImmInstrInfo::TruncateImmTo, llvm::ISD::XOR, llvm::ImmInstrInfo::ZeroIsSpecialNew, and llvm::ImmInstrInfo::ZeroIsSpecialOrig.

Referenced by convertToImmediateForm(), and replaceInstrWithLI().

◆ isAssociativeAndCommutative()

bool PPCInstrInfo::isAssociativeAndCommutative ( const MachineInstr &  Inst) const
override

Definition at line 235 of file PPCInstrInfo.cpp.

References llvm::ISD::FADD, llvm::ISD::FMUL, and llvm::MachineInstr::getOpcode().

◆ isCoalescableExtInstr()

bool PPCInstrInfo::isCoalescableExtInstr ( const MachineInstr &  MI,
unsigned &  SrcReg,
unsigned &  DstReg,
unsigned &  SubIdx 
) const
override

Definition at line 285 of file PPCInstrInfo.cpp.

References llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), and llvm::MachineOperand::getReg().

◆ isLoadFromStackSlot()

unsigned PPCInstrInfo::isLoadFromStackSlot ( const MachineInstr &  MI,
int &  FrameIndex 
) const
override

Definition at line 300 of file PPCInstrInfo.cpp.

References llvm::MachineInstr::getOpcode().

◆ isPredicable()

bool PPCInstrInfo::isPredicable ( const MachineInstr &  MI) const
override

Definition at line 1575 of file PPCInstrInfo.cpp.

References B, llvm::PPCISD::BCTRL, and llvm::MachineInstr::getOpcode().

◆ isPredicated()

bool PPCInstrInfo::isPredicated ( const MachineInstr &  MI) const
override

Definition at line 1400 of file PPCInstrInfo.cpp.

Referenced by isUnpredicatedTerminator().

◆ isProfitableToDupForIfCvt()

bool llvm::PPCInstrInfo::isProfitableToDupForIfCvt ( MachineBasicBlock &  MBB,
unsigned  NumCycles,
BranchProbability  Probability 
) const
inlineoverride

Definition at line 330 of file PPCInstrInfo.h.

◆ isProfitableToIfCvt() [1/2]

bool llvm::PPCInstrInfo::isProfitableToIfCvt ( MachineBasicBlock &  MBB,
unsigned  NumCycles,
unsigned  ExtraPredCycles,
BranchProbability  Probability 
) const
inlineoverride

Definition at line 318 of file PPCInstrInfo.h.

◆ isProfitableToIfCvt() [2/2]

bool PPCInstrInfo::isProfitableToIfCvt ( MachineBasicBlock &  TMBB,
unsigned  NumT,
unsigned  ExtraT,
MachineBasicBlock &  FMBB,
unsigned  NumF,
unsigned  ExtraF,
BranchProbability  Probability 
) const
override

Definition at line 1391 of file PPCInstrInfo.cpp.

References MBBDefinesCTR().

◆ isProfitableToUnpredicate()

bool llvm::PPCInstrInfo::isProfitableToUnpredicate ( MachineBasicBlock &  TMBB,
MachineBasicBlock &  FMBB 
) const
inlineoverride

Definition at line 335 of file PPCInstrInfo.h.

References llvm::HexagonMCInstrInfo::isPredicated(), and llvm::BitmaskEnumDetail::Mask().

◆ isReallyTriviallyReMaterializable()

bool PPCInstrInfo::isReallyTriviallyReMaterializable ( const MachineInstr &  MI,
AliasAnalysis *  AA 
) const
override

Definition at line 320 of file PPCInstrInfo.cpp.

References llvm::MachineInstr::getOpcode(), llvm_unreachable, and llvm::PPCISD::QVGPCI.

◆ isSameClassPhysRegCopy()

static bool llvm::PPCInstrInfo::isSameClassPhysRegCopy ( unsigned  Opcode)
inlinestatic

Definition at line 195 of file PPCInstrInfo.h.

References OR, and UseMI.

◆ isSignExtended()

bool llvm::PPCInstrInfo::isSignExtended ( const MachineInstr &  MI,
const unsigned  depth = 0 
) const
inline

Return true if the output of the instruction is always a sign-extended, i.e.

0 to 31-th bits are same as 32-th bit.

Definition at line 403 of file PPCInstrInfo.h.

Referenced by optimizeCompareInstr().

◆ isSignOrZeroExtended()

bool PPCInstrInfo::isSignOrZeroExtended ( const MachineInstr &  MI,
bool  SignExt,
const unsigned  PhiDepth 
) const

Definition at line 3628 of file PPCInstrInfo.cpp.

References llvm::ISD::AND, assert(), llvm::AMDGPU::HSAMD::Kernel::Key::Attrs, D, llvm::dyn_cast(), E, llvm::Function::getAttributes(), llvm::MachineBasicBlock::getBasicBlock(), llvm::IntegerType::getBitWidth(), llvm::Function::getEntryBlock(), llvm::MachineFunction::getFunction(), llvm::MachineOperand::getGlobal(), llvm::MachineFunction::getInfo(), llvm::MachineInstr::getNumOperands(), getOpcode(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), llvm::AttributeList::getRetAttributes(), llvm::Function::getReturnType(), llvm::MachineFunction::getSubtarget(), llvm::MachineRegisterInfo::getVRegDef(), llvm::AttributeSet::hasAttribute(), I, llvm::MachineBasicBlock::instr_begin(), llvm::MachineInstr::isCall(), llvm::MachineOperand::isGlobal(), llvm::MachineRegisterInfo::isLiveIn(), llvm::PPCFunctionInfo::isLiveInSExt(), llvm::PPCFunctionInfo::isLiveInZExt(), llvm::MachineOperand::isReg(), isSignExtendingOp(), llvm::PPCSubtarget::isSVR4ABI(), llvm::TargetRegisterInfo::isVirtualRegister(), isZeroExtendingOp(), MRI, OR, llvm::Attribute::SExt, and llvm::Attribute::ZExt.

◆ isStoreToStackSlot()

unsigned PPCInstrInfo::isStoreToStackSlot ( const MachineInstr &  MI,
int &  FrameIndex 
) const
override

Definition at line 341 of file PPCInstrInfo.cpp.

References llvm::MachineInstr::getOpcode().

◆ isTOCSaveMI()

bool PPCInstrInfo::isTOCSaveMI ( const MachineInstr &  MI) const

Definition at line 3611 of file PPCInstrInfo.cpp.

References llvm::MachineOperand::getImm(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::isImm(), and llvm::MachineOperand::isReg().

◆ isUnpredicatedTerminator()

bool PPCInstrInfo::isUnpredicatedTerminator ( const MachineInstr &  MI) const
override

Definition at line 1411 of file PPCInstrInfo.cpp.

References llvm::MachineInstr::isBarrier(), llvm::MachineInstr::isBranch(), isPredicated(), and llvm::MachineInstr::isTerminator().

Referenced by analyzeBranch().

◆ isVFRegister()

static bool llvm::PPCInstrInfo::isVFRegister ( unsigned  Reg)
inlinestatic

Definition at line 387 of file PPCInstrInfo.h.

◆ isVRRegister()

static bool llvm::PPCInstrInfo::isVRRegister ( unsigned  Reg)
inlinestatic

Definition at line 390 of file PPCInstrInfo.h.

◆ isXFormMemOp()

bool llvm::PPCInstrInfo::isXFormMemOp ( unsigned  Opcode) const
inline

Definition at line 192 of file PPCInstrInfo.h.

References llvm::PPCII::XFormMemOp.

Referenced by getLoadOpcodeForSpill(), and storeRegToStackSlot().

◆ isZeroExtended()

bool llvm::PPCInstrInfo::isZeroExtended ( const MachineInstr &  MI,
const unsigned  depth = 0 
) const
inline

Return true if the output of the instruction is always zero-extended, i.e.

0 to 31-th bits are all zeros

Definition at line 409 of file PPCInstrInfo.h.

Referenced by optimizeCompareInstr().

◆ loadRegFromStackSlot()

void PPCInstrInfo::loadRegFromStackSlot ( MachineBasicBlock &  MBB,
MachineBasicBlock::iterator  MBBI,
unsigned  DestReg,
int  FrameIndex,
const TargetRegisterClass *  RC,
const TargetRegisterInfo *  TRI 
) const
override

Definition at line 1262 of file PPCInstrInfo.cpp.

References llvm::SmallVectorTemplateCommon< T, typename >::back(), llvm::MachineBasicBlock::end(), llvm::MachinePointerInfo::getFixedStack(), llvm::MachineFunction::getFrameInfo(), llvm::MachineFunction::getInfo(), llvm::MachineFunction::getMachineMemOperand(), llvm::MachineFrameInfo::getObjectAlignment(), llvm::MachineFrameInfo::getObjectSize(), llvm::MachineBasicBlock::getParent(), llvm::PPCSubtarget::hasVSX(), llvm::MachineBasicBlock::insert(), llvm::MachineMemOperand::MOLoad, reverseBranchCondition(), llvm::PPCFunctionInfo::setHasSpills(), and llvm::SmallVectorBase::size().

Referenced by llvm::PPCFrameLowering::restoreCalleeSavedRegisters().

◆ optimizeCompareInstr()

bool PPCInstrInfo::optimizeCompareInstr ( MachineInstr &  CmpInstr,
unsigned  SrcReg,
unsigned  SrcReg2,
int  Mask,
int  Value,
const MachineRegisterInfo *  MRI 
) const
override

Definition at line 1621 of file PPCInstrInfo.cpp.

References llvm::MachineInstr::addOperand(), llvm::MachineInstrBuilder::addReg(), assert(), B, llvm::MachineBasicBlock::begin(), llvm::BuildMI(), llvm::MachineInstr::clearRegisterDeads(), llvm::MachineOperand::CreateReg(), llvm::MachineInstr::definesRegister(), DisableCmpOpt, E, llvm::MachineBasicBlock::end(), llvm::MachineInstr::eraseFromParent(), first, llvm::MachineInstr::getDebugLoc(), llvm::MachineOperand::getImm(), llvm::MCInstrDesc::getImplicitDefs(), llvm::MCInstrDesc::getImplicitUses(), llvm::PPC::getNonRecordFormOpcode(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), llvm::PPC::getPredicate(), llvm::PPC::getPredicateCondition(), llvm::PPC::getPredicateHint(), llvm::MachineOperand::getReg(), getRegisterInfo(), llvm::MachineOperand::getSubReg(), llvm::PPC::getSwappedPredicate(), llvm::MachineRegisterInfo::getUniqueVRegDef(), llvm::MachineRegisterInfo::hasOneUse(), I, llvm::ARM_PROC::IE, llvm::MCInstrDesc::ImplicitDefs, llvm::MCInstrDesc::ImplicitUses, llvm::PPCSubtarget::isPPC64(), isSignExtended(), isZeroExtended(), llvm::RegState::Kill, MI, llvm::MachineInstr::modifiesRegister(), llvm::PPC::PRED_EQ, llvm::PPC::PRED_GE, llvm::PPC::PRED_GT, llvm::PPC::PRED_LE, llvm::PPC::PRED_LT, llvm::PPC::PRED_NE, llvm::SmallVectorTemplateBase< T >::push_back(), llvm::MachineInstr::readsRegister(), llvm::MachineInstr::RemoveOperand(), llvm::MachineInstr::setDesc(), llvm::MachineOperand::setImm(), llvm::SmallVectorBase::size(), TRI, llvm::MachineRegisterInfo::use_empty(), llvm::MachineRegisterInfo::use_instr_begin(), llvm::MachineRegisterInfo::use_instr_end(), and UseMI.

◆ PredicateInstruction()

bool PPCInstrInfo::PredicateInstruction ( MachineInstr &  MI,
ArrayRef< MachineOperand >  Pred 
) const
override

Definition at line 1422 of file PPCInstrInfo.cpp.

References llvm::ARM_AM::add, B, llvm::PPCISD::BCTRL, llvm::PPCISD::BDNZ, llvm::PPCISD::BDZ, llvm::MachineOperand::getMBB(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), getReg(), llvm::PPCSubtarget::isPPC64(), llvm_unreachable, MI, llvm::PPC::PRED_BIT_SET, llvm::PPC::PRED_BIT_UNSET, llvm::MachineInstr::RemoveOperand(), and llvm::MachineInstr::setDesc().

◆ removeBranch()

unsigned PPCInstrInfo::removeBranch ( MachineBasicBlock &  MBB,
int *  BytesRemoved = nullptr 
) const
override

Definition at line 658 of file PPCInstrInfo.cpp.

References assert(), B, llvm::PPCISD::BDNZ, llvm::PPCISD::BDZ, llvm::MachineBasicBlock::begin(), llvm::MachineBasicBlock::end(), llvm::MachineBasicBlock::getLastNonDebugInstr(), and I.

◆ replaceInstrOperandWithImm()

void PPCInstrInfo::replaceInstrOperandWithImm ( MachineInstr &  MI,
unsigned  OpNo,
int64_t  Imm 
) const

Definition at line 2251 of file PPCInstrInfo.cpp.

References assert(), llvm::MachineOperand::ChangeToImmediate(), llvm::empty(), llvm::MachineInstr::findRegisterUseOperandIdx(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), getRegisterInfo(), llvm::MachineInstr::implicit_operands(), llvm::MachineOperand::isImplicit(), llvm::MachineOperand::isReg(), llvm::MachineInstr::RemoveOperand(), and TRI.

Referenced by convertToImmediateForm(), and swapMIOperands().

◆ replaceInstrWithLI()

void PPCInstrInfo::replaceInstrWithLI ( MachineInstr &  MI,
const LoadImmediateInfo &  LII 
) const

Definition at line 2282 of file PPCInstrInfo.cpp.

References llvm::MachineInstrBuilder::addReg(), contains(), DefMI, E, llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), getRegisterInfo(), llvm::MachineRegisterInfo::getVRegDef(), llvm::LoadImmediateInfo::Imm, llvm::RegState::ImplicitDefine, instrHasImmForm(), llvm::LoadImmediateInfo::Is64Bit, llvm::MachineOperand::isImplicit(), llvm::MachineOperand::isReg(), llvm::MachineRegisterInfo::isSSA(), llvm::MachineOperand::isUse(), llvm::TargetRegisterInfo::isVirtualRegister(), llvm::ARM_MB::LD, llvm::TargetRegisterInfo::lookThruCopyLike(), llvm::PPCISD::LXVD2X, MI, MRI, OR, Reg, llvm::MachineInstr::RemoveOperand(), llvm::MachineBasicBlock::rend(), llvm::LoadImmediateInfo::SetCR, llvm::MachineInstr::setDesc(), SOK_LastOpcodeSpill, llvm::PPCISD::STXVD2X, and TRI.

Referenced by convertToImmediateForm(), and swapMIOperands().

◆ reverseBranchCondition()

bool PPCInstrInfo::reverseBranchCondition ( SmallVectorImpl< MachineOperand > &  Cond) const
override

Definition at line 1299 of file PPCInstrInfo.cpp.

References assert(), getReg(), llvm::PPC::InvertPredicate(), and llvm::SmallVectorBase::size().

Referenced by loadRegFromStackSlot().

◆ storeRegToStackSlot()

void PPCInstrInfo::storeRegToStackSlot ( MachineBasicBlock &  MBB,
MachineBasicBlock::iterator  MBBI,
unsigned  SrcReg,
bool  isKill,
int  FrameIndex,
const TargetRegisterClass *  RC,
const TargetRegisterInfo *  TRI 
) const
override

Definition at line 1209 of file PPCInstrInfo.cpp.

References llvm::addFrameReference(), llvm::SmallVectorTemplateCommon< T, typename >::back(), llvm::BuildMI(), llvm::MachinePointerInfo::getFixedStack(), llvm::MachineFunction::getFrameInfo(), llvm::MachineFunction::getInfo(), getLoadOpcodeForSpill(), llvm::MachineFunction::getMachineMemOperand(), llvm::MachineFrameInfo::getObjectAlignment(), llvm::MachineFrameInfo::getObjectSize(), llvm::MachineBasicBlock::getParent(), llvm::MachineBasicBlock::insert(), isXFormMemOp(), llvm::MachineMemOperand::MOStore, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::PPCFunctionInfo::setHasNonRISpills(), llvm::PPCFunctionInfo::setSpillsCR(), llvm::PPCFunctionInfo::setSpillsVRSAVE(), llvm::SmallVectorBase::size(), and updatedRC().

Referenced by llvm::PPCFrameLowering::spillCalleeSavedRegisters().

◆ SubsumesPredicate()

bool PPCInstrInfo::SubsumesPredicate ( ArrayRef< MachineOperand >  Pred1,
ArrayRef< MachineOperand >  Pred2 
) const
override

Definition at line 1508 of file PPCInstrInfo.cpp.

References assert(), getReg(), llvm::PPC::PRED_EQ, llvm::PPC::PRED_GE, llvm::PPC::PRED_GT, llvm::PPC::PRED_LE, llvm::PPC::PRED_LT, and llvm::ArrayRef< T >::size().

◆ updatedRC()

const TargetRegisterClass * PPCInstrInfo::updatedRC ( const TargetRegisterClass *  RC) const

Definition at line 3490 of file PPCInstrInfo.cpp.

Referenced by storeRegToStackSlot().

◆ useMachineCombiner()

bool llvm::PPCInstrInfo::useMachineCombiner ( ) const
inlineoverride

Definition at line 237 of file PPCInstrInfo.h.

References llvm::ISD::FrameIndex, I, MRI, P, Reg, and TRI.

The documentation for this class was generated from the following files:
Generated on Sun Dec 20 2020 14:12:30 for LLVM by   doxygen 1.8.13