Define some predicates that are used for node matching. More...

Enumerations
enum	Fixups { fixup_ppc_br24 = FirstTargetFixupKind, fixup_ppc_brcond14, fixup_ppc_br24abs, fixup_ppc_brcond14abs, fixup_ppc_half16, fixup_ppc_half16ds, fixup_ppc_nofixup, LastTargetFixupKind, NumTargetFixupKinds = LastTargetFixupKind - FirstTargetFixupKind }

enum	Predicate { PRED_LT = (0 << 5) \| 12, PRED_LE = (1 << 5) \| 4, PRED_EQ = (2 << 5) \| 12, PRED_GE = (0 << 5) \| 4, PRED_GT = (1 << 5) \| 12, PRED_NE = (2 << 5) \| 4, PRED_UN = (3 << 5) \| 12, PRED_NU = (3 << 5) \| 4, PRED_LT_MINUS = (0 << 5) \| 14, PRED_LE_MINUS = (1 << 5) \| 6, PRED_EQ_MINUS = (2 << 5) \| 14, PRED_GE_MINUS = (0 << 5) \| 6, PRED_GT_MINUS = (1 << 5) \| 14, PRED_NE_MINUS = (2 << 5) \| 6, PRED_UN_MINUS = (3 << 5) \| 14, PRED_NU_MINUS = (3 << 5) \| 6, PRED_LT_PLUS = (0 << 5) \| 15, PRED_LE_PLUS = (1 << 5) \| 7, PRED_EQ_PLUS = (2 << 5) \| 15, PRED_GE_PLUS = (0 << 5) \| 7, PRED_GT_PLUS = (1 << 5) \| 15, PRED_NE_PLUS = (2 << 5) \| 7, PRED_UN_PLUS = (3 << 5) \| 15, PRED_NU_PLUS = (3 << 5) \| 7, PRED_SPE = PRED_GT, PRED_BIT_SET = 1024, PRED_BIT_UNSET = 1025 }
	Predicate - These are "(BI << 5) \| BO" for various predicates. More...

enum	BranchHintBit { BR_NO_HINT = 0x0, BR_NONTAKEN_HINT = 0x2, BR_TAKEN_HINT = 0x3, BR_HINT_MASK = 0X3 }

enum	{ DIR_NONE, DIR_32, DIR_440, DIR_601, DIR_602, DIR_603, DIR_7400, DIR_750, DIR_970, DIR_A2, DIR_E500, DIR_E500mc, DIR_E5500, DIR_PWR3, DIR_PWR4, DIR_PWR5, DIR_PWR5X, DIR_PWR6, DIR_PWR6X, DIR_PWR7, DIR_PWR8, DIR_PWR9, DIR_64 }

Functions
Predicate	InvertPredicate (Predicate Opcode)
	Invert the specified predicate. != -> ==, < -> >=. More...

Predicate	getSwappedPredicate (Predicate Opcode)
	Assume the condition register is set by MI(a,b), return the predicate if we modify the instructions such that condition register is set by MI(b,a). More...

unsigned	getPredicateCondition (Predicate Opcode)
	Return the condition without hint bits. More...

unsigned	getPredicateHint (Predicate Opcode)
	Return the hint bits of the predicate. More...

Predicate	getPredicate (unsigned Condition, unsigned Hint)
	Return predicate consisting of specified condition and hint bits. More...

int	getNonRecordFormOpcode (uint16_t)

bool	isVPKUHUMShuffleMask (ShuffleVectorSDNode *N, unsigned ShuffleKind, SelectionDAG &DAG)
	isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a VPKUHUM instruction. More...

bool	isVPKUWUMShuffleMask (ShuffleVectorSDNode *N, unsigned ShuffleKind, SelectionDAG &DAG)
	isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a VPKUWUM instruction. More...

bool	isVPKUDUMShuffleMask (ShuffleVectorSDNode *N, unsigned ShuffleKind, SelectionDAG &DAG)
	isVPKUDUMShuffleMask - Return true if this is the shuffle mask for a VPKUDUM instruction. More...

bool	isVMRGLShuffleMask (ShuffleVectorSDNode *N, unsigned UnitSize, unsigned ShuffleKind, SelectionDAG &DAG)
	isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for a VRGL* instruction with the specified unit size (1,2 or 4 bytes). More...

bool	isVMRGHShuffleMask (ShuffleVectorSDNode *N, unsigned UnitSize, unsigned ShuffleKind, SelectionDAG &DAG)
	isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for a VRGH* instruction with the specified unit size (1,2 or 4 bytes). More...

bool	isVMRGEOShuffleMask (ShuffleVectorSDNode *N, bool CheckEven, unsigned ShuffleKind, SelectionDAG &DAG)
	isVMRGEOShuffleMask - Return true if this is a shuffle mask suitable for a VMRGEW or VMRGOW instruction More...

bool	isXXSLDWIShuffleMask (ShuffleVectorSDNode *N, unsigned &ShiftElts, bool &Swap, bool IsLE)
	isXXSLDWIShuffleMask - Return true if this is a shuffle mask suitable for a XXSLDWI instruction. More...

bool	isXXBRHShuffleMask (ShuffleVectorSDNode *N)
	isXXBRHShuffleMask - Return true if this is a shuffle mask suitable for a XXBRH instruction. More...

bool	isXXBRWShuffleMask (ShuffleVectorSDNode *N)
	isXXBRWShuffleMask - Return true if this is a shuffle mask suitable for a XXBRW instruction. More...

bool	isXXBRDShuffleMask (ShuffleVectorSDNode *N)
	isXXBRDShuffleMask - Return true if this is a shuffle mask suitable for a XXBRD instruction. More...

bool	isXXBRQShuffleMask (ShuffleVectorSDNode *N)
	isXXBRQShuffleMask - Return true if this is a shuffle mask suitable for a XXBRQ instruction. More...

bool	isXXPERMDIShuffleMask (ShuffleVectorSDNode *N, unsigned &ShiftElts, bool &Swap, bool IsLE)
	isXXPERMDIShuffleMask - Return true if this is a shuffle mask suitable for a XXPERMDI instruction. More...

int	isVSLDOIShuffleMask (SDNode *N, unsigned ShuffleKind, SelectionDAG &DAG)
	isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift amount, otherwise return -1. More...

bool	isSplatShuffleMask (ShuffleVectorSDNode *N, unsigned EltSize)
	isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand specifies a splat of a single element that is suitable for input to VSPLTB/VSPLTH/VSPLTW. More...

bool	isXXINSERTWMask (ShuffleVectorSDNode *N, unsigned &ShiftElts, unsigned &InsertAtByte, bool &Swap, bool IsLE)
	isXXINSERTWMask - Return true if this VECTOR_SHUFFLE can be handled by the XXINSERTW instruction introduced in ISA 3.0. More...

unsigned	getVSPLTImmediate (SDNode *N, unsigned EltSize, SelectionDAG &DAG)
	getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the specified isSplatShuffleMask VECTOR_SHUFFLE mask. More...

SDValue	get_VSPLTI_elt (SDNode *N, unsigned ByteSize, SelectionDAG &DAG)
	get_VSPLTI_elt - If this is a build_vector of constants which can be formed by using a vspltis[bhw] instruction of the specified element size, return the constant being splatted. More...

int	isQVALIGNIShuffleMask (SDNode *N)
	If this is a qvaligni shuffle mask, return the shift amount, otherwise return -1. More...

FastISel *	createFastISel (FunctionLoweringInfo &FuncInfo, const TargetLibraryInfo *LibInfo)

int	getAltVSXFMAOpcode (uint16_t Opcode)

Detailed Description

Define some predicates that are used for node matching.

Enumeration Type Documentation

◆ anonymous enum

anonymous enum

Enumerator
DIR_NONE
DIR_32
DIR_440
DIR_601
DIR_602
DIR_603
DIR_7400
DIR_750
DIR_970
DIR_A2
DIR_E500
DIR_E500mc
DIR_E5500
DIR_PWR3
DIR_PWR4
DIR_PWR5
DIR_PWR5X
DIR_PWR6
DIR_PWR6X
DIR_PWR7
DIR_PWR8
DIR_PWR9
DIR_64

Definition at line 38 of file PPCSubtarget.h.

◆ BranchHintBit

enum llvm::PPC::BranchHintBit

Enumerator
BR_NO_HINT
BR_NONTAKEN_HINT
BR_TAKEN_HINT
BR_HINT_MASK

Definition at line 63 of file PPCPredicates.h.

◆ Fixups

enum llvm::PPC::Fixups

Enumerator
fixup_ppc_br24
fixup_ppc_brcond14	14-bit PC relative relocation for conditional branches.
fixup_ppc_br24abs	24-bit absolute relocation for direct branches like 'ba' and 'bla'.
fixup_ppc_brcond14abs	14-bit absolute relocation for conditional branches.
fixup_ppc_half16	A 16-bit fixup corresponding to lo16(_foo) or ha16(_foo) for instrs like 'li' or 'addis'.
fixup_ppc_half16ds	A 14-bit fixup corresponding to lo16(_foo) with implied 2 zero bits for instrs like 'std'.
fixup_ppc_nofixup	Not a true fixup, but ties a symbol to a call to __tls_get_addr for the TLS general and local dynamic models, or inserts the thread-pointer register number.
LastTargetFixupKind
NumTargetFixupKinds

Definition at line 19 of file PPCFixupKinds.h.

◆ Predicate

enum llvm::PPC::Predicate

Predicate - These are "(BI << 5) | BO" for various predicates.

Enumerator
PRED_LT
PRED_LE
PRED_EQ
PRED_GE
PRED_GT
PRED_NE
PRED_UN
PRED_NU
PRED_LT_MINUS
PRED_LE_MINUS
PRED_EQ_MINUS
PRED_GE_MINUS
PRED_GT_MINUS
PRED_NE_MINUS
PRED_UN_MINUS
PRED_NU_MINUS
PRED_LT_PLUS
PRED_LE_PLUS
PRED_EQ_PLUS
PRED_GE_PLUS
PRED_GT_PLUS
PRED_NE_PLUS
PRED_UN_PLUS
PRED_NU_PLUS
PRED_SPE
PRED_BIT_SET
PRED_BIT_UNSET

Definition at line 27 of file PPCPredicates.h.

Function Documentation

◆ createFastISel()

FastISel * llvm::PPC::createFastISel	(	FunctionLoweringInfo &	FuncInfo,
		const TargetLibraryInfo *	LibInfo
	)

Definition at line 2469 of file PPCFastISel.cpp.

References llvm::MachineFunction::getSubtarget(), llvm::PPCSubtarget::isPPC64(), llvm::PPCSubtarget::isSVR4ABI(), and llvm::FunctionLoweringInfo::MF.

Referenced by llvm::PPCTargetLowering::convertSelectOfConstantsToMath(), llvm::PPCTargetLowering::createFastISel(), and llvm::PPCTargetLowering::functionArgumentNeedsConsecutiveRegisters().

◆ get_VSPLTI_elt()

SDValue llvm::PPC::get_VSPLTI_elt	(	SDNode *	N,
		unsigned	ByteSize,
		SelectionDAG &	DAG
	)

get_VSPLTI_elt - If this is a build_vector of constants which can be formed by using a vspltis[bhw] instruction of the specified element size, return the constant being splatted.

The ByteSize field indicates the number of bytes of each element [124] -> [bhw].

Definition at line 2053 of file PPCISelLowering.cpp.

References assert(), llvm::MVT::f32, llvm::FloatToBits(), llvm::SDValue::getNode(), llvm::SDNode::getNumOperands(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getTargetConstant(), llvm::MVT::i32, llvm::isAllOnesConstant(), llvm::isNullConstant(), isSplat(), llvm::SDValue::isUndef(), and llvm::SignExtend32().

◆ getAltVSXFMAOpcode()

int llvm::PPC::getAltVSXFMAOpcode ( uint16_t Opcode )

Referenced by llvm::PPCInstrInfo::findCommutedOpIndices().

◆ getNonRecordFormOpcode()

int llvm::PPC::getNonRecordFormOpcode ( uint16_t )

Referenced by llvm::PPCInstrInfo::optimizeCompareInstr().

◆ getPredicate()

Predicate llvm::PPC::getPredicate	(	unsigned	Condition,
		unsigned	Hint
	)

inline

Return predicate consisting of specified condition and hint bits.

Definition at line 88 of file PPCPredicates.h.

References BR_HINT_MASK.

Referenced by buildNew(), llvm::FunctionComparator::cmpOperations(), computeValueLLTs(), emitSignedInt64(), llvm::ConstantExpr::getAsInstruction(), llvm::SystemZTTIImpl::getCmpSelInstrCost(), llvm::CmpInst::getFlippedStrictnessPredicate(), llvm::CmpInst::getInversePredicate(), llvm::DOTGraphTraits< BoUpSLP * >::getNodeAttributes(), llvm::CmpInst::getNonStrictPredicate(), llvm::ConstantExpr::getOpcode(), llvm::CmpInst::getSignedPredicate(), llvm::ICmpInst::getSignedPredicate(), llvm::CmpInst::getSwappedPredicate(), llvm::ICmpInst::getUnsignedPredicate(), llvm::ConstantExpr::getWithOperands(), haveSameSpecialState(), inversePermutation(), llvm::FCmpInst::isCommutative(), llvm::ICmpInst::isEquality(), llvm::FCmpInst::isEquality(), llvm::CmpInst::isFalseWhenEqual(), llvm::CmpInst::isFPPredicate(), llvm::CmpInst::isIntPredicate(), llvm::CmpInst::isSigned(), llvm::CmpInst::isTrueWhenEqual(), llvm::CmpInst::isUnsigned(), mapBinOpcode(), llvm::PPCInstrInfo::optimizeCompareInstr(), and llvm::SimplifyInstruction().

◆ getPredicateCondition()

unsigned llvm::PPC::getPredicateCondition ( Predicate Opcode )

inline

Return the condition without hint bits.

Definition at line 78 of file PPCPredicates.h.

References BR_HINT_MASK.

Referenced by llvm::PPCInstrInfo::optimizeCompareInstr().

◆ getPredicateHint()

unsigned llvm::PPC::getPredicateHint ( Predicate Opcode )

inline

Return the hint bits of the predicate.

Definition at line 83 of file PPCPredicates.h.

References BR_HINT_MASK.

Referenced by llvm::PPCInstrInfo::optimizeCompareInstr().

◆ getSwappedPredicate()

Predicate llvm::PPC::getSwappedPredicate ( Predicate Opcode )

Assume the condition register is set by MI(a,b), return the predicate if we modify the instructions such that condition register is set by MI(b,a).

Referenced by llvm::CmpInst::getSwappedPredicate(), llvm::PPCInstrInfo::optimizeCompareInstr(), llvm::ICmpInst::swapOperands(), and llvm::FCmpInst::swapOperands().

◆ getVSPLTImmediate()

unsigned llvm::PPC::getVSPLTImmediate	(	SDNode *	N,
		unsigned	EltSize,
		SelectionDAG &	DAG
	)

getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the specified isSplatShuffleMask VECTOR_SHUFFLE mask.

Definition at line 2039 of file PPCISelLowering.cpp.

References assert(), llvm::SelectionDAG::getDataLayout(), llvm::ShuffleVectorSDNode::getMaskElt(), llvm::DataLayout::isLittleEndian(), isSplatShuffleMask(), and N.

Referenced by GeneratePerfectShuffle().

◆ InvertPredicate()

Predicate llvm::PPC::InvertPredicate ( Predicate Opcode )

Invert the specified predicate. != -> ==, < -> >=.

Referenced by getComparePred(), INITIALIZE_PASS(), and llvm::PPCInstrInfo::reverseBranchCondition().

◆ isQVALIGNIShuffleMask()

int llvm::PPC::isQVALIGNIShuffleMask ( SDNode * N )

If this is a qvaligni shuffle mask, return the shift amount, otherwise return -1.

isQVALIGNIShuffleMask - If this is a qvaligni shuffle mask, return the shift amount, otherwise return -1.

Definition at line 2155 of file PPCISelLowering.cpp.

References llvm::ShuffleVectorSDNode::getMaskElt(), llvm::SDNode::getValueType(), isConstantOrUndef(), N, llvm::MVT::v4f32, llvm::MVT::v4f64, and llvm::MVT::v4i1.

Referenced by GeneratePerfectShuffle().

◆ isSplatShuffleMask()

bool llvm::PPC::isSplatShuffleMask	(	ShuffleVectorSDNode *	N,
		unsigned	EltSize
	)

isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand specifies a splat of a single element that is suitable for input to VSPLTB/VSPLTH/VSPLTW.

Definition at line 1742 of file PPCISelLowering.cpp.

References assert(), llvm::ShuffleVectorSDNode::getMaskElt(), llvm::SDNode::getValueType(), and llvm::MVT::v16i8.

Referenced by GeneratePerfectShuffle(), and getVSPLTImmediate().

◆ isVMRGEOShuffleMask()

bool llvm::PPC::isVMRGEOShuffleMask	(	ShuffleVectorSDNode *	N,
		bool	CheckEven,
		unsigned	ShuffleKind,
		SelectionDAG &	DAG
	)

isVMRGEOShuffleMask - Return true if this is a shuffle mask suitable for a VMRGEW or VMRGOW instruction

Determine if the specified shuffle mask is suitable for the vmrgew or vmrgow instructions.

Parameters

[in]	N	The shuffle vector SD Node to analyze
[in]	CheckEven	Check for an even merge (true) or an odd merge (false)
[in]	ShuffleKind	Identify the type of merge: 0 = big-endian merge with two different inputs; 1 = either-endian merge with two identical inputs; 2 = little-endian merge with two different inputs (inputs are swapped for little-endian merges).
[in]	DAG	The current SelectionDAG

Returns: true iff this shuffle mask

Definition at line 1669 of file PPCISelLowering.cpp.

References llvm::SelectionDAG::getDataLayout(), llvm::DataLayout::isLittleEndian(), and isVMerge().

Referenced by GeneratePerfectShuffle().

◆ isVMRGHShuffleMask()

bool llvm::PPC::isVMRGHShuffleMask	(	ShuffleVectorSDNode *	N,
		unsigned	UnitSize,
		unsigned	ShuffleKind,
		SelectionDAG &	DAG
	)

isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for a VRGH* instruction with the specified unit size (1,2 or 4 bytes).

isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for a VMRGH* instruction with the specified unit size (1,2 or 4 bytes).

The ShuffleKind distinguishes between big-endian merges with two different inputs (0), either-endian merges with two identical inputs (1), and little-endian merges with two different inputs (2). For the latter, the input operands are swapped (see PPCInstrAltivec.td).

Definition at line 1579 of file PPCISelLowering.cpp.

References llvm::SelectionDAG::getDataLayout(), llvm::DataLayout::isLittleEndian(), and isVMerge().

Referenced by GeneratePerfectShuffle().

◆ isVMRGLShuffleMask()

bool llvm::PPC::isVMRGLShuffleMask	(	ShuffleVectorSDNode *	N,
		unsigned	UnitSize,
		unsigned	ShuffleKind,
		SelectionDAG &	DAG
	)

isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for a VRGL* instruction with the specified unit size (1,2 or 4 bytes).

isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for a VMRGL* instruction with the specified unit size (1,2 or 4 bytes).

The ShuffleKind distinguishes between big-endian merges with two different inputs (0), either-endian merges with two identical inputs (1), and little-endian merges with two different inputs (2). For the latter, the input operands are swapped (see PPCInstrAltivec.td).

Definition at line 1554 of file PPCISelLowering.cpp.

References llvm::SelectionDAG::getDataLayout(), llvm::DataLayout::isLittleEndian(), and isVMerge().

Referenced by GeneratePerfectShuffle().

◆ isVPKUDUMShuffleMask()

bool llvm::PPC::isVPKUDUMShuffleMask	(	ShuffleVectorSDNode *	N,
		unsigned	ShuffleKind,
		SelectionDAG &	DAG
	)

isVPKUDUMShuffleMask - Return true if this is the shuffle mask for a VPKUDUM instruction.

isVPKUDUMShuffleMask - Return true if this is the shuffle mask for a VPKUDUM instruction, AND the VPKUDUM instruction exists for the current subtarget.

The ShuffleKind distinguishes between big-endian operations with two different inputs (0), either-endian operations with two identical inputs (1), and little-endian operations with two different inputs (2). For the latter, the input operands are swapped (see PPCInstrAltivec.td).

Definition at line 1486 of file PPCISelLowering.cpp.

References llvm::SelectionDAG::getDataLayout(), llvm::ShuffleVectorSDNode::getMaskElt(), llvm::SelectionDAG::getSubtarget(), llvm::PPCSubtarget::hasP8Vector(), isConstantOrUndef(), and llvm::DataLayout::isLittleEndian().

Referenced by GeneratePerfectShuffle().

◆ isVPKUHUMShuffleMask()

bool llvm::PPC::isVPKUHUMShuffleMask	(	ShuffleVectorSDNode *	N,
		unsigned	ShuffleKind,
		SelectionDAG &	DAG
	)

isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a VPKUHUM instruction.

The ShuffleKind distinguishes between big-endian operations with two different inputs (0), either-endian operations with two identical inputs (1), and little-endian operations with two different inputs (2). For the latter, the input operands are swapped (see PPCInstrAltivec.td).

Definition at line 1418 of file PPCISelLowering.cpp.

References llvm::SelectionDAG::getDataLayout(), llvm::ShuffleVectorSDNode::getMaskElt(), isConstantOrUndef(), and llvm::DataLayout::isLittleEndian().

Referenced by GeneratePerfectShuffle().

◆ isVPKUWUMShuffleMask()

bool llvm::PPC::isVPKUWUMShuffleMask	(	ShuffleVectorSDNode *	N,
		unsigned	ShuffleKind,
		SelectionDAG &	DAG
	)

isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a VPKUWUM instruction.

The ShuffleKind distinguishes between big-endian operations with two different inputs (0), either-endian operations with two identical inputs (1), and little-endian operations with two different inputs (2). For the latter, the input operands are swapped (see PPCInstrAltivec.td).

Definition at line 1449 of file PPCISelLowering.cpp.

References llvm::SelectionDAG::getDataLayout(), llvm::ShuffleVectorSDNode::getMaskElt(), isConstantOrUndef(), and llvm::DataLayout::isLittleEndian().

Referenced by GeneratePerfectShuffle().

◆ isVSLDOIShuffleMask()

int llvm::PPC::isVSLDOIShuffleMask	(	SDNode *	N,
		unsigned	ShuffleKind,
		SelectionDAG &	DAG
	)

isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift amount, otherwise return -1.

The ShuffleKind distinguishes between big-endian operations with two different inputs (0), either-endian operations with two identical inputs (1), and little-endian operations with two different inputs (2). For the latter, the input operands are swapped (see PPCInstrAltivec.td).

Definition at line 1698 of file PPCISelLowering.cpp.

References llvm::SelectionDAG::getDataLayout(), llvm::ShuffleVectorSDNode::getMaskElt(), llvm::SDNode::getValueType(), isConstantOrUndef(), llvm::DataLayout::isLittleEndian(), N, and llvm::MVT::v16i8.

Referenced by GeneratePerfectShuffle().

◆ isXXBRDShuffleMask()

bool llvm::PPC::isXXBRDShuffleMask ( ShuffleVectorSDNode * N )

isXXBRDShuffleMask - Return true if this is a shuffle mask suitable for a XXBRD instruction.

Definition at line 1968 of file PPCISelLowering.cpp.

References isXXBRShuffleMaskHelper().

Referenced by GeneratePerfectShuffle().

◆ isXXBRHShuffleMask()

bool llvm::PPC::isXXBRHShuffleMask ( ShuffleVectorSDNode * N )

isXXBRHShuffleMask - Return true if this is a shuffle mask suitable for a XXBRH instruction.

Definition at line 1960 of file PPCISelLowering.cpp.

References isXXBRShuffleMaskHelper().

Referenced by GeneratePerfectShuffle().

◆ isXXBRQShuffleMask()

bool llvm::PPC::isXXBRQShuffleMask ( ShuffleVectorSDNode * N )

isXXBRQShuffleMask - Return true if this is a shuffle mask suitable for a XXBRQ instruction.

Definition at line 1972 of file PPCISelLowering.cpp.

References isXXBRShuffleMaskHelper().

Referenced by GeneratePerfectShuffle().

◆ isXXBRWShuffleMask()

bool llvm::PPC::isXXBRWShuffleMask ( ShuffleVectorSDNode * N )

isXXBRWShuffleMask - Return true if this is a shuffle mask suitable for a XXBRW instruction.

Definition at line 1964 of file PPCISelLowering.cpp.

References isXXBRShuffleMaskHelper().

Referenced by GeneratePerfectShuffle().

◆ isXXINSERTWMask()

bool llvm::PPC::isXXINSERTWMask	(	ShuffleVectorSDNode *	N,
		unsigned &	ShiftElts,
		unsigned &	InsertAtByte,
		bool &	Swap,
		bool	IsLE
	)

isXXINSERTWMask - Return true if this VECTOR_SHUFFLE can be handled by the XXINSERTW instruction introduced in ISA 3.0.

This is essentially any shuffle of v4f32/v4i32 vectors that just inserts one element from one vector into the other. This function will also set a couple of output parameters for how much the source vector needs to be shifted and what byte number needs to be specified for the instruction to put the element in the desired location of the target vector.

Definition at line 1810 of file PPCISelLowering.cpp.

References llvm::ShuffleVectorSDNode::getMaskElt(), llvm::SDNode::getOperand(), isNByteElemShuffleMask(), and llvm::SDValue::isUndef().

Referenced by GeneratePerfectShuffle().

◆ isXXPERMDIShuffleMask()

bool llvm::PPC::isXXPERMDIShuffleMask	(	ShuffleVectorSDNode *	N,
		unsigned &	DM,
		bool &	Swap,
		bool	IsLE
	)

isXXPERMDIShuffleMask - Return true if this is a shuffle mask suitable for a XXPERMDI instruction.

Can node N be lowered to an XXPERMDI instruction? If so, set Swap if the inputs to the instruction should be swapped and set DM to the value for the immediate.

Specifically, set Swap to true only if N can be lowered to XXPERMDI AND element 0 of the result comes from the first input (LE) or second input (BE). Set DM to the calculated result (0-3) only if N can be lowered.

Returns: true iff the given mask of shuffle node N is a XXPERMDI shuffle mask.

Definition at line 1984 of file PPCISelLowering.cpp.

References assert(), llvm::ShuffleVectorSDNode::getMaskElt(), llvm::SDNode::getOperand(), llvm::SDNode::getValueType(), isNByteElemShuffleMask(), llvm::SDValue::isUndef(), and llvm::MVT::v16i8.

Referenced by GeneratePerfectShuffle().

◆ isXXSLDWIShuffleMask()

bool llvm::PPC::isXXSLDWIShuffleMask	(	ShuffleVectorSDNode *	N,
		unsigned &	ShiftElts,
		bool &	Swap,
		bool	IsLE
	)

isXXSLDWIShuffleMask - Return true if this is a shuffle mask suitable for a XXSLDWI instruction.

Definition at line 1885 of file PPCISelLowering.cpp.

References assert(), llvm::ShuffleVectorSDNode::getMaskElt(), llvm::SDNode::getOperand(), llvm::SDNode::getValueType(), isNByteElemShuffleMask(), llvm::SDValue::isUndef(), and llvm::MVT::v16i8.

Referenced by GeneratePerfectShuffle().

Enumerations

Functions

Detailed Description

Enumeration Type Documentation

◆ anonymous enum

◆ BranchHintBit

◆ Fixups

◆ Predicate

Function Documentation

◆ createFastISel()

◆ get_VSPLTI_elt()

◆ getAltVSXFMAOpcode()

◆ getNonRecordFormOpcode()

◆ getPredicate()

◆ getPredicateCondition()

◆ getPredicateHint()

◆ getSwappedPredicate()

◆ getVSPLTImmediate()

◆ InvertPredicate()

◆ isQVALIGNIShuffleMask()

◆ isSplatShuffleMask()

◆ isVMRGEOShuffleMask()

◆ isVMRGHShuffleMask()

◆ isVMRGLShuffleMask()

◆ isVPKUDUMShuffleMask()

◆ isVPKUHUMShuffleMask()

◆ isVPKUWUMShuffleMask()

◆ isVSLDOIShuffleMask()

◆ isXXBRDShuffleMask()

◆ isXXBRHShuffleMask()

◆ isXXBRQShuffleMask()

◆ isXXBRWShuffleMask()

◆ isXXINSERTWMask()

◆ isXXPERMDIShuffleMask()

◆ isXXSLDWIShuffleMask()