LLVM  8.0.1
llvm::PPCInstrInfo Member List

This is the complete list of members for llvm::PPCInstrInfo, including all inherited members.

analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const overridellvm::PPCInstrInfo
analyzeCompare(const MachineInstr &MI, unsigned &SrcReg, unsigned &SrcReg2, int &Mask, int &Value) const overridellvm::PPCInstrInfo
canInsertSelect(const MachineBasicBlock &, ArrayRef< MachineOperand > Cond, unsigned, unsigned, int &, int &, int &) const overridellvm::PPCInstrInfo
commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const overridellvm::PPCInstrInfoprotected
convertToImmediateForm(MachineInstr &MI, MachineInstr **KilledDef=nullptr) constllvm::PPCInstrInfo
copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const overridellvm::PPCInstrInfo
CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI, const ScheduleDAG *DAG) const overridellvm::PPCInstrInfo
CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, const ScheduleDAG *DAG) const overridellvm::PPCInstrInfo
decomposeMachineOperandsTargetFlags(unsigned TF) const overridellvm::PPCInstrInfo
DefinesPredicate(MachineInstr &MI, std::vector< MachineOperand > &Pred) const overridellvm::PPCInstrInfo
expandPostRAPseudo(MachineInstr &MI) const overridellvm::PPCInstrInfo
expandVSXMemPseudo(MachineInstr &MI) constllvm::PPCInstrInfo
findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const overridellvm::PPCInstrInfo
FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, unsigned Reg, MachineRegisterInfo *MRI) const overridellvm::PPCInstrInfo
getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr &MI, unsigned *PredCost=nullptr) const overridellvm::PPCInstrInfo
getInstSizeInBytes(const MachineInstr &MI) const overridellvm::PPCInstrInfo
getLoadOpcodeForSpill(unsigned Reg, const TargetRegisterClass *RC=nullptr) constllvm::PPCInstrInfo
getMachineCombinerPatterns(MachineInstr &Root, SmallVectorImpl< MachineCombinerPattern > &P) const overridellvm::PPCInstrInfo
getNoop(MCInst &NopInst) const overridellvm::PPCInstrInfo
getOperandLatency(const InstrItineraryData *ItinData, const MachineInstr &DefMI, unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const overridellvm::PPCInstrInfo
getOperandLatency(const InstrItineraryData *ItinData, SDNode *DefNode, unsigned DefIdx, SDNode *UseNode, unsigned UseIdx) const overridellvm::PPCInstrInfoinline
getRecordFormOpcode(unsigned Opcode)llvm::PPCInstrInfostatic
getRegisterInfo() constllvm::PPCInstrInfoinline
getRegNumForOperand(const MCInstrDesc &Desc, unsigned Reg, unsigned OpNo)llvm::PPCInstrInfoinlinestatic
getSerializableBitmaskMachineOperandTargetFlags() const overridellvm::PPCInstrInfo
getSerializableDirectMachineOperandTargetFlags() const overridellvm::PPCInstrInfo
getStoreOpcodeForSpill(unsigned Reg, const TargetRegisterClass *RC=nullptr) constllvm::PPCInstrInfo
hasLowDefLatency(const TargetSchedModel &SchedModel, const MachineInstr &DefMI, unsigned DefIdx) const overridellvm::PPCInstrInfoinline
insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const overridellvm::PPCInstrInfo
insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const overridellvm::PPCInstrInfo
insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, unsigned DstReg, ArrayRef< MachineOperand > Cond, unsigned TrueReg, unsigned FalseReg) const overridellvm::PPCInstrInfo
instrHasImmForm(const MachineInstr &MI, ImmInstrInfo &III, bool PostRA) constllvm::PPCInstrInfo
isAssociativeAndCommutative(const MachineInstr &Inst) const overridellvm::PPCInstrInfo
isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg, unsigned &SubIdx) const overridellvm::PPCInstrInfo
isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const overridellvm::PPCInstrInfo
isPredicable(const MachineInstr &MI) const overridellvm::PPCInstrInfo
isPredicated(const MachineInstr &MI) const overridellvm::PPCInstrInfo
isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, BranchProbability Probability) const overridellvm::PPCInstrInfoinline
isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, BranchProbability Probability) const overridellvm::PPCInstrInfoinline
isProfitableToIfCvt(MachineBasicBlock &TMBB, unsigned NumT, unsigned ExtraT, MachineBasicBlock &FMBB, unsigned NumF, unsigned ExtraF, BranchProbability Probability) const overridellvm::PPCInstrInfo
isProfitableToUnpredicate(MachineBasicBlock &TMBB, MachineBasicBlock &FMBB) const overridellvm::PPCInstrInfoinline
isReallyTriviallyReMaterializable(const MachineInstr &MI, AliasAnalysis *AA) const overridellvm::PPCInstrInfo
isSameClassPhysRegCopy(unsigned Opcode)llvm::PPCInstrInfoinlinestatic
isSignExtended(const MachineInstr &MI, const unsigned depth=0) constllvm::PPCInstrInfoinline
isSignOrZeroExtended(const MachineInstr &MI, bool SignExt, const unsigned PhiDepth) constllvm::PPCInstrInfo
isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const overridellvm::PPCInstrInfo
isTOCSaveMI(const MachineInstr &MI) constllvm::PPCInstrInfo
isUnpredicatedTerminator(const MachineInstr &MI) const overridellvm::PPCInstrInfo
isVFRegister(unsigned Reg)llvm::PPCInstrInfoinlinestatic
isVRRegister(unsigned Reg)llvm::PPCInstrInfoinlinestatic
isXFormMemOp(unsigned Opcode) constllvm::PPCInstrInfoinline
isZeroExtended(const MachineInstr &MI, const unsigned depth=0) constllvm::PPCInstrInfoinline
loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const overridellvm::PPCInstrInfo
optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg, unsigned SrcReg2, int Mask, int Value, const MachineRegisterInfo *MRI) const overridellvm::PPCInstrInfo
PPCInstrInfo(PPCSubtarget &STI)llvm::PPCInstrInfoexplicit
PredicateInstruction(MachineInstr &MI, ArrayRef< MachineOperand > Pred) const overridellvm::PPCInstrInfo
removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const overridellvm::PPCInstrInfo
replaceInstrOperandWithImm(MachineInstr &MI, unsigned OpNo, int64_t Imm) constllvm::PPCInstrInfo
replaceInstrWithLI(MachineInstr &MI, const LoadImmediateInfo &LII) constllvm::PPCInstrInfo
reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const overridellvm::PPCInstrInfo
storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const overridellvm::PPCInstrInfo
SubsumesPredicate(ArrayRef< MachineOperand > Pred1, ArrayRef< MachineOperand > Pred2) const overridellvm::PPCInstrInfo
updatedRC(const TargetRegisterClass *RC) constllvm::PPCInstrInfo
useMachineCombiner() const overridellvm::PPCInstrInfoinline