LLVM
8.0.1
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This is the complete list of members for llvm::PPCInstrInfo, including all inherited members.
analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override | llvm::PPCInstrInfo | |
analyzeCompare(const MachineInstr &MI, unsigned &SrcReg, unsigned &SrcReg2, int &Mask, int &Value) const override | llvm::PPCInstrInfo | |
canInsertSelect(const MachineBasicBlock &, ArrayRef< MachineOperand > Cond, unsigned, unsigned, int &, int &, int &) const override | llvm::PPCInstrInfo | |
commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const override | llvm::PPCInstrInfo | protected |
convertToImmediateForm(MachineInstr &MI, MachineInstr **KilledDef=nullptr) const | llvm::PPCInstrInfo | |
copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override | llvm::PPCInstrInfo | |
CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI, const ScheduleDAG *DAG) const override | llvm::PPCInstrInfo | |
CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, const ScheduleDAG *DAG) const override | llvm::PPCInstrInfo | |
decomposeMachineOperandsTargetFlags(unsigned TF) const override | llvm::PPCInstrInfo | |
DefinesPredicate(MachineInstr &MI, std::vector< MachineOperand > &Pred) const override | llvm::PPCInstrInfo | |
expandPostRAPseudo(MachineInstr &MI) const override | llvm::PPCInstrInfo | |
expandVSXMemPseudo(MachineInstr &MI) const | llvm::PPCInstrInfo | |
findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const override | llvm::PPCInstrInfo | |
FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, unsigned Reg, MachineRegisterInfo *MRI) const override | llvm::PPCInstrInfo | |
getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr &MI, unsigned *PredCost=nullptr) const override | llvm::PPCInstrInfo | |
getInstSizeInBytes(const MachineInstr &MI) const override | llvm::PPCInstrInfo | |
getLoadOpcodeForSpill(unsigned Reg, const TargetRegisterClass *RC=nullptr) const | llvm::PPCInstrInfo | |
getMachineCombinerPatterns(MachineInstr &Root, SmallVectorImpl< MachineCombinerPattern > &P) const override | llvm::PPCInstrInfo | |
getNoop(MCInst &NopInst) const override | llvm::PPCInstrInfo | |
getOperandLatency(const InstrItineraryData *ItinData, const MachineInstr &DefMI, unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const override | llvm::PPCInstrInfo | |
getOperandLatency(const InstrItineraryData *ItinData, SDNode *DefNode, unsigned DefIdx, SDNode *UseNode, unsigned UseIdx) const override | llvm::PPCInstrInfo | inline |
getRecordFormOpcode(unsigned Opcode) | llvm::PPCInstrInfo | static |
getRegisterInfo() const | llvm::PPCInstrInfo | inline |
getRegNumForOperand(const MCInstrDesc &Desc, unsigned Reg, unsigned OpNo) | llvm::PPCInstrInfo | inlinestatic |
getSerializableBitmaskMachineOperandTargetFlags() const override | llvm::PPCInstrInfo | |
getSerializableDirectMachineOperandTargetFlags() const override | llvm::PPCInstrInfo | |
getStoreOpcodeForSpill(unsigned Reg, const TargetRegisterClass *RC=nullptr) const | llvm::PPCInstrInfo | |
hasLowDefLatency(const TargetSchedModel &SchedModel, const MachineInstr &DefMI, unsigned DefIdx) const override | llvm::PPCInstrInfo | inline |
insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override | llvm::PPCInstrInfo | |
insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override | llvm::PPCInstrInfo | |
insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, unsigned DstReg, ArrayRef< MachineOperand > Cond, unsigned TrueReg, unsigned FalseReg) const override | llvm::PPCInstrInfo | |
instrHasImmForm(const MachineInstr &MI, ImmInstrInfo &III, bool PostRA) const | llvm::PPCInstrInfo | |
isAssociativeAndCommutative(const MachineInstr &Inst) const override | llvm::PPCInstrInfo | |
isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg, unsigned &SubIdx) const override | llvm::PPCInstrInfo | |
isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override | llvm::PPCInstrInfo | |
isPredicable(const MachineInstr &MI) const override | llvm::PPCInstrInfo | |
isPredicated(const MachineInstr &MI) const override | llvm::PPCInstrInfo | |
isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, BranchProbability Probability) const override | llvm::PPCInstrInfo | inline |
isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, BranchProbability Probability) const override | llvm::PPCInstrInfo | inline |
isProfitableToIfCvt(MachineBasicBlock &TMBB, unsigned NumT, unsigned ExtraT, MachineBasicBlock &FMBB, unsigned NumF, unsigned ExtraF, BranchProbability Probability) const override | llvm::PPCInstrInfo | |
isProfitableToUnpredicate(MachineBasicBlock &TMBB, MachineBasicBlock &FMBB) const override | llvm::PPCInstrInfo | inline |
isReallyTriviallyReMaterializable(const MachineInstr &MI, AliasAnalysis *AA) const override | llvm::PPCInstrInfo | |
isSameClassPhysRegCopy(unsigned Opcode) | llvm::PPCInstrInfo | inlinestatic |
isSignExtended(const MachineInstr &MI, const unsigned depth=0) const | llvm::PPCInstrInfo | inline |
isSignOrZeroExtended(const MachineInstr &MI, bool SignExt, const unsigned PhiDepth) const | llvm::PPCInstrInfo | |
isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override | llvm::PPCInstrInfo | |
isTOCSaveMI(const MachineInstr &MI) const | llvm::PPCInstrInfo | |
isUnpredicatedTerminator(const MachineInstr &MI) const override | llvm::PPCInstrInfo | |
isVFRegister(unsigned Reg) | llvm::PPCInstrInfo | inlinestatic |
isVRRegister(unsigned Reg) | llvm::PPCInstrInfo | inlinestatic |
isXFormMemOp(unsigned Opcode) const | llvm::PPCInstrInfo | inline |
isZeroExtended(const MachineInstr &MI, const unsigned depth=0) const | llvm::PPCInstrInfo | inline |
loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override | llvm::PPCInstrInfo | |
optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg, unsigned SrcReg2, int Mask, int Value, const MachineRegisterInfo *MRI) const override | llvm::PPCInstrInfo | |
PPCInstrInfo(PPCSubtarget &STI) | llvm::PPCInstrInfo | explicit |
PredicateInstruction(MachineInstr &MI, ArrayRef< MachineOperand > Pred) const override | llvm::PPCInstrInfo | |
removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override | llvm::PPCInstrInfo | |
replaceInstrOperandWithImm(MachineInstr &MI, unsigned OpNo, int64_t Imm) const | llvm::PPCInstrInfo | |
replaceInstrWithLI(MachineInstr &MI, const LoadImmediateInfo &LII) const | llvm::PPCInstrInfo | |
reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override | llvm::PPCInstrInfo | |
storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override | llvm::PPCInstrInfo | |
SubsumesPredicate(ArrayRef< MachineOperand > Pred1, ArrayRef< MachineOperand > Pred2) const override | llvm::PPCInstrInfo | |
updatedRC(const TargetRegisterClass *RC) const | llvm::PPCInstrInfo | |
useMachineCombiner() const override | llvm::PPCInstrInfo | inline |