Go to the source code of this file.
|
enum | SpillOpcodeKey {
SOK_Int4Spill,
SOK_Int8Spill,
SOK_Float8Spill,
SOK_Float4Spill,
SOK_CRSpill,
SOK_CRBitSpill,
SOK_VRVectorSpill,
SOK_VSXVectorSpill,
SOK_VectorFloat8Spill,
SOK_VectorFloat4Spill,
SOK_VRSaveSpill,
SOK_QuadFloat8Spill,
SOK_QuadFloat4Spill,
SOK_QuadBitSpill,
SOK_SpillToVSR,
SOK_SPESpill,
SOK_SPE4Spill,
SOK_LastOpcodeSpill
} |
|
|
| STATISTIC (NumStoreSPILLVSRRCAsVec, "Number of spillvsrrc spilled to stack as vec") |
|
| STATISTIC (NumStoreSPILLVSRRCAsGpr, "Number of spillvsrrc spilled to stack as gpr") |
|
| STATISTIC (NumGPRtoVSRSpill, "Number of gpr spills to spillvsrrc") |
|
| STATISTIC (CmpIselsConverted, "Number of ISELs that depend on comparison of constants converted") |
|
| STATISTIC (MissedConvertibleImmediateInstrs, "Number of compare-immediate instructions fed by constants") |
|
| STATISTIC (NumRcRotatesConvertedToRcAnd, "Number of record-form rotates converted to record-form andi") |
|
static unsigned | getCRBitValue (unsigned CRBit) |
|
static bool | MBBDefinesCTR (MachineBasicBlock &MBB) |
|
static bool | isAnImmediateOperand (const MachineOperand &MO) |
|
static unsigned | selectReg (int64_t Imm1, int64_t Imm2, unsigned CompareOpc, unsigned TrueReg, unsigned FalseReg, unsigned CRSubReg) |
|
static bool | isVFReg (unsigned Reg) |
|
static void | swapMIOperands (MachineInstr &MI, unsigned Op1, unsigned Op2) |
|
static bool | isSignExtendingOp (const MachineInstr &MI) |
|
static bool | isZeroExtendingOp (const MachineInstr &MI) |
|
◆ DEBUG_TYPE
#define DEBUG_TYPE "ppc-instr-info" |
◆ GET_INSTRINFO_CTOR_DTOR
#define GET_INSTRINFO_CTOR_DTOR |
◆ GET_INSTRMAP_INFO
#define GET_INSTRMAP_INFO |
◆ SpillOpcodeKey
Enumerator |
---|
SOK_Int4Spill | |
SOK_Int8Spill | |
SOK_Float8Spill | |
SOK_Float4Spill | |
SOK_CRSpill | |
SOK_CRBitSpill | |
SOK_VRVectorSpill | |
SOK_VSXVectorSpill | |
SOK_VectorFloat8Spill | |
SOK_VectorFloat4Spill | |
SOK_VRSaveSpill | |
SOK_QuadFloat8Spill | |
SOK_QuadFloat4Spill | |
SOK_QuadBitSpill | |
SOK_SpillToVSR | |
SOK_SPESpill | |
SOK_SPE4Spill | |
SOK_LastOpcodeSpill | |
Definition at line 77 of file PPCInstrInfo.cpp.
◆ getCRBitValue()
◆ isAnImmediateOperand()
◆ isSignExtendingOp()
◆ isVFReg()
◆ isZeroExtendingOp()
◆ MBBDefinesCTR()
◆ selectReg()
◆ STATISTIC() [1/6]
STATISTIC |
( |
NumStoreSPILLVSRRCAsVec |
, |
|
|
"Number of spillvsrrc spilled to stack as vec" |
|
|
) |
| |
◆ STATISTIC() [2/6]
STATISTIC |
( |
NumStoreSPILLVSRRCAsGpr |
, |
|
|
"Number of spillvsrrc spilled to stack as gpr" |
|
|
) |
| |
◆ STATISTIC() [3/6]
STATISTIC |
( |
NumGPRtoVSRSpill |
, |
|
|
"Number of gpr spills to spillvsrrc" |
|
|
) |
| |
◆ STATISTIC() [4/6]
STATISTIC |
( |
CmpIselsConverted |
, |
|
|
"Number of ISELs that depend on comparison of constants converted" |
|
|
) |
| |
◆ STATISTIC() [5/6]
STATISTIC |
( |
MissedConvertibleImmediateInstrs |
, |
|
|
"Number of compare-immediate instructions fed by constants" |
|
|
) |
| |
◆ STATISTIC() [6/6]
STATISTIC |
( |
NumRcRotatesConvertedToRcAnd |
, |
|
|
"Number of record-form rotates converted to record-form andi" |
|
|
) |
| |
◆ swapMIOperands()
Definition at line 3075 of file PPCInstrInfo.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstr::addOperand(), assert(), llvm::SmallVectorTemplateCommon< T >::back(), llvm::MachineOperand::ChangeToRegister(), contains(), llvm::dbgs(), DefMI, llvm::MachineInstr::dump(), E, llvm::GlobalValue::getAlignment(), llvm::MachineOperand::getGlobal(), llvm::MachineOperand::getImm(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), llvm::MachineRegisterInfo::getRegClass(), llvm::MachineFunction::getRegInfo(), llvm::PPCInstrInfo::getRegisterInfo(), llvm::TargetRegisterClass::hasSuperClassEq(), llvm::LoadImmediateInfo::Imm, llvm::ImmInstrInfo::ImmMustBeMultipleOf, llvm::ImmInstrInfo::ImmOpcode, llvm::ImmInstrInfo::ImmOpNo, llvm::ImmInstrInfo::ImmWidth, llvm::LoadImmediateInfo::Is64Bit, isAnImmediateOperand(), llvm::ImmInstrInfo::IsCommutative, llvm::MachineOperand::isGlobal(), llvm::MachineOperand::isImm(), llvm::MachineOperand::isKill(), llvm::APInt::isSignedIntN(), llvm::MachineRegisterInfo::isSSA(), llvm::ImmInstrInfo::IsSummingOperands, llvm::TargetRegisterInfo::isVirtualRegister(), LLVM_DEBUG, llvm_unreachable, llvm::max(), MI, llvm::PPCII::MO_TOC_LO, MRI, llvm::ImmInstrInfo::OpNoForForwarding, llvm::SmallVectorTemplateBase< T >::pop_back(), llvm::SmallVectorTemplateBase< T >::push_back(), llvm::MachineInstr::readsRegister(), Reg, llvm::MachineInstr::RemoveOperand(), llvm::MachineBasicBlock::rend(), llvm::PPCInstrInfo::replaceInstrOperandWithImm(), llvm::PPCInstrInfo::replaceInstrWithLI(), llvm::LoadImmediateInfo::SetCR, llvm::MachineInstr::setDesc(), llvm::MachineRegisterInfo::setRegClass(), llvm::MachineOperand::setTargetFlags(), llvm::ImmInstrInfo::SignedImm, llvm::ImmInstrInfo::TruncateImmTo, llvm::ImmInstrInfo::ZeroIsSpecialNew, and llvm::ImmInstrInfo::ZeroIsSpecialOrig.
◆ DisableCmpOpt
◆ DisableCTRLoopAnal
◆ MAX_DEPTH
◆ UseOldLatencyCalc
cl::opt<bool> UseOldLatencyCalc("ppc-old-latency-calc", cl::Hidden, cl::desc("Use the old (incorrect) instruction latency calculation")) |
|
static |
◆ VSXSelfCopyCrash
cl::opt<bool> VSXSelfCopyCrash("crash-on-ppc-vsx-self-copy", cl::desc("Causes the backend to crash instead of generating a nop VSX copy"), cl::Hidden) |
|
static |