#include "Target/Hexagon/HexagonInstrInfo.h"
Detailed Description
Definition at line 39 of file HexagonInstrInfo.h.
Constructor & Destructor Documentation
◆ HexagonInstrInfo()
|
explicit |
Definition at line 118 of file HexagonInstrInfo.cpp.
Member Function Documentation
◆ addLatencyToSchedule()
| bool HexagonInstrInfo::addLatencyToSchedule | ( | const MachineInstr & | MI1, |
| const MachineInstr & | MI2 | ||
| ) | const |
Definition at line 2887 of file HexagonInstrInfo.cpp.
References isHVXVec(), and isVecUsableNextPacket().
◆ analyzeBranch()
|
override |
Analyze the branching code at the end of MBB, returning true if it cannot be understood (e.g.
This function can analyze one/two way branching only and should (mostly) be called by target independent side.
it's a switch dispatch or isn't implemented for a target). Upon success, this returns false and returns with the following information in various cases:
- If this block ends with no branches (it just falls through to its succ) just return false, leaving TBB/FBB null.
- If this block ends with only an unconditional branch, it sets TBB to be the destination block.
- If this block ends with a conditional branch and it falls through to a successor block, it sets TBB to be the branch destination block and a list of operands that evaluate the condition. These operands can be passed to other TargetInstrInfo methods to create new branches.
- If this block ends with a conditional branch followed by an unconditional branch, it returns the 'true' destination in TBB, the 'false' destination in FBB, and a list of operands that evaluate the condition. These operands can be passed to other TargetInstrInfo methods to create new branches.
Note that removeBranch and insertBranch must be implemented to support cases where this method returns success.
If AllowModify is true, then this routine is allowed to modify the basic block (e.g. delete instructions after the unconditional branch).
First entry is always the opcode of the branching instruction, except when the Cond vector is supposed to be empty, e.g., when AnalyzeBranch fails, a BB with only unconditional jump. Subsequent entries depend upon the opcode, e.g. Jump_c p will have Cond[0] = Jump_c Cond[1] = p HW-loop ENDLOOP: Cond[0] = ENDLOOP Cond[1] = MBB New value jump: Cond[0] = Hexagon::CMPEQri_f_Jumpnv_t_V4 – specific opcode Cond[1] = R Cond[2] = Imm
Definition at line 386 of file HexagonInstrInfo.cpp.
References llvm::SmallVectorImpl< T >::clear(), llvm::MachineOperand::CreateImm(), llvm::dbgs(), llvm::ilist_node_impl< OptionsT >::getIterator(), llvm::MachineOperand::getMBB(), llvm::MachineInstr::getNumExplicitOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), I, llvm::MachineBasicBlock::instr_begin(), llvm::MachineBasicBlock::instr_end(), llvm::MachineInstr::isBundle(), isEndLoopN(), llvm::MachineBasicBlock::isLayoutSuccessor(), llvm::MachineOperand::isMBB(), isNewValueJump(), LLVM_DEBUG, PredOpcodeHasJMP_c(), llvm::printMBBReference(), and llvm::SmallVectorTemplateBase< T >::push_back().
Referenced by llvm::createHexagonHardwareLoops(), INITIALIZE_PASS(), insertBranch(), isImmValidForOpcode(), parseCond(), and profitImm().
◆ analyzeCompare()
|
override |
For a comparison instruction, return the source registers in SrcReg and SrcReg2 if having two register operands, and the value it compares against in CmpValue.
For a comparison instruction, return the source registers in SrcReg and SrcReg2 if having two register operands, and the value it compares against in CmpValue.
Return true if the comparison instruction can be analyzed.
Definition at line 1720 of file HexagonInstrInfo.cpp.
References llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), and llvm::MachineOperand::isImm().
Referenced by llvm::createHexagonHardwareLoops(), and profitImm().
◆ analyzeLoop()
|
override |
Analyze the loop code, return true if it cannot be understood.
Analyze the loop code to find the loop induction variable and compare used to compute the number of iterations.
Upon success, this function returns false and returns information about the induction variable and compare instruction used at the end.
Currently, we analyze loop that are controlled using hardware loops. In this case, the induction variable instruction is null. For all other cases, this function returns true, which means we're unable to analyze it.
Definition at line 683 of file HexagonInstrInfo.cpp.
References llvm::MachineBasicBlock::end(), llvm::MachineLoop::getBottomBlock(), llvm::MachineBasicBlock::getFirstTerminator(), I, and isEndLoopN().
◆ areMemAccessesTriviallyDisjoint()
|
override |
Definition at line 1825 of file HexagonInstrInfo.cpp.
References getBaseAndOffsetPosition(), llvm::MachineOperand::getImm(), getMemAccessSize(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::getSubReg(), llvm::MachineInstr::hasOrderedMemoryRef(), llvm::MachineInstr::hasUnmodeledSideEffects(), llvm::MachineOperand::isImm(), isMemOp(), isPostIncrement(), and llvm::MachineInstr::mayLoad().
◆ canExecuteInBundle()
| bool HexagonInstrInfo::canExecuteInBundle | ( | const MachineInstr & | First, |
| const MachineInstr & | Second | ||
| ) | const |
Can these instructions execute at the same time in a bundle.
Definition at line 2908 of file HexagonInstrInfo.cpp.
References DisableNVSchedule, llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::isDef(), llvm::MachineOperand::isReg(), llvm::MachineOperand::isUse(), mayBeNewStore(), and llvm::MachineInstr::mayStore().
Referenced by llvm::HexagonSubtarget::adjustSchedDependency(), getZeroLatency(), and hasDependence().
◆ changeAddrMode_abs_io() [1/2]
| short HexagonInstrInfo::changeAddrMode_abs_io | ( | short | Opc | ) | const |
Definition at line 4405 of file HexagonInstrInfo.cpp.
Referenced by changeAddrMode_abs_io().
◆ changeAddrMode_abs_io() [2/2]
|
inline |
Definition at line 502 of file HexagonInstrInfo.h.
References changeAddrMode_abs_io(), and llvm::MachineInstr::getOpcode().
◆ changeAddrMode_io_abs() [1/2]
| short HexagonInstrInfo::changeAddrMode_io_abs | ( | short | Opc | ) | const |
Definition at line 4409 of file HexagonInstrInfo.cpp.
Referenced by changeAddrMode_io_abs().
◆ changeAddrMode_io_abs() [2/2]
|
inline |
Definition at line 505 of file HexagonInstrInfo.h.
References changeAddrMode_io_abs(), and llvm::MachineInstr::getOpcode().
◆ changeAddrMode_io_pi()
| short HexagonInstrInfo::changeAddrMode_io_pi | ( | short | Opc | ) | const |
Definition at line 4413 of file HexagonInstrInfo.cpp.
◆ changeAddrMode_io_rr() [1/2]
| short HexagonInstrInfo::changeAddrMode_io_rr | ( | short | Opc | ) | const |
Definition at line 4417 of file HexagonInstrInfo.cpp.
Referenced by changeAddrMode_io_rr().
◆ changeAddrMode_io_rr() [2/2]
|
inline |
Definition at line 508 of file HexagonInstrInfo.h.
References changeAddrMode_io_rr(), and llvm::MachineInstr::getOpcode().
◆ changeAddrMode_pi_io()
| short HexagonInstrInfo::changeAddrMode_pi_io | ( | short | Opc | ) | const |
Definition at line 4421 of file HexagonInstrInfo.cpp.
◆ changeAddrMode_rr_io() [1/2]
| short HexagonInstrInfo::changeAddrMode_rr_io | ( | short | Opc | ) | const |
Definition at line 4425 of file HexagonInstrInfo.cpp.
Referenced by changeAddrMode_rr_io().
◆ changeAddrMode_rr_io() [2/2]
|
inline |
Definition at line 511 of file HexagonInstrInfo.h.
References changeAddrMode_rr_io(), and llvm::MachineInstr::getOpcode().
◆ changeAddrMode_rr_ur() [1/2]
| short HexagonInstrInfo::changeAddrMode_rr_ur | ( | short | Opc | ) | const |
Definition at line 4429 of file HexagonInstrInfo.cpp.
Referenced by changeAddrMode_rr_ur().
◆ changeAddrMode_rr_ur() [2/2]
|
inline |
Definition at line 514 of file HexagonInstrInfo.h.
References changeAddrMode_rr_ur(), and llvm::MachineInstr::getOpcode().
◆ changeAddrMode_ur_rr() [1/2]
| short HexagonInstrInfo::changeAddrMode_ur_rr | ( | short | Opc | ) | const |
Definition at line 4433 of file HexagonInstrInfo.cpp.
Referenced by changeAddrMode_ur_rr().
◆ changeAddrMode_ur_rr() [2/2]
|
inline |
Definition at line 517 of file HexagonInstrInfo.h.
References changeAddrMode_ur_rr(), and llvm::MachineInstr::getOpcode().
◆ copyPhysReg()
|
override |
Emit instructions to copy a pair of physical registers.
This function should support copies within any legal register class as well as any cross-class copies created during instruction selection.
The source and destination registers may overlap, which may require a careful implementation when multiple copy instructions are required for large registers. See for example the ARM target.
Definition at line 778 of file HexagonInstrInfo.cpp.
References llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), contains(), llvm::dbgs(), llvm::getKillRegState(), llvm::HexagonSubtarget::getRegisterInfo(), llvm_unreachable, llvm::printMBBReference(), and llvm::printReg().
Referenced by expandPostRAPseudo(), INITIALIZE_PASS(), and isLEASimpleIncOrDec().
◆ CreateTargetPostRAHazardRecognizer()
|
override |
Allocate and return a hazard recognizer to use for this target when scheduling the machine instructions after register allocation.
Definition at line 1709 of file HexagonInstrInfo.cpp.
References llvm::TargetInstrInfo::CreateTargetPostRAHazardRecognizer(), and UseDFAHazardRec.
◆ CreateTargetScheduleState()
|
override |
Create machine specific model for scheduling.
Definition at line 1815 of file HexagonInstrInfo.cpp.
References llvm::TargetSubtargetInfo::getInstrItineraryData().
◆ createVR()
| unsigned HexagonInstrInfo::createVR | ( | MachineFunction * | MF, |
| MVT | VT | ||
| ) | const |
HexagonInstrInfo specifics.
Definition at line 1940 of file HexagonInstrInfo.cpp.
References llvm::MachineRegisterInfo::createVirtualRegister(), llvm::MVT::f32, llvm::MVT::f64, llvm::MachineFunction::getRegInfo(), llvm::MVT::i1, llvm::MVT::i32, llvm::MVT::i64, llvm_unreachable, and MRI.
Referenced by reduceLoopCount().
◆ decomposeMachineOperandsTargetFlags()
|
override |
Decompose the machine operand's target flags into two values - the direct target flag value and any of bit flags that are applied.
Definition at line 1906 of file HexagonInstrInfo.cpp.
References llvm::HexagonII::MO_Bitmasks.
Referenced by llvm::MachineOperand::printTargetFlags().
◆ DefinesPredicate()
|
override |
If the specified instruction defines any predicate or condition code register(s) used for predication, returns true as well as the definition predicate(s) by reference.
Definition at line 1576 of file HexagonInstrInfo.cpp.
References llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::HexagonSubtarget::getRegisterInfo(), llvm::MachineOperand::isDef(), llvm::MachineOperand::isReg(), llvm::MachineOperand::isRegMask(), and llvm::MachineInstr::modifiesRegister().
◆ doesNotReturn()
| bool HexagonInstrInfo::doesNotReturn | ( | const MachineInstr & | CallMI | ) | const |
Definition at line 2933 of file HexagonInstrInfo.cpp.
References llvm::MachineInstr::getOpcode().
Referenced by isSchedulingBoundary().
◆ expandPostRAPseudo()
|
override |
This function is called for all pseudo instructions that remain after register allocation.
expandPostRAPseudo - This function is called for all pseudo instructions that remain after register allocation.
Many pseudo instructions are created to help register allocation. This is the place to convert them into real instructions. The target can edit MI in place, or it can insert new instructions and erase MI. The function should return true if anything was changed.
Definition at line 1012 of file HexagonInstrInfo.cpp.
References llvm::ARM_AM::add, llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::LivePhysRegs::available(), llvm::BuildMI(), llvm::MachineRegisterInfo::clearKillFlags(), llvm::MachineInstrBuilder::cloneMemRefs(), copyPhysReg(), llvm::MachineBasicBlock::erase(), llvm::MachineInstr::getDebugLoc(), llvm::HexagonRegisterInfo::getFrameRegister(), llvm::MachineOperand::getImm(), llvm::ilist_node_impl< OptionsT >::getIterator(), llvm::getKillRegState(), getLiveRegsAt(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), llvm::HexagonSubtarget::getRegisterInfo(), llvm::getRegState(), llvm::MachineOperand::getSubReg(), llvm::RegState::Implicit, llvm::MachineOperand::isKill(), llvm::MachineOperand::isUndef(), llvm::RegState::Kill, MI, MRI, Reg, llvm::MachineInstr::setDesc(), llvm::MachineOperand::setIsKill(), and llvm::RegState::Undef.
Referenced by INITIALIZE_PASS().
◆ expandVGatherPseudo()
| MachineBasicBlock::instr_iterator HexagonInstrInfo::expandVGatherPseudo | ( | MachineInstr & | MI | ) | const |
Definition at line 1393 of file HexagonInstrInfo.cpp.
References llvm::ARM_AM::add, llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::MachineBasicBlock::erase(), llvm::MachineInstr::getDebugLoc(), llvm::MachineInstrBundleIterator< Ty, IsReverse >::getInstrIterator(), llvm::ilist_node_impl< OptionsT >::getIterator(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), and llvm::MachineInstr::getParent().
◆ findLoopInstr()
| MachineInstr * HexagonInstrInfo::findLoopInstr | ( | MachineBasicBlock * | BB, |
| unsigned | EndLoopOp, | ||
| MachineBasicBlock * | TargetBB, | ||
| SmallPtrSet< MachineBasicBlock *, 8 > & | Visited | ||
| ) | const |
Find the hardware loop instruction used to set-up the specified loop.
On Hexagon, we have two instructions used to set-up the hardware loop (LOOP0, LOOP1) with corresponding endloop (ENDLOOP0, ENDLOOP1) instructions to indicate the end of a loop.
Definition at line 147 of file HexagonInstrInfo.cpp.
References E, I, llvm::SmallPtrSetImpl< PtrType >::insert(), and llvm::MachineBasicBlock::predecessors().
Referenced by insertBranch(), and reduceLoopCount().
◆ genAllInsnTimingClasses()
| void HexagonInstrInfo::genAllInsnTimingClasses | ( | MachineFunction & | MF | ) | const |
Definition at line 4343 of file HexagonInstrInfo.cpp.
References B, llvm::MachineBasicBlock::begin(), llvm::MachineFunction::begin(), llvm::BuildMI(), llvm::dbgs(), llvm::MachineInstr::eraseFromParent(), llvm::MachineInstr::getDesc(), getName(), llvm::MachineInstr::getOpcode(), llvm::MCInstrDesc::getSchedClass(), I, and LLVM_DEBUG.
◆ getAddrMode()
| unsigned HexagonInstrInfo::getAddrMode | ( | const MachineInstr & | MI | ) | const |
Definition at line 3104 of file HexagonInstrInfo.cpp.
References llvm::HexagonII::AddrModeMask, llvm::HexagonII::AddrModePos, F(), llvm::MachineInstr::getDesc(), and llvm::MCInstrDesc::TSFlags.
Referenced by llvm::HexagonSubtarget::BankConflictMutation::apply(), getBaseAndOffset(), getNonExtOpcode(), hasNonExtEquivalent(), isAbsoluteSet(), isBaseImmOffset(), and isPostIncrement().
◆ getBaseAndOffset()
| MachineOperand * HexagonInstrInfo::getBaseAndOffset | ( | const MachineInstr & | MI, |
| int64_t & | Offset, | ||
| unsigned & | AccessSize | ||
| ) | const |
Definition at line 3113 of file HexagonInstrInfo.cpp.
References llvm::HexagonII::BaseImmOffset, llvm::HexagonII::BaseLongOffset, getAddrMode(), getBaseAndOffsetPosition(), llvm::MachineOperand::getImm(), getMemAccessSize(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getSubReg(), llvm::MachineOperand::isImm(), isMemOp(), and isPostIncrement().
Referenced by llvm::HexagonSubtarget::BankConflictMutation::apply(), and getMemOperandWithOffset().
◆ getBaseAndOffsetPosition()
|
override |
For instructions with a base and offset, return the position of the base register and offset operands.
Return the position of the base and offset operands for this instruction.
Definition at line 3146 of file HexagonInstrInfo.cpp.
References llvm::MachineInstr::getOperand(), isAddrModeWithOffset(), llvm::MachineOperand::isImm(), isMemOp(), isPostIncrement(), isPredicated(), llvm::MachineOperand::isReg(), llvm::MachineInstr::mayLoad(), and llvm::MachineInstr::mayStore().
Referenced by areMemAccessesTriviallyDisjoint(), getBaseAndOffset(), and getIncrementValue().
◆ getBranchingInstrs()
| SmallVector< MachineInstr *, 2 > HexagonInstrInfo::getBranchingInstrs | ( | MachineBasicBlock & | MBB | ) | const |
Definition at line 3183 of file HexagonInstrInfo.cpp.
References I, llvm::MachineBasicBlock::instr_begin(), llvm::MachineBasicBlock::instr_end(), llvm::MachineInstr::isBundle(), and llvm::SmallVectorTemplateBase< T >::push_back().
◆ getBundleNoShuf()
| bool HexagonInstrInfo::getBundleNoShuf | ( | const MachineInstr & | MIB | ) | const |
Definition at line 4398 of file HexagonInstrInfo.cpp.
References assert(), llvm::MachineInstr::getOperand(), and llvm::MachineInstr::isBundle().
◆ getCExtOpNum()
| unsigned HexagonInstrInfo::getCExtOpNum | ( | const MachineInstr & | MI | ) | const |
Definition at line 3241 of file HexagonInstrInfo.cpp.
References llvm::HexagonII::ExtendableOpMask, llvm::HexagonII::ExtendableOpPos, F(), llvm::MachineInstr::getDesc(), and llvm::MCInstrDesc::TSFlags.
Referenced by immediateExtend(), and isConstExtended().
◆ getCompoundCandidateGroup()
| HexagonII::CompoundGroup HexagonInstrInfo::getCompoundCandidateGroup | ( | const MachineInstr & | MI | ) | const |
Definition at line 3248 of file HexagonInstrInfo.cpp.
References contains(), llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::HexagonII::HCG_A, llvm::HexagonII::HCG_B, llvm::HexagonII::HCG_C, llvm::HexagonII::HCG_None, llvm::MachineOperand::isImm(), and isIntRegForSubInst().
Referenced by getCompoundOpcode().
◆ getCompoundOpcode()
| unsigned HexagonInstrInfo::getCompoundOpcode | ( | const MachineInstr & | GA, |
| const MachineInstr & | GB | ||
| ) | const |
Definition at line 3336 of file HexagonInstrInfo.cpp.
References assert(), getCompoundCandidateGroup(), llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::HexagonII::HCG_A, llvm::HexagonII::HCG_B, llvm::MachineOperand::isImm(), and llvm::MachineInstr::readsRegister().
◆ getCondOpcode()
| int HexagonInstrInfo::getCondOpcode | ( | int | Opc, |
| bool | sense | ||
| ) | const |
Definition at line 3362 of file HexagonInstrInfo.cpp.
References llvm_unreachable.
Referenced by PredicateInstruction().
◆ getDotCurOp()
| int HexagonInstrInfo::getDotCurOp | ( | const MachineInstr & | MI | ) | const |
Definition at line 3374 of file HexagonInstrInfo.cpp.
References llvm::MachineInstr::getOpcode(), and llvm_unreachable.
◆ getDotNewOp()
| int HexagonInstrInfo::getDotNewOp | ( | const MachineInstr & | MI | ) | const |
Definition at line 3487 of file HexagonInstrInfo.cpp.
References llvm::MachineInstr::getOpcode(), llvm::report_fatal_error(), and llvm::to_string().
Referenced by llvm::HexagonHazardRecognizer::EmitInstruction(), and llvm::HexagonHazardRecognizer::getHazardType().
◆ getDotNewPredJumpOp()
| int HexagonInstrInfo::getDotNewPredJumpOp | ( | const MachineInstr & | MI, |
| const MachineBranchProbabilityInfo * | MBPI | ||
| ) | const |
Definition at line 3528 of file HexagonInstrInfo.cpp.
References assert(), B, llvm::MachineBranchProbabilityInfo::getEdgeProbability(), llvm::MachineOperand::getMBB(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), I, llvm::MachineInstr::isConditionalBranch(), llvm::MachineOperand::isMBB(), llvm_unreachable, llvm::MachineBasicBlock::succ_size(), and llvm::MachineBasicBlock::successors().
Referenced by getDotNewPredOp().
◆ getDotNewPredOp()
| int HexagonInstrInfo::getDotNewPredOp | ( | const MachineInstr & | MI, |
| const MachineBranchProbabilityInfo * | MBPI | ||
| ) | const |
Definition at line 3614 of file HexagonInstrInfo.cpp.
References getDotNewPredJumpOp(), and llvm::MachineInstr::getOpcode().
◆ getDotOldOp()
| int HexagonInstrInfo::getDotOldOp | ( | const MachineInstr & | MI | ) | const |
Definition at line 3629 of file HexagonInstrInfo.cpp.
References assert(), llvm::MachineInstr::getOpcode(), isNewValueStore(), isPredicated(), and isPredicatedNew().
◆ getDuplexCandidateGroup()
| HexagonII::SubInstructionGroup HexagonInstrInfo::getDuplexCandidateGroup | ( | const MachineInstr & | MI | ) | const |
Definition at line 3680 of file HexagonInstrInfo.cpp.
References contains(), llvm::MachineOperand::getImm(), llvm::MachineOperand::getOffset(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::HexagonRegisterInfo::getStackRegister(), llvm::HexagonII::HSIG_A, llvm::HexagonII::HSIG_L1, llvm::HexagonII::HSIG_L2, llvm::HexagonII::HSIG_None, llvm::HexagonII::HSIG_S1, llvm::HexagonII::HSIG_S2, isDblRegForSubInst(), llvm::MachineOperand::isGlobal(), llvm::MachineOperand::isImm(), and isIntRegForSubInst().
Referenced by isDuplexPair().
◆ getEquivalentHWInstr()
| short HexagonInstrInfo::getEquivalentHWInstr | ( | const MachineInstr & | MI | ) | const |
Definition at line 4026 of file HexagonInstrInfo.cpp.
References llvm::MachineInstr::getOpcode().
◆ getIncrementValue()
|
override |
If the instruction is an increment of a constant value, return the amount.
Definition at line 1883 of file HexagonInstrInfo.cpp.
References getBaseAndOffsetPosition(), llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::isImm(), and isPostIncrement().
◆ getInlineAsmLength()
|
override |
Measure the specified inline asm to determine an approximation of its length.
Comments (which run till the next SeparatorString or newline) do not count as an instruction. Any other non-whitespace text is considered an instruction, with multiple instructions separated by SeparatorString or newlines. Variable-length instructions are not handled here; this function may be overloaded in the target code to do that. Hexagon counts the number of ##'s and adjust for that many constant exenders.
Definition at line 1683 of file HexagonInstrInfo.cpp.
References llvm::StringRef::count(), llvm::StringRef::data(), llvm::MCAsmInfo::getCommentString(), llvm::MCAsmInfo::getMaxInstLength(), llvm::MCAsmInfo::getSeparatorString(), and llvm::StringRef::size().
Referenced by getSize().
◆ getInstrLatency()
|
override |
Compute the instruction latency of a given instruction.
If the instruction has higher cost when predicated, it's returned via PredCost.
Definition at line 1809 of file HexagonInstrInfo.cpp.
References getInstrTimingClassLatency().
Referenced by getInstrTimingClassLatency().
◆ getInstrTimingClassLatency()
| unsigned HexagonInstrInfo::getInstrTimingClassLatency | ( | const InstrItineraryData * | ItinData, |
| const MachineInstr & | MI | ||
| ) | const |
Definition at line 4030 of file HexagonInstrInfo.cpp.
References llvm::MachineInstr::getDesc(), getInstrLatency(), llvm::MCInstrDesc::getSchedClass(), llvm::InstrItineraryData::getStageLatency(), and llvm::MachineInstr::isTransient().
Referenced by getInstrLatency().
◆ getInvertedPredicatedOpcode()
Definition at line 4105 of file HexagonInstrInfo.cpp.
References isPredicatedTrue(), and llvm_unreachable.
Referenced by getInvertedPredSense(), invertAndChangeJumpTarget(), reverseBranchCondition(), and reversePredSense().
◆ getInvertedPredSense()
| bool HexagonInstrInfo::getInvertedPredSense | ( | SmallVectorImpl< MachineOperand > & | Cond | ) | const |
Definition at line 4096 of file HexagonInstrInfo.cpp.
References llvm::SmallVectorBase::empty(), and getInvertedPredicatedOpcode().
◆ getMaxValue()
| int HexagonInstrInfo::getMaxValue | ( | const MachineInstr & | MI | ) | const |
Definition at line 4116 of file HexagonInstrInfo.cpp.
References bits, llvm::HexagonII::ExtentBitsMask, llvm::HexagonII::ExtentBitsPos, llvm::HexagonII::ExtentSignedMask, llvm::HexagonII::ExtentSignedPos, F(), llvm::MachineInstr::getDesc(), and llvm::MCInstrDesc::TSFlags.
Referenced by isConstExtended().
◆ getMemAccessSize()
| unsigned HexagonInstrInfo::getMemAccessSize | ( | const MachineInstr & | MI | ) | const |
Definition at line 4158 of file HexagonInstrInfo.cpp.
References F(), llvm::MachineInstr::getDesc(), llvm::HexagonII::getMemAccessSizeInBytes(), llvm::HexagonII::HVXVectorAccess, llvm_unreachable, llvm::HexagonII::MemAccesSizeMask, llvm::HexagonII::MemAccessSizePos, Size, and llvm::MCInstrDesc::TSFlags.
Referenced by areMemAccessesTriviallyDisjoint(), and getBaseAndOffset().
◆ getMemOperandWithOffset()
|
override |
Get the base register and byte offset of a load/store instr.
Definition at line 2896 of file HexagonInstrInfo.cpp.
References assert(), getBaseAndOffset(), and llvm::MachineOperand::isReg().
Referenced by llvm::createStoreClusterDAGMutation(), and INITIALIZE_PASS().
◆ getMinValue()
| int HexagonInstrInfo::getMinValue | ( | const MachineInstr & | MI | ) | const |
Definition at line 4178 of file HexagonInstrInfo.cpp.
References bits, llvm::HexagonII::ExtentBitsMask, llvm::HexagonII::ExtentBitsPos, llvm::HexagonII::ExtentSignedMask, llvm::HexagonII::ExtentSignedPos, F(), llvm::MachineInstr::getDesc(), and llvm::MCInstrDesc::TSFlags.
Referenced by isConstExtended().
◆ getNonDotCurOp()
| int HexagonInstrInfo::getNonDotCurOp | ( | const MachineInstr & | MI | ) | const |
Definition at line 3390 of file HexagonInstrInfo.cpp.
References llvm::MachineInstr::getOpcode(), and llvm_unreachable.
◆ getNonExtOpcode()
| short HexagonInstrInfo::getNonExtOpcode | ( | const MachineInstr & | MI | ) | const |
Definition at line 4192 of file HexagonInstrInfo.cpp.
References llvm::HexagonII::Absolute, llvm::HexagonII::BaseImmOffset, llvm::HexagonII::BaseLongOffset, getAddrMode(), llvm::MachineInstr::getDesc(), llvm::MachineInstr::getOpcode(), llvm::MCInstrDesc::mayLoad(), and llvm::MCInstrDesc::mayStore().
◆ getOperandLatency()
|
override |
getOperandLatency - Compute and return the use operand latency of a given pair of def and use.
In most cases, the static scheduling itinerary was enough to determine the operand latency. But it may not be possible for instructions with variable number of defs / uses.
This is a raw interface to the itinerary that may be directly overriden by a target. Use computeOperandLatency to get the best estimate of latency.
Definition at line 4050 of file HexagonInstrInfo.cpp.
References llvm::MachineInstr::findRegisterDefOperandIdx(), llvm::MachineInstr::findRegisterUseOperandIdx(), llvm::MachineInstr::getOperand(), llvm::TargetInstrInfo::getOperandLatency(), llvm::MachineOperand::getReg(), llvm::MachineOperand::isImplicit(), llvm::MachineOperand::isReg(), llvm::MCRegisterInfo::DiffListIterator::isValid(), and llvm::Latency.
Referenced by llvm::HexagonSubtarget::adjustSchedDependency(), and llvm::HexagonSubtarget::usePredicatedCalls().
◆ getPredReg()
| bool HexagonInstrInfo::getPredReg | ( | ArrayRef< MachineOperand > | Cond, |
| unsigned & | PredReg, | ||
| unsigned & | PredRegPos, | ||
| unsigned & | PredRegFlags | ||
| ) | const |
Definition at line 4216 of file HexagonInstrInfo.cpp.
References assert(), llvm::dbgs(), llvm::ArrayRef< T >::empty(), llvm::RegState::Implicit, isNewValueJump(), isUndef(), LLVM_DEBUG, llvm::ArrayRef< T >::size(), and llvm::RegState::Undef.
Referenced by llvm::createHexagonHardwareLoops(), and PredicateInstruction().
◆ getPseudoInstrPair()
| short HexagonInstrInfo::getPseudoInstrPair | ( | const MachineInstr & | MI | ) | const |
Definition at line 4236 of file HexagonInstrInfo.cpp.
References llvm::MachineInstr::getOpcode().
◆ getRegForm()
| short HexagonInstrInfo::getRegForm | ( | const MachineInstr & | MI | ) | const |
Definition at line 4240 of file HexagonInstrInfo.cpp.
References llvm::MachineInstr::getOpcode().
◆ getSerializableBitmaskMachineOperandTargetFlags()
|
override |
Return an array that contains the bitmask target flag values and their names.
MIR Serialization is able to serialize only the target flags that are defined by this method.
Definition at line 1931 of file HexagonInstrInfo.cpp.
References llvm::HexagonII::HMOTF_ConstExtended, and llvm::makeArrayRef().
Referenced by initSlots2Values(), and llvm::MachineOperand::printTargetFlags().
◆ getSerializableDirectMachineOperandTargetFlags()
|
override |
Return an array that contains the direct target flag values and their names.
MIR Serialization is able to serialize only the target flags that are defined by this method.
Definition at line 1912 of file HexagonInstrInfo.cpp.
References llvm::makeArrayRef(), llvm::HexagonII::MO_GDGOT, llvm::HexagonII::MO_GDPLT, llvm::AArch64II::MO_GOT, llvm::HexagonII::MO_GPREL, llvm::ARMII::MO_HI16, llvm::HexagonII::MO_IE, llvm::HexagonII::MO_IEGOT, llvm::ARMII::MO_LO16, llvm::HexagonII::MO_PCREL, and llvm::HexagonII::MO_TPREL.
Referenced by initSlots2Values().
◆ getSize()
| unsigned HexagonInstrInfo::getSize | ( | const MachineInstr & | MI | ) | const |
Definition at line 4248 of file HexagonInstrInfo.cpp.
References assert(), BranchRelaxAsmLarge, llvm::MachineInstr::getDesc(), getInlineAsmLength(), llvm::TargetMachine::getMCAsmInfo(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), llvm::MCInstrDesc::getSize(), llvm::MachineOperand::getSymbolName(), llvm::MachineFunction::getTarget(), HEXAGON_INSTR_SIZE, llvm::ISD::INLINEASM, isConstExtended(), llvm::MachineInstr::isDebugInstr(), llvm::MachineOperand::isDef(), isExtended(), llvm::MachineInstr::isPosition(), llvm::MachineOperand::isReg(), llvm::MachineOperand::isSymbol(), and Size.
Referenced by isHardwareLoop().
◆ getType()
| uint64_t HexagonInstrInfo::getType | ( | const MachineInstr & | MI | ) | const |
Definition at line 4282 of file HexagonInstrInfo.cpp.
References F(), llvm::MachineInstr::getDesc(), llvm::MCInstrDesc::TSFlags, llvm::HexagonII::TypeMask, and llvm::HexagonII::TypePos.
Referenced by llvm::HexagonSubtarget::HVXMemLatencyMutation::apply(), cannotCoexistAsymm(), isCompoundBranchInstr(), isHVXVec(), and isLateSourceInstr().
◆ getUnits()
| unsigned HexagonInstrInfo::getUnits | ( | const MachineInstr & | MI | ) | const |
Definition at line 4287 of file HexagonInstrInfo.cpp.
References llvm::InstrItineraryData::beginStage(), llvm::MachineInstr::getDesc(), llvm::MCInstrDesc::getSchedClass(), and llvm::InstrStage::getUnits().
◆ hasEHLabel()
| bool HexagonInstrInfo::hasEHLabel | ( | const MachineBasicBlock * | B | ) | const |
Definition at line 2938 of file HexagonInstrInfo.cpp.
References I.
◆ hasLoadFromStackSlot()
|
override |
Check if the instruction or the bundle of instructions has load from stack slots.
This function checks if the instruction or bundle of instructions has load from stack slot and returns frameindex and machine memory operand of that instruction if true.
Return the frameindex and machine memory operand if true.
Definition at line 338 of file HexagonInstrInfo.cpp.
References llvm::ilist_node_impl< OptionsT >::getIterator(), llvm::MachineInstr::getParent(), llvm::TargetInstrInfo::hasLoadFromStackSlot(), llvm::MachineBasicBlock::instr_end(), and llvm::MachineInstr::isBundle().
◆ hasNonExtEquivalent()
| bool HexagonInstrInfo::hasNonExtEquivalent | ( | const MachineInstr & | MI | ) | const |
Definition at line 2947 of file HexagonInstrInfo.cpp.
References llvm::HexagonII::Absolute, llvm::HexagonII::BaseImmOffset, llvm::HexagonII::BaseLongOffset, getAddrMode(), llvm::MachineInstr::getDesc(), llvm::MachineInstr::getOpcode(), llvm::MCInstrDesc::mayLoad(), and llvm::MCInstrDesc::mayStore().
◆ hasPseudoInstrPair()
| bool HexagonInstrInfo::hasPseudoInstrPair | ( | const MachineInstr & | MI | ) | const |
Definition at line 2982 of file HexagonInstrInfo.cpp.
References llvm::MachineInstr::getOpcode().
◆ hasStoreToStackSlot()
|
override |
Check if the instruction or the bundle of instructions has store to stack slots.
This function checks if the instruction or bundle of instructions has store to stack slot and returns frameindex and machine memory operand of that instruction if true.
Return the frameindex and machine memory operand if true.
Definition at line 356 of file HexagonInstrInfo.cpp.
References llvm::ilist_node_impl< OptionsT >::getIterator(), llvm::MachineInstr::getParent(), llvm::TargetInstrInfo::hasStoreToStackSlot(), llvm::MachineBasicBlock::instr_end(), and llvm::MachineInstr::isBundle().
Referenced by INITIALIZE_PASS().
◆ hasUncondBranch()
| bool HexagonInstrInfo::hasUncondBranch | ( | const MachineBasicBlock * | B | ) | const |
Definition at line 2987 of file HexagonInstrInfo.cpp.
References E, llvm::MachineBasicBlock::end(), llvm::MachineBasicBlock::getFirstTerminator(), and I.
◆ immediateExtend()
| void HexagonInstrInfo::immediateExtend | ( | MachineInstr & | MI | ) | const |
immediateExtend - Changes the instruction in place to one using an immediate extender.
Definition at line 4309 of file HexagonInstrInfo.cpp.
References llvm::MachineOperand::addTargetFlag(), assert(), getCExtOpNum(), llvm::MachineInstr::getOperand(), llvm::HexagonII::HMOTF_ConstExtended, isConstExtended(), isExtendable(), llvm::MachineOperand::isImm(), and llvm::MachineOperand::isMBB().
◆ insertBranch()
|
override |
Insert branch code into the end of the specified MachineBasicBlock.
The operands to this method are the same as those returned by AnalyzeBranch. This is only invoked in cases where AnalyzeBranch returns success. It returns the number of instructions inserted.
It is also invoked by tail merging to add unconditional branches in cases where AnalyzeBranch doesn't apply because there was no original branch to analyze. At least this much must be implemented, else tail merging needs to be disabled.
Definition at line 579 of file HexagonInstrInfo.cpp.
References llvm::MachineInstrBuilder::addMBB(), llvm::MachineInstrBuilder::addReg(), analyzeBranch(), assert(), llvm::BuildMI(), llvm::dbgs(), llvm::ArrayRef< T >::empty(), llvm::MachineBasicBlock::end(), findLoopInstr(), llvm::MachineBasicBlock::getFirstTerminator(), llvm::ilist_node_impl< OptionsT >::getIterator(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), getReg(), llvm::getUndefRegState(), isEndLoopN(), isNewValueJump(), isPredicated(), isReg(), llvm::MachineOperand::isUndef(), isUndef(), LLVM_DEBUG, llvm_unreachable, llvm::printMBBReference(), removeBranch(), reverseBranchCondition(), llvm::MachineOperand::setMBB(), llvm::ArrayRef< T >::size(), and validateBranchCond().
Referenced by llvm::FastISel::fastEmitBranch(), and isImmValidForOpcode().
◆ insertNoop()
|
override |
Insert a noop into the instruction stream at the specified point.
Definition at line 1496 of file HexagonInstrInfo.cpp.
References llvm::BuildMI().
Referenced by INITIALIZE_PASS().
◆ invertAndChangeJumpTarget()
| bool HexagonInstrInfo::invertAndChangeJumpTarget | ( | MachineInstr & | MI, |
| MachineBasicBlock * | NewTarget | ||
| ) | const |
Definition at line 4322 of file HexagonInstrInfo.cpp.
References assert(), llvm::dbgs(), llvm::MachineInstr::dump(), EnableBranchPrediction, getInvertedPredicatedOpcode(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::isBranch(), llvm::MachineOperand::isMBB(), isPredicatedNew(), LLVM_DEBUG, llvm::printMBBReference(), reversePrediction(), llvm::MachineInstr::setDesc(), and llvm::MachineOperand::setMBB().
◆ isAbsoluteSet()
| bool HexagonInstrInfo::isAbsoluteSet | ( | const MachineInstr & | MI | ) | const |
Definition at line 1957 of file HexagonInstrInfo.cpp.
References llvm::HexagonII::AbsoluteSet, and getAddrMode().
◆ isAccumulator()
| bool HexagonInstrInfo::isAccumulator | ( | const MachineInstr & | MI | ) | const |
Definition at line 1961 of file HexagonInstrInfo.cpp.
References llvm::HexagonII::AccumulatorMask, llvm::HexagonII::AccumulatorPos, F(), llvm::MachineInstr::getDesc(), and llvm::MCInstrDesc::TSFlags.
Referenced by isVecAcc().
◆ isAddrModeWithOffset()
| bool HexagonInstrInfo::isAddrModeWithOffset | ( | const MachineInstr & | MI | ) | const |
Definition at line 4130 of file HexagonInstrInfo.cpp.
References llvm::HexagonII::AddrModeMask, llvm::HexagonII::AddrModePos, llvm::HexagonII::BaseImmOffset, llvm::HexagonII::BaseLongOffset, llvm::HexagonII::BaseRegOffset, F(), llvm::MachineInstr::getDesc(), llvm::MachineInstr::getOpcode(), and llvm::MCInstrDesc::TSFlags.
Referenced by getBaseAndOffsetPosition().
◆ isBaseImmOffset()
| bool HexagonInstrInfo::isBaseImmOffset | ( | const MachineInstr & | MI | ) | const |
Definition at line 1966 of file HexagonInstrInfo.cpp.
References llvm::HexagonII::BaseImmOffset, and getAddrMode().
◆ isComplex()
| bool HexagonInstrInfo::isComplex | ( | const MachineInstr & | MI | ) | const |
Definition at line 1970 of file HexagonInstrInfo.cpp.
References llvm::MachineInstr::getDesc(), llvm::MCInstrDesc::getOpcode(), llvm::MachineInstr::isBranch(), llvm::MachineInstr::isCall(), isMemOp(), llvm::MachineInstr::isReturn(), isTC1(), isTC2Early(), llvm::MCInstrDesc::mayLoad(), and llvm::MCInstrDesc::mayStore().
◆ isCompoundBranchInstr()
| bool HexagonInstrInfo::isCompoundBranchInstr | ( | const MachineInstr & | MI | ) | const |
Definition at line 1979 of file HexagonInstrInfo.cpp.
References getType(), llvm::MachineInstr::isBranch(), and llvm::HexagonII::TypeCJ.
◆ isConstExtended()
| bool HexagonInstrInfo::isConstExtended | ( | const MachineInstr & | MI | ) | const |
Definition at line 1985 of file HexagonInstrInfo.cpp.
References assert(), llvm::HexagonII::ExtendableMask, llvm::HexagonII::ExtendablePos, llvm::HexagonII::ExtendedMask, llvm::HexagonII::ExtendedPos, F(), getCExtOpNum(), llvm::MachineInstr::getDesc(), llvm::MachineOperand::getImm(), getMaxValue(), getMinValue(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getTargetFlags(), llvm::HexagonII::HMOTF_ConstExtended, llvm::MachineOperand::isBlockAddress(), llvm::MachineInstr::isCall(), llvm::MachineOperand::isCPI(), isExtendable(), isExtended(), llvm::MachineOperand::isFPImm(), llvm::MachineOperand::isGlobal(), llvm::MachineOperand::isImm(), llvm::MachineOperand::isJTI(), llvm::MachineOperand::isMBB(), llvm::MachineOperand::isSymbol(), and llvm::MCInstrDesc::TSFlags.
Referenced by getSize(), and immediateExtend().
◆ isDeallocRet()
| bool HexagonInstrInfo::isDeallocRet | ( | const MachineInstr & | MI | ) | const |
Definition at line 2028 of file HexagonInstrInfo.cpp.
References llvm::MachineInstr::getOpcode().
◆ isDependent()
| bool HexagonInstrInfo::isDependent | ( | const MachineInstr & | ProdMI, |
| const MachineInstr & | ConsMI | ||
| ) | const |
Definition at line 2043 of file HexagonInstrInfo.cpp.
References llvm::MachineInstr::getDesc(), llvm::MCInstrDesc::getNumDefs(), llvm::TargetRegisterInfo::isPhysicalRegister(), llvm::MCRegisterInfo::DiffListIterator::isValid(), and parseOperands().
Referenced by producesStall().
◆ isDotCurInst()
| bool HexagonInstrInfo::isDotCurInst | ( | const MachineInstr & | MI | ) | const |
Definition at line 2078 of file HexagonInstrInfo.cpp.
References llvm::MachineInstr::getOpcode().
◆ isDotNewInst()
| bool HexagonInstrInfo::isDotNewInst | ( | const MachineInstr & | MI | ) | const |
Definition at line 2089 of file HexagonInstrInfo.cpp.
References isNewValueInst(), isPredicated(), and isPredicatedNew().
◆ isDuplexPair()
| bool HexagonInstrInfo::isDuplexPair | ( | const MachineInstr & | MIa, |
| const MachineInstr & | MIb | ||
| ) | const |
Symmetrical. See if these two instructions are fit for duplex pair.
Definition at line 2097 of file HexagonInstrInfo.cpp.
References getDuplexCandidateGroup(), and isDuplexPairMatch().
◆ isEarlySourceInstr()
| bool HexagonInstrInfo::isEarlySourceInstr | ( | const MachineInstr & | MI | ) | const |
Definition at line 2104 of file HexagonInstrInfo.cpp.
References llvm::MachineInstr::getDesc(), llvm::MCInstrDesc::getSchedClass(), llvm::is_TC3x(), llvm::is_TC4x(), llvm::MachineInstr::isCompare(), llvm::MachineInstr::mayLoad(), and llvm::MachineInstr::mayStore().
Referenced by isLateInstrFeedsEarlyInstr().
◆ isEndLoopN()
Definition at line 2113 of file HexagonInstrInfo.cpp.
Referenced by analyzeBranch(), analyzeLoop(), insertBranch(), PredicateInstruction(), reduceLoopCount(), and reverseBranchCondition().
◆ isExpr()
Definition at line 2118 of file HexagonInstrInfo.cpp.
References llvm::MachineOperand::MO_BlockAddress, llvm::MachineOperand::MO_ConstantPoolIndex, llvm::MachineOperand::MO_ExternalSymbol, llvm::MachineOperand::MO_GlobalAddress, llvm::MachineOperand::MO_JumpTableIndex, and llvm::MachineOperand::MO_MachineBasicBlock.
◆ isExtendable()
| bool HexagonInstrInfo::isExtendable | ( | const MachineInstr & | MI | ) | const |
Definition at line 2132 of file HexagonInstrInfo.cpp.
References llvm::HexagonII::ExtendableMask, llvm::HexagonII::ExtendablePos, F(), llvm::MachineInstr::getDesc(), llvm::MachineInstr::getOpcode(), and llvm::MCInstrDesc::TSFlags.
Referenced by immediateExtend(), and isConstExtended().
◆ isExtended()
| bool HexagonInstrInfo::isExtended | ( | const MachineInstr & | MI | ) | const |
Definition at line 2154 of file HexagonInstrInfo.cpp.
References llvm::HexagonII::ExtendedMask, llvm::HexagonII::ExtendedPos, F(), llvm::MachineInstr::getDesc(), llvm::HexagonII::HMOTF_ConstExtended, llvm::MachineInstr::operands(), and llvm::MCInstrDesc::TSFlags.
Referenced by getSize(), and isConstExtended().
◆ isFloat()
| bool HexagonInstrInfo::isFloat | ( | const MachineInstr & | MI | ) | const |
Definition at line 2167 of file HexagonInstrInfo.cpp.
References F(), llvm::HexagonII::FPMask, llvm::HexagonII::FPPos, and llvm::MachineInstr::getOpcode().
◆ isHVXMemWithAIndirect()
| bool HexagonInstrInfo::isHVXMemWithAIndirect | ( | const MachineInstr & | I, |
| const MachineInstr & | J | ||
| ) | const |
Definition at line 2174 of file HexagonInstrInfo.cpp.
References isHVXVec(), llvm::MachineInstr::isIndirectBranch(), isIndirectCall(), isIndirectL4Return(), llvm::MachineInstr::mayLoad(), and llvm::MachineInstr::mayStore().
Referenced by cannotCoexistAsymm().
◆ isHVXVec()
| bool HexagonInstrInfo::isHVXVec | ( | const MachineInstr & | MI | ) | const |
Definition at line 2588 of file HexagonInstrInfo.cpp.
References getType(), llvm::HexagonII::TypeCVI_FIRST, and llvm::HexagonII::TypeCVI_LAST.
Referenced by addLatencyToSchedule(), llvm::HexagonHazardRecognizer::EmitInstruction(), isHVXMemWithAIndirect(), isVecAcc(), and producesStall().
◆ isIndirectCall()
| bool HexagonInstrInfo::isIndirectCall | ( | const MachineInstr & | MI | ) | const |
Definition at line 2183 of file HexagonInstrInfo.cpp.
References llvm::MachineInstr::getOpcode().
Referenced by isHVXMemWithAIndirect().
◆ isIndirectL4Return()
| bool HexagonInstrInfo::isIndirectL4Return | ( | const MachineInstr & | MI | ) | const |
Definition at line 2194 of file HexagonInstrInfo.cpp.
References llvm::MachineInstr::getOpcode().
Referenced by isHVXMemWithAIndirect().
◆ isJumpR()
| bool HexagonInstrInfo::isJumpR | ( | const MachineInstr & | MI | ) | const |
Definition at line 2208 of file HexagonInstrInfo.cpp.
References llvm::MachineInstr::getOpcode().
◆ isJumpWithinBranchRange()
| bool HexagonInstrInfo::isJumpWithinBranchRange | ( | const MachineInstr & | MI, |
| unsigned | offset | ||
| ) | const |
Definition at line 2226 of file HexagonInstrInfo.cpp.
References llvm::MachineInstr::getOpcode(), and isNewValueJump().
◆ isLateInstrFeedsEarlyInstr()
| bool HexagonInstrInfo::isLateInstrFeedsEarlyInstr | ( | const MachineInstr & | LRMI, |
| const MachineInstr & | ESMI | ||
| ) | const |
Definition at line 2268 of file HexagonInstrInfo.cpp.
References llvm::dbgs(), llvm::MachineInstr::dump(), isEarlySourceInstr(), isLateResultInstr(), and LLVM_DEBUG.
◆ isLateResultInstr()
| bool HexagonInstrInfo::isLateResultInstr | ( | const MachineInstr & | MI | ) | const |
Definition at line 2286 of file HexagonInstrInfo.cpp.
References llvm::MachineInstr::getDesc(), llvm::MachineInstr::getOpcode(), llvm::MCInstrDesc::getSchedClass(), llvm::ISD::INLINEASM, and llvm::is_TC1().
Referenced by isLateInstrFeedsEarlyInstr().
◆ isLateSourceInstr()
| bool HexagonInstrInfo::isLateSourceInstr | ( | const MachineInstr & | MI | ) | const |
Definition at line 2305 of file HexagonInstrInfo.cpp.
References getType(), and llvm::HexagonII::TypeCVI_VX_LATE.
Referenced by isVecUsableNextPacket().
◆ isLoadFromStackSlot()
|
override |
TargetInstrInfo overrides.
isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot, return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot.
If the specified machine instruction is a direct load from a stack slot, return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot. If not, return 0. This predicate must return 0 if the instruction has any side effects other than loading from the stack slot.
If not, return 0. This predicate must return 0 if the instruction has any side effects other than loading from the stack slot.
Definition at line 240 of file HexagonInstrInfo.cpp.
References llvm::MachineOperand::getImm(), llvm::MachineOperand::getIndex(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::isFI(), and llvm::MachineOperand::isImm().
Referenced by isFullCopyOf().
◆ isLoopN()
| bool HexagonInstrInfo::isLoopN | ( | const MachineInstr & | MI | ) | const |
Definition at line 2311 of file HexagonInstrInfo.cpp.
References llvm::MachineInstr::getOpcode().
◆ isMemOp()
| bool HexagonInstrInfo::isMemOp | ( | const MachineInstr & | MI | ) | const |
Definition at line 2323 of file HexagonInstrInfo.cpp.
References llvm::MachineInstr::getOpcode().
Referenced by areMemAccessesTriviallyDisjoint(), getBaseAndOffset(), getBaseAndOffsetPosition(), and isComplex().
◆ isNewValue() [1/2]
| bool HexagonInstrInfo::isNewValue | ( | const MachineInstr & | MI | ) | const |
Definition at line 2355 of file HexagonInstrInfo.cpp.
References F(), llvm::MachineInstr::getDesc(), llvm::HexagonII::NewValueMask, llvm::HexagonII::NewValuePos, and llvm::MCInstrDesc::TSFlags.
Referenced by isNewValueJump(), and isPredictedTaken().
◆ isNewValue() [2/2]
Definition at line 2360 of file HexagonInstrInfo.cpp.
References F(), llvm::HexagonII::NewValueMask, and llvm::HexagonII::NewValuePos.
◆ isNewValueInst()
| bool HexagonInstrInfo::isNewValueInst | ( | const MachineInstr & | MI | ) | const |
Definition at line 2365 of file HexagonInstrInfo.cpp.
References isNewValueJump(), and isNewValueStore().
Referenced by isDotNewInst().
◆ isNewValueJump() [1/2]
| bool HexagonInstrInfo::isNewValueJump | ( | const MachineInstr & | MI | ) | const |
Definition at line 2369 of file HexagonInstrInfo.cpp.
References llvm::MachineInstr::isBranch(), and isNewValue().
Referenced by analyzeBranch(), getPredReg(), insertBranch(), isJumpWithinBranchRange(), isNewValueInst(), and PredicateInstruction().
◆ isNewValueJump() [2/2]
Definition at line 2373 of file HexagonInstrInfo.cpp.
References isBranch(), isNewValue(), and isPredicated().
◆ isNewValueStore() [1/2]
| bool HexagonInstrInfo::isNewValueStore | ( | const MachineInstr & | MI | ) | const |
Definition at line 2377 of file HexagonInstrInfo.cpp.
References F(), llvm::MachineInstr::getDesc(), llvm::HexagonII::NVStoreMask, llvm::HexagonII::NVStorePos, and llvm::MCInstrDesc::TSFlags.
Referenced by cannotCoexistAsymm(), getDotOldOp(), and isNewValueInst().
◆ isNewValueStore() [2/2]
Definition at line 2382 of file HexagonInstrInfo.cpp.
References F(), llvm::HexagonII::NVStoreMask, and llvm::HexagonII::NVStorePos.
◆ isOperandExtended()
| bool HexagonInstrInfo::isOperandExtended | ( | const MachineInstr & | MI, |
| unsigned | OperandNum | ||
| ) | const |
Definition at line 2388 of file HexagonInstrInfo.cpp.
References llvm::HexagonII::ExtendableOpMask, llvm::HexagonII::ExtendableOpPos, F(), llvm::MachineInstr::getDesc(), and llvm::MCInstrDesc::TSFlags.
◆ isPostIncrement()
|
override |
Return true for post-incremented instructions.
Definition at line 1502 of file HexagonInstrInfo.cpp.
References getAddrMode(), and llvm::HexagonII::PostInc.
Referenced by areMemAccessesTriviallyDisjoint(), getBaseAndOffset(), getBaseAndOffsetPosition(), getIncrementValue(), and getPostIncrementOperand().
◆ isPredicable()
|
override |
Return true if the specified instruction can be predicated.
By default, this returns true for every instruction with a PredicateOperand.
Definition at line 1603 of file HexagonInstrInfo.cpp.
References llvm::MachineInstr::getDesc(), llvm::MachineInstr::getOpcode(), llvm::HexagonSubtarget::hasV62Ops(), llvm::MachineInstr::isCall(), llvm::MCInstrDesc::isPredicable(), isTailCall(), and llvm::HexagonSubtarget::usePredicatedCalls().
Referenced by PredicateInstruction().
◆ isPredicated() [1/2]
|
override |
Returns true if the instruction is already predicated.
Definition at line 1514 of file HexagonInstrInfo.cpp.
References F(), llvm::MachineInstr::getDesc(), llvm::HexagonII::PredicatedMask, llvm::HexagonII::PredicatedPos, and llvm::MCInstrDesc::TSFlags.
Referenced by llvm::HexagonEvaluator::evaluate(), getBaseAndOffsetPosition(), getDotOldOp(), getPredicatedRegister(), getPredicateSense(), insertBranch(), isDotNewInst(), isNewValueJump(), isPredicatedNew(), llvm::rdf::TargetOperandInfo::isPreserving(), and predOpcodeHasNot().
◆ isPredicated() [2/2]
Definition at line 2421 of file HexagonInstrInfo.cpp.
References F(), llvm::HexagonII::PredicatedMask, and llvm::HexagonII::PredicatedPos.
◆ isPredicatedNew() [1/2]
| bool HexagonInstrInfo::isPredicatedNew | ( | const MachineInstr & | MI | ) | const |
Definition at line 2395 of file HexagonInstrInfo.cpp.
References assert(), F(), llvm::MachineInstr::getDesc(), isPredicated(), llvm::HexagonII::PredicatedNewMask, llvm::HexagonII::PredicatedNewPos, and llvm::MCInstrDesc::TSFlags.
Referenced by getDotOldOp(), invertAndChangeJumpTarget(), isDotNewInst(), and isPredictedTaken().
◆ isPredicatedNew() [2/2]
Definition at line 2401 of file HexagonInstrInfo.cpp.
References assert(), F(), isPredicated(), llvm::HexagonII::PredicatedNewMask, and llvm::HexagonII::PredicatedNewPos.
◆ isPredicatedTrue() [1/2]
| bool HexagonInstrInfo::isPredicatedTrue | ( | const MachineInstr & | MI | ) | const |
Definition at line 2407 of file HexagonInstrInfo.cpp.
References F(), llvm::MachineInstr::getDesc(), llvm::HexagonII::PredicatedFalseMask, llvm::HexagonII::PredicatedFalsePos, and llvm::MCInstrDesc::TSFlags.
Referenced by getInvertedPredicatedOpcode(), getPredicateSense(), and predOpcodeHasNot().
◆ isPredicatedTrue() [2/2]
Definition at line 2413 of file HexagonInstrInfo.cpp.
References assert(), F(), llvm::HexagonII::PredicatedFalseMask, llvm::HexagonII::PredicatedFalsePos, llvm::HexagonII::PredicatedMask, and llvm::HexagonII::PredicatedPos.
◆ isPredicateLate()
Definition at line 2426 of file HexagonInstrInfo.cpp.
References F(), llvm::HexagonII::PredicateLateMask, and llvm::HexagonII::PredicateLatePos.
◆ isPredictedTaken()
Definition at line 2431 of file HexagonInstrInfo.cpp.
References assert(), F(), isBranch(), isNewValue(), isPredicatedNew(), llvm::HexagonII::TakenMask, and llvm::HexagonII::TakenPos.
Referenced by reversePrediction().
◆ isProfitableToDupForIfCvt()
|
override |
Return true if it's profitable for if-converter to duplicate instructions of specified accumulated instruction latencies in the specified MBB to enable if-conversion.
The probability of the instructions being executed is given by Probability, and Confidence is a measure of our confidence that it will be properly predicted.
Definition at line 773 of file HexagonInstrInfo.cpp.
◆ isProfitableToIfCvt() [1/2]
|
override |
Return true if it's profitable to predicate instructions with accumulated instruction latency of "NumCycles" of the specified basic block, where the probability of the instructions being executed is given by Probability, and Confidence is a measure of our confidence that it will be properly predicted.
Definition at line 760 of file HexagonInstrInfo.cpp.
References nonDbgBBSize().
◆ isProfitableToIfCvt() [2/2]
|
override |
Second variant of isProfitableToIfCvt.
This one checks for the case where two basic blocks from true and false path of a if-then-else (diamond) are predicated on mutally exclusive predicates, where the probability of the true path being taken is given by Probability, and Confidence is a measure of our confidence that it will be properly predicted.
Definition at line 766 of file HexagonInstrInfo.cpp.
References nonDbgBBSize().
◆ isSaveCalleeSavedRegsCall()
| bool HexagonInstrInfo::isSaveCalleeSavedRegsCall | ( | const MachineInstr & | MI | ) | const |
Definition at line 2438 of file HexagonInstrInfo.cpp.
References llvm::MachineInstr::getOpcode().
◆ isSchedulingBoundary()
|
override |
Test if the given instruction should be considered a scheduling boundary.
This primarily includes labels and terminators.
Definition at line 1639 of file HexagonInstrInfo.cpp.
References doesNotReturn(), llvm::MachineInstr::getDesc(), I, llvm::MachineInstr::isCall(), llvm::MachineInstr::isDebugInstr(), llvm::MachineInstr::isInlineAsm(), llvm::MachineInstr::isPosition(), llvm::MCInstrDesc::isTerminator(), ScheduleInlineAsm, and llvm::MachineBasicBlock::successors().
Referenced by INITIALIZE_PASS().
◆ isSignExtendingLoad()
| bool HexagonInstrInfo::isSignExtendingLoad | ( | const MachineInstr & | MI | ) | const |
Definition at line 2445 of file HexagonInstrInfo.cpp.
References llvm::MachineInstr::getOpcode().
◆ isSolo()
| bool HexagonInstrInfo::isSolo | ( | const MachineInstr & | MI | ) | const |
Definition at line 2523 of file HexagonInstrInfo.cpp.
References F(), llvm::MachineInstr::getDesc(), llvm::HexagonII::SoloMask, llvm::HexagonII::SoloPos, and llvm::MCInstrDesc::TSFlags.
◆ isSpillPredRegOp()
| bool HexagonInstrInfo::isSpillPredRegOp | ( | const MachineInstr & | MI | ) | const |
Definition at line 2528 of file HexagonInstrInfo.cpp.
References llvm::MachineInstr::getOpcode().
◆ isStoreToStackSlot()
|
override |
If the specified machine instruction is a direct store to a stack slot, return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot.
isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot, return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot.
If not, return 0. This predicate must return 0 if the instruction has any side effects other than storing to the stack slot.
Definition at line 288 of file HexagonInstrInfo.cpp.
References llvm::MachineOperand::getImm(), llvm::MachineOperand::getIndex(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::isFI(), and llvm::MachineOperand::isImm().
Referenced by dumpMachineInstrRangeWithSlotIndex(), and isFullCopyOf().
◆ isTailCall()
|
override |
Definition at line 2538 of file HexagonInstrInfo.cpp.
References llvm::MachineInstr::isBranch(), and llvm::MachineInstr::operands().
Referenced by isPredicable().
◆ isTC1()
| bool HexagonInstrInfo::isTC1 | ( | const MachineInstr & | MI | ) | const |
Definition at line 2549 of file HexagonInstrInfo.cpp.
References llvm::MachineInstr::getDesc(), llvm::MCInstrDesc::getSchedClass(), and llvm::is_TC1().
Referenced by isComplex().
◆ isTC2()
| bool HexagonInstrInfo::isTC2 | ( | const MachineInstr & | MI | ) | const |
Definition at line 2554 of file HexagonInstrInfo.cpp.
References llvm::MachineInstr::getDesc(), llvm::MCInstrDesc::getSchedClass(), and llvm::is_TC2().
◆ isTC2Early()
| bool HexagonInstrInfo::isTC2Early | ( | const MachineInstr & | MI | ) | const |
Definition at line 2559 of file HexagonInstrInfo.cpp.
References llvm::MachineInstr::getDesc(), llvm::MCInstrDesc::getSchedClass(), and llvm::is_TC2early().
Referenced by isComplex().
◆ isTC4x()
| bool HexagonInstrInfo::isTC4x | ( | const MachineInstr & | MI | ) | const |
Definition at line 2564 of file HexagonInstrInfo.cpp.
References llvm::MachineInstr::getDesc(), llvm::MCInstrDesc::getSchedClass(), and llvm::is_TC4x().
◆ isToBeScheduledASAP()
| bool HexagonInstrInfo::isToBeScheduledASAP | ( | const MachineInstr & | MI1, |
| const MachineInstr & | MI2 | ||
| ) | const |
Definition at line 2570 of file HexagonInstrInfo.cpp.
References llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), I, llvm::MachineOperand::isReg(), mayBeCurLoad(), mayBeNewStore(), and N.
Referenced by llvm::HexagonSubtarget::adjustSchedDependency(), and getZeroLatency().
◆ isValidAutoIncImm()
Definition at line 2594 of file HexagonInstrInfo.cpp.
References llvm::MVT::f32, llvm::MVT::f64, llvm::EVT::getSimpleVT(), llvm::EVT::getSizeInBits(), llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i64, llvm::MVT::i8, llvm_unreachable, llvm::MVT::SimpleTy, Size, llvm::MVT::v128i8, llvm::MVT::v16i32, llvm::MVT::v16i64, llvm::MVT::v2i16, llvm::MVT::v2i32, llvm::MVT::v32i16, llvm::MVT::v32i32, llvm::MVT::v4i16, llvm::MVT::v4i8, llvm::MVT::v64i16, llvm::MVT::v64i8, llvm::MVT::v8i64, and llvm::MVT::v8i8.
Referenced by llvm::HexagonDAGToDAGISel::SelectIndexedLoad(), and llvm::HexagonDAGToDAGISel::SelectIndexedStore().
◆ isValidOffset()
| bool HexagonInstrInfo::isValidOffset | ( | unsigned | Opcode, |
| int | Offset, | ||
| const TargetRegisterInfo * | TRI, | ||
| bool | Extend = true |
||
| ) | const |
Definition at line 2631 of file HexagonInstrInfo.cpp.
References assert(), llvm::TargetRegisterInfo::getSpillSize(), Hexagon_ADDI_OFFSET_MAX, Hexagon_MEMB_OFFSET_MAX, Hexagon_MEMD_OFFSET_MAX, Hexagon_MEMH_OFFSET_MAX, Hexagon_MEMW_OFFSET_MAX, llvm::ISD::INLINEASM, llvm::isPowerOf2_32(), llvm_unreachable, and llvm::Log2_32().
◆ isVecAcc()
| bool HexagonInstrInfo::isVecAcc | ( | const MachineInstr & | MI | ) | const |
Definition at line 2782 of file HexagonInstrInfo.cpp.
References isAccumulator(), and isHVXVec().
Referenced by isVecUsableNextPacket().
◆ isVecALU()
| bool HexagonInstrInfo::isVecALU | ( | const MachineInstr & | MI | ) | const |
Definition at line 2786 of file HexagonInstrInfo.cpp.
References F(), llvm::MachineInstr::getOpcode(), llvm::HexagonII::TypeCVI_VA, llvm::HexagonII::TypeCVI_VA_DV, llvm::HexagonII::TypeMask, and llvm::HexagonII::TypePos.
Referenced by isVecUsableNextPacket().
◆ isVecUsableNextPacket()
| bool HexagonInstrInfo::isVecUsableNextPacket | ( | const MachineInstr & | ProdMI, |
| const MachineInstr & | ConsMI | ||
| ) | const |
Definition at line 2794 of file HexagonInstrInfo.cpp.
References EnableACCForwarding, EnableALUForwarding, isLateSourceInstr(), isVecAcc(), isVecALU(), and mayBeNewStore().
Referenced by addLatencyToSchedule(), and producesStall().
◆ isZeroExtendingLoad()
| bool HexagonInstrInfo::isZeroExtendingLoad | ( | const MachineInstr & | MI | ) | const |
Definition at line 2808 of file HexagonInstrInfo.cpp.
References llvm::MachineInstr::getOpcode().
◆ loadRegFromStackSlot()
|
override |
Load the specified register of the given register class from the specified stack frame index.
The load instruction is to be added to the given machine basic block before the specified machine instruction.
Definition at line 940 of file HexagonInstrInfo.cpp.
References llvm::MachineInstrBuilder::addFrameIndex(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMemOperand(), llvm::BuildMI(), llvm::MachineBasicBlock::findDebugLoc(), llvm::MachinePointerInfo::getFixedStack(), llvm::MachineFunction::getFrameInfo(), llvm::HexagonSubtarget::getFrameLowering(), llvm::MachineFunction::getMachineMemOperand(), llvm::MachineFrameInfo::getObjectAlignment(), llvm::MachineFrameInfo::getObjectSize(), llvm::MachineBasicBlock::getParent(), llvm::TargetRegisterInfo::getSpillAlignment(), llvm::TargetFrameLowering::getStackAlignment(), llvm::MachineFrameInfo::hasVarSizedObjects(), llvm_unreachable, and llvm::MachineMemOperand::MOLoad.
Referenced by llvm::HexagonFrameLowering::assignCalleeSavedSpillSlots(), dumpMachineInstrRangeWithSlotIndex(), and getFrameIndexOperandNum().
◆ mayBeCurLoad()
| bool HexagonInstrInfo::mayBeCurLoad | ( | const MachineInstr & | MI | ) | const |
Definition at line 2999 of file HexagonInstrInfo.cpp.
References F(), llvm::MachineInstr::getDesc(), llvm::HexagonII::mayCVLoadMask, llvm::HexagonII::mayCVLoadPos, and llvm::MCInstrDesc::TSFlags.
Referenced by llvm::HexagonHazardRecognizer::EmitInstruction(), hasDependence(), and isToBeScheduledASAP().
◆ mayBeNewStore()
| bool HexagonInstrInfo::mayBeNewStore | ( | const MachineInstr & | MI | ) | const |
Definition at line 3006 of file HexagonInstrInfo.cpp.
References F(), llvm::MachineInstr::getDesc(), llvm::HexagonII::mayNVStoreMask, llvm::HexagonII::mayNVStorePos, llvm::MachineInstr::mayStore(), and llvm::MCInstrDesc::TSFlags.
Referenced by canExecuteInBundle(), llvm::HexagonHazardRecognizer::EmitInstruction(), llvm::HexagonHazardRecognizer::getHazardType(), isToBeScheduledASAP(), and isVecUsableNextPacket().
◆ nonDbgBBSize()
| unsigned HexagonInstrInfo::nonDbgBBSize | ( | const MachineBasicBlock * | BB | ) | const |
getInstrTimingClassLatency - Compute the instruction latency of a given instruction using Timing Class information, if available.
Definition at line 4295 of file HexagonInstrInfo.cpp.
References llvm::MachineBasicBlock::instr_begin(), llvm::MachineBasicBlock::instr_end(), and nonDbgMICount().
Referenced by isProfitableToIfCvt().
◆ nonDbgBundleSize()
| unsigned HexagonInstrInfo::nonDbgBundleSize | ( | MachineBasicBlock::const_iterator | BundleHead | ) | const |
Definition at line 4299 of file HexagonInstrInfo.cpp.
References assert(), llvm::getBundleEnd(), llvm::MachineInstrBundleIterator< Ty, IsReverse >::getInstrIterator(), and nonDbgMICount().
◆ predCanBeUsedAsDotNew()
| bool HexagonInstrInfo::predCanBeUsedAsDotNew | ( | const MachineInstr & | MI, |
| unsigned | PredReg | ||
| ) | const |
Definition at line 3052 of file HexagonInstrInfo.cpp.
References llvm::MachineInstr::getOpcode(), and llvm::MachineInstr::operands().
◆ PredicateInstruction()
|
override |
Convert the instruction into a predicated instruction.
It returns true if the operation was successful.
Definition at line 1519 of file HexagonInstrInfo.cpp.
References llvm::MachineInstrBuilder::add(), llvm::MachineInstr::addOperand(), llvm::MachineInstrBuilder::addReg(), assert(), B, llvm::BuildMI(), llvm::MachineRegisterInfo::clearKillFlags(), llvm::dbgs(), llvm::MachineInstr::dump(), llvm::ArrayRef< T >::empty(), llvm::MachineBasicBlock::erase(), getCondOpcode(), llvm::MachineInstr::getDebugLoc(), llvm::ilist_node_impl< OptionsT >::getIterator(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), getPredReg(), llvm::MachineFunction::getRegInfo(), llvm::MachineOperand::isDef(), isEndLoopN(), llvm::MachineOperand::isImplicit(), isNewValueJump(), isPredicable(), llvm::MachineOperand::isReg(), LLVM_DEBUG, MRI, predOpcodeHasNot(), llvm::MachineInstr::RemoveOperand(), and llvm::MachineInstr::setDesc().
◆ PredOpcodeHasJMP_c()
Definition at line 3087 of file HexagonInstrInfo.cpp.
Referenced by analyzeBranch(), and profitImm().
◆ predOpcodeHasNot()
| bool HexagonInstrInfo::predOpcodeHasNot | ( | ArrayRef< MachineOperand > | Cond | ) | const |
Definition at line 3098 of file HexagonInstrInfo.cpp.
References llvm::ArrayRef< T >::empty(), isPredicated(), and isPredicatedTrue().
Referenced by llvm::createHexagonHardwareLoops(), and PredicateInstruction().
◆ producesStall() [1/2]
| bool HexagonInstrInfo::producesStall | ( | const MachineInstr & | ProdMI, |
| const MachineInstr & | ConsMI | ||
| ) | const |
Definition at line 3014 of file HexagonInstrInfo.cpp.
References isDependent(), isHVXVec(), and isVecUsableNextPacket().
Referenced by producesStall().
◆ producesStall() [2/2]
| bool HexagonInstrInfo::producesStall | ( | const MachineInstr & | MI, |
| MachineBasicBlock::const_instr_iterator | MII | ||
| ) | const |
Definition at line 3032 of file HexagonInstrInfo.cpp.
References isHVXVec(), and producesStall().
◆ reduceLoopCount()
|
override |
Generate code to reduce the loop iteration by one and check if the loop is finished.
Return the value/register of the new loop count. We need this function when peeling off one or more iterations of a loop. This function assumes the nth iteration is peeled first.
Return the value/register of the new loop count. this function assumes the nth iteration is peeled first.
Definition at line 701 of file HexagonInstrInfo.cpp.
References llvm::MachineInstrBuilder::addImm(), assert(), llvm::SmallVectorTemplateCommon< T, typename >::begin(), llvm::BuildMI(), llvm::SmallVectorImpl< T >::clear(), llvm::MachineOperand::CreateImm(), createVR(), E, llvm::SmallVectorTemplateCommon< T, typename >::end(), llvm::MachineInstr::eraseFromParent(), findLoopInstr(), llvm::MachineInstr::getDebugLoc(), llvm::MachineOperand::getImm(), llvm::MachineOperand::getMBB(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getReg(), llvm::HexagonSubtarget::getRegisterInfo(), I, llvm::MVT::i1, llvm::MVT::i32, isEndLoopN(), llvm::SmallVectorTemplateBase< T >::push_back(), llvm::SmallVectorTemplateBase< T, bool >::push_back(), and llvm::MachineOperand::setImm().
◆ removeBranch()
|
override |
Remove the branching code at the end of the specific MBB.
This is only invoked in cases where AnalyzeBranch returns success. It returns the number of instructions that were removed.
Definition at line 556 of file HexagonInstrInfo.cpp.
References assert(), llvm::MachineBasicBlock::back(), llvm::MachineBasicBlock::begin(), llvm::dbgs(), llvm::MachineBasicBlock::end(), llvm::MachineBasicBlock::erase(), I, LLVM_DEBUG, llvm_unreachable, and llvm::printMBBReference().
Referenced by insertBranch().
◆ reverseBranchCondition()
|
override |
Reverses the branch condition of the specified condition list, returning false on success and true if it cannot be reversed.
Definition at line 1481 of file HexagonInstrInfo.cpp.
References assert(), llvm::SmallVectorBase::empty(), getInvertedPredicatedOpcode(), isBranch(), and isEndLoopN().
Referenced by insertBranch(), and isInRage().
◆ reversePrediction()
Definition at line 4372 of file HexagonInstrInfo.cpp.
References assert(), and isPredictedTaken().
Referenced by invertAndChangeJumpTarget().
◆ reversePredSense()
| bool HexagonInstrInfo::reversePredSense | ( | MachineInstr & | MI | ) | const |
Definition at line 4365 of file HexagonInstrInfo.cpp.
References llvm::dbgs(), llvm::MachineInstr::dump(), getInvertedPredicatedOpcode(), llvm::MachineInstr::getOpcode(), LLVM_DEBUG, and llvm::MachineInstr::setDesc().
◆ setBundleNoShuf()
| void HexagonInstrInfo::setBundleNoShuf | ( | MachineBasicBlock::instr_iterator | MIB | ) | const |
Definition at line 4389 of file HexagonInstrInfo.cpp.
References assert(), llvm::MachineOperand::CreateImm(), and llvm::MachineOperand::setImm().
Referenced by validateBranchCond().
◆ storeRegToStackSlot()
|
override |
Store the specified register of the given register class to the specified stack frame index.
The store instruction is to be added to the given machine basic block before the specified machine instruction. If isKill is true, the register operand is the last use and must be marked kill.
Definition at line 875 of file HexagonInstrInfo.cpp.
References llvm::MachineInstrBuilder::addFrameIndex(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMemOperand(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::MachineBasicBlock::findDebugLoc(), llvm::MachinePointerInfo::getFixedStack(), llvm::MachineFunction::getFrameInfo(), llvm::HexagonSubtarget::getFrameLowering(), llvm::getKillRegState(), llvm::MachineFunction::getMachineMemOperand(), llvm::MachineFrameInfo::getObjectAlignment(), llvm::MachineFrameInfo::getObjectSize(), llvm::MachineBasicBlock::getParent(), llvm::TargetRegisterInfo::getSpillAlignment(), llvm::TargetFrameLowering::getStackAlignment(), llvm::MachineFrameInfo::hasVarSizedObjects(), llvm_unreachable, and llvm::MachineMemOperand::MOStore.
Referenced by llvm::HexagonFrameLowering::assignCalleeSavedSpillSlots(), getFrameIndexOperandNum(), isFullCopyOf(), and isFullUndefDef().
◆ SubsumesPredicate()
|
override |
Returns true if the first specified predicate subsumes the second, e.g.
GE subsumes GT.
Definition at line 1570 of file HexagonInstrInfo.cpp.
◆ validateBranchCond()
| bool HexagonInstrInfo::validateBranchCond | ( | const ArrayRef< MachineOperand > & | Cond | ) | const |
Definition at line 4383 of file HexagonInstrInfo.cpp.
References llvm::ArrayRef< T >::empty(), setBundleNoShuf(), and llvm::ArrayRef< T >::size().
Referenced by insertBranch().
The documentation for this class was generated from the following files:
- lib/Target/Hexagon/HexagonInstrInfo.h
- lib/Target/Hexagon/HexagonInstrInfo.cpp
