llvm::AArch64InstrInfo Class Reference

#include "Target/AArch64/AArch64InstrInfo.h"

Inheritance diagram for llvm::AArch64InstrInfo:

Collaboration diagram for llvm::AArch64InstrInfo:

Public Member Functions
	AArch64InstrInfo (const AArch64Subtarget &STI)
const AArch64RegisterInfo &	getRegisterInfo () const
	getRegisterInfo - TargetInstrInfo is a superset of MRegister info. More...
unsigned	getInstSizeInBytes (const MachineInstr &MI) const override
	GetInstSize - Return the number of bytes of code the specified instruction may be. More...
bool	isAsCheapAsAMove (const MachineInstr &MI) const override
bool	isCoalescableExtInstr (const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg, unsigned &SubIdx) const override
bool	areMemAccessesTriviallyDisjoint (MachineInstr &MIa, MachineInstr &MIb, AliasAnalysis *AA=nullptr) const override
unsigned	isLoadFromStackSlot (const MachineInstr &MI, int &FrameIndex) const override
unsigned	isStoreToStackSlot (const MachineInstr &MI, int &FrameIndex) const override
bool	isCandidateToMergeOrPair (MachineInstr &MI) const
	Return true if this is a load/store that can be potentially paired/merged. More...
bool	getMemOperandWithOffset (MachineInstr &MI, MachineOperand *&BaseOp, int64_t &Offset, const TargetRegisterInfo *TRI) const override
bool	getMemOperandWithOffsetWidth (MachineInstr &MI, MachineOperand *&BaseOp, int64_t &Offset, unsigned &Width, const TargetRegisterInfo *TRI) const
MachineOperand &	getMemOpBaseRegImmOfsOffsetOperand (MachineInstr &LdSt) const
	Return the immediate offset of the base register in a load/store LdSt. More...
bool	getMemOpInfo (unsigned Opcode, unsigned &Scale, unsigned &Width, int64_t &MinOffset, int64_t &MaxOffset) const
	Returns true if opcode Opc is a memory operation. More...
bool	shouldClusterMemOps (MachineOperand &BaseOp1, MachineOperand &BaseOp2, unsigned NumLoads) const override
	Detect opportunities for ldp/stp formation. More...
void	copyPhysRegTuple (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, bool KillSrc, unsigned Opcode, llvm::ArrayRef< unsigned > Indices) const
void	copyGPRRegTuple (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc, unsigned Opcode, unsigned ZeroReg, llvm::ArrayRef< unsigned > Indices) const
void	copyPhysReg (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
void	storeRegToStackSlot (MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
void	loadRegFromStackSlot (MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
bool	isSubregFoldable () const override
MachineInstr *	foldMemoryOperandImpl (MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex, LiveIntervals *LIS=nullptr) const override
bool	isBranchOffsetInRange (unsigned BranchOpc, int64_t BrOffset) const override
MachineBasicBlock *	getBranchDestBlock (const MachineInstr &MI) const override
bool	analyzeBranch (MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const override
unsigned	removeBranch (MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
unsigned	insertBranch (MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
bool	reverseBranchCondition (SmallVectorImpl< MachineOperand > &Cond) const override
bool	canInsertSelect (const MachineBasicBlock &, ArrayRef< MachineOperand > Cond, unsigned, unsigned, int &, int &, int &) const override
void	insertSelect (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, unsigned DstReg, ArrayRef< MachineOperand > Cond, unsigned TrueReg, unsigned FalseReg) const override
void	getNoop (MCInst &NopInst) const override
bool	isSchedulingBoundary (const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const override
bool	analyzeCompare (const MachineInstr &MI, unsigned &SrcReg, unsigned &SrcReg2, int &CmpMask, int &CmpValue) const override
	analyzeCompare - For a comparison instruction, return the source registers in SrcReg and SrcReg2, and the value it compares against in CmpValue. More...
bool	optimizeCompareInstr (MachineInstr &CmpInstr, unsigned SrcReg, unsigned SrcReg2, int CmpMask, int CmpValue, const MachineRegisterInfo *MRI) const override
	optimizeCompareInstr - Convert the instruction supplying the argument to the comparison into one that sets the zero bit in the flags register. More...
bool	optimizeCondBranch (MachineInstr &MI) const override
	Replace csincr-branch sequence by simple conditional branch. More...
bool	isThroughputPattern (MachineCombinerPattern Pattern) const override
	Return true when a code sequence can improve throughput. More...
bool	getMachineCombinerPatterns (MachineInstr &Root, SmallVectorImpl< MachineCombinerPattern > &Patterns) const override
	Return true when there is potentially a faster code sequence for an instruction chain ending in Root. More...
bool	isAssociativeAndCommutative (const MachineInstr &Inst) const override
	Return true when Inst is associative and commutative so that it can be reassociated. More...
void	genAlternativeCodeSequence (MachineInstr &Root, MachineCombinerPattern Pattern, SmallVectorImpl< MachineInstr *> &InsInstrs, SmallVectorImpl< MachineInstr *> &DelInstrs, DenseMap< unsigned, unsigned > &InstrIdxForVirtReg) const override
	When getMachineCombinerPatterns() finds patterns, this function generates the instructions that could replace the original code sequence. More...
bool	useMachineCombiner () const override
	AArch64 supports MachineCombiner. More...
bool	expandPostRAPseudo (MachineInstr &MI) const override
std::pair< unsigned, unsigned >	decomposeMachineOperandsTargetFlags (unsigned TF) const override
ArrayRef< std::pair< unsigned, const char * > >	getSerializableDirectMachineOperandTargetFlags () const override
ArrayRef< std::pair< unsigned, const char * > >	getSerializableBitmaskMachineOperandTargetFlags () const override
ArrayRef< std::pair< MachineMemOperand::Flags, const char * > >	getSerializableMachineMemOperandTargetFlags () const override
bool	isFunctionSafeToOutlineFrom (MachineFunction &MF, bool OutlineFromLinkOnceODRs) const override
outliner::OutlinedFunction	getOutliningCandidateInfo (std::vector< outliner::Candidate > &RepeatedSequenceLocs) const override
outliner::InstrType	getOutliningType (MachineBasicBlock::iterator &MIT, unsigned Flags) const override
bool	isMBBSafeToOutlineFrom (MachineBasicBlock &MBB, unsigned &Flags) const override
void	buildOutlinedFrame (MachineBasicBlock &MBB, MachineFunction &MF, const outliner::OutlinedFunction &OF) const override
MachineBasicBlock::iterator	insertOutlinedCall (Module &M, MachineBasicBlock &MBB, MachineBasicBlock::iterator &It, MachineFunction &MF, const outliner::Candidate &C) const override
bool	shouldOutlineFromFunctionByDefault (MachineFunction &MF) const override

Static Public Member Functions
static bool	isGPRZero (const MachineInstr &MI)
	Does this instruction set its full destination register to zero? More...
static bool	isGPRCopy (const MachineInstr &MI)
	Does this instruction rename a GPR without modifying bits? More...
static bool	isFPRCopy (const MachineInstr &MI)
	Does this instruction rename an FPR without modifying bits? More...
static bool	isLdStPairSuppressed (const MachineInstr &MI)
	Return true if pairing the given load or store is hinted to be unprofitable. More...
static bool	isStridedAccess (const MachineInstr &MI)
	Return true if the given load or store is a strided memory access. More...
static bool	isUnscaledLdSt (unsigned Opc)
	Return true if this is an unscaled load/store. More...
static bool	isUnscaledLdSt (MachineInstr &MI)
static bool	isPairableLdStInst (const MachineInstr &MI)
	Return true if pairing the given load or store may be paired with another. More...
static unsigned	convertToFlagSettingOpc (unsigned Opc, bool &Is64Bit)
	Return the opcode that set flags when possible. More...
static void	suppressLdStPair (MachineInstr &MI)
	Hint that pairing the given load or store is unprofitable. More...
static bool	isFalkorShiftExtFast (const MachineInstr &MI)
	Returns true if the instruction has a shift by immediate that can be executed in one cycle less. More...
static bool	isSEHInstruction (const MachineInstr &MI)
	Return true if the instructions is a SEH instruciton used for unwinding on Windows. More...

Detailed Description

Definition at line 37 of file AArch64InstrInfo.h.

Constructor & Destructor Documentation

AArch64InstrInfo()

AArch64InstrInfo::AArch64InstrInfo ( const AArch64Subtarget &  STI )

explicit

Definition at line 68 of file AArch64InstrInfo.cpp.

Member Function Documentation

analyzeBranch()

bool AArch64InstrInfo::analyzeBranch ( MachineBasicBlock &  MBB, MachineBasicBlock *&  TBB, MachineBasicBlock *&  FBB, SmallVectorImpl< MachineOperand > &  Cond, bool  AllowModify = false  ) const

override

Definition at line 207 of file AArch64InstrInfo.cpp.

References llvm::MachineBasicBlock::begin(), llvm::MachineBasicBlock::end(), llvm::MachineInstr::eraseFromParent(), llvm::MachineBasicBlock::getLastNonDebugInstr(), llvm::MachineOperand::getMBB(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), I, llvm::isCondBranchOpcode(), llvm::isIndirectBranchOpcode(), llvm::isUncondBranchOpcode(), and parseCondBranch().

Referenced by isSubregFoldable().

analyzeCompare()

bool AArch64InstrInfo::analyzeCompare ( const MachineInstr &  MI, unsigned &  SrcReg, unsigned &  SrcReg2, int &  CmpMask, int &  CmpValue  ) const

override

analyzeCompare - For a comparison instruction, return the source registers in SrcReg and SrcReg2, and the value it compares against in CmpValue.

Return true if the comparison instruction can be analyzed.

Definition at line 985 of file AArch64InstrInfo.cpp.

References assert(), llvm::AArch64_AM::decodeLogicalImmediate(), llvm::MachineOperand::getImm(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), and llvm::MachineOperand::isReg().

Referenced by isSubregFoldable().

areMemAccessesTriviallyDisjoint()

bool AArch64InstrInfo::areMemAccessesTriviallyDisjoint ( MachineInstr &  MIa, MachineInstr &  MIb, AliasAnalysis *  AA = nullptr  ) const

override

Definition at line 930 of file AArch64InstrInfo.cpp.

References assert(), getMemOperandWithOffsetWidth(), getRegisterInfo(), llvm::MachineInstr::hasOrderedMemoryRef(), llvm::MachineInstr::hasUnmodeledSideEffects(), llvm::MachineOperand::isIdenticalTo(), llvm::MachineInstr::mayLoadOrStore(), and TRI.

Referenced by getRegisterInfo().

buildOutlinedFrame()

void AArch64InstrInfo::buildOutlinedFrame ( MachineBasicBlock &  MBB, MachineFunction &  MF, const outliner::OutlinedFunction &  OF  ) const

override

Definition at line 5407 of file AArch64InstrInfo.cpp.

References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addCFIIndex(), llvm::MachineFunction::addFrameInst(), llvm::MachineInstrBuilder::addImm(), llvm::MachineBasicBlock::addLiveIn(), llvm::MachineInstrBuilder::addReg(), llvm::any_of(), assert(), llvm::MachineBasicBlock::begin(), llvm::ARCISD::BL, llvm::BuildMI(), llvm::MCCFIInstruction::createDefCfaOffset(), llvm::MCCFIInstruction::createOffset(), llvm::RegState::Define, llvm::MachineBasicBlock::end(), llvm::MachineInstr::eraseFromParent(), llvm::outliner::OutlinedFunction::FrameConstructionID, llvm::MachineInstr::FrameSetup, llvm::MCRegisterInfo::getDwarfRegNum(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::TargetSubtargetInfo::getRegisterInfo(), llvm::MachineFunction::getSubtarget(), llvm::MachineBasicBlock::insert(), llvm::MachineBasicBlock::instr_begin(), llvm::MachineBasicBlock::instr_end(), MachineOutlinerDefault, MachineOutlinerTailCall, MachineOutlinerThunk, MI, llvm::ARCISD::RET, llvm::MachineInstrBuilder::setMIFlags(), and llvm::RegState::Undef.

Referenced by isSubregFoldable().

canInsertSelect()

bool AArch64InstrInfo::canInsertSelect ( const MachineBasicBlock &  MBB, ArrayRef< MachineOperand >  Cond, unsigned  TrueReg, unsigned  FalseReg, int &  CondCycles, int &  TrueCycles, int &  FalseCycles  ) const

override

Definition at line 495 of file AArch64InstrInfo.cpp.

References canFoldIntoCSel(), llvm::MachineBasicBlock::getParent(), llvm::MachineRegisterInfo::getRegClass(), llvm::MachineFunction::getRegInfo(), MRI, and llvm::ArrayRef< T >::size().

Referenced by isSubregFoldable().

convertToFlagSettingOpc()

unsigned AArch64InstrInfo::convertToFlagSettingOpc ( unsigned  Opc, bool &  Is64Bit  )

static

Return the opcode that set flags when possible.

The caller is responsible for ensuring the opc has a flag setting equivalent.

Definition at line 1750 of file AArch64InstrInfo.cpp.

References llvm_unreachable.

Referenced by isUnscaledLdSt().

copyGPRRegTuple()

void AArch64InstrInfo::copyGPRRegTuple	(	MachineBasicBlock &	MBB,
		MachineBasicBlock::iterator	I,
		DebugLoc	DL,
		unsigned	DestReg,
		unsigned	SrcReg,
		bool	KillSrc,
		unsigned	Opcode,
		unsigned	ZeroReg,
		llvm::ArrayRef< unsigned >	Indices
	)		const

Definition at line 2295 of file AArch64InstrInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), AddSubReg(), assert(), llvm::BuildMI(), llvm::RegState::Define, llvm::MCRegisterInfo::getEncodingValue(), llvm::getKillRegState(), getRegisterInfo(), llvm::ArrayRef< T >::size(), SubReg, and TRI.

Referenced by copyPhysReg(), and isUnscaledLdSt().

copyPhysReg()

void AArch64InstrInfo::copyPhysReg ( MachineBasicBlock &  MBB, MachineBasicBlock::iterator  I, const DebugLoc &  DL, unsigned  DestReg, unsigned  SrcReg, bool  KillSrc  ) const

override

Definition at line 2320 of file AArch64InstrInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), contains(), copyGPRRegTuple(), copyPhysRegTuple(), llvm::RegState::Define, llvm::getKillRegState(), llvm::TargetRegisterInfo::getMatchingSuperReg(), getRegisterInfo(), llvm::AArch64_AM::getShifterImm(), llvm::RegState::Implicit, llvm_unreachable, llvm::AArch64_AM::LSL, TRI, and llvm::RegState::Undef.

Referenced by isUnscaledLdSt().

copyPhysRegTuple()

void AArch64InstrInfo::copyPhysRegTuple	(	MachineBasicBlock &	MBB,
		MachineBasicBlock::iterator	I,
		const DebugLoc &	DL,
		unsigned	DestReg,
		unsigned	SrcReg,
		bool	KillSrc,
		unsigned	Opcode,
		llvm::ArrayRef< unsigned >	Indices
	)		const

Definition at line 2268 of file AArch64InstrInfo.cpp.

References assert(), getRegisterInfo(), llvm::ArrayRef< T >::size(), SubReg, and TRI.

Referenced by copyPhysReg(), and isUnscaledLdSt().

decomposeMachineOperandsTargetFlags()

std::pair< unsigned, unsigned > AArch64InstrInfo::decomposeMachineOperandsTargetFlags ( unsigned  TF ) const

override

Definition at line 4771 of file AArch64InstrInfo.cpp.

References llvm::BitmaskEnumDetail::Mask(), and llvm::AArch64II::MO_FRAGMENT.

Referenced by isSubregFoldable().

expandPostRAPseudo()

bool AArch64InstrInfo::expandPostRAPseudo ( MachineInstr &  MI ) const

override

Definition at line 1467 of file AArch64InstrInfo.cpp.

References llvm::MachineInstrBuilder::addGlobalAddress(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMBB(), llvm::MachineInstrBuilder::addMemOperand(), llvm::MachineInstrBuilder::addReg(), llvm::AArch64ISD::ADR, llvm::AArch64ISD::ADRP, llvm::MachineBasicBlock::begin(), llvm::BuildMI(), llvm::ISD::CATCHRET, llvm::RegState::Define, llvm::MachineBasicBlock::erase(), llvm::MachineInstr::FrameDestroy, llvm::MCInstrInfo::get(), llvm::MachineInstr::getDebugLoc(), llvm::TargetSubtargetInfo::getInstrInfo(), llvm::MachineOperand::getMBB(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getSubtarget(), llvm::MachineFunction::getTarget(), llvm::RegState::Kill, llvm::CodeModel::Large, llvm::AArch64ISD::LOADgot, llvm::MachineInstr::memoperands_begin(), llvm::AArch64II::MO_G0, llvm::AArch64II::MO_G1, llvm::AArch64II::MO_G2, llvm::AArch64II::MO_G3, llvm::AArch64II::MO_GOT, llvm::AArch64II::MO_NC, llvm::AArch64II::MO_PAGE, llvm::AArch64II::MO_PAGEOFF, Reg, TII, llvm::CodeModel::Tiny, and llvm::SystemZISD::TM.

Referenced by isSubregFoldable().

foldMemoryOperandImpl()

MachineInstr * AArch64InstrInfo::foldMemoryOperandImpl ( MachineFunction &  MF, MachineInstr &  MI, ArrayRef< unsigned >  Ops, MachineBasicBlock::iterator  InsertPt, int  FrameIndex, LiveIntervals *  LIS = nullptr  ) const

override

Definition at line 2960 of file AArch64InstrInfo.cpp.

References assert(), llvm::MachineRegisterInfo::constrainRegClass(), contains(), llvm::ISD::FrameIndex, llvm::TargetRegisterInfo::getMatchingSuperReg(), llvm::TargetRegisterInfo::getMinimalPhysRegClass(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), llvm::MachineRegisterInfo::getRegClass(), getRegClass(), llvm::MachineFunction::getRegInfo(), llvm::TargetSubtargetInfo::getRegisterInfo(), llvm::TargetRegisterInfo::getRegSizeInBits(), llvm::MachineOperand::getSubReg(), llvm::MachineFunction::getSubtarget(), llvm::MachineInstr::isCopy(), llvm::MachineInstr::isFullCopy(), llvm::MachineOperand::isKill(), llvm::TargetRegisterInfo::isPhysicalRegister(), llvm::MachineOperand::isUndef(), llvm::TargetRegisterInfo::isVirtualRegister(), loadRegFromStackSlot(), Reg, llvm::MachineOperand::setIsUndef(), llvm::MachineOperand::setSubReg(), llvm::ArrayRef< T >::size(), storeRegToStackSlot(), and TRI.

Referenced by isSubregFoldable().

genAlternativeCodeSequence()

void AArch64InstrInfo::genAlternativeCodeSequence ( MachineInstr &  Root, MachineCombinerPattern  Pattern, SmallVectorImpl< MachineInstr *> &  InsInstrs, SmallVectorImpl< MachineInstr *> &  DelInstrs, DenseMap< unsigned, unsigned > &  InstrIdxForVirtReg  ) const

override

When getMachineCombinerPatterns() finds patterns, this function generates the instructions that could replace the original code sequence.

When getMachineCombinerPatterns() finds potential patterns, this function generates the instructions that could replace the original code sequence.

Definition at line 4100 of file AArch64InstrInfo.cpp.

References Accumulator, llvm::ARM_AM::add, llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addImm(), llvm::BuildMI(), llvm::MachineRegisterInfo::createVirtualRegister(), llvm::FMLAv1i32_indexed_OP1, llvm::FMLAv1i32_indexed_OP2, llvm::FMLAv1i64_indexed_OP1, llvm::FMLAv1i64_indexed_OP2, llvm::FMLAv2f32_OP1, llvm::FMLAv2f32_OP2, llvm::FMLAv2f64_OP1, llvm::FMLAv2f64_OP2, llvm::FMLAv2i32_indexed_OP1, llvm::FMLAv2i32_indexed_OP2, llvm::FMLAv2i64_indexed_OP1, llvm::FMLAv2i64_indexed_OP2, llvm::FMLAv4f32_OP1, llvm::FMLAv4f32_OP2, llvm::FMLAv4i32_indexed_OP1, llvm::FMLAv4i32_indexed_OP2, llvm::FMLSv1i32_indexed_OP2, llvm::FMLSv1i64_indexed_OP2, llvm::FMLSv2f32_OP1, llvm::FMLSv2f32_OP2, llvm::FMLSv2f64_OP1, llvm::FMLSv2f64_OP2, llvm::FMLSv2i32_indexed_OP1, llvm::FMLSv2i32_indexed_OP2, llvm::FMLSv2i64_indexed_OP1, llvm::FMLSv2i64_indexed_OP2, llvm::FMLSv4f32_OP1, llvm::FMLSv4f32_OP2, llvm::FMLSv4i32_indexed_OP1, llvm::FMLSv4i32_indexed_OP2, llvm::FMULADDD_OP1, llvm::FMULADDD_OP2, llvm::FMULADDS_OP1, llvm::FMULADDS_OP2, llvm::FMULSUBD_OP1, llvm::FMULSUBD_OP2, llvm::FMULSUBS_OP1, llvm::FMULSUBS_OP2, llvm::FNMULSUBD_OP1, llvm::FNMULSUBS_OP1, llvm::TargetInstrInfo::genAlternativeCodeSequence(), genFusedMultiply(), genMaddR(), llvm::MCInstrInfo::get(), llvm::MachineInstr::getDebugLoc(), llvm::MachineOperand::getImm(), llvm::TargetSubtargetInfo::getInstrInfo(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), llvm::MachineFunction::getRegInfo(), llvm::MachineFunction::getSubtarget(), Indexed, llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::insert(), llvm::MachineOperand::isImm(), llvm::ISD::MUL, llvm::MULADDW_OP1, llvm::MULADDW_OP2, llvm::MULADDWI_OP1, llvm::MULADDX_OP1, llvm::MULADDX_OP2, llvm::MULADDXI_OP1, llvm::MULSUBW_OP1, llvm::MULSUBW_OP2, llvm::MULSUBWI_OP1, llvm::MULSUBX_OP1, llvm::MULSUBX_OP2, llvm::MULSUBXI_OP1, llvm::AArch64_AM::processLogicalImmediate(), llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::SignExtend64(), and TII.

Referenced by isSubregFoldable().

getBranchDestBlock()

MachineBasicBlock * AArch64InstrInfo::getBranchDestBlock ( const MachineInstr &  MI ) const

override

Definition at line 186 of file AArch64InstrInfo.cpp.

References B, llvm::MachineOperand::getMBB(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), and llvm_unreachable.

Referenced by isSubregFoldable().

getInstSizeInBytes()

unsigned AArch64InstrInfo::getInstSizeInBytes ( const MachineInstr &  MI ) const

override

GetInstSize - Return the number of bytes of code the specified instruction may be.

This returns the maximum number of bytes.

Definition at line 75 of file AArch64InstrInfo.cpp.

References assert(), llvm::ISD::EH_LABEL, llvm::MachineInstr::getDesc(), llvm::MachineOperand::getImm(), llvm::TargetMachine::getMCAsmInfo(), llvm::StackMapOpers::getNumPatchBytes(), llvm::PatchPointOpers::getNumPatchBytes(), llvm::MCInstrDesc::getOpcode(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getSymbolName(), llvm::MachineFunction::getTarget(), llvm::ISD::INLINEASM, llvm::AMDGPUISD::KILL, and llvm::AArch64ISD::TLSDESC_CALLSEQ.

Referenced by getOutliningCandidateInfo(), and getRegisterInfo().

getMachineCombinerPatterns()

bool AArch64InstrInfo::getMachineCombinerPatterns ( MachineInstr &  Root, SmallVectorImpl< MachineCombinerPattern > &  Patterns  ) const

override

Return true when there is potentially a faster code sequence for an instruction chain ending in Root.

Return true when there is potentially a faster code sequence for an instruction chain ending in Root.

All potential patterns are listed in the Patterns array.

All potential patterns are listed in the Pattern vector. Pattern should be sorted in priority order since the pattern evaluator stops checking as soon as it finds a faster sequence.

Definition at line 3951 of file AArch64InstrInfo.cpp.

References getFMAPatterns(), llvm::TargetInstrInfo::getMachineCombinerPatterns(), and getMaddPatterns().

Referenced by isSubregFoldable().

getMemOpBaseRegImmOfsOffsetOperand()

MachineOperand & AArch64InstrInfo::getMemOpBaseRegImmOfsOffsetOperand

(

MachineInstr &

LdSt

)

const

Return the immediate offset of the base register in a load/store LdSt.

Definition at line 1938 of file AArch64InstrInfo.cpp.

References assert(), llvm::MachineInstr::getNumExplicitOperands(), llvm::MachineInstr::getOperand(), and llvm::MachineInstr::mayLoadOrStore().

Referenced by getOutliningType(), and isUnscaledLdSt().

getMemOperandWithOffset()

bool AArch64InstrInfo::getMemOperandWithOffset ( MachineInstr &  MI, MachineOperand *&  BaseOp, int64_t &  Offset, const TargetRegisterInfo *  TRI  ) const

override

Definition at line 1882 of file AArch64InstrInfo.cpp.

References getMemOperandWithOffsetWidth().

Referenced by getOutliningCandidateInfo(), and isUnscaledLdSt().

getMemOperandWithOffsetWidth()

bool AArch64InstrInfo::getMemOperandWithOffsetWidth	(	MachineInstr &	MI,
		MachineOperand *&	BaseOp,
		int64_t &	Offset,
		unsigned &	Width,
		const TargetRegisterInfo *	TRI
	)		const

Definition at line 1890 of file AArch64InstrInfo.cpp.

References assert(), llvm::MachineOperand::getImm(), getMemOpInfo(), llvm::MachineInstr::getNumExplicitOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::isFI(), llvm::MachineOperand::isImm(), llvm::MachineOperand::isReg(), and llvm::MachineInstr::mayLoadOrStore().

Referenced by areMemAccessesTriviallyDisjoint(), getMemOperandWithOffset(), getOutliningType(), and isUnscaledLdSt().

getMemOpInfo()

bool AArch64InstrInfo::getMemOpInfo	(	unsigned	Opcode,
		unsigned &	Scale,
		unsigned &	Width,
		int64_t &	MinOffset,
		int64_t &	MaxOffset
	)		const

Returns true if opcode Opc is a memory operation.

If it is, set Scale, Width, MinOffset, and MaxOffset accordingly.

For unscaled instructions, Scale is set to 1.

Definition at line 1945 of file AArch64InstrInfo.cpp.

Referenced by getMemOperandWithOffsetWidth(), getOutliningCandidateInfo(), getOutliningType(), and isUnscaledLdSt().

getNoop()

void AArch64InstrInfo::getNoop ( MCInst &  NopInst ) const

override

Definition at line 3415 of file AArch64InstrInfo.cpp.

References llvm::MCInst::addOperand(), llvm::MCOperand::createImm(), and llvm::MCInst::setOpcode().

Referenced by isSubregFoldable().

getOutliningCandidateInfo()

outliner::OutlinedFunction AArch64InstrInfo::getOutliningCandidateInfo ( std::vector< outliner::Candidate > &  RepeatedSequenceLocs ) const

override

Definition at line 4925 of file AArch64InstrInfo.cpp.

References llvm::all_of(), llvm::any_of(), llvm::LiveRegUnits::available(), llvm::outliner::Candidate::back(), llvm::ARCISD::BL, C, llvm::for_each(), llvm::outliner::Candidate::front(), llvm::MachineFunction::getFunction(), getInstSizeInBytes(), getMemOperandWithOffset(), getMemOpInfo(), llvm::outliner::Candidate::getMF(), llvm::MachineInstr::getOpcode(), llvm::MachineOperand::getReg(), getRegisterInfo(), HasCalls, llvm::Function::hasFnAttribute(), llvm::outliner::Candidate::initLRU(), llvm::MachineInstr::isCall(), llvm::MachineOperand::isReg(), llvm::outliner::Candidate::LRU, MachineOutlinerDefault, MachineOutlinerNoLRSave, MachineOutlinerRegSave, MachineOutlinerTailCall, MachineOutlinerThunk, llvm::MachineInstr::mayLoadOrStore(), MI, llvm::MachineInstr::modifiesRegister(), llvm::MachineInstr::readsRegister(), llvm::remove_if(), llvm::outliner::Candidate::setCallInfo(), TRI, UnsafeRegsDead, and llvm::outliner::Candidate::UsedInSequence.

Referenced by isSubregFoldable().

getOutliningType()

outliner::InstrType AArch64InstrInfo::getOutliningType ( MachineBasicBlock::iterator &  MIT, unsigned  Flags  ) const

override

Definition at line 5256 of file AArch64InstrInfo.cpp.

References llvm::AArch64ISD::ADRP, assert(), llvm::ARCISD::BL, Callee, llvm::SmallPtrSetImpl< PtrType >::count(), llvm::dyn_cast(), llvm::MachineFunction::getFrameInfo(), llvm::MachineFunction::getInfo(), llvm::AArch64FunctionInfo::getLOHRelated(), llvm::MachineModuleInfo::getMachineFunction(), getMemOpBaseRegImmOfsOffsetOperand(), getMemOperandWithOffsetWidth(), getMemOpInfo(), llvm::MachineFunction::getMMI(), llvm::Value::getName(), llvm::MachineFrameInfo::getNumObjects(), llvm::MachineInstr::getOpcode(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), getRegisterInfo(), llvm::MachineFrameInfo::getStackSize(), llvm::outliner::Illegal, llvm::outliner::Invisible, llvm::MachineInstr::isCall(), llvm::MachineFrameInfo::isCalleeSavedInfoValid(), llvm::MachineInstr::isDebugInstr(), llvm::MachineOperand::isImm(), llvm::MachineInstr::isIndirectDebugValue(), llvm::MachineInstr::isKill(), llvm::MachineInstr::isPosition(), llvm::MachineOperand::isReg(), llvm::MachineInstr::isTerminator(), llvm::LegalizeActions::Legal, llvm::outliner::LegalTerminator, MI, llvm::MachineInstr::modifiesRegister(), llvm::MachineInstr::operands(), llvm::MachineInstr::readsRegister(), llvm::MachineOperand::setImm(), and llvm::MachineBasicBlock::succ_empty().

Referenced by isSubregFoldable().

getRegisterInfo()

const AArch64RegisterInfo& llvm::AArch64InstrInfo::getRegisterInfo ( ) const

inline

getRegisterInfo - TargetInstrInfo is a superset of MRegister info.

As such, whenever a client has an instance of instruction info, it should always be able to get register info as well (through this method).

Definition at line 47 of file AArch64InstrInfo.h.

References areMemAccessesTriviallyDisjoint(), llvm::ISD::FrameIndex, getInstSizeInBytes(), isAsCheapAsAMove(), isCoalescableExtInstr(), isFPRCopy(), isGPRCopy(), isGPRZero(), isLdStPairSuppressed(), isLoadFromStackSlot(), isStoreToStackSlot(), isStridedAccess(), isUnscaledLdSt(), and MI.

Referenced by areMemAccessesTriviallyDisjoint(), canInstrSubstituteCmpInstr(), copyGPRRegTuple(), copyPhysReg(), copyPhysRegTuple(), getOutliningCandidateInfo(), getOutliningType(), llvm::AArch64Subtarget::getRegisterInfo(), isCandidateToMergeOrPair(), isMBBSafeToOutlineFrom(), loadRegFromStackSlot(), optimizeCondBranch(), and storeRegToStackSlot().

getSerializableBitmaskMachineOperandTargetFlags()

ArrayRef< std::pair< unsigned, const char * > > AArch64InstrInfo::getSerializableBitmaskMachineOperandTargetFlags ( ) const

override

Definition at line 4789 of file AArch64InstrInfo.cpp.

References llvm::makeArrayRef(), llvm::AArch64II::MO_COFFSTUB, llvm::AArch64II::MO_DLLIMPORT, llvm::AArch64II::MO_GOT, llvm::AArch64II::MO_NC, llvm::AArch64II::MO_S, and llvm::AArch64II::MO_TLS.

Referenced by isSubregFoldable().

getSerializableDirectMachineOperandTargetFlags()

ArrayRef< std::pair< unsigned, const char * > > AArch64InstrInfo::getSerializableDirectMachineOperandTargetFlags ( ) const

override

Definition at line 4777 of file AArch64InstrInfo.cpp.

References llvm::makeArrayRef(), llvm::AArch64II::MO_G0, llvm::AArch64II::MO_G1, llvm::AArch64II::MO_G2, llvm::AArch64II::MO_G3, llvm::AArch64II::MO_HI12, llvm::AArch64II::MO_PAGE, and llvm::AArch64II::MO_PAGEOFF.

Referenced by isSubregFoldable().

getSerializableMachineMemOperandTargetFlags()

ArrayRef< std::pair< MachineMemOperand::Flags, const char * > > AArch64InstrInfo::getSerializableMachineMemOperandTargetFlags ( ) const

override

Definition at line 4801 of file AArch64InstrInfo.cpp.

References llvm::makeArrayRef(), llvm::MOStridedAccess, and llvm::MOSuppressPair.

Referenced by isSubregFoldable().

insertBranch()

unsigned AArch64InstrInfo::insertBranch ( MachineBasicBlock &  MBB, MachineBasicBlock *  TBB, MachineBasicBlock *  FBB, ArrayRef< MachineOperand >  Cond, const DebugLoc &  DL, int *  BytesAdded = nullptr  ) const

override

Definition at line 387 of file AArch64InstrInfo.cpp.

References llvm::MachineInstrBuilder::addMBB(), assert(), B, llvm::BuildMI(), and llvm::ArrayRef< T >::empty().

Referenced by isSubregFoldable().

insertOutlinedCall()

MachineBasicBlock::iterator AArch64InstrInfo::insertOutlinedCall ( Module &  M, MachineBasicBlock &  MBB, MachineBasicBlock::iterator &  It, MachineFunction &  MF, const outliner::Candidate &  C  ) const

override

Definition at line 5504 of file AArch64InstrInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::ARCISD::BL, llvm::BuildMI(), llvm::outliner::Candidate::CallConstructionID, llvm::RegState::Define, llvm::MachineFunction::getName(), llvm::Module::getNamedValue(), llvm::MachineBasicBlock::insert(), MachineOutlinerNoLRSave, MachineOutlinerRegSave, MachineOutlinerTailCall, MachineOutlinerThunk, and Reg.

Referenced by isSubregFoldable().

insertSelect()

void AArch64InstrInfo::insertSelect ( MachineBasicBlock &  MBB, MachineBasicBlock::iterator  MI, const DebugLoc &  DL, unsigned  DstReg, ArrayRef< MachineOperand >  Cond, unsigned  TrueReg, unsigned  FalseReg  ) const

override

Definition at line 537 of file AArch64InstrInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), canFoldIntoCSel(), llvm::MachineRegisterInfo::clearKillFlags(), llvm::MachineRegisterInfo::constrainRegClass(), llvm::AArch64_AM::encodeLogicalImmediate(), llvm::AArch64CC::EQ, llvm::AArch64CC::getInvertedCondCode(), llvm::MachineBasicBlock::getParent(), getReg(), llvm::MachineFunction::getRegInfo(), llvm_unreachable, MRI, llvm::AArch64CC::NE, and llvm::ArrayRef< T >::size().

Referenced by isSubregFoldable().

isAsCheapAsAMove()

bool AArch64InstrInfo::isAsCheapAsAMove ( const MachineInstr &  MI ) const

override

Definition at line 683 of file AArch64InstrInfo.cpp.

References canBeExpandedToORR(), llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::AArch64Subtarget::hasCustomCheapAsMoveHandling(), llvm::AArch64Subtarget::hasExynosCheapAsMoveHandling(), llvm::AArch64Subtarget::hasZeroCycleZeroingFP(), llvm::AArch64Subtarget::hasZeroCycleZeroingGP(), llvm::MachineInstr::isAsCheapAsAMove(), and llvm_unreachable.

Referenced by getRegisterInfo().

isAssociativeAndCommutative()

bool AArch64InstrInfo::isAssociativeAndCommutative ( const MachineInstr &  Inst ) const

override

Return true when Inst is associative and commutative so that it can be reassociated.

Definition at line 3555 of file AArch64InstrInfo.cpp.

References llvm::MachineInstr::getOpcode(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), llvm::MachineFunction::getTarget(), llvm::TargetMachine::Options, and llvm::TargetOptions::UnsafeFPMath.

Referenced by isSubregFoldable().

isBranchOffsetInRange()

bool AArch64InstrInfo::isBranchOffsetInRange ( unsigned  BranchOpc, int64_t  BrOffset  ) const

override

Returns

true if a branch from an instruction with opcode BranchOpc bytes is capable of jumping to a position BrOffset bytes away.

Definition at line 177 of file AArch64InstrInfo.cpp.

References assert(), llvm::tgtok::Bits, getBranchDisplacementBits(), and llvm::isIntN().

Referenced by isSubregFoldable().

isCandidateToMergeOrPair()

bool AArch64InstrInfo::isCandidateToMergeOrPair

(

MachineInstr &

MI

)

const

Return true if this is a load/store that can be potentially paired/merged.

Definition at line 1840 of file AArch64InstrInfo.cpp.

References assert(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), getRegisterInfo(), llvm::MachineInstr::hasOrderedMemoryRef(), llvm::MachineOperand::isFI(), llvm::MachineOperand::isImm(), isLdStPairSuppressed(), llvm::MachineOperand::isReg(), llvm::MachineInstr::modifiesRegister(), and TRI.

Referenced by isUnscaledLdSt(), and shouldClusterMemOps().

isCoalescableExtInstr()

bool AArch64InstrInfo::isCoalescableExtInstr ( const MachineInstr &  MI, unsigned &  SrcReg, unsigned &  DstReg, unsigned &  SubIdx  ) const

override

Definition at line 910 of file AArch64InstrInfo.cpp.

References llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), and llvm::MachineOperand::getReg().

Referenced by getRegisterInfo().

isFalkorShiftExtFast()

bool AArch64InstrInfo::isFalkorShiftExtFast ( const MachineInstr &  MI )

static

Returns true if the instruction has a shift by immediate that can be executed in one cycle less.

Definition at line 762 of file AArch64InstrInfo.cpp.

References llvm::AArch64_AM::ASR, llvm::AArch64_AM::getArithExtendType(), llvm::AArch64_AM::getArithShiftValue(), llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::AArch64_AM::getShiftType(), llvm::AArch64_AM::getShiftValue(), llvm::AArch64_AM::LSL, llvm::AArch64_AM::UXTB, llvm::AArch64_AM::UXTH, llvm::AArch64_AM::UXTW, and llvm::AArch64_AM::UXTX.

Referenced by isSubregFoldable().

isFPRCopy()

bool AArch64InstrInfo::isFPRCopy ( const MachineInstr &  MI )

static

Does this instruction rename an FPR without modifying bits?

Definition at line 1606 of file AArch64InstrInfo.cpp.

References assert(), contains(), llvm::MachineInstr::getDesc(), llvm::MCInstrDesc::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), and llvm::MachineOperand::isReg().

Referenced by getRegisterInfo().

isFunctionSafeToOutlineFrom()

bool AArch64InstrInfo::isFunctionSafeToOutlineFrom ( MachineFunction &  MF, bool  OutlineFromLinkOnceODRs  ) const

override

Definition at line 5163 of file AArch64InstrInfo.cpp.

References F(), llvm::MachineFunction::getFunction(), llvm::MachineFunction::getInfo(), llvm::Optional< T >::getValueOr(), llvm::GlobalValue::hasLinkOnceODRLinkage(), llvm::AArch64FunctionInfo::hasRedZone(), and llvm::GlobalObject::hasSection().

Referenced by isSubregFoldable().

isGPRCopy()

bool AArch64InstrInfo::isGPRCopy ( const MachineInstr &  MI )

static

Does this instruction rename a GPR without modifying bits?

Definition at line 1576 of file AArch64InstrInfo.cpp.

References assert(), contains(), llvm::MachineInstr::getDesc(), llvm::MachineOperand::getImm(), llvm::MCInstrDesc::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), and llvm::MachineOperand::getReg().

Referenced by getRegisterInfo().

isGPRZero()

bool AArch64InstrInfo::isGPRZero ( const MachineInstr &  MI )

static

Does this instruction set its full destination register to zero?

Definition at line 1552 of file AArch64InstrInfo.cpp.

References assert(), llvm::MachineInstr::getDesc(), llvm::MachineOperand::getImm(), llvm::MCInstrDesc::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), and llvm::MachineOperand::isImm().

Referenced by getRegisterInfo().

isLdStPairSuppressed()

bool AArch64InstrInfo::isLdStPairSuppressed ( const MachineInstr &  MI )

static

Return true if pairing the given load or store is hinted to be unprofitable.

Check all MachineMemOperands for a hint to suppress pairing.

Definition at line 1673 of file AArch64InstrInfo.cpp.

References llvm::any_of(), llvm::MachineInstr::memoperands(), and llvm::MOSuppressPair.

Referenced by areCandidatesToMergeOrPair(), getRegisterInfo(), and isCandidateToMergeOrPair().

isLoadFromStackSlot()

unsigned AArch64InstrInfo::isLoadFromStackSlot ( const MachineInstr &  MI, int &  FrameIndex  ) const

override

Definition at line 1627 of file AArch64InstrInfo.cpp.

References llvm::MachineOperand::getImm(), llvm::MachineOperand::getIndex(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::getSubReg(), llvm::MachineOperand::isFI(), and llvm::MachineOperand::isImm().

Referenced by getRegisterInfo().

isMBBSafeToOutlineFrom()

bool AArch64InstrInfo::isMBBSafeToOutlineFrom ( MachineBasicBlock &  MBB, unsigned &  Flags  ) const

override

Definition at line 5189 of file AArch64InstrInfo.cpp.

References llvm::any_of(), assert(), llvm::for_each(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), getRegisterInfo(), llvm::TargetSubtargetInfo::getRegisterInfo(), llvm::MachineFunction::getSubtarget(), HasCalls, llvm::MachineInstr::isCall(), llvm::AArch64RegisterInfo::isReservedReg(), LRUnavailableSomewhere, MI, llvm::MachineBasicBlock::rbegin(), Reg, llvm::MachineBasicBlock::rend(), llvm::MachineRegisterInfo::tracksLiveness(), and UnsafeRegsDead.

Referenced by isSubregFoldable().

isPairableLdStInst()

bool AArch64InstrInfo::isPairableLdStInst ( const MachineInstr &  MI )

static

Return true if pairing the given load or store may be paired with another.

Definition at line 1718 of file AArch64InstrInfo.cpp.

References llvm::MachineInstr::getOpcode().

Referenced by isUnscaledLdSt(), and shouldClusterMemOps().

isSchedulingBoundary()

bool AArch64InstrInfo::isSchedulingBoundary ( const MachineInstr &  MI, const MachineBasicBlock *  MBB, const MachineFunction &  MF  ) const

override

Definition at line 962 of file AArch64InstrInfo.cpp.

References llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::TargetInstrInfo::isSchedulingBoundary(), and isSEHInstruction().

Referenced by isSubregFoldable().

isSEHInstruction()

bool AArch64InstrInfo::isSEHInstruction ( const MachineInstr &  MI )

static

Return true if the instructions is a SEH instruciton used for unwinding on Windows.

Definition at line 884 of file AArch64InstrInfo.cpp.

References llvm::MachineInstr::getOpcode().

Referenced by convertCalleeSaveRestoreToSPPrePostIncDec(), llvm::AArch64FrameLowering::emitEpilogue(), fixupCalleeSaveRestoreStackOffset(), isSchedulingBoundary(), and isSubregFoldable().

isStoreToStackSlot()

unsigned AArch64InstrInfo::isStoreToStackSlot ( const MachineInstr &  MI, int &  FrameIndex  ) const

override

Definition at line 1650 of file AArch64InstrInfo.cpp.

References llvm::MachineOperand::getImm(), llvm::MachineOperand::getIndex(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::getSubReg(), llvm::MachineOperand::isFI(), and llvm::MachineOperand::isImm().

Referenced by getRegisterInfo().

isStridedAccess()

bool AArch64InstrInfo::isStridedAccess ( const MachineInstr &  MI )

static

Return true if the given load or store is a strided memory access.

Check all MachineMemOperands for a hint that the load/store is strided.

Definition at line 1687 of file AArch64InstrInfo.cpp.

References llvm::any_of(), llvm::MachineInstr::memoperands(), and llvm::MOStridedAccess.

Referenced by getRegisterInfo().

isSubregFoldable()

bool llvm::AArch64InstrInfo::isSubregFoldable ( ) const

inlineoverride

Definition at line 146 of file AArch64InstrInfo.h.

References analyzeBranch(), analyzeCompare(), buildOutlinedFrame(), C, canInsertSelect(), decomposeMachineOperandsTargetFlags(), expandPostRAPseudo(), foldMemoryOperandImpl(), llvm::TargetInstrInfo::foldMemoryOperandImpl(), genAlternativeCodeSequence(), getBranchDestBlock(), getMachineCombinerPatterns(), getNoop(), getOutliningCandidateInfo(), getOutliningType(), getSerializableBitmaskMachineOperandTargetFlags(), getSerializableDirectMachineOperandTargetFlags(), getSerializableMachineMemOperandTargetFlags(), insertBranch(), insertOutlinedCall(), insertSelect(), isAssociativeAndCommutative(), isBranchOffsetInRange(), isFalkorShiftExtFast(), isFunctionSafeToOutlineFrom(), isMBBSafeToOutlineFrom(), isSchedulingBoundary(), isSEHInstruction(), isThroughputPattern(), MRI, optimizeCompareInstr(), optimizeCondBranch(), removeBranch(), reverseBranchCondition(), shouldOutlineFromFunctionByDefault(), and useMachineCombiner().

isThroughputPattern()

bool AArch64InstrInfo::isThroughputPattern ( MachineCombinerPattern  Pattern ) const

override

Return true when a code sequence can improve throughput.

It should be called only for instructions in loops.

Parameters

Pattern

- combiner pattern

Definition at line 3903 of file AArch64InstrInfo.cpp.

References llvm::FMLAv1i32_indexed_OP1, llvm::FMLAv1i32_indexed_OP2, llvm::FMLAv1i64_indexed_OP1, llvm::FMLAv1i64_indexed_OP2, llvm::FMLAv2f32_OP1, llvm::FMLAv2f32_OP2, llvm::FMLAv2f64_OP1, llvm::FMLAv2f64_OP2, llvm::FMLAv2i32_indexed_OP1, llvm::FMLAv2i32_indexed_OP2, llvm::FMLAv2i64_indexed_OP1, llvm::FMLAv2i64_indexed_OP2, llvm::FMLAv4f32_OP1, llvm::FMLAv4f32_OP2, llvm::FMLAv4i32_indexed_OP1, llvm::FMLAv4i32_indexed_OP2, llvm::FMLSv1i32_indexed_OP2, llvm::FMLSv1i64_indexed_OP2, llvm::FMLSv2f32_OP2, llvm::FMLSv2f64_OP2, llvm::FMLSv2i32_indexed_OP2, llvm::FMLSv2i64_indexed_OP2, llvm::FMLSv4f32_OP2, llvm::FMLSv4i32_indexed_OP2, llvm::FMULADDD_OP1, llvm::FMULADDD_OP2, llvm::FMULADDS_OP1, llvm::FMULADDS_OP2, llvm::FMULSUBD_OP1, llvm::FMULSUBD_OP2, llvm::FMULSUBS_OP1, llvm::FMULSUBS_OP2, llvm::FNMULSUBD_OP1, and llvm::FNMULSUBS_OP1.

Referenced by isSubregFoldable().

isUnscaledLdSt() [1/2]

bool AArch64InstrInfo::isUnscaledLdSt ( unsigned  Opc )

static

Return true if this is an unscaled load/store.

Definition at line 1693 of file AArch64InstrInfo.cpp.

Referenced by areCandidatesToMergeOrPair(), getRegisterInfo(), isLdOffsetInRangeOfSt(), isUnscaledLdSt(), and shouldClusterMemOps().

isUnscaledLdSt() [2/2]

static bool llvm::AArch64InstrInfo::isUnscaledLdSt ( MachineInstr &  MI )

inlinestatic

Definition at line 83 of file AArch64InstrInfo.h.

References convertToFlagSettingOpc(), copyGPRRegTuple(), copyPhysReg(), copyPhysRegTuple(), getMemOpBaseRegImmOfsOffsetOperand(), getMemOperandWithOffset(), getMemOperandWithOffsetWidth(), getMemOpInfo(), llvm::MachineInstr::getOpcode(), I, isCandidateToMergeOrPair(), isPairableLdStInst(), isUnscaledLdSt(), loadRegFromStackSlot(), shouldClusterMemOps(), storeRegToStackSlot(), suppressLdStPair(), and TRI.

loadRegFromStackSlot()

void AArch64InstrInfo::loadRegFromStackSlot ( MachineBasicBlock &  MBB, MachineBasicBlock::iterator  MBBI, unsigned  DestReg, int  FrameIndex, const TargetRegisterClass *  RC, const TargetRegisterInfo *  TRI  ) const

override

Definition at line 2773 of file AArch64InstrInfo.cpp.

References llvm::MachineInstrBuilder::addFrameIndex(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMemOperand(), llvm::MachineInstrBuilder::addReg(), llvm::AMDGPU::HSAMD::Kernel::Arg::Key::Align, assert(), llvm::BuildMI(), llvm::MachineRegisterInfo::constrainRegClass(), llvm::getDefRegState(), llvm::MachinePointerInfo::getFixedStack(), llvm::MachineFunction::getFrameInfo(), llvm::MachineFunction::getMachineMemOperand(), llvm::MachineFrameInfo::getObjectAlignment(), llvm::MachineFrameInfo::getObjectSize(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), getRegisterInfo(), llvm::TargetRegisterInfo::getSpillSize(), llvm::TargetRegisterInfo::isVirtualRegister(), loadRegPairFromStackSlot(), MI, and llvm::MachineMemOperand::MOLoad.

Referenced by foldMemoryOperandImpl(), and isUnscaledLdSt().

optimizeCompareInstr()

bool AArch64InstrInfo::optimizeCompareInstr ( MachineInstr &  CmpInstr, unsigned  SrcReg, unsigned  SrcReg2, int  CmpMask, int  CmpValue, const MachineRegisterInfo *  MRI  ) const

override

optimizeCompareInstr - Convert the instruction supplying the argument to the comparison into one that sets the zero bit in the flags register.

Try to optimize a compare instruction.

A compare instruction is an instruction which produces AArch64::NZCV. It can be truly compare instruction when there are no uses of its destination register.

The following steps are tried in order:

1. Convert CmpInstr into an unconditional version.
2. Remove CmpInstr if above there is an instruction producing a needed condition code or an instruction which can be converted into such an instruction. Only comparison with zero is supported.

Definition at line 1180 of file AArch64InstrInfo.cpp.

References assert(), convertToNonFlagSettingOpc(), llvm::MachineInstr::definesRegister(), llvm::MachineInstr::eraseFromParent(), llvm::MachineInstr::findRegisterDefOperandIdx(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), llvm::MachineInstr::RemoveOperand(), llvm::MachineInstr::setDesc(), UpdateOperandRegClass(), and llvm::MachineRegisterInfo::use_nodbg_empty().

Referenced by isSubregFoldable().

optimizeCondBranch()

bool AArch64InstrInfo::optimizeCondBranch ( MachineInstr &  MI ) const

override

Replace csincr-branch sequence by simple conditional branch.

Examples:

1. csinc  w9, wzr, wzr, <condition code>
   tbnz   w9, #0, 0x44

   to

   b.<inverted condition code>

2. csinc w9, wzr, wzr, <condition code>
   tbz   w9, #0, 0x44

   to

   b.<condition code>

Replace compare and branch sequence by TBZ/TBNZ instruction when the compare's constant operand is power of 2.

Examples:

and  w8, w8, #0x400
cbnz w8, L1

to

tbnz w8, #10, L1

Parameters

MI	Conditional Branch

Returns

True when the simple conditional branch is generated

Definition at line 4633 of file AArch64InstrInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMBB(), llvm::MachineInstrBuilder::addReg(), AK_Write, areCFlagsAccessedBetweenInstrs(), assert(), llvm::BuildMI(), llvm::AArch64_AM::decodeLogicalImmediate(), llvm::MachineRegisterInfo::def_empty(), DefMI, llvm::MachineInstr::eraseFromParent(), llvm::MachineInstr::findRegisterDefOperandIdx(), llvm::MachineInstr::getDebugLoc(), llvm::MachineOperand::getImm(), llvm::AArch64CC::getInvertedCondCode(), llvm::MachineOperand::getMBB(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), getRegisterInfo(), llvm::MachineRegisterInfo::getVRegDef(), llvm::MachineRegisterInfo::hasOneDef(), llvm::MachineRegisterInfo::hasOneNonDBGUse(), llvm::MachineInstr::isCopy(), llvm::isPowerOf2_64(), llvm::TargetRegisterInfo::isVirtualRegister(), llvm_unreachable, llvm::Log2_64(), llvm::BitmaskEnumDetail::Mask(), llvm::MachineOperand::setIsKill(), and llvm::MachineOperand::setSubReg().

Referenced by isSubregFoldable().

removeBranch()

unsigned AArch64InstrInfo::removeBranch ( MachineBasicBlock &  MBB, int *  BytesRemoved = nullptr  ) const

override

Definition at line 335 of file AArch64InstrInfo.cpp.

References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMBB(), llvm::MachineBasicBlock::begin(), llvm::BuildMI(), llvm::MachineBasicBlock::end(), llvm::MachineBasicBlock::getLastNonDebugInstr(), I, llvm::isCondBranchOpcode(), llvm::isUncondBranchOpcode(), and llvm::ArrayRef< T >::size().

Referenced by isSubregFoldable().

reverseBranchCondition()

bool AArch64InstrInfo::reverseBranchCondition ( SmallVectorImpl< MachineOperand > &  Cond ) const

override

Definition at line 294 of file AArch64InstrInfo.cpp.

References llvm::AArch64CC::getInvertedCondCode(), and llvm_unreachable.

Referenced by isSubregFoldable().

shouldClusterMemOps()

bool AArch64InstrInfo::shouldClusterMemOps ( MachineOperand &  BaseOp1, MachineOperand &  BaseOp2, unsigned  NumLoads  ) const

override

Detect opportunities for ldp/stp formation.

Only called for LdSt for which getMemOperandWithOffset returns true.

Definition at line 2184 of file AArch64InstrInfo.cpp.

References assert(), canPairLdStOpc(), llvm::MachineFunction::getFrameInfo(), llvm::MachineOperand::getImm(), llvm::MachineOperand::getIndex(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getParent(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), llvm::MachineOperand::getType(), isCandidateToMergeOrPair(), llvm::MachineOperand::isFI(), llvm::MachineOperand::isIdenticalTo(), isPairableLdStInst(), llvm::MachineOperand::isReg(), isUnscaledLdSt(), scaleOffset(), and shouldClusterFI().

Referenced by isUnscaledLdSt().

shouldOutlineFromFunctionByDefault()

bool AArch64InstrInfo::shouldOutlineFromFunctionByDefault ( MachineFunction &  MF ) const

override

Definition at line 5576 of file AArch64InstrInfo.cpp.

References llvm::MachineFunction::getFunction(), and llvm::Function::optForMinSize().

Referenced by isSubregFoldable().

storeRegToStackSlot()

void AArch64InstrInfo::storeRegToStackSlot ( MachineBasicBlock &  MBB, MachineBasicBlock::iterator  MBBI, unsigned  SrcReg, bool  isKill, int  FrameIndex, const TargetRegisterClass *  RC, const TargetRegisterInfo *  TRI  ) const

override

Definition at line 2642 of file AArch64InstrInfo.cpp.

References llvm::MachineInstrBuilder::addFrameIndex(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMemOperand(), llvm::MachineInstrBuilder::addReg(), llvm::AMDGPU::HSAMD::Kernel::Arg::Key::Align, assert(), llvm::BuildMI(), llvm::MachineRegisterInfo::constrainRegClass(), llvm::MachinePointerInfo::getFixedStack(), llvm::MachineFunction::getFrameInfo(), llvm::getKillRegState(), llvm::MachineFunction::getMachineMemOperand(), llvm::MachineFrameInfo::getObjectAlignment(), llvm::MachineFrameInfo::getObjectSize(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), getRegisterInfo(), llvm::TargetRegisterInfo::getSpillSize(), llvm::TargetRegisterInfo::isVirtualRegister(), MI, llvm::MachineMemOperand::MOStore, and storeRegPairToStackSlot().

Referenced by foldMemoryOperandImpl(), and isUnscaledLdSt().

suppressLdStPair()

void AArch64InstrInfo::suppressLdStPair ( MachineInstr &  MI )

static

Hint that pairing the given load or store is unprofitable.

Set a flag on the first MachineMemOperand to suppress pairing.

Definition at line 1680 of file AArch64InstrInfo.cpp.

References llvm::MachineInstr::memoperands_begin(), llvm::MachineInstr::memoperands_empty(), and llvm::MOSuppressPair.

Referenced by isUnscaledLdSt().

useMachineCombiner()

bool AArch64InstrInfo::useMachineCombiner ( ) const

override

AArch64 supports MachineCombiner.

Definition at line 3421 of file AArch64InstrInfo.cpp.

Referenced by isSubregFoldable().

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The documentation for this class was generated from the following files:

• lib/Target/AArch64/AArch64InstrInfo.h
• lib/Target/AArch64/AArch64InstrInfo.cpp