AArch64InstrInfo.cpp File Reference

#include "AArch64InstrInfo.h"
#include "AArch64MachineFunctionInfo.h"
#include "AArch64Subtarget.h"
#include "MCTargetDesc/AArch64AddressingModes.h"
#include "Utils/AArch64BaseInfo.h"
#include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineMemOperand.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/MachineModuleInfo.h"
#include "llvm/CodeGen/StackMaps.h"
#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/IR/DebugLoc.h"
#include "llvm/IR/GlobalValue.h"
#include "llvm/MC/MCInst.h"
#include "llvm/MC/MCInstrDesc.h"
#include "llvm/Support/Casting.h"
#include "llvm/Support/CodeGen.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Compiler.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetOptions.h"
#include <cassert>
#include <cstdint>
#include <iterator>
#include <utility>
#include "AArch64GenInstrInfo.inc"

Include dependency graph for AArch64InstrInfo.cpp:

Go to the source code of this file.

Macros
#define	GET_INSTRINFO_CTOR_DTOR
#define	GET_INSTRINFO_HELPERS

Enumerations
enum	AccessKind { AK_Write = 0x01, AK_Read = 0x10, AK_All = 0x11 }
enum	FMAInstKind { FMAInstKind::Default, FMAInstKind::Indexed, FMAInstKind::Accumulator }
enum	MachineOutlinerClass {   MachineOutlinerDefault, MachineOutlinerTailCall, MachineOutlinerNoLRSave, MachineOutlinerThunk,   MachineOutlinerRegSave, MachineOutlinerDefault, MachineOutlinerTailCall }
	Constants defining how certain sequences should be outlined. More...
enum	MachineOutlinerMBBFlags { LRUnavailableSomewhere = 0x2, HasCalls = 0x4, UnsafeRegsDead = 0x8 }

Functions
static void	parseCondBranch (MachineInstr *LastInst, MachineBasicBlock *&Target, SmallVectorImpl< MachineOperand > &Cond)
static unsigned	getBranchDisplacementBits (unsigned Opc)
static unsigned	removeCopies (const MachineRegisterInfo &MRI, unsigned VReg)
static unsigned	canFoldIntoCSel (const MachineRegisterInfo &MRI, unsigned VReg, unsigned *NewVReg=nullptr)
static bool	canBeExpandedToORR (const MachineInstr &MI, unsigned BitSize)
	Returns true if a MOVi32imm or MOVi64imm can be expanded to an ORRxx. More...
static bool	UpdateOperandRegClass (MachineInstr &Instr)
static unsigned	convertToNonFlagSettingOpc (const MachineInstr &MI)
	Return the opcode that does not set flags when possible - otherwise return the original opcode. More...
static bool	areCFlagsAccessedBetweenInstrs (MachineBasicBlock::iterator From, MachineBasicBlock::iterator To, const TargetRegisterInfo *TRI, const AccessKind AccessToCheck=AK_All)
	True when condition flags are accessed (either by writing or reading) on the instruction trace starting at From and ending at To. More...
static unsigned	sForm (MachineInstr &Instr)
	Get opcode of S version of Instr. More...
static bool	areCFlagsAliveInSuccessors (MachineBasicBlock *MBB)
	Check if AArch64::NZCV should be alive in successors of MBB. More...
static AArch64CC::CondCode	findCondCodeUsedByInstr (const MachineInstr &Instr)
	Find a condition code used by the instruction. More...
static UsedNZCV	getUsedNZCV (AArch64CC::CondCode CC)
static bool	isADDSRegImm (unsigned Opcode)
static bool	isSUBSRegImm (unsigned Opcode)
static bool	canInstrSubstituteCmpInstr (MachineInstr *MI, MachineInstr *CmpInstr, const TargetRegisterInfo *TRI)
	Check if CmpInstr can be substituted by MI. More...
static unsigned	getOffsetStride (unsigned Opc)
static bool	scaleOffset (unsigned Opc, int64_t &Offset)
static bool	unscaleOffset (unsigned Opc, int64_t &Offset)
static bool	canPairLdStOpc (unsigned FirstOpc, unsigned SecondOpc)
static bool	shouldClusterFI (const MachineFrameInfo &MFI, int FI1, int64_t Offset1, unsigned Opcode1, int FI2, int64_t Offset2, unsigned Opcode2)
static const MachineInstrBuilder &	AddSubReg (const MachineInstrBuilder &MIB, unsigned Reg, unsigned SubIdx, unsigned State, const TargetRegisterInfo *TRI)
static bool	forwardCopyWillClobberTuple (unsigned DestReg, unsigned SrcReg, unsigned NumRegs)
static void	storeRegPairToStackSlot (const TargetRegisterInfo &TRI, MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore, const MCInstrDesc &MCID, unsigned SrcReg, bool IsKill, unsigned SubIdx0, unsigned SubIdx1, int FI, MachineMemOperand *MMO)
static void	loadRegPairFromStackSlot (const TargetRegisterInfo &TRI, MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore, const MCInstrDesc &MCID, unsigned DestReg, unsigned SubIdx0, unsigned SubIdx1, int FI, MachineMemOperand *MMO)
static bool	isCombineInstrSettingFlag (unsigned Opc)
static bool	isCombineInstrCandidate32 (unsigned Opc)
static bool	isCombineInstrCandidate64 (unsigned Opc)
static bool	isCombineInstrCandidateFP (const MachineInstr &Inst)
static bool	isCombineInstrCandidate (unsigned Opc)
static bool	canCombine (MachineBasicBlock &MBB, MachineOperand &MO, unsigned CombineOpc, unsigned ZeroReg=0, bool CheckZeroReg=false)
static bool	canCombineWithMUL (MachineBasicBlock &MBB, MachineOperand &MO, unsigned MulOpc, unsigned ZeroReg)
static bool	canCombineWithFMUL (MachineBasicBlock &MBB, MachineOperand &MO, unsigned MulOpc)
static bool	getMaddPatterns (MachineInstr &Root, SmallVectorImpl< MachineCombinerPattern > &Patterns)
	Find instructions that can be turned into madd. More...
static bool	getFMAPatterns (MachineInstr &Root, SmallVectorImpl< MachineCombinerPattern > &Patterns)
	Floating-Point Support. More...
static MachineInstr *	genFusedMultiply (MachineFunction &MF, MachineRegisterInfo &MRI, const TargetInstrInfo *TII, MachineInstr &Root, SmallVectorImpl< MachineInstr *> &InsInstrs, unsigned IdxMulOpd, unsigned MaddOpc, const TargetRegisterClass *RC, FMAInstKind kind=FMAInstKind::Default, const unsigned *ReplacedAddend=nullptr)
	genFusedMultiply - Generate fused multiply instructions. More...
static MachineInstr *	genMaddR (MachineFunction &MF, MachineRegisterInfo &MRI, const TargetInstrInfo *TII, MachineInstr &Root, SmallVectorImpl< MachineInstr *> &InsInstrs, unsigned IdxMulOpd, unsigned MaddOpc, unsigned VR, const TargetRegisterClass *RC)
	genMaddR - Generate madd instruction and combine mul and add using an extra virtual register Example - an ADD intermediate needs to be stored in a register: MUL I=A,B,0 ADD R,I,Imm ==> ORR V, ZR, Imm ==> MADD R,A,B,V More...

Variables
static cl::opt< unsigned >	TBZDisplacementBits ("aarch64-tbz-offset-bits", cl::Hidden, cl::init(14), cl::desc("Restrict range of TB[N]Z instructions (DEBUG)"))
static cl::opt< unsigned >	CBZDisplacementBits ("aarch64-cbz-offset-bits", cl::Hidden, cl::init(19), cl::desc("Restrict range of CB[N]Z instructions (DEBUG)"))
static cl::opt< unsigned >	BCCDisplacementBits ("aarch64-bcc-offset-bits", cl::Hidden, cl::init(19), cl::desc("Restrict range of Bcc instructions (DEBUG)"))

Macro Definition Documentation

GET_INSTRINFO_CTOR_DTOR

#define GET_INSTRINFO_CTOR_DTOR

Definition at line 53 of file AArch64InstrInfo.cpp.

GET_INSTRINFO_HELPERS

#define GET_INSTRINFO_HELPERS

Definition at line 5581 of file AArch64InstrInfo.cpp.

Enumeration Type Documentation

AccessKind

enum AccessKind

Enumerator
AK_Write
AK_Read
AK_All

Definition at line 1132 of file AArch64InstrInfo.cpp.

FMAInstKind

enum FMAInstKind

strong

Enumerator
Default
Indexed
Accumulator

Definition at line 3964 of file AArch64InstrInfo.cpp.

MachineOutlinerClass

enum MachineOutlinerClass

Constants defining how certain sequences should be outlined.

This encompasses how an outlined function should be called, and what kind of frame should be emitted for that outlined function.

MachineOutlinerDefault implies that the function should be called with a save and restore of LR to the stack.

That is,

I1 Save LR OUTLINED_FUNCTION: I2 –> BL OUTLINED_FUNCTION I1 I3 Restore LR I2 I3 RET

• Call construction overhead: 3 (save + BL + restore)
• Frame construction overhead: 1 (ret)
• Requires stack fixups? Yes

MachineOutlinerTailCall implies that the function is being created from a sequence of instructions ending in a return.

That is,

I1 OUTLINED_FUNCTION: I2 –> B OUTLINED_FUNCTION I1 RET I2 RET

• Call construction overhead: 1 (B)
• Frame construction overhead: 0 (Return included in sequence)
• Requires stack fixups? No

MachineOutlinerNoLRSave implies that the function should be called using a BL instruction, but doesn't require LR to be saved and restored. This happens when LR is known to be dead.

That is,

I1 OUTLINED_FUNCTION: I2 –> BL OUTLINED_FUNCTION I1 I3 I2 I3 RET

• Call construction overhead: 1 (BL)
• Frame construction overhead: 1 (RET)
• Requires stack fixups? No

MachineOutlinerThunk implies that the function is being created from a sequence of instructions ending in a call. The outlined function is called with a BL instruction, and the outlined function tail-calls the original call destination.

That is,

I1 OUTLINED_FUNCTION: I2 –> BL OUTLINED_FUNCTION I1 BL f I2 B f

• Call construction overhead: 1 (BL)
• Frame construction overhead: 0
• Requires stack fixups? No

MachineOutlinerRegSave implies that the function should be called with a save and restore of LR to an available register. This allows us to avoid stack fixups. Note that this outlining variant is compatible with the NoLRSave case.

That is,

I1 Save LR OUTLINED_FUNCTION: I2 –> BL OUTLINED_FUNCTION I1 I3 Restore LR I2 I3 RET

• Call construction overhead: 3 (save + BL + restore)
• Frame construction overhead: 1 (ret)
• Requires stack fixups? No

Enumerator
MachineOutlinerDefault
MachineOutlinerTailCall	Emit a save, restore, call, and return.
MachineOutlinerNoLRSave	Only emit a branch.
MachineOutlinerThunk	Emit a call and return.
MachineOutlinerRegSave	Emit a call and tail-call. Same as default, but save to a register.
MachineOutlinerDefault
MachineOutlinerTailCall

Definition at line 4888 of file AArch64InstrInfo.cpp.

MachineOutlinerMBBFlags

enum MachineOutlinerMBBFlags

Enumerator
LRUnavailableSomewhere
HasCalls
UnsafeRegsDead

Definition at line 4896 of file AArch64InstrInfo.cpp.

Function Documentation

AddSubReg()

static const MachineInstrBuilder& AddSubReg ( const MachineInstrBuilder &  MIB, unsigned  Reg, unsigned  SubIdx, unsigned  State, const TargetRegisterInfo *  TRI  )

static

Definition at line 2249 of file AArch64InstrInfo.cpp.

References llvm::MachineInstrBuilder::addReg(), llvm::MCRegisterInfo::getSubReg(), and llvm::TargetRegisterInfo::isPhysicalRegister().

Referenced by llvm::AArch64InstrInfo::copyGPRRegTuple().

areCFlagsAccessedBetweenInstrs()

static bool areCFlagsAccessedBetweenInstrs ( MachineBasicBlock::iterator  From, MachineBasicBlock::iterator  To, const TargetRegisterInfo *  TRI, const AccessKind  AccessToCheck = AK_All  )

static

True when condition flags are accessed (either by writing or reading) on the instruction trace starting at From and ending at To.

Note: If From and To are from different blocks it's assumed CC are accessed on the path.

Definition at line 1139 of file AArch64InstrInfo.cpp.

References AK_Read, AK_Write, assert(), llvm::find_if(), From, llvm::MachineInstrBundleIterator< Ty, IsReverse >::getReverse(), MI, llvm::MachineInstr::modifiesRegister(), and llvm::MachineInstr::readsRegister().

Referenced by canInstrSubstituteCmpInstr(), and llvm::AArch64InstrInfo::optimizeCondBranch().

areCFlagsAliveInSuccessors()

static bool areCFlagsAliveInSuccessors ( MachineBasicBlock *  MBB )

static

Check if AArch64::NZCV should be alive in successors of MBB.

Definition at line 1272 of file AArch64InstrInfo.cpp.

References C, N, llvm::operator|=(), llvm::MachineBasicBlock::successors(), and llvm::Z.

Referenced by canInstrSubstituteCmpInstr().

canBeExpandedToORR()

static bool canBeExpandedToORR ( const MachineInstr &  MI, unsigned  BitSize  )

static

Returns true if a MOVi32imm or MOVi64imm can be expanded to an ORRxx.

Definition at line 674 of file AArch64InstrInfo.cpp.

References llvm::MachineOperand::getImm(), llvm::MachineInstr::getOperand(), and llvm::AArch64_AM::processLogicalImmediate().

Referenced by llvm::AArch64InstrInfo::isAsCheapAsAMove().

canCombine()

static bool canCombine ( MachineBasicBlock &  MBB, MachineOperand &  MO, unsigned  CombineOpc, unsigned  ZeroReg = 0, bool  CheckZeroReg = false  )

static

Definition at line 3510 of file AArch64InstrInfo.cpp.

References assert(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), llvm::MachineRegisterInfo::getUniqueVRegDef(), llvm::MachineRegisterInfo::hasOneNonDBGUse(), llvm::MachineOperand::isReg(), llvm::TargetRegisterInfo::isVirtualRegister(), and MI.

Referenced by canCombineWithFMUL(), and canCombineWithMUL().

canCombineWithFMUL()

static bool canCombineWithFMUL ( MachineBasicBlock &  MBB, MachineOperand &  MO, unsigned  MulOpc  )

static

Definition at line 3546 of file AArch64InstrInfo.cpp.

References canCombine().

Referenced by getFMAPatterns().

canCombineWithMUL()

static bool canCombineWithMUL ( MachineBasicBlock &  MBB, MachineOperand &  MO, unsigned  MulOpc, unsigned  ZeroReg  )

static

Definition at line 3539 of file AArch64InstrInfo.cpp.

References canCombine().

Referenced by getMaddPatterns().

canFoldIntoCSel()

static unsigned canFoldIntoCSel ( const MachineRegisterInfo &  MRI, unsigned  VReg, unsigned *  NewVReg = nullptr  )

static

Definition at line 429 of file AArch64InstrInfo.cpp.

References assert(), DefMI, llvm::MachineInstr::findRegisterDefOperandIdx(), llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineRegisterInfo::getRegClass(), llvm::MachineRegisterInfo::getVRegDef(), llvm::MachineOperand::isImm(), llvm::TargetRegisterInfo::isVirtualRegister(), LLVM_FALLTHROUGH, and removeCopies().

Referenced by llvm::AArch64InstrInfo::canInsertSelect(), and llvm::AArch64InstrInfo::insertSelect().

canInstrSubstituteCmpInstr()

static bool canInstrSubstituteCmpInstr ( MachineInstr *  MI, MachineInstr *  CmpInstr, const TargetRegisterInfo *  TRI  )

static

Check if CmpInstr can be substituted by MI.

CmpInstr can be substituted:

• CmpInstr is either 'ADDS vreg, 0' or 'SUBS vreg, 0'
• and, MI and CmpInstr are from the same MachineBB
• and, condition flags are not alive in successors of the CmpInstr parent
• and, if MI opcode is the S form there must be no defs of flags between MI and CmpInstr or if MI opcode is not the S form there must be neither defs of flags nor uses of flags between MI and CmpInstr.
• and C/V flags are not used after CmpInstr

Definition at line 1394 of file AArch64InstrInfo.cpp.

References llvm::MachineInstr::addRegisterDefined(), AK_All, AK_Write, areCFlagsAccessedBetweenInstrs(), areCFlagsAliveInSuccessors(), assert(), E, llvm::MachineInstr::eraseFromParent(), findCondCodeUsedByInstr(), llvm::ilist_node_impl< OptionsT >::getIterator(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getParent(), llvm::AArch64InstrInfo::getRegisterInfo(), llvm::MachineRegisterInfo::getUniqueVRegDef(), getUsedNZCV(), I, llvm::MachineBasicBlock::instr_end(), llvm::AArch64CC::Invalid, isADDSRegImm(), isSUBSRegImm(), MI, llvm::MachineInstr::modifiesRegister(), MRI, llvm::MachineInstr::readsRegister(), llvm::MachineInstr::setDesc(), sForm(), TRI, and UpdateOperandRegClass().

canPairLdStOpc()

static bool canPairLdStOpc ( unsigned  FirstOpc, unsigned  SecondOpc  )

static

Definition at line 2139 of file AArch64InstrInfo.cpp.

Referenced by llvm::AArch64InstrInfo::shouldClusterMemOps().

convertToNonFlagSettingOpc()

static unsigned convertToNonFlagSettingOpc ( const MachineInstr &  MI )

static

Return the opcode that does not set flags when possible - otherwise return the original opcode.

The caller is responsible to do the actual substitution and legality checking.

Definition at line 1087 of file AArch64InstrInfo.cpp.

References llvm::MachineInstr::definesRegister(), and llvm::MachineInstr::getOpcode().

Referenced by getMaddPatterns(), and llvm::AArch64InstrInfo::optimizeCompareInstr().

findCondCodeUsedByInstr()

static AArch64CC::CondCode findCondCodeUsedByInstr ( const MachineInstr &  Instr )

static

Find a condition code used by the instruction.

Returns AArch64CC::Invalid if either the instruction does not use condition codes or we don't optimize CmpInstr in the presence of such instructions.

Definition at line 1303 of file AArch64InstrInfo.cpp.

References assert(), llvm::MachineInstr::findRegisterUseOperandIdx(), llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), and llvm::AArch64CC::Invalid.

Referenced by canInstrSubstituteCmpInstr().

forwardCopyWillClobberTuple()

static bool forwardCopyWillClobberTuple ( unsigned  DestReg, unsigned  SrcReg, unsigned  NumRegs  )

static

Definition at line 2261 of file AArch64InstrInfo.cpp.

genFusedMultiply()

static MachineInstr* genFusedMultiply ( MachineFunction &  MF, MachineRegisterInfo &  MRI, const TargetInstrInfo *  TII, MachineInstr &  Root, SmallVectorImpl< MachineInstr *> &  InsInstrs, unsigned  IdxMulOpd, unsigned  MaddOpc, const TargetRegisterClass *  RC, FMAInstKind  kind = FMAInstKind::Default, const unsigned *  ReplacedAddend = nullptr  )

static

genFusedMultiply - Generate fused multiply instructions.

This function supports both integer and floating point instructions. A typical example: F|MUL I=A,B,0 F|ADD R,I,C ==> F|MADD R,A,B,C

Parameters

	MF	Containing MachineFunction
	MRI	Register information
	TII	Target information
	Root	is the F|ADD instruction
[out]	InsInstrs	is a vector of machine instructions and will contain the generated madd instruction
	IdxMulOpd	is index of operand in Root that is the result of the F|MUL. In the example above IdxMulOpd is 1.
	MaddOpc	the opcode fo the f|madd instruction
	RC	Register class of operands
	kind	of fma instruction (addressing mode) to be generated
	ReplacedAddend	is the result register from the instruction replacing the non-combined operand, if any.

Definition at line 3985 of file AArch64InstrInfo.cpp.

References Accumulator, assert(), llvm::BuildMI(), llvm::MachineRegisterInfo::constrainRegClass(), Default, llvm::MCInstrInfo::get(), llvm::MachineInstr::getDebugLoc(), llvm::MachineOperand::getImm(), llvm::getKillRegState(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineRegisterInfo::getUniqueVRegDef(), Indexed, llvm::MachineOperand::isKill(), llvm::TargetRegisterInfo::isVirtualRegister(), llvm::ISD::MUL, and llvm::SmallVectorTemplateBase< T, bool >::push_back().

Referenced by llvm::AArch64InstrInfo::genAlternativeCodeSequence().

genMaddR()

static MachineInstr* genMaddR ( MachineFunction &  MF, MachineRegisterInfo &  MRI, const TargetInstrInfo *  TII, MachineInstr &  Root, SmallVectorImpl< MachineInstr *> &  InsInstrs, unsigned  IdxMulOpd, unsigned  MaddOpc, unsigned  VR, const TargetRegisterClass *  RC  )

static

genMaddR - Generate madd instruction and combine mul and add using an extra virtual register Example - an ADD intermediate needs to be stored in a register: MUL I=A,B,0 ADD R,I,Imm ==> ORR V, ZR, Imm ==> MADD R,A,B,V

Parameters

	MF	Containing MachineFunction
	MRI	Register information
	TII	Target information
	Root	is the ADD instruction
[out]	InsInstrs	is a vector of machine instructions and will contain the generated madd instruction
	IdxMulOpd	is index of operand in Root that is the result of the MUL. In the example above IdxMulOpd is 1.
	MaddOpc	the opcode fo the madd instruction
	VR	is a virtual register that holds the value of an ADD operand (V in the example above).
	RC	Register class of operands

Definition at line 4064 of file AArch64InstrInfo.cpp.

References assert(), llvm::BuildMI(), llvm::MachineRegisterInfo::constrainRegClass(), llvm::MCInstrInfo::get(), llvm::MachineInstr::getDebugLoc(), llvm::getKillRegState(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineRegisterInfo::getUniqueVRegDef(), llvm::MachineOperand::isKill(), llvm::TargetRegisterInfo::isVirtualRegister(), llvm::ISD::MUL, and llvm::SmallVectorTemplateBase< T, bool >::push_back().

Referenced by llvm::AArch64InstrInfo::genAlternativeCodeSequence().

getBranchDisplacementBits()

static unsigned getBranchDisplacementBits ( unsigned  Opc )

static

Definition at line 156 of file AArch64InstrInfo.cpp.

References B, BCCDisplacementBits, CBZDisplacementBits, llvm_unreachable, and TBZDisplacementBits.

Referenced by llvm::AArch64InstrInfo::isBranchOffsetInRange().

getFMAPatterns()

static bool getFMAPatterns ( MachineInstr &  Root, SmallVectorImpl< MachineCombinerPattern > &  Patterns  )

static

Floating-Point Support.

Find instructions that can be turned into madd.

Definition at line 3688 of file AArch64InstrInfo.cpp.

References assert(), canCombineWithFMUL(), llvm::FMLAv1i32_indexed_OP1, llvm::FMLAv1i32_indexed_OP2, llvm::FMLAv1i64_indexed_OP1, llvm::FMLAv1i64_indexed_OP2, llvm::FMLAv2f32_OP1, llvm::FMLAv2f32_OP2, llvm::FMLAv2f64_OP1, llvm::FMLAv2f64_OP2, llvm::FMLAv2i32_indexed_OP1, llvm::FMLAv2i32_indexed_OP2, llvm::FMLAv2i64_indexed_OP1, llvm::FMLAv2i64_indexed_OP2, llvm::FMLAv4f32_OP1, llvm::FMLAv4f32_OP2, llvm::FMLAv4i32_indexed_OP1, llvm::FMLAv4i32_indexed_OP2, llvm::FMLSv1i32_indexed_OP2, llvm::FMLSv1i64_indexed_OP2, llvm::FMLSv2f32_OP1, llvm::FMLSv2f32_OP2, llvm::FMLSv2f64_OP1, llvm::FMLSv2f64_OP2, llvm::FMLSv2i32_indexed_OP1, llvm::FMLSv2i32_indexed_OP2, llvm::FMLSv2i64_indexed_OP1, llvm::FMLSv2i64_indexed_OP2, llvm::FMLSv4f32_OP1, llvm::FMLSv4f32_OP2, llvm::FMLSv4i32_indexed_OP1, llvm::FMLSv4i32_indexed_OP2, llvm::FMULADDD_OP1, llvm::FMULADDD_OP2, llvm::FMULADDS_OP1, llvm::FMULADDS_OP2, llvm::FMULSUBD_OP1, llvm::FMULSUBD_OP2, llvm::FMULSUBS_OP1, llvm::FMULSUBS_OP2, llvm::FNMULSUBD_OP1, llvm::FNMULSUBS_OP1, llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), isCombineInstrCandidateFP(), llvm::MachineOperand::isReg(), and llvm::SmallVectorTemplateBase< T >::push_back().

Referenced by llvm::AArch64InstrInfo::getMachineCombinerPatterns().

getMaddPatterns()

static bool getMaddPatterns ( MachineInstr &  Root, SmallVectorImpl< MachineCombinerPattern > &  Patterns  )

static

Find instructions that can be turned into madd.

Definition at line 3580 of file AArch64InstrInfo.cpp.

References assert(), canCombineWithMUL(), convertToNonFlagSettingOpc(), llvm::MachineInstr::findRegisterDefOperandIdx(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), isCombineInstrCandidate(), isCombineInstrSettingFlag(), llvm::MachineOperand::isReg(), llvm::MULADDW_OP1, llvm::MULADDW_OP2, llvm::MULADDWI_OP1, llvm::MULADDX_OP1, llvm::MULADDX_OP2, llvm::MULADDXI_OP1, llvm::MULSUBW_OP1, llvm::MULSUBW_OP2, llvm::MULSUBWI_OP1, llvm::MULSUBX_OP1, llvm::MULSUBX_OP2, llvm::MULSUBXI_OP1, and llvm::SmallVectorTemplateBase< T >::push_back().

Referenced by llvm::AArch64InstrInfo::getMachineCombinerPatterns().

getOffsetStride()

static unsigned getOffsetStride ( unsigned  Opc )

static

Definition at line 2088 of file AArch64InstrInfo.cpp.

Referenced by scaleOffset(), and unscaleOffset().

getUsedNZCV()

static UsedNZCV getUsedNZCV ( AArch64CC::CondCode  CC )

static

Definition at line 1331 of file AArch64InstrInfo.cpp.

References assert(), llvm::AArch64CC::EQ, llvm::AArch64CC::GE, llvm::AArch64CC::GT, llvm::AArch64CC::HI, llvm::AArch64CC::HS, llvm::AArch64CC::Invalid, llvm::AArch64CC::LE, LLVM_FALLTHROUGH, llvm::AArch64CC::LO, llvm::AArch64CC::LS, llvm::AArch64CC::LT, llvm::AArch64CC::MI, llvm::AArch64CC::NE, llvm::AArch64CC::PL, llvm::AArch64CC::VC, and llvm::AArch64CC::VS.

Referenced by canInstrSubstituteCmpInstr().

isADDSRegImm()

static bool isADDSRegImm ( unsigned  Opcode )

static

Definition at line 1375 of file AArch64InstrInfo.cpp.

Referenced by canInstrSubstituteCmpInstr().

isCombineInstrCandidate()

static bool isCombineInstrCandidate ( unsigned  Opc )

static

Definition at line 3503 of file AArch64InstrInfo.cpp.

References isCombineInstrCandidate32(), and isCombineInstrCandidate64().

Referenced by getMaddPatterns().

isCombineInstrCandidate32()

static bool isCombineInstrCandidate32 ( unsigned  Opc )

static

Definition at line 3443 of file AArch64InstrInfo.cpp.

Referenced by isCombineInstrCandidate().

isCombineInstrCandidate64()

static bool isCombineInstrCandidate64 ( unsigned  Opc )

static

Definition at line 3462 of file AArch64InstrInfo.cpp.

Referenced by isCombineInstrCandidate().

isCombineInstrCandidateFP()

static bool isCombineInstrCandidateFP ( const MachineInstr &  Inst )

static

Definition at line 3481 of file AArch64InstrInfo.cpp.

References llvm::TargetOptions::AllowFPOpFusion, llvm::FPOpFusion::Fast, llvm::MachineInstr::getOpcode(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), llvm::MachineFunction::getTarget(), llvm::TargetMachine::Options, and llvm::TargetOptions::UnsafeFPMath.

Referenced by getFMAPatterns().

isCombineInstrSettingFlag()

static bool isCombineInstrSettingFlag ( unsigned  Opc )

static

Definition at line 3424 of file AArch64InstrInfo.cpp.

Referenced by getMaddPatterns().

isSUBSRegImm()

static bool isSUBSRegImm ( unsigned  Opcode )

static

Definition at line 1379 of file AArch64InstrInfo.cpp.

Referenced by canInstrSubstituteCmpInstr().

loadRegPairFromStackSlot()

static void loadRegPairFromStackSlot ( const TargetRegisterInfo &  TRI, MachineBasicBlock &  MBB, MachineBasicBlock::iterator  InsertBefore, const MCInstrDesc &  MCID, unsigned  DestReg, unsigned  SubIdx0, unsigned  SubIdx1, int  FI, MachineMemOperand *  MMO  )

static

Definition at line 2748 of file AArch64InstrInfo.cpp.

References llvm::MachineInstrBuilder::addFrameIndex(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMemOperand(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::RegState::Define, llvm::MCRegisterInfo::getSubReg(), llvm::getUndefRegState(), and llvm::TargetRegisterInfo::isPhysicalRegister().

Referenced by llvm::AArch64InstrInfo::loadRegFromStackSlot().

parseCondBranch()

static void parseCondBranch ( MachineInstr *  LastInst, MachineBasicBlock *&  Target, SmallVectorImpl< MachineOperand > &  Cond  )

static

Definition at line 125 of file AArch64InstrInfo.cpp.

References llvm::MachineOperand::CreateImm(), llvm::MachineOperand::getMBB(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm_unreachable, and llvm::SmallVectorTemplateBase< T >::push_back().

Referenced by llvm::AArch64InstrInfo::analyzeBranch().

removeCopies()

static unsigned removeCopies ( const MachineRegisterInfo &  MRI, unsigned  VReg  )

static

Definition at line 416 of file AArch64InstrInfo.cpp.

References DefMI, llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineRegisterInfo::getVRegDef(), llvm::MachineInstr::isFullCopy(), and llvm::TargetRegisterInfo::isVirtualRegister().

Referenced by canFoldIntoCSel().

scaleOffset()

static bool scaleOffset ( unsigned  Opc, int64_t &  Offset  )

static

Definition at line 2111 of file AArch64InstrInfo.cpp.

References getOffsetStride().

Referenced by shouldClusterFI(), and llvm::AArch64InstrInfo::shouldClusterMemOps().

sForm()

static unsigned sForm ( MachineInstr &  Instr )

static

Get opcode of S version of Instr.

If Instr is S version its opcode is returned. AArch64::INSTRUCTION_LIST_END is returned if Instr does not have S version or we are not interested in it.

Definition at line 1225 of file AArch64InstrInfo.cpp.

References llvm::MachineInstr::getOpcode().

Referenced by canInstrSubstituteCmpInstr().

shouldClusterFI()

static bool shouldClusterFI ( const MachineFrameInfo &  MFI, int  FI1, int64_t  Offset1, unsigned  Opcode1, int  FI2, int64_t  Offset2, unsigned  Opcode2  )

static

Definition at line 2157 of file AArch64InstrInfo.cpp.

References assert(), llvm::MachineFrameInfo::getObjectOffset(), llvm::MachineFrameInfo::isFixedObjectIndex(), scaleOffset(), and unscaleOffset().

Referenced by llvm::AArch64InstrInfo::shouldClusterMemOps().

storeRegPairToStackSlot()

static void storeRegPairToStackSlot ( const TargetRegisterInfo &  TRI, MachineBasicBlock &  MBB, MachineBasicBlock::iterator  InsertBefore, const MCInstrDesc &  MCID, unsigned  SrcReg, bool  IsKill, unsigned  SubIdx0, unsigned  SubIdx1, int  FI, MachineMemOperand *  MMO  )

static

Definition at line 2619 of file AArch64InstrInfo.cpp.

References llvm::MachineInstrBuilder::addFrameIndex(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMemOperand(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::getKillRegState(), llvm::MCRegisterInfo::getSubReg(), and llvm::TargetRegisterInfo::isPhysicalRegister().

Referenced by llvm::AArch64InstrInfo::storeRegToStackSlot().

unscaleOffset()

static bool unscaleOffset ( unsigned  Opc, int64_t &  Offset  )

static

Definition at line 2128 of file AArch64InstrInfo.cpp.

References getOffsetStride().

Referenced by shouldClusterFI().

UpdateOperandRegClass()

static bool UpdateOperandRegClass ( MachineInstr &  Instr )

static

Definition at line 1046 of file AArch64InstrInfo.cpp.

References assert(), llvm::MachineRegisterInfo::constrainRegClass(), llvm::TargetRegisterClass::contains(), llvm::TargetSubtargetInfo::getInstrInfo(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), llvm::MachineRegisterInfo::getRegClass(), llvm::MachineInstr::getRegClassConstraint(), llvm::MachineFunction::getRegInfo(), llvm::TargetSubtargetInfo::getRegisterInfo(), llvm::MachineFunction::getSubtarget(), llvm::TargetRegisterClass::hasSubClassEq(), llvm::MachineOperand::isFI(), llvm::TargetRegisterInfo::isPhysicalRegister(), llvm::MachineOperand::isReg(), MRI, Reg, TII, and TRI.

Referenced by canInstrSubstituteCmpInstr(), and llvm::AArch64InstrInfo::optimizeCompareInstr().

Variable Documentation

BCCDisplacementBits

cl::opt<unsigned> BCCDisplacementBits("aarch64-bcc-offset-bits", cl::Hidden, cl::init(19), cl::desc("Restrict range of Bcc instructions (DEBUG)"))

static

Referenced by getBranchDisplacementBits().

CBZDisplacementBits

cl::opt<unsigned> CBZDisplacementBits("aarch64-cbz-offset-bits", cl::Hidden, cl::init(19), cl::desc("Restrict range of CB[N]Z instructions (DEBUG)"))

static

Referenced by getBranchDisplacementBits().

TBZDisplacementBits

cl::opt<unsigned> TBZDisplacementBits("aarch64-tbz-offset-bits", cl::Hidden, cl::init(14), cl::desc("Restrict range of TB[N]Z instructions (DEBUG)"))

static

Referenced by getBranchDisplacementBits().