LLVM  8.0.1
AArch64Subtarget.h
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1 //===--- AArch64Subtarget.h - Define Subtarget for the AArch64 -*- C++ -*--===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file declares the AArch64 specific subclass of TargetSubtarget.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_AARCH64_AARCH64SUBTARGET_H
15 #define LLVM_LIB_TARGET_AARCH64_AARCH64SUBTARGET_H
16 
17 #include "AArch64FrameLowering.h"
18 #include "AArch64ISelLowering.h"
19 #include "AArch64InstrInfo.h"
20 #include "AArch64RegisterInfo.h"
27 #include "llvm/IR/DataLayout.h"
28 #include <string>
29 
30 #define GET_SUBTARGETINFO_HEADER
31 #include "AArch64GenSubtargetInfo.inc"
32 
33 namespace llvm {
34 class GlobalValue;
35 class StringRef;
36 class Triple;
37 
39 public:
40  enum ARMProcFamilyEnum : uint8_t {
61  };
62 
63 protected:
64  /// ARMProcFamily - ARM processor family: Cortex-A53, Cortex-A57, and others.
66 
67  bool HasV8_1aOps = false;
68  bool HasV8_2aOps = false;
69  bool HasV8_3aOps = false;
70  bool HasV8_4aOps = false;
71  bool HasV8_5aOps = false;
72 
73  bool HasFPARMv8 = false;
74  bool HasNEON = false;
75  bool HasCrypto = false;
76  bool HasDotProd = false;
77  bool HasCRC = false;
78  bool HasLSE = false;
79  bool HasRAS = false;
80  bool HasRDM = false;
81  bool HasPerfMon = false;
82  bool HasFullFP16 = false;
83  bool HasFP16FML = false;
84  bool HasSPE = false;
85 
86  // ARMv8.1 extensions
87  bool HasVH = false;
88  bool HasPAN = false;
89  bool HasLOR = false;
90 
91  // ARMv8.2 extensions
92  bool HasPsUAO = false;
93  bool HasPAN_RWV = false;
94  bool HasCCPP = false;
95 
96  // ARMv8.3 extensions
97  bool HasPA = false;
98  bool HasJS = false;
99  bool HasCCIDX = false;
100  bool HasComplxNum = false;
101 
102  // ARMv8.4 extensions
103  bool HasNV = false;
104  bool HasRASv8_4 = false;
105  bool HasMPAM = false;
106  bool HasDIT = false;
107  bool HasTRACEV8_4 = false;
108  bool HasAM = false;
109  bool HasSEL2 = false;
110  bool HasTLB_RMI = false;
111  bool HasFMI = false;
112  bool HasRCPC_IMMO = false;
113  // ARMv8.4 Crypto extensions
114  bool HasSM4 = true;
115  bool HasSHA3 = true;
116 
117  bool HasSHA2 = true;
118  bool HasAES = true;
119 
120  bool HasLSLFast = false;
121  bool HasSVE = false;
122  bool HasRCPC = false;
123  bool HasAggressiveFMA = false;
124 
125  // Armv8.5-A Extensions
126  bool HasAlternativeNZCV = false;
127  bool HasFRInt3264 = false;
128  bool HasSpecRestrict = false;
129  bool HasSSBS = false;
130  bool HasSB = false;
131  bool HasPredRes = false;
132  bool HasCCDP = false;
133  bool HasBTI = false;
134  bool HasRandGen = false;
135  bool HasMTE = false;
136 
137  // HasZeroCycleRegMove - Has zero-cycle register mov instructions.
138  bool HasZeroCycleRegMove = false;
139 
140  // HasZeroCycleZeroing - Has zero-cycle zeroing instructions.
141  bool HasZeroCycleZeroing = false;
142  bool HasZeroCycleZeroingGP = false;
143  bool HasZeroCycleZeroingFP = false;
145 
146  // StrictAlign - Disallow unaligned memory accesses.
147  bool StrictAlign = false;
148 
149  // NegativeImmediates - transform instructions with negative immediates
150  bool NegativeImmediates = true;
151 
152  // Enable 64-bit vectorization in SLP.
154 
155  bool UseAA = false;
157  bool BalanceFPOps = false;
158  bool CustomAsCheapAsMove = false;
159  bool ExynosAsCheapAsMove = false;
160  bool UsePostRAScheduler = false;
162  bool Paired128IsSlow = false;
163  bool STRQroIsSlow = false;
167  bool HasFuseAddress = false;
168  bool HasFuseAES = false;
170  bool HasFuseCCSelect = false;
171  bool HasFuseCryptoEOR = false;
172  bool HasFuseLiterals = false;
174  bool UseRSqrt = false;
175  bool Force32BitJumpTables = false;
176  uint8_t MaxInterleaveFactor = 2;
178  uint16_t CacheLineSize = 0;
179  uint16_t PrefetchDistance = 0;
180  uint16_t MinPrefetchStride = 1;
181  unsigned MaxPrefetchIterationsAhead = UINT_MAX;
182  unsigned PrefFunctionAlignment = 0;
183  unsigned PrefLoopAlignment = 0;
184  unsigned MaxJumpTableSize = 0;
185  unsigned WideningBaseCost = 0;
186 
187  // ReserveXRegister[i] - X#i is not available as a general purpose register.
189 
190  // CustomCallUsedXRegister[i] - X#i call saved.
192 
193  bool IsLittle;
194 
195  /// TargetTriple - What processor and OS we're targeting.
197 
202 
203  /// GlobalISel related APIs.
204  std::unique_ptr<CallLowering> CallLoweringInfo;
205  std::unique_ptr<InstructionSelector> InstSelector;
206  std::unique_ptr<LegalizerInfo> Legalizer;
207  std::unique_ptr<RegisterBankInfo> RegBankInfo;
208 
209 private:
210  /// initializeSubtargetDependencies - Initializes using CPUString and the
211  /// passed in feature string so that we can use initializer lists for
212  /// subtarget initialization.
213  AArch64Subtarget &initializeSubtargetDependencies(StringRef FS,
214  StringRef CPUString);
215 
216  /// Initialize properties based on the selected processor family.
217  void initializeProperties();
218 
219 public:
220  /// This constructor initializes the data members to match that
221  /// of the specified triple.
222  AArch64Subtarget(const Triple &TT, const std::string &CPU,
223  const std::string &FS, const TargetMachine &TM,
224  bool LittleEndian);
225 
227  return &TSInfo;
228  }
229  const AArch64FrameLowering *getFrameLowering() const override {
230  return &FrameLowering;
231  }
232  const AArch64TargetLowering *getTargetLowering() const override {
233  return &TLInfo;
234  }
235  const AArch64InstrInfo *getInstrInfo() const override { return &InstrInfo; }
236  const AArch64RegisterInfo *getRegisterInfo() const override {
237  return &getInstrInfo()->getRegisterInfo();
238  }
239  const CallLowering *getCallLowering() const override;
240  const InstructionSelector *getInstructionSelector() const override;
241  const LegalizerInfo *getLegalizerInfo() const override;
242  const RegisterBankInfo *getRegBankInfo() const override;
243  const Triple &getTargetTriple() const { return TargetTriple; }
244  bool enableMachineScheduler() const override { return true; }
245  bool enablePostRAScheduler() const override {
246  return UsePostRAScheduler;
247  }
248 
249  /// Returns ARM processor family.
250  /// Avoid this function! CPU specifics should be kept local to this class
251  /// and preferably modeled with SubtargetFeatures or properties in
252  /// initializeProperties().
254  return ARMProcFamily;
255  }
256 
257  bool hasV8_1aOps() const { return HasV8_1aOps; }
258  bool hasV8_2aOps() const { return HasV8_2aOps; }
259  bool hasV8_3aOps() const { return HasV8_3aOps; }
260  bool hasV8_4aOps() const { return HasV8_4aOps; }
261  bool hasV8_5aOps() const { return HasV8_5aOps; }
262 
263  bool hasZeroCycleRegMove() const { return HasZeroCycleRegMove; }
264 
266 
268 
271  }
272 
273  bool requiresStrictAlign() const { return StrictAlign; }
274 
275  bool isXRaySupported() const override { return true; }
276 
277  unsigned getMinVectorRegisterBitWidth() const {
279  }
280 
281  bool isXRegisterReserved(size_t i) const { return ReserveXRegister[i]; }
282  unsigned getNumXRegisterReserved() const { return ReserveXRegister.count(); }
283  bool isXRegCustomCalleeSaved(size_t i) const {
284  return CustomCallSavedXRegs[i];
285  }
286  bool hasCustomCallingConv() const { return CustomCallSavedXRegs.any(); }
287  bool hasFPARMv8() const { return HasFPARMv8; }
288  bool hasNEON() const { return HasNEON; }
289  bool hasCrypto() const { return HasCrypto; }
290  bool hasDotProd() const { return HasDotProd; }
291  bool hasCRC() const { return HasCRC; }
292  bool hasLSE() const { return HasLSE; }
293  bool hasRAS() const { return HasRAS; }
294  bool hasRDM() const { return HasRDM; }
295  bool hasSM4() const { return HasSM4; }
296  bool hasSHA3() const { return HasSHA3; }
297  bool hasSHA2() const { return HasSHA2; }
298  bool hasAES() const { return HasAES; }
299  bool balanceFPOps() const { return BalanceFPOps; }
302  }
306  bool isPaired128Slow() const { return Paired128IsSlow; }
307  bool isSTRQroSlow() const { return STRQroIsSlow; }
310  }
313  bool hasFuseAddress() const { return HasFuseAddress; }
314  bool hasFuseAES() const { return HasFuseAES; }
316  bool hasFuseCCSelect() const { return HasFuseCCSelect; }
317  bool hasFuseCryptoEOR() const { return HasFuseCryptoEOR; }
318  bool hasFuseLiterals() const { return HasFuseLiterals; }
319 
320  /// Return true if the CPU supports any kind of instruction fusion.
321  bool hasFusion() const {
325  }
326 
327  bool useRSqrt() const { return UseRSqrt; }
329  unsigned getMaxInterleaveFactor() const { return MaxInterleaveFactor; }
332  }
333  unsigned getCacheLineSize() const { return CacheLineSize; }
334  unsigned getPrefetchDistance() const { return PrefetchDistance; }
335  unsigned getMinPrefetchStride() const { return MinPrefetchStride; }
336  unsigned getMaxPrefetchIterationsAhead() const {
338  }
339  unsigned getPrefFunctionAlignment() const { return PrefFunctionAlignment; }
340  unsigned getPrefLoopAlignment() const { return PrefLoopAlignment; }
341 
342  unsigned getMaximumJumpTableSize() const { return MaxJumpTableSize; }
343 
344  unsigned getWideningBaseCost() const { return WideningBaseCost; }
345 
346  /// CPU has TBI (top byte of addresses is ignored during HW address
347  /// translation) and OS enables it.
348  bool supportsAddressTopByteIgnored() const;
349 
350  bool hasPerfMon() const { return HasPerfMon; }
351  bool hasFullFP16() const { return HasFullFP16; }
352  bool hasFP16FML() const { return HasFP16FML; }
353  bool hasSPE() const { return HasSPE; }
354  bool hasLSLFast() const { return HasLSLFast; }
355  bool hasSVE() const { return HasSVE; }
356  bool hasRCPC() const { return HasRCPC; }
357  bool hasAggressiveFMA() const { return HasAggressiveFMA; }
358  bool hasAlternativeNZCV() const { return HasAlternativeNZCV; }
359  bool hasFRInt3264() const { return HasFRInt3264; }
360  bool hasSpecRestrict() const { return HasSpecRestrict; }
361  bool hasSSBS() const { return HasSSBS; }
362  bool hasSB() const { return HasSB; }
363  bool hasPredRes() const { return HasPredRes; }
364  bool hasCCDP() const { return HasCCDP; }
365  bool hasBTI() const { return HasBTI; }
366  bool hasRandGen() const { return HasRandGen; }
367  bool hasMTE() const { return HasMTE; }
368 
369  bool isLittleEndian() const { return IsLittle; }
370 
371  bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
372  bool isTargetIOS() const { return TargetTriple.isiOS(); }
373  bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
374  bool isTargetWindows() const { return TargetTriple.isOSWindows(); }
375  bool isTargetAndroid() const { return TargetTriple.isAndroid(); }
376  bool isTargetFuchsia() const { return TargetTriple.isOSFuchsia(); }
377 
378  bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); }
379  bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
380  bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
381 
382  bool useAA() const override { return UseAA; }
383 
384  bool hasVH() const { return HasVH; }
385  bool hasPAN() const { return HasPAN; }
386  bool hasLOR() const { return HasLOR; }
387 
388  bool hasPsUAO() const { return HasPsUAO; }
389  bool hasPAN_RWV() const { return HasPAN_RWV; }
390  bool hasCCPP() const { return HasCCPP; }
391 
392  bool hasPA() const { return HasPA; }
393  bool hasJS() const { return HasJS; }
394  bool hasCCIDX() const { return HasCCIDX; }
395  bool hasComplxNum() const { return HasComplxNum; }
396 
397  bool hasNV() const { return HasNV; }
398  bool hasRASv8_4() const { return HasRASv8_4; }
399  bool hasMPAM() const { return HasMPAM; }
400  bool hasDIT() const { return HasDIT; }
401  bool hasTRACEV8_4() const { return HasTRACEV8_4; }
402  bool hasAM() const { return HasAM; }
403  bool hasSEL2() const { return HasSEL2; }
404  bool hasTLB_RMI() const { return HasTLB_RMI; }
405  bool hasFMI() const { return HasFMI; }
406  bool hasRCPC_IMMO() const { return HasRCPC_IMMO; }
407 
408  bool useSmallAddressing() const {
409  switch (TLInfo.getTargetMachine().getCodeModel()) {
410  case CodeModel::Kernel:
411  // Kernel is currently allowed only for Fuchsia targets,
412  // where it is the same as Small for almost all purposes.
413  case CodeModel::Small:
414  return true;
415  default:
416  return false;
417  }
418  }
419 
420  /// ParseSubtargetFeatures - Parses features string setting specified
421  /// subtarget options. Definition of function is auto generated by tblgen.
423 
424  /// ClassifyGlobalReference - Find the target operand flags that describe
425  /// how a global value should be referenced for the current subtarget.
426  unsigned char ClassifyGlobalReference(const GlobalValue *GV,
427  const TargetMachine &TM) const;
428 
429  unsigned char classifyGlobalFunctionReference(const GlobalValue *GV,
430  const TargetMachine &TM) const;
431 
433  unsigned NumRegionInstrs) const override;
434 
435  bool enableEarlyIfConversion() const override;
436 
437  std::unique_ptr<PBQPRAConstraint> getCustomPBQPConstraints() const override;
438 
440  switch (CC) {
441  case CallingConv::C:
442  case CallingConv::Fast:
443  case CallingConv::Swift:
444  return isTargetWindows();
445  case CallingConv::Win64:
446  return true;
447  default:
448  return false;
449  }
450  }
451 
452  void mirFileLoaded(MachineFunction &MF) const override;
453 };
454 } // End llvm namespace
455 
456 #endif
const Triple & getTargetTriple() const
bool isOSDarwin() const
isOSDarwin - Is this a "Darwin" OS (OS X, iOS, or watchOS).
Definition: Triple.h:475
bool hasAlternativeNZCV() const
C - The default llvm calling convention, compatible with C.
Definition: CallingConv.h:35
bool isMisaligned128StoreSlow() const
This class represents lattice values for constants.
Definition: AllocatorList.h:24
bool hasCustomCallingConv() const
bool isOSBinFormatELF() const
Tests whether the OS uses the ELF binary format.
Definition: Triple.h:604
bool predictableSelectIsExpensive() const
unsigned char ClassifyGlobalReference(const GlobalValue *GV, const TargetMachine &TM) const
ClassifyGlobalReference - Find the target operand flags that describe how a global value should be re...
const InstructionSelector * getInstructionSelector() const override
The C convention as implemented on Windows/x86-64 and AArch64.
Definition: CallingConv.h:154
AArch64SelectionDAGInfo TSInfo
const AArch64FrameLowering * getFrameLowering() const override
bool isOSFuchsia() const
Definition: Triple.h:495
const CallLowering * getCallLowering() const override
bool isCallingConvWin64(CallingConv::ID CC) const
bool hasCustomCheapAsMoveHandling() const
void mirFileLoaded(MachineFunction &MF) const override
void overrideSchedPolicy(MachineSchedPolicy &Policy, unsigned NumRegionInstrs) const override
bool hasFuseArithmeticLogic() const
unsigned getCacheLineSize() const
Holds all the information related to register banks.
bool hasFusion() const
Return true if the CPU supports any kind of instruction fusion.
bool hasArithmeticBccFusion() const
bool hasZeroCycleRegMove() const
bool force32BitJumpTables() const
std::unique_ptr< InstructionSelector > InstSelector
Fast - This calling convention attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:43
bool useAlternateSExtLoadCVTF32Pattern() const
const AArch64RegisterInfo * getRegisterInfo() const override
std::unique_ptr< LegalizerInfo > Legalizer
unsigned getPrefetchDistance() const
bool useAA() const override
bool isiOS() const
Is this an iOS triple.
Definition: Triple.h:456
unsigned getWideningBaseCost() const
bool enableMachineScheduler() const override
bool isXRegisterReserved(size_t i) const
bool supportsAddressTopByteIgnored() const
CPU has TBI (top byte of addresses is ignored during HW address translation) and OS enables it...
bool enableEarlyIfConversion() const override
unsigned getMinVectorRegisterBitWidth() const
bool isOSWindows() const
Tests whether the OS is Windows.
Definition: Triple.h:567
const AArch64TargetLowering * getTargetLowering() const override
const AArch64RegisterInfo & getRegisterInfo() const
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
bool requiresStrictAlign() const
bool isOSBinFormatCOFF() const
Tests whether the OS uses the COFF binary format.
Definition: Triple.h:609
bool hasExynosCheapAsMoveHandling() const
bool isXRaySupported() const override
bool any() const
any - Returns true if any bit is set.
Definition: BitVector.h:181
unsigned getPrefFunctionAlignment() const
bool useSmallAddressing() const
std::unique_ptr< CallLowering > CallLoweringInfo
GlobalISel related APIs.
bool isOSBinFormatMachO() const
Tests whether the environment is MachO.
Definition: Triple.h:614
const TargetMachine & getTargetMachine() const
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
unsigned getMinPrefetchStride() const
const AArch64SelectionDAGInfo * getSelectionDAGInfo() const override
bool hasArithmeticCbzFusion() const
size_type count() const
count - Returns the number of bits which are set.
Definition: BitVector.h:173
AArch64InstrInfo InstrInfo
unsigned getMaximumJumpTableSize() const
void ParseSubtargetFeatures(StringRef CPU, StringRef FS)
ParseSubtargetFeatures - Parses features string setting specified subtarget options.
bool isOSLinux() const
Tests whether the OS is Linux.
Definition: Triple.h:577
bool enablePostRAScheduler() const override
CodeModel::Model getCodeModel() const
Returns the code model.
unsigned getMaxInterleaveFactor() const
unsigned getNumXRegisterReserved() const
std::unique_ptr< RegisterBankInfo > RegBankInfo
Provides the logic to select generic machine instructions.
Define a generic scheduling policy for targets that don&#39;t provide their own MachineSchedStrategy.
std::unique_ptr< PBQPRAConstraint > getCustomPBQPConstraints() const override
AArch64Subtarget(const Triple &TT, const std::string &CPU, const std::string &FS, const TargetMachine &TM, bool LittleEndian)
This constructor initializes the data members to match that of the specified triple.
const LegalizerInfo * getLegalizerInfo() const override
AArch64FrameLowering FrameLowering
ARMProcFamilyEnum getProcFamily() const
Returns ARM processor family.
bool hasZeroCycleZeroingFPWorkaround() const
Triple TargetTriple
TargetTriple - What processor and OS we&#39;re targeting.
ARMProcFamilyEnum ARMProcFamily
ARMProcFamily - ARM processor family: Cortex-A53, Cortex-A57, and others.
bool hasZeroCycleZeroingFP() const
bool hasZeroCycleZeroingGP() const
unsigned getMaxPrefetchIterationsAhead() const
bool isXRegCustomCalleeSaved(size_t i) const
const AArch64InstrInfo * getInstrInfo() const override
This file describes how to lower LLVM calls to machine code calls.
const RegisterBankInfo * getRegBankInfo() const override
bool isAndroid() const
Tests whether the target is Android.
Definition: Triple.h:637
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:59
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
AArch64TargetLowering TLInfo
unsigned char classifyGlobalFunctionReference(const GlobalValue *GV, const TargetMachine &TM) const
unsigned getPrefLoopAlignment() const
unsigned getVectorInsertExtractBaseCost() const