llvm::AMDGPUInstructionSelector Class Reference

#include "Target/AMDGPU/AMDGPUInstructionSelector.h"

Inheritance diagram for llvm::AMDGPUInstructionSelector:

Collaboration diagram for llvm::AMDGPUInstructionSelector:

Public Member Functions
	AMDGPUInstructionSelector (const GCNSubtarget &STI, const AMDGPURegisterBankInfo &RBI, const AMDGPUTargetMachine &TM)
bool	select (MachineInstr &I, CodeGenCoverage &CoverageInfo) const override
	Select the (possibly generic) instruction I to only use target-specific opcodes. More...
Public Member Functions inherited from llvm::InstructionSelector
virtual	~InstructionSelector ()=default

Static Public Member Functions
static const char *	getName ()

Additional Inherited Members
Protected Types inherited from llvm::InstructionSelector
using	ComplexRendererFns = Optional< SmallVector< std::function< void(MachineInstrBuilder &)>, 4 > >
using	RecordedMIVector = SmallVector< MachineInstr *, 4 >
using	NewMIVector = SmallVector< MachineInstrBuilder, 4 >
Protected Member Functions inherited from llvm::InstructionSelector
	InstructionSelector ()
template<class TgtInstructionSelector , class PredicateBitset , class ComplexMatcherMemFn , class CustomRendererFn >
bool	executeMatchTable (TgtInstructionSelector &ISel, NewMIVector &OutMIs, MatcherState &State, const ISelInfoTy< PredicateBitset, ComplexMatcherMemFn, CustomRendererFn > &ISelInfo, const int64_t *MatchTable, const TargetInstrInfo &TII, MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI, const PredicateBitset &AvailableFeatures, CodeGenCoverage &CoverageInfo) const
	Execute a given matcher table and return true if the match was successful and false otherwise. More...
virtual const int64_t *	getMatchTable () const
virtual bool	testImmPredicate_I64 (unsigned, int64_t) const
virtual bool	testImmPredicate_APInt (unsigned, const APInt &) const
virtual bool	testImmPredicate_APFloat (unsigned, const APFloat &) const
virtual bool	testMIPredicate_MI (unsigned, const MachineInstr &) const
bool	constrainOperandRegToRegClass (MachineInstr &I, unsigned OpIdx, const TargetRegisterClass &RC, const TargetInstrInfo &TII, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI) const
	Constrain a register operand of an instruction I to a specified register class. More...
bool	isOperandImmEqual (const MachineOperand &MO, int64_t Value, const MachineRegisterInfo &MRI) const
bool	isBaseWithConstantOffset (const MachineOperand &Root, const MachineRegisterInfo &MRI) const
	Return true if the specified operand is a G_GEP with a G_CONSTANT on the right-hand side. More...
bool	isObviouslySafeToFold (MachineInstr &MI, MachineInstr &IntoMI) const
	Return true if MI can obviously be folded into IntoMI. More...

Detailed Description

Definition at line 43 of file AMDGPUInstructionSelector.h.

Constructor & Destructor Documentation

AMDGPUInstructionSelector()

AMDGPUInstructionSelector::AMDGPUInstructionSelector	(	const GCNSubtarget &	STI,
		const AMDGPURegisterBankInfo &	RBI,
		const AMDGPUTargetMachine &	TM
	)

Definition at line 45 of file AMDGPUInstructionSelector.cpp.

References assert(), llvm::BuildMI(), llvm::RegisterBankInfo::constrainGenericRegister(), llvm::MachineOperand::CreateImm(), llvm::MachineOperand::CreateReg(), llvm::MachineRegisterInfo::createVirtualRegister(), DEBUG_TYPE, llvm::SIRegisterInfo::getConstrainedRegClassForOperand(), llvm::MachineInstr::getDebugLoc(), llvm::MachineOperand::getImm(), getName(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getParent(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), llvm::MachineOperand::getSubReg(), I, llvm::MachineOperand::isDead(), llvm::MachineOperand::isDebug(), llvm::MachineOperand::isDef(), llvm::MachineOperand::isEarlyClobber(), llvm::MachineOperand::isImm(), llvm::MachineOperand::isImplicit(), llvm::MachineOperand::isInternalRead(), llvm::MachineOperand::isKill(), llvm::TargetRegisterInfo::isPhysicalRegister(), llvm::MachineOperand::isReg(), llvm::MachineOperand::isUndef(), llvm_unreachable, MI, MRI, llvm::MachineInstr::operands(), Reg, and llvm::MachineInstr::setDesc().

Member Function Documentation

getName()

static const char* llvm::AMDGPUInstructionSelector::getName ( )

static

Referenced by AMDGPUInstructionSelector().

select()

bool AMDGPUInstructionSelector::select ( MachineInstr &  I, CodeGenCoverage &  CoverageInfo  ) const

overridevirtual

Select the (possibly generic) instruction I to only use target-specific opcodes.

It is OK to insert multiple instructions, but they cannot be generic pre-isel instructions.

Returns

whether selection succeeded.

Precondition

I.getParent() && I.getParent()->getParent()

Postcondition

if returns true: for I in all mutated/inserted instructions: !isPreISelGenericOpcode(I.getOpcode())

Implements llvm::InstructionSelector.

Definition at line 619 of file AMDGPUInstructionSelector.cpp.

References llvm::MachineInstr::getOpcode(), llvm::MachineInstr::isCopy(), and llvm::isPreISelGenericOpcode().

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The documentation for this class was generated from the following files:

• lib/Target/AMDGPU/AMDGPUInstructionSelector.h
• lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp