35 #define DEBUG_TYPE "asm-printer" 37 #define PRINT_ALIAS_INSTR 38 #include "ARMGenAsmWriter.inc" 45 assert((imm & ~0x1f) == 0 &&
"Invalid shift encoding");
54 unsigned ShImm,
bool UseMarkup) {
129 O <<
", " <<
markup(
"<imm:") <<
"#" 137 case ARM::t2STMDB_UPD:
142 if (Opcode == ARM::t2STMDB_UPD)
151 case ARM::STR_PRE_IMM:
166 case ARM::t2LDMIA_UPD:
171 if (Opcode == ARM::t2LDMIA_UPD)
180 case ARM::LDR_POST_IMM:
194 case ARM::VSTMSDB_UPD:
195 case ARM::VSTMDDB_UPD:
197 O <<
'\t' <<
"vpush";
207 case ARM::VLDMSIA_UPD:
208 case ARM::VLDMDIA_UPD:
220 bool Writeback =
true;
251 bool isStore = Opcode == ARM::STREXD || Opcode == ARM::STLEXD;
305 }
else if (Op.
isImm()) {
308 assert(Op.
isExpr() &&
"unknown operand kind in printOperand");
310 switch (Expr->getKind()) {
313 Expr->print(O, &
MAI);
320 int64_t TargetAddress;
323 Expr->print(O, &
MAI);
326 O.
write_hex(static_cast<uint32_t>(TargetAddress));
333 Expr->print(O, &
MAI);
348 O <<
markup(
"<mem:") <<
"[pc, ";
350 int32_t OffImm = (int32_t)MO1.
getImm();
351 bool isSub = OffImm < 0;
354 if (OffImm == INT32_MIN)
413 O <<
markup(
"<mem:") <<
"[";
418 O <<
", " <<
markup(
"<imm:") <<
"#" 440 O <<
markup(
"<mem:") <<
"[";
452 O <<
markup(
"<mem:") <<
"[";
487 O <<
markup(
"<imm:") <<
'#' 506 bool AlwaysPrintImm0) {
511 O <<
markup(
"<mem:") <<
'[';
525 if (AlwaysPrintImm0 || ImmOffs || (op ==
ARM_AM::sub)) {
532 template <
bool AlwaysPr
intImm0>
544 "unexpected idxmode");
562 O <<
markup(
"<imm:") <<
'#' 571 unsigned Imm = MO.
getImm();
572 O <<
markup(
"<imm:") <<
'#' << ((Imm & 256) ?
"" :
"-") << (Imm & 0xff)
582 O << (MO2.
getImm() ?
"" :
"-");
590 unsigned Imm = MO.
getImm();
591 O <<
markup(
"<imm:") <<
'#' << ((Imm & 256) ?
"" :
"-") << ((Imm & 0xff) << 2)
603 template <
bool AlwaysPr
intImm0>
615 O <<
markup(
"<mem:") <<
"[";
620 if (AlwaysPrintImm0 || ImmOffs || Op ==
ARM_AM::sub) {
622 << ImmOffs * 4 <<
markup(
">");
627 template <
bool AlwaysPr
intImm0>
639 O <<
markup(
"<mem:") <<
"[";
644 if (AlwaysPrintImm0 || ImmOffs || Op ==
ARM_AM::sub) {
661 O <<
markup(
"<mem:") <<
"[";
664 O <<
":" << (MO2.
getImm() << 3);
673 O <<
markup(
"<mem:") <<
"[";
699 assert(MO.
isImm() &&
"Not a valid bf_inv_mask_imm value!");
701 <<
'#' << width <<
markup(
">");
729 bool isASR = (ShiftOp & (1 << 5)) != 0;
730 unsigned Amt = ShiftOp & 0x1f;
732 O <<
", asr " <<
markup(
"<imm:") <<
"#" << (Amt == 0 ? 32 : Amt)
735 O <<
", lsl " <<
markup(
"<imm:") <<
"#" << Amt <<
markup(
">");
745 assert(Imm > 0 && Imm < 32 &&
"Invalid PKH shift immediate value!");
746 O <<
", lsl " <<
markup(
"<imm:") <<
"#" << Imm <<
markup(
">");
756 assert(Imm > 0 && Imm <= 32 &&
"Invalid PKH shift immediate value!");
757 O <<
", asr " <<
markup(
"<imm:") <<
"#" << Imm <<
markup(
">");
807 for (
int i = 2; i >= 0; --i)
808 if (IFlags & (1 << i))
820 if (FeatureBits[ARM::FeatureMClass]) {
822 unsigned SYSm = Op.
getImm() & 0xFFF;
826 if (Opcode == ARM::t2MSR_M && FeatureBits[ARM::FeatureDSP]) {
828 if (TheReg && TheReg->isInRequiredFeatures({ARM::FeatureDSP})) {
836 if (Opcode == ARM::t2MSR_M && FeatureBits [ARM::HasV7Ops]) {
859 unsigned SpecRegRBit = Op.
getImm() >> 4;
862 if (!SpecRegRBit && (Mask == 8 || Mask == 4 || Mask == 12)) {
901 auto TheReg = ARMBankedReg::lookupBankedRegByEncoding(Banked);
902 assert(TheReg &&
"invalid banked register operand");
903 std::string
Name = TheReg->Name;
905 uint32_t isSPSR = (Banked & 0x20) >> 5;
907 Name.replace(0, 4,
"SPSR");
916 if ((
unsigned)CC == 15)
935 "Expect ARM CPSR register!");
969 template <
unsigned scale>
983 if (OffImm == INT32_MIN)
986 O <<
"#-" << -OffImm;
1013 unsigned CondBit0 = Firstcond & 1;
1015 assert(NumTZ <= 3 &&
"Invalid IT mask!");
1016 for (
unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) {
1017 bool T = ((Mask >> Pos) & 1) == CondBit0;
1036 O <<
markup(
"<mem:") <<
"[";
1038 if (
unsigned RegNum = MO2.
getReg()) {
1058 O <<
markup(
"<mem:") <<
"[";
1060 if (
unsigned ImmOffs = MO2.
getImm()) {
1108 assert(MO2.
isImm() &&
"Not a valid t2_so_reg value!");
1113 template <
bool AlwaysPr
intImm0>
1125 O <<
markup(
"<mem:") <<
"[";
1128 int32_t OffImm = (int32_t)MO2.
getImm();
1129 bool isSub = OffImm < 0;
1131 if (OffImm == INT32_MIN)
1135 }
else if (AlwaysPrintImm0 || OffImm > 0) {
1141 template <
bool AlwaysPr
intImm0>
1149 O <<
markup(
"<mem:") <<
"[";
1152 int32_t OffImm = (int32_t)MO2.
getImm();
1153 bool isSub = OffImm < 0;
1155 if (OffImm == INT32_MIN)
1158 O <<
", " <<
markup(
"<imm:") <<
"#-" << -OffImm <<
markup(
">");
1159 }
else if (AlwaysPrintImm0 || OffImm > 0) {
1160 O <<
", " <<
markup(
"<imm:") <<
"#" << OffImm <<
markup(
">");
1165 template <
bool AlwaysPr
intImm0>
1178 O <<
markup(
"<mem:") <<
"[";
1181 int32_t OffImm = (int32_t)MO2.
getImm();
1182 bool isSub = OffImm < 0;
1184 assert(((OffImm & 0x3) == 0) &&
"Not a valid immediate!");
1187 if (OffImm == INT32_MIN)
1190 O <<
", " <<
markup(
"<imm:") <<
"#-" << -OffImm <<
markup(
">");
1191 }
else if (AlwaysPrintImm0 || OffImm > 0) {
1192 O <<
", " <<
markup(
"<imm:") <<
"#" << OffImm <<
markup(
">");
1203 O <<
markup(
"<mem:") <<
"[";
1216 int32_t OffImm = (int32_t)MO1.
getImm();
1217 O <<
", " <<
markup(
"<imm:");
1218 if (OffImm == INT32_MIN)
1220 else if (OffImm < 0)
1221 O <<
"#-" << -OffImm;
1231 int32_t OffImm = (int32_t)MO1.
getImm();
1233 assert(((OffImm & 0x3) == 0) &&
"Not a valid immediate!");
1235 O <<
", " <<
markup(
"<imm:");
1236 if (OffImm == INT32_MIN)
1238 else if (OffImm < 0)
1239 O <<
"#-" << -OffImm;
1253 O <<
markup(
"<mem:") <<
"[";
1256 assert(MO2.
getReg() &&
"Invalid so_reg load / store address!");
1260 unsigned ShAmt = MO3.
getImm();
1262 assert(ShAmt <= 3 &&
"Not a valid Thumb2 addressing mode!");
1263 O <<
", lsl " <<
markup(
"<imm:") <<
"#" << ShAmt <<
markup(
">");
1282 O <<
markup(
"<imm:") <<
"#0x";
1300 assert(Imm <= 3 &&
"illegal ror immediate!");
1301 O <<
", ror " <<
markup(
"<imm:") <<
"#" << 8 * Imm <<
markup(
">");
1314 unsigned Rot = (Op.
getImm() & 0xF00) >> 7;
1316 bool PrintUnsigned =
false;
1324 PrintUnsigned =
true;
1331 O <<
"#" <<
markup(
"<imm:");
1333 O << static_cast<uint32_t>(Rotated);
1564 template<
int64_t Angle,
int64_t Remainder>
1569 O <<
"#" << (Val * Angle) + Remainder;
void printVectorListTwoAllLanes(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printThumbAddrModeImm5S1Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printAddrMode3OffsetOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printNoHashImmediate(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
virtual bool printAliasInstr(const MCInst *MI, const MCSubtargetInfo &STI, raw_ostream &O)
This class represents lattice values for constants.
void printVectorListThreeAllLanes(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printT2AddrModeImm8Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printAddrModeTBB(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printThumbAddrModeImm5S2Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
unsigned getAM2IdxMode(unsigned AM2Opc)
void printBankedRegOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
const char * getAMSubModeStr(AMSubMode Mode)
void printBitfieldInvMaskImmOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printT2AddrModeImm8s4Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
std::size_t countLeadingZeros(T Val, ZeroBehavior ZB=ZB_Width)
Count number of 0's from the most significant bit to the least stopping at the first 1...
uint64_t decodeNEONModImm(unsigned ModImm, unsigned &EltBits)
decodeNEONModImm - Decode a NEON modified immediate value into the element value and the element size...
void printAddrMode7Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printThumbLdrLabelOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
const MClassSysReg * lookupMClassSysRegBy8bitSYSmValue(unsigned SYSm)
void printPKHASRShiftImm(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
const char * getShiftOpcStr(ShiftOpc Op)
static unsigned translateShiftImm(unsigned imm)
translateShiftImm - Convert shift immediate from 0-31 to 1-32 for printing.
void printAddrMode5FP16Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printAM2PreOrOffsetIndexOp(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
amdgpu Simplify well known AMD library false Value Value const Twine & Name
void printThumbAddrModeSPOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
ShiftOpc getAM2ShiftOpc(unsigned AM2Opc)
static MCOperand createReg(unsigned Reg)
void printT2AddrModeImm8s4OffsetOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
bool contains(unsigned Reg) const
contains - Return true if the specified register is included in this register class.
const FeatureBitset & getFeatureBits() const
void printVectorListThree(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printVectorListTwoSpacedAllLanes(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
AMSubMode getAM4SubMode(unsigned Mode)
void printT2AddrModeImm8OffsetOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printLdStmModeOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Base class for the full range of assembler expressions which are needed for parsing.
void printFBits32(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printCoprocOptionImm(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
unsigned getReg() const
Returns the register number.
void printCPSIFlag(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
unsigned char getAM3Offset(unsigned AM3Opc)
unsigned getAM3IdxMode(unsigned AM3Opc)
raw_ostream & write_hex(unsigned long long N)
Output N in hexadecimal, without any prefix or padding.
void printInstruction(const MCInst *MI, const MCSubtargetInfo &STI, raw_ostream &O)
format_object< int64_t > formatImm(int64_t Value) const
Utility function to print immediates in decimal or hex.
static bool isStore(int Opcode)
float getFPImmFloat(unsigned Imm)
void printSBitModifierOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
const MCExpr * getExpr() const
static const char * getRegisterName(unsigned RegNo)
MCRegisterClass - Base class of TargetRegisterClass.
Instances of this class represent a single low-level machine instruction.
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
AddrOpc getAM2Op(unsigned AM2Opc)
This class is intended to be used as a base class for asm properties and features specific to the tar...
unsigned char getAM5Offset(unsigned AM5Opc)
void printThumbSRImm(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printPostIdxImm8s4Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printMandatoryPredicateOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
AddrOpc getAM3Op(unsigned AM3Opc)
void print(raw_ostream &OS, const MCAsmInfo *MAI, bool InParens=false) const
unsigned const MachineRegisterInfo * MRI
Container class for subtarget features.
std::size_t countTrailingZeros(T Val, ZeroBehavior ZB=ZB_Width)
Count number of 0's from the least significant bit to the most stopping at the first 1...
static const char * InstSyncBOptToString(unsigned val)
unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx, const MCRegisterClass *RC) const
Return a super-register of the specified register Reg so its sub-register of index SubIdx is Reg...
void printGPRPairOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
StringRef markup(StringRef s) const
Utility functions to make adding mark ups simpler.
void printRegisterList(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
unsigned getSORegOffset(unsigned Op)
void printComplexRotationOp(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
This is an important base class in LLVM.
void printThumbAddrModeImm5S4Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Interface to description of machine instruction set.
unsigned getSubReg(unsigned Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo...
const MClassSysReg * lookupMClassSysRegAPSRNonDeprecated(unsigned SYSm)
static const char * TraceSyncBOptToString(unsigned val)
void printVectorListOne(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printVectorListTwo(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printAddrModeTBH(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printVectorIndex(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
static uint64_t scale(uint64_t Num, uint32_t N, uint32_t D)
unsigned getNumOperands() const
void printAddrMode6Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printRotImmOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printMemBOption(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
const MClassSysReg * lookupMClassSysRegBy12bitSYSmValue(unsigned SYSm)
void printAddrMode5Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printSORegRegOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
unsigned rotr32(unsigned Val, unsigned Amt)
rotr32 - Rotate a 32-bit unsigned value right by a specified # bits.
void printThumbAddrModeRROperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printAdrLabelOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printPKHLSLShiftImm(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printCImmediate(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
void printVectorListFourSpacedAllLanes(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
static const char * ARMCondCodeToString(ARMCC::CondCodes CC)
static const char * IModToString(unsigned val)
const char * getAddrOpcStr(AddrOpc Op)
void printPostIdxRegOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printVectorListFourSpaced(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void setOpcode(unsigned Op)
int getSOImmVal(unsigned Arg)
getSOImmVal - Given a 32-bit immediate, if it is something that can fit into an shifter_operand immed...
void printFBits16(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printVectorListTwoSpaced(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printTraceSyncBOption(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printVectorListThreeSpaced(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
const MCOperand & getOperand(unsigned i) const
ARMInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI)
unsigned getAM2Offset(unsigned AM2Opc)
void printPCLabel(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
AddrOpc getAM5FP16Op(unsigned AM5Opc)
void printAddrMode6OffsetOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
static void printRegImmShift(raw_ostream &O, ARM_AM::ShiftOpc ShOpc, unsigned ShImm, bool UseMarkup)
Prints the shift value with an immediate value.
static const char * MemBOptToString(unsigned val, bool HasV8)
bool evaluateAsAbsolute(int64_t &Res, const MCAsmLayout &Layout, const SectionAddrMap &Addrs) const
Try to evaluate the expression to an absolute value.
static const char * IFlagsToString(unsigned val)
ShiftOpc getSORegShOp(unsigned Op)
void printVectorListFourAllLanes(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printThumbAddrModeImm5SOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O, unsigned Scale)
bool UseMarkup
True if we are printing marked up assembly.
This is an instance of a target assembly language printer that converts an MCInst to valid target ass...
uint16_t getEncodingValue(unsigned RegNo) const
Returns the encoding for RegNo.
void printT2SOOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
void printAddrMode2Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printT2AddrModeImm0_1020s4Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Generic base class for all target subtargets.
void printVectorListFour(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printT2AddrModeSoRegOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printPostIdxImm8Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printVectorListOneAllLanes(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printImmPlusOneOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
void printAddrMode2OffsetOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printNEONModImmOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printSetendOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printAnnotation(raw_ostream &OS, StringRef Annot)
Utility function for printing annotations.
void printMSRMaskOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printAddrModeImm12Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
This class implements an extremely fast bulk output stream that can only output to a stream...
void printVectorListThreeSpacedAllLanes(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void addOperand(const MCOperand &Op)
StringRef - Represent a constant reference to a string, i.e.
void printPImmediate(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
unsigned char getAM5FP16Offset(unsigned AM5Opc)
void printThumbITMask(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
AddrOpc getAM5Op(unsigned AM5Opc)
void printShiftImmOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
unsigned getOpcode() const
void printAM3PreOrOffsetIndexOp(const MCInst *MI, unsigned Op, raw_ostream &O, bool AlwaysPrintImm0)
Instances of this class represent operands of the MCInst class.
void printAddrMode3Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printSORegImmOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot, const MCSubtargetInfo &STI) override
Print the specified MCInst to the specified raw_ostream.
void printThumbS4ImmOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printPredicateOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printRegName(raw_ostream &OS, unsigned RegNo) const override
Print the assembler register name.
void printInstSyncBOption(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printFPImmOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
const MCRegisterClass & getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
void printCPSIMod(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
const MCRegisterInfo & MRI
void printModImmOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)