Intrinsics.h File Reference

#include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/None.h"
#include "llvm/ADT/Optional.h"
#include <string>
#include "llvm/IR/IntrinsicEnums.inc"

Include dependency graph for Intrinsics.h:

Go to the source code of this file.

Classes
struct	llvm::Intrinsic::IITDescriptor
	This is a type descriptor which explains the type requirements of an intrinsic. More...

Namespaces
	llvm
	This class represents lattice values for constants.
	llvm::Intrinsic
	This namespace contains an enum with a value for every intrinsic/builtin function known by LLVM.

Macros
#define	GET_INTRINSIC_ENUM_VALUES

Enumerations
enum	llvm::Intrinsic::ID : unsigned {   llvm::Intrinsic::not_intrinsic = 0, llvm::Intrinsic::addressofreturnaddress, llvm::Intrinsic::adjust_trampoline, llvm::Intrinsic::annotation,   llvm::Intrinsic::assume, llvm::Intrinsic::bitreverse, llvm::Intrinsic::bswap, llvm::Intrinsic::canonicalize,   llvm::Intrinsic::ceil, llvm::Intrinsic::clear_cache, llvm::Intrinsic::codeview_annotation, llvm::Intrinsic::convert_from_fp16,   llvm::Intrinsic::convert_to_fp16, llvm::Intrinsic::copysign, llvm::Intrinsic::coro_alloc, llvm::Intrinsic::coro_begin,   llvm::Intrinsic::coro_destroy, llvm::Intrinsic::coro_done, llvm::Intrinsic::coro_end, llvm::Intrinsic::coro_frame,   llvm::Intrinsic::coro_free, llvm::Intrinsic::coro_id, llvm::Intrinsic::coro_noop, llvm::Intrinsic::coro_param,   llvm::Intrinsic::coro_promise, llvm::Intrinsic::coro_resume, llvm::Intrinsic::coro_save, llvm::Intrinsic::coro_size,   llvm::Intrinsic::coro_subfn_addr, llvm::Intrinsic::coro_suspend, llvm::Intrinsic::cos, llvm::Intrinsic::ctlz,   llvm::Intrinsic::ctpop, llvm::Intrinsic::cttz, llvm::Intrinsic::dbg_addr, llvm::Intrinsic::dbg_declare,   llvm::Intrinsic::dbg_label, llvm::Intrinsic::dbg_value, llvm::Intrinsic::debugtrap, llvm::Intrinsic::donothing,   llvm::Intrinsic::eh_dwarf_cfa, llvm::Intrinsic::eh_exceptioncode, llvm::Intrinsic::eh_exceptionpointer, llvm::Intrinsic::eh_recoverfp,   llvm::Intrinsic::eh_return_i32, llvm::Intrinsic::eh_return_i64, llvm::Intrinsic::eh_sjlj_callsite, llvm::Intrinsic::eh_sjlj_functioncontext,   llvm::Intrinsic::eh_sjlj_longjmp, llvm::Intrinsic::eh_sjlj_lsda, llvm::Intrinsic::eh_sjlj_setjmp, llvm::Intrinsic::eh_sjlj_setup_dispatch,   llvm::Intrinsic::eh_typeid_for, llvm::Intrinsic::eh_unwind_init, llvm::Intrinsic::exp, llvm::Intrinsic::exp2,   llvm::Intrinsic::expect, llvm::Intrinsic::experimental_constrained_ceil, llvm::Intrinsic::experimental_constrained_cos, llvm::Intrinsic::experimental_constrained_exp,   llvm::Intrinsic::experimental_constrained_exp2, llvm::Intrinsic::experimental_constrained_fadd, llvm::Intrinsic::experimental_constrained_fdiv, llvm::Intrinsic::experimental_constrained_floor,   llvm::Intrinsic::experimental_constrained_fma, llvm::Intrinsic::experimental_constrained_fmul, llvm::Intrinsic::experimental_constrained_frem, llvm::Intrinsic::experimental_constrained_fsub,   llvm::Intrinsic::experimental_constrained_log, llvm::Intrinsic::experimental_constrained_log10, llvm::Intrinsic::experimental_constrained_log2, llvm::Intrinsic::experimental_constrained_maxnum,   llvm::Intrinsic::experimental_constrained_minnum, llvm::Intrinsic::experimental_constrained_nearbyint, llvm::Intrinsic::experimental_constrained_pow, llvm::Intrinsic::experimental_constrained_powi,   llvm::Intrinsic::experimental_constrained_rint, llvm::Intrinsic::experimental_constrained_round, llvm::Intrinsic::experimental_constrained_sin, llvm::Intrinsic::experimental_constrained_sqrt,   llvm::Intrinsic::experimental_constrained_trunc, llvm::Intrinsic::experimental_deoptimize, llvm::Intrinsic::experimental_gc_relocate, llvm::Intrinsic::experimental_gc_result,   llvm::Intrinsic::experimental_gc_statepoint, llvm::Intrinsic::experimental_guard, llvm::Intrinsic::experimental_patchpoint_i64, llvm::Intrinsic::experimental_patchpoint_void,   llvm::Intrinsic::experimental_stackmap, llvm::Intrinsic::experimental_vector_reduce_add, llvm::Intrinsic::experimental_vector_reduce_and, llvm::Intrinsic::experimental_vector_reduce_fadd,   llvm::Intrinsic::experimental_vector_reduce_fmax, llvm::Intrinsic::experimental_vector_reduce_fmin, llvm::Intrinsic::experimental_vector_reduce_fmul, llvm::Intrinsic::experimental_vector_reduce_mul,   llvm::Intrinsic::experimental_vector_reduce_or, llvm::Intrinsic::experimental_vector_reduce_smax, llvm::Intrinsic::experimental_vector_reduce_smin, llvm::Intrinsic::experimental_vector_reduce_umax,   llvm::Intrinsic::experimental_vector_reduce_umin, llvm::Intrinsic::experimental_vector_reduce_xor, llvm::Intrinsic::experimental_widenable_condition, llvm::Intrinsic::fabs,   llvm::Intrinsic::floor, llvm::Intrinsic::flt_rounds, llvm::Intrinsic::fma, llvm::Intrinsic::fmuladd,   llvm::Intrinsic::frameaddress, llvm::Intrinsic::fshl, llvm::Intrinsic::fshr, llvm::Intrinsic::gcread,   llvm::Intrinsic::gcroot, llvm::Intrinsic::gcwrite, llvm::Intrinsic::get_dynamic_area_offset, llvm::Intrinsic::icall_branch_funnel,   llvm::Intrinsic::init_trampoline, llvm::Intrinsic::instrprof_increment, llvm::Intrinsic::instrprof_increment_step, llvm::Intrinsic::instrprof_value_profile,   llvm::Intrinsic::invariant_end, llvm::Intrinsic::invariant_start, llvm::Intrinsic::is_constant, llvm::Intrinsic::launder_invariant_group,   llvm::Intrinsic::lifetime_end, llvm::Intrinsic::lifetime_start, llvm::Intrinsic::load_relative, llvm::Intrinsic::localaddress,   llvm::Intrinsic::localescape, llvm::Intrinsic::localrecover, llvm::Intrinsic::log, llvm::Intrinsic::log10,   llvm::Intrinsic::log2, llvm::Intrinsic::longjmp, llvm::Intrinsic::masked_compressstore, llvm::Intrinsic::masked_expandload,   llvm::Intrinsic::masked_gather, llvm::Intrinsic::masked_load, llvm::Intrinsic::masked_scatter, llvm::Intrinsic::masked_store,   llvm::Intrinsic::maximum, llvm::Intrinsic::maxnum, llvm::Intrinsic::memcpy, llvm::Intrinsic::memcpy_element_unordered_atomic,   llvm::Intrinsic::memmove, llvm::Intrinsic::memmove_element_unordered_atomic, llvm::Intrinsic::memset, llvm::Intrinsic::memset_element_unordered_atomic,   llvm::Intrinsic::minimum, llvm::Intrinsic::minnum, llvm::Intrinsic::nearbyint, llvm::Intrinsic::objc_arc_annotation_bottomup_bbend,   llvm::Intrinsic::objc_arc_annotation_bottomup_bbstart, llvm::Intrinsic::objc_arc_annotation_topdown_bbend, llvm::Intrinsic::objc_arc_annotation_topdown_bbstart, llvm::Intrinsic::objc_autorelease,   llvm::Intrinsic::objc_autoreleasePoolPop, llvm::Intrinsic::objc_autoreleasePoolPush, llvm::Intrinsic::objc_autoreleaseReturnValue, llvm::Intrinsic::objc_clang_arc_use,   llvm::Intrinsic::objc_copyWeak, llvm::Intrinsic::objc_destroyWeak, llvm::Intrinsic::objc_initWeak, llvm::Intrinsic::objc_loadWeak,   llvm::Intrinsic::objc_loadWeakRetained, llvm::Intrinsic::objc_moveWeak, llvm::Intrinsic::objc_release, llvm::Intrinsic::objc_retain,   llvm::Intrinsic::objc_retain_autorelease, llvm::Intrinsic::objc_retainAutorelease, llvm::Intrinsic::objc_retainAutoreleaseReturnValue, llvm::Intrinsic::objc_retainAutoreleasedReturnValue,   llvm::Intrinsic::objc_retainBlock, llvm::Intrinsic::objc_retainedObject, llvm::Intrinsic::objc_storeStrong, llvm::Intrinsic::objc_storeWeak,   llvm::Intrinsic::objc_sync_enter, llvm::Intrinsic::objc_sync_exit, llvm::Intrinsic::objc_unretainedObject, llvm::Intrinsic::objc_unretainedPointer,   llvm::Intrinsic::objc_unsafeClaimAutoreleasedReturnValue, llvm::Intrinsic::objectsize, llvm::Intrinsic::pcmarker, llvm::Intrinsic::pow,   llvm::Intrinsic::powi, llvm::Intrinsic::prefetch, llvm::Intrinsic::ptr_annotation, llvm::Intrinsic::read_register,   llvm::Intrinsic::readcyclecounter, llvm::Intrinsic::returnaddress, llvm::Intrinsic::rint, llvm::Intrinsic::round,   llvm::Intrinsic::sadd_sat, llvm::Intrinsic::sadd_with_overflow, llvm::Intrinsic::setjmp, llvm::Intrinsic::sideeffect,   llvm::Intrinsic::siglongjmp, llvm::Intrinsic::sigsetjmp, llvm::Intrinsic::sin, llvm::Intrinsic::smul_fix,   llvm::Intrinsic::smul_with_overflow, llvm::Intrinsic::sponentry, llvm::Intrinsic::sqrt, llvm::Intrinsic::ssa_copy,   llvm::Intrinsic::ssub_sat, llvm::Intrinsic::ssub_with_overflow, llvm::Intrinsic::stackguard, llvm::Intrinsic::stackprotector,   llvm::Intrinsic::stackrestore, llvm::Intrinsic::stacksave, llvm::Intrinsic::strip_invariant_group, llvm::Intrinsic::thread_pointer,   llvm::Intrinsic::trap, llvm::Intrinsic::trunc, llvm::Intrinsic::type_checked_load, llvm::Intrinsic::type_test,   llvm::Intrinsic::uadd_sat, llvm::Intrinsic::uadd_with_overflow, llvm::Intrinsic::umul_with_overflow, llvm::Intrinsic::usub_sat,   llvm::Intrinsic::usub_with_overflow, llvm::Intrinsic::vacopy, llvm::Intrinsic::vaend, llvm::Intrinsic::vastart,   llvm::Intrinsic::var_annotation, llvm::Intrinsic::write_register, llvm::Intrinsic::xray_customevent, llvm::Intrinsic::xray_typedevent,   llvm::Intrinsic::aarch64_clrex, llvm::Intrinsic::aarch64_crc32b, llvm::Intrinsic::aarch64_crc32cb, llvm::Intrinsic::aarch64_crc32ch,   llvm::Intrinsic::aarch64_crc32cw, llvm::Intrinsic::aarch64_crc32cx, llvm::Intrinsic::aarch64_crc32h, llvm::Intrinsic::aarch64_crc32w,   llvm::Intrinsic::aarch64_crc32x, llvm::Intrinsic::aarch64_crypto_aesd, llvm::Intrinsic::aarch64_crypto_aese, llvm::Intrinsic::aarch64_crypto_aesimc,   llvm::Intrinsic::aarch64_crypto_aesmc, llvm::Intrinsic::aarch64_crypto_sha1c, llvm::Intrinsic::aarch64_crypto_sha1h, llvm::Intrinsic::aarch64_crypto_sha1m,   llvm::Intrinsic::aarch64_crypto_sha1p, llvm::Intrinsic::aarch64_crypto_sha1su0, llvm::Intrinsic::aarch64_crypto_sha1su1, llvm::Intrinsic::aarch64_crypto_sha256h,   llvm::Intrinsic::aarch64_crypto_sha256h2, llvm::Intrinsic::aarch64_crypto_sha256su0, llvm::Intrinsic::aarch64_crypto_sha256su1, llvm::Intrinsic::aarch64_dmb,   llvm::Intrinsic::aarch64_dsb, llvm::Intrinsic::aarch64_get_fpcr, llvm::Intrinsic::aarch64_hint, llvm::Intrinsic::aarch64_isb,   llvm::Intrinsic::aarch64_ldaxp, llvm::Intrinsic::aarch64_ldaxr, llvm::Intrinsic::aarch64_ldxp, llvm::Intrinsic::aarch64_ldxr,   llvm::Intrinsic::aarch64_neon_abs, llvm::Intrinsic::aarch64_neon_addhn, llvm::Intrinsic::aarch64_neon_addp, llvm::Intrinsic::aarch64_neon_cls,   llvm::Intrinsic::aarch64_neon_fabd, llvm::Intrinsic::aarch64_neon_facge, llvm::Intrinsic::aarch64_neon_facgt, llvm::Intrinsic::aarch64_neon_faddv,   llvm::Intrinsic::aarch64_neon_fcvtas, llvm::Intrinsic::aarch64_neon_fcvtau, llvm::Intrinsic::aarch64_neon_fcvtms, llvm::Intrinsic::aarch64_neon_fcvtmu,   llvm::Intrinsic::aarch64_neon_fcvtns, llvm::Intrinsic::aarch64_neon_fcvtnu, llvm::Intrinsic::aarch64_neon_fcvtps, llvm::Intrinsic::aarch64_neon_fcvtpu,   llvm::Intrinsic::aarch64_neon_fcvtxn, llvm::Intrinsic::aarch64_neon_fcvtzs, llvm::Intrinsic::aarch64_neon_fcvtzu, llvm::Intrinsic::aarch64_neon_fmax,   llvm::Intrinsic::aarch64_neon_fmaxnm, llvm::Intrinsic::aarch64_neon_fmaxnmp, llvm::Intrinsic::aarch64_neon_fmaxnmv, llvm::Intrinsic::aarch64_neon_fmaxp,   llvm::Intrinsic::aarch64_neon_fmaxv, llvm::Intrinsic::aarch64_neon_fmin, llvm::Intrinsic::aarch64_neon_fminnm, llvm::Intrinsic::aarch64_neon_fminnmp,   llvm::Intrinsic::aarch64_neon_fminnmv, llvm::Intrinsic::aarch64_neon_fminp, llvm::Intrinsic::aarch64_neon_fminv, llvm::Intrinsic::aarch64_neon_fmlal,   llvm::Intrinsic::aarch64_neon_fmlal2, llvm::Intrinsic::aarch64_neon_fmlsl, llvm::Intrinsic::aarch64_neon_fmlsl2, llvm::Intrinsic::aarch64_neon_fmulx,   llvm::Intrinsic::aarch64_neon_frecpe, llvm::Intrinsic::aarch64_neon_frecps, llvm::Intrinsic::aarch64_neon_frecpx, llvm::Intrinsic::aarch64_neon_frintn,   llvm::Intrinsic::aarch64_neon_frsqrte, llvm::Intrinsic::aarch64_neon_frsqrts, llvm::Intrinsic::aarch64_neon_ld1x2, llvm::Intrinsic::aarch64_neon_ld1x3,   llvm::Intrinsic::aarch64_neon_ld1x4, llvm::Intrinsic::aarch64_neon_ld2, llvm::Intrinsic::aarch64_neon_ld2lane, llvm::Intrinsic::aarch64_neon_ld2r,   llvm::Intrinsic::aarch64_neon_ld3, llvm::Intrinsic::aarch64_neon_ld3lane, llvm::Intrinsic::aarch64_neon_ld3r, llvm::Intrinsic::aarch64_neon_ld4,   llvm::Intrinsic::aarch64_neon_ld4lane, llvm::Intrinsic::aarch64_neon_ld4r, llvm::Intrinsic::aarch64_neon_pmul, llvm::Intrinsic::aarch64_neon_pmull,   llvm::Intrinsic::aarch64_neon_pmull64, llvm::Intrinsic::aarch64_neon_raddhn, llvm::Intrinsic::aarch64_neon_rbit, llvm::Intrinsic::aarch64_neon_rshrn,   llvm::Intrinsic::aarch64_neon_rsubhn, llvm::Intrinsic::aarch64_neon_sabd, llvm::Intrinsic::aarch64_neon_saddlp, llvm::Intrinsic::aarch64_neon_saddlv,   llvm::Intrinsic::aarch64_neon_saddv, llvm::Intrinsic::aarch64_neon_scalar_sqxtn, llvm::Intrinsic::aarch64_neon_scalar_sqxtun, llvm::Intrinsic::aarch64_neon_scalar_uqxtn,   llvm::Intrinsic::aarch64_neon_sdot, llvm::Intrinsic::aarch64_neon_shadd, llvm::Intrinsic::aarch64_neon_shll, llvm::Intrinsic::aarch64_neon_shsub,   llvm::Intrinsic::aarch64_neon_smax, llvm::Intrinsic::aarch64_neon_smaxp, llvm::Intrinsic::aarch64_neon_smaxv, llvm::Intrinsic::aarch64_neon_smin,   llvm::Intrinsic::aarch64_neon_sminp, llvm::Intrinsic::aarch64_neon_sminv, llvm::Intrinsic::aarch64_neon_smull, llvm::Intrinsic::aarch64_neon_sqabs,   llvm::Intrinsic::aarch64_neon_sqadd, llvm::Intrinsic::aarch64_neon_sqdmulh, llvm::Intrinsic::aarch64_neon_sqdmull, llvm::Intrinsic::aarch64_neon_sqdmulls_scalar,   llvm::Intrinsic::aarch64_neon_sqneg, llvm::Intrinsic::aarch64_neon_sqrdmulh, llvm::Intrinsic::aarch64_neon_sqrshl, llvm::Intrinsic::aarch64_neon_sqrshrn,   llvm::Intrinsic::aarch64_neon_sqrshrun, llvm::Intrinsic::aarch64_neon_sqshl, llvm::Intrinsic::aarch64_neon_sqshlu, llvm::Intrinsic::aarch64_neon_sqshrn,   llvm::Intrinsic::aarch64_neon_sqshrun, llvm::Intrinsic::aarch64_neon_sqsub, llvm::Intrinsic::aarch64_neon_sqxtn, llvm::Intrinsic::aarch64_neon_sqxtun,   llvm::Intrinsic::aarch64_neon_srhadd, llvm::Intrinsic::aarch64_neon_srshl, llvm::Intrinsic::aarch64_neon_sshl, llvm::Intrinsic::aarch64_neon_sshll,   llvm::Intrinsic::aarch64_neon_st1x2, llvm::Intrinsic::aarch64_neon_st1x3, llvm::Intrinsic::aarch64_neon_st1x4, llvm::Intrinsic::aarch64_neon_st2,   llvm::Intrinsic::aarch64_neon_st2lane, llvm::Intrinsic::aarch64_neon_st3, llvm::Intrinsic::aarch64_neon_st3lane, llvm::Intrinsic::aarch64_neon_st4,   llvm::Intrinsic::aarch64_neon_st4lane, llvm::Intrinsic::aarch64_neon_subhn, llvm::Intrinsic::aarch64_neon_suqadd, llvm::Intrinsic::aarch64_neon_tbl1,   llvm::Intrinsic::aarch64_neon_tbl2, llvm::Intrinsic::aarch64_neon_tbl3, llvm::Intrinsic::aarch64_neon_tbl4, llvm::Intrinsic::aarch64_neon_tbx1,   llvm::Intrinsic::aarch64_neon_tbx2, llvm::Intrinsic::aarch64_neon_tbx3, llvm::Intrinsic::aarch64_neon_tbx4, llvm::Intrinsic::aarch64_neon_uabd,   llvm::Intrinsic::aarch64_neon_uaddlp, llvm::Intrinsic::aarch64_neon_uaddlv, llvm::Intrinsic::aarch64_neon_uaddv, llvm::Intrinsic::aarch64_neon_udot,   llvm::Intrinsic::aarch64_neon_uhadd, llvm::Intrinsic::aarch64_neon_uhsub, llvm::Intrinsic::aarch64_neon_umax, llvm::Intrinsic::aarch64_neon_umaxp,   llvm::Intrinsic::aarch64_neon_umaxv, llvm::Intrinsic::aarch64_neon_umin, llvm::Intrinsic::aarch64_neon_uminp, llvm::Intrinsic::aarch64_neon_uminv,   llvm::Intrinsic::aarch64_neon_umull, llvm::Intrinsic::aarch64_neon_uqadd, llvm::Intrinsic::aarch64_neon_uqrshl, llvm::Intrinsic::aarch64_neon_uqrshrn,   llvm::Intrinsic::aarch64_neon_uqshl, llvm::Intrinsic::aarch64_neon_uqshrn, llvm::Intrinsic::aarch64_neon_uqsub, llvm::Intrinsic::aarch64_neon_uqxtn,   llvm::Intrinsic::aarch64_neon_urecpe, llvm::Intrinsic::aarch64_neon_urhadd, llvm::Intrinsic::aarch64_neon_urshl, llvm::Intrinsic::aarch64_neon_ursqrte,   llvm::Intrinsic::aarch64_neon_ushl, llvm::Intrinsic::aarch64_neon_ushll, llvm::Intrinsic::aarch64_neon_usqadd, llvm::Intrinsic::aarch64_neon_vcopy_lane,   llvm::Intrinsic::aarch64_neon_vcvtfp2fxs, llvm::Intrinsic::aarch64_neon_vcvtfp2fxu, llvm::Intrinsic::aarch64_neon_vcvtfp2hf, llvm::Intrinsic::aarch64_neon_vcvtfxs2fp,   llvm::Intrinsic::aarch64_neon_vcvtfxu2fp, llvm::Intrinsic::aarch64_neon_vcvthf2fp, llvm::Intrinsic::aarch64_neon_vsli, llvm::Intrinsic::aarch64_neon_vsri,   llvm::Intrinsic::aarch64_sdiv, llvm::Intrinsic::aarch64_sisd_fabd, llvm::Intrinsic::aarch64_sisd_fcvtxn, llvm::Intrinsic::aarch64_space,   llvm::Intrinsic::aarch64_stlxp, llvm::Intrinsic::aarch64_stlxr, llvm::Intrinsic::aarch64_stxp, llvm::Intrinsic::aarch64_stxr,   llvm::Intrinsic::aarch64_udiv, llvm::Intrinsic::amdgcn_alignbit, llvm::Intrinsic::amdgcn_alignbyte, llvm::Intrinsic::amdgcn_atomic_dec,   llvm::Intrinsic::amdgcn_atomic_inc, llvm::Intrinsic::amdgcn_buffer_atomic_add, llvm::Intrinsic::amdgcn_buffer_atomic_and, llvm::Intrinsic::amdgcn_buffer_atomic_cmpswap,   llvm::Intrinsic::amdgcn_buffer_atomic_or, llvm::Intrinsic::amdgcn_buffer_atomic_smax, llvm::Intrinsic::amdgcn_buffer_atomic_smin, llvm::Intrinsic::amdgcn_buffer_atomic_sub,   llvm::Intrinsic::amdgcn_buffer_atomic_swap, llvm::Intrinsic::amdgcn_buffer_atomic_umax, llvm::Intrinsic::amdgcn_buffer_atomic_umin, llvm::Intrinsic::amdgcn_buffer_atomic_xor,   llvm::Intrinsic::amdgcn_buffer_load, llvm::Intrinsic::amdgcn_buffer_load_format, llvm::Intrinsic::amdgcn_buffer_store, llvm::Intrinsic::amdgcn_buffer_store_format,   llvm::Intrinsic::amdgcn_buffer_wbinvl1, llvm::Intrinsic::amdgcn_buffer_wbinvl1_sc, llvm::Intrinsic::amdgcn_buffer_wbinvl1_vol, llvm::Intrinsic::amdgcn_class,   llvm::Intrinsic::amdgcn_cos, llvm::Intrinsic::amdgcn_cubeid, llvm::Intrinsic::amdgcn_cubema, llvm::Intrinsic::amdgcn_cubesc,   llvm::Intrinsic::amdgcn_cubetc, llvm::Intrinsic::amdgcn_cvt_pk_i16, llvm::Intrinsic::amdgcn_cvt_pk_u16, llvm::Intrinsic::amdgcn_cvt_pk_u8_f32,   llvm::Intrinsic::amdgcn_cvt_pknorm_i16, llvm::Intrinsic::amdgcn_cvt_pknorm_u16, llvm::Intrinsic::amdgcn_cvt_pkrtz, llvm::Intrinsic::amdgcn_dispatch_id,   llvm::Intrinsic::amdgcn_dispatch_ptr, llvm::Intrinsic::amdgcn_div_fixup, llvm::Intrinsic::amdgcn_div_fmas, llvm::Intrinsic::amdgcn_div_scale,   llvm::Intrinsic::amdgcn_ds_bpermute, llvm::Intrinsic::amdgcn_ds_fadd, llvm::Intrinsic::amdgcn_ds_fmax, llvm::Intrinsic::amdgcn_ds_fmin,   llvm::Intrinsic::amdgcn_ds_ordered_add, llvm::Intrinsic::amdgcn_ds_ordered_swap, llvm::Intrinsic::amdgcn_ds_permute, llvm::Intrinsic::amdgcn_ds_swizzle,   llvm::Intrinsic::amdgcn_else, llvm::Intrinsic::amdgcn_end_cf, llvm::Intrinsic::amdgcn_exp, llvm::Intrinsic::amdgcn_exp_compr,   llvm::Intrinsic::amdgcn_fcmp, llvm::Intrinsic::amdgcn_fdiv_fast, llvm::Intrinsic::amdgcn_fdot2, llvm::Intrinsic::amdgcn_fmad_ftz,   llvm::Intrinsic::amdgcn_fmed3, llvm::Intrinsic::amdgcn_fmul_legacy, llvm::Intrinsic::amdgcn_fract, llvm::Intrinsic::amdgcn_frexp_exp,   llvm::Intrinsic::amdgcn_frexp_mant, llvm::Intrinsic::amdgcn_groupstaticsize, llvm::Intrinsic::amdgcn_icmp, llvm::Intrinsic::amdgcn_if,   llvm::Intrinsic::amdgcn_if_break, llvm::Intrinsic::amdgcn_image_atomic_add_1d, llvm::Intrinsic::amdgcn_image_atomic_add_1darray, llvm::Intrinsic::amdgcn_image_atomic_add_2d,   llvm::Intrinsic::amdgcn_image_atomic_add_2darray, llvm::Intrinsic::amdgcn_image_atomic_add_2darraymsaa, llvm::Intrinsic::amdgcn_image_atomic_add_2dmsaa, llvm::Intrinsic::amdgcn_image_atomic_add_3d,   llvm::Intrinsic::amdgcn_image_atomic_add_cube, llvm::Intrinsic::amdgcn_image_atomic_and_1d, llvm::Intrinsic::amdgcn_image_atomic_and_1darray, llvm::Intrinsic::amdgcn_image_atomic_and_2d,   llvm::Intrinsic::amdgcn_image_atomic_and_2darray, llvm::Intrinsic::amdgcn_image_atomic_and_2darraymsaa, llvm::Intrinsic::amdgcn_image_atomic_and_2dmsaa, llvm::Intrinsic::amdgcn_image_atomic_and_3d,   llvm::Intrinsic::amdgcn_image_atomic_and_cube, llvm::Intrinsic::amdgcn_image_atomic_cmpswap_1d, llvm::Intrinsic::amdgcn_image_atomic_cmpswap_1darray, llvm::Intrinsic::amdgcn_image_atomic_cmpswap_2d,   llvm::Intrinsic::amdgcn_image_atomic_cmpswap_2darray, llvm::Intrinsic::amdgcn_image_atomic_cmpswap_2darraymsaa, llvm::Intrinsic::amdgcn_image_atomic_cmpswap_2dmsaa, llvm::Intrinsic::amdgcn_image_atomic_cmpswap_3d,   llvm::Intrinsic::amdgcn_image_atomic_cmpswap_cube, llvm::Intrinsic::amdgcn_image_atomic_dec_1d, llvm::Intrinsic::amdgcn_image_atomic_dec_1darray, llvm::Intrinsic::amdgcn_image_atomic_dec_2d,   llvm::Intrinsic::amdgcn_image_atomic_dec_2darray, llvm::Intrinsic::amdgcn_image_atomic_dec_2darraymsaa, llvm::Intrinsic::amdgcn_image_atomic_dec_2dmsaa, llvm::Intrinsic::amdgcn_image_atomic_dec_3d,   llvm::Intrinsic::amdgcn_image_atomic_dec_cube, llvm::Intrinsic::amdgcn_image_atomic_inc_1d, llvm::Intrinsic::amdgcn_image_atomic_inc_1darray, llvm::Intrinsic::amdgcn_image_atomic_inc_2d,   llvm::Intrinsic::amdgcn_image_atomic_inc_2darray, llvm::Intrinsic::amdgcn_image_atomic_inc_2darraymsaa, llvm::Intrinsic::amdgcn_image_atomic_inc_2dmsaa, llvm::Intrinsic::amdgcn_image_atomic_inc_3d,   llvm::Intrinsic::amdgcn_image_atomic_inc_cube, llvm::Intrinsic::amdgcn_image_atomic_or_1d, llvm::Intrinsic::amdgcn_image_atomic_or_1darray, llvm::Intrinsic::amdgcn_image_atomic_or_2d,   llvm::Intrinsic::amdgcn_image_atomic_or_2darray, llvm::Intrinsic::amdgcn_image_atomic_or_2darraymsaa, llvm::Intrinsic::amdgcn_image_atomic_or_2dmsaa, llvm::Intrinsic::amdgcn_image_atomic_or_3d,   llvm::Intrinsic::amdgcn_image_atomic_or_cube, llvm::Intrinsic::amdgcn_image_atomic_smax_1d, llvm::Intrinsic::amdgcn_image_atomic_smax_1darray, llvm::Intrinsic::amdgcn_image_atomic_smax_2d,   llvm::Intrinsic::amdgcn_image_atomic_smax_2darray, llvm::Intrinsic::amdgcn_image_atomic_smax_2darraymsaa, llvm::Intrinsic::amdgcn_image_atomic_smax_2dmsaa, llvm::Intrinsic::amdgcn_image_atomic_smax_3d,   llvm::Intrinsic::amdgcn_image_atomic_smax_cube, llvm::Intrinsic::amdgcn_image_atomic_smin_1d, llvm::Intrinsic::amdgcn_image_atomic_smin_1darray, llvm::Intrinsic::amdgcn_image_atomic_smin_2d,   llvm::Intrinsic::amdgcn_image_atomic_smin_2darray, llvm::Intrinsic::amdgcn_image_atomic_smin_2darraymsaa, llvm::Intrinsic::amdgcn_image_atomic_smin_2dmsaa, llvm::Intrinsic::amdgcn_image_atomic_smin_3d,   llvm::Intrinsic::amdgcn_image_atomic_smin_cube, llvm::Intrinsic::amdgcn_image_atomic_sub_1d, llvm::Intrinsic::amdgcn_image_atomic_sub_1darray, llvm::Intrinsic::amdgcn_image_atomic_sub_2d,   llvm::Intrinsic::amdgcn_image_atomic_sub_2darray, llvm::Intrinsic::amdgcn_image_atomic_sub_2darraymsaa, llvm::Intrinsic::amdgcn_image_atomic_sub_2dmsaa, llvm::Intrinsic::amdgcn_image_atomic_sub_3d,   llvm::Intrinsic::amdgcn_image_atomic_sub_cube, llvm::Intrinsic::amdgcn_image_atomic_swap_1d, llvm::Intrinsic::amdgcn_image_atomic_swap_1darray, llvm::Intrinsic::amdgcn_image_atomic_swap_2d,   llvm::Intrinsic::amdgcn_image_atomic_swap_2darray, llvm::Intrinsic::amdgcn_image_atomic_swap_2darraymsaa, llvm::Intrinsic::amdgcn_image_atomic_swap_2dmsaa, llvm::Intrinsic::amdgcn_image_atomic_swap_3d,   llvm::Intrinsic::amdgcn_image_atomic_swap_cube, llvm::Intrinsic::amdgcn_image_atomic_umax_1d, llvm::Intrinsic::amdgcn_image_atomic_umax_1darray, llvm::Intrinsic::amdgcn_image_atomic_umax_2d,   llvm::Intrinsic::amdgcn_image_atomic_umax_2darray, llvm::Intrinsic::amdgcn_image_atomic_umax_2darraymsaa, llvm::Intrinsic::amdgcn_image_atomic_umax_2dmsaa, llvm::Intrinsic::amdgcn_image_atomic_umax_3d,   llvm::Intrinsic::amdgcn_image_atomic_umax_cube, llvm::Intrinsic::amdgcn_image_atomic_umin_1d, llvm::Intrinsic::amdgcn_image_atomic_umin_1darray, llvm::Intrinsic::amdgcn_image_atomic_umin_2d,   llvm::Intrinsic::amdgcn_image_atomic_umin_2darray, llvm::Intrinsic::amdgcn_image_atomic_umin_2darraymsaa, llvm::Intrinsic::amdgcn_image_atomic_umin_2dmsaa, llvm::Intrinsic::amdgcn_image_atomic_umin_3d,   llvm::Intrinsic::amdgcn_image_atomic_umin_cube, llvm::Intrinsic::amdgcn_image_atomic_xor_1d, llvm::Intrinsic::amdgcn_image_atomic_xor_1darray, llvm::Intrinsic::amdgcn_image_atomic_xor_2d,   llvm::Intrinsic::amdgcn_image_atomic_xor_2darray, llvm::Intrinsic::amdgcn_image_atomic_xor_2darraymsaa, llvm::Intrinsic::amdgcn_image_atomic_xor_2dmsaa, llvm::Intrinsic::amdgcn_image_atomic_xor_3d,   llvm::Intrinsic::amdgcn_image_atomic_xor_cube, llvm::Intrinsic::amdgcn_image_gather4_2d, llvm::Intrinsic::amdgcn_image_gather4_2darray, llvm::Intrinsic::amdgcn_image_gather4_b_2d,   llvm::Intrinsic::amdgcn_image_gather4_b_2darray, llvm::Intrinsic::amdgcn_image_gather4_b_cl_2d, llvm::Intrinsic::amdgcn_image_gather4_b_cl_2darray, llvm::Intrinsic::amdgcn_image_gather4_b_cl_cube,   llvm::Intrinsic::amdgcn_image_gather4_b_cl_o_2d, llvm::Intrinsic::amdgcn_image_gather4_b_cl_o_2darray, llvm::Intrinsic::amdgcn_image_gather4_b_cl_o_cube, llvm::Intrinsic::amdgcn_image_gather4_b_cube,   llvm::Intrinsic::amdgcn_image_gather4_b_o_2d, llvm::Intrinsic::amdgcn_image_gather4_b_o_2darray, llvm::Intrinsic::amdgcn_image_gather4_b_o_cube, llvm::Intrinsic::amdgcn_image_gather4_c_2d,   llvm::Intrinsic::amdgcn_image_gather4_c_2darray, llvm::Intrinsic::amdgcn_image_gather4_c_b_2d, llvm::Intrinsic::amdgcn_image_gather4_c_b_2darray, llvm::Intrinsic::amdgcn_image_gather4_c_b_cl_2d,   llvm::Intrinsic::amdgcn_image_gather4_c_b_cl_2darray, llvm::Intrinsic::amdgcn_image_gather4_c_b_cl_cube, llvm::Intrinsic::amdgcn_image_gather4_c_b_cl_o_2d, llvm::Intrinsic::amdgcn_image_gather4_c_b_cl_o_2darray,   llvm::Intrinsic::amdgcn_image_gather4_c_b_cl_o_cube, llvm::Intrinsic::amdgcn_image_gather4_c_b_cube, llvm::Intrinsic::amdgcn_image_gather4_c_b_o_2d, llvm::Intrinsic::amdgcn_image_gather4_c_b_o_2darray,   llvm::Intrinsic::amdgcn_image_gather4_c_b_o_cube, llvm::Intrinsic::amdgcn_image_gather4_c_cl_2d, llvm::Intrinsic::amdgcn_image_gather4_c_cl_2darray, llvm::Intrinsic::amdgcn_image_gather4_c_cl_cube,   llvm::Intrinsic::amdgcn_image_gather4_c_cl_o_2d, llvm::Intrinsic::amdgcn_image_gather4_c_cl_o_2darray, llvm::Intrinsic::amdgcn_image_gather4_c_cl_o_cube, llvm::Intrinsic::amdgcn_image_gather4_c_cube,   llvm::Intrinsic::amdgcn_image_gather4_c_l_2d, llvm::Intrinsic::amdgcn_image_gather4_c_l_2darray, llvm::Intrinsic::amdgcn_image_gather4_c_l_cube, llvm::Intrinsic::amdgcn_image_gather4_c_l_o_2d,   llvm::Intrinsic::amdgcn_image_gather4_c_l_o_2darray, llvm::Intrinsic::amdgcn_image_gather4_c_l_o_cube, llvm::Intrinsic::amdgcn_image_gather4_c_lz_2d, llvm::Intrinsic::amdgcn_image_gather4_c_lz_2darray,   llvm::Intrinsic::amdgcn_image_gather4_c_lz_cube, llvm::Intrinsic::amdgcn_image_gather4_c_lz_o_2d, llvm::Intrinsic::amdgcn_image_gather4_c_lz_o_2darray, llvm::Intrinsic::amdgcn_image_gather4_c_lz_o_cube,   llvm::Intrinsic::amdgcn_image_gather4_c_o_2d, llvm::Intrinsic::amdgcn_image_gather4_c_o_2darray, llvm::Intrinsic::amdgcn_image_gather4_c_o_cube, llvm::Intrinsic::amdgcn_image_gather4_cl_2d,   llvm::Intrinsic::amdgcn_image_gather4_cl_2darray, llvm::Intrinsic::amdgcn_image_gather4_cl_cube, llvm::Intrinsic::amdgcn_image_gather4_cl_o_2d, llvm::Intrinsic::amdgcn_image_gather4_cl_o_2darray,   llvm::Intrinsic::amdgcn_image_gather4_cl_o_cube, llvm::Intrinsic::amdgcn_image_gather4_cube, llvm::Intrinsic::amdgcn_image_gather4_l_2d, llvm::Intrinsic::amdgcn_image_gather4_l_2darray,   llvm::Intrinsic::amdgcn_image_gather4_l_cube, llvm::Intrinsic::amdgcn_image_gather4_l_o_2d, llvm::Intrinsic::amdgcn_image_gather4_l_o_2darray, llvm::Intrinsic::amdgcn_image_gather4_l_o_cube,   llvm::Intrinsic::amdgcn_image_gather4_lz_2d, llvm::Intrinsic::amdgcn_image_gather4_lz_2darray, llvm::Intrinsic::amdgcn_image_gather4_lz_cube, llvm::Intrinsic::amdgcn_image_gather4_lz_o_2d,   llvm::Intrinsic::amdgcn_image_gather4_lz_o_2darray, llvm::Intrinsic::amdgcn_image_gather4_lz_o_cube, llvm::Intrinsic::amdgcn_image_gather4_o_2d, llvm::Intrinsic::amdgcn_image_gather4_o_2darray,   llvm::Intrinsic::amdgcn_image_gather4_o_cube, llvm::Intrinsic::amdgcn_image_getlod_1d, llvm::Intrinsic::amdgcn_image_getlod_1darray, llvm::Intrinsic::amdgcn_image_getlod_2d,   llvm::Intrinsic::amdgcn_image_getlod_2darray, llvm::Intrinsic::amdgcn_image_getlod_3d, llvm::Intrinsic::amdgcn_image_getlod_cube, llvm::Intrinsic::amdgcn_image_getresinfo_1d,   llvm::Intrinsic::amdgcn_image_getresinfo_1darray, llvm::Intrinsic::amdgcn_image_getresinfo_2d, llvm::Intrinsic::amdgcn_image_getresinfo_2darray, llvm::Intrinsic::amdgcn_image_getresinfo_2darraymsaa,   llvm::Intrinsic::amdgcn_image_getresinfo_2dmsaa, llvm::Intrinsic::amdgcn_image_getresinfo_3d, llvm::Intrinsic::amdgcn_image_getresinfo_cube, llvm::Intrinsic::amdgcn_image_load_1d,   llvm::Intrinsic::amdgcn_image_load_1darray, llvm::Intrinsic::amdgcn_image_load_2d, llvm::Intrinsic::amdgcn_image_load_2darray, llvm::Intrinsic::amdgcn_image_load_2darraymsaa,   llvm::Intrinsic::amdgcn_image_load_2dmsaa, llvm::Intrinsic::amdgcn_image_load_3d, llvm::Intrinsic::amdgcn_image_load_cube, llvm::Intrinsic::amdgcn_image_load_mip_1d,   llvm::Intrinsic::amdgcn_image_load_mip_1darray, llvm::Intrinsic::amdgcn_image_load_mip_2d, llvm::Intrinsic::amdgcn_image_load_mip_2darray, llvm::Intrinsic::amdgcn_image_load_mip_3d,   llvm::Intrinsic::amdgcn_image_load_mip_cube, llvm::Intrinsic::amdgcn_image_sample_1d, llvm::Intrinsic::amdgcn_image_sample_1darray, llvm::Intrinsic::amdgcn_image_sample_2d,   llvm::Intrinsic::amdgcn_image_sample_2darray, llvm::Intrinsic::amdgcn_image_sample_3d, llvm::Intrinsic::amdgcn_image_sample_b_1d, llvm::Intrinsic::amdgcn_image_sample_b_1darray,   llvm::Intrinsic::amdgcn_image_sample_b_2d, llvm::Intrinsic::amdgcn_image_sample_b_2darray, llvm::Intrinsic::amdgcn_image_sample_b_3d, llvm::Intrinsic::amdgcn_image_sample_b_cl_1d,   llvm::Intrinsic::amdgcn_image_sample_b_cl_1darray, llvm::Intrinsic::amdgcn_image_sample_b_cl_2d, llvm::Intrinsic::amdgcn_image_sample_b_cl_2darray, llvm::Intrinsic::amdgcn_image_sample_b_cl_3d,   llvm::Intrinsic::amdgcn_image_sample_b_cl_cube, llvm::Intrinsic::amdgcn_image_sample_b_cl_o_1d, llvm::Intrinsic::amdgcn_image_sample_b_cl_o_1darray, llvm::Intrinsic::amdgcn_image_sample_b_cl_o_2d,   llvm::Intrinsic::amdgcn_image_sample_b_cl_o_2darray, llvm::Intrinsic::amdgcn_image_sample_b_cl_o_3d, llvm::Intrinsic::amdgcn_image_sample_b_cl_o_cube, llvm::Intrinsic::amdgcn_image_sample_b_cube,   llvm::Intrinsic::amdgcn_image_sample_b_o_1d, llvm::Intrinsic::amdgcn_image_sample_b_o_1darray, llvm::Intrinsic::amdgcn_image_sample_b_o_2d, llvm::Intrinsic::amdgcn_image_sample_b_o_2darray,   llvm::Intrinsic::amdgcn_image_sample_b_o_3d, llvm::Intrinsic::amdgcn_image_sample_b_o_cube, llvm::Intrinsic::amdgcn_image_sample_c_1d, llvm::Intrinsic::amdgcn_image_sample_c_1darray,   llvm::Intrinsic::amdgcn_image_sample_c_2d, llvm::Intrinsic::amdgcn_image_sample_c_2darray, llvm::Intrinsic::amdgcn_image_sample_c_3d, llvm::Intrinsic::amdgcn_image_sample_c_b_1d,   llvm::Intrinsic::amdgcn_image_sample_c_b_1darray, llvm::Intrinsic::amdgcn_image_sample_c_b_2d, llvm::Intrinsic::amdgcn_image_sample_c_b_2darray, llvm::Intrinsic::amdgcn_image_sample_c_b_3d,   llvm::Intrinsic::amdgcn_image_sample_c_b_cl_1d, llvm::Intrinsic::amdgcn_image_sample_c_b_cl_1darray, llvm::Intrinsic::amdgcn_image_sample_c_b_cl_2d, llvm::Intrinsic::amdgcn_image_sample_c_b_cl_2darray,   llvm::Intrinsic::amdgcn_image_sample_c_b_cl_3d, llvm::Intrinsic::amdgcn_image_sample_c_b_cl_cube, llvm::Intrinsic::amdgcn_image_sample_c_b_cl_o_1d, llvm::Intrinsic::amdgcn_image_sample_c_b_cl_o_1darray,   llvm::Intrinsic::amdgcn_image_sample_c_b_cl_o_2d, llvm::Intrinsic::amdgcn_image_sample_c_b_cl_o_2darray, llvm::Intrinsic::amdgcn_image_sample_c_b_cl_o_3d, llvm::Intrinsic::amdgcn_image_sample_c_b_cl_o_cube,   llvm::Intrinsic::amdgcn_image_sample_c_b_cube, llvm::Intrinsic::amdgcn_image_sample_c_b_o_1d, llvm::Intrinsic::amdgcn_image_sample_c_b_o_1darray, llvm::Intrinsic::amdgcn_image_sample_c_b_o_2d,   llvm::Intrinsic::amdgcn_image_sample_c_b_o_2darray, llvm::Intrinsic::amdgcn_image_sample_c_b_o_3d, llvm::Intrinsic::amdgcn_image_sample_c_b_o_cube, llvm::Intrinsic::amdgcn_image_sample_c_cd_1d,   llvm::Intrinsic::amdgcn_image_sample_c_cd_1darray, llvm::Intrinsic::amdgcn_image_sample_c_cd_2d, llvm::Intrinsic::amdgcn_image_sample_c_cd_2darray, llvm::Intrinsic::amdgcn_image_sample_c_cd_3d,   llvm::Intrinsic::amdgcn_image_sample_c_cd_cl_1d, llvm::Intrinsic::amdgcn_image_sample_c_cd_cl_1darray, llvm::Intrinsic::amdgcn_image_sample_c_cd_cl_2d, llvm::Intrinsic::amdgcn_image_sample_c_cd_cl_2darray,   llvm::Intrinsic::amdgcn_image_sample_c_cd_cl_3d, llvm::Intrinsic::amdgcn_image_sample_c_cd_cl_cube, llvm::Intrinsic::amdgcn_image_sample_c_cd_cl_o_1d, llvm::Intrinsic::amdgcn_image_sample_c_cd_cl_o_1darray,   llvm::Intrinsic::amdgcn_image_sample_c_cd_cl_o_2d, llvm::Intrinsic::amdgcn_image_sample_c_cd_cl_o_2darray, llvm::Intrinsic::amdgcn_image_sample_c_cd_cl_o_3d, llvm::Intrinsic::amdgcn_image_sample_c_cd_cl_o_cube,   llvm::Intrinsic::amdgcn_image_sample_c_cd_cube, llvm::Intrinsic::amdgcn_image_sample_c_cd_o_1d, llvm::Intrinsic::amdgcn_image_sample_c_cd_o_1darray, llvm::Intrinsic::amdgcn_image_sample_c_cd_o_2d,   llvm::Intrinsic::amdgcn_image_sample_c_cd_o_2darray, llvm::Intrinsic::amdgcn_image_sample_c_cd_o_3d, llvm::Intrinsic::amdgcn_image_sample_c_cd_o_cube, llvm::Intrinsic::amdgcn_image_sample_c_cl_1d,   llvm::Intrinsic::amdgcn_image_sample_c_cl_1darray, llvm::Intrinsic::amdgcn_image_sample_c_cl_2d, llvm::Intrinsic::amdgcn_image_sample_c_cl_2darray, llvm::Intrinsic::amdgcn_image_sample_c_cl_3d,   llvm::Intrinsic::amdgcn_image_sample_c_cl_cube, llvm::Intrinsic::amdgcn_image_sample_c_cl_o_1d, llvm::Intrinsic::amdgcn_image_sample_c_cl_o_1darray, llvm::Intrinsic::amdgcn_image_sample_c_cl_o_2d,   llvm::Intrinsic::amdgcn_image_sample_c_cl_o_2darray, llvm::Intrinsic::amdgcn_image_sample_c_cl_o_3d, llvm::Intrinsic::amdgcn_image_sample_c_cl_o_cube, llvm::Intrinsic::amdgcn_image_sample_c_cube,   llvm::Intrinsic::amdgcn_image_sample_c_d_1d, llvm::Intrinsic::amdgcn_image_sample_c_d_1darray, llvm::Intrinsic::amdgcn_image_sample_c_d_2d, llvm::Intrinsic::amdgcn_image_sample_c_d_2darray,   llvm::Intrinsic::amdgcn_image_sample_c_d_3d, llvm::Intrinsic::amdgcn_image_sample_c_d_cl_1d, llvm::Intrinsic::amdgcn_image_sample_c_d_cl_1darray, llvm::Intrinsic::amdgcn_image_sample_c_d_cl_2d,   llvm::Intrinsic::amdgcn_image_sample_c_d_cl_2darray, llvm::Intrinsic::amdgcn_image_sample_c_d_cl_3d, llvm::Intrinsic::amdgcn_image_sample_c_d_cl_cube, llvm::Intrinsic::amdgcn_image_sample_c_d_cl_o_1d,   llvm::Intrinsic::amdgcn_image_sample_c_d_cl_o_1darray, llvm::Intrinsic::amdgcn_image_sample_c_d_cl_o_2d, llvm::Intrinsic::amdgcn_image_sample_c_d_cl_o_2darray, llvm::Intrinsic::amdgcn_image_sample_c_d_cl_o_3d,   llvm::Intrinsic::amdgcn_image_sample_c_d_cl_o_cube, llvm::Intrinsic::amdgcn_image_sample_c_d_cube, llvm::Intrinsic::amdgcn_image_sample_c_d_o_1d, llvm::Intrinsic::amdgcn_image_sample_c_d_o_1darray,   llvm::Intrinsic::amdgcn_image_sample_c_d_o_2d, llvm::Intrinsic::amdgcn_image_sample_c_d_o_2darray, llvm::Intrinsic::amdgcn_image_sample_c_d_o_3d, llvm::Intrinsic::amdgcn_image_sample_c_d_o_cube,   llvm::Intrinsic::amdgcn_image_sample_c_l_1d, llvm::Intrinsic::amdgcn_image_sample_c_l_1darray, llvm::Intrinsic::amdgcn_image_sample_c_l_2d, llvm::Intrinsic::amdgcn_image_sample_c_l_2darray,   llvm::Intrinsic::amdgcn_image_sample_c_l_3d, llvm::Intrinsic::amdgcn_image_sample_c_l_cube, llvm::Intrinsic::amdgcn_image_sample_c_l_o_1d, llvm::Intrinsic::amdgcn_image_sample_c_l_o_1darray,   llvm::Intrinsic::amdgcn_image_sample_c_l_o_2d, llvm::Intrinsic::amdgcn_image_sample_c_l_o_2darray, llvm::Intrinsic::amdgcn_image_sample_c_l_o_3d, llvm::Intrinsic::amdgcn_image_sample_c_l_o_cube,   llvm::Intrinsic::amdgcn_image_sample_c_lz_1d, llvm::Intrinsic::amdgcn_image_sample_c_lz_1darray, llvm::Intrinsic::amdgcn_image_sample_c_lz_2d, llvm::Intrinsic::amdgcn_image_sample_c_lz_2darray,   llvm::Intrinsic::amdgcn_image_sample_c_lz_3d, llvm::Intrinsic::amdgcn_image_sample_c_lz_cube, llvm::Intrinsic::amdgcn_image_sample_c_lz_o_1d, llvm::Intrinsic::amdgcn_image_sample_c_lz_o_1darray,   llvm::Intrinsic::amdgcn_image_sample_c_lz_o_2d, llvm::Intrinsic::amdgcn_image_sample_c_lz_o_2darray, llvm::Intrinsic::amdgcn_image_sample_c_lz_o_3d, llvm::Intrinsic::amdgcn_image_sample_c_lz_o_cube,   llvm::Intrinsic::amdgcn_image_sample_c_o_1d, llvm::Intrinsic::amdgcn_image_sample_c_o_1darray, llvm::Intrinsic::amdgcn_image_sample_c_o_2d, llvm::Intrinsic::amdgcn_image_sample_c_o_2darray,   llvm::Intrinsic::amdgcn_image_sample_c_o_3d, llvm::Intrinsic::amdgcn_image_sample_c_o_cube, llvm::Intrinsic::amdgcn_image_sample_cd_1d, llvm::Intrinsic::amdgcn_image_sample_cd_1darray,   llvm::Intrinsic::amdgcn_image_sample_cd_2d, llvm::Intrinsic::amdgcn_image_sample_cd_2darray, llvm::Intrinsic::amdgcn_image_sample_cd_3d, llvm::Intrinsic::amdgcn_image_sample_cd_cl_1d,   llvm::Intrinsic::amdgcn_image_sample_cd_cl_1darray, llvm::Intrinsic::amdgcn_image_sample_cd_cl_2d, llvm::Intrinsic::amdgcn_image_sample_cd_cl_2darray, llvm::Intrinsic::amdgcn_image_sample_cd_cl_3d,   llvm::Intrinsic::amdgcn_image_sample_cd_cl_cube, llvm::Intrinsic::amdgcn_image_sample_cd_cl_o_1d, llvm::Intrinsic::amdgcn_image_sample_cd_cl_o_1darray, llvm::Intrinsic::amdgcn_image_sample_cd_cl_o_2d,   llvm::Intrinsic::amdgcn_image_sample_cd_cl_o_2darray, llvm::Intrinsic::amdgcn_image_sample_cd_cl_o_3d, llvm::Intrinsic::amdgcn_image_sample_cd_cl_o_cube, llvm::Intrinsic::amdgcn_image_sample_cd_cube,   llvm::Intrinsic::amdgcn_image_sample_cd_o_1d, llvm::Intrinsic::amdgcn_image_sample_cd_o_1darray, llvm::Intrinsic::amdgcn_image_sample_cd_o_2d, llvm::Intrinsic::amdgcn_image_sample_cd_o_2darray,   llvm::Intrinsic::amdgcn_image_sample_cd_o_3d, llvm::Intrinsic::amdgcn_image_sample_cd_o_cube, llvm::Intrinsic::amdgcn_image_sample_cl_1d, llvm::Intrinsic::amdgcn_image_sample_cl_1darray,   llvm::Intrinsic::amdgcn_image_sample_cl_2d, llvm::Intrinsic::amdgcn_image_sample_cl_2darray, llvm::Intrinsic::amdgcn_image_sample_cl_3d, llvm::Intrinsic::amdgcn_image_sample_cl_cube,   llvm::Intrinsic::amdgcn_image_sample_cl_o_1d, llvm::Intrinsic::amdgcn_image_sample_cl_o_1darray, llvm::Intrinsic::amdgcn_image_sample_cl_o_2d, llvm::Intrinsic::amdgcn_image_sample_cl_o_2darray,   llvm::Intrinsic::amdgcn_image_sample_cl_o_3d, llvm::Intrinsic::amdgcn_image_sample_cl_o_cube, llvm::Intrinsic::amdgcn_image_sample_cube, llvm::Intrinsic::amdgcn_image_sample_d_1d,   llvm::Intrinsic::amdgcn_image_sample_d_1darray, llvm::Intrinsic::amdgcn_image_sample_d_2d, llvm::Intrinsic::amdgcn_image_sample_d_2darray, llvm::Intrinsic::amdgcn_image_sample_d_3d,   llvm::Intrinsic::amdgcn_image_sample_d_cl_1d, llvm::Intrinsic::amdgcn_image_sample_d_cl_1darray, llvm::Intrinsic::amdgcn_image_sample_d_cl_2d, llvm::Intrinsic::amdgcn_image_sample_d_cl_2darray,   llvm::Intrinsic::amdgcn_image_sample_d_cl_3d, llvm::Intrinsic::amdgcn_image_sample_d_cl_cube, llvm::Intrinsic::amdgcn_image_sample_d_cl_o_1d, llvm::Intrinsic::amdgcn_image_sample_d_cl_o_1darray,   llvm::Intrinsic::amdgcn_image_sample_d_cl_o_2d, llvm::Intrinsic::amdgcn_image_sample_d_cl_o_2darray, llvm::Intrinsic::amdgcn_image_sample_d_cl_o_3d, llvm::Intrinsic::amdgcn_image_sample_d_cl_o_cube,   llvm::Intrinsic::amdgcn_image_sample_d_cube, llvm::Intrinsic::amdgcn_image_sample_d_o_1d, llvm::Intrinsic::amdgcn_image_sample_d_o_1darray, llvm::Intrinsic::amdgcn_image_sample_d_o_2d,   llvm::Intrinsic::amdgcn_image_sample_d_o_2darray, llvm::Intrinsic::amdgcn_image_sample_d_o_3d, llvm::Intrinsic::amdgcn_image_sample_d_o_cube, llvm::Intrinsic::amdgcn_image_sample_l_1d,   llvm::Intrinsic::amdgcn_image_sample_l_1darray, llvm::Intrinsic::amdgcn_image_sample_l_2d, llvm::Intrinsic::amdgcn_image_sample_l_2darray, llvm::Intrinsic::amdgcn_image_sample_l_3d,   llvm::Intrinsic::amdgcn_image_sample_l_cube, llvm::Intrinsic::amdgcn_image_sample_l_o_1d, llvm::Intrinsic::amdgcn_image_sample_l_o_1darray, llvm::Intrinsic::amdgcn_image_sample_l_o_2d,   llvm::Intrinsic::amdgcn_image_sample_l_o_2darray, llvm::Intrinsic::amdgcn_image_sample_l_o_3d, llvm::Intrinsic::amdgcn_image_sample_l_o_cube, llvm::Intrinsic::amdgcn_image_sample_lz_1d,   llvm::Intrinsic::amdgcn_image_sample_lz_1darray, llvm::Intrinsic::amdgcn_image_sample_lz_2d, llvm::Intrinsic::amdgcn_image_sample_lz_2darray, llvm::Intrinsic::amdgcn_image_sample_lz_3d,   llvm::Intrinsic::amdgcn_image_sample_lz_cube, llvm::Intrinsic::amdgcn_image_sample_lz_o_1d, llvm::Intrinsic::amdgcn_image_sample_lz_o_1darray, llvm::Intrinsic::amdgcn_image_sample_lz_o_2d,   llvm::Intrinsic::amdgcn_image_sample_lz_o_2darray, llvm::Intrinsic::amdgcn_image_sample_lz_o_3d, llvm::Intrinsic::amdgcn_image_sample_lz_o_cube, llvm::Intrinsic::amdgcn_image_sample_o_1d,   llvm::Intrinsic::amdgcn_image_sample_o_1darray, llvm::Intrinsic::amdgcn_image_sample_o_2d, llvm::Intrinsic::amdgcn_image_sample_o_2darray, llvm::Intrinsic::amdgcn_image_sample_o_3d,   llvm::Intrinsic::amdgcn_image_sample_o_cube, llvm::Intrinsic::amdgcn_image_store_1d, llvm::Intrinsic::amdgcn_image_store_1darray, llvm::Intrinsic::amdgcn_image_store_2d,   llvm::Intrinsic::amdgcn_image_store_2darray, llvm::Intrinsic::amdgcn_image_store_2darraymsaa, llvm::Intrinsic::amdgcn_image_store_2dmsaa, llvm::Intrinsic::amdgcn_image_store_3d,   llvm::Intrinsic::amdgcn_image_store_cube, llvm::Intrinsic::amdgcn_image_store_mip_1d, llvm::Intrinsic::amdgcn_image_store_mip_1darray, llvm::Intrinsic::amdgcn_image_store_mip_2d,   llvm::Intrinsic::amdgcn_image_store_mip_2darray, llvm::Intrinsic::amdgcn_image_store_mip_3d, llvm::Intrinsic::amdgcn_image_store_mip_cube, llvm::Intrinsic::amdgcn_implicit_buffer_ptr,   llvm::Intrinsic::amdgcn_implicitarg_ptr, llvm::Intrinsic::amdgcn_init_exec, llvm::Intrinsic::amdgcn_init_exec_from_input, llvm::Intrinsic::amdgcn_interp_mov,   llvm::Intrinsic::amdgcn_interp_p1, llvm::Intrinsic::amdgcn_interp_p2, llvm::Intrinsic::amdgcn_kernarg_segment_ptr, llvm::Intrinsic::amdgcn_kill,   llvm::Intrinsic::amdgcn_ldexp, llvm::Intrinsic::amdgcn_lerp, llvm::Intrinsic::amdgcn_log_clamp, llvm::Intrinsic::amdgcn_loop,   llvm::Intrinsic::amdgcn_mbcnt_hi, llvm::Intrinsic::amdgcn_mbcnt_lo, llvm::Intrinsic::amdgcn_mov_dpp, llvm::Intrinsic::amdgcn_mqsad_pk_u16_u8,   llvm::Intrinsic::amdgcn_mqsad_u32_u8, llvm::Intrinsic::amdgcn_msad_u8, llvm::Intrinsic::amdgcn_ps_live, llvm::Intrinsic::amdgcn_qsad_pk_u16_u8,   llvm::Intrinsic::amdgcn_queue_ptr, llvm::Intrinsic::amdgcn_raw_buffer_atomic_add, llvm::Intrinsic::amdgcn_raw_buffer_atomic_and, llvm::Intrinsic::amdgcn_raw_buffer_atomic_cmpswap,   llvm::Intrinsic::amdgcn_raw_buffer_atomic_or, llvm::Intrinsic::amdgcn_raw_buffer_atomic_smax, llvm::Intrinsic::amdgcn_raw_buffer_atomic_smin, llvm::Intrinsic::amdgcn_raw_buffer_atomic_sub,   llvm::Intrinsic::amdgcn_raw_buffer_atomic_swap, llvm::Intrinsic::amdgcn_raw_buffer_atomic_umax, llvm::Intrinsic::amdgcn_raw_buffer_atomic_umin, llvm::Intrinsic::amdgcn_raw_buffer_atomic_xor,   llvm::Intrinsic::amdgcn_raw_buffer_load, llvm::Intrinsic::amdgcn_raw_buffer_load_format, llvm::Intrinsic::amdgcn_raw_buffer_store, llvm::Intrinsic::amdgcn_raw_buffer_store_format,   llvm::Intrinsic::amdgcn_raw_tbuffer_load, llvm::Intrinsic::amdgcn_raw_tbuffer_store, llvm::Intrinsic::amdgcn_rcp, llvm::Intrinsic::amdgcn_rcp_legacy,   llvm::Intrinsic::amdgcn_readfirstlane, llvm::Intrinsic::amdgcn_readlane, llvm::Intrinsic::amdgcn_rsq, llvm::Intrinsic::amdgcn_rsq_clamp,   llvm::Intrinsic::amdgcn_rsq_legacy, llvm::Intrinsic::amdgcn_s_barrier, llvm::Intrinsic::amdgcn_s_buffer_load, llvm::Intrinsic::amdgcn_s_dcache_inv,   llvm::Intrinsic::amdgcn_s_dcache_inv_vol, llvm::Intrinsic::amdgcn_s_dcache_wb, llvm::Intrinsic::amdgcn_s_dcache_wb_vol, llvm::Intrinsic::amdgcn_s_decperflevel,   llvm::Intrinsic::amdgcn_s_getpc, llvm::Intrinsic::amdgcn_s_getreg, llvm::Intrinsic::amdgcn_s_incperflevel, llvm::Intrinsic::amdgcn_s_memrealtime,   llvm::Intrinsic::amdgcn_s_memtime, llvm::Intrinsic::amdgcn_s_sendmsg, llvm::Intrinsic::amdgcn_s_sendmsghalt, llvm::Intrinsic::amdgcn_s_sleep,   llvm::Intrinsic::amdgcn_s_waitcnt, llvm::Intrinsic::amdgcn_sad_hi_u8, llvm::Intrinsic::amdgcn_sad_u16, llvm::Intrinsic::amdgcn_sad_u8,   llvm::Intrinsic::amdgcn_sbfe, llvm::Intrinsic::amdgcn_sdot2, llvm::Intrinsic::amdgcn_sdot4, llvm::Intrinsic::amdgcn_sdot8,   llvm::Intrinsic::amdgcn_set_inactive, llvm::Intrinsic::amdgcn_sffbh, llvm::Intrinsic::amdgcn_sin, llvm::Intrinsic::amdgcn_struct_buffer_atomic_add,   llvm::Intrinsic::amdgcn_struct_buffer_atomic_and, llvm::Intrinsic::amdgcn_struct_buffer_atomic_cmpswap, llvm::Intrinsic::amdgcn_struct_buffer_atomic_or, llvm::Intrinsic::amdgcn_struct_buffer_atomic_smax,   llvm::Intrinsic::amdgcn_struct_buffer_atomic_smin, llvm::Intrinsic::amdgcn_struct_buffer_atomic_sub, llvm::Intrinsic::amdgcn_struct_buffer_atomic_swap, llvm::Intrinsic::amdgcn_struct_buffer_atomic_umax,   llvm::Intrinsic::amdgcn_struct_buffer_atomic_umin, llvm::Intrinsic::amdgcn_struct_buffer_atomic_xor, llvm::Intrinsic::amdgcn_struct_buffer_load, llvm::Intrinsic::amdgcn_struct_buffer_load_format,   llvm::Intrinsic::amdgcn_struct_buffer_store, llvm::Intrinsic::amdgcn_struct_buffer_store_format, llvm::Intrinsic::amdgcn_struct_tbuffer_load, llvm::Intrinsic::amdgcn_struct_tbuffer_store,   llvm::Intrinsic::amdgcn_tbuffer_load, llvm::Intrinsic::amdgcn_tbuffer_store, llvm::Intrinsic::amdgcn_trig_preop, llvm::Intrinsic::amdgcn_ubfe,   llvm::Intrinsic::amdgcn_udot2, llvm::Intrinsic::amdgcn_udot4, llvm::Intrinsic::amdgcn_udot8, llvm::Intrinsic::amdgcn_unreachable,   llvm::Intrinsic::amdgcn_update_dpp, llvm::Intrinsic::amdgcn_wave_barrier, llvm::Intrinsic::amdgcn_workgroup_id_x, llvm::Intrinsic::amdgcn_workgroup_id_y,   llvm::Intrinsic::amdgcn_workgroup_id_z, llvm::Intrinsic::amdgcn_workitem_id_x, llvm::Intrinsic::amdgcn_workitem_id_y, llvm::Intrinsic::amdgcn_workitem_id_z,   llvm::Intrinsic::amdgcn_wqm, llvm::Intrinsic::amdgcn_wqm_vote, llvm::Intrinsic::amdgcn_writelane, llvm::Intrinsic::amdgcn_wwm,   llvm::Intrinsic::arm_cdp, llvm::Intrinsic::arm_cdp2, llvm::Intrinsic::arm_clrex, llvm::Intrinsic::arm_crc32b,   llvm::Intrinsic::arm_crc32cb, llvm::Intrinsic::arm_crc32ch, llvm::Intrinsic::arm_crc32cw, llvm::Intrinsic::arm_crc32h,   llvm::Intrinsic::arm_crc32w, llvm::Intrinsic::arm_dbg, llvm::Intrinsic::arm_dmb, llvm::Intrinsic::arm_dsb,   llvm::Intrinsic::arm_get_fpscr, llvm::Intrinsic::arm_hint, llvm::Intrinsic::arm_isb, llvm::Intrinsic::arm_ldaex,   llvm::Intrinsic::arm_ldaexd, llvm::Intrinsic::arm_ldc, llvm::Intrinsic::arm_ldc2, llvm::Intrinsic::arm_ldc2l,   llvm::Intrinsic::arm_ldcl, llvm::Intrinsic::arm_ldrex, llvm::Intrinsic::arm_ldrexd, llvm::Intrinsic::arm_mcr,   llvm::Intrinsic::arm_mcr2, llvm::Intrinsic::arm_mcrr, llvm::Intrinsic::arm_mcrr2, llvm::Intrinsic::arm_mrc,   llvm::Intrinsic::arm_mrc2, llvm::Intrinsic::arm_mrrc, llvm::Intrinsic::arm_mrrc2, llvm::Intrinsic::arm_neon_aesd,   llvm::Intrinsic::arm_neon_aese, llvm::Intrinsic::arm_neon_aesimc, llvm::Intrinsic::arm_neon_aesmc, llvm::Intrinsic::arm_neon_sdot,   llvm::Intrinsic::arm_neon_sha1c, llvm::Intrinsic::arm_neon_sha1h, llvm::Intrinsic::arm_neon_sha1m, llvm::Intrinsic::arm_neon_sha1p,   llvm::Intrinsic::arm_neon_sha1su0, llvm::Intrinsic::arm_neon_sha1su1, llvm::Intrinsic::arm_neon_sha256h, llvm::Intrinsic::arm_neon_sha256h2,   llvm::Intrinsic::arm_neon_sha256su0, llvm::Intrinsic::arm_neon_sha256su1, llvm::Intrinsic::arm_neon_udot, llvm::Intrinsic::arm_neon_vabds,   llvm::Intrinsic::arm_neon_vabdu, llvm::Intrinsic::arm_neon_vabs, llvm::Intrinsic::arm_neon_vacge, llvm::Intrinsic::arm_neon_vacgt,   llvm::Intrinsic::arm_neon_vbsl, llvm::Intrinsic::arm_neon_vcls, llvm::Intrinsic::arm_neon_vcvtas, llvm::Intrinsic::arm_neon_vcvtau,   llvm::Intrinsic::arm_neon_vcvtfp2fxs, llvm::Intrinsic::arm_neon_vcvtfp2fxu, llvm::Intrinsic::arm_neon_vcvtfp2hf, llvm::Intrinsic::arm_neon_vcvtfxs2fp,   llvm::Intrinsic::arm_neon_vcvtfxu2fp, llvm::Intrinsic::arm_neon_vcvthf2fp, llvm::Intrinsic::arm_neon_vcvtms, llvm::Intrinsic::arm_neon_vcvtmu,   llvm::Intrinsic::arm_neon_vcvtns, llvm::Intrinsic::arm_neon_vcvtnu, llvm::Intrinsic::arm_neon_vcvtps, llvm::Intrinsic::arm_neon_vcvtpu,   llvm::Intrinsic::arm_neon_vhadds, llvm::Intrinsic::arm_neon_vhaddu, llvm::Intrinsic::arm_neon_vhsubs, llvm::Intrinsic::arm_neon_vhsubu,   llvm::Intrinsic::arm_neon_vld1, llvm::Intrinsic::arm_neon_vld1x2, llvm::Intrinsic::arm_neon_vld1x3, llvm::Intrinsic::arm_neon_vld1x4,   llvm::Intrinsic::arm_neon_vld2, llvm::Intrinsic::arm_neon_vld2dup, llvm::Intrinsic::arm_neon_vld2lane, llvm::Intrinsic::arm_neon_vld3,   llvm::Intrinsic::arm_neon_vld3dup, llvm::Intrinsic::arm_neon_vld3lane, llvm::Intrinsic::arm_neon_vld4, llvm::Intrinsic::arm_neon_vld4dup,   llvm::Intrinsic::arm_neon_vld4lane, llvm::Intrinsic::arm_neon_vmaxnm, llvm::Intrinsic::arm_neon_vmaxs, llvm::Intrinsic::arm_neon_vmaxu,   llvm::Intrinsic::arm_neon_vminnm, llvm::Intrinsic::arm_neon_vmins, llvm::Intrinsic::arm_neon_vminu, llvm::Intrinsic::arm_neon_vmullp,   llvm::Intrinsic::arm_neon_vmulls, llvm::Intrinsic::arm_neon_vmullu, llvm::Intrinsic::arm_neon_vmulp, llvm::Intrinsic::arm_neon_vpadals,   llvm::Intrinsic::arm_neon_vpadalu, llvm::Intrinsic::arm_neon_vpadd, llvm::Intrinsic::arm_neon_vpaddls, llvm::Intrinsic::arm_neon_vpaddlu,   llvm::Intrinsic::arm_neon_vpmaxs, llvm::Intrinsic::arm_neon_vpmaxu, llvm::Intrinsic::arm_neon_vpmins, llvm::Intrinsic::arm_neon_vpminu,   llvm::Intrinsic::arm_neon_vqabs, llvm::Intrinsic::arm_neon_vqadds, llvm::Intrinsic::arm_neon_vqaddu, llvm::Intrinsic::arm_neon_vqdmulh,   llvm::Intrinsic::arm_neon_vqdmull, llvm::Intrinsic::arm_neon_vqmovns, llvm::Intrinsic::arm_neon_vqmovnsu, llvm::Intrinsic::arm_neon_vqmovnu,   llvm::Intrinsic::arm_neon_vqneg, llvm::Intrinsic::arm_neon_vqrdmulh, llvm::Intrinsic::arm_neon_vqrshiftns, llvm::Intrinsic::arm_neon_vqrshiftnsu,   llvm::Intrinsic::arm_neon_vqrshiftnu, llvm::Intrinsic::arm_neon_vqrshifts, llvm::Intrinsic::arm_neon_vqrshiftu, llvm::Intrinsic::arm_neon_vqshiftns,   llvm::Intrinsic::arm_neon_vqshiftnsu, llvm::Intrinsic::arm_neon_vqshiftnu, llvm::Intrinsic::arm_neon_vqshifts, llvm::Intrinsic::arm_neon_vqshiftsu,   llvm::Intrinsic::arm_neon_vqshiftu, llvm::Intrinsic::arm_neon_vqsubs, llvm::Intrinsic::arm_neon_vqsubu, llvm::Intrinsic::arm_neon_vraddhn,   llvm::Intrinsic::arm_neon_vrecpe, llvm::Intrinsic::arm_neon_vrecps, llvm::Intrinsic::arm_neon_vrhadds, llvm::Intrinsic::arm_neon_vrhaddu,   llvm::Intrinsic::arm_neon_vrinta, llvm::Intrinsic::arm_neon_vrintm, llvm::Intrinsic::arm_neon_vrintn, llvm::Intrinsic::arm_neon_vrintp,   llvm::Intrinsic::arm_neon_vrintx, llvm::Intrinsic::arm_neon_vrintz, llvm::Intrinsic::arm_neon_vrshiftn, llvm::Intrinsic::arm_neon_vrshifts,   llvm::Intrinsic::arm_neon_vrshiftu, llvm::Intrinsic::arm_neon_vrsqrte, llvm::Intrinsic::arm_neon_vrsqrts, llvm::Intrinsic::arm_neon_vrsubhn,   llvm::Intrinsic::arm_neon_vshiftins, llvm::Intrinsic::arm_neon_vshifts, llvm::Intrinsic::arm_neon_vshiftu, llvm::Intrinsic::arm_neon_vst1,   llvm::Intrinsic::arm_neon_vst1x2, llvm::Intrinsic::arm_neon_vst1x3, llvm::Intrinsic::arm_neon_vst1x4, llvm::Intrinsic::arm_neon_vst2,   llvm::Intrinsic::arm_neon_vst2lane, llvm::Intrinsic::arm_neon_vst3, llvm::Intrinsic::arm_neon_vst3lane, llvm::Intrinsic::arm_neon_vst4,   llvm::Intrinsic::arm_neon_vst4lane, llvm::Intrinsic::arm_neon_vtbl1, llvm::Intrinsic::arm_neon_vtbl2, llvm::Intrinsic::arm_neon_vtbl3,   llvm::Intrinsic::arm_neon_vtbl4, llvm::Intrinsic::arm_neon_vtbx1, llvm::Intrinsic::arm_neon_vtbx2, llvm::Intrinsic::arm_neon_vtbx3,   llvm::Intrinsic::arm_neon_vtbx4, llvm::Intrinsic::arm_qadd, llvm::Intrinsic::arm_qadd16, llvm::Intrinsic::arm_qadd8,   llvm::Intrinsic::arm_qasx, llvm::Intrinsic::arm_qsax, llvm::Intrinsic::arm_qsub, llvm::Intrinsic::arm_qsub16,   llvm::Intrinsic::arm_qsub8, llvm::Intrinsic::arm_sadd16, llvm::Intrinsic::arm_sadd8, llvm::Intrinsic::arm_sasx,   llvm::Intrinsic::arm_sel, llvm::Intrinsic::arm_set_fpscr, llvm::Intrinsic::arm_shadd16, llvm::Intrinsic::arm_shadd8,   llvm::Intrinsic::arm_shasx, llvm::Intrinsic::arm_shsax, llvm::Intrinsic::arm_shsub16, llvm::Intrinsic::arm_shsub8,   llvm::Intrinsic::arm_smlabb, llvm::Intrinsic::arm_smlabt, llvm::Intrinsic::arm_smlad, llvm::Intrinsic::arm_smladx,   llvm::Intrinsic::arm_smlald, llvm::Intrinsic::arm_smlaldx, llvm::Intrinsic::arm_smlatb, llvm::Intrinsic::arm_smlatt,   llvm::Intrinsic::arm_smlawb, llvm::Intrinsic::arm_smlawt, llvm::Intrinsic::arm_smlsd, llvm::Intrinsic::arm_smlsdx,   llvm::Intrinsic::arm_smlsld, llvm::Intrinsic::arm_smlsldx, llvm::Intrinsic::arm_smuad, llvm::Intrinsic::arm_smuadx,   llvm::Intrinsic::arm_smulbb, llvm::Intrinsic::arm_smulbt, llvm::Intrinsic::arm_smultb, llvm::Intrinsic::arm_smultt,   llvm::Intrinsic::arm_smulwb, llvm::Intrinsic::arm_smulwt, llvm::Intrinsic::arm_smusd, llvm::Intrinsic::arm_smusdx,   llvm::Intrinsic::arm_space, llvm::Intrinsic::arm_ssat, llvm::Intrinsic::arm_ssat16, llvm::Intrinsic::arm_ssax,   llvm::Intrinsic::arm_ssub16, llvm::Intrinsic::arm_ssub8, llvm::Intrinsic::arm_stc, llvm::Intrinsic::arm_stc2,   llvm::Intrinsic::arm_stc2l, llvm::Intrinsic::arm_stcl, llvm::Intrinsic::arm_stlex, llvm::Intrinsic::arm_stlexd,   llvm::Intrinsic::arm_strex, llvm::Intrinsic::arm_strexd, llvm::Intrinsic::arm_sxtab16, llvm::Intrinsic::arm_sxtb16,   llvm::Intrinsic::arm_uadd16, llvm::Intrinsic::arm_uadd8, llvm::Intrinsic::arm_uasx, llvm::Intrinsic::arm_uhadd16,   llvm::Intrinsic::arm_uhadd8, llvm::Intrinsic::arm_uhasx, llvm::Intrinsic::arm_uhsax, llvm::Intrinsic::arm_uhsub16,   llvm::Intrinsic::arm_uhsub8, llvm::Intrinsic::arm_undefined, llvm::Intrinsic::arm_uqadd16, llvm::Intrinsic::arm_uqadd8,   llvm::Intrinsic::arm_uqasx, llvm::Intrinsic::arm_uqsax, llvm::Intrinsic::arm_uqsub16, llvm::Intrinsic::arm_uqsub8,   llvm::Intrinsic::arm_usad8, llvm::Intrinsic::arm_usada8, llvm::Intrinsic::arm_usat, llvm::Intrinsic::arm_usat16,   llvm::Intrinsic::arm_usax, llvm::Intrinsic::arm_usub16, llvm::Intrinsic::arm_usub8, llvm::Intrinsic::arm_uxtab16,   llvm::Intrinsic::arm_uxtb16, llvm::Intrinsic::arm_vcvtr, llvm::Intrinsic::arm_vcvtru, llvm::Intrinsic::bpf_load_byte,   llvm::Intrinsic::bpf_load_half, llvm::Intrinsic::bpf_load_word, llvm::Intrinsic::bpf_pseudo, llvm::Intrinsic::hexagon_A2_abs,   llvm::Intrinsic::hexagon_A2_absp, llvm::Intrinsic::hexagon_A2_abssat, llvm::Intrinsic::hexagon_A2_add, llvm::Intrinsic::hexagon_A2_addh_h16_hh,   llvm::Intrinsic::hexagon_A2_addh_h16_hl, llvm::Intrinsic::hexagon_A2_addh_h16_lh, llvm::Intrinsic::hexagon_A2_addh_h16_ll, llvm::Intrinsic::hexagon_A2_addh_h16_sat_hh,   llvm::Intrinsic::hexagon_A2_addh_h16_sat_hl, llvm::Intrinsic::hexagon_A2_addh_h16_sat_lh, llvm::Intrinsic::hexagon_A2_addh_h16_sat_ll, llvm::Intrinsic::hexagon_A2_addh_l16_hl,   llvm::Intrinsic::hexagon_A2_addh_l16_ll, llvm::Intrinsic::hexagon_A2_addh_l16_sat_hl, llvm::Intrinsic::hexagon_A2_addh_l16_sat_ll, llvm::Intrinsic::hexagon_A2_addi,   llvm::Intrinsic::hexagon_A2_addp, llvm::Intrinsic::hexagon_A2_addpsat, llvm::Intrinsic::hexagon_A2_addsat, llvm::Intrinsic::hexagon_A2_addsp,   llvm::Intrinsic::hexagon_A2_and, llvm::Intrinsic::hexagon_A2_andir, llvm::Intrinsic::hexagon_A2_andp, llvm::Intrinsic::hexagon_A2_aslh,   llvm::Intrinsic::hexagon_A2_asrh, llvm::Intrinsic::hexagon_A2_combine_hh, llvm::Intrinsic::hexagon_A2_combine_hl, llvm::Intrinsic::hexagon_A2_combine_lh,   llvm::Intrinsic::hexagon_A2_combine_ll, llvm::Intrinsic::hexagon_A2_combineii, llvm::Intrinsic::hexagon_A2_combinew, llvm::Intrinsic::hexagon_A2_max,   llvm::Intrinsic::hexagon_A2_maxp, llvm::Intrinsic::hexagon_A2_maxu, llvm::Intrinsic::hexagon_A2_maxup, llvm::Intrinsic::hexagon_A2_min,   llvm::Intrinsic::hexagon_A2_minp, llvm::Intrinsic::hexagon_A2_minu, llvm::Intrinsic::hexagon_A2_minup, llvm::Intrinsic::hexagon_A2_neg,   llvm::Intrinsic::hexagon_A2_negp, llvm::Intrinsic::hexagon_A2_negsat, llvm::Intrinsic::hexagon_A2_not, llvm::Intrinsic::hexagon_A2_notp,   llvm::Intrinsic::hexagon_A2_or, llvm::Intrinsic::hexagon_A2_orir, llvm::Intrinsic::hexagon_A2_orp, llvm::Intrinsic::hexagon_A2_pxorf,   llvm::Intrinsic::hexagon_A2_roundsat, llvm::Intrinsic::hexagon_A2_sat, llvm::Intrinsic::hexagon_A2_satb, llvm::Intrinsic::hexagon_A2_sath,   llvm::Intrinsic::hexagon_A2_satub, llvm::Intrinsic::hexagon_A2_satuh, llvm::Intrinsic::hexagon_A2_sub, llvm::Intrinsic::hexagon_A2_subh_h16_hh,   llvm::Intrinsic::hexagon_A2_subh_h16_hl, llvm::Intrinsic::hexagon_A2_subh_h16_lh, llvm::Intrinsic::hexagon_A2_subh_h16_ll, llvm::Intrinsic::hexagon_A2_subh_h16_sat_hh,   llvm::Intrinsic::hexagon_A2_subh_h16_sat_hl, llvm::Intrinsic::hexagon_A2_subh_h16_sat_lh, llvm::Intrinsic::hexagon_A2_subh_h16_sat_ll, llvm::Intrinsic::hexagon_A2_subh_l16_hl,   llvm::Intrinsic::hexagon_A2_subh_l16_ll, llvm::Intrinsic::hexagon_A2_subh_l16_sat_hl, llvm::Intrinsic::hexagon_A2_subh_l16_sat_ll, llvm::Intrinsic::hexagon_A2_subp,   llvm::Intrinsic::hexagon_A2_subri, llvm::Intrinsic::hexagon_A2_subsat, llvm::Intrinsic::hexagon_A2_svaddh, llvm::Intrinsic::hexagon_A2_svaddhs,   llvm::Intrinsic::hexagon_A2_svadduhs, llvm::Intrinsic::hexagon_A2_svavgh, llvm::Intrinsic::hexagon_A2_svavghs, llvm::Intrinsic::hexagon_A2_svnavgh,   llvm::Intrinsic::hexagon_A2_svsubh, llvm::Intrinsic::hexagon_A2_svsubhs, llvm::Intrinsic::hexagon_A2_svsubuhs, llvm::Intrinsic::hexagon_A2_swiz,   llvm::Intrinsic::hexagon_A2_sxtb, llvm::Intrinsic::hexagon_A2_sxth, llvm::Intrinsic::hexagon_A2_sxtw, llvm::Intrinsic::hexagon_A2_tfr,   llvm::Intrinsic::hexagon_A2_tfrcrr, llvm::Intrinsic::hexagon_A2_tfrih, llvm::Intrinsic::hexagon_A2_tfril, llvm::Intrinsic::hexagon_A2_tfrp,   llvm::Intrinsic::hexagon_A2_tfrpi, llvm::Intrinsic::hexagon_A2_tfrrcr, llvm::Intrinsic::hexagon_A2_tfrsi, llvm::Intrinsic::hexagon_A2_vabsh,   llvm::Intrinsic::hexagon_A2_vabshsat, llvm::Intrinsic::hexagon_A2_vabsw, llvm::Intrinsic::hexagon_A2_vabswsat, llvm::Intrinsic::hexagon_A2_vaddb_map,   llvm::Intrinsic::hexagon_A2_vaddh, llvm::Intrinsic::hexagon_A2_vaddhs, llvm::Intrinsic::hexagon_A2_vaddub, llvm::Intrinsic::hexagon_A2_vaddubs,   llvm::Intrinsic::hexagon_A2_vadduhs, llvm::Intrinsic::hexagon_A2_vaddw, llvm::Intrinsic::hexagon_A2_vaddws, llvm::Intrinsic::hexagon_A2_vavgh,   llvm::Intrinsic::hexagon_A2_vavghcr, llvm::Intrinsic::hexagon_A2_vavghr, llvm::Intrinsic::hexagon_A2_vavgub, llvm::Intrinsic::hexagon_A2_vavgubr,   llvm::Intrinsic::hexagon_A2_vavguh, llvm::Intrinsic::hexagon_A2_vavguhr, llvm::Intrinsic::hexagon_A2_vavguw, llvm::Intrinsic::hexagon_A2_vavguwr,   llvm::Intrinsic::hexagon_A2_vavgw, llvm::Intrinsic::hexagon_A2_vavgwcr, llvm::Intrinsic::hexagon_A2_vavgwr, llvm::Intrinsic::hexagon_A2_vcmpbeq,   llvm::Intrinsic::hexagon_A2_vcmpbgtu, llvm::Intrinsic::hexagon_A2_vcmpheq, llvm::Intrinsic::hexagon_A2_vcmphgt, llvm::Intrinsic::hexagon_A2_vcmphgtu,   llvm::Intrinsic::hexagon_A2_vcmpweq, llvm::Intrinsic::hexagon_A2_vcmpwgt, llvm::Intrinsic::hexagon_A2_vcmpwgtu, llvm::Intrinsic::hexagon_A2_vconj,   llvm::Intrinsic::hexagon_A2_vmaxb, llvm::Intrinsic::hexagon_A2_vmaxh, llvm::Intrinsic::hexagon_A2_vmaxub, llvm::Intrinsic::hexagon_A2_vmaxuh,   llvm::Intrinsic::hexagon_A2_vmaxuw, llvm::Intrinsic::hexagon_A2_vmaxw, llvm::Intrinsic::hexagon_A2_vminb, llvm::Intrinsic::hexagon_A2_vminh,   llvm::Intrinsic::hexagon_A2_vminub, llvm::Intrinsic::hexagon_A2_vminuh, llvm::Intrinsic::hexagon_A2_vminuw, llvm::Intrinsic::hexagon_A2_vminw,   llvm::Intrinsic::hexagon_A2_vnavgh, llvm::Intrinsic::hexagon_A2_vnavghcr, llvm::Intrinsic::hexagon_A2_vnavghr, llvm::Intrinsic::hexagon_A2_vnavgw,   llvm::Intrinsic::hexagon_A2_vnavgwcr, llvm::Intrinsic::hexagon_A2_vnavgwr, llvm::Intrinsic::hexagon_A2_vraddub, llvm::Intrinsic::hexagon_A2_vraddub_acc,   llvm::Intrinsic::hexagon_A2_vrsadub, llvm::Intrinsic::hexagon_A2_vrsadub_acc, llvm::Intrinsic::hexagon_A2_vsubb_map, llvm::Intrinsic::hexagon_A2_vsubh,   llvm::Intrinsic::hexagon_A2_vsubhs, llvm::Intrinsic::hexagon_A2_vsubub, llvm::Intrinsic::hexagon_A2_vsububs, llvm::Intrinsic::hexagon_A2_vsubuhs,   llvm::Intrinsic::hexagon_A2_vsubw, llvm::Intrinsic::hexagon_A2_vsubws, llvm::Intrinsic::hexagon_A2_xor, llvm::Intrinsic::hexagon_A2_xorp,   llvm::Intrinsic::hexagon_A2_zxtb, llvm::Intrinsic::hexagon_A2_zxth, llvm::Intrinsic::hexagon_A4_addp_c, llvm::Intrinsic::hexagon_A4_andn,   llvm::Intrinsic::hexagon_A4_andnp, llvm::Intrinsic::hexagon_A4_bitsplit, llvm::Intrinsic::hexagon_A4_bitspliti, llvm::Intrinsic::hexagon_A4_boundscheck,   llvm::Intrinsic::hexagon_A4_cmpbeq, llvm::Intrinsic::hexagon_A4_cmpbeqi, llvm::Intrinsic::hexagon_A4_cmpbgt, llvm::Intrinsic::hexagon_A4_cmpbgti,   llvm::Intrinsic::hexagon_A4_cmpbgtu, llvm::Intrinsic::hexagon_A4_cmpbgtui, llvm::Intrinsic::hexagon_A4_cmpheq, llvm::Intrinsic::hexagon_A4_cmpheqi,   llvm::Intrinsic::hexagon_A4_cmphgt, llvm::Intrinsic::hexagon_A4_cmphgti, llvm::Intrinsic::hexagon_A4_cmphgtu, llvm::Intrinsic::hexagon_A4_cmphgtui,   llvm::Intrinsic::hexagon_A4_combineii, llvm::Intrinsic::hexagon_A4_combineir, llvm::Intrinsic::hexagon_A4_combineri, llvm::Intrinsic::hexagon_A4_cround_ri,   llvm::Intrinsic::hexagon_A4_cround_rr, llvm::Intrinsic::hexagon_A4_modwrapu, llvm::Intrinsic::hexagon_A4_orn, llvm::Intrinsic::hexagon_A4_ornp,   llvm::Intrinsic::hexagon_A4_rcmpeq, llvm::Intrinsic::hexagon_A4_rcmpeqi, llvm::Intrinsic::hexagon_A4_rcmpneq, llvm::Intrinsic::hexagon_A4_rcmpneqi,   llvm::Intrinsic::hexagon_A4_round_ri, llvm::Intrinsic::hexagon_A4_round_ri_sat, llvm::Intrinsic::hexagon_A4_round_rr, llvm::Intrinsic::hexagon_A4_round_rr_sat,   llvm::Intrinsic::hexagon_A4_subp_c, llvm::Intrinsic::hexagon_A4_tfrcpp, llvm::Intrinsic::hexagon_A4_tfrpcp, llvm::Intrinsic::hexagon_A4_tlbmatch,   llvm::Intrinsic::hexagon_A4_vcmpbeq_any, llvm::Intrinsic::hexagon_A4_vcmpbeqi, llvm::Intrinsic::hexagon_A4_vcmpbgt, llvm::Intrinsic::hexagon_A4_vcmpbgti,   llvm::Intrinsic::hexagon_A4_vcmpbgtui, llvm::Intrinsic::hexagon_A4_vcmpheqi, llvm::Intrinsic::hexagon_A4_vcmphgti, llvm::Intrinsic::hexagon_A4_vcmphgtui,   llvm::Intrinsic::hexagon_A4_vcmpweqi, llvm::Intrinsic::hexagon_A4_vcmpwgti, llvm::Intrinsic::hexagon_A4_vcmpwgtui, llvm::Intrinsic::hexagon_A4_vrmaxh,   llvm::Intrinsic::hexagon_A4_vrmaxuh, llvm::Intrinsic::hexagon_A4_vrmaxuw, llvm::Intrinsic::hexagon_A4_vrmaxw, llvm::Intrinsic::hexagon_A4_vrminh,   llvm::Intrinsic::hexagon_A4_vrminuh, llvm::Intrinsic::hexagon_A4_vrminuw, llvm::Intrinsic::hexagon_A4_vrminw, llvm::Intrinsic::hexagon_A5_ACS,   llvm::Intrinsic::hexagon_A5_vaddhubs, llvm::Intrinsic::hexagon_A6_vcmpbeq_notany, llvm::Intrinsic::hexagon_A6_vminub_RdP, llvm::Intrinsic::hexagon_C2_all8,   llvm::Intrinsic::hexagon_C2_and, llvm::Intrinsic::hexagon_C2_andn, llvm::Intrinsic::hexagon_C2_any8, llvm::Intrinsic::hexagon_C2_bitsclr,   llvm::Intrinsic::hexagon_C2_bitsclri, llvm::Intrinsic::hexagon_C2_bitsset, llvm::Intrinsic::hexagon_C2_cmpeq, llvm::Intrinsic::hexagon_C2_cmpeqi,   llvm::Intrinsic::hexagon_C2_cmpeqp, llvm::Intrinsic::hexagon_C2_cmpgei, llvm::Intrinsic::hexagon_C2_cmpgeui, llvm::Intrinsic::hexagon_C2_cmpgt,   llvm::Intrinsic::hexagon_C2_cmpgti, llvm::Intrinsic::hexagon_C2_cmpgtp, llvm::Intrinsic::hexagon_C2_cmpgtu, llvm::Intrinsic::hexagon_C2_cmpgtui,   llvm::Intrinsic::hexagon_C2_cmpgtup, llvm::Intrinsic::hexagon_C2_cmplt, llvm::Intrinsic::hexagon_C2_cmpltu, llvm::Intrinsic::hexagon_C2_mask,   llvm::Intrinsic::hexagon_C2_mux, llvm::Intrinsic::hexagon_C2_muxii, llvm::Intrinsic::hexagon_C2_muxir, llvm::Intrinsic::hexagon_C2_muxri,   llvm::Intrinsic::hexagon_C2_not, llvm::Intrinsic::hexagon_C2_or, llvm::Intrinsic::hexagon_C2_orn, llvm::Intrinsic::hexagon_C2_pxfer_map,   llvm::Intrinsic::hexagon_C2_tfrpr, llvm::Intrinsic::hexagon_C2_tfrrp, llvm::Intrinsic::hexagon_C2_vitpack, llvm::Intrinsic::hexagon_C2_vmux,   llvm::Intrinsic::hexagon_C2_xor, llvm::Intrinsic::hexagon_C4_and_and, llvm::Intrinsic::hexagon_C4_and_andn, llvm::Intrinsic::hexagon_C4_and_or,   llvm::Intrinsic::hexagon_C4_and_orn, llvm::Intrinsic::hexagon_C4_cmplte, llvm::Intrinsic::hexagon_C4_cmpltei, llvm::Intrinsic::hexagon_C4_cmplteu,   llvm::Intrinsic::hexagon_C4_cmplteui, llvm::Intrinsic::hexagon_C4_cmpneq, llvm::Intrinsic::hexagon_C4_cmpneqi, llvm::Intrinsic::hexagon_C4_fastcorner9,   llvm::Intrinsic::hexagon_C4_fastcorner9_not, llvm::Intrinsic::hexagon_C4_nbitsclr, llvm::Intrinsic::hexagon_C4_nbitsclri, llvm::Intrinsic::hexagon_C4_nbitsset,   llvm::Intrinsic::hexagon_C4_or_and, llvm::Intrinsic::hexagon_C4_or_andn, llvm::Intrinsic::hexagon_C4_or_or, llvm::Intrinsic::hexagon_C4_or_orn,   llvm::Intrinsic::hexagon_F2_conv_d2df, llvm::Intrinsic::hexagon_F2_conv_d2sf, llvm::Intrinsic::hexagon_F2_conv_df2d, llvm::Intrinsic::hexagon_F2_conv_df2d_chop,   llvm::Intrinsic::hexagon_F2_conv_df2sf, llvm::Intrinsic::hexagon_F2_conv_df2ud, llvm::Intrinsic::hexagon_F2_conv_df2ud_chop, llvm::Intrinsic::hexagon_F2_conv_df2uw,   llvm::Intrinsic::hexagon_F2_conv_df2uw_chop, llvm::Intrinsic::hexagon_F2_conv_df2w, llvm::Intrinsic::hexagon_F2_conv_df2w_chop, llvm::Intrinsic::hexagon_F2_conv_sf2d,   llvm::Intrinsic::hexagon_F2_conv_sf2d_chop, llvm::Intrinsic::hexagon_F2_conv_sf2df, llvm::Intrinsic::hexagon_F2_conv_sf2ud, llvm::Intrinsic::hexagon_F2_conv_sf2ud_chop,   llvm::Intrinsic::hexagon_F2_conv_sf2uw, llvm::Intrinsic::hexagon_F2_conv_sf2uw_chop, llvm::Intrinsic::hexagon_F2_conv_sf2w, llvm::Intrinsic::hexagon_F2_conv_sf2w_chop,   llvm::Intrinsic::hexagon_F2_conv_ud2df, llvm::Intrinsic::hexagon_F2_conv_ud2sf, llvm::Intrinsic::hexagon_F2_conv_uw2df, llvm::Intrinsic::hexagon_F2_conv_uw2sf,   llvm::Intrinsic::hexagon_F2_conv_w2df, llvm::Intrinsic::hexagon_F2_conv_w2sf, llvm::Intrinsic::hexagon_F2_dfadd, llvm::Intrinsic::hexagon_F2_dfclass,   llvm::Intrinsic::hexagon_F2_dfcmpeq, llvm::Intrinsic::hexagon_F2_dfcmpge, llvm::Intrinsic::hexagon_F2_dfcmpgt, llvm::Intrinsic::hexagon_F2_dfcmpuo,   llvm::Intrinsic::hexagon_F2_dfimm_n, llvm::Intrinsic::hexagon_F2_dfimm_p, llvm::Intrinsic::hexagon_F2_dfsub, llvm::Intrinsic::hexagon_F2_sfadd,   llvm::Intrinsic::hexagon_F2_sfclass, llvm::Intrinsic::hexagon_F2_sfcmpeq, llvm::Intrinsic::hexagon_F2_sfcmpge, llvm::Intrinsic::hexagon_F2_sfcmpgt,   llvm::Intrinsic::hexagon_F2_sfcmpuo, llvm::Intrinsic::hexagon_F2_sffixupd, llvm::Intrinsic::hexagon_F2_sffixupn, llvm::Intrinsic::hexagon_F2_sffixupr,   llvm::Intrinsic::hexagon_F2_sffma, llvm::Intrinsic::hexagon_F2_sffma_lib, llvm::Intrinsic::hexagon_F2_sffma_sc, llvm::Intrinsic::hexagon_F2_sffms,   llvm::Intrinsic::hexagon_F2_sffms_lib, llvm::Intrinsic::hexagon_F2_sfimm_n, llvm::Intrinsic::hexagon_F2_sfimm_p, llvm::Intrinsic::hexagon_F2_sfinvsqrta,   llvm::Intrinsic::hexagon_F2_sfmax, llvm::Intrinsic::hexagon_F2_sfmin, llvm::Intrinsic::hexagon_F2_sfmpy, llvm::Intrinsic::hexagon_F2_sfrecipa,   llvm::Intrinsic::hexagon_F2_sfsub, llvm::Intrinsic::hexagon_L2_loadrb_pbr, llvm::Intrinsic::hexagon_L2_loadrb_pci, llvm::Intrinsic::hexagon_L2_loadrb_pcr,   llvm::Intrinsic::hexagon_L2_loadrd_pbr, llvm::Intrinsic::hexagon_L2_loadrd_pci, llvm::Intrinsic::hexagon_L2_loadrd_pcr, llvm::Intrinsic::hexagon_L2_loadrh_pbr,   llvm::Intrinsic::hexagon_L2_loadrh_pci, llvm::Intrinsic::hexagon_L2_loadrh_pcr, llvm::Intrinsic::hexagon_L2_loadri_pbr, llvm::Intrinsic::hexagon_L2_loadri_pci,   llvm::Intrinsic::hexagon_L2_loadri_pcr, llvm::Intrinsic::hexagon_L2_loadrub_pbr, llvm::Intrinsic::hexagon_L2_loadrub_pci, llvm::Intrinsic::hexagon_L2_loadrub_pcr,   llvm::Intrinsic::hexagon_L2_loadruh_pbr, llvm::Intrinsic::hexagon_L2_loadruh_pci, llvm::Intrinsic::hexagon_L2_loadruh_pcr, llvm::Intrinsic::hexagon_L2_loadw_locked,   llvm::Intrinsic::hexagon_L4_loadd_locked, llvm::Intrinsic::hexagon_M2_acci, llvm::Intrinsic::hexagon_M2_accii, llvm::Intrinsic::hexagon_M2_cmaci_s0,   llvm::Intrinsic::hexagon_M2_cmacr_s0, llvm::Intrinsic::hexagon_M2_cmacs_s0, llvm::Intrinsic::hexagon_M2_cmacs_s1, llvm::Intrinsic::hexagon_M2_cmacsc_s0,   llvm::Intrinsic::hexagon_M2_cmacsc_s1, llvm::Intrinsic::hexagon_M2_cmpyi_s0, llvm::Intrinsic::hexagon_M2_cmpyr_s0, llvm::Intrinsic::hexagon_M2_cmpyrs_s0,   llvm::Intrinsic::hexagon_M2_cmpyrs_s1, llvm::Intrinsic::hexagon_M2_cmpyrsc_s0, llvm::Intrinsic::hexagon_M2_cmpyrsc_s1, llvm::Intrinsic::hexagon_M2_cmpys_s0,   llvm::Intrinsic::hexagon_M2_cmpys_s1, llvm::Intrinsic::hexagon_M2_cmpysc_s0, llvm::Intrinsic::hexagon_M2_cmpysc_s1, llvm::Intrinsic::hexagon_M2_cnacs_s0,   llvm::Intrinsic::hexagon_M2_cnacs_s1, llvm::Intrinsic::hexagon_M2_cnacsc_s0, llvm::Intrinsic::hexagon_M2_cnacsc_s1, llvm::Intrinsic::hexagon_M2_dpmpyss_acc_s0,   llvm::Intrinsic::hexagon_M2_dpmpyss_nac_s0, llvm::Intrinsic::hexagon_M2_dpmpyss_rnd_s0, llvm::Intrinsic::hexagon_M2_dpmpyss_s0, llvm::Intrinsic::hexagon_M2_dpmpyuu_acc_s0,   llvm::Intrinsic::hexagon_M2_dpmpyuu_nac_s0, llvm::Intrinsic::hexagon_M2_dpmpyuu_s0, llvm::Intrinsic::hexagon_M2_hmmpyh_rs1, llvm::Intrinsic::hexagon_M2_hmmpyh_s1,   llvm::Intrinsic::hexagon_M2_hmmpyl_rs1, llvm::Intrinsic::hexagon_M2_hmmpyl_s1, llvm::Intrinsic::hexagon_M2_maci, llvm::Intrinsic::hexagon_M2_macsin,   llvm::Intrinsic::hexagon_M2_macsip, llvm::Intrinsic::hexagon_M2_mmachs_rs0, llvm::Intrinsic::hexagon_M2_mmachs_rs1, llvm::Intrinsic::hexagon_M2_mmachs_s0,   llvm::Intrinsic::hexagon_M2_mmachs_s1, llvm::Intrinsic::hexagon_M2_mmacls_rs0, llvm::Intrinsic::hexagon_M2_mmacls_rs1, llvm::Intrinsic::hexagon_M2_mmacls_s0,   llvm::Intrinsic::hexagon_M2_mmacls_s1, llvm::Intrinsic::hexagon_M2_mmacuhs_rs0, llvm::Intrinsic::hexagon_M2_mmacuhs_rs1, llvm::Intrinsic::hexagon_M2_mmacuhs_s0,   llvm::Intrinsic::hexagon_M2_mmacuhs_s1, llvm::Intrinsic::hexagon_M2_mmaculs_rs0, llvm::Intrinsic::hexagon_M2_mmaculs_rs1, llvm::Intrinsic::hexagon_M2_mmaculs_s0,   llvm::Intrinsic::hexagon_M2_mmaculs_s1, llvm::Intrinsic::hexagon_M2_mmpyh_rs0, llvm::Intrinsic::hexagon_M2_mmpyh_rs1, llvm::Intrinsic::hexagon_M2_mmpyh_s0,   llvm::Intrinsic::hexagon_M2_mmpyh_s1, llvm::Intrinsic::hexagon_M2_mmpyl_rs0, llvm::Intrinsic::hexagon_M2_mmpyl_rs1, llvm::Intrinsic::hexagon_M2_mmpyl_s0,   llvm::Intrinsic::hexagon_M2_mmpyl_s1, llvm::Intrinsic::hexagon_M2_mmpyuh_rs0, llvm::Intrinsic::hexagon_M2_mmpyuh_rs1, llvm::Intrinsic::hexagon_M2_mmpyuh_s0,   llvm::Intrinsic::hexagon_M2_mmpyuh_s1, llvm::Intrinsic::hexagon_M2_mmpyul_rs0, llvm::Intrinsic::hexagon_M2_mmpyul_rs1, llvm::Intrinsic::hexagon_M2_mmpyul_s0,   llvm::Intrinsic::hexagon_M2_mmpyul_s1, llvm::Intrinsic::hexagon_M2_mnaci, llvm::Intrinsic::hexagon_M2_mpy_acc_hh_s0, llvm::Intrinsic::hexagon_M2_mpy_acc_hh_s1,   llvm::Intrinsic::hexagon_M2_mpy_acc_hl_s0, llvm::Intrinsic::hexagon_M2_mpy_acc_hl_s1, llvm::Intrinsic::hexagon_M2_mpy_acc_lh_s0, llvm::Intrinsic::hexagon_M2_mpy_acc_lh_s1,   llvm::Intrinsic::hexagon_M2_mpy_acc_ll_s0, llvm::Intrinsic::hexagon_M2_mpy_acc_ll_s1, llvm::Intrinsic::hexagon_M2_mpy_acc_sat_hh_s0, llvm::Intrinsic::hexagon_M2_mpy_acc_sat_hh_s1,   llvm::Intrinsic::hexagon_M2_mpy_acc_sat_hl_s0, llvm::Intrinsic::hexagon_M2_mpy_acc_sat_hl_s1, llvm::Intrinsic::hexagon_M2_mpy_acc_sat_lh_s0, llvm::Intrinsic::hexagon_M2_mpy_acc_sat_lh_s1,   llvm::Intrinsic::hexagon_M2_mpy_acc_sat_ll_s0, llvm::Intrinsic::hexagon_M2_mpy_acc_sat_ll_s1, llvm::Intrinsic::hexagon_M2_mpy_hh_s0, llvm::Intrinsic::hexagon_M2_mpy_hh_s1,   llvm::Intrinsic::hexagon_M2_mpy_hl_s0, llvm::Intrinsic::hexagon_M2_mpy_hl_s1, llvm::Intrinsic::hexagon_M2_mpy_lh_s0, llvm::Intrinsic::hexagon_M2_mpy_lh_s1,   llvm::Intrinsic::hexagon_M2_mpy_ll_s0, llvm::Intrinsic::hexagon_M2_mpy_ll_s1, llvm::Intrinsic::hexagon_M2_mpy_nac_hh_s0, llvm::Intrinsic::hexagon_M2_mpy_nac_hh_s1,   llvm::Intrinsic::hexagon_M2_mpy_nac_hl_s0, llvm::Intrinsic::hexagon_M2_mpy_nac_hl_s1, llvm::Intrinsic::hexagon_M2_mpy_nac_lh_s0, llvm::Intrinsic::hexagon_M2_mpy_nac_lh_s1,   llvm::Intrinsic::hexagon_M2_mpy_nac_ll_s0, llvm::Intrinsic::hexagon_M2_mpy_nac_ll_s1, llvm::Intrinsic::hexagon_M2_mpy_nac_sat_hh_s0, llvm::Intrinsic::hexagon_M2_mpy_nac_sat_hh_s1,   llvm::Intrinsic::hexagon_M2_mpy_nac_sat_hl_s0, llvm::Intrinsic::hexagon_M2_mpy_nac_sat_hl_s1, llvm::Intrinsic::hexagon_M2_mpy_nac_sat_lh_s0, llvm::Intrinsic::hexagon_M2_mpy_nac_sat_lh_s1,   llvm::Intrinsic::hexagon_M2_mpy_nac_sat_ll_s0, llvm::Intrinsic::hexagon_M2_mpy_nac_sat_ll_s1, llvm::Intrinsic::hexagon_M2_mpy_rnd_hh_s0, llvm::Intrinsic::hexagon_M2_mpy_rnd_hh_s1,   llvm::Intrinsic::hexagon_M2_mpy_rnd_hl_s0, llvm::Intrinsic::hexagon_M2_mpy_rnd_hl_s1, llvm::Intrinsic::hexagon_M2_mpy_rnd_lh_s0, llvm::Intrinsic::hexagon_M2_mpy_rnd_lh_s1,   llvm::Intrinsic::hexagon_M2_mpy_rnd_ll_s0, llvm::Intrinsic::hexagon_M2_mpy_rnd_ll_s1, llvm::Intrinsic::hexagon_M2_mpy_sat_hh_s0, llvm::Intrinsic::hexagon_M2_mpy_sat_hh_s1,   llvm::Intrinsic::hexagon_M2_mpy_sat_hl_s0, llvm::Intrinsic::hexagon_M2_mpy_sat_hl_s1, llvm::Intrinsic::hexagon_M2_mpy_sat_lh_s0, llvm::Intrinsic::hexagon_M2_mpy_sat_lh_s1,   llvm::Intrinsic::hexagon_M2_mpy_sat_ll_s0, llvm::Intrinsic::hexagon_M2_mpy_sat_ll_s1, llvm::Intrinsic::hexagon_M2_mpy_sat_rnd_hh_s0, llvm::Intrinsic::hexagon_M2_mpy_sat_rnd_hh_s1,   llvm::Intrinsic::hexagon_M2_mpy_sat_rnd_hl_s0, llvm::Intrinsic::hexagon_M2_mpy_sat_rnd_hl_s1, llvm::Intrinsic::hexagon_M2_mpy_sat_rnd_lh_s0, llvm::Intrinsic::hexagon_M2_mpy_sat_rnd_lh_s1,   llvm::Intrinsic::hexagon_M2_mpy_sat_rnd_ll_s0, llvm::Intrinsic::hexagon_M2_mpy_sat_rnd_ll_s1, llvm::Intrinsic::hexagon_M2_mpy_up, llvm::Intrinsic::hexagon_M2_mpy_up_s1,   llvm::Intrinsic::hexagon_M2_mpy_up_s1_sat, llvm::Intrinsic::hexagon_M2_mpyd_acc_hh_s0, llvm::Intrinsic::hexagon_M2_mpyd_acc_hh_s1, llvm::Intrinsic::hexagon_M2_mpyd_acc_hl_s0,   llvm::Intrinsic::hexagon_M2_mpyd_acc_hl_s1, llvm::Intrinsic::hexagon_M2_mpyd_acc_lh_s0, llvm::Intrinsic::hexagon_M2_mpyd_acc_lh_s1, llvm::Intrinsic::hexagon_M2_mpyd_acc_ll_s0,   llvm::Intrinsic::hexagon_M2_mpyd_acc_ll_s1, llvm::Intrinsic::hexagon_M2_mpyd_hh_s0, llvm::Intrinsic::hexagon_M2_mpyd_hh_s1, llvm::Intrinsic::hexagon_M2_mpyd_hl_s0,   llvm::Intrinsic::hexagon_M2_mpyd_hl_s1, llvm::Intrinsic::hexagon_M2_mpyd_lh_s0, llvm::Intrinsic::hexagon_M2_mpyd_lh_s1, llvm::Intrinsic::hexagon_M2_mpyd_ll_s0,   llvm::Intrinsic::hexagon_M2_mpyd_ll_s1, llvm::Intrinsic::hexagon_M2_mpyd_nac_hh_s0, llvm::Intrinsic::hexagon_M2_mpyd_nac_hh_s1, llvm::Intrinsic::hexagon_M2_mpyd_nac_hl_s0,   llvm::Intrinsic::hexagon_M2_mpyd_nac_hl_s1, llvm::Intrinsic::hexagon_M2_mpyd_nac_lh_s0, llvm::Intrinsic::hexagon_M2_mpyd_nac_lh_s1, llvm::Intrinsic::hexagon_M2_mpyd_nac_ll_s0,   llvm::Intrinsic::hexagon_M2_mpyd_nac_ll_s1, llvm::Intrinsic::hexagon_M2_mpyd_rnd_hh_s0, llvm::Intrinsic::hexagon_M2_mpyd_rnd_hh_s1, llvm::Intrinsic::hexagon_M2_mpyd_rnd_hl_s0,   llvm::Intrinsic::hexagon_M2_mpyd_rnd_hl_s1, llvm::Intrinsic::hexagon_M2_mpyd_rnd_lh_s0, llvm::Intrinsic::hexagon_M2_mpyd_rnd_lh_s1, llvm::Intrinsic::hexagon_M2_mpyd_rnd_ll_s0,   llvm::Intrinsic::hexagon_M2_mpyd_rnd_ll_s1, llvm::Intrinsic::hexagon_M2_mpyi, llvm::Intrinsic::hexagon_M2_mpysin, llvm::Intrinsic::hexagon_M2_mpysip,   llvm::Intrinsic::hexagon_M2_mpysmi, llvm::Intrinsic::hexagon_M2_mpysu_up, llvm::Intrinsic::hexagon_M2_mpyu_acc_hh_s0, llvm::Intrinsic::hexagon_M2_mpyu_acc_hh_s1,   llvm::Intrinsic::hexagon_M2_mpyu_acc_hl_s0, llvm::Intrinsic::hexagon_M2_mpyu_acc_hl_s1, llvm::Intrinsic::hexagon_M2_mpyu_acc_lh_s0, llvm::Intrinsic::hexagon_M2_mpyu_acc_lh_s1,   llvm::Intrinsic::hexagon_M2_mpyu_acc_ll_s0, llvm::Intrinsic::hexagon_M2_mpyu_acc_ll_s1, llvm::Intrinsic::hexagon_M2_mpyu_hh_s0, llvm::Intrinsic::hexagon_M2_mpyu_hh_s1,   llvm::Intrinsic::hexagon_M2_mpyu_hl_s0, llvm::Intrinsic::hexagon_M2_mpyu_hl_s1, llvm::Intrinsic::hexagon_M2_mpyu_lh_s0, llvm::Intrinsic::hexagon_M2_mpyu_lh_s1,   llvm::Intrinsic::hexagon_M2_mpyu_ll_s0, llvm::Intrinsic::hexagon_M2_mpyu_ll_s1, llvm::Intrinsic::hexagon_M2_mpyu_nac_hh_s0, llvm::Intrinsic::hexagon_M2_mpyu_nac_hh_s1,   llvm::Intrinsic::hexagon_M2_mpyu_nac_hl_s0, llvm::Intrinsic::hexagon_M2_mpyu_nac_hl_s1, llvm::Intrinsic::hexagon_M2_mpyu_nac_lh_s0, llvm::Intrinsic::hexagon_M2_mpyu_nac_lh_s1,   llvm::Intrinsic::hexagon_M2_mpyu_nac_ll_s0, llvm::Intrinsic::hexagon_M2_mpyu_nac_ll_s1, llvm::Intrinsic::hexagon_M2_mpyu_up, llvm::Intrinsic::hexagon_M2_mpyud_acc_hh_s0,   llvm::Intrinsic::hexagon_M2_mpyud_acc_hh_s1, llvm::Intrinsic::hexagon_M2_mpyud_acc_hl_s0, llvm::Intrinsic::hexagon_M2_mpyud_acc_hl_s1, llvm::Intrinsic::hexagon_M2_mpyud_acc_lh_s0,   llvm::Intrinsic::hexagon_M2_mpyud_acc_lh_s1, llvm::Intrinsic::hexagon_M2_mpyud_acc_ll_s0, llvm::Intrinsic::hexagon_M2_mpyud_acc_ll_s1, llvm::Intrinsic::hexagon_M2_mpyud_hh_s0,   llvm::Intrinsic::hexagon_M2_mpyud_hh_s1, llvm::Intrinsic::hexagon_M2_mpyud_hl_s0, llvm::Intrinsic::hexagon_M2_mpyud_hl_s1, llvm::Intrinsic::hexagon_M2_mpyud_lh_s0,   llvm::Intrinsic::hexagon_M2_mpyud_lh_s1, llvm::Intrinsic::hexagon_M2_mpyud_ll_s0, llvm::Intrinsic::hexagon_M2_mpyud_ll_s1, llvm::Intrinsic::hexagon_M2_mpyud_nac_hh_s0,   llvm::Intrinsic::hexagon_M2_mpyud_nac_hh_s1, llvm::Intrinsic::hexagon_M2_mpyud_nac_hl_s0, llvm::Intrinsic::hexagon_M2_mpyud_nac_hl_s1, llvm::Intrinsic::hexagon_M2_mpyud_nac_lh_s0,   llvm::Intrinsic::hexagon_M2_mpyud_nac_lh_s1, llvm::Intrinsic::hexagon_M2_mpyud_nac_ll_s0, llvm::Intrinsic::hexagon_M2_mpyud_nac_ll_s1, llvm::Intrinsic::hexagon_M2_mpyui,   llvm::Intrinsic::hexagon_M2_nacci, llvm::Intrinsic::hexagon_M2_naccii, llvm::Intrinsic::hexagon_M2_subacc, llvm::Intrinsic::hexagon_M2_vabsdiffh,   llvm::Intrinsic::hexagon_M2_vabsdiffw, llvm::Intrinsic::hexagon_M2_vcmac_s0_sat_i, llvm::Intrinsic::hexagon_M2_vcmac_s0_sat_r, llvm::Intrinsic::hexagon_M2_vcmpy_s0_sat_i,   llvm::Intrinsic::hexagon_M2_vcmpy_s0_sat_r, llvm::Intrinsic::hexagon_M2_vcmpy_s1_sat_i, llvm::Intrinsic::hexagon_M2_vcmpy_s1_sat_r, llvm::Intrinsic::hexagon_M2_vdmacs_s0,   llvm::Intrinsic::hexagon_M2_vdmacs_s1, llvm::Intrinsic::hexagon_M2_vdmpyrs_s0, llvm::Intrinsic::hexagon_M2_vdmpyrs_s1, llvm::Intrinsic::hexagon_M2_vdmpys_s0,   llvm::Intrinsic::hexagon_M2_vdmpys_s1, llvm::Intrinsic::hexagon_M2_vmac2, llvm::Intrinsic::hexagon_M2_vmac2es, llvm::Intrinsic::hexagon_M2_vmac2es_s0,   llvm::Intrinsic::hexagon_M2_vmac2es_s1, llvm::Intrinsic::hexagon_M2_vmac2s_s0, llvm::Intrinsic::hexagon_M2_vmac2s_s1, llvm::Intrinsic::hexagon_M2_vmac2su_s0,   llvm::Intrinsic::hexagon_M2_vmac2su_s1, llvm::Intrinsic::hexagon_M2_vmpy2es_s0, llvm::Intrinsic::hexagon_M2_vmpy2es_s1, llvm::Intrinsic::hexagon_M2_vmpy2s_s0,   llvm::Intrinsic::hexagon_M2_vmpy2s_s0pack, llvm::Intrinsic::hexagon_M2_vmpy2s_s1, llvm::Intrinsic::hexagon_M2_vmpy2s_s1pack, llvm::Intrinsic::hexagon_M2_vmpy2su_s0,   llvm::Intrinsic::hexagon_M2_vmpy2su_s1, llvm::Intrinsic::hexagon_M2_vraddh, llvm::Intrinsic::hexagon_M2_vradduh, llvm::Intrinsic::hexagon_M2_vrcmaci_s0,   llvm::Intrinsic::hexagon_M2_vrcmaci_s0c, llvm::Intrinsic::hexagon_M2_vrcmacr_s0, llvm::Intrinsic::hexagon_M2_vrcmacr_s0c, llvm::Intrinsic::hexagon_M2_vrcmpyi_s0,   llvm::Intrinsic::hexagon_M2_vrcmpyi_s0c, llvm::Intrinsic::hexagon_M2_vrcmpyr_s0, llvm::Intrinsic::hexagon_M2_vrcmpyr_s0c, llvm::Intrinsic::hexagon_M2_vrcmpys_acc_s1,   llvm::Intrinsic::hexagon_M2_vrcmpys_s1, llvm::Intrinsic::hexagon_M2_vrcmpys_s1rp, llvm::Intrinsic::hexagon_M2_vrmac_s0, llvm::Intrinsic::hexagon_M2_vrmpy_s0,   llvm::Intrinsic::hexagon_M2_xor_xacc, llvm::Intrinsic::hexagon_M4_and_and, llvm::Intrinsic::hexagon_M4_and_andn, llvm::Intrinsic::hexagon_M4_and_or,   llvm::Intrinsic::hexagon_M4_and_xor, llvm::Intrinsic::hexagon_M4_cmpyi_wh, llvm::Intrinsic::hexagon_M4_cmpyi_whc, llvm::Intrinsic::hexagon_M4_cmpyr_wh,   llvm::Intrinsic::hexagon_M4_cmpyr_whc, llvm::Intrinsic::hexagon_M4_mac_up_s1_sat, llvm::Intrinsic::hexagon_M4_mpyri_addi, llvm::Intrinsic::hexagon_M4_mpyri_addr,   llvm::Intrinsic::hexagon_M4_mpyri_addr_u2, llvm::Intrinsic::hexagon_M4_mpyrr_addi, llvm::Intrinsic::hexagon_M4_mpyrr_addr, llvm::Intrinsic::hexagon_M4_nac_up_s1_sat,   llvm::Intrinsic::hexagon_M4_or_and, llvm::Intrinsic::hexagon_M4_or_andn, llvm::Intrinsic::hexagon_M4_or_or, llvm::Intrinsic::hexagon_M4_or_xor,   llvm::Intrinsic::hexagon_M4_pmpyw, llvm::Intrinsic::hexagon_M4_pmpyw_acc, llvm::Intrinsic::hexagon_M4_vpmpyh, llvm::Intrinsic::hexagon_M4_vpmpyh_acc,   llvm::Intrinsic::hexagon_M4_vrmpyeh_acc_s0, llvm::Intrinsic::hexagon_M4_vrmpyeh_acc_s1, llvm::Intrinsic::hexagon_M4_vrmpyeh_s0, llvm::Intrinsic::hexagon_M4_vrmpyeh_s1,   llvm::Intrinsic::hexagon_M4_vrmpyoh_acc_s0, llvm::Intrinsic::hexagon_M4_vrmpyoh_acc_s1, llvm::Intrinsic::hexagon_M4_vrmpyoh_s0, llvm::Intrinsic::hexagon_M4_vrmpyoh_s1,   llvm::Intrinsic::hexagon_M4_xor_and, llvm::Intrinsic::hexagon_M4_xor_andn, llvm::Intrinsic::hexagon_M4_xor_or, llvm::Intrinsic::hexagon_M4_xor_xacc,   llvm::Intrinsic::hexagon_M5_vdmacbsu, llvm::Intrinsic::hexagon_M5_vdmpybsu, llvm::Intrinsic::hexagon_M5_vmacbsu, llvm::Intrinsic::hexagon_M5_vmacbuu,   llvm::Intrinsic::hexagon_M5_vmpybsu, llvm::Intrinsic::hexagon_M5_vmpybuu, llvm::Intrinsic::hexagon_M5_vrmacbsu, llvm::Intrinsic::hexagon_M5_vrmacbuu,   llvm::Intrinsic::hexagon_M5_vrmpybsu, llvm::Intrinsic::hexagon_M5_vrmpybuu, llvm::Intrinsic::hexagon_M6_vabsdiffb, llvm::Intrinsic::hexagon_M6_vabsdiffub,   llvm::Intrinsic::hexagon_S2_addasl_rrri, llvm::Intrinsic::hexagon_S2_asl_i_p, llvm::Intrinsic::hexagon_S2_asl_i_p_acc, llvm::Intrinsic::hexagon_S2_asl_i_p_and,   llvm::Intrinsic::hexagon_S2_asl_i_p_nac, llvm::Intrinsic::hexagon_S2_asl_i_p_or, llvm::Intrinsic::hexagon_S2_asl_i_p_xacc, llvm::Intrinsic::hexagon_S2_asl_i_r,   llvm::Intrinsic::hexagon_S2_asl_i_r_acc, llvm::Intrinsic::hexagon_S2_asl_i_r_and, llvm::Intrinsic::hexagon_S2_asl_i_r_nac, llvm::Intrinsic::hexagon_S2_asl_i_r_or,   llvm::Intrinsic::hexagon_S2_asl_i_r_sat, llvm::Intrinsic::hexagon_S2_asl_i_r_xacc, llvm::Intrinsic::hexagon_S2_asl_i_vh, llvm::Intrinsic::hexagon_S2_asl_i_vw,   llvm::Intrinsic::hexagon_S2_asl_r_p, llvm::Intrinsic::hexagon_S2_asl_r_p_acc, llvm::Intrinsic::hexagon_S2_asl_r_p_and, llvm::Intrinsic::hexagon_S2_asl_r_p_nac,   llvm::Intrinsic::hexagon_S2_asl_r_p_or, llvm::Intrinsic::hexagon_S2_asl_r_p_xor, llvm::Intrinsic::hexagon_S2_asl_r_r, llvm::Intrinsic::hexagon_S2_asl_r_r_acc,   llvm::Intrinsic::hexagon_S2_asl_r_r_and, llvm::Intrinsic::hexagon_S2_asl_r_r_nac, llvm::Intrinsic::hexagon_S2_asl_r_r_or, llvm::Intrinsic::hexagon_S2_asl_r_r_sat,   llvm::Intrinsic::hexagon_S2_asl_r_vh, llvm::Intrinsic::hexagon_S2_asl_r_vw, llvm::Intrinsic::hexagon_S2_asr_i_p, llvm::Intrinsic::hexagon_S2_asr_i_p_acc,   llvm::Intrinsic::hexagon_S2_asr_i_p_and, llvm::Intrinsic::hexagon_S2_asr_i_p_nac, llvm::Intrinsic::hexagon_S2_asr_i_p_or, llvm::Intrinsic::hexagon_S2_asr_i_p_rnd,   llvm::Intrinsic::hexagon_S2_asr_i_p_rnd_goodsyntax, llvm::Intrinsic::hexagon_S2_asr_i_r, llvm::Intrinsic::hexagon_S2_asr_i_r_acc, llvm::Intrinsic::hexagon_S2_asr_i_r_and,   llvm::Intrinsic::hexagon_S2_asr_i_r_nac, llvm::Intrinsic::hexagon_S2_asr_i_r_or, llvm::Intrinsic::hexagon_S2_asr_i_r_rnd, llvm::Intrinsic::hexagon_S2_asr_i_r_rnd_goodsyntax,   llvm::Intrinsic::hexagon_S2_asr_i_svw_trun, llvm::Intrinsic::hexagon_S2_asr_i_vh, llvm::Intrinsic::hexagon_S2_asr_i_vw, llvm::Intrinsic::hexagon_S2_asr_r_p,   llvm::Intrinsic::hexagon_S2_asr_r_p_acc, llvm::Intrinsic::hexagon_S2_asr_r_p_and, llvm::Intrinsic::hexagon_S2_asr_r_p_nac, llvm::Intrinsic::hexagon_S2_asr_r_p_or,   llvm::Intrinsic::hexagon_S2_asr_r_p_xor, llvm::Intrinsic::hexagon_S2_asr_r_r, llvm::Intrinsic::hexagon_S2_asr_r_r_acc, llvm::Intrinsic::hexagon_S2_asr_r_r_and,   llvm::Intrinsic::hexagon_S2_asr_r_r_nac, llvm::Intrinsic::hexagon_S2_asr_r_r_or, llvm::Intrinsic::hexagon_S2_asr_r_r_sat, llvm::Intrinsic::hexagon_S2_asr_r_svw_trun,   llvm::Intrinsic::hexagon_S2_asr_r_vh, llvm::Intrinsic::hexagon_S2_asr_r_vw, llvm::Intrinsic::hexagon_S2_brev, llvm::Intrinsic::hexagon_S2_brevp,   llvm::Intrinsic::hexagon_S2_cl0, llvm::Intrinsic::hexagon_S2_cl0p, llvm::Intrinsic::hexagon_S2_cl1, llvm::Intrinsic::hexagon_S2_cl1p,   llvm::Intrinsic::hexagon_S2_clb, llvm::Intrinsic::hexagon_S2_clbnorm, llvm::Intrinsic::hexagon_S2_clbp, llvm::Intrinsic::hexagon_S2_clrbit_i,   llvm::Intrinsic::hexagon_S2_clrbit_r, llvm::Intrinsic::hexagon_S2_ct0, llvm::Intrinsic::hexagon_S2_ct0p, llvm::Intrinsic::hexagon_S2_ct1,   llvm::Intrinsic::hexagon_S2_ct1p, llvm::Intrinsic::hexagon_S2_deinterleave, llvm::Intrinsic::hexagon_S2_extractu, llvm::Intrinsic::hexagon_S2_extractu_rp,   llvm::Intrinsic::hexagon_S2_extractup, llvm::Intrinsic::hexagon_S2_extractup_rp, llvm::Intrinsic::hexagon_S2_insert, llvm::Intrinsic::hexagon_S2_insert_rp,   llvm::Intrinsic::hexagon_S2_insertp, llvm::Intrinsic::hexagon_S2_insertp_rp, llvm::Intrinsic::hexagon_S2_interleave, llvm::Intrinsic::hexagon_S2_lfsp,   llvm::Intrinsic::hexagon_S2_lsl_r_p, llvm::Intrinsic::hexagon_S2_lsl_r_p_acc, llvm::Intrinsic::hexagon_S2_lsl_r_p_and, llvm::Intrinsic::hexagon_S2_lsl_r_p_nac,   llvm::Intrinsic::hexagon_S2_lsl_r_p_or, llvm::Intrinsic::hexagon_S2_lsl_r_p_xor, llvm::Intrinsic::hexagon_S2_lsl_r_r, llvm::Intrinsic::hexagon_S2_lsl_r_r_acc,   llvm::Intrinsic::hexagon_S2_lsl_r_r_and, llvm::Intrinsic::hexagon_S2_lsl_r_r_nac, llvm::Intrinsic::hexagon_S2_lsl_r_r_or, llvm::Intrinsic::hexagon_S2_lsl_r_vh,   llvm::Intrinsic::hexagon_S2_lsl_r_vw, llvm::Intrinsic::hexagon_S2_lsr_i_p, llvm::Intrinsic::hexagon_S2_lsr_i_p_acc, llvm::Intrinsic::hexagon_S2_lsr_i_p_and,   llvm::Intrinsic::hexagon_S2_lsr_i_p_nac, llvm::Intrinsic::hexagon_S2_lsr_i_p_or, llvm::Intrinsic::hexagon_S2_lsr_i_p_xacc, llvm::Intrinsic::hexagon_S2_lsr_i_r,   llvm::Intrinsic::hexagon_S2_lsr_i_r_acc, llvm::Intrinsic::hexagon_S2_lsr_i_r_and, llvm::Intrinsic::hexagon_S2_lsr_i_r_nac, llvm::Intrinsic::hexagon_S2_lsr_i_r_or,   llvm::Intrinsic::hexagon_S2_lsr_i_r_xacc, llvm::Intrinsic::hexagon_S2_lsr_i_vh, llvm::Intrinsic::hexagon_S2_lsr_i_vw, llvm::Intrinsic::hexagon_S2_lsr_r_p,   llvm::Intrinsic::hexagon_S2_lsr_r_p_acc, llvm::Intrinsic::hexagon_S2_lsr_r_p_and, llvm::Intrinsic::hexagon_S2_lsr_r_p_nac, llvm::Intrinsic::hexagon_S2_lsr_r_p_or,   llvm::Intrinsic::hexagon_S2_lsr_r_p_xor, llvm::Intrinsic::hexagon_S2_lsr_r_r, llvm::Intrinsic::hexagon_S2_lsr_r_r_acc, llvm::Intrinsic::hexagon_S2_lsr_r_r_and,   llvm::Intrinsic::hexagon_S2_lsr_r_r_nac, llvm::Intrinsic::hexagon_S2_lsr_r_r_or, llvm::Intrinsic::hexagon_S2_lsr_r_vh, llvm::Intrinsic::hexagon_S2_lsr_r_vw,   llvm::Intrinsic::hexagon_S2_mask, llvm::Intrinsic::hexagon_S2_packhl, llvm::Intrinsic::hexagon_S2_parityp, llvm::Intrinsic::hexagon_S2_setbit_i,   llvm::Intrinsic::hexagon_S2_setbit_r, llvm::Intrinsic::hexagon_S2_shuffeb, llvm::Intrinsic::hexagon_S2_shuffeh, llvm::Intrinsic::hexagon_S2_shuffob,   llvm::Intrinsic::hexagon_S2_shuffoh, llvm::Intrinsic::hexagon_S2_storerb_pbr, llvm::Intrinsic::hexagon_S2_storerb_pci, llvm::Intrinsic::hexagon_S2_storerb_pcr,   llvm::Intrinsic::hexagon_S2_storerd_pbr, llvm::Intrinsic::hexagon_S2_storerd_pci, llvm::Intrinsic::hexagon_S2_storerd_pcr, llvm::Intrinsic::hexagon_S2_storerf_pbr,   llvm::Intrinsic::hexagon_S2_storerf_pci, llvm::Intrinsic::hexagon_S2_storerf_pcr, llvm::Intrinsic::hexagon_S2_storerh_pbr, llvm::Intrinsic::hexagon_S2_storerh_pci,   llvm::Intrinsic::hexagon_S2_storerh_pcr, llvm::Intrinsic::hexagon_S2_storeri_pbr, llvm::Intrinsic::hexagon_S2_storeri_pci, llvm::Intrinsic::hexagon_S2_storeri_pcr,   llvm::Intrinsic::hexagon_S2_storew_locked, llvm::Intrinsic::hexagon_S2_svsathb, llvm::Intrinsic::hexagon_S2_svsathub, llvm::Intrinsic::hexagon_S2_tableidxb_goodsyntax,   llvm::Intrinsic::hexagon_S2_tableidxd_goodsyntax, llvm::Intrinsic::hexagon_S2_tableidxh_goodsyntax, llvm::Intrinsic::hexagon_S2_tableidxw_goodsyntax, llvm::Intrinsic::hexagon_S2_togglebit_i,   llvm::Intrinsic::hexagon_S2_togglebit_r, llvm::Intrinsic::hexagon_S2_tstbit_i, llvm::Intrinsic::hexagon_S2_tstbit_r, llvm::Intrinsic::hexagon_S2_valignib,   llvm::Intrinsic::hexagon_S2_valignrb, llvm::Intrinsic::hexagon_S2_vcnegh, llvm::Intrinsic::hexagon_S2_vcrotate, llvm::Intrinsic::hexagon_S2_vrcnegh,   llvm::Intrinsic::hexagon_S2_vrndpackwh, llvm::Intrinsic::hexagon_S2_vrndpackwhs, llvm::Intrinsic::hexagon_S2_vsathb, llvm::Intrinsic::hexagon_S2_vsathb_nopack,   llvm::Intrinsic::hexagon_S2_vsathub, llvm::Intrinsic::hexagon_S2_vsathub_nopack, llvm::Intrinsic::hexagon_S2_vsatwh, llvm::Intrinsic::hexagon_S2_vsatwh_nopack,   llvm::Intrinsic::hexagon_S2_vsatwuh, llvm::Intrinsic::hexagon_S2_vsatwuh_nopack, llvm::Intrinsic::hexagon_S2_vsplatrb, llvm::Intrinsic::hexagon_S2_vsplatrh,   llvm::Intrinsic::hexagon_S2_vspliceib, llvm::Intrinsic::hexagon_S2_vsplicerb, llvm::Intrinsic::hexagon_S2_vsxtbh, llvm::Intrinsic::hexagon_S2_vsxthw,   llvm::Intrinsic::hexagon_S2_vtrunehb, llvm::Intrinsic::hexagon_S2_vtrunewh, llvm::Intrinsic::hexagon_S2_vtrunohb, llvm::Intrinsic::hexagon_S2_vtrunowh,   llvm::Intrinsic::hexagon_S2_vzxtbh, llvm::Intrinsic::hexagon_S2_vzxthw, llvm::Intrinsic::hexagon_S4_addaddi, llvm::Intrinsic::hexagon_S4_addi_asl_ri,   llvm::Intrinsic::hexagon_S4_addi_lsr_ri, llvm::Intrinsic::hexagon_S4_andi_asl_ri, llvm::Intrinsic::hexagon_S4_andi_lsr_ri, llvm::Intrinsic::hexagon_S4_clbaddi,   llvm::Intrinsic::hexagon_S4_clbpaddi, llvm::Intrinsic::hexagon_S4_clbpnorm, llvm::Intrinsic::hexagon_S4_extract, llvm::Intrinsic::hexagon_S4_extract_rp,   llvm::Intrinsic::hexagon_S4_extractp, llvm::Intrinsic::hexagon_S4_extractp_rp, llvm::Intrinsic::hexagon_S4_lsli, llvm::Intrinsic::hexagon_S4_ntstbit_i,   llvm::Intrinsic::hexagon_S4_ntstbit_r, llvm::Intrinsic::hexagon_S4_or_andi, llvm::Intrinsic::hexagon_S4_or_andix, llvm::Intrinsic::hexagon_S4_or_ori,   llvm::Intrinsic::hexagon_S4_ori_asl_ri, llvm::Intrinsic::hexagon_S4_ori_lsr_ri, llvm::Intrinsic::hexagon_S4_parity, llvm::Intrinsic::hexagon_S4_stored_locked,   llvm::Intrinsic::hexagon_S4_subaddi, llvm::Intrinsic::hexagon_S4_subi_asl_ri, llvm::Intrinsic::hexagon_S4_subi_lsr_ri, llvm::Intrinsic::hexagon_S4_vrcrotate,   llvm::Intrinsic::hexagon_S4_vrcrotate_acc, llvm::Intrinsic::hexagon_S4_vxaddsubh, llvm::Intrinsic::hexagon_S4_vxaddsubhr, llvm::Intrinsic::hexagon_S4_vxaddsubw,   llvm::Intrinsic::hexagon_S4_vxsubaddh, llvm::Intrinsic::hexagon_S4_vxsubaddhr, llvm::Intrinsic::hexagon_S4_vxsubaddw, llvm::Intrinsic::hexagon_S5_asrhub_rnd_sat_goodsyntax,   llvm::Intrinsic::hexagon_S5_asrhub_sat, llvm::Intrinsic::hexagon_S5_popcountp, llvm::Intrinsic::hexagon_S5_vasrhrnd_goodsyntax, llvm::Intrinsic::hexagon_S6_rol_i_p,   llvm::Intrinsic::hexagon_S6_rol_i_p_acc, llvm::Intrinsic::hexagon_S6_rol_i_p_and, llvm::Intrinsic::hexagon_S6_rol_i_p_nac, llvm::Intrinsic::hexagon_S6_rol_i_p_or,   llvm::Intrinsic::hexagon_S6_rol_i_p_xacc, llvm::Intrinsic::hexagon_S6_rol_i_r, llvm::Intrinsic::hexagon_S6_rol_i_r_acc, llvm::Intrinsic::hexagon_S6_rol_i_r_and,   llvm::Intrinsic::hexagon_S6_rol_i_r_nac, llvm::Intrinsic::hexagon_S6_rol_i_r_or, llvm::Intrinsic::hexagon_S6_rol_i_r_xacc, llvm::Intrinsic::hexagon_S6_vsplatrbp,   llvm::Intrinsic::hexagon_S6_vtrunehb_ppp, llvm::Intrinsic::hexagon_S6_vtrunohb_ppp, llvm::Intrinsic::hexagon_V6_extractw, llvm::Intrinsic::hexagon_V6_extractw_128B,   llvm::Intrinsic::hexagon_V6_hi, llvm::Intrinsic::hexagon_V6_hi_128B, llvm::Intrinsic::hexagon_V6_ld0, llvm::Intrinsic::hexagon_V6_ld0_128B,   llvm::Intrinsic::hexagon_V6_ldcnp0, llvm::Intrinsic::hexagon_V6_ldcnp0_128B, llvm::Intrinsic::hexagon_V6_ldcnpnt0, llvm::Intrinsic::hexagon_V6_ldcnpnt0_128B,   llvm::Intrinsic::hexagon_V6_ldcp0, llvm::Intrinsic::hexagon_V6_ldcp0_128B, llvm::Intrinsic::hexagon_V6_ldcpnt0, llvm::Intrinsic::hexagon_V6_ldcpnt0_128B,   llvm::Intrinsic::hexagon_V6_ldnp0, llvm::Intrinsic::hexagon_V6_ldnp0_128B, llvm::Intrinsic::hexagon_V6_ldnpnt0, llvm::Intrinsic::hexagon_V6_ldnpnt0_128B,   llvm::Intrinsic::hexagon_V6_ldnt0, llvm::Intrinsic::hexagon_V6_ldnt0_128B, llvm::Intrinsic::hexagon_V6_ldntnt0, llvm::Intrinsic::hexagon_V6_ldp0,   llvm::Intrinsic::hexagon_V6_ldp0_128B, llvm::Intrinsic::hexagon_V6_ldpnt0, llvm::Intrinsic::hexagon_V6_ldpnt0_128B, llvm::Intrinsic::hexagon_V6_ldtnp0,   llvm::Intrinsic::hexagon_V6_ldtnp0_128B, llvm::Intrinsic::hexagon_V6_ldtnpnt0, llvm::Intrinsic::hexagon_V6_ldtnpnt0_128B, llvm::Intrinsic::hexagon_V6_ldtp0,   llvm::Intrinsic::hexagon_V6_ldtp0_128B, llvm::Intrinsic::hexagon_V6_ldtpnt0, llvm::Intrinsic::hexagon_V6_ldtpnt0_128B, llvm::Intrinsic::hexagon_V6_ldu0,   llvm::Intrinsic::hexagon_V6_ldu0_128B, llvm::Intrinsic::hexagon_V6_lo, llvm::Intrinsic::hexagon_V6_lo_128B, llvm::Intrinsic::hexagon_V6_lvsplatb,   llvm::Intrinsic::hexagon_V6_lvsplatb_128B, llvm::Intrinsic::hexagon_V6_lvsplath, llvm::Intrinsic::hexagon_V6_lvsplath_128B, llvm::Intrinsic::hexagon_V6_lvsplatw,   llvm::Intrinsic::hexagon_V6_lvsplatw_128B, llvm::Intrinsic::hexagon_V6_pred_and, llvm::Intrinsic::hexagon_V6_pred_and_128B, llvm::Intrinsic::hexagon_V6_pred_and_n,   llvm::Intrinsic::hexagon_V6_pred_and_n_128B, llvm::Intrinsic::hexagon_V6_pred_not, llvm::Intrinsic::hexagon_V6_pred_not_128B, llvm::Intrinsic::hexagon_V6_pred_or,   llvm::Intrinsic::hexagon_V6_pred_or_128B, llvm::Intrinsic::hexagon_V6_pred_or_n, llvm::Intrinsic::hexagon_V6_pred_or_n_128B, llvm::Intrinsic::hexagon_V6_pred_scalar2,   llvm::Intrinsic::hexagon_V6_pred_scalar2_128B, llvm::Intrinsic::hexagon_V6_pred_scalar2v2, llvm::Intrinsic::hexagon_V6_pred_scalar2v2_128B, llvm::Intrinsic::hexagon_V6_pred_xor,   llvm::Intrinsic::hexagon_V6_pred_xor_128B, llvm::Intrinsic::hexagon_V6_shuffeqh, llvm::Intrinsic::hexagon_V6_shuffeqh_128B, llvm::Intrinsic::hexagon_V6_shuffeqw,   llvm::Intrinsic::hexagon_V6_shuffeqw_128B, llvm::Intrinsic::hexagon_V6_vS32b_nqpred_ai, llvm::Intrinsic::hexagon_V6_vS32b_nqpred_ai_128B, llvm::Intrinsic::hexagon_V6_vS32b_nt_nqpred_ai,   llvm::Intrinsic::hexagon_V6_vS32b_nt_nqpred_ai_128B, llvm::Intrinsic::hexagon_V6_vS32b_nt_qpred_ai, llvm::Intrinsic::hexagon_V6_vS32b_nt_qpred_ai_128B, llvm::Intrinsic::hexagon_V6_vS32b_qpred_ai,   llvm::Intrinsic::hexagon_V6_vS32b_qpred_ai_128B, llvm::Intrinsic::hexagon_V6_vabsb, llvm::Intrinsic::hexagon_V6_vabsb_128B, llvm::Intrinsic::hexagon_V6_vabsb_sat,   llvm::Intrinsic::hexagon_V6_vabsb_sat_128B, llvm::Intrinsic::hexagon_V6_vabsdiffh, llvm::Intrinsic::hexagon_V6_vabsdiffh_128B, llvm::Intrinsic::hexagon_V6_vabsdiffub,   llvm::Intrinsic::hexagon_V6_vabsdiffub_128B, llvm::Intrinsic::hexagon_V6_vabsdiffuh, llvm::Intrinsic::hexagon_V6_vabsdiffuh_128B, llvm::Intrinsic::hexagon_V6_vabsdiffw,   llvm::Intrinsic::hexagon_V6_vabsdiffw_128B, llvm::Intrinsic::hexagon_V6_vabsh, llvm::Intrinsic::hexagon_V6_vabsh_128B, llvm::Intrinsic::hexagon_V6_vabsh_sat,   llvm::Intrinsic::hexagon_V6_vabsh_sat_128B, llvm::Intrinsic::hexagon_V6_vabsw, llvm::Intrinsic::hexagon_V6_vabsw_128B, llvm::Intrinsic::hexagon_V6_vabsw_sat,   llvm::Intrinsic::hexagon_V6_vabsw_sat_128B, llvm::Intrinsic::hexagon_V6_vaddb, llvm::Intrinsic::hexagon_V6_vaddb_128B, llvm::Intrinsic::hexagon_V6_vaddb_dv,   llvm::Intrinsic::hexagon_V6_vaddb_dv_128B, llvm::Intrinsic::hexagon_V6_vaddbnq, llvm::Intrinsic::hexagon_V6_vaddbnq_128B, llvm::Intrinsic::hexagon_V6_vaddbq,   llvm::Intrinsic::hexagon_V6_vaddbq_128B, llvm::Intrinsic::hexagon_V6_vaddbsat, llvm::Intrinsic::hexagon_V6_vaddbsat_128B, llvm::Intrinsic::hexagon_V6_vaddbsat_dv,   llvm::Intrinsic::hexagon_V6_vaddbsat_dv_128B, llvm::Intrinsic::hexagon_V6_vaddcarry, llvm::Intrinsic::hexagon_V6_vaddcarry_128B, llvm::Intrinsic::hexagon_V6_vaddcarrysat,   llvm::Intrinsic::hexagon_V6_vaddcarrysat_128B, llvm::Intrinsic::hexagon_V6_vaddclbh, llvm::Intrinsic::hexagon_V6_vaddclbh_128B, llvm::Intrinsic::hexagon_V6_vaddclbw,   llvm::Intrinsic::hexagon_V6_vaddclbw_128B, llvm::Intrinsic::hexagon_V6_vaddh, llvm::Intrinsic::hexagon_V6_vaddh_128B, llvm::Intrinsic::hexagon_V6_vaddh_dv,   llvm::Intrinsic::hexagon_V6_vaddh_dv_128B, llvm::Intrinsic::hexagon_V6_vaddhnq, llvm::Intrinsic::hexagon_V6_vaddhnq_128B, llvm::Intrinsic::hexagon_V6_vaddhq,   llvm::Intrinsic::hexagon_V6_vaddhq_128B, llvm::Intrinsic::hexagon_V6_vaddhsat, llvm::Intrinsic::hexagon_V6_vaddhsat_128B, llvm::Intrinsic::hexagon_V6_vaddhsat_dv,   llvm::Intrinsic::hexagon_V6_vaddhsat_dv_128B, llvm::Intrinsic::hexagon_V6_vaddhw, llvm::Intrinsic::hexagon_V6_vaddhw_128B, llvm::Intrinsic::hexagon_V6_vaddhw_acc,   llvm::Intrinsic::hexagon_V6_vaddhw_acc_128B, llvm::Intrinsic::hexagon_V6_vaddubh, llvm::Intrinsic::hexagon_V6_vaddubh_128B, llvm::Intrinsic::hexagon_V6_vaddubh_acc,   llvm::Intrinsic::hexagon_V6_vaddubh_acc_128B, llvm::Intrinsic::hexagon_V6_vaddubsat, llvm::Intrinsic::hexagon_V6_vaddubsat_128B, llvm::Intrinsic::hexagon_V6_vaddubsat_dv,   llvm::Intrinsic::hexagon_V6_vaddubsat_dv_128B, llvm::Intrinsic::hexagon_V6_vaddububb_sat, llvm::Intrinsic::hexagon_V6_vaddububb_sat_128B, llvm::Intrinsic::hexagon_V6_vadduhsat,   llvm::Intrinsic::hexagon_V6_vadduhsat_128B, llvm::Intrinsic::hexagon_V6_vadduhsat_dv, llvm::Intrinsic::hexagon_V6_vadduhsat_dv_128B, llvm::Intrinsic::hexagon_V6_vadduhw,   llvm::Intrinsic::hexagon_V6_vadduhw_128B, llvm::Intrinsic::hexagon_V6_vadduhw_acc, llvm::Intrinsic::hexagon_V6_vadduhw_acc_128B, llvm::Intrinsic::hexagon_V6_vadduwsat,   llvm::Intrinsic::hexagon_V6_vadduwsat_128B, llvm::Intrinsic::hexagon_V6_vadduwsat_dv, llvm::Intrinsic::hexagon_V6_vadduwsat_dv_128B, llvm::Intrinsic::hexagon_V6_vaddw,   llvm::Intrinsic::hexagon_V6_vaddw_128B, llvm::Intrinsic::hexagon_V6_vaddw_dv, llvm::Intrinsic::hexagon_V6_vaddw_dv_128B, llvm::Intrinsic::hexagon_V6_vaddwnq,   llvm::Intrinsic::hexagon_V6_vaddwnq_128B, llvm::Intrinsic::hexagon_V6_vaddwq, llvm::Intrinsic::hexagon_V6_vaddwq_128B, llvm::Intrinsic::hexagon_V6_vaddwsat,   llvm::Intrinsic::hexagon_V6_vaddwsat_128B, llvm::Intrinsic::hexagon_V6_vaddwsat_dv, llvm::Intrinsic::hexagon_V6_vaddwsat_dv_128B, llvm::Intrinsic::hexagon_V6_valignb,   llvm::Intrinsic::hexagon_V6_valignb_128B, llvm::Intrinsic::hexagon_V6_valignbi, llvm::Intrinsic::hexagon_V6_valignbi_128B, llvm::Intrinsic::hexagon_V6_vand,   llvm::Intrinsic::hexagon_V6_vand_128B, llvm::Intrinsic::hexagon_V6_vandnqrt, llvm::Intrinsic::hexagon_V6_vandnqrt_128B, llvm::Intrinsic::hexagon_V6_vandnqrt_acc,   llvm::Intrinsic::hexagon_V6_vandnqrt_acc_128B, llvm::Intrinsic::hexagon_V6_vandqrt, llvm::Intrinsic::hexagon_V6_vandqrt_128B, llvm::Intrinsic::hexagon_V6_vandqrt_acc,   llvm::Intrinsic::hexagon_V6_vandqrt_acc_128B, llvm::Intrinsic::hexagon_V6_vandvnqv, llvm::Intrinsic::hexagon_V6_vandvnqv_128B, llvm::Intrinsic::hexagon_V6_vandvqv,   llvm::Intrinsic::hexagon_V6_vandvqv_128B, llvm::Intrinsic::hexagon_V6_vandvrt, llvm::Intrinsic::hexagon_V6_vandvrt_128B, llvm::Intrinsic::hexagon_V6_vandvrt_acc,   llvm::Intrinsic::hexagon_V6_vandvrt_acc_128B, llvm::Intrinsic::hexagon_V6_vaslh, llvm::Intrinsic::hexagon_V6_vaslh_128B, llvm::Intrinsic::hexagon_V6_vaslh_acc,   llvm::Intrinsic::hexagon_V6_vaslh_acc_128B, llvm::Intrinsic::hexagon_V6_vaslhv, llvm::Intrinsic::hexagon_V6_vaslhv_128B, llvm::Intrinsic::hexagon_V6_vaslw,   llvm::Intrinsic::hexagon_V6_vaslw_128B, llvm::Intrinsic::hexagon_V6_vaslw_acc, llvm::Intrinsic::hexagon_V6_vaslw_acc_128B, llvm::Intrinsic::hexagon_V6_vaslwv,   llvm::Intrinsic::hexagon_V6_vaslwv_128B, llvm::Intrinsic::hexagon_V6_vasr_into, llvm::Intrinsic::hexagon_V6_vasr_into_128B, llvm::Intrinsic::hexagon_V6_vasrh,   llvm::Intrinsic::hexagon_V6_vasrh_128B, llvm::Intrinsic::hexagon_V6_vasrh_acc, llvm::Intrinsic::hexagon_V6_vasrh_acc_128B, llvm::Intrinsic::hexagon_V6_vasrhbrndsat,   llvm::Intrinsic::hexagon_V6_vasrhbrndsat_128B, llvm::Intrinsic::hexagon_V6_vasrhbsat, llvm::Intrinsic::hexagon_V6_vasrhbsat_128B, llvm::Intrinsic::hexagon_V6_vasrhubrndsat,   llvm::Intrinsic::hexagon_V6_vasrhubrndsat_128B, llvm::Intrinsic::hexagon_V6_vasrhubsat, llvm::Intrinsic::hexagon_V6_vasrhubsat_128B, llvm::Intrinsic::hexagon_V6_vasrhv,   llvm::Intrinsic::hexagon_V6_vasrhv_128B, llvm::Intrinsic::hexagon_V6_vasruhubrndsat, llvm::Intrinsic::hexagon_V6_vasruhubrndsat_128B, llvm::Intrinsic::hexagon_V6_vasruhubsat,   llvm::Intrinsic::hexagon_V6_vasruhubsat_128B, llvm::Intrinsic::hexagon_V6_vasruwuhrndsat, llvm::Intrinsic::hexagon_V6_vasruwuhrndsat_128B, llvm::Intrinsic::hexagon_V6_vasruwuhsat,   llvm::Intrinsic::hexagon_V6_vasruwuhsat_128B, llvm::Intrinsic::hexagon_V6_vasrw, llvm::Intrinsic::hexagon_V6_vasrw_128B, llvm::Intrinsic::hexagon_V6_vasrw_acc,   llvm::Intrinsic::hexagon_V6_vasrw_acc_128B, llvm::Intrinsic::hexagon_V6_vasrwh, llvm::Intrinsic::hexagon_V6_vasrwh_128B, llvm::Intrinsic::hexagon_V6_vasrwhrndsat,   llvm::Intrinsic::hexagon_V6_vasrwhrndsat_128B, llvm::Intrinsic::hexagon_V6_vasrwhsat, llvm::Intrinsic::hexagon_V6_vasrwhsat_128B, llvm::Intrinsic::hexagon_V6_vasrwuhrndsat,   llvm::Intrinsic::hexagon_V6_vasrwuhrndsat_128B, llvm::Intrinsic::hexagon_V6_vasrwuhsat, llvm::Intrinsic::hexagon_V6_vasrwuhsat_128B, llvm::Intrinsic::hexagon_V6_vasrwv,   llvm::Intrinsic::hexagon_V6_vasrwv_128B, llvm::Intrinsic::hexagon_V6_vassign, llvm::Intrinsic::hexagon_V6_vassign_128B, llvm::Intrinsic::hexagon_V6_vassignp,   llvm::Intrinsic::hexagon_V6_vassignp_128B, llvm::Intrinsic::hexagon_V6_vavgb, llvm::Intrinsic::hexagon_V6_vavgb_128B, llvm::Intrinsic::hexagon_V6_vavgbrnd,   llvm::Intrinsic::hexagon_V6_vavgbrnd_128B, llvm::Intrinsic::hexagon_V6_vavgh, llvm::Intrinsic::hexagon_V6_vavgh_128B, llvm::Intrinsic::hexagon_V6_vavghrnd,   llvm::Intrinsic::hexagon_V6_vavghrnd_128B, llvm::Intrinsic::hexagon_V6_vavgub, llvm::Intrinsic::hexagon_V6_vavgub_128B, llvm::Intrinsic::hexagon_V6_vavgubrnd,   llvm::Intrinsic::hexagon_V6_vavgubrnd_128B, llvm::Intrinsic::hexagon_V6_vavguh, llvm::Intrinsic::hexagon_V6_vavguh_128B, llvm::Intrinsic::hexagon_V6_vavguhrnd,   llvm::Intrinsic::hexagon_V6_vavguhrnd_128B, llvm::Intrinsic::hexagon_V6_vavguw, llvm::Intrinsic::hexagon_V6_vavguw_128B, llvm::Intrinsic::hexagon_V6_vavguwrnd,   llvm::Intrinsic::hexagon_V6_vavguwrnd_128B, llvm::Intrinsic::hexagon_V6_vavgw, llvm::Intrinsic::hexagon_V6_vavgw_128B, llvm::Intrinsic::hexagon_V6_vavgwrnd,   llvm::Intrinsic::hexagon_V6_vavgwrnd_128B, llvm::Intrinsic::hexagon_V6_vcl0h, llvm::Intrinsic::hexagon_V6_vcl0h_128B, llvm::Intrinsic::hexagon_V6_vcl0w,   llvm::Intrinsic::hexagon_V6_vcl0w_128B, llvm::Intrinsic::hexagon_V6_vcombine, llvm::Intrinsic::hexagon_V6_vcombine_128B, llvm::Intrinsic::hexagon_V6_vd0,   llvm::Intrinsic::hexagon_V6_vd0_128B, llvm::Intrinsic::hexagon_V6_vdd0, llvm::Intrinsic::hexagon_V6_vdd0_128B, llvm::Intrinsic::hexagon_V6_vdealb,   llvm::Intrinsic::hexagon_V6_vdealb_128B, llvm::Intrinsic::hexagon_V6_vdealb4w, llvm::Intrinsic::hexagon_V6_vdealb4w_128B, llvm::Intrinsic::hexagon_V6_vdealh,   llvm::Intrinsic::hexagon_V6_vdealh_128B, llvm::Intrinsic::hexagon_V6_vdealvdd, llvm::Intrinsic::hexagon_V6_vdealvdd_128B, llvm::Intrinsic::hexagon_V6_vdelta,   llvm::Intrinsic::hexagon_V6_vdelta_128B, llvm::Intrinsic::hexagon_V6_vdmpybus, llvm::Intrinsic::hexagon_V6_vdmpybus_128B, llvm::Intrinsic::hexagon_V6_vdmpybus_acc,   llvm::Intrinsic::hexagon_V6_vdmpybus_acc_128B, llvm::Intrinsic::hexagon_V6_vdmpybus_dv, llvm::Intrinsic::hexagon_V6_vdmpybus_dv_128B, llvm::Intrinsic::hexagon_V6_vdmpybus_dv_acc,   llvm::Intrinsic::hexagon_V6_vdmpybus_dv_acc_128B, llvm::Intrinsic::hexagon_V6_vdmpyhb, llvm::Intrinsic::hexagon_V6_vdmpyhb_128B, llvm::Intrinsic::hexagon_V6_vdmpyhb_acc,   llvm::Intrinsic::hexagon_V6_vdmpyhb_acc_128B, llvm::Intrinsic::hexagon_V6_vdmpyhb_dv, llvm::Intrinsic::hexagon_V6_vdmpyhb_dv_128B, llvm::Intrinsic::hexagon_V6_vdmpyhb_dv_acc,   llvm::Intrinsic::hexagon_V6_vdmpyhb_dv_acc_128B, llvm::Intrinsic::hexagon_V6_vdmpyhisat, llvm::Intrinsic::hexagon_V6_vdmpyhisat_128B, llvm::Intrinsic::hexagon_V6_vdmpyhisat_acc,   llvm::Intrinsic::hexagon_V6_vdmpyhisat_acc_128B, llvm::Intrinsic::hexagon_V6_vdmpyhsat, llvm::Intrinsic::hexagon_V6_vdmpyhsat_128B, llvm::Intrinsic::hexagon_V6_vdmpyhsat_acc,   llvm::Intrinsic::hexagon_V6_vdmpyhsat_acc_128B, llvm::Intrinsic::hexagon_V6_vdmpyhsuisat, llvm::Intrinsic::hexagon_V6_vdmpyhsuisat_128B, llvm::Intrinsic::hexagon_V6_vdmpyhsuisat_acc,   llvm::Intrinsic::hexagon_V6_vdmpyhsuisat_acc_128B, llvm::Intrinsic::hexagon_V6_vdmpyhsusat, llvm::Intrinsic::hexagon_V6_vdmpyhsusat_128B, llvm::Intrinsic::hexagon_V6_vdmpyhsusat_acc,   llvm::Intrinsic::hexagon_V6_vdmpyhsusat_acc_128B, llvm::Intrinsic::hexagon_V6_vdmpyhvsat, llvm::Intrinsic::hexagon_V6_vdmpyhvsat_128B, llvm::Intrinsic::hexagon_V6_vdmpyhvsat_acc,   llvm::Intrinsic::hexagon_V6_vdmpyhvsat_acc_128B, llvm::Intrinsic::hexagon_V6_vdsaduh, llvm::Intrinsic::hexagon_V6_vdsaduh_128B, llvm::Intrinsic::hexagon_V6_vdsaduh_acc,   llvm::Intrinsic::hexagon_V6_vdsaduh_acc_128B, llvm::Intrinsic::hexagon_V6_veqb, llvm::Intrinsic::hexagon_V6_veqb_128B, llvm::Intrinsic::hexagon_V6_veqb_and,   llvm::Intrinsic::hexagon_V6_veqb_and_128B, llvm::Intrinsic::hexagon_V6_veqb_or, llvm::Intrinsic::hexagon_V6_veqb_or_128B, llvm::Intrinsic::hexagon_V6_veqb_xor,   llvm::Intrinsic::hexagon_V6_veqb_xor_128B, llvm::Intrinsic::hexagon_V6_veqh, llvm::Intrinsic::hexagon_V6_veqh_128B, llvm::Intrinsic::hexagon_V6_veqh_and,   llvm::Intrinsic::hexagon_V6_veqh_and_128B, llvm::Intrinsic::hexagon_V6_veqh_or, llvm::Intrinsic::hexagon_V6_veqh_or_128B, llvm::Intrinsic::hexagon_V6_veqh_xor,   llvm::Intrinsic::hexagon_V6_veqh_xor_128B, llvm::Intrinsic::hexagon_V6_veqw, llvm::Intrinsic::hexagon_V6_veqw_128B, llvm::Intrinsic::hexagon_V6_veqw_and,   llvm::Intrinsic::hexagon_V6_veqw_and_128B, llvm::Intrinsic::hexagon_V6_veqw_or, llvm::Intrinsic::hexagon_V6_veqw_or_128B, llvm::Intrinsic::hexagon_V6_veqw_xor,   llvm::Intrinsic::hexagon_V6_veqw_xor_128B, llvm::Intrinsic::hexagon_V6_vgathermh, llvm::Intrinsic::hexagon_V6_vgathermh_128B, llvm::Intrinsic::hexagon_V6_vgathermhq,   llvm::Intrinsic::hexagon_V6_vgathermhq_128B, llvm::Intrinsic::hexagon_V6_vgathermhw, llvm::Intrinsic::hexagon_V6_vgathermhw_128B, llvm::Intrinsic::hexagon_V6_vgathermhwq,   llvm::Intrinsic::hexagon_V6_vgathermhwq_128B, llvm::Intrinsic::hexagon_V6_vgathermw, llvm::Intrinsic::hexagon_V6_vgathermw_128B, llvm::Intrinsic::hexagon_V6_vgathermwq,   llvm::Intrinsic::hexagon_V6_vgathermwq_128B, llvm::Intrinsic::hexagon_V6_vgtb, llvm::Intrinsic::hexagon_V6_vgtb_128B, llvm::Intrinsic::hexagon_V6_vgtb_and,   llvm::Intrinsic::hexagon_V6_vgtb_and_128B, llvm::Intrinsic::hexagon_V6_vgtb_or, llvm::Intrinsic::hexagon_V6_vgtb_or_128B, llvm::Intrinsic::hexagon_V6_vgtb_xor,   llvm::Intrinsic::hexagon_V6_vgtb_xor_128B, llvm::Intrinsic::hexagon_V6_vgth, llvm::Intrinsic::hexagon_V6_vgth_128B, llvm::Intrinsic::hexagon_V6_vgth_and,   llvm::Intrinsic::hexagon_V6_vgth_and_128B, llvm::Intrinsic::hexagon_V6_vgth_or, llvm::Intrinsic::hexagon_V6_vgth_or_128B, llvm::Intrinsic::hexagon_V6_vgth_xor,   llvm::Intrinsic::hexagon_V6_vgth_xor_128B, llvm::Intrinsic::hexagon_V6_vgtub, llvm::Intrinsic::hexagon_V6_vgtub_128B, llvm::Intrinsic::hexagon_V6_vgtub_and,   llvm::Intrinsic::hexagon_V6_vgtub_and_128B, llvm::Intrinsic::hexagon_V6_vgtub_or, llvm::Intrinsic::hexagon_V6_vgtub_or_128B, llvm::Intrinsic::hexagon_V6_vgtub_xor,   llvm::Intrinsic::hexagon_V6_vgtub_xor_128B, llvm::Intrinsic::hexagon_V6_vgtuh, llvm::Intrinsic::hexagon_V6_vgtuh_128B, llvm::Intrinsic::hexagon_V6_vgtuh_and,   llvm::Intrinsic::hexagon_V6_vgtuh_and_128B, llvm::Intrinsic::hexagon_V6_vgtuh_or, llvm::Intrinsic::hexagon_V6_vgtuh_or_128B, llvm::Intrinsic::hexagon_V6_vgtuh_xor,   llvm::Intrinsic::hexagon_V6_vgtuh_xor_128B, llvm::Intrinsic::hexagon_V6_vgtuw, llvm::Intrinsic::hexagon_V6_vgtuw_128B, llvm::Intrinsic::hexagon_V6_vgtuw_and,   llvm::Intrinsic::hexagon_V6_vgtuw_and_128B, llvm::Intrinsic::hexagon_V6_vgtuw_or, llvm::Intrinsic::hexagon_V6_vgtuw_or_128B, llvm::Intrinsic::hexagon_V6_vgtuw_xor,   llvm::Intrinsic::hexagon_V6_vgtuw_xor_128B, llvm::Intrinsic::hexagon_V6_vgtw, llvm::Intrinsic::hexagon_V6_vgtw_128B, llvm::Intrinsic::hexagon_V6_vgtw_and,   llvm::Intrinsic::hexagon_V6_vgtw_and_128B, llvm::Intrinsic::hexagon_V6_vgtw_or, llvm::Intrinsic::hexagon_V6_vgtw_or_128B, llvm::Intrinsic::hexagon_V6_vgtw_xor,   llvm::Intrinsic::hexagon_V6_vgtw_xor_128B, llvm::Intrinsic::hexagon_V6_vinsertwr, llvm::Intrinsic::hexagon_V6_vinsertwr_128B, llvm::Intrinsic::hexagon_V6_vlalignb,   llvm::Intrinsic::hexagon_V6_vlalignb_128B, llvm::Intrinsic::hexagon_V6_vlalignbi, llvm::Intrinsic::hexagon_V6_vlalignbi_128B, llvm::Intrinsic::hexagon_V6_vlsrb,   llvm::Intrinsic::hexagon_V6_vlsrb_128B, llvm::Intrinsic::hexagon_V6_vlsrh, llvm::Intrinsic::hexagon_V6_vlsrh_128B, llvm::Intrinsic::hexagon_V6_vlsrhv,   llvm::Intrinsic::hexagon_V6_vlsrhv_128B, llvm::Intrinsic::hexagon_V6_vlsrw, llvm::Intrinsic::hexagon_V6_vlsrw_128B, llvm::Intrinsic::hexagon_V6_vlsrwv,   llvm::Intrinsic::hexagon_V6_vlsrwv_128B, llvm::Intrinsic::hexagon_V6_vlut4, llvm::Intrinsic::hexagon_V6_vlut4_128B, llvm::Intrinsic::hexagon_V6_vlutvvb,   llvm::Intrinsic::hexagon_V6_vlutvvb_128B, llvm::Intrinsic::hexagon_V6_vlutvvb_nm, llvm::Intrinsic::hexagon_V6_vlutvvb_nm_128B, llvm::Intrinsic::hexagon_V6_vlutvvb_oracc,   llvm::Intrinsic::hexagon_V6_vlutvvb_oracc_128B, llvm::Intrinsic::hexagon_V6_vlutvvb_oracci, llvm::Intrinsic::hexagon_V6_vlutvvb_oracci_128B, llvm::Intrinsic::hexagon_V6_vlutvvbi,   llvm::Intrinsic::hexagon_V6_vlutvvbi_128B, llvm::Intrinsic::hexagon_V6_vlutvwh, llvm::Intrinsic::hexagon_V6_vlutvwh_128B, llvm::Intrinsic::hexagon_V6_vlutvwh_nm,   llvm::Intrinsic::hexagon_V6_vlutvwh_nm_128B, llvm::Intrinsic::hexagon_V6_vlutvwh_oracc, llvm::Intrinsic::hexagon_V6_vlutvwh_oracc_128B, llvm::Intrinsic::hexagon_V6_vlutvwh_oracci,   llvm::Intrinsic::hexagon_V6_vlutvwh_oracci_128B, llvm::Intrinsic::hexagon_V6_vlutvwhi, llvm::Intrinsic::hexagon_V6_vlutvwhi_128B, llvm::Intrinsic::hexagon_V6_vmaskedstorenq,   llvm::Intrinsic::hexagon_V6_vmaskedstorenq_128B, llvm::Intrinsic::hexagon_V6_vmaskedstorentnq, llvm::Intrinsic::hexagon_V6_vmaskedstorentnq_128B, llvm::Intrinsic::hexagon_V6_vmaskedstorentq,   llvm::Intrinsic::hexagon_V6_vmaskedstorentq_128B, llvm::Intrinsic::hexagon_V6_vmaskedstoreq, llvm::Intrinsic::hexagon_V6_vmaskedstoreq_128B, llvm::Intrinsic::hexagon_V6_vmaxb,   llvm::Intrinsic::hexagon_V6_vmaxb_128B, llvm::Intrinsic::hexagon_V6_vmaxh, llvm::Intrinsic::hexagon_V6_vmaxh_128B, llvm::Intrinsic::hexagon_V6_vmaxub,   llvm::Intrinsic::hexagon_V6_vmaxub_128B, llvm::Intrinsic::hexagon_V6_vmaxuh, llvm::Intrinsic::hexagon_V6_vmaxuh_128B, llvm::Intrinsic::hexagon_V6_vmaxw,   llvm::Intrinsic::hexagon_V6_vmaxw_128B, llvm::Intrinsic::hexagon_V6_vminb, llvm::Intrinsic::hexagon_V6_vminb_128B, llvm::Intrinsic::hexagon_V6_vminh,   llvm::Intrinsic::hexagon_V6_vminh_128B, llvm::Intrinsic::hexagon_V6_vminub, llvm::Intrinsic::hexagon_V6_vminub_128B, llvm::Intrinsic::hexagon_V6_vminuh,   llvm::Intrinsic::hexagon_V6_vminuh_128B, llvm::Intrinsic::hexagon_V6_vminw, llvm::Intrinsic::hexagon_V6_vminw_128B, llvm::Intrinsic::hexagon_V6_vmpabus,   llvm::Intrinsic::hexagon_V6_vmpabus_128B, llvm::Intrinsic::hexagon_V6_vmpabus_acc, llvm::Intrinsic::hexagon_V6_vmpabus_acc_128B, llvm::Intrinsic::hexagon_V6_vmpabusv,   llvm::Intrinsic::hexagon_V6_vmpabusv_128B, llvm::Intrinsic::hexagon_V6_vmpabuu, llvm::Intrinsic::hexagon_V6_vmpabuu_128B, llvm::Intrinsic::hexagon_V6_vmpabuu_acc,   llvm::Intrinsic::hexagon_V6_vmpabuu_acc_128B, llvm::Intrinsic::hexagon_V6_vmpabuuv, llvm::Intrinsic::hexagon_V6_vmpabuuv_128B, llvm::Intrinsic::hexagon_V6_vmpahb,   llvm::Intrinsic::hexagon_V6_vmpahb_128B, llvm::Intrinsic::hexagon_V6_vmpahb_acc, llvm::Intrinsic::hexagon_V6_vmpahb_acc_128B, llvm::Intrinsic::hexagon_V6_vmpahhsat,   llvm::Intrinsic::hexagon_V6_vmpahhsat_128B, llvm::Intrinsic::hexagon_V6_vmpauhb, llvm::Intrinsic::hexagon_V6_vmpauhb_128B, llvm::Intrinsic::hexagon_V6_vmpauhb_acc,   llvm::Intrinsic::hexagon_V6_vmpauhb_acc_128B, llvm::Intrinsic::hexagon_V6_vmpauhuhsat, llvm::Intrinsic::hexagon_V6_vmpauhuhsat_128B, llvm::Intrinsic::hexagon_V6_vmpsuhuhsat,   llvm::Intrinsic::hexagon_V6_vmpsuhuhsat_128B, llvm::Intrinsic::hexagon_V6_vmpybus, llvm::Intrinsic::hexagon_V6_vmpybus_128B, llvm::Intrinsic::hexagon_V6_vmpybus_acc,   llvm::Intrinsic::hexagon_V6_vmpybus_acc_128B, llvm::Intrinsic::hexagon_V6_vmpybusv, llvm::Intrinsic::hexagon_V6_vmpybusv_128B, llvm::Intrinsic::hexagon_V6_vmpybusv_acc,   llvm::Intrinsic::hexagon_V6_vmpybusv_acc_128B, llvm::Intrinsic::hexagon_V6_vmpybv, llvm::Intrinsic::hexagon_V6_vmpybv_128B, llvm::Intrinsic::hexagon_V6_vmpybv_acc,   llvm::Intrinsic::hexagon_V6_vmpybv_acc_128B, llvm::Intrinsic::hexagon_V6_vmpyewuh, llvm::Intrinsic::hexagon_V6_vmpyewuh_128B, llvm::Intrinsic::hexagon_V6_vmpyewuh_64,   llvm::Intrinsic::hexagon_V6_vmpyewuh_64_128B, llvm::Intrinsic::hexagon_V6_vmpyh, llvm::Intrinsic::hexagon_V6_vmpyh_128B, llvm::Intrinsic::hexagon_V6_vmpyh_acc,   llvm::Intrinsic::hexagon_V6_vmpyh_acc_128B, llvm::Intrinsic::hexagon_V6_vmpyhsat_acc, llvm::Intrinsic::hexagon_V6_vmpyhsat_acc_128B, llvm::Intrinsic::hexagon_V6_vmpyhsrs,   llvm::Intrinsic::hexagon_V6_vmpyhsrs_128B, llvm::Intrinsic::hexagon_V6_vmpyhss, llvm::Intrinsic::hexagon_V6_vmpyhss_128B, llvm::Intrinsic::hexagon_V6_vmpyhus,   llvm::Intrinsic::hexagon_V6_vmpyhus_128B, llvm::Intrinsic::hexagon_V6_vmpyhus_acc, llvm::Intrinsic::hexagon_V6_vmpyhus_acc_128B, llvm::Intrinsic::hexagon_V6_vmpyhv,   llvm::Intrinsic::hexagon_V6_vmpyhv_128B, llvm::Intrinsic::hexagon_V6_vmpyhv_acc, llvm::Intrinsic::hexagon_V6_vmpyhv_acc_128B, llvm::Intrinsic::hexagon_V6_vmpyhvsrs,   llvm::Intrinsic::hexagon_V6_vmpyhvsrs_128B, llvm::Intrinsic::hexagon_V6_vmpyieoh, llvm::Intrinsic::hexagon_V6_vmpyieoh_128B, llvm::Intrinsic::hexagon_V6_vmpyiewh_acc,   llvm::Intrinsic::hexagon_V6_vmpyiewh_acc_128B, llvm::Intrinsic::hexagon_V6_vmpyiewuh, llvm::Intrinsic::hexagon_V6_vmpyiewuh_128B, llvm::Intrinsic::hexagon_V6_vmpyiewuh_acc,   llvm::Intrinsic::hexagon_V6_vmpyiewuh_acc_128B, llvm::Intrinsic::hexagon_V6_vmpyih, llvm::Intrinsic::hexagon_V6_vmpyih_128B, llvm::Intrinsic::hexagon_V6_vmpyih_acc,   llvm::Intrinsic::hexagon_V6_vmpyih_acc_128B, llvm::Intrinsic::hexagon_V6_vmpyihb, llvm::Intrinsic::hexagon_V6_vmpyihb_128B, llvm::Intrinsic::hexagon_V6_vmpyihb_acc,   llvm::Intrinsic::hexagon_V6_vmpyihb_acc_128B, llvm::Intrinsic::hexagon_V6_vmpyiowh, llvm::Intrinsic::hexagon_V6_vmpyiowh_128B, llvm::Intrinsic::hexagon_V6_vmpyiwb,   llvm::Intrinsic::hexagon_V6_vmpyiwb_128B, llvm::Intrinsic::hexagon_V6_vmpyiwb_acc, llvm::Intrinsic::hexagon_V6_vmpyiwb_acc_128B, llvm::Intrinsic::hexagon_V6_vmpyiwh,   llvm::Intrinsic::hexagon_V6_vmpyiwh_128B, llvm::Intrinsic::hexagon_V6_vmpyiwh_acc, llvm::Intrinsic::hexagon_V6_vmpyiwh_acc_128B, llvm::Intrinsic::hexagon_V6_vmpyiwub,   llvm::Intrinsic::hexagon_V6_vmpyiwub_128B, llvm::Intrinsic::hexagon_V6_vmpyiwub_acc, llvm::Intrinsic::hexagon_V6_vmpyiwub_acc_128B, llvm::Intrinsic::hexagon_V6_vmpyowh,   llvm::Intrinsic::hexagon_V6_vmpyowh_128B, llvm::Intrinsic::hexagon_V6_vmpyowh_64_acc, llvm::Intrinsic::hexagon_V6_vmpyowh_64_acc_128B, llvm::Intrinsic::hexagon_V6_vmpyowh_rnd,   llvm::Intrinsic::hexagon_V6_vmpyowh_rnd_128B, llvm::Intrinsic::hexagon_V6_vmpyowh_rnd_sacc, llvm::Intrinsic::hexagon_V6_vmpyowh_rnd_sacc_128B, llvm::Intrinsic::hexagon_V6_vmpyowh_sacc,   llvm::Intrinsic::hexagon_V6_vmpyowh_sacc_128B, llvm::Intrinsic::hexagon_V6_vmpyub, llvm::Intrinsic::hexagon_V6_vmpyub_128B, llvm::Intrinsic::hexagon_V6_vmpyub_acc,   llvm::Intrinsic::hexagon_V6_vmpyub_acc_128B, llvm::Intrinsic::hexagon_V6_vmpyubv, llvm::Intrinsic::hexagon_V6_vmpyubv_128B, llvm::Intrinsic::hexagon_V6_vmpyubv_acc,   llvm::Intrinsic::hexagon_V6_vmpyubv_acc_128B, llvm::Intrinsic::hexagon_V6_vmpyuh, llvm::Intrinsic::hexagon_V6_vmpyuh_128B, llvm::Intrinsic::hexagon_V6_vmpyuh_acc,   llvm::Intrinsic::hexagon_V6_vmpyuh_acc_128B, llvm::Intrinsic::hexagon_V6_vmpyuhe, llvm::Intrinsic::hexagon_V6_vmpyuhe_128B, llvm::Intrinsic::hexagon_V6_vmpyuhe_acc,   llvm::Intrinsic::hexagon_V6_vmpyuhe_acc_128B, llvm::Intrinsic::hexagon_V6_vmpyuhv, llvm::Intrinsic::hexagon_V6_vmpyuhv_128B, llvm::Intrinsic::hexagon_V6_vmpyuhv_acc,   llvm::Intrinsic::hexagon_V6_vmpyuhv_acc_128B, llvm::Intrinsic::hexagon_V6_vmux, llvm::Intrinsic::hexagon_V6_vmux_128B, llvm::Intrinsic::hexagon_V6_vnavgb,   llvm::Intrinsic::hexagon_V6_vnavgb_128B, llvm::Intrinsic::hexagon_V6_vnavgh, llvm::Intrinsic::hexagon_V6_vnavgh_128B, llvm::Intrinsic::hexagon_V6_vnavgub,   llvm::Intrinsic::hexagon_V6_vnavgub_128B, llvm::Intrinsic::hexagon_V6_vnavgw, llvm::Intrinsic::hexagon_V6_vnavgw_128B, llvm::Intrinsic::hexagon_V6_vnormamth,   llvm::Intrinsic::hexagon_V6_vnormamth_128B, llvm::Intrinsic::hexagon_V6_vnormamtw, llvm::Intrinsic::hexagon_V6_vnormamtw_128B, llvm::Intrinsic::hexagon_V6_vnot,   llvm::Intrinsic::hexagon_V6_vnot_128B, llvm::Intrinsic::hexagon_V6_vor, llvm::Intrinsic::hexagon_V6_vor_128B, llvm::Intrinsic::hexagon_V6_vpackeb,   llvm::Intrinsic::hexagon_V6_vpackeb_128B, llvm::Intrinsic::hexagon_V6_vpackeh, llvm::Intrinsic::hexagon_V6_vpackeh_128B, llvm::Intrinsic::hexagon_V6_vpackhb_sat,   llvm::Intrinsic::hexagon_V6_vpackhb_sat_128B, llvm::Intrinsic::hexagon_V6_vpackhub_sat, llvm::Intrinsic::hexagon_V6_vpackhub_sat_128B, llvm::Intrinsic::hexagon_V6_vpackob,   llvm::Intrinsic::hexagon_V6_vpackob_128B, llvm::Intrinsic::hexagon_V6_vpackoh, llvm::Intrinsic::hexagon_V6_vpackoh_128B, llvm::Intrinsic::hexagon_V6_vpackwh_sat,   llvm::Intrinsic::hexagon_V6_vpackwh_sat_128B, llvm::Intrinsic::hexagon_V6_vpackwuh_sat, llvm::Intrinsic::hexagon_V6_vpackwuh_sat_128B, llvm::Intrinsic::hexagon_V6_vpopcounth,   llvm::Intrinsic::hexagon_V6_vpopcounth_128B, llvm::Intrinsic::hexagon_V6_vprefixqb, llvm::Intrinsic::hexagon_V6_vprefixqb_128B, llvm::Intrinsic::hexagon_V6_vprefixqh,   llvm::Intrinsic::hexagon_V6_vprefixqh_128B, llvm::Intrinsic::hexagon_V6_vprefixqw, llvm::Intrinsic::hexagon_V6_vprefixqw_128B, llvm::Intrinsic::hexagon_V6_vrdelta,   llvm::Intrinsic::hexagon_V6_vrdelta_128B, llvm::Intrinsic::hexagon_V6_vrmpybub_rtt, llvm::Intrinsic::hexagon_V6_vrmpybub_rtt_128B, llvm::Intrinsic::hexagon_V6_vrmpybub_rtt_acc,   llvm::Intrinsic::hexagon_V6_vrmpybub_rtt_acc_128B, llvm::Intrinsic::hexagon_V6_vrmpybus, llvm::Intrinsic::hexagon_V6_vrmpybus_128B, llvm::Intrinsic::hexagon_V6_vrmpybus_acc,   llvm::Intrinsic::hexagon_V6_vrmpybus_acc_128B, llvm::Intrinsic::hexagon_V6_vrmpybusi, llvm::Intrinsic::hexagon_V6_vrmpybusi_128B, llvm::Intrinsic::hexagon_V6_vrmpybusi_acc,   llvm::Intrinsic::hexagon_V6_vrmpybusi_acc_128B, llvm::Intrinsic::hexagon_V6_vrmpybusv, llvm::Intrinsic::hexagon_V6_vrmpybusv_128B, llvm::Intrinsic::hexagon_V6_vrmpybusv_acc,   llvm::Intrinsic::hexagon_V6_vrmpybusv_acc_128B, llvm::Intrinsic::hexagon_V6_vrmpybv, llvm::Intrinsic::hexagon_V6_vrmpybv_128B, llvm::Intrinsic::hexagon_V6_vrmpybv_acc,   llvm::Intrinsic::hexagon_V6_vrmpybv_acc_128B, llvm::Intrinsic::hexagon_V6_vrmpyub, llvm::Intrinsic::hexagon_V6_vrmpyub_128B, llvm::Intrinsic::hexagon_V6_vrmpyub_acc,   llvm::Intrinsic::hexagon_V6_vrmpyub_acc_128B, llvm::Intrinsic::hexagon_V6_vrmpyub_rtt, llvm::Intrinsic::hexagon_V6_vrmpyub_rtt_128B, llvm::Intrinsic::hexagon_V6_vrmpyub_rtt_acc,   llvm::Intrinsic::hexagon_V6_vrmpyub_rtt_acc_128B, llvm::Intrinsic::hexagon_V6_vrmpyubi, llvm::Intrinsic::hexagon_V6_vrmpyubi_128B, llvm::Intrinsic::hexagon_V6_vrmpyubi_acc,   llvm::Intrinsic::hexagon_V6_vrmpyubi_acc_128B, llvm::Intrinsic::hexagon_V6_vrmpyubv, llvm::Intrinsic::hexagon_V6_vrmpyubv_128B, llvm::Intrinsic::hexagon_V6_vrmpyubv_acc,   llvm::Intrinsic::hexagon_V6_vrmpyubv_acc_128B, llvm::Intrinsic::hexagon_V6_vror, llvm::Intrinsic::hexagon_V6_vror_128B, llvm::Intrinsic::hexagon_V6_vrotr,   llvm::Intrinsic::hexagon_V6_vrotr_128B, llvm::Intrinsic::hexagon_V6_vroundhb, llvm::Intrinsic::hexagon_V6_vroundhb_128B, llvm::Intrinsic::hexagon_V6_vroundhub,   llvm::Intrinsic::hexagon_V6_vroundhub_128B, llvm::Intrinsic::hexagon_V6_vrounduhub, llvm::Intrinsic::hexagon_V6_vrounduhub_128B, llvm::Intrinsic::hexagon_V6_vrounduwuh,   llvm::Intrinsic::hexagon_V6_vrounduwuh_128B, llvm::Intrinsic::hexagon_V6_vroundwh, llvm::Intrinsic::hexagon_V6_vroundwh_128B, llvm::Intrinsic::hexagon_V6_vroundwuh,   llvm::Intrinsic::hexagon_V6_vroundwuh_128B, llvm::Intrinsic::hexagon_V6_vrsadubi, llvm::Intrinsic::hexagon_V6_vrsadubi_128B, llvm::Intrinsic::hexagon_V6_vrsadubi_acc,   llvm::Intrinsic::hexagon_V6_vrsadubi_acc_128B, llvm::Intrinsic::hexagon_V6_vsatdw, llvm::Intrinsic::hexagon_V6_vsatdw_128B, llvm::Intrinsic::hexagon_V6_vsathub,   llvm::Intrinsic::hexagon_V6_vsathub_128B, llvm::Intrinsic::hexagon_V6_vsatuwuh, llvm::Intrinsic::hexagon_V6_vsatuwuh_128B, llvm::Intrinsic::hexagon_V6_vsatwh,   llvm::Intrinsic::hexagon_V6_vsatwh_128B, llvm::Intrinsic::hexagon_V6_vsb, llvm::Intrinsic::hexagon_V6_vsb_128B, llvm::Intrinsic::hexagon_V6_vscattermh,   llvm::Intrinsic::hexagon_V6_vscattermh_128B, llvm::Intrinsic::hexagon_V6_vscattermh_add, llvm::Intrinsic::hexagon_V6_vscattermh_add_128B, llvm::Intrinsic::hexagon_V6_vscattermhq,   llvm::Intrinsic::hexagon_V6_vscattermhq_128B, llvm::Intrinsic::hexagon_V6_vscattermhw, llvm::Intrinsic::hexagon_V6_vscattermhw_128B, llvm::Intrinsic::hexagon_V6_vscattermhw_add,   llvm::Intrinsic::hexagon_V6_vscattermhw_add_128B, llvm::Intrinsic::hexagon_V6_vscattermhwq, llvm::Intrinsic::hexagon_V6_vscattermhwq_128B, llvm::Intrinsic::hexagon_V6_vscattermw,   llvm::Intrinsic::hexagon_V6_vscattermw_128B, llvm::Intrinsic::hexagon_V6_vscattermw_add, llvm::Intrinsic::hexagon_V6_vscattermw_add_128B, llvm::Intrinsic::hexagon_V6_vscattermwq,   llvm::Intrinsic::hexagon_V6_vscattermwq_128B, llvm::Intrinsic::hexagon_V6_vsh, llvm::Intrinsic::hexagon_V6_vsh_128B, llvm::Intrinsic::hexagon_V6_vshufeh,   llvm::Intrinsic::hexagon_V6_vshufeh_128B, llvm::Intrinsic::hexagon_V6_vshuffb, llvm::Intrinsic::hexagon_V6_vshuffb_128B, llvm::Intrinsic::hexagon_V6_vshuffeb,   llvm::Intrinsic::hexagon_V6_vshuffeb_128B, llvm::Intrinsic::hexagon_V6_vshuffh, llvm::Intrinsic::hexagon_V6_vshuffh_128B, llvm::Intrinsic::hexagon_V6_vshuffob,   llvm::Intrinsic::hexagon_V6_vshuffob_128B, llvm::Intrinsic::hexagon_V6_vshuffvdd, llvm::Intrinsic::hexagon_V6_vshuffvdd_128B, llvm::Intrinsic::hexagon_V6_vshufoeb,   llvm::Intrinsic::hexagon_V6_vshufoeb_128B, llvm::Intrinsic::hexagon_V6_vshufoeh, llvm::Intrinsic::hexagon_V6_vshufoeh_128B, llvm::Intrinsic::hexagon_V6_vshufoh,   llvm::Intrinsic::hexagon_V6_vshufoh_128B, llvm::Intrinsic::hexagon_V6_vsubb, llvm::Intrinsic::hexagon_V6_vsubb_128B, llvm::Intrinsic::hexagon_V6_vsubb_dv,   llvm::Intrinsic::hexagon_V6_vsubb_dv_128B, llvm::Intrinsic::hexagon_V6_vsubbnq, llvm::Intrinsic::hexagon_V6_vsubbnq_128B, llvm::Intrinsic::hexagon_V6_vsubbq,   llvm::Intrinsic::hexagon_V6_vsubbq_128B, llvm::Intrinsic::hexagon_V6_vsubbsat, llvm::Intrinsic::hexagon_V6_vsubbsat_128B, llvm::Intrinsic::hexagon_V6_vsubbsat_dv,   llvm::Intrinsic::hexagon_V6_vsubbsat_dv_128B, llvm::Intrinsic::hexagon_V6_vsubcarry, llvm::Intrinsic::hexagon_V6_vsubcarry_128B, llvm::Intrinsic::hexagon_V6_vsubh,   llvm::Intrinsic::hexagon_V6_vsubh_128B, llvm::Intrinsic::hexagon_V6_vsubh_dv, llvm::Intrinsic::hexagon_V6_vsubh_dv_128B, llvm::Intrinsic::hexagon_V6_vsubhnq,   llvm::Intrinsic::hexagon_V6_vsubhnq_128B, llvm::Intrinsic::hexagon_V6_vsubhq, llvm::Intrinsic::hexagon_V6_vsubhq_128B, llvm::Intrinsic::hexagon_V6_vsubhsat,   llvm::Intrinsic::hexagon_V6_vsubhsat_128B, llvm::Intrinsic::hexagon_V6_vsubhsat_dv, llvm::Intrinsic::hexagon_V6_vsubhsat_dv_128B, llvm::Intrinsic::hexagon_V6_vsubhw,   llvm::Intrinsic::hexagon_V6_vsubhw_128B, llvm::Intrinsic::hexagon_V6_vsububh, llvm::Intrinsic::hexagon_V6_vsububh_128B, llvm::Intrinsic::hexagon_V6_vsububsat,   llvm::Intrinsic::hexagon_V6_vsububsat_128B, llvm::Intrinsic::hexagon_V6_vsububsat_dv, llvm::Intrinsic::hexagon_V6_vsububsat_dv_128B, llvm::Intrinsic::hexagon_V6_vsubububb_sat,   llvm::Intrinsic::hexagon_V6_vsubububb_sat_128B, llvm::Intrinsic::hexagon_V6_vsubuhsat, llvm::Intrinsic::hexagon_V6_vsubuhsat_128B, llvm::Intrinsic::hexagon_V6_vsubuhsat_dv,   llvm::Intrinsic::hexagon_V6_vsubuhsat_dv_128B, llvm::Intrinsic::hexagon_V6_vsubuhw, llvm::Intrinsic::hexagon_V6_vsubuhw_128B, llvm::Intrinsic::hexagon_V6_vsubuwsat,   llvm::Intrinsic::hexagon_V6_vsubuwsat_128B, llvm::Intrinsic::hexagon_V6_vsubuwsat_dv, llvm::Intrinsic::hexagon_V6_vsubuwsat_dv_128B, llvm::Intrinsic::hexagon_V6_vsubw,   llvm::Intrinsic::hexagon_V6_vsubw_128B, llvm::Intrinsic::hexagon_V6_vsubw_dv, llvm::Intrinsic::hexagon_V6_vsubw_dv_128B, llvm::Intrinsic::hexagon_V6_vsubwnq,   llvm::Intrinsic::hexagon_V6_vsubwnq_128B, llvm::Intrinsic::hexagon_V6_vsubwq, llvm::Intrinsic::hexagon_V6_vsubwq_128B, llvm::Intrinsic::hexagon_V6_vsubwsat,   llvm::Intrinsic::hexagon_V6_vsubwsat_128B, llvm::Intrinsic::hexagon_V6_vsubwsat_dv, llvm::Intrinsic::hexagon_V6_vsubwsat_dv_128B, llvm::Intrinsic::hexagon_V6_vswap,   llvm::Intrinsic::hexagon_V6_vswap_128B, llvm::Intrinsic::hexagon_V6_vtmpyb, llvm::Intrinsic::hexagon_V6_vtmpyb_128B, llvm::Intrinsic::hexagon_V6_vtmpyb_acc,   llvm::Intrinsic::hexagon_V6_vtmpyb_acc_128B, llvm::Intrinsic::hexagon_V6_vtmpybus, llvm::Intrinsic::hexagon_V6_vtmpybus_128B, llvm::Intrinsic::hexagon_V6_vtmpybus_acc,   llvm::Intrinsic::hexagon_V6_vtmpybus_acc_128B, llvm::Intrinsic::hexagon_V6_vtmpyhb, llvm::Intrinsic::hexagon_V6_vtmpyhb_128B, llvm::Intrinsic::hexagon_V6_vtmpyhb_acc,   llvm::Intrinsic::hexagon_V6_vtmpyhb_acc_128B, llvm::Intrinsic::hexagon_V6_vtran2x2_map, llvm::Intrinsic::hexagon_V6_vtran2x2_map_128B, llvm::Intrinsic::hexagon_V6_vunpackb,   llvm::Intrinsic::hexagon_V6_vunpackb_128B, llvm::Intrinsic::hexagon_V6_vunpackh, llvm::Intrinsic::hexagon_V6_vunpackh_128B, llvm::Intrinsic::hexagon_V6_vunpackob,   llvm::Intrinsic::hexagon_V6_vunpackob_128B, llvm::Intrinsic::hexagon_V6_vunpackoh, llvm::Intrinsic::hexagon_V6_vunpackoh_128B, llvm::Intrinsic::hexagon_V6_vunpackub,   llvm::Intrinsic::hexagon_V6_vunpackub_128B, llvm::Intrinsic::hexagon_V6_vunpackuh, llvm::Intrinsic::hexagon_V6_vunpackuh_128B, llvm::Intrinsic::hexagon_V6_vxor,   llvm::Intrinsic::hexagon_V6_vxor_128B, llvm::Intrinsic::hexagon_V6_vzb, llvm::Intrinsic::hexagon_V6_vzb_128B, llvm::Intrinsic::hexagon_V6_vzh,   llvm::Intrinsic::hexagon_V6_vzh_128B, llvm::Intrinsic::hexagon_Y2_dccleana, llvm::Intrinsic::hexagon_Y2_dccleaninva, llvm::Intrinsic::hexagon_Y2_dcinva,   llvm::Intrinsic::hexagon_Y2_dczeroa, llvm::Intrinsic::hexagon_Y4_l2fetch, llvm::Intrinsic::hexagon_Y5_l2fetch, llvm::Intrinsic::hexagon_circ_ldb,   llvm::Intrinsic::hexagon_circ_ldd, llvm::Intrinsic::hexagon_circ_ldh, llvm::Intrinsic::hexagon_circ_ldub, llvm::Intrinsic::hexagon_circ_lduh,   llvm::Intrinsic::hexagon_circ_ldw, llvm::Intrinsic::hexagon_circ_stb, llvm::Intrinsic::hexagon_circ_std, llvm::Intrinsic::hexagon_circ_sth,   llvm::Intrinsic::hexagon_circ_sthhi, llvm::Intrinsic::hexagon_circ_stw, llvm::Intrinsic::hexagon_prefetch, llvm::Intrinsic::hexagon_vmemcpy,   llvm::Intrinsic::hexagon_vmemset, llvm::Intrinsic::mips_absq_s_ph, llvm::Intrinsic::mips_absq_s_qb, llvm::Intrinsic::mips_absq_s_w,   llvm::Intrinsic::mips_add_a_b, llvm::Intrinsic::mips_add_a_d, llvm::Intrinsic::mips_add_a_h, llvm::Intrinsic::mips_add_a_w,   llvm::Intrinsic::mips_addq_ph, llvm::Intrinsic::mips_addq_s_ph, llvm::Intrinsic::mips_addq_s_w, llvm::Intrinsic::mips_addqh_ph,   llvm::Intrinsic::mips_addqh_r_ph, llvm::Intrinsic::mips_addqh_r_w, llvm::Intrinsic::mips_addqh_w, llvm::Intrinsic::mips_adds_a_b,   llvm::Intrinsic::mips_adds_a_d, llvm::Intrinsic::mips_adds_a_h, llvm::Intrinsic::mips_adds_a_w, llvm::Intrinsic::mips_adds_s_b,   llvm::Intrinsic::mips_adds_s_d, llvm::Intrinsic::mips_adds_s_h, llvm::Intrinsic::mips_adds_s_w, llvm::Intrinsic::mips_adds_u_b,   llvm::Intrinsic::mips_adds_u_d, llvm::Intrinsic::mips_adds_u_h, llvm::Intrinsic::mips_adds_u_w, llvm::Intrinsic::mips_addsc,   llvm::Intrinsic::mips_addu_ph, llvm::Intrinsic::mips_addu_qb, llvm::Intrinsic::mips_addu_s_ph, llvm::Intrinsic::mips_addu_s_qb,   llvm::Intrinsic::mips_adduh_qb, llvm::Intrinsic::mips_adduh_r_qb, llvm::Intrinsic::mips_addv_b, llvm::Intrinsic::mips_addv_d,   llvm::Intrinsic::mips_addv_h, llvm::Intrinsic::mips_addv_w, llvm::Intrinsic::mips_addvi_b, llvm::Intrinsic::mips_addvi_d,   llvm::Intrinsic::mips_addvi_h, llvm::Intrinsic::mips_addvi_w, llvm::Intrinsic::mips_addwc, llvm::Intrinsic::mips_and_v,   llvm::Intrinsic::mips_andi_b, llvm::Intrinsic::mips_append, llvm::Intrinsic::mips_asub_s_b, llvm::Intrinsic::mips_asub_s_d,   llvm::Intrinsic::mips_asub_s_h, llvm::Intrinsic::mips_asub_s_w, llvm::Intrinsic::mips_asub_u_b, llvm::Intrinsic::mips_asub_u_d,   llvm::Intrinsic::mips_asub_u_h, llvm::Intrinsic::mips_asub_u_w, llvm::Intrinsic::mips_ave_s_b, llvm::Intrinsic::mips_ave_s_d,   llvm::Intrinsic::mips_ave_s_h, llvm::Intrinsic::mips_ave_s_w, llvm::Intrinsic::mips_ave_u_b, llvm::Intrinsic::mips_ave_u_d,   llvm::Intrinsic::mips_ave_u_h, llvm::Intrinsic::mips_ave_u_w, llvm::Intrinsic::mips_aver_s_b, llvm::Intrinsic::mips_aver_s_d,   llvm::Intrinsic::mips_aver_s_h, llvm::Intrinsic::mips_aver_s_w, llvm::Intrinsic::mips_aver_u_b, llvm::Intrinsic::mips_aver_u_d,   llvm::Intrinsic::mips_aver_u_h, llvm::Intrinsic::mips_aver_u_w, llvm::Intrinsic::mips_balign, llvm::Intrinsic::mips_bclr_b,   llvm::Intrinsic::mips_bclr_d, llvm::Intrinsic::mips_bclr_h, llvm::Intrinsic::mips_bclr_w, llvm::Intrinsic::mips_bclri_b,   llvm::Intrinsic::mips_bclri_d, llvm::Intrinsic::mips_bclri_h, llvm::Intrinsic::mips_bclri_w, llvm::Intrinsic::mips_binsl_b,   llvm::Intrinsic::mips_binsl_d, llvm::Intrinsic::mips_binsl_h, llvm::Intrinsic::mips_binsl_w, llvm::Intrinsic::mips_binsli_b,   llvm::Intrinsic::mips_binsli_d, llvm::Intrinsic::mips_binsli_h, llvm::Intrinsic::mips_binsli_w, llvm::Intrinsic::mips_binsr_b,   llvm::Intrinsic::mips_binsr_d, llvm::Intrinsic::mips_binsr_h, llvm::Intrinsic::mips_binsr_w, llvm::Intrinsic::mips_binsri_b,   llvm::Intrinsic::mips_binsri_d, llvm::Intrinsic::mips_binsri_h, llvm::Intrinsic::mips_binsri_w, llvm::Intrinsic::mips_bitrev,   llvm::Intrinsic::mips_bmnz_v, llvm::Intrinsic::mips_bmnzi_b, llvm::Intrinsic::mips_bmz_v, llvm::Intrinsic::mips_bmzi_b,   llvm::Intrinsic::mips_bneg_b, llvm::Intrinsic::mips_bneg_d, llvm::Intrinsic::mips_bneg_h, llvm::Intrinsic::mips_bneg_w,   llvm::Intrinsic::mips_bnegi_b, llvm::Intrinsic::mips_bnegi_d, llvm::Intrinsic::mips_bnegi_h, llvm::Intrinsic::mips_bnegi_w,   llvm::Intrinsic::mips_bnz_b, llvm::Intrinsic::mips_bnz_d, llvm::Intrinsic::mips_bnz_h, llvm::Intrinsic::mips_bnz_v,   llvm::Intrinsic::mips_bnz_w, llvm::Intrinsic::mips_bposge32, llvm::Intrinsic::mips_bsel_v, llvm::Intrinsic::mips_bseli_b,   llvm::Intrinsic::mips_bset_b, llvm::Intrinsic::mips_bset_d, llvm::Intrinsic::mips_bset_h, llvm::Intrinsic::mips_bset_w,   llvm::Intrinsic::mips_bseti_b, llvm::Intrinsic::mips_bseti_d, llvm::Intrinsic::mips_bseti_h, llvm::Intrinsic::mips_bseti_w,   llvm::Intrinsic::mips_bz_b, llvm::Intrinsic::mips_bz_d, llvm::Intrinsic::mips_bz_h, llvm::Intrinsic::mips_bz_v,   llvm::Intrinsic::mips_bz_w, llvm::Intrinsic::mips_ceq_b, llvm::Intrinsic::mips_ceq_d, llvm::Intrinsic::mips_ceq_h,   llvm::Intrinsic::mips_ceq_w, llvm::Intrinsic::mips_ceqi_b, llvm::Intrinsic::mips_ceqi_d, llvm::Intrinsic::mips_ceqi_h,   llvm::Intrinsic::mips_ceqi_w, llvm::Intrinsic::mips_cfcmsa, llvm::Intrinsic::mips_cle_s_b, llvm::Intrinsic::mips_cle_s_d,   llvm::Intrinsic::mips_cle_s_h, llvm::Intrinsic::mips_cle_s_w, llvm::Intrinsic::mips_cle_u_b, llvm::Intrinsic::mips_cle_u_d,   llvm::Intrinsic::mips_cle_u_h, llvm::Intrinsic::mips_cle_u_w, llvm::Intrinsic::mips_clei_s_b, llvm::Intrinsic::mips_clei_s_d,   llvm::Intrinsic::mips_clei_s_h, llvm::Intrinsic::mips_clei_s_w, llvm::Intrinsic::mips_clei_u_b, llvm::Intrinsic::mips_clei_u_d,   llvm::Intrinsic::mips_clei_u_h, llvm::Intrinsic::mips_clei_u_w, llvm::Intrinsic::mips_clt_s_b, llvm::Intrinsic::mips_clt_s_d,   llvm::Intrinsic::mips_clt_s_h, llvm::Intrinsic::mips_clt_s_w, llvm::Intrinsic::mips_clt_u_b, llvm::Intrinsic::mips_clt_u_d,   llvm::Intrinsic::mips_clt_u_h, llvm::Intrinsic::mips_clt_u_w, llvm::Intrinsic::mips_clti_s_b, llvm::Intrinsic::mips_clti_s_d,   llvm::Intrinsic::mips_clti_s_h, llvm::Intrinsic::mips_clti_s_w, llvm::Intrinsic::mips_clti_u_b, llvm::Intrinsic::mips_clti_u_d,   llvm::Intrinsic::mips_clti_u_h, llvm::Intrinsic::mips_clti_u_w, llvm::Intrinsic::mips_cmp_eq_ph, llvm::Intrinsic::mips_cmp_le_ph,   llvm::Intrinsic::mips_cmp_lt_ph, llvm::Intrinsic::mips_cmpgdu_eq_qb, llvm::Intrinsic::mips_cmpgdu_le_qb, llvm::Intrinsic::mips_cmpgdu_lt_qb,   llvm::Intrinsic::mips_cmpgu_eq_qb, llvm::Intrinsic::mips_cmpgu_le_qb, llvm::Intrinsic::mips_cmpgu_lt_qb, llvm::Intrinsic::mips_cmpu_eq_qb,   llvm::Intrinsic::mips_cmpu_le_qb, llvm::Intrinsic::mips_cmpu_lt_qb, llvm::Intrinsic::mips_copy_s_b, llvm::Intrinsic::mips_copy_s_d,   llvm::Intrinsic::mips_copy_s_h, llvm::Intrinsic::mips_copy_s_w, llvm::Intrinsic::mips_copy_u_b, llvm::Intrinsic::mips_copy_u_d,   llvm::Intrinsic::mips_copy_u_h, llvm::Intrinsic::mips_copy_u_w, llvm::Intrinsic::mips_ctcmsa, llvm::Intrinsic::mips_div_s_b,   llvm::Intrinsic::mips_div_s_d, llvm::Intrinsic::mips_div_s_h, llvm::Intrinsic::mips_div_s_w, llvm::Intrinsic::mips_div_u_b,   llvm::Intrinsic::mips_div_u_d, llvm::Intrinsic::mips_div_u_h, llvm::Intrinsic::mips_div_u_w, llvm::Intrinsic::mips_dlsa,   llvm::Intrinsic::mips_dotp_s_d, llvm::Intrinsic::mips_dotp_s_h, llvm::Intrinsic::mips_dotp_s_w, llvm::Intrinsic::mips_dotp_u_d,   llvm::Intrinsic::mips_dotp_u_h, llvm::Intrinsic::mips_dotp_u_w, llvm::Intrinsic::mips_dpa_w_ph, llvm::Intrinsic::mips_dpadd_s_d,   llvm::Intrinsic::mips_dpadd_s_h, llvm::Intrinsic::mips_dpadd_s_w, llvm::Intrinsic::mips_dpadd_u_d, llvm::Intrinsic::mips_dpadd_u_h,   llvm::Intrinsic::mips_dpadd_u_w, llvm::Intrinsic::mips_dpaq_s_w_ph, llvm::Intrinsic::mips_dpaq_sa_l_w, llvm::Intrinsic::mips_dpaqx_s_w_ph,   llvm::Intrinsic::mips_dpaqx_sa_w_ph, llvm::Intrinsic::mips_dpau_h_qbl, llvm::Intrinsic::mips_dpau_h_qbr, llvm::Intrinsic::mips_dpax_w_ph,   llvm::Intrinsic::mips_dps_w_ph, llvm::Intrinsic::mips_dpsq_s_w_ph, llvm::Intrinsic::mips_dpsq_sa_l_w, llvm::Intrinsic::mips_dpsqx_s_w_ph,   llvm::Intrinsic::mips_dpsqx_sa_w_ph, llvm::Intrinsic::mips_dpsu_h_qbl, llvm::Intrinsic::mips_dpsu_h_qbr, llvm::Intrinsic::mips_dpsub_s_d,   llvm::Intrinsic::mips_dpsub_s_h, llvm::Intrinsic::mips_dpsub_s_w, llvm::Intrinsic::mips_dpsub_u_d, llvm::Intrinsic::mips_dpsub_u_h,   llvm::Intrinsic::mips_dpsub_u_w, llvm::Intrinsic::mips_dpsx_w_ph, llvm::Intrinsic::mips_extp, llvm::Intrinsic::mips_extpdp,   llvm::Intrinsic::mips_extr_r_w, llvm::Intrinsic::mips_extr_rs_w, llvm::Intrinsic::mips_extr_s_h, llvm::Intrinsic::mips_extr_w,   llvm::Intrinsic::mips_fadd_d, llvm::Intrinsic::mips_fadd_w, llvm::Intrinsic::mips_fcaf_d, llvm::Intrinsic::mips_fcaf_w,   llvm::Intrinsic::mips_fceq_d, llvm::Intrinsic::mips_fceq_w, llvm::Intrinsic::mips_fclass_d, llvm::Intrinsic::mips_fclass_w,   llvm::Intrinsic::mips_fcle_d, llvm::Intrinsic::mips_fcle_w, llvm::Intrinsic::mips_fclt_d, llvm::Intrinsic::mips_fclt_w,   llvm::Intrinsic::mips_fcne_d, llvm::Intrinsic::mips_fcne_w, llvm::Intrinsic::mips_fcor_d, llvm::Intrinsic::mips_fcor_w,   llvm::Intrinsic::mips_fcueq_d, llvm::Intrinsic::mips_fcueq_w, llvm::Intrinsic::mips_fcule_d, llvm::Intrinsic::mips_fcule_w,   llvm::Intrinsic::mips_fcult_d, llvm::Intrinsic::mips_fcult_w, llvm::Intrinsic::mips_fcun_d, llvm::Intrinsic::mips_fcun_w,   llvm::Intrinsic::mips_fcune_d, llvm::Intrinsic::mips_fcune_w, llvm::Intrinsic::mips_fdiv_d, llvm::Intrinsic::mips_fdiv_w,   llvm::Intrinsic::mips_fexdo_h, llvm::Intrinsic::mips_fexdo_w, llvm::Intrinsic::mips_fexp2_d, llvm::Intrinsic::mips_fexp2_w,   llvm::Intrinsic::mips_fexupl_d, llvm::Intrinsic::mips_fexupl_w, llvm::Intrinsic::mips_fexupr_d, llvm::Intrinsic::mips_fexupr_w,   llvm::Intrinsic::mips_ffint_s_d, llvm::Intrinsic::mips_ffint_s_w, llvm::Intrinsic::mips_ffint_u_d, llvm::Intrinsic::mips_ffint_u_w,   llvm::Intrinsic::mips_ffql_d, llvm::Intrinsic::mips_ffql_w, llvm::Intrinsic::mips_ffqr_d, llvm::Intrinsic::mips_ffqr_w,   llvm::Intrinsic::mips_fill_b, llvm::Intrinsic::mips_fill_d, llvm::Intrinsic::mips_fill_h, llvm::Intrinsic::mips_fill_w,   llvm::Intrinsic::mips_flog2_d, llvm::Intrinsic::mips_flog2_w, llvm::Intrinsic::mips_fmadd_d, llvm::Intrinsic::mips_fmadd_w,   llvm::Intrinsic::mips_fmax_a_d, llvm::Intrinsic::mips_fmax_a_w, llvm::Intrinsic::mips_fmax_d, llvm::Intrinsic::mips_fmax_w,   llvm::Intrinsic::mips_fmin_a_d, llvm::Intrinsic::mips_fmin_a_w, llvm::Intrinsic::mips_fmin_d, llvm::Intrinsic::mips_fmin_w,   llvm::Intrinsic::mips_fmsub_d, llvm::Intrinsic::mips_fmsub_w, llvm::Intrinsic::mips_fmul_d, llvm::Intrinsic::mips_fmul_w,   llvm::Intrinsic::mips_frcp_d, llvm::Intrinsic::mips_frcp_w, llvm::Intrinsic::mips_frint_d, llvm::Intrinsic::mips_frint_w,   llvm::Intrinsic::mips_frsqrt_d, llvm::Intrinsic::mips_frsqrt_w, llvm::Intrinsic::mips_fsaf_d, llvm::Intrinsic::mips_fsaf_w,   llvm::Intrinsic::mips_fseq_d, llvm::Intrinsic::mips_fseq_w, llvm::Intrinsic::mips_fsle_d, llvm::Intrinsic::mips_fsle_w,   llvm::Intrinsic::mips_fslt_d, llvm::Intrinsic::mips_fslt_w, llvm::Intrinsic::mips_fsne_d, llvm::Intrinsic::mips_fsne_w,   llvm::Intrinsic::mips_fsor_d, llvm::Intrinsic::mips_fsor_w, llvm::Intrinsic::mips_fsqrt_d, llvm::Intrinsic::mips_fsqrt_w,   llvm::Intrinsic::mips_fsub_d, llvm::Intrinsic::mips_fsub_w, llvm::Intrinsic::mips_fsueq_d, llvm::Intrinsic::mips_fsueq_w,   llvm::Intrinsic::mips_fsule_d, llvm::Intrinsic::mips_fsule_w, llvm::Intrinsic::mips_fsult_d, llvm::Intrinsic::mips_fsult_w,   llvm::Intrinsic::mips_fsun_d, llvm::Intrinsic::mips_fsun_w, llvm::Intrinsic::mips_fsune_d, llvm::Intrinsic::mips_fsune_w,   llvm::Intrinsic::mips_ftint_s_d, llvm::Intrinsic::mips_ftint_s_w, llvm::Intrinsic::mips_ftint_u_d, llvm::Intrinsic::mips_ftint_u_w,   llvm::Intrinsic::mips_ftq_h, llvm::Intrinsic::mips_ftq_w, llvm::Intrinsic::mips_ftrunc_s_d, llvm::Intrinsic::mips_ftrunc_s_w,   llvm::Intrinsic::mips_ftrunc_u_d, llvm::Intrinsic::mips_ftrunc_u_w, llvm::Intrinsic::mips_hadd_s_d, llvm::Intrinsic::mips_hadd_s_h,   llvm::Intrinsic::mips_hadd_s_w, llvm::Intrinsic::mips_hadd_u_d, llvm::Intrinsic::mips_hadd_u_h, llvm::Intrinsic::mips_hadd_u_w,   llvm::Intrinsic::mips_hsub_s_d, llvm::Intrinsic::mips_hsub_s_h, llvm::Intrinsic::mips_hsub_s_w, llvm::Intrinsic::mips_hsub_u_d,   llvm::Intrinsic::mips_hsub_u_h, llvm::Intrinsic::mips_hsub_u_w, llvm::Intrinsic::mips_ilvev_b, llvm::Intrinsic::mips_ilvev_d,   llvm::Intrinsic::mips_ilvev_h, llvm::Intrinsic::mips_ilvev_w, llvm::Intrinsic::mips_ilvl_b, llvm::Intrinsic::mips_ilvl_d,   llvm::Intrinsic::mips_ilvl_h, llvm::Intrinsic::mips_ilvl_w, llvm::Intrinsic::mips_ilvod_b, llvm::Intrinsic::mips_ilvod_d,   llvm::Intrinsic::mips_ilvod_h, llvm::Intrinsic::mips_ilvod_w, llvm::Intrinsic::mips_ilvr_b, llvm::Intrinsic::mips_ilvr_d,   llvm::Intrinsic::mips_ilvr_h, llvm::Intrinsic::mips_ilvr_w, llvm::Intrinsic::mips_insert_b, llvm::Intrinsic::mips_insert_d,   llvm::Intrinsic::mips_insert_h, llvm::Intrinsic::mips_insert_w, llvm::Intrinsic::mips_insv, llvm::Intrinsic::mips_insve_b,   llvm::Intrinsic::mips_insve_d, llvm::Intrinsic::mips_insve_h, llvm::Intrinsic::mips_insve_w, llvm::Intrinsic::mips_lbux,   llvm::Intrinsic::mips_ld_b, llvm::Intrinsic::mips_ld_d, llvm::Intrinsic::mips_ld_h, llvm::Intrinsic::mips_ld_w,   llvm::Intrinsic::mips_ldi_b, llvm::Intrinsic::mips_ldi_d, llvm::Intrinsic::mips_ldi_h, llvm::Intrinsic::mips_ldi_w,   llvm::Intrinsic::mips_lhx, llvm::Intrinsic::mips_lsa, llvm::Intrinsic::mips_lwx, llvm::Intrinsic::mips_madd,   llvm::Intrinsic::mips_madd_q_h, llvm::Intrinsic::mips_madd_q_w, llvm::Intrinsic::mips_maddr_q_h, llvm::Intrinsic::mips_maddr_q_w,   llvm::Intrinsic::mips_maddu, llvm::Intrinsic::mips_maddv_b, llvm::Intrinsic::mips_maddv_d, llvm::Intrinsic::mips_maddv_h,   llvm::Intrinsic::mips_maddv_w, llvm::Intrinsic::mips_maq_s_w_phl, llvm::Intrinsic::mips_maq_s_w_phr, llvm::Intrinsic::mips_maq_sa_w_phl,   llvm::Intrinsic::mips_maq_sa_w_phr, llvm::Intrinsic::mips_max_a_b, llvm::Intrinsic::mips_max_a_d, llvm::Intrinsic::mips_max_a_h,   llvm::Intrinsic::mips_max_a_w, llvm::Intrinsic::mips_max_s_b, llvm::Intrinsic::mips_max_s_d, llvm::Intrinsic::mips_max_s_h,   llvm::Intrinsic::mips_max_s_w, llvm::Intrinsic::mips_max_u_b, llvm::Intrinsic::mips_max_u_d, llvm::Intrinsic::mips_max_u_h,   llvm::Intrinsic::mips_max_u_w, llvm::Intrinsic::mips_maxi_s_b, llvm::Intrinsic::mips_maxi_s_d, llvm::Intrinsic::mips_maxi_s_h,   llvm::Intrinsic::mips_maxi_s_w, llvm::Intrinsic::mips_maxi_u_b, llvm::Intrinsic::mips_maxi_u_d, llvm::Intrinsic::mips_maxi_u_h,   llvm::Intrinsic::mips_maxi_u_w, llvm::Intrinsic::mips_min_a_b, llvm::Intrinsic::mips_min_a_d, llvm::Intrinsic::mips_min_a_h,   llvm::Intrinsic::mips_min_a_w, llvm::Intrinsic::mips_min_s_b, llvm::Intrinsic::mips_min_s_d, llvm::Intrinsic::mips_min_s_h,   llvm::Intrinsic::mips_min_s_w, llvm::Intrinsic::mips_min_u_b, llvm::Intrinsic::mips_min_u_d, llvm::Intrinsic::mips_min_u_h,   llvm::Intrinsic::mips_min_u_w, llvm::Intrinsic::mips_mini_s_b, llvm::Intrinsic::mips_mini_s_d, llvm::Intrinsic::mips_mini_s_h,   llvm::Intrinsic::mips_mini_s_w, llvm::Intrinsic::mips_mini_u_b, llvm::Intrinsic::mips_mini_u_d, llvm::Intrinsic::mips_mini_u_h,   llvm::Intrinsic::mips_mini_u_w, llvm::Intrinsic::mips_mod_s_b, llvm::Intrinsic::mips_mod_s_d, llvm::Intrinsic::mips_mod_s_h,   llvm::Intrinsic::mips_mod_s_w, llvm::Intrinsic::mips_mod_u_b, llvm::Intrinsic::mips_mod_u_d, llvm::Intrinsic::mips_mod_u_h,   llvm::Intrinsic::mips_mod_u_w, llvm::Intrinsic::mips_modsub, llvm::Intrinsic::mips_move_v, llvm::Intrinsic::mips_msub,   llvm::Intrinsic::mips_msub_q_h, llvm::Intrinsic::mips_msub_q_w, llvm::Intrinsic::mips_msubr_q_h, llvm::Intrinsic::mips_msubr_q_w,   llvm::Intrinsic::mips_msubu, llvm::Intrinsic::mips_msubv_b, llvm::Intrinsic::mips_msubv_d, llvm::Intrinsic::mips_msubv_h,   llvm::Intrinsic::mips_msubv_w, llvm::Intrinsic::mips_mthlip, llvm::Intrinsic::mips_mul_ph, llvm::Intrinsic::mips_mul_q_h,   llvm::Intrinsic::mips_mul_q_w, llvm::Intrinsic::mips_mul_s_ph, llvm::Intrinsic::mips_muleq_s_w_phl, llvm::Intrinsic::mips_muleq_s_w_phr,   llvm::Intrinsic::mips_muleu_s_ph_qbl, llvm::Intrinsic::mips_muleu_s_ph_qbr, llvm::Intrinsic::mips_mulq_rs_ph, llvm::Intrinsic::mips_mulq_rs_w,   llvm::Intrinsic::mips_mulq_s_ph, llvm::Intrinsic::mips_mulq_s_w, llvm::Intrinsic::mips_mulr_q_h, llvm::Intrinsic::mips_mulr_q_w,   llvm::Intrinsic::mips_mulsa_w_ph, llvm::Intrinsic::mips_mulsaq_s_w_ph, llvm::Intrinsic::mips_mult, llvm::Intrinsic::mips_multu,   llvm::Intrinsic::mips_mulv_b, llvm::Intrinsic::mips_mulv_d, llvm::Intrinsic::mips_mulv_h, llvm::Intrinsic::mips_mulv_w,   llvm::Intrinsic::mips_nloc_b, llvm::Intrinsic::mips_nloc_d, llvm::Intrinsic::mips_nloc_h, llvm::Intrinsic::mips_nloc_w,   llvm::Intrinsic::mips_nlzc_b, llvm::Intrinsic::mips_nlzc_d, llvm::Intrinsic::mips_nlzc_h, llvm::Intrinsic::mips_nlzc_w,   llvm::Intrinsic::mips_nor_v, llvm::Intrinsic::mips_nori_b, llvm::Intrinsic::mips_or_v, llvm::Intrinsic::mips_ori_b,   llvm::Intrinsic::mips_packrl_ph, llvm::Intrinsic::mips_pckev_b, llvm::Intrinsic::mips_pckev_d, llvm::Intrinsic::mips_pckev_h,   llvm::Intrinsic::mips_pckev_w, llvm::Intrinsic::mips_pckod_b, llvm::Intrinsic::mips_pckod_d, llvm::Intrinsic::mips_pckod_h,   llvm::Intrinsic::mips_pckod_w, llvm::Intrinsic::mips_pcnt_b, llvm::Intrinsic::mips_pcnt_d, llvm::Intrinsic::mips_pcnt_h,   llvm::Intrinsic::mips_pcnt_w, llvm::Intrinsic::mips_pick_ph, llvm::Intrinsic::mips_pick_qb, llvm::Intrinsic::mips_preceq_w_phl,   llvm::Intrinsic::mips_preceq_w_phr, llvm::Intrinsic::mips_precequ_ph_qbl, llvm::Intrinsic::mips_precequ_ph_qbla, llvm::Intrinsic::mips_precequ_ph_qbr,   llvm::Intrinsic::mips_precequ_ph_qbra, llvm::Intrinsic::mips_preceu_ph_qbl, llvm::Intrinsic::mips_preceu_ph_qbla, llvm::Intrinsic::mips_preceu_ph_qbr,   llvm::Intrinsic::mips_preceu_ph_qbra, llvm::Intrinsic::mips_precr_qb_ph, llvm::Intrinsic::mips_precr_sra_ph_w, llvm::Intrinsic::mips_precr_sra_r_ph_w,   llvm::Intrinsic::mips_precrq_ph_w, llvm::Intrinsic::mips_precrq_qb_ph, llvm::Intrinsic::mips_precrq_rs_ph_w, llvm::Intrinsic::mips_precrqu_s_qb_ph,   llvm::Intrinsic::mips_prepend, llvm::Intrinsic::mips_raddu_w_qb, llvm::Intrinsic::mips_rddsp, llvm::Intrinsic::mips_repl_ph,   llvm::Intrinsic::mips_repl_qb, llvm::Intrinsic::mips_sat_s_b, llvm::Intrinsic::mips_sat_s_d, llvm::Intrinsic::mips_sat_s_h,   llvm::Intrinsic::mips_sat_s_w, llvm::Intrinsic::mips_sat_u_b, llvm::Intrinsic::mips_sat_u_d, llvm::Intrinsic::mips_sat_u_h,   llvm::Intrinsic::mips_sat_u_w, llvm::Intrinsic::mips_shf_b, llvm::Intrinsic::mips_shf_h, llvm::Intrinsic::mips_shf_w,   llvm::Intrinsic::mips_shilo, llvm::Intrinsic::mips_shll_ph, llvm::Intrinsic::mips_shll_qb, llvm::Intrinsic::mips_shll_s_ph,   llvm::Intrinsic::mips_shll_s_w, llvm::Intrinsic::mips_shra_ph, llvm::Intrinsic::mips_shra_qb, llvm::Intrinsic::mips_shra_r_ph,   llvm::Intrinsic::mips_shra_r_qb, llvm::Intrinsic::mips_shra_r_w, llvm::Intrinsic::mips_shrl_ph, llvm::Intrinsic::mips_shrl_qb,   llvm::Intrinsic::mips_sld_b, llvm::Intrinsic::mips_sld_d, llvm::Intrinsic::mips_sld_h, llvm::Intrinsic::mips_sld_w,   llvm::Intrinsic::mips_sldi_b, llvm::Intrinsic::mips_sldi_d, llvm::Intrinsic::mips_sldi_h, llvm::Intrinsic::mips_sldi_w,   llvm::Intrinsic::mips_sll_b, llvm::Intrinsic::mips_sll_d, llvm::Intrinsic::mips_sll_h, llvm::Intrinsic::mips_sll_w,   llvm::Intrinsic::mips_slli_b, llvm::Intrinsic::mips_slli_d, llvm::Intrinsic::mips_slli_h, llvm::Intrinsic::mips_slli_w,   llvm::Intrinsic::mips_splat_b, llvm::Intrinsic::mips_splat_d, llvm::Intrinsic::mips_splat_h, llvm::Intrinsic::mips_splat_w,   llvm::Intrinsic::mips_splati_b, llvm::Intrinsic::mips_splati_d, llvm::Intrinsic::mips_splati_h, llvm::Intrinsic::mips_splati_w,   llvm::Intrinsic::mips_sra_b, llvm::Intrinsic::mips_sra_d, llvm::Intrinsic::mips_sra_h, llvm::Intrinsic::mips_sra_w,   llvm::Intrinsic::mips_srai_b, llvm::Intrinsic::mips_srai_d, llvm::Intrinsic::mips_srai_h, llvm::Intrinsic::mips_srai_w,   llvm::Intrinsic::mips_srar_b, llvm::Intrinsic::mips_srar_d, llvm::Intrinsic::mips_srar_h, llvm::Intrinsic::mips_srar_w,   llvm::Intrinsic::mips_srari_b, llvm::Intrinsic::mips_srari_d, llvm::Intrinsic::mips_srari_h, llvm::Intrinsic::mips_srari_w,   llvm::Intrinsic::mips_srl_b, llvm::Intrinsic::mips_srl_d, llvm::Intrinsic::mips_srl_h, llvm::Intrinsic::mips_srl_w,   llvm::Intrinsic::mips_srli_b, llvm::Intrinsic::mips_srli_d, llvm::Intrinsic::mips_srli_h, llvm::Intrinsic::mips_srli_w,   llvm::Intrinsic::mips_srlr_b, llvm::Intrinsic::mips_srlr_d, llvm::Intrinsic::mips_srlr_h, llvm::Intrinsic::mips_srlr_w,   llvm::Intrinsic::mips_srlri_b, llvm::Intrinsic::mips_srlri_d, llvm::Intrinsic::mips_srlri_h, llvm::Intrinsic::mips_srlri_w,   llvm::Intrinsic::mips_st_b, llvm::Intrinsic::mips_st_d, llvm::Intrinsic::mips_st_h, llvm::Intrinsic::mips_st_w,   llvm::Intrinsic::mips_subq_ph, llvm::Intrinsic::mips_subq_s_ph, llvm::Intrinsic::mips_subq_s_w, llvm::Intrinsic::mips_subqh_ph,   llvm::Intrinsic::mips_subqh_r_ph, llvm::Intrinsic::mips_subqh_r_w, llvm::Intrinsic::mips_subqh_w, llvm::Intrinsic::mips_subs_s_b,   llvm::Intrinsic::mips_subs_s_d, llvm::Intrinsic::mips_subs_s_h, llvm::Intrinsic::mips_subs_s_w, llvm::Intrinsic::mips_subs_u_b,   llvm::Intrinsic::mips_subs_u_d, llvm::Intrinsic::mips_subs_u_h, llvm::Intrinsic::mips_subs_u_w, llvm::Intrinsic::mips_subsus_u_b,   llvm::Intrinsic::mips_subsus_u_d, llvm::Intrinsic::mips_subsus_u_h, llvm::Intrinsic::mips_subsus_u_w, llvm::Intrinsic::mips_subsuu_s_b,   llvm::Intrinsic::mips_subsuu_s_d, llvm::Intrinsic::mips_subsuu_s_h, llvm::Intrinsic::mips_subsuu_s_w, llvm::Intrinsic::mips_subu_ph,   llvm::Intrinsic::mips_subu_qb, llvm::Intrinsic::mips_subu_s_ph, llvm::Intrinsic::mips_subu_s_qb, llvm::Intrinsic::mips_subuh_qb,   llvm::Intrinsic::mips_subuh_r_qb, llvm::Intrinsic::mips_subv_b, llvm::Intrinsic::mips_subv_d, llvm::Intrinsic::mips_subv_h,   llvm::Intrinsic::mips_subv_w, llvm::Intrinsic::mips_subvi_b, llvm::Intrinsic::mips_subvi_d, llvm::Intrinsic::mips_subvi_h,   llvm::Intrinsic::mips_subvi_w, llvm::Intrinsic::mips_vshf_b, llvm::Intrinsic::mips_vshf_d, llvm::Intrinsic::mips_vshf_h,   llvm::Intrinsic::mips_vshf_w, llvm::Intrinsic::mips_wrdsp, llvm::Intrinsic::mips_xor_v, llvm::Intrinsic::mips_xori_b,   llvm::Intrinsic::nvvm_add_rm_d, llvm::Intrinsic::nvvm_add_rm_f, llvm::Intrinsic::nvvm_add_rm_ftz_f, llvm::Intrinsic::nvvm_add_rn_d,   llvm::Intrinsic::nvvm_add_rn_f, llvm::Intrinsic::nvvm_add_rn_ftz_f, llvm::Intrinsic::nvvm_add_rp_d, llvm::Intrinsic::nvvm_add_rp_f,   llvm::Intrinsic::nvvm_add_rp_ftz_f, llvm::Intrinsic::nvvm_add_rz_d, llvm::Intrinsic::nvvm_add_rz_f, llvm::Intrinsic::nvvm_add_rz_ftz_f,   llvm::Intrinsic::nvvm_atomic_add_gen_f_cta, llvm::Intrinsic::nvvm_atomic_add_gen_f_sys, llvm::Intrinsic::nvvm_atomic_add_gen_i_cta, llvm::Intrinsic::nvvm_atomic_add_gen_i_sys,   llvm::Intrinsic::nvvm_atomic_and_gen_i_cta, llvm::Intrinsic::nvvm_atomic_and_gen_i_sys, llvm::Intrinsic::nvvm_atomic_cas_gen_i_cta, llvm::Intrinsic::nvvm_atomic_cas_gen_i_sys,   llvm::Intrinsic::nvvm_atomic_dec_gen_i_cta, llvm::Intrinsic::nvvm_atomic_dec_gen_i_sys, llvm::Intrinsic::nvvm_atomic_exch_gen_i_cta, llvm::Intrinsic::nvvm_atomic_exch_gen_i_sys,   llvm::Intrinsic::nvvm_atomic_inc_gen_i_cta, llvm::Intrinsic::nvvm_atomic_inc_gen_i_sys, llvm::Intrinsic::nvvm_atomic_load_add_f32, llvm::Intrinsic::nvvm_atomic_load_add_f64,   llvm::Intrinsic::nvvm_atomic_load_dec_32, llvm::Intrinsic::nvvm_atomic_load_inc_32, llvm::Intrinsic::nvvm_atomic_max_gen_i_cta, llvm::Intrinsic::nvvm_atomic_max_gen_i_sys,   llvm::Intrinsic::nvvm_atomic_min_gen_i_cta, llvm::Intrinsic::nvvm_atomic_min_gen_i_sys, llvm::Intrinsic::nvvm_atomic_or_gen_i_cta, llvm::Intrinsic::nvvm_atomic_or_gen_i_sys,   llvm::Intrinsic::nvvm_atomic_xor_gen_i_cta, llvm::Intrinsic::nvvm_atomic_xor_gen_i_sys, llvm::Intrinsic::nvvm_bar_sync, llvm::Intrinsic::nvvm_bar_warp_sync,   llvm::Intrinsic::nvvm_barrier, llvm::Intrinsic::nvvm_barrier_n, llvm::Intrinsic::nvvm_barrier_sync, llvm::Intrinsic::nvvm_barrier_sync_cnt,   llvm::Intrinsic::nvvm_barrier0, llvm::Intrinsic::nvvm_barrier0_and, llvm::Intrinsic::nvvm_barrier0_or, llvm::Intrinsic::nvvm_barrier0_popc,   llvm::Intrinsic::nvvm_bitcast_d2ll, llvm::Intrinsic::nvvm_bitcast_f2i, llvm::Intrinsic::nvvm_bitcast_i2f, llvm::Intrinsic::nvvm_bitcast_ll2d,   llvm::Intrinsic::nvvm_ceil_d, llvm::Intrinsic::nvvm_ceil_f, llvm::Intrinsic::nvvm_ceil_ftz_f, llvm::Intrinsic::nvvm_compiler_error,   llvm::Intrinsic::nvvm_compiler_warn, llvm::Intrinsic::nvvm_cos_approx_f, llvm::Intrinsic::nvvm_cos_approx_ftz_f, llvm::Intrinsic::nvvm_d2f_rm,   llvm::Intrinsic::nvvm_d2f_rm_ftz, llvm::Intrinsic::nvvm_d2f_rn, llvm::Intrinsic::nvvm_d2f_rn_ftz, llvm::Intrinsic::nvvm_d2f_rp,   llvm::Intrinsic::nvvm_d2f_rp_ftz, llvm::Intrinsic::nvvm_d2f_rz, llvm::Intrinsic::nvvm_d2f_rz_ftz, llvm::Intrinsic::nvvm_d2i_hi,   llvm::Intrinsic::nvvm_d2i_lo, llvm::Intrinsic::nvvm_d2i_rm, llvm::Intrinsic::nvvm_d2i_rn, llvm::Intrinsic::nvvm_d2i_rp,   llvm::Intrinsic::nvvm_d2i_rz, llvm::Intrinsic::nvvm_d2ll_rm, llvm::Intrinsic::nvvm_d2ll_rn, llvm::Intrinsic::nvvm_d2ll_rp,   llvm::Intrinsic::nvvm_d2ll_rz, llvm::Intrinsic::nvvm_d2ui_rm, llvm::Intrinsic::nvvm_d2ui_rn, llvm::Intrinsic::nvvm_d2ui_rp,   llvm::Intrinsic::nvvm_d2ui_rz, llvm::Intrinsic::nvvm_d2ull_rm, llvm::Intrinsic::nvvm_d2ull_rn, llvm::Intrinsic::nvvm_d2ull_rp,   llvm::Intrinsic::nvvm_d2ull_rz, llvm::Intrinsic::nvvm_div_approx_f, llvm::Intrinsic::nvvm_div_approx_ftz_f, llvm::Intrinsic::nvvm_div_rm_d,   llvm::Intrinsic::nvvm_div_rm_f, llvm::Intrinsic::nvvm_div_rm_ftz_f, llvm::Intrinsic::nvvm_div_rn_d, llvm::Intrinsic::nvvm_div_rn_f,   llvm::Intrinsic::nvvm_div_rn_ftz_f, llvm::Intrinsic::nvvm_div_rp_d, llvm::Intrinsic::nvvm_div_rp_f, llvm::Intrinsic::nvvm_div_rp_ftz_f,   llvm::Intrinsic::nvvm_div_rz_d, llvm::Intrinsic::nvvm_div_rz_f, llvm::Intrinsic::nvvm_div_rz_ftz_f, llvm::Intrinsic::nvvm_ex2_approx_d,   llvm::Intrinsic::nvvm_ex2_approx_f, llvm::Intrinsic::nvvm_ex2_approx_ftz_f, llvm::Intrinsic::nvvm_f2h_rn, llvm::Intrinsic::nvvm_f2h_rn_ftz,   llvm::Intrinsic::nvvm_f2i_rm, llvm::Intrinsic::nvvm_f2i_rm_ftz, llvm::Intrinsic::nvvm_f2i_rn, llvm::Intrinsic::nvvm_f2i_rn_ftz,   llvm::Intrinsic::nvvm_f2i_rp, llvm::Intrinsic::nvvm_f2i_rp_ftz, llvm::Intrinsic::nvvm_f2i_rz, llvm::Intrinsic::nvvm_f2i_rz_ftz,   llvm::Intrinsic::nvvm_f2ll_rm, llvm::Intrinsic::nvvm_f2ll_rm_ftz, llvm::Intrinsic::nvvm_f2ll_rn, llvm::Intrinsic::nvvm_f2ll_rn_ftz,   llvm::Intrinsic::nvvm_f2ll_rp, llvm::Intrinsic::nvvm_f2ll_rp_ftz, llvm::Intrinsic::nvvm_f2ll_rz, llvm::Intrinsic::nvvm_f2ll_rz_ftz,   llvm::Intrinsic::nvvm_f2ui_rm, llvm::Intrinsic::nvvm_f2ui_rm_ftz, llvm::Intrinsic::nvvm_f2ui_rn, llvm::Intrinsic::nvvm_f2ui_rn_ftz,   llvm::Intrinsic::nvvm_f2ui_rp, llvm::Intrinsic::nvvm_f2ui_rp_ftz, llvm::Intrinsic::nvvm_f2ui_rz, llvm::Intrinsic::nvvm_f2ui_rz_ftz,   llvm::Intrinsic::nvvm_f2ull_rm, llvm::Intrinsic::nvvm_f2ull_rm_ftz, llvm::Intrinsic::nvvm_f2ull_rn, llvm::Intrinsic::nvvm_f2ull_rn_ftz,   llvm::Intrinsic::nvvm_f2ull_rp, llvm::Intrinsic::nvvm_f2ull_rp_ftz, llvm::Intrinsic::nvvm_f2ull_rz, llvm::Intrinsic::nvvm_f2ull_rz_ftz,   llvm::Intrinsic::nvvm_fabs_d, llvm::Intrinsic::nvvm_fabs_f, llvm::Intrinsic::nvvm_fabs_ftz_f, llvm::Intrinsic::nvvm_floor_d,   llvm::Intrinsic::nvvm_floor_f, llvm::Intrinsic::nvvm_floor_ftz_f, llvm::Intrinsic::nvvm_fma_rm_d, llvm::Intrinsic::nvvm_fma_rm_f,   llvm::Intrinsic::nvvm_fma_rm_ftz_f, llvm::Intrinsic::nvvm_fma_rn_d, llvm::Intrinsic::nvvm_fma_rn_f, llvm::Intrinsic::nvvm_fma_rn_ftz_f,   llvm::Intrinsic::nvvm_fma_rp_d, llvm::Intrinsic::nvvm_fma_rp_f, llvm::Intrinsic::nvvm_fma_rp_ftz_f, llvm::Intrinsic::nvvm_fma_rz_d,   llvm::Intrinsic::nvvm_fma_rz_f, llvm::Intrinsic::nvvm_fma_rz_ftz_f, llvm::Intrinsic::nvvm_fmax_d, llvm::Intrinsic::nvvm_fmax_f,   llvm::Intrinsic::nvvm_fmax_ftz_f, llvm::Intrinsic::nvvm_fmin_d, llvm::Intrinsic::nvvm_fmin_f, llvm::Intrinsic::nvvm_fmin_ftz_f,   llvm::Intrinsic::nvvm_fns, llvm::Intrinsic::nvvm_i2d_rm, llvm::Intrinsic::nvvm_i2d_rn, llvm::Intrinsic::nvvm_i2d_rp,   llvm::Intrinsic::nvvm_i2d_rz, llvm::Intrinsic::nvvm_i2f_rm, llvm::Intrinsic::nvvm_i2f_rn, llvm::Intrinsic::nvvm_i2f_rp,   llvm::Intrinsic::nvvm_i2f_rz, llvm::Intrinsic::nvvm_isspacep_const, llvm::Intrinsic::nvvm_isspacep_global, llvm::Intrinsic::nvvm_isspacep_local,   llvm::Intrinsic::nvvm_isspacep_shared, llvm::Intrinsic::nvvm_istypep_sampler, llvm::Intrinsic::nvvm_istypep_surface, llvm::Intrinsic::nvvm_istypep_texture,   llvm::Intrinsic::nvvm_ldg_global_f, llvm::Intrinsic::nvvm_ldg_global_i, llvm::Intrinsic::nvvm_ldg_global_p, llvm::Intrinsic::nvvm_ldu_global_f,   llvm::Intrinsic::nvvm_ldu_global_i, llvm::Intrinsic::nvvm_ldu_global_p, llvm::Intrinsic::nvvm_lg2_approx_d, llvm::Intrinsic::nvvm_lg2_approx_f,   llvm::Intrinsic::nvvm_lg2_approx_ftz_f, llvm::Intrinsic::nvvm_ll2d_rm, llvm::Intrinsic::nvvm_ll2d_rn, llvm::Intrinsic::nvvm_ll2d_rp,   llvm::Intrinsic::nvvm_ll2d_rz, llvm::Intrinsic::nvvm_ll2f_rm, llvm::Intrinsic::nvvm_ll2f_rn, llvm::Intrinsic::nvvm_ll2f_rp,   llvm::Intrinsic::nvvm_ll2f_rz, llvm::Intrinsic::nvvm_lohi_i2d, llvm::Intrinsic::nvvm_match_all_sync_i32p, llvm::Intrinsic::nvvm_match_all_sync_i64p,   llvm::Intrinsic::nvvm_match_any_sync_i32, llvm::Intrinsic::nvvm_match_any_sync_i64, llvm::Intrinsic::nvvm_membar_cta, llvm::Intrinsic::nvvm_membar_gl,   llvm::Intrinsic::nvvm_membar_sys, llvm::Intrinsic::nvvm_move_double, llvm::Intrinsic::nvvm_move_float, llvm::Intrinsic::nvvm_move_i16,   llvm::Intrinsic::nvvm_move_i32, llvm::Intrinsic::nvvm_move_i64, llvm::Intrinsic::nvvm_move_ptr, llvm::Intrinsic::nvvm_mul_rm_d,   llvm::Intrinsic::nvvm_mul_rm_f, llvm::Intrinsic::nvvm_mul_rm_ftz_f, llvm::Intrinsic::nvvm_mul_rn_d, llvm::Intrinsic::nvvm_mul_rn_f,   llvm::Intrinsic::nvvm_mul_rn_ftz_f, llvm::Intrinsic::nvvm_mul_rp_d, llvm::Intrinsic::nvvm_mul_rp_f, llvm::Intrinsic::nvvm_mul_rp_ftz_f,   llvm::Intrinsic::nvvm_mul_rz_d, llvm::Intrinsic::nvvm_mul_rz_f, llvm::Intrinsic::nvvm_mul_rz_ftz_f, llvm::Intrinsic::nvvm_mul24_i,   llvm::Intrinsic::nvvm_mul24_ui, llvm::Intrinsic::nvvm_mulhi_i, llvm::Intrinsic::nvvm_mulhi_ll, llvm::Intrinsic::nvvm_mulhi_ui,   llvm::Intrinsic::nvvm_mulhi_ull, llvm::Intrinsic::nvvm_prmt, llvm::Intrinsic::nvvm_ptr_constant_to_gen, llvm::Intrinsic::nvvm_ptr_gen_to_constant,   llvm::Intrinsic::nvvm_ptr_gen_to_global, llvm::Intrinsic::nvvm_ptr_gen_to_local, llvm::Intrinsic::nvvm_ptr_gen_to_param, llvm::Intrinsic::nvvm_ptr_gen_to_shared,   llvm::Intrinsic::nvvm_ptr_global_to_gen, llvm::Intrinsic::nvvm_ptr_local_to_gen, llvm::Intrinsic::nvvm_ptr_shared_to_gen, llvm::Intrinsic::nvvm_rcp_approx_ftz_d,   llvm::Intrinsic::nvvm_rcp_rm_d, llvm::Intrinsic::nvvm_rcp_rm_f, llvm::Intrinsic::nvvm_rcp_rm_ftz_f, llvm::Intrinsic::nvvm_rcp_rn_d,   llvm::Intrinsic::nvvm_rcp_rn_f, llvm::Intrinsic::nvvm_rcp_rn_ftz_f, llvm::Intrinsic::nvvm_rcp_rp_d, llvm::Intrinsic::nvvm_rcp_rp_f,   llvm::Intrinsic::nvvm_rcp_rp_ftz_f, llvm::Intrinsic::nvvm_rcp_rz_d, llvm::Intrinsic::nvvm_rcp_rz_f, llvm::Intrinsic::nvvm_rcp_rz_ftz_f,   llvm::Intrinsic::nvvm_read_ptx_sreg_clock, llvm::Intrinsic::nvvm_read_ptx_sreg_clock64, llvm::Intrinsic::nvvm_read_ptx_sreg_ctaid_w, llvm::Intrinsic::nvvm_read_ptx_sreg_ctaid_x,   llvm::Intrinsic::nvvm_read_ptx_sreg_ctaid_y, llvm::Intrinsic::nvvm_read_ptx_sreg_ctaid_z, llvm::Intrinsic::nvvm_read_ptx_sreg_envreg0, llvm::Intrinsic::nvvm_read_ptx_sreg_envreg1,   llvm::Intrinsic::nvvm_read_ptx_sreg_envreg10, llvm::Intrinsic::nvvm_read_ptx_sreg_envreg11, llvm::Intrinsic::nvvm_read_ptx_sreg_envreg12, llvm::Intrinsic::nvvm_read_ptx_sreg_envreg13,   llvm::Intrinsic::nvvm_read_ptx_sreg_envreg14, llvm::Intrinsic::nvvm_read_ptx_sreg_envreg15, llvm::Intrinsic::nvvm_read_ptx_sreg_envreg16, llvm::Intrinsic::nvvm_read_ptx_sreg_envreg17,   llvm::Intrinsic::nvvm_read_ptx_sreg_envreg18, llvm::Intrinsic::nvvm_read_ptx_sreg_envreg19, llvm::Intrinsic::nvvm_read_ptx_sreg_envreg2, llvm::Intrinsic::nvvm_read_ptx_sreg_envreg20,   llvm::Intrinsic::nvvm_read_ptx_sreg_envreg21, llvm::Intrinsic::nvvm_read_ptx_sreg_envreg22, llvm::Intrinsic::nvvm_read_ptx_sreg_envreg23, llvm::Intrinsic::nvvm_read_ptx_sreg_envreg24,   llvm::Intrinsic::nvvm_read_ptx_sreg_envreg25, llvm::Intrinsic::nvvm_read_ptx_sreg_envreg26, llvm::Intrinsic::nvvm_read_ptx_sreg_envreg27, llvm::Intrinsic::nvvm_read_ptx_sreg_envreg28,   llvm::Intrinsic::nvvm_read_ptx_sreg_envreg29, llvm::Intrinsic::nvvm_read_ptx_sreg_envreg3, llvm::Intrinsic::nvvm_read_ptx_sreg_envreg30, llvm::Intrinsic::nvvm_read_ptx_sreg_envreg31,   llvm::Intrinsic::nvvm_read_ptx_sreg_envreg4, llvm::Intrinsic::nvvm_read_ptx_sreg_envreg5, llvm::Intrinsic::nvvm_read_ptx_sreg_envreg6, llvm::Intrinsic::nvvm_read_ptx_sreg_envreg7,   llvm::Intrinsic::nvvm_read_ptx_sreg_envreg8, llvm::Intrinsic::nvvm_read_ptx_sreg_envreg9, llvm::Intrinsic::nvvm_read_ptx_sreg_gridid, llvm::Intrinsic::nvvm_read_ptx_sreg_laneid,   llvm::Intrinsic::nvvm_read_ptx_sreg_lanemask_eq, llvm::Intrinsic::nvvm_read_ptx_sreg_lanemask_ge, llvm::Intrinsic::nvvm_read_ptx_sreg_lanemask_gt, llvm::Intrinsic::nvvm_read_ptx_sreg_lanemask_le,   llvm::Intrinsic::nvvm_read_ptx_sreg_lanemask_lt, llvm::Intrinsic::nvvm_read_ptx_sreg_nctaid_w, llvm::Intrinsic::nvvm_read_ptx_sreg_nctaid_x, llvm::Intrinsic::nvvm_read_ptx_sreg_nctaid_y,   llvm::Intrinsic::nvvm_read_ptx_sreg_nctaid_z, llvm::Intrinsic::nvvm_read_ptx_sreg_nsmid, llvm::Intrinsic::nvvm_read_ptx_sreg_ntid_w, llvm::Intrinsic::nvvm_read_ptx_sreg_ntid_x,   llvm::Intrinsic::nvvm_read_ptx_sreg_ntid_y, llvm::Intrinsic::nvvm_read_ptx_sreg_ntid_z, llvm::Intrinsic::nvvm_read_ptx_sreg_nwarpid, llvm::Intrinsic::nvvm_read_ptx_sreg_pm0,   llvm::Intrinsic::nvvm_read_ptx_sreg_pm1, llvm::Intrinsic::nvvm_read_ptx_sreg_pm2, llvm::Intrinsic::nvvm_read_ptx_sreg_pm3, llvm::Intrinsic::nvvm_read_ptx_sreg_smid,   llvm::Intrinsic::nvvm_read_ptx_sreg_tid_w, llvm::Intrinsic::nvvm_read_ptx_sreg_tid_x, llvm::Intrinsic::nvvm_read_ptx_sreg_tid_y, llvm::Intrinsic::nvvm_read_ptx_sreg_tid_z,   llvm::Intrinsic::nvvm_read_ptx_sreg_warpid, llvm::Intrinsic::nvvm_read_ptx_sreg_warpsize, llvm::Intrinsic::nvvm_reflect, llvm::Intrinsic::nvvm_rotate_b32,   llvm::Intrinsic::nvvm_rotate_b64, llvm::Intrinsic::nvvm_rotate_right_b64, llvm::Intrinsic::nvvm_round_d, llvm::Intrinsic::nvvm_round_f,   llvm::Intrinsic::nvvm_round_ftz_f, llvm::Intrinsic::nvvm_rsqrt_approx_d, llvm::Intrinsic::nvvm_rsqrt_approx_f, llvm::Intrinsic::nvvm_rsqrt_approx_ftz_f,   llvm::Intrinsic::nvvm_sad_i, llvm::Intrinsic::nvvm_sad_ui, llvm::Intrinsic::nvvm_saturate_d, llvm::Intrinsic::nvvm_saturate_f,   llvm::Intrinsic::nvvm_saturate_ftz_f, llvm::Intrinsic::nvvm_shfl_bfly_f32, llvm::Intrinsic::nvvm_shfl_bfly_i32, llvm::Intrinsic::nvvm_shfl_down_f32,   llvm::Intrinsic::nvvm_shfl_down_i32, llvm::Intrinsic::nvvm_shfl_idx_f32, llvm::Intrinsic::nvvm_shfl_idx_i32, llvm::Intrinsic::nvvm_shfl_sync_bfly_f32,   llvm::Intrinsic::nvvm_shfl_sync_bfly_i32, llvm::Intrinsic::nvvm_shfl_sync_down_f32, llvm::Intrinsic::nvvm_shfl_sync_down_i32, llvm::Intrinsic::nvvm_shfl_sync_idx_f32,   llvm::Intrinsic::nvvm_shfl_sync_idx_i32, llvm::Intrinsic::nvvm_shfl_sync_up_f32, llvm::Intrinsic::nvvm_shfl_sync_up_i32, llvm::Intrinsic::nvvm_shfl_up_f32,   llvm::Intrinsic::nvvm_shfl_up_i32, llvm::Intrinsic::nvvm_sin_approx_f, llvm::Intrinsic::nvvm_sin_approx_ftz_f, llvm::Intrinsic::nvvm_sqrt_approx_f,   llvm::Intrinsic::nvvm_sqrt_approx_ftz_f, llvm::Intrinsic::nvvm_sqrt_f, llvm::Intrinsic::nvvm_sqrt_rm_d, llvm::Intrinsic::nvvm_sqrt_rm_f,   llvm::Intrinsic::nvvm_sqrt_rm_ftz_f, llvm::Intrinsic::nvvm_sqrt_rn_d, llvm::Intrinsic::nvvm_sqrt_rn_f, llvm::Intrinsic::nvvm_sqrt_rn_ftz_f,   llvm::Intrinsic::nvvm_sqrt_rp_d, llvm::Intrinsic::nvvm_sqrt_rp_f, llvm::Intrinsic::nvvm_sqrt_rp_ftz_f, llvm::Intrinsic::nvvm_sqrt_rz_d,   llvm::Intrinsic::nvvm_sqrt_rz_f, llvm::Intrinsic::nvvm_sqrt_rz_ftz_f, llvm::Intrinsic::nvvm_suld_1d_array_i16_clamp, llvm::Intrinsic::nvvm_suld_1d_array_i16_trap,   llvm::Intrinsic::nvvm_suld_1d_array_i16_zero, llvm::Intrinsic::nvvm_suld_1d_array_i32_clamp, llvm::Intrinsic::nvvm_suld_1d_array_i32_trap, llvm::Intrinsic::nvvm_suld_1d_array_i32_zero,   llvm::Intrinsic::nvvm_suld_1d_array_i64_clamp, llvm::Intrinsic::nvvm_suld_1d_array_i64_trap, llvm::Intrinsic::nvvm_suld_1d_array_i64_zero, llvm::Intrinsic::nvvm_suld_1d_array_i8_clamp,   llvm::Intrinsic::nvvm_suld_1d_array_i8_trap, llvm::Intrinsic::nvvm_suld_1d_array_i8_zero, llvm::Intrinsic::nvvm_suld_1d_array_v2i16_clamp, llvm::Intrinsic::nvvm_suld_1d_array_v2i16_trap,   llvm::Intrinsic::nvvm_suld_1d_array_v2i16_zero, llvm::Intrinsic::nvvm_suld_1d_array_v2i32_clamp, llvm::Intrinsic::nvvm_suld_1d_array_v2i32_trap, llvm::Intrinsic::nvvm_suld_1d_array_v2i32_zero,   llvm::Intrinsic::nvvm_suld_1d_array_v2i64_clamp, llvm::Intrinsic::nvvm_suld_1d_array_v2i64_trap, llvm::Intrinsic::nvvm_suld_1d_array_v2i64_zero, llvm::Intrinsic::nvvm_suld_1d_array_v2i8_clamp,   llvm::Intrinsic::nvvm_suld_1d_array_v2i8_trap, llvm::Intrinsic::nvvm_suld_1d_array_v2i8_zero, llvm::Intrinsic::nvvm_suld_1d_array_v4i16_clamp, llvm::Intrinsic::nvvm_suld_1d_array_v4i16_trap,   llvm::Intrinsic::nvvm_suld_1d_array_v4i16_zero, llvm::Intrinsic::nvvm_suld_1d_array_v4i32_clamp, llvm::Intrinsic::nvvm_suld_1d_array_v4i32_trap, llvm::Intrinsic::nvvm_suld_1d_array_v4i32_zero,   llvm::Intrinsic::nvvm_suld_1d_array_v4i8_clamp, llvm::Intrinsic::nvvm_suld_1d_array_v4i8_trap, llvm::Intrinsic::nvvm_suld_1d_array_v4i8_zero, llvm::Intrinsic::nvvm_suld_1d_i16_clamp,   llvm::Intrinsic::nvvm_suld_1d_i16_trap, llvm::Intrinsic::nvvm_suld_1d_i16_zero, llvm::Intrinsic::nvvm_suld_1d_i32_clamp, llvm::Intrinsic::nvvm_suld_1d_i32_trap,   llvm::Intrinsic::nvvm_suld_1d_i32_zero, llvm::Intrinsic::nvvm_suld_1d_i64_clamp, llvm::Intrinsic::nvvm_suld_1d_i64_trap, llvm::Intrinsic::nvvm_suld_1d_i64_zero,   llvm::Intrinsic::nvvm_suld_1d_i8_clamp, llvm::Intrinsic::nvvm_suld_1d_i8_trap, llvm::Intrinsic::nvvm_suld_1d_i8_zero, llvm::Intrinsic::nvvm_suld_1d_v2i16_clamp,   llvm::Intrinsic::nvvm_suld_1d_v2i16_trap, llvm::Intrinsic::nvvm_suld_1d_v2i16_zero, llvm::Intrinsic::nvvm_suld_1d_v2i32_clamp, llvm::Intrinsic::nvvm_suld_1d_v2i32_trap,   llvm::Intrinsic::nvvm_suld_1d_v2i32_zero, llvm::Intrinsic::nvvm_suld_1d_v2i64_clamp, llvm::Intrinsic::nvvm_suld_1d_v2i64_trap, llvm::Intrinsic::nvvm_suld_1d_v2i64_zero,   llvm::Intrinsic::nvvm_suld_1d_v2i8_clamp, llvm::Intrinsic::nvvm_suld_1d_v2i8_trap, llvm::Intrinsic::nvvm_suld_1d_v2i8_zero, llvm::Intrinsic::nvvm_suld_1d_v4i16_clamp,   llvm::Intrinsic::nvvm_suld_1d_v4i16_trap, llvm::Intrinsic::nvvm_suld_1d_v4i16_zero, llvm::Intrinsic::nvvm_suld_1d_v4i32_clamp, llvm::Intrinsic::nvvm_suld_1d_v4i32_trap,   llvm::Intrinsic::nvvm_suld_1d_v4i32_zero, llvm::Intrinsic::nvvm_suld_1d_v4i8_clamp, llvm::Intrinsic::nvvm_suld_1d_v4i8_trap, llvm::Intrinsic::nvvm_suld_1d_v4i8_zero,   llvm::Intrinsic::nvvm_suld_2d_array_i16_clamp, llvm::Intrinsic::nvvm_suld_2d_array_i16_trap, llvm::Intrinsic::nvvm_suld_2d_array_i16_zero, llvm::Intrinsic::nvvm_suld_2d_array_i32_clamp,   llvm::Intrinsic::nvvm_suld_2d_array_i32_trap, llvm::Intrinsic::nvvm_suld_2d_array_i32_zero, llvm::Intrinsic::nvvm_suld_2d_array_i64_clamp, llvm::Intrinsic::nvvm_suld_2d_array_i64_trap,   llvm::Intrinsic::nvvm_suld_2d_array_i64_zero, llvm::Intrinsic::nvvm_suld_2d_array_i8_clamp, llvm::Intrinsic::nvvm_suld_2d_array_i8_trap, llvm::Intrinsic::nvvm_suld_2d_array_i8_zero,   llvm::Intrinsic::nvvm_suld_2d_array_v2i16_clamp, llvm::Intrinsic::nvvm_suld_2d_array_v2i16_trap, llvm::Intrinsic::nvvm_suld_2d_array_v2i16_zero, llvm::Intrinsic::nvvm_suld_2d_array_v2i32_clamp,   llvm::Intrinsic::nvvm_suld_2d_array_v2i32_trap, llvm::Intrinsic::nvvm_suld_2d_array_v2i32_zero, llvm::Intrinsic::nvvm_suld_2d_array_v2i64_clamp, llvm::Intrinsic::nvvm_suld_2d_array_v2i64_trap,   llvm::Intrinsic::nvvm_suld_2d_array_v2i64_zero, llvm::Intrinsic::nvvm_suld_2d_array_v2i8_clamp, llvm::Intrinsic::nvvm_suld_2d_array_v2i8_trap, llvm::Intrinsic::nvvm_suld_2d_array_v2i8_zero,   llvm::Intrinsic::nvvm_suld_2d_array_v4i16_clamp, llvm::Intrinsic::nvvm_suld_2d_array_v4i16_trap, llvm::Intrinsic::nvvm_suld_2d_array_v4i16_zero, llvm::Intrinsic::nvvm_suld_2d_array_v4i32_clamp,   llvm::Intrinsic::nvvm_suld_2d_array_v4i32_trap, llvm::Intrinsic::nvvm_suld_2d_array_v4i32_zero, llvm::Intrinsic::nvvm_suld_2d_array_v4i8_clamp, llvm::Intrinsic::nvvm_suld_2d_array_v4i8_trap,   llvm::Intrinsic::nvvm_suld_2d_array_v4i8_zero, llvm::Intrinsic::nvvm_suld_2d_i16_clamp, llvm::Intrinsic::nvvm_suld_2d_i16_trap, llvm::Intrinsic::nvvm_suld_2d_i16_zero,   llvm::Intrinsic::nvvm_suld_2d_i32_clamp, llvm::Intrinsic::nvvm_suld_2d_i32_trap, llvm::Intrinsic::nvvm_suld_2d_i32_zero, llvm::Intrinsic::nvvm_suld_2d_i64_clamp,   llvm::Intrinsic::nvvm_suld_2d_i64_trap, llvm::Intrinsic::nvvm_suld_2d_i64_zero, llvm::Intrinsic::nvvm_suld_2d_i8_clamp, llvm::Intrinsic::nvvm_suld_2d_i8_trap,   llvm::Intrinsic::nvvm_suld_2d_i8_zero, llvm::Intrinsic::nvvm_suld_2d_v2i16_clamp, llvm::Intrinsic::nvvm_suld_2d_v2i16_trap, llvm::Intrinsic::nvvm_suld_2d_v2i16_zero,   llvm::Intrinsic::nvvm_suld_2d_v2i32_clamp, llvm::Intrinsic::nvvm_suld_2d_v2i32_trap, llvm::Intrinsic::nvvm_suld_2d_v2i32_zero, llvm::Intrinsic::nvvm_suld_2d_v2i64_clamp,   llvm::Intrinsic::nvvm_suld_2d_v2i64_trap, llvm::Intrinsic::nvvm_suld_2d_v2i64_zero, llvm::Intrinsic::nvvm_suld_2d_v2i8_clamp, llvm::Intrinsic::nvvm_suld_2d_v2i8_trap,   llvm::Intrinsic::nvvm_suld_2d_v2i8_zero, llvm::Intrinsic::nvvm_suld_2d_v4i16_clamp, llvm::Intrinsic::nvvm_suld_2d_v4i16_trap, llvm::Intrinsic::nvvm_suld_2d_v4i16_zero,   llvm::Intrinsic::nvvm_suld_2d_v4i32_clamp, llvm::Intrinsic::nvvm_suld_2d_v4i32_trap, llvm::Intrinsic::nvvm_suld_2d_v4i32_zero, llvm::Intrinsic::nvvm_suld_2d_v4i8_clamp,   llvm::Intrinsic::nvvm_suld_2d_v4i8_trap, llvm::Intrinsic::nvvm_suld_2d_v4i8_zero, llvm::Intrinsic::nvvm_suld_3d_i16_clamp, llvm::Intrinsic::nvvm_suld_3d_i16_trap,   llvm::Intrinsic::nvvm_suld_3d_i16_zero, llvm::Intrinsic::nvvm_suld_3d_i32_clamp, llvm::Intrinsic::nvvm_suld_3d_i32_trap, llvm::Intrinsic::nvvm_suld_3d_i32_zero,   llvm::Intrinsic::nvvm_suld_3d_i64_clamp, llvm::Intrinsic::nvvm_suld_3d_i64_trap, llvm::Intrinsic::nvvm_suld_3d_i64_zero, llvm::Intrinsic::nvvm_suld_3d_i8_clamp,   llvm::Intrinsic::nvvm_suld_3d_i8_trap, llvm::Intrinsic::nvvm_suld_3d_i8_zero, llvm::Intrinsic::nvvm_suld_3d_v2i16_clamp, llvm::Intrinsic::nvvm_suld_3d_v2i16_trap,   llvm::Intrinsic::nvvm_suld_3d_v2i16_zero, llvm::Intrinsic::nvvm_suld_3d_v2i32_clamp, llvm::Intrinsic::nvvm_suld_3d_v2i32_trap, llvm::Intrinsic::nvvm_suld_3d_v2i32_zero,   llvm::Intrinsic::nvvm_suld_3d_v2i64_clamp, llvm::Intrinsic::nvvm_suld_3d_v2i64_trap, llvm::Intrinsic::nvvm_suld_3d_v2i64_zero, llvm::Intrinsic::nvvm_suld_3d_v2i8_clamp,   llvm::Intrinsic::nvvm_suld_3d_v2i8_trap, llvm::Intrinsic::nvvm_suld_3d_v2i8_zero, llvm::Intrinsic::nvvm_suld_3d_v4i16_clamp, llvm::Intrinsic::nvvm_suld_3d_v4i16_trap,   llvm::Intrinsic::nvvm_suld_3d_v4i16_zero, llvm::Intrinsic::nvvm_suld_3d_v4i32_clamp, llvm::Intrinsic::nvvm_suld_3d_v4i32_trap, llvm::Intrinsic::nvvm_suld_3d_v4i32_zero,   llvm::Intrinsic::nvvm_suld_3d_v4i8_clamp, llvm::Intrinsic::nvvm_suld_3d_v4i8_trap, llvm::Intrinsic::nvvm_suld_3d_v4i8_zero, llvm::Intrinsic::nvvm_suq_array_size,   llvm::Intrinsic::nvvm_suq_channel_data_type, llvm::Intrinsic::nvvm_suq_channel_order, llvm::Intrinsic::nvvm_suq_depth, llvm::Intrinsic::nvvm_suq_height,   llvm::Intrinsic::nvvm_suq_width, llvm::Intrinsic::nvvm_sust_b_1d_array_i16_clamp, llvm::Intrinsic::nvvm_sust_b_1d_array_i16_trap, llvm::Intrinsic::nvvm_sust_b_1d_array_i16_zero,   llvm::Intrinsic::nvvm_sust_b_1d_array_i32_clamp, llvm::Intrinsic::nvvm_sust_b_1d_array_i32_trap, llvm::Intrinsic::nvvm_sust_b_1d_array_i32_zero, llvm::Intrinsic::nvvm_sust_b_1d_array_i64_clamp,   llvm::Intrinsic::nvvm_sust_b_1d_array_i64_trap, llvm::Intrinsic::nvvm_sust_b_1d_array_i64_zero, llvm::Intrinsic::nvvm_sust_b_1d_array_i8_clamp, llvm::Intrinsic::nvvm_sust_b_1d_array_i8_trap,   llvm::Intrinsic::nvvm_sust_b_1d_array_i8_zero, llvm::Intrinsic::nvvm_sust_b_1d_array_v2i16_clamp, llvm::Intrinsic::nvvm_sust_b_1d_array_v2i16_trap, llvm::Intrinsic::nvvm_sust_b_1d_array_v2i16_zero,   llvm::Intrinsic::nvvm_sust_b_1d_array_v2i32_clamp, llvm::Intrinsic::nvvm_sust_b_1d_array_v2i32_trap, llvm::Intrinsic::nvvm_sust_b_1d_array_v2i32_zero, llvm::Intrinsic::nvvm_sust_b_1d_array_v2i64_clamp,   llvm::Intrinsic::nvvm_sust_b_1d_array_v2i64_trap, llvm::Intrinsic::nvvm_sust_b_1d_array_v2i64_zero, llvm::Intrinsic::nvvm_sust_b_1d_array_v2i8_clamp, llvm::Intrinsic::nvvm_sust_b_1d_array_v2i8_trap,   llvm::Intrinsic::nvvm_sust_b_1d_array_v2i8_zero, llvm::Intrinsic::nvvm_sust_b_1d_array_v4i16_clamp, llvm::Intrinsic::nvvm_sust_b_1d_array_v4i16_trap, llvm::Intrinsic::nvvm_sust_b_1d_array_v4i16_zero,   llvm::Intrinsic::nvvm_sust_b_1d_array_v4i32_clamp, llvm::Intrinsic::nvvm_sust_b_1d_array_v4i32_trap, llvm::Intrinsic::nvvm_sust_b_1d_array_v4i32_zero, llvm::Intrinsic::nvvm_sust_b_1d_array_v4i8_clamp,   llvm::Intrinsic::nvvm_sust_b_1d_array_v4i8_trap, llvm::Intrinsic::nvvm_sust_b_1d_array_v4i8_zero, llvm::Intrinsic::nvvm_sust_b_1d_i16_clamp, llvm::Intrinsic::nvvm_sust_b_1d_i16_trap,   llvm::Intrinsic::nvvm_sust_b_1d_i16_zero, llvm::Intrinsic::nvvm_sust_b_1d_i32_clamp, llvm::Intrinsic::nvvm_sust_b_1d_i32_trap, llvm::Intrinsic::nvvm_sust_b_1d_i32_zero,   llvm::Intrinsic::nvvm_sust_b_1d_i64_clamp, llvm::Intrinsic::nvvm_sust_b_1d_i64_trap, llvm::Intrinsic::nvvm_sust_b_1d_i64_zero, llvm::Intrinsic::nvvm_sust_b_1d_i8_clamp,   llvm::Intrinsic::nvvm_sust_b_1d_i8_trap, llvm::Intrinsic::nvvm_sust_b_1d_i8_zero, llvm::Intrinsic::nvvm_sust_b_1d_v2i16_clamp, llvm::Intrinsic::nvvm_sust_b_1d_v2i16_trap,   llvm::Intrinsic::nvvm_sust_b_1d_v2i16_zero, llvm::Intrinsic::nvvm_sust_b_1d_v2i32_clamp, llvm::Intrinsic::nvvm_sust_b_1d_v2i32_trap, llvm::Intrinsic::nvvm_sust_b_1d_v2i32_zero,   llvm::Intrinsic::nvvm_sust_b_1d_v2i64_clamp, llvm::Intrinsic::nvvm_sust_b_1d_v2i64_trap, llvm::Intrinsic::nvvm_sust_b_1d_v2i64_zero, llvm::Intrinsic::nvvm_sust_b_1d_v2i8_clamp,   llvm::Intrinsic::nvvm_sust_b_1d_v2i8_trap, llvm::Intrinsic::nvvm_sust_b_1d_v2i8_zero, llvm::Intrinsic::nvvm_sust_b_1d_v4i16_clamp, llvm::Intrinsic::nvvm_sust_b_1d_v4i16_trap,   llvm::Intrinsic::nvvm_sust_b_1d_v4i16_zero, llvm::Intrinsic::nvvm_sust_b_1d_v4i32_clamp, llvm::Intrinsic::nvvm_sust_b_1d_v4i32_trap, llvm::Intrinsic::nvvm_sust_b_1d_v4i32_zero,   llvm::Intrinsic::nvvm_sust_b_1d_v4i8_clamp, llvm::Intrinsic::nvvm_sust_b_1d_v4i8_trap, llvm::Intrinsic::nvvm_sust_b_1d_v4i8_zero, llvm::Intrinsic::nvvm_sust_b_2d_array_i16_clamp,   llvm::Intrinsic::nvvm_sust_b_2d_array_i16_trap, llvm::Intrinsic::nvvm_sust_b_2d_array_i16_zero, llvm::Intrinsic::nvvm_sust_b_2d_array_i32_clamp, llvm::Intrinsic::nvvm_sust_b_2d_array_i32_trap,   llvm::Intrinsic::nvvm_sust_b_2d_array_i32_zero, llvm::Intrinsic::nvvm_sust_b_2d_array_i64_clamp, llvm::Intrinsic::nvvm_sust_b_2d_array_i64_trap, llvm::Intrinsic::nvvm_sust_b_2d_array_i64_zero,   llvm::Intrinsic::nvvm_sust_b_2d_array_i8_clamp, llvm::Intrinsic::nvvm_sust_b_2d_array_i8_trap, llvm::Intrinsic::nvvm_sust_b_2d_array_i8_zero, llvm::Intrinsic::nvvm_sust_b_2d_array_v2i16_clamp,   llvm::Intrinsic::nvvm_sust_b_2d_array_v2i16_trap, llvm::Intrinsic::nvvm_sust_b_2d_array_v2i16_zero, llvm::Intrinsic::nvvm_sust_b_2d_array_v2i32_clamp, llvm::Intrinsic::nvvm_sust_b_2d_array_v2i32_trap,   llvm::Intrinsic::nvvm_sust_b_2d_array_v2i32_zero, llvm::Intrinsic::nvvm_sust_b_2d_array_v2i64_clamp, llvm::Intrinsic::nvvm_sust_b_2d_array_v2i64_trap, llvm::Intrinsic::nvvm_sust_b_2d_array_v2i64_zero,   llvm::Intrinsic::nvvm_sust_b_2d_array_v2i8_clamp, llvm::Intrinsic::nvvm_sust_b_2d_array_v2i8_trap, llvm::Intrinsic::nvvm_sust_b_2d_array_v2i8_zero, llvm::Intrinsic::nvvm_sust_b_2d_array_v4i16_clamp,   llvm::Intrinsic::nvvm_sust_b_2d_array_v4i16_trap, llvm::Intrinsic::nvvm_sust_b_2d_array_v4i16_zero, llvm::Intrinsic::nvvm_sust_b_2d_array_v4i32_clamp, llvm::Intrinsic::nvvm_sust_b_2d_array_v4i32_trap,   llvm::Intrinsic::nvvm_sust_b_2d_array_v4i32_zero, llvm::Intrinsic::nvvm_sust_b_2d_array_v4i8_clamp, llvm::Intrinsic::nvvm_sust_b_2d_array_v4i8_trap, llvm::Intrinsic::nvvm_sust_b_2d_array_v4i8_zero,   llvm::Intrinsic::nvvm_sust_b_2d_i16_clamp, llvm::Intrinsic::nvvm_sust_b_2d_i16_trap, llvm::Intrinsic::nvvm_sust_b_2d_i16_zero, llvm::Intrinsic::nvvm_sust_b_2d_i32_clamp,   llvm::Intrinsic::nvvm_sust_b_2d_i32_trap, llvm::Intrinsic::nvvm_sust_b_2d_i32_zero, llvm::Intrinsic::nvvm_sust_b_2d_i64_clamp, llvm::Intrinsic::nvvm_sust_b_2d_i64_trap,   llvm::Intrinsic::nvvm_sust_b_2d_i64_zero, llvm::Intrinsic::nvvm_sust_b_2d_i8_clamp, llvm::Intrinsic::nvvm_sust_b_2d_i8_trap, llvm::Intrinsic::nvvm_sust_b_2d_i8_zero,   llvm::Intrinsic::nvvm_sust_b_2d_v2i16_clamp, llvm::Intrinsic::nvvm_sust_b_2d_v2i16_trap, llvm::Intrinsic::nvvm_sust_b_2d_v2i16_zero, llvm::Intrinsic::nvvm_sust_b_2d_v2i32_clamp,   llvm::Intrinsic::nvvm_sust_b_2d_v2i32_trap, llvm::Intrinsic::nvvm_sust_b_2d_v2i32_zero, llvm::Intrinsic::nvvm_sust_b_2d_v2i64_clamp, llvm::Intrinsic::nvvm_sust_b_2d_v2i64_trap,   llvm::Intrinsic::nvvm_sust_b_2d_v2i64_zero, llvm::Intrinsic::nvvm_sust_b_2d_v2i8_clamp, llvm::Intrinsic::nvvm_sust_b_2d_v2i8_trap, llvm::Intrinsic::nvvm_sust_b_2d_v2i8_zero,   llvm::Intrinsic::nvvm_sust_b_2d_v4i16_clamp, llvm::Intrinsic::nvvm_sust_b_2d_v4i16_trap, llvm::Intrinsic::nvvm_sust_b_2d_v4i16_zero, llvm::Intrinsic::nvvm_sust_b_2d_v4i32_clamp,   llvm::Intrinsic::nvvm_sust_b_2d_v4i32_trap, llvm::Intrinsic::nvvm_sust_b_2d_v4i32_zero, llvm::Intrinsic::nvvm_sust_b_2d_v4i8_clamp, llvm::Intrinsic::nvvm_sust_b_2d_v4i8_trap,   llvm::Intrinsic::nvvm_sust_b_2d_v4i8_zero, llvm::Intrinsic::nvvm_sust_b_3d_i16_clamp, llvm::Intrinsic::nvvm_sust_b_3d_i16_trap, llvm::Intrinsic::nvvm_sust_b_3d_i16_zero,   llvm::Intrinsic::nvvm_sust_b_3d_i32_clamp, llvm::Intrinsic::nvvm_sust_b_3d_i32_trap, llvm::Intrinsic::nvvm_sust_b_3d_i32_zero, llvm::Intrinsic::nvvm_sust_b_3d_i64_clamp,   llvm::Intrinsic::nvvm_sust_b_3d_i64_trap, llvm::Intrinsic::nvvm_sust_b_3d_i64_zero, llvm::Intrinsic::nvvm_sust_b_3d_i8_clamp, llvm::Intrinsic::nvvm_sust_b_3d_i8_trap,   llvm::Intrinsic::nvvm_sust_b_3d_i8_zero, llvm::Intrinsic::nvvm_sust_b_3d_v2i16_clamp, llvm::Intrinsic::nvvm_sust_b_3d_v2i16_trap, llvm::Intrinsic::nvvm_sust_b_3d_v2i16_zero,   llvm::Intrinsic::nvvm_sust_b_3d_v2i32_clamp, llvm::Intrinsic::nvvm_sust_b_3d_v2i32_trap, llvm::Intrinsic::nvvm_sust_b_3d_v2i32_zero, llvm::Intrinsic::nvvm_sust_b_3d_v2i64_clamp,   llvm::Intrinsic::nvvm_sust_b_3d_v2i64_trap, llvm::Intrinsic::nvvm_sust_b_3d_v2i64_zero, llvm::Intrinsic::nvvm_sust_b_3d_v2i8_clamp, llvm::Intrinsic::nvvm_sust_b_3d_v2i8_trap,   llvm::Intrinsic::nvvm_sust_b_3d_v2i8_zero, llvm::Intrinsic::nvvm_sust_b_3d_v4i16_clamp, llvm::Intrinsic::nvvm_sust_b_3d_v4i16_trap, llvm::Intrinsic::nvvm_sust_b_3d_v4i16_zero,   llvm::Intrinsic::nvvm_sust_b_3d_v4i32_clamp, llvm::Intrinsic::nvvm_sust_b_3d_v4i32_trap, llvm::Intrinsic::nvvm_sust_b_3d_v4i32_zero, llvm::Intrinsic::nvvm_sust_b_3d_v4i8_clamp,   llvm::Intrinsic::nvvm_sust_b_3d_v4i8_trap, llvm::Intrinsic::nvvm_sust_b_3d_v4i8_zero, llvm::Intrinsic::nvvm_sust_p_1d_array_i16_trap, llvm::Intrinsic::nvvm_sust_p_1d_array_i32_trap,   llvm::Intrinsic::nvvm_sust_p_1d_array_i8_trap, llvm::Intrinsic::nvvm_sust_p_1d_array_v2i16_trap, llvm::Intrinsic::nvvm_sust_p_1d_array_v2i32_trap, llvm::Intrinsic::nvvm_sust_p_1d_array_v2i8_trap,   llvm::Intrinsic::nvvm_sust_p_1d_array_v4i16_trap, llvm::Intrinsic::nvvm_sust_p_1d_array_v4i32_trap, llvm::Intrinsic::nvvm_sust_p_1d_array_v4i8_trap, llvm::Intrinsic::nvvm_sust_p_1d_i16_trap,   llvm::Intrinsic::nvvm_sust_p_1d_i32_trap, llvm::Intrinsic::nvvm_sust_p_1d_i8_trap, llvm::Intrinsic::nvvm_sust_p_1d_v2i16_trap, llvm::Intrinsic::nvvm_sust_p_1d_v2i32_trap,   llvm::Intrinsic::nvvm_sust_p_1d_v2i8_trap, llvm::Intrinsic::nvvm_sust_p_1d_v4i16_trap, llvm::Intrinsic::nvvm_sust_p_1d_v4i32_trap, llvm::Intrinsic::nvvm_sust_p_1d_v4i8_trap,   llvm::Intrinsic::nvvm_sust_p_2d_array_i16_trap, llvm::Intrinsic::nvvm_sust_p_2d_array_i32_trap, llvm::Intrinsic::nvvm_sust_p_2d_array_i8_trap, llvm::Intrinsic::nvvm_sust_p_2d_array_v2i16_trap,   llvm::Intrinsic::nvvm_sust_p_2d_array_v2i32_trap, llvm::Intrinsic::nvvm_sust_p_2d_array_v2i8_trap, llvm::Intrinsic::nvvm_sust_p_2d_array_v4i16_trap, llvm::Intrinsic::nvvm_sust_p_2d_array_v4i32_trap,   llvm::Intrinsic::nvvm_sust_p_2d_array_v4i8_trap, llvm::Intrinsic::nvvm_sust_p_2d_i16_trap, llvm::Intrinsic::nvvm_sust_p_2d_i32_trap, llvm::Intrinsic::nvvm_sust_p_2d_i8_trap,   llvm::Intrinsic::nvvm_sust_p_2d_v2i16_trap, llvm::Intrinsic::nvvm_sust_p_2d_v2i32_trap, llvm::Intrinsic::nvvm_sust_p_2d_v2i8_trap, llvm::Intrinsic::nvvm_sust_p_2d_v4i16_trap,   llvm::Intrinsic::nvvm_sust_p_2d_v4i32_trap, llvm::Intrinsic::nvvm_sust_p_2d_v4i8_trap, llvm::Intrinsic::nvvm_sust_p_3d_i16_trap, llvm::Intrinsic::nvvm_sust_p_3d_i32_trap,   llvm::Intrinsic::nvvm_sust_p_3d_i8_trap, llvm::Intrinsic::nvvm_sust_p_3d_v2i16_trap, llvm::Intrinsic::nvvm_sust_p_3d_v2i32_trap, llvm::Intrinsic::nvvm_sust_p_3d_v2i8_trap,   llvm::Intrinsic::nvvm_sust_p_3d_v4i16_trap, llvm::Intrinsic::nvvm_sust_p_3d_v4i32_trap, llvm::Intrinsic::nvvm_sust_p_3d_v4i8_trap, llvm::Intrinsic::nvvm_swap_lo_hi_b64,   llvm::Intrinsic::nvvm_tex_1d_array_grad_v4f32_f32, llvm::Intrinsic::nvvm_tex_1d_array_grad_v4s32_f32, llvm::Intrinsic::nvvm_tex_1d_array_grad_v4u32_f32, llvm::Intrinsic::nvvm_tex_1d_array_level_v4f32_f32,   llvm::Intrinsic::nvvm_tex_1d_array_level_v4s32_f32, llvm::Intrinsic::nvvm_tex_1d_array_level_v4u32_f32, llvm::Intrinsic::nvvm_tex_1d_array_v4f32_f32, llvm::Intrinsic::nvvm_tex_1d_array_v4f32_s32,   llvm::Intrinsic::nvvm_tex_1d_array_v4s32_f32, llvm::Intrinsic::nvvm_tex_1d_array_v4s32_s32, llvm::Intrinsic::nvvm_tex_1d_array_v4u32_f32, llvm::Intrinsic::nvvm_tex_1d_array_v4u32_s32,   llvm::Intrinsic::nvvm_tex_1d_grad_v4f32_f32, llvm::Intrinsic::nvvm_tex_1d_grad_v4s32_f32, llvm::Intrinsic::nvvm_tex_1d_grad_v4u32_f32, llvm::Intrinsic::nvvm_tex_1d_level_v4f32_f32,   llvm::Intrinsic::nvvm_tex_1d_level_v4s32_f32, llvm::Intrinsic::nvvm_tex_1d_level_v4u32_f32, llvm::Intrinsic::nvvm_tex_1d_v4f32_f32, llvm::Intrinsic::nvvm_tex_1d_v4f32_s32,   llvm::Intrinsic::nvvm_tex_1d_v4s32_f32, llvm::Intrinsic::nvvm_tex_1d_v4s32_s32, llvm::Intrinsic::nvvm_tex_1d_v4u32_f32, llvm::Intrinsic::nvvm_tex_1d_v4u32_s32,   llvm::Intrinsic::nvvm_tex_2d_array_grad_v4f32_f32, llvm::Intrinsic::nvvm_tex_2d_array_grad_v4s32_f32, llvm::Intrinsic::nvvm_tex_2d_array_grad_v4u32_f32, llvm::Intrinsic::nvvm_tex_2d_array_level_v4f32_f32,   llvm::Intrinsic::nvvm_tex_2d_array_level_v4s32_f32, llvm::Intrinsic::nvvm_tex_2d_array_level_v4u32_f32, llvm::Intrinsic::nvvm_tex_2d_array_v4f32_f32, llvm::Intrinsic::nvvm_tex_2d_array_v4f32_s32,   llvm::Intrinsic::nvvm_tex_2d_array_v4s32_f32, llvm::Intrinsic::nvvm_tex_2d_array_v4s32_s32, llvm::Intrinsic::nvvm_tex_2d_array_v4u32_f32, llvm::Intrinsic::nvvm_tex_2d_array_v4u32_s32,   llvm::Intrinsic::nvvm_tex_2d_grad_v4f32_f32, llvm::Intrinsic::nvvm_tex_2d_grad_v4s32_f32, llvm::Intrinsic::nvvm_tex_2d_grad_v4u32_f32, llvm::Intrinsic::nvvm_tex_2d_level_v4f32_f32,   llvm::Intrinsic::nvvm_tex_2d_level_v4s32_f32, llvm::Intrinsic::nvvm_tex_2d_level_v4u32_f32, llvm::Intrinsic::nvvm_tex_2d_v4f32_f32, llvm::Intrinsic::nvvm_tex_2d_v4f32_s32,   llvm::Intrinsic::nvvm_tex_2d_v4s32_f32, llvm::Intrinsic::nvvm_tex_2d_v4s32_s32, llvm::Intrinsic::nvvm_tex_2d_v4u32_f32, llvm::Intrinsic::nvvm_tex_2d_v4u32_s32,   llvm::Intrinsic::nvvm_tex_3d_grad_v4f32_f32, llvm::Intrinsic::nvvm_tex_3d_grad_v4s32_f32, llvm::Intrinsic::nvvm_tex_3d_grad_v4u32_f32, llvm::Intrinsic::nvvm_tex_3d_level_v4f32_f32,   llvm::Intrinsic::nvvm_tex_3d_level_v4s32_f32, llvm::Intrinsic::nvvm_tex_3d_level_v4u32_f32, llvm::Intrinsic::nvvm_tex_3d_v4f32_f32, llvm::Intrinsic::nvvm_tex_3d_v4f32_s32,   llvm::Intrinsic::nvvm_tex_3d_v4s32_f32, llvm::Intrinsic::nvvm_tex_3d_v4s32_s32, llvm::Intrinsic::nvvm_tex_3d_v4u32_f32, llvm::Intrinsic::nvvm_tex_3d_v4u32_s32,   llvm::Intrinsic::nvvm_tex_cube_array_level_v4f32_f32, llvm::Intrinsic::nvvm_tex_cube_array_level_v4s32_f32, llvm::Intrinsic::nvvm_tex_cube_array_level_v4u32_f32, llvm::Intrinsic::nvvm_tex_cube_array_v4f32_f32,   llvm::Intrinsic::nvvm_tex_cube_array_v4s32_f32, llvm::Intrinsic::nvvm_tex_cube_array_v4u32_f32, llvm::Intrinsic::nvvm_tex_cube_level_v4f32_f32, llvm::Intrinsic::nvvm_tex_cube_level_v4s32_f32,   llvm::Intrinsic::nvvm_tex_cube_level_v4u32_f32, llvm::Intrinsic::nvvm_tex_cube_v4f32_f32, llvm::Intrinsic::nvvm_tex_cube_v4s32_f32, llvm::Intrinsic::nvvm_tex_cube_v4u32_f32,   llvm::Intrinsic::nvvm_tex_unified_1d_array_grad_v4f32_f32, llvm::Intrinsic::nvvm_tex_unified_1d_array_grad_v4s32_f32, llvm::Intrinsic::nvvm_tex_unified_1d_array_grad_v4u32_f32, llvm::Intrinsic::nvvm_tex_unified_1d_array_level_v4f32_f32,   llvm::Intrinsic::nvvm_tex_unified_1d_array_level_v4s32_f32, llvm::Intrinsic::nvvm_tex_unified_1d_array_level_v4u32_f32, llvm::Intrinsic::nvvm_tex_unified_1d_array_v4f32_f32, llvm::Intrinsic::nvvm_tex_unified_1d_array_v4f32_s32,   llvm::Intrinsic::nvvm_tex_unified_1d_array_v4s32_f32, llvm::Intrinsic::nvvm_tex_unified_1d_array_v4s32_s32, llvm::Intrinsic::nvvm_tex_unified_1d_array_v4u32_f32, llvm::Intrinsic::nvvm_tex_unified_1d_array_v4u32_s32,   llvm::Intrinsic::nvvm_tex_unified_1d_grad_v4f32_f32, llvm::Intrinsic::nvvm_tex_unified_1d_grad_v4s32_f32, llvm::Intrinsic::nvvm_tex_unified_1d_grad_v4u32_f32, llvm::Intrinsic::nvvm_tex_unified_1d_level_v4f32_f32,   llvm::Intrinsic::nvvm_tex_unified_1d_level_v4s32_f32, llvm::Intrinsic::nvvm_tex_unified_1d_level_v4u32_f32, llvm::Intrinsic::nvvm_tex_unified_1d_v4f32_f32, llvm::Intrinsic::nvvm_tex_unified_1d_v4f32_s32,   llvm::Intrinsic::nvvm_tex_unified_1d_v4s32_f32, llvm::Intrinsic::nvvm_tex_unified_1d_v4s32_s32, llvm::Intrinsic::nvvm_tex_unified_1d_v4u32_f32, llvm::Intrinsic::nvvm_tex_unified_1d_v4u32_s32,   llvm::Intrinsic::nvvm_tex_unified_2d_array_grad_v4f32_f32, llvm::Intrinsic::nvvm_tex_unified_2d_array_grad_v4s32_f32, llvm::Intrinsic::nvvm_tex_unified_2d_array_grad_v4u32_f32, llvm::Intrinsic::nvvm_tex_unified_2d_array_level_v4f32_f32,   llvm::Intrinsic::nvvm_tex_unified_2d_array_level_v4s32_f32, llvm::Intrinsic::nvvm_tex_unified_2d_array_level_v4u32_f32, llvm::Intrinsic::nvvm_tex_unified_2d_array_v4f32_f32, llvm::Intrinsic::nvvm_tex_unified_2d_array_v4f32_s32,   llvm::Intrinsic::nvvm_tex_unified_2d_array_v4s32_f32, llvm::Intrinsic::nvvm_tex_unified_2d_array_v4s32_s32, llvm::Intrinsic::nvvm_tex_unified_2d_array_v4u32_f32, llvm::Intrinsic::nvvm_tex_unified_2d_array_v4u32_s32,   llvm::Intrinsic::nvvm_tex_unified_2d_grad_v4f32_f32, llvm::Intrinsic::nvvm_tex_unified_2d_grad_v4s32_f32, llvm::Intrinsic::nvvm_tex_unified_2d_grad_v4u32_f32, llvm::Intrinsic::nvvm_tex_unified_2d_level_v4f32_f32,   llvm::Intrinsic::nvvm_tex_unified_2d_level_v4s32_f32, llvm::Intrinsic::nvvm_tex_unified_2d_level_v4u32_f32, llvm::Intrinsic::nvvm_tex_unified_2d_v4f32_f32, llvm::Intrinsic::nvvm_tex_unified_2d_v4f32_s32,   llvm::Intrinsic::nvvm_tex_unified_2d_v4s32_f32, llvm::Intrinsic::nvvm_tex_unified_2d_v4s32_s32, llvm::Intrinsic::nvvm_tex_unified_2d_v4u32_f32, llvm::Intrinsic::nvvm_tex_unified_2d_v4u32_s32,   llvm::Intrinsic::nvvm_tex_unified_3d_grad_v4f32_f32, llvm::Intrinsic::nvvm_tex_unified_3d_grad_v4s32_f32, llvm::Intrinsic::nvvm_tex_unified_3d_grad_v4u32_f32, llvm::Intrinsic::nvvm_tex_unified_3d_level_v4f32_f32,   llvm::Intrinsic::nvvm_tex_unified_3d_level_v4s32_f32, llvm::Intrinsic::nvvm_tex_unified_3d_level_v4u32_f32, llvm::Intrinsic::nvvm_tex_unified_3d_v4f32_f32, llvm::Intrinsic::nvvm_tex_unified_3d_v4f32_s32,   llvm::Intrinsic::nvvm_tex_unified_3d_v4s32_f32, llvm::Intrinsic::nvvm_tex_unified_3d_v4s32_s32, llvm::Intrinsic::nvvm_tex_unified_3d_v4u32_f32, llvm::Intrinsic::nvvm_tex_unified_3d_v4u32_s32,   llvm::Intrinsic::nvvm_tex_unified_cube_array_level_v4f32_f32, llvm::Intrinsic::nvvm_tex_unified_cube_array_level_v4s32_f32, llvm::Intrinsic::nvvm_tex_unified_cube_array_level_v4u32_f32, llvm::Intrinsic::nvvm_tex_unified_cube_array_v4f32_f32,   llvm::Intrinsic::nvvm_tex_unified_cube_array_v4s32_f32, llvm::Intrinsic::nvvm_tex_unified_cube_array_v4u32_f32, llvm::Intrinsic::nvvm_tex_unified_cube_level_v4f32_f32, llvm::Intrinsic::nvvm_tex_unified_cube_level_v4s32_f32,   llvm::Intrinsic::nvvm_tex_unified_cube_level_v4u32_f32, llvm::Intrinsic::nvvm_tex_unified_cube_v4f32_f32, llvm::Intrinsic::nvvm_tex_unified_cube_v4s32_f32, llvm::Intrinsic::nvvm_tex_unified_cube_v4u32_f32,   llvm::Intrinsic::nvvm_texsurf_handle, llvm::Intrinsic::nvvm_texsurf_handle_internal, llvm::Intrinsic::nvvm_tld4_a_2d_v4f32_f32, llvm::Intrinsic::nvvm_tld4_a_2d_v4s32_f32,   llvm::Intrinsic::nvvm_tld4_a_2d_v4u32_f32, llvm::Intrinsic::nvvm_tld4_b_2d_v4f32_f32, llvm::Intrinsic::nvvm_tld4_b_2d_v4s32_f32, llvm::Intrinsic::nvvm_tld4_b_2d_v4u32_f32,   llvm::Intrinsic::nvvm_tld4_g_2d_v4f32_f32, llvm::Intrinsic::nvvm_tld4_g_2d_v4s32_f32, llvm::Intrinsic::nvvm_tld4_g_2d_v4u32_f32, llvm::Intrinsic::nvvm_tld4_r_2d_v4f32_f32,   llvm::Intrinsic::nvvm_tld4_r_2d_v4s32_f32, llvm::Intrinsic::nvvm_tld4_r_2d_v4u32_f32, llvm::Intrinsic::nvvm_tld4_unified_a_2d_v4f32_f32, llvm::Intrinsic::nvvm_tld4_unified_a_2d_v4s32_f32,   llvm::Intrinsic::nvvm_tld4_unified_a_2d_v4u32_f32, llvm::Intrinsic::nvvm_tld4_unified_b_2d_v4f32_f32, llvm::Intrinsic::nvvm_tld4_unified_b_2d_v4s32_f32, llvm::Intrinsic::nvvm_tld4_unified_b_2d_v4u32_f32,   llvm::Intrinsic::nvvm_tld4_unified_g_2d_v4f32_f32, llvm::Intrinsic::nvvm_tld4_unified_g_2d_v4s32_f32, llvm::Intrinsic::nvvm_tld4_unified_g_2d_v4u32_f32, llvm::Intrinsic::nvvm_tld4_unified_r_2d_v4f32_f32,   llvm::Intrinsic::nvvm_tld4_unified_r_2d_v4s32_f32, llvm::Intrinsic::nvvm_tld4_unified_r_2d_v4u32_f32, llvm::Intrinsic::nvvm_trunc_d, llvm::Intrinsic::nvvm_trunc_f,   llvm::Intrinsic::nvvm_trunc_ftz_f, llvm::Intrinsic::nvvm_txq_array_size, llvm::Intrinsic::nvvm_txq_channel_data_type, llvm::Intrinsic::nvvm_txq_channel_order,   llvm::Intrinsic::nvvm_txq_depth, llvm::Intrinsic::nvvm_txq_height, llvm::Intrinsic::nvvm_txq_num_mipmap_levels, llvm::Intrinsic::nvvm_txq_num_samples,   llvm::Intrinsic::nvvm_txq_width, llvm::Intrinsic::nvvm_ui2d_rm, llvm::Intrinsic::nvvm_ui2d_rn, llvm::Intrinsic::nvvm_ui2d_rp,   llvm::Intrinsic::nvvm_ui2d_rz, llvm::Intrinsic::nvvm_ui2f_rm, llvm::Intrinsic::nvvm_ui2f_rn, llvm::Intrinsic::nvvm_ui2f_rp,   llvm::Intrinsic::nvvm_ui2f_rz, llvm::Intrinsic::nvvm_ull2d_rm, llvm::Intrinsic::nvvm_ull2d_rn, llvm::Intrinsic::nvvm_ull2d_rp,   llvm::Intrinsic::nvvm_ull2d_rz, llvm::Intrinsic::nvvm_ull2f_rm, llvm::Intrinsic::nvvm_ull2f_rn, llvm::Intrinsic::nvvm_ull2f_rp,   llvm::Intrinsic::nvvm_ull2f_rz, llvm::Intrinsic::nvvm_vote_all, llvm::Intrinsic::nvvm_vote_all_sync, llvm::Intrinsic::nvvm_vote_any,   llvm::Intrinsic::nvvm_vote_any_sync, llvm::Intrinsic::nvvm_vote_ballot, llvm::Intrinsic::nvvm_vote_ballot_sync, llvm::Intrinsic::nvvm_vote_uni,   llvm::Intrinsic::nvvm_vote_uni_sync, llvm::Intrinsic::nvvm_wmma_m16n16k16_load_a_f16_col, llvm::Intrinsic::nvvm_wmma_m16n16k16_load_a_f16_col_stride, llvm::Intrinsic::nvvm_wmma_m16n16k16_load_a_f16_row,   llvm::Intrinsic::nvvm_wmma_m16n16k16_load_a_f16_row_stride, llvm::Intrinsic::nvvm_wmma_m16n16k16_load_b_f16_col, llvm::Intrinsic::nvvm_wmma_m16n16k16_load_b_f16_col_stride, llvm::Intrinsic::nvvm_wmma_m16n16k16_load_b_f16_row,   llvm::Intrinsic::nvvm_wmma_m16n16k16_load_b_f16_row_stride, llvm::Intrinsic::nvvm_wmma_m16n16k16_load_c_f16_col, llvm::Intrinsic::nvvm_wmma_m16n16k16_load_c_f32_col, llvm::Intrinsic::nvvm_wmma_m16n16k16_load_c_f16_col_stride,   llvm::Intrinsic::nvvm_wmma_m16n16k16_load_c_f32_col_stride, llvm::Intrinsic::nvvm_wmma_m16n16k16_load_c_f16_row, llvm::Intrinsic::nvvm_wmma_m16n16k16_load_c_f32_row, llvm::Intrinsic::nvvm_wmma_m16n16k16_load_c_f16_row_stride,   llvm::Intrinsic::nvvm_wmma_m16n16k16_load_c_f32_row_stride, llvm::Intrinsic::nvvm_wmma_m16n16k16_mma_col_col_f16_f16, llvm::Intrinsic::nvvm_wmma_m16n16k16_mma_col_col_f16_f16_satfinite, llvm::Intrinsic::nvvm_wmma_m16n16k16_mma_col_col_f16_f32,   llvm::Intrinsic::nvvm_wmma_m16n16k16_mma_col_col_f16_f32_satfinite, llvm::Intrinsic::nvvm_wmma_m16n16k16_mma_col_col_f32_f16, llvm::Intrinsic::nvvm_wmma_m16n16k16_mma_col_col_f32_f16_satfinite, llvm::Intrinsic::nvvm_wmma_m16n16k16_mma_col_col_f32_f32,   llvm::Intrinsic::nvvm_wmma_m16n16k16_mma_col_col_f32_f32_satfinite, llvm::Intrinsic::nvvm_wmma_m16n16k16_mma_col_row_f16_f16, llvm::Intrinsic::nvvm_wmma_m16n16k16_mma_col_row_f16_f16_satfinite, llvm::Intrinsic::nvvm_wmma_m16n16k16_mma_col_row_f16_f32,   llvm::Intrinsic::nvvm_wmma_m16n16k16_mma_col_row_f16_f32_satfinite, llvm::Intrinsic::nvvm_wmma_m16n16k16_mma_col_row_f32_f16, llvm::Intrinsic::nvvm_wmma_m16n16k16_mma_col_row_f32_f16_satfinite, llvm::Intrinsic::nvvm_wmma_m16n16k16_mma_col_row_f32_f32,   llvm::Intrinsic::nvvm_wmma_m16n16k16_mma_col_row_f32_f32_satfinite, llvm::Intrinsic::nvvm_wmma_m16n16k16_mma_row_col_f16_f16, llvm::Intrinsic::nvvm_wmma_m16n16k16_mma_row_col_f16_f16_satfinite, llvm::Intrinsic::nvvm_wmma_m16n16k16_mma_row_col_f16_f32,   llvm::Intrinsic::nvvm_wmma_m16n16k16_mma_row_col_f16_f32_satfinite, llvm::Intrinsic::nvvm_wmma_m16n16k16_mma_row_col_f32_f16, llvm::Intrinsic::nvvm_wmma_m16n16k16_mma_row_col_f32_f16_satfinite, llvm::Intrinsic::nvvm_wmma_m16n16k16_mma_row_col_f32_f32,   llvm::Intrinsic::nvvm_wmma_m16n16k16_mma_row_col_f32_f32_satfinite, llvm::Intrinsic::nvvm_wmma_m16n16k16_mma_row_row_f16_f16, llvm::Intrinsic::nvvm_wmma_m16n16k16_mma_row_row_f16_f16_satfinite, llvm::Intrinsic::nvvm_wmma_m16n16k16_mma_row_row_f16_f32,   llvm::Intrinsic::nvvm_wmma_m16n16k16_mma_row_row_f16_f32_satfinite, llvm::Intrinsic::nvvm_wmma_m16n16k16_mma_row_row_f32_f16, llvm::Intrinsic::nvvm_wmma_m16n16k16_mma_row_row_f32_f16_satfinite, llvm::Intrinsic::nvvm_wmma_m16n16k16_mma_row_row_f32_f32,   llvm::Intrinsic::nvvm_wmma_m16n16k16_mma_row_row_f32_f32_satfinite, llvm::Intrinsic::nvvm_wmma_m16n16k16_store_d_f16_col, llvm::Intrinsic::nvvm_wmma_m16n16k16_store_d_f32_col, llvm::Intrinsic::nvvm_wmma_m16n16k16_store_d_f16_col_stride,   llvm::Intrinsic::nvvm_wmma_m16n16k16_store_d_f32_col_stride, llvm::Intrinsic::nvvm_wmma_m16n16k16_store_d_f16_row, llvm::Intrinsic::nvvm_wmma_m16n16k16_store_d_f32_row, llvm::Intrinsic::nvvm_wmma_m16n16k16_store_d_f16_row_stride,   llvm::Intrinsic::nvvm_wmma_m16n16k16_store_d_f32_row_stride, llvm::Intrinsic::nvvm_wmma_m32n8k16_load_a_f16_col, llvm::Intrinsic::nvvm_wmma_m32n8k16_load_a_f16_col_stride, llvm::Intrinsic::nvvm_wmma_m32n8k16_load_a_f16_row,   llvm::Intrinsic::nvvm_wmma_m32n8k16_load_a_f16_row_stride, llvm::Intrinsic::nvvm_wmma_m32n8k16_load_b_f16_col, llvm::Intrinsic::nvvm_wmma_m32n8k16_load_b_f16_col_stride, llvm::Intrinsic::nvvm_wmma_m32n8k16_load_b_f16_row,   llvm::Intrinsic::nvvm_wmma_m32n8k16_load_b_f16_row_stride, llvm::Intrinsic::nvvm_wmma_m32n8k16_load_c_f16_col, llvm::Intrinsic::nvvm_wmma_m32n8k16_load_c_f32_col, llvm::Intrinsic::nvvm_wmma_m32n8k16_load_c_f16_col_stride,   llvm::Intrinsic::nvvm_wmma_m32n8k16_load_c_f32_col_stride, llvm::Intrinsic::nvvm_wmma_m32n8k16_load_c_f16_row, llvm::Intrinsic::nvvm_wmma_m32n8k16_load_c_f32_row, llvm::Intrinsic::nvvm_wmma_m32n8k16_load_c_f16_row_stride,   llvm::Intrinsic::nvvm_wmma_m32n8k16_load_c_f32_row_stride, llvm::Intrinsic::nvvm_wmma_m32n8k16_mma_col_col_f16_f16, llvm::Intrinsic::nvvm_wmma_m32n8k16_mma_col_col_f16_f16_satfinite, llvm::Intrinsic::nvvm_wmma_m32n8k16_mma_col_col_f16_f32,   llvm::Intrinsic::nvvm_wmma_m32n8k16_mma_col_col_f16_f32_satfinite, llvm::Intrinsic::nvvm_wmma_m32n8k16_mma_col_col_f32_f16, llvm::Intrinsic::nvvm_wmma_m32n8k16_mma_col_col_f32_f16_satfinite, llvm::Intrinsic::nvvm_wmma_m32n8k16_mma_col_col_f32_f32,   llvm::Intrinsic::nvvm_wmma_m32n8k16_mma_col_col_f32_f32_satfinite, llvm::Intrinsic::nvvm_wmma_m32n8k16_mma_col_row_f16_f16, llvm::Intrinsic::nvvm_wmma_m32n8k16_mma_col_row_f16_f16_satfinite, llvm::Intrinsic::nvvm_wmma_m32n8k16_mma_col_row_f16_f32,   llvm::Intrinsic::nvvm_wmma_m32n8k16_mma_col_row_f16_f32_satfinite, llvm::Intrinsic::nvvm_wmma_m32n8k16_mma_col_row_f32_f16, llvm::Intrinsic::nvvm_wmma_m32n8k16_mma_col_row_f32_f16_satfinite, llvm::Intrinsic::nvvm_wmma_m32n8k16_mma_col_row_f32_f32,   llvm::Intrinsic::nvvm_wmma_m32n8k16_mma_col_row_f32_f32_satfinite, llvm::Intrinsic::nvvm_wmma_m32n8k16_mma_row_col_f16_f16, llvm::Intrinsic::nvvm_wmma_m32n8k16_mma_row_col_f16_f16_satfinite, llvm::Intrinsic::nvvm_wmma_m32n8k16_mma_row_col_f16_f32,   llvm::Intrinsic::nvvm_wmma_m32n8k16_mma_row_col_f16_f32_satfinite, llvm::Intrinsic::nvvm_wmma_m32n8k16_mma_row_col_f32_f16, llvm::Intrinsic::nvvm_wmma_m32n8k16_mma_row_col_f32_f16_satfinite, llvm::Intrinsic::nvvm_wmma_m32n8k16_mma_row_col_f32_f32,   llvm::Intrinsic::nvvm_wmma_m32n8k16_mma_row_col_f32_f32_satfinite, llvm::Intrinsic::nvvm_wmma_m32n8k16_mma_row_row_f16_f16, llvm::Intrinsic::nvvm_wmma_m32n8k16_mma_row_row_f16_f16_satfinite, llvm::Intrinsic::nvvm_wmma_m32n8k16_mma_row_row_f16_f32,   llvm::Intrinsic::nvvm_wmma_m32n8k16_mma_row_row_f16_f32_satfinite, llvm::Intrinsic::nvvm_wmma_m32n8k16_mma_row_row_f32_f16, llvm::Intrinsic::nvvm_wmma_m32n8k16_mma_row_row_f32_f16_satfinite, llvm::Intrinsic::nvvm_wmma_m32n8k16_mma_row_row_f32_f32,   llvm::Intrinsic::nvvm_wmma_m32n8k16_mma_row_row_f32_f32_satfinite, llvm::Intrinsic::nvvm_wmma_m32n8k16_store_d_f16_col, llvm::Intrinsic::nvvm_wmma_m32n8k16_store_d_f32_col, llvm::Intrinsic::nvvm_wmma_m32n8k16_store_d_f16_col_stride,   llvm::Intrinsic::nvvm_wmma_m32n8k16_store_d_f32_col_stride, llvm::Intrinsic::nvvm_wmma_m32n8k16_store_d_f16_row, llvm::Intrinsic::nvvm_wmma_m32n8k16_store_d_f32_row, llvm::Intrinsic::nvvm_wmma_m32n8k16_store_d_f16_row_stride,   llvm::Intrinsic::nvvm_wmma_m32n8k16_store_d_f32_row_stride, llvm::Intrinsic::nvvm_wmma_m8n32k16_load_a_f16_col, llvm::Intrinsic::nvvm_wmma_m8n32k16_load_a_f16_col_stride, llvm::Intrinsic::nvvm_wmma_m8n32k16_load_a_f16_row,   llvm::Intrinsic::nvvm_wmma_m8n32k16_load_a_f16_row_stride, llvm::Intrinsic::nvvm_wmma_m8n32k16_load_b_f16_col, llvm::Intrinsic::nvvm_wmma_m8n32k16_load_b_f16_col_stride, llvm::Intrinsic::nvvm_wmma_m8n32k16_load_b_f16_row,   llvm::Intrinsic::nvvm_wmma_m8n32k16_load_b_f16_row_stride, llvm::Intrinsic::nvvm_wmma_m8n32k16_load_c_f16_col, llvm::Intrinsic::nvvm_wmma_m8n32k16_load_c_f32_col, llvm::Intrinsic::nvvm_wmma_m8n32k16_load_c_f16_col_stride,   llvm::Intrinsic::nvvm_wmma_m8n32k16_load_c_f32_col_stride, llvm::Intrinsic::nvvm_wmma_m8n32k16_load_c_f16_row, llvm::Intrinsic::nvvm_wmma_m8n32k16_load_c_f32_row, llvm::Intrinsic::nvvm_wmma_m8n32k16_load_c_f16_row_stride,   llvm::Intrinsic::nvvm_wmma_m8n32k16_load_c_f32_row_stride, llvm::Intrinsic::nvvm_wmma_m8n32k16_mma_col_col_f16_f16, llvm::Intrinsic::nvvm_wmma_m8n32k16_mma_col_col_f16_f16_satfinite, llvm::Intrinsic::nvvm_wmma_m8n32k16_mma_col_col_f16_f32,   llvm::Intrinsic::nvvm_wmma_m8n32k16_mma_col_col_f16_f32_satfinite, llvm::Intrinsic::nvvm_wmma_m8n32k16_mma_col_col_f32_f16, llvm::Intrinsic::nvvm_wmma_m8n32k16_mma_col_col_f32_f16_satfinite, llvm::Intrinsic::nvvm_wmma_m8n32k16_mma_col_col_f32_f32,   llvm::Intrinsic::nvvm_wmma_m8n32k16_mma_col_col_f32_f32_satfinite, llvm::Intrinsic::nvvm_wmma_m8n32k16_mma_col_row_f16_f16, llvm::Intrinsic::nvvm_wmma_m8n32k16_mma_col_row_f16_f16_satfinite, llvm::Intrinsic::nvvm_wmma_m8n32k16_mma_col_row_f16_f32,   llvm::Intrinsic::nvvm_wmma_m8n32k16_mma_col_row_f16_f32_satfinite, llvm::Intrinsic::nvvm_wmma_m8n32k16_mma_col_row_f32_f16, llvm::Intrinsic::nvvm_wmma_m8n32k16_mma_col_row_f32_f16_satfinite, llvm::Intrinsic::nvvm_wmma_m8n32k16_mma_col_row_f32_f32,   llvm::Intrinsic::nvvm_wmma_m8n32k16_mma_col_row_f32_f32_satfinite, llvm::Intrinsic::nvvm_wmma_m8n32k16_mma_row_col_f16_f16, llvm::Intrinsic::nvvm_wmma_m8n32k16_mma_row_col_f16_f16_satfinite, llvm::Intrinsic::nvvm_wmma_m8n32k16_mma_row_col_f16_f32,   llvm::Intrinsic::nvvm_wmma_m8n32k16_mma_row_col_f16_f32_satfinite, llvm::Intrinsic::nvvm_wmma_m8n32k16_mma_row_col_f32_f16, llvm::Intrinsic::nvvm_wmma_m8n32k16_mma_row_col_f32_f16_satfinite, llvm::Intrinsic::nvvm_wmma_m8n32k16_mma_row_col_f32_f32,   llvm::Intrinsic::nvvm_wmma_m8n32k16_mma_row_col_f32_f32_satfinite, llvm::Intrinsic::nvvm_wmma_m8n32k16_mma_row_row_f16_f16, llvm::Intrinsic::nvvm_wmma_m8n32k16_mma_row_row_f16_f16_satfinite, llvm::Intrinsic::nvvm_wmma_m8n32k16_mma_row_row_f16_f32,   llvm::Intrinsic::nvvm_wmma_m8n32k16_mma_row_row_f16_f32_satfinite, llvm::Intrinsic::nvvm_wmma_m8n32k16_mma_row_row_f32_f16, llvm::Intrinsic::nvvm_wmma_m8n32k16_mma_row_row_f32_f16_satfinite, llvm::Intrinsic::nvvm_wmma_m8n32k16_mma_row_row_f32_f32,   llvm::Intrinsic::nvvm_wmma_m8n32k16_mma_row_row_f32_f32_satfinite, llvm::Intrinsic::nvvm_wmma_m8n32k16_store_d_f16_col, llvm::Intrinsic::nvvm_wmma_m8n32k16_store_d_f32_col, llvm::Intrinsic::nvvm_wmma_m8n32k16_store_d_f16_col_stride,   llvm::Intrinsic::nvvm_wmma_m8n32k16_store_d_f32_col_stride, llvm::Intrinsic::nvvm_wmma_m8n32k16_store_d_f16_row, llvm::Intrinsic::nvvm_wmma_m8n32k16_store_d_f32_row, llvm::Intrinsic::nvvm_wmma_m8n32k16_store_d_f16_row_stride,   llvm::Intrinsic::nvvm_wmma_m8n32k16_store_d_f32_row_stride, llvm::Intrinsic::ppc_addf128_round_to_odd, llvm::Intrinsic::ppc_altivec_crypto_vcipher, llvm::Intrinsic::ppc_altivec_crypto_vcipherlast,   llvm::Intrinsic::ppc_altivec_crypto_vncipher, llvm::Intrinsic::ppc_altivec_crypto_vncipherlast, llvm::Intrinsic::ppc_altivec_crypto_vpermxor, llvm::Intrinsic::ppc_altivec_crypto_vpmsumb,   llvm::Intrinsic::ppc_altivec_crypto_vpmsumd, llvm::Intrinsic::ppc_altivec_crypto_vpmsumh, llvm::Intrinsic::ppc_altivec_crypto_vpmsumw, llvm::Intrinsic::ppc_altivec_crypto_vsbox,   llvm::Intrinsic::ppc_altivec_crypto_vshasigmad, llvm::Intrinsic::ppc_altivec_crypto_vshasigmaw, llvm::Intrinsic::ppc_altivec_dss, llvm::Intrinsic::ppc_altivec_dssall,   llvm::Intrinsic::ppc_altivec_dst, llvm::Intrinsic::ppc_altivec_dstst, llvm::Intrinsic::ppc_altivec_dststt, llvm::Intrinsic::ppc_altivec_dstt,   llvm::Intrinsic::ppc_altivec_lvebx, llvm::Intrinsic::ppc_altivec_lvehx, llvm::Intrinsic::ppc_altivec_lvewx, llvm::Intrinsic::ppc_altivec_lvsl,   llvm::Intrinsic::ppc_altivec_lvsr, llvm::Intrinsic::ppc_altivec_lvx, llvm::Intrinsic::ppc_altivec_lvxl, llvm::Intrinsic::ppc_altivec_mfvscr,   llvm::Intrinsic::ppc_altivec_mtvscr, llvm::Intrinsic::ppc_altivec_stvebx, llvm::Intrinsic::ppc_altivec_stvehx, llvm::Intrinsic::ppc_altivec_stvewx,   llvm::Intrinsic::ppc_altivec_stvx, llvm::Intrinsic::ppc_altivec_stvxl, llvm::Intrinsic::ppc_altivec_vabsdub, llvm::Intrinsic::ppc_altivec_vabsduh,   llvm::Intrinsic::ppc_altivec_vabsduw, llvm::Intrinsic::ppc_altivec_vaddcuq, llvm::Intrinsic::ppc_altivec_vaddcuw, llvm::Intrinsic::ppc_altivec_vaddecuq,   llvm::Intrinsic::ppc_altivec_vaddeuqm, llvm::Intrinsic::ppc_altivec_vaddsbs, llvm::Intrinsic::ppc_altivec_vaddshs, llvm::Intrinsic::ppc_altivec_vaddsws,   llvm::Intrinsic::ppc_altivec_vaddubs, llvm::Intrinsic::ppc_altivec_vadduhs, llvm::Intrinsic::ppc_altivec_vadduws, llvm::Intrinsic::ppc_altivec_vavgsb,   llvm::Intrinsic::ppc_altivec_vavgsh, llvm::Intrinsic::ppc_altivec_vavgsw, llvm::Intrinsic::ppc_altivec_vavgub, llvm::Intrinsic::ppc_altivec_vavguh,   llvm::Intrinsic::ppc_altivec_vavguw, llvm::Intrinsic::ppc_altivec_vbpermq, llvm::Intrinsic::ppc_altivec_vcfsx, llvm::Intrinsic::ppc_altivec_vcfux,   llvm::Intrinsic::ppc_altivec_vclzlsbb, llvm::Intrinsic::ppc_altivec_vcmpbfp, llvm::Intrinsic::ppc_altivec_vcmpbfp_p, llvm::Intrinsic::ppc_altivec_vcmpeqfp,   llvm::Intrinsic::ppc_altivec_vcmpeqfp_p, llvm::Intrinsic::ppc_altivec_vcmpequb, llvm::Intrinsic::ppc_altivec_vcmpequb_p, llvm::Intrinsic::ppc_altivec_vcmpequd,   llvm::Intrinsic::ppc_altivec_vcmpequd_p, llvm::Intrinsic::ppc_altivec_vcmpequh, llvm::Intrinsic::ppc_altivec_vcmpequh_p, llvm::Intrinsic::ppc_altivec_vcmpequw,   llvm::Intrinsic::ppc_altivec_vcmpequw_p, llvm::Intrinsic::ppc_altivec_vcmpgefp, llvm::Intrinsic::ppc_altivec_vcmpgefp_p, llvm::Intrinsic::ppc_altivec_vcmpgtfp,   llvm::Intrinsic::ppc_altivec_vcmpgtfp_p, llvm::Intrinsic::ppc_altivec_vcmpgtsb, llvm::Intrinsic::ppc_altivec_vcmpgtsb_p, llvm::Intrinsic::ppc_altivec_vcmpgtsd,   llvm::Intrinsic::ppc_altivec_vcmpgtsd_p, llvm::Intrinsic::ppc_altivec_vcmpgtsh, llvm::Intrinsic::ppc_altivec_vcmpgtsh_p, llvm::Intrinsic::ppc_altivec_vcmpgtsw,   llvm::Intrinsic::ppc_altivec_vcmpgtsw_p, llvm::Intrinsic::ppc_altivec_vcmpgtub, llvm::Intrinsic::ppc_altivec_vcmpgtub_p, llvm::Intrinsic::ppc_altivec_vcmpgtud,   llvm::Intrinsic::ppc_altivec_vcmpgtud_p, llvm::Intrinsic::ppc_altivec_vcmpgtuh, llvm::Intrinsic::ppc_altivec_vcmpgtuh_p, llvm::Intrinsic::ppc_altivec_vcmpgtuw,   llvm::Intrinsic::ppc_altivec_vcmpgtuw_p, llvm::Intrinsic::ppc_altivec_vcmpneb, llvm::Intrinsic::ppc_altivec_vcmpneb_p, llvm::Intrinsic::ppc_altivec_vcmpneh,   llvm::Intrinsic::ppc_altivec_vcmpneh_p, llvm::Intrinsic::ppc_altivec_vcmpnew, llvm::Intrinsic::ppc_altivec_vcmpnew_p, llvm::Intrinsic::ppc_altivec_vcmpnezb,   llvm::Intrinsic::ppc_altivec_vcmpnezb_p, llvm::Intrinsic::ppc_altivec_vcmpnezh, llvm::Intrinsic::ppc_altivec_vcmpnezh_p, llvm::Intrinsic::ppc_altivec_vcmpnezw,   llvm::Intrinsic::ppc_altivec_vcmpnezw_p, llvm::Intrinsic::ppc_altivec_vctsxs, llvm::Intrinsic::ppc_altivec_vctuxs, llvm::Intrinsic::ppc_altivec_vctzlsbb,   llvm::Intrinsic::ppc_altivec_vexptefp, llvm::Intrinsic::ppc_altivec_vgbbd, llvm::Intrinsic::ppc_altivec_vlogefp, llvm::Intrinsic::ppc_altivec_vmaddfp,   llvm::Intrinsic::ppc_altivec_vmaxfp, llvm::Intrinsic::ppc_altivec_vmaxsb, llvm::Intrinsic::ppc_altivec_vmaxsd, llvm::Intrinsic::ppc_altivec_vmaxsh,   llvm::Intrinsic::ppc_altivec_vmaxsw, llvm::Intrinsic::ppc_altivec_vmaxub, llvm::Intrinsic::ppc_altivec_vmaxud, llvm::Intrinsic::ppc_altivec_vmaxuh,   llvm::Intrinsic::ppc_altivec_vmaxuw, llvm::Intrinsic::ppc_altivec_vmhaddshs, llvm::Intrinsic::ppc_altivec_vmhraddshs, llvm::Intrinsic::ppc_altivec_vminfp,   llvm::Intrinsic::ppc_altivec_vminsb, llvm::Intrinsic::ppc_altivec_vminsd, llvm::Intrinsic::ppc_altivec_vminsh, llvm::Intrinsic::ppc_altivec_vminsw,   llvm::Intrinsic::ppc_altivec_vminub, llvm::Intrinsic::ppc_altivec_vminud, llvm::Intrinsic::ppc_altivec_vminuh, llvm::Intrinsic::ppc_altivec_vminuw,   llvm::Intrinsic::ppc_altivec_vmladduhm, llvm::Intrinsic::ppc_altivec_vmsummbm, llvm::Intrinsic::ppc_altivec_vmsumshm, llvm::Intrinsic::ppc_altivec_vmsumshs,   llvm::Intrinsic::ppc_altivec_vmsumubm, llvm::Intrinsic::ppc_altivec_vmsumuhm, llvm::Intrinsic::ppc_altivec_vmsumuhs, llvm::Intrinsic::ppc_altivec_vmulesb,   llvm::Intrinsic::ppc_altivec_vmulesh, llvm::Intrinsic::ppc_altivec_vmulesw, llvm::Intrinsic::ppc_altivec_vmuleub, llvm::Intrinsic::ppc_altivec_vmuleuh,   llvm::Intrinsic::ppc_altivec_vmuleuw, llvm::Intrinsic::ppc_altivec_vmulosb, llvm::Intrinsic::ppc_altivec_vmulosh, llvm::Intrinsic::ppc_altivec_vmulosw,   llvm::Intrinsic::ppc_altivec_vmuloub, llvm::Intrinsic::ppc_altivec_vmulouh, llvm::Intrinsic::ppc_altivec_vmulouw, llvm::Intrinsic::ppc_altivec_vnmsubfp,   llvm::Intrinsic::ppc_altivec_vperm, llvm::Intrinsic::ppc_altivec_vpkpx, llvm::Intrinsic::ppc_altivec_vpksdss, llvm::Intrinsic::ppc_altivec_vpksdus,   llvm::Intrinsic::ppc_altivec_vpkshss, llvm::Intrinsic::ppc_altivec_vpkshus, llvm::Intrinsic::ppc_altivec_vpkswss, llvm::Intrinsic::ppc_altivec_vpkswus,   llvm::Intrinsic::ppc_altivec_vpkudus, llvm::Intrinsic::ppc_altivec_vpkuhus, llvm::Intrinsic::ppc_altivec_vpkuwus, llvm::Intrinsic::ppc_altivec_vprtybd,   llvm::Intrinsic::ppc_altivec_vprtybq, llvm::Intrinsic::ppc_altivec_vprtybw, llvm::Intrinsic::ppc_altivec_vrefp, llvm::Intrinsic::ppc_altivec_vrfim,   llvm::Intrinsic::ppc_altivec_vrfin, llvm::Intrinsic::ppc_altivec_vrfip, llvm::Intrinsic::ppc_altivec_vrfiz, llvm::Intrinsic::ppc_altivec_vrlb,   llvm::Intrinsic::ppc_altivec_vrld, llvm::Intrinsic::ppc_altivec_vrldmi, llvm::Intrinsic::ppc_altivec_vrldnm, llvm::Intrinsic::ppc_altivec_vrlh,   llvm::Intrinsic::ppc_altivec_vrlw, llvm::Intrinsic::ppc_altivec_vrlwmi, llvm::Intrinsic::ppc_altivec_vrlwnm, llvm::Intrinsic::ppc_altivec_vrsqrtefp,   llvm::Intrinsic::ppc_altivec_vsel, llvm::Intrinsic::ppc_altivec_vsl, llvm::Intrinsic::ppc_altivec_vslb, llvm::Intrinsic::ppc_altivec_vslh,   llvm::Intrinsic::ppc_altivec_vslo, llvm::Intrinsic::ppc_altivec_vslv, llvm::Intrinsic::ppc_altivec_vslw, llvm::Intrinsic::ppc_altivec_vsr,   llvm::Intrinsic::ppc_altivec_vsrab, llvm::Intrinsic::ppc_altivec_vsrah, llvm::Intrinsic::ppc_altivec_vsraw, llvm::Intrinsic::ppc_altivec_vsrb,   llvm::Intrinsic::ppc_altivec_vsrh, llvm::Intrinsic::ppc_altivec_vsro, llvm::Intrinsic::ppc_altivec_vsrv, llvm::Intrinsic::ppc_altivec_vsrw,   llvm::Intrinsic::ppc_altivec_vsubcuq, llvm::Intrinsic::ppc_altivec_vsubcuw, llvm::Intrinsic::ppc_altivec_vsubecuq, llvm::Intrinsic::ppc_altivec_vsubeuqm,   llvm::Intrinsic::ppc_altivec_vsubsbs, llvm::Intrinsic::ppc_altivec_vsubshs, llvm::Intrinsic::ppc_altivec_vsubsws, llvm::Intrinsic::ppc_altivec_vsububs,   llvm::Intrinsic::ppc_altivec_vsubuhs, llvm::Intrinsic::ppc_altivec_vsubuws, llvm::Intrinsic::ppc_altivec_vsum2sws, llvm::Intrinsic::ppc_altivec_vsum4sbs,   llvm::Intrinsic::ppc_altivec_vsum4shs, llvm::Intrinsic::ppc_altivec_vsum4ubs, llvm::Intrinsic::ppc_altivec_vsumsws, llvm::Intrinsic::ppc_altivec_vupkhpx,   llvm::Intrinsic::ppc_altivec_vupkhsb, llvm::Intrinsic::ppc_altivec_vupkhsh, llvm::Intrinsic::ppc_altivec_vupkhsw, llvm::Intrinsic::ppc_altivec_vupklpx,   llvm::Intrinsic::ppc_altivec_vupklsb, llvm::Intrinsic::ppc_altivec_vupklsh, llvm::Intrinsic::ppc_altivec_vupklsw, llvm::Intrinsic::ppc_bpermd,   llvm::Intrinsic::ppc_cfence, llvm::Intrinsic::ppc_dcba, llvm::Intrinsic::ppc_dcbf, llvm::Intrinsic::ppc_dcbi,   llvm::Intrinsic::ppc_dcbst, llvm::Intrinsic::ppc_dcbt, llvm::Intrinsic::ppc_dcbtst, llvm::Intrinsic::ppc_dcbz,   llvm::Intrinsic::ppc_dcbzl, llvm::Intrinsic::ppc_divde, llvm::Intrinsic::ppc_divdeu, llvm::Intrinsic::ppc_divf128_round_to_odd,   llvm::Intrinsic::ppc_divwe, llvm::Intrinsic::ppc_divweu, llvm::Intrinsic::ppc_fmaf128_round_to_odd, llvm::Intrinsic::ppc_get_texasr,   llvm::Intrinsic::ppc_get_texasru, llvm::Intrinsic::ppc_get_tfhar, llvm::Intrinsic::ppc_get_tfiar, llvm::Intrinsic::ppc_is_decremented_ctr_nonzero,   llvm::Intrinsic::ppc_lwsync, llvm::Intrinsic::ppc_mtctr, llvm::Intrinsic::ppc_mulf128_round_to_odd, llvm::Intrinsic::ppc_qpx_qvfabs,   llvm::Intrinsic::ppc_qpx_qvfadd, llvm::Intrinsic::ppc_qpx_qvfadds, llvm::Intrinsic::ppc_qpx_qvfcfid, llvm::Intrinsic::ppc_qpx_qvfcfids,   llvm::Intrinsic::ppc_qpx_qvfcfidu, llvm::Intrinsic::ppc_qpx_qvfcfidus, llvm::Intrinsic::ppc_qpx_qvfcmpeq, llvm::Intrinsic::ppc_qpx_qvfcmpgt,   llvm::Intrinsic::ppc_qpx_qvfcmplt, llvm::Intrinsic::ppc_qpx_qvfcpsgn, llvm::Intrinsic::ppc_qpx_qvfctid, llvm::Intrinsic::ppc_qpx_qvfctidu,   llvm::Intrinsic::ppc_qpx_qvfctiduz, llvm::Intrinsic::ppc_qpx_qvfctidz, llvm::Intrinsic::ppc_qpx_qvfctiw, llvm::Intrinsic::ppc_qpx_qvfctiwu,   llvm::Intrinsic::ppc_qpx_qvfctiwuz, llvm::Intrinsic::ppc_qpx_qvfctiwz, llvm::Intrinsic::ppc_qpx_qvflogical, llvm::Intrinsic::ppc_qpx_qvfmadd,   llvm::Intrinsic::ppc_qpx_qvfmadds, llvm::Intrinsic::ppc_qpx_qvfmsub, llvm::Intrinsic::ppc_qpx_qvfmsubs, llvm::Intrinsic::ppc_qpx_qvfmul,   llvm::Intrinsic::ppc_qpx_qvfmuls, llvm::Intrinsic::ppc_qpx_qvfnabs, llvm::Intrinsic::ppc_qpx_qvfneg, llvm::Intrinsic::ppc_qpx_qvfnmadd,   llvm::Intrinsic::ppc_qpx_qvfnmadds, llvm::Intrinsic::ppc_qpx_qvfnmsub, llvm::Intrinsic::ppc_qpx_qvfnmsubs, llvm::Intrinsic::ppc_qpx_qvfperm,   llvm::Intrinsic::ppc_qpx_qvfre, llvm::Intrinsic::ppc_qpx_qvfres, llvm::Intrinsic::ppc_qpx_qvfrim, llvm::Intrinsic::ppc_qpx_qvfrin,   llvm::Intrinsic::ppc_qpx_qvfrip, llvm::Intrinsic::ppc_qpx_qvfriz, llvm::Intrinsic::ppc_qpx_qvfrsp, llvm::Intrinsic::ppc_qpx_qvfrsqrte,   llvm::Intrinsic::ppc_qpx_qvfrsqrtes, llvm::Intrinsic::ppc_qpx_qvfsel, llvm::Intrinsic::ppc_qpx_qvfsub, llvm::Intrinsic::ppc_qpx_qvfsubs,   llvm::Intrinsic::ppc_qpx_qvftstnan, llvm::Intrinsic::ppc_qpx_qvfxmadd, llvm::Intrinsic::ppc_qpx_qvfxmadds, llvm::Intrinsic::ppc_qpx_qvfxmul,   llvm::Intrinsic::ppc_qpx_qvfxmuls, llvm::Intrinsic::ppc_qpx_qvfxxcpnmadd, llvm::Intrinsic::ppc_qpx_qvfxxcpnmadds, llvm::Intrinsic::ppc_qpx_qvfxxmadd,   llvm::Intrinsic::ppc_qpx_qvfxxmadds, llvm::Intrinsic::ppc_qpx_qvfxxnpmadd, llvm::Intrinsic::ppc_qpx_qvfxxnpmadds, llvm::Intrinsic::ppc_qpx_qvgpci,   llvm::Intrinsic::ppc_qpx_qvlfcd, llvm::Intrinsic::ppc_qpx_qvlfcda, llvm::Intrinsic::ppc_qpx_qvlfcs, llvm::Intrinsic::ppc_qpx_qvlfcsa,   llvm::Intrinsic::ppc_qpx_qvlfd, llvm::Intrinsic::ppc_qpx_qvlfda, llvm::Intrinsic::ppc_qpx_qvlfiwa, llvm::Intrinsic::ppc_qpx_qvlfiwaa,   llvm::Intrinsic::ppc_qpx_qvlfiwz, llvm::Intrinsic::ppc_qpx_qvlfiwza, llvm::Intrinsic::ppc_qpx_qvlfs, llvm::Intrinsic::ppc_qpx_qvlfsa,   llvm::Intrinsic::ppc_qpx_qvlpcld, llvm::Intrinsic::ppc_qpx_qvlpcls, llvm::Intrinsic::ppc_qpx_qvlpcrd, llvm::Intrinsic::ppc_qpx_qvlpcrs,   llvm::Intrinsic::ppc_qpx_qvstfcd, llvm::Intrinsic::ppc_qpx_qvstfcda, llvm::Intrinsic::ppc_qpx_qvstfcs, llvm::Intrinsic::ppc_qpx_qvstfcsa,   llvm::Intrinsic::ppc_qpx_qvstfd, llvm::Intrinsic::ppc_qpx_qvstfda, llvm::Intrinsic::ppc_qpx_qvstfiw, llvm::Intrinsic::ppc_qpx_qvstfiwa,   llvm::Intrinsic::ppc_qpx_qvstfs, llvm::Intrinsic::ppc_qpx_qvstfsa, llvm::Intrinsic::ppc_scalar_extract_expq, llvm::Intrinsic::ppc_scalar_insert_exp_qp,   llvm::Intrinsic::ppc_set_texasr, llvm::Intrinsic::ppc_set_texasru, llvm::Intrinsic::ppc_set_tfhar, llvm::Intrinsic::ppc_set_tfiar,   llvm::Intrinsic::ppc_sqrtf128_round_to_odd, llvm::Intrinsic::ppc_subf128_round_to_odd, llvm::Intrinsic::ppc_sync, llvm::Intrinsic::ppc_tabort,   llvm::Intrinsic::ppc_tabortdc, llvm::Intrinsic::ppc_tabortdci, llvm::Intrinsic::ppc_tabortwc, llvm::Intrinsic::ppc_tabortwci,   llvm::Intrinsic::ppc_tbegin, llvm::Intrinsic::ppc_tcheck, llvm::Intrinsic::ppc_tend, llvm::Intrinsic::ppc_tendall,   llvm::Intrinsic::ppc_trechkpt, llvm::Intrinsic::ppc_treclaim, llvm::Intrinsic::ppc_tresume, llvm::Intrinsic::ppc_truncf128_round_to_odd,   llvm::Intrinsic::ppc_tsr, llvm::Intrinsic::ppc_tsuspend, llvm::Intrinsic::ppc_ttest, llvm::Intrinsic::ppc_vsx_lxvd2x,   llvm::Intrinsic::ppc_vsx_lxvd2x_be, llvm::Intrinsic::ppc_vsx_lxvl, llvm::Intrinsic::ppc_vsx_lxvll, llvm::Intrinsic::ppc_vsx_lxvw4x,   llvm::Intrinsic::ppc_vsx_lxvw4x_be, llvm::Intrinsic::ppc_vsx_stxvd2x, llvm::Intrinsic::ppc_vsx_stxvd2x_be, llvm::Intrinsic::ppc_vsx_stxvl,   llvm::Intrinsic::ppc_vsx_stxvll, llvm::Intrinsic::ppc_vsx_stxvw4x, llvm::Intrinsic::ppc_vsx_stxvw4x_be, llvm::Intrinsic::ppc_vsx_xsmaxdp,   llvm::Intrinsic::ppc_vsx_xsmindp, llvm::Intrinsic::ppc_vsx_xvcmpeqdp, llvm::Intrinsic::ppc_vsx_xvcmpeqdp_p, llvm::Intrinsic::ppc_vsx_xvcmpeqsp,   llvm::Intrinsic::ppc_vsx_xvcmpeqsp_p, llvm::Intrinsic::ppc_vsx_xvcmpgedp, llvm::Intrinsic::ppc_vsx_xvcmpgedp_p, llvm::Intrinsic::ppc_vsx_xvcmpgesp,   llvm::Intrinsic::ppc_vsx_xvcmpgesp_p, llvm::Intrinsic::ppc_vsx_xvcmpgtdp, llvm::Intrinsic::ppc_vsx_xvcmpgtdp_p, llvm::Intrinsic::ppc_vsx_xvcmpgtsp,   llvm::Intrinsic::ppc_vsx_xvcmpgtsp_p, llvm::Intrinsic::ppc_vsx_xvcvdpsp, llvm::Intrinsic::ppc_vsx_xvcvdpsxws, llvm::Intrinsic::ppc_vsx_xvcvdpuxws,   llvm::Intrinsic::ppc_vsx_xvcvhpsp, llvm::Intrinsic::ppc_vsx_xvcvspdp, llvm::Intrinsic::ppc_vsx_xvcvsphp, llvm::Intrinsic::ppc_vsx_xvcvsxdsp,   llvm::Intrinsic::ppc_vsx_xvcvsxwdp, llvm::Intrinsic::ppc_vsx_xvcvuxdsp, llvm::Intrinsic::ppc_vsx_xvcvuxwdp, llvm::Intrinsic::ppc_vsx_xvdivdp,   llvm::Intrinsic::ppc_vsx_xvdivsp, llvm::Intrinsic::ppc_vsx_xviexpdp, llvm::Intrinsic::ppc_vsx_xviexpsp, llvm::Intrinsic::ppc_vsx_xvmaxdp,   llvm::Intrinsic::ppc_vsx_xvmaxsp, llvm::Intrinsic::ppc_vsx_xvmindp, llvm::Intrinsic::ppc_vsx_xvminsp, llvm::Intrinsic::ppc_vsx_xvrdpip,   llvm::Intrinsic::ppc_vsx_xvredp, llvm::Intrinsic::ppc_vsx_xvresp, llvm::Intrinsic::ppc_vsx_xvrspip, llvm::Intrinsic::ppc_vsx_xvrsqrtedp,   llvm::Intrinsic::ppc_vsx_xvrsqrtesp, llvm::Intrinsic::ppc_vsx_xvtstdcdp, llvm::Intrinsic::ppc_vsx_xvtstdcsp, llvm::Intrinsic::ppc_vsx_xvxexpdp,   llvm::Intrinsic::ppc_vsx_xvxexpsp, llvm::Intrinsic::ppc_vsx_xvxsigdp, llvm::Intrinsic::ppc_vsx_xvxsigsp, llvm::Intrinsic::ppc_vsx_xxextractuw,   llvm::Intrinsic::ppc_vsx_xxinsertw, llvm::Intrinsic::ppc_vsx_xxleqv, llvm::Intrinsic::r600_cube, llvm::Intrinsic::r600_ddx,   llvm::Intrinsic::r600_ddy, llvm::Intrinsic::r600_dot4, llvm::Intrinsic::r600_group_barrier, llvm::Intrinsic::r600_implicitarg_ptr,   llvm::Intrinsic::r600_kill, llvm::Intrinsic::r600_rat_store_typed, llvm::Intrinsic::r600_read_global_size_x, llvm::Intrinsic::r600_read_global_size_y,   llvm::Intrinsic::r600_read_global_size_z, llvm::Intrinsic::r600_read_local_size_x, llvm::Intrinsic::r600_read_local_size_y, llvm::Intrinsic::r600_read_local_size_z,   llvm::Intrinsic::r600_read_ngroups_x, llvm::Intrinsic::r600_read_ngroups_y, llvm::Intrinsic::r600_read_ngroups_z, llvm::Intrinsic::r600_read_tgid_x,   llvm::Intrinsic::r600_read_tgid_y, llvm::Intrinsic::r600_read_tgid_z, llvm::Intrinsic::r600_read_tidig_x, llvm::Intrinsic::r600_read_tidig_y,   llvm::Intrinsic::r600_read_tidig_z, llvm::Intrinsic::r600_recipsqrt_clamped, llvm::Intrinsic::r600_recipsqrt_ieee, llvm::Intrinsic::r600_store_stream_output,   llvm::Intrinsic::r600_store_swizzle, llvm::Intrinsic::r600_tex, llvm::Intrinsic::r600_texc, llvm::Intrinsic::r600_txb,   llvm::Intrinsic::r600_txbc, llvm::Intrinsic::r600_txf, llvm::Intrinsic::r600_txl, llvm::Intrinsic::r600_txlc,   llvm::Intrinsic::r600_txq, llvm::Intrinsic::riscv_masked_atomicrmw_add_i32, llvm::Intrinsic::riscv_masked_atomicrmw_max_i32, llvm::Intrinsic::riscv_masked_atomicrmw_min_i32,   llvm::Intrinsic::riscv_masked_atomicrmw_nand_i32, llvm::Intrinsic::riscv_masked_atomicrmw_sub_i32, llvm::Intrinsic::riscv_masked_atomicrmw_umax_i32, llvm::Intrinsic::riscv_masked_atomicrmw_umin_i32,   llvm::Intrinsic::riscv_masked_atomicrmw_xchg_i32, llvm::Intrinsic::riscv_masked_cmpxchg_i32, llvm::Intrinsic::s390_efpc, llvm::Intrinsic::s390_etnd,   llvm::Intrinsic::s390_lcbb, llvm::Intrinsic::s390_ntstg, llvm::Intrinsic::s390_ppa_txassist, llvm::Intrinsic::s390_sfpc,   llvm::Intrinsic::s390_tabort, llvm::Intrinsic::s390_tbegin, llvm::Intrinsic::s390_tbegin_nofloat, llvm::Intrinsic::s390_tbeginc,   llvm::Intrinsic::s390_tdc, llvm::Intrinsic::s390_tend, llvm::Intrinsic::s390_vaccb, llvm::Intrinsic::s390_vacccq,   llvm::Intrinsic::s390_vaccf, llvm::Intrinsic::s390_vaccg, llvm::Intrinsic::s390_vacch, llvm::Intrinsic::s390_vaccq,   llvm::Intrinsic::s390_vacq, llvm::Intrinsic::s390_vaq, llvm::Intrinsic::s390_vavgb, llvm::Intrinsic::s390_vavgf,   llvm::Intrinsic::s390_vavgg, llvm::Intrinsic::s390_vavgh, llvm::Intrinsic::s390_vavglb, llvm::Intrinsic::s390_vavglf,   llvm::Intrinsic::s390_vavglg, llvm::Intrinsic::s390_vavglh, llvm::Intrinsic::s390_vbperm, llvm::Intrinsic::s390_vceqbs,   llvm::Intrinsic::s390_vceqfs, llvm::Intrinsic::s390_vceqgs, llvm::Intrinsic::s390_vceqhs, llvm::Intrinsic::s390_vchbs,   llvm::Intrinsic::s390_vchfs, llvm::Intrinsic::s390_vchgs, llvm::Intrinsic::s390_vchhs, llvm::Intrinsic::s390_vchlbs,   llvm::Intrinsic::s390_vchlfs, llvm::Intrinsic::s390_vchlgs, llvm::Intrinsic::s390_vchlhs, llvm::Intrinsic::s390_vcksm,   llvm::Intrinsic::s390_verimb, llvm::Intrinsic::s390_verimf, llvm::Intrinsic::s390_verimg, llvm::Intrinsic::s390_verimh,   llvm::Intrinsic::s390_verllb, llvm::Intrinsic::s390_verllf, llvm::Intrinsic::s390_verllg, llvm::Intrinsic::s390_verllh,   llvm::Intrinsic::s390_verllvb, llvm::Intrinsic::s390_verllvf, llvm::Intrinsic::s390_verllvg, llvm::Intrinsic::s390_verllvh,   llvm::Intrinsic::s390_vfaeb, llvm::Intrinsic::s390_vfaebs, llvm::Intrinsic::s390_vfaef, llvm::Intrinsic::s390_vfaefs,   llvm::Intrinsic::s390_vfaeh, llvm::Intrinsic::s390_vfaehs, llvm::Intrinsic::s390_vfaezb, llvm::Intrinsic::s390_vfaezbs,   llvm::Intrinsic::s390_vfaezf, llvm::Intrinsic::s390_vfaezfs, llvm::Intrinsic::s390_vfaezh, llvm::Intrinsic::s390_vfaezhs,   llvm::Intrinsic::s390_vfcedbs, llvm::Intrinsic::s390_vfcesbs, llvm::Intrinsic::s390_vfchdbs, llvm::Intrinsic::s390_vfchedbs,   llvm::Intrinsic::s390_vfchesbs, llvm::Intrinsic::s390_vfchsbs, llvm::Intrinsic::s390_vfeeb, llvm::Intrinsic::s390_vfeebs,   llvm::Intrinsic::s390_vfeef, llvm::Intrinsic::s390_vfeefs, llvm::Intrinsic::s390_vfeeh, llvm::Intrinsic::s390_vfeehs,   llvm::Intrinsic::s390_vfeezb, llvm::Intrinsic::s390_vfeezbs, llvm::Intrinsic::s390_vfeezf, llvm::Intrinsic::s390_vfeezfs,   llvm::Intrinsic::s390_vfeezh, llvm::Intrinsic::s390_vfeezhs, llvm::Intrinsic::s390_vfeneb, llvm::Intrinsic::s390_vfenebs,   llvm::Intrinsic::s390_vfenef, llvm::Intrinsic::s390_vfenefs, llvm::Intrinsic::s390_vfeneh, llvm::Intrinsic::s390_vfenehs,   llvm::Intrinsic::s390_vfenezb, llvm::Intrinsic::s390_vfenezbs, llvm::Intrinsic::s390_vfenezf, llvm::Intrinsic::s390_vfenezfs,   llvm::Intrinsic::s390_vfenezh, llvm::Intrinsic::s390_vfenezhs, llvm::Intrinsic::s390_vfidb, llvm::Intrinsic::s390_vfisb,   llvm::Intrinsic::s390_vfmaxdb, llvm::Intrinsic::s390_vfmaxsb, llvm::Intrinsic::s390_vfmindb, llvm::Intrinsic::s390_vfminsb,   llvm::Intrinsic::s390_vftcidb, llvm::Intrinsic::s390_vftcisb, llvm::Intrinsic::s390_vgfmab, llvm::Intrinsic::s390_vgfmaf,   llvm::Intrinsic::s390_vgfmag, llvm::Intrinsic::s390_vgfmah, llvm::Intrinsic::s390_vgfmb, llvm::Intrinsic::s390_vgfmf,   llvm::Intrinsic::s390_vgfmg, llvm::Intrinsic::s390_vgfmh, llvm::Intrinsic::s390_vistrb, llvm::Intrinsic::s390_vistrbs,   llvm::Intrinsic::s390_vistrf, llvm::Intrinsic::s390_vistrfs, llvm::Intrinsic::s390_vistrh, llvm::Intrinsic::s390_vistrhs,   llvm::Intrinsic::s390_vlbb, llvm::Intrinsic::s390_vll, llvm::Intrinsic::s390_vlrl, llvm::Intrinsic::s390_vmaeb,   llvm::Intrinsic::s390_vmaef, llvm::Intrinsic::s390_vmaeh, llvm::Intrinsic::s390_vmahb, llvm::Intrinsic::s390_vmahf,   llvm::Intrinsic::s390_vmahh, llvm::Intrinsic::s390_vmaleb, llvm::Intrinsic::s390_vmalef, llvm::Intrinsic::s390_vmaleh,   llvm::Intrinsic::s390_vmalhb, llvm::Intrinsic::s390_vmalhf, llvm::Intrinsic::s390_vmalhh, llvm::Intrinsic::s390_vmalob,   llvm::Intrinsic::s390_vmalof, llvm::Intrinsic::s390_vmaloh, llvm::Intrinsic::s390_vmaob, llvm::Intrinsic::s390_vmaof,   llvm::Intrinsic::s390_vmaoh, llvm::Intrinsic::s390_vmeb, llvm::Intrinsic::s390_vmef, llvm::Intrinsic::s390_vmeh,   llvm::Intrinsic::s390_vmhb, llvm::Intrinsic::s390_vmhf, llvm::Intrinsic::s390_vmhh, llvm::Intrinsic::s390_vmleb,   llvm::Intrinsic::s390_vmlef, llvm::Intrinsic::s390_vmleh, llvm::Intrinsic::s390_vmlhb, llvm::Intrinsic::s390_vmlhf,   llvm::Intrinsic::s390_vmlhh, llvm::Intrinsic::s390_vmlob, llvm::Intrinsic::s390_vmlof, llvm::Intrinsic::s390_vmloh,   llvm::Intrinsic::s390_vmob, llvm::Intrinsic::s390_vmof, llvm::Intrinsic::s390_vmoh, llvm::Intrinsic::s390_vmslg,   llvm::Intrinsic::s390_vpdi, llvm::Intrinsic::s390_vperm, llvm::Intrinsic::s390_vpklsf, llvm::Intrinsic::s390_vpklsfs,   llvm::Intrinsic::s390_vpklsg, llvm::Intrinsic::s390_vpklsgs, llvm::Intrinsic::s390_vpklsh, llvm::Intrinsic::s390_vpklshs,   llvm::Intrinsic::s390_vpksf, llvm::Intrinsic::s390_vpksfs, llvm::Intrinsic::s390_vpksg, llvm::Intrinsic::s390_vpksgs,   llvm::Intrinsic::s390_vpksh, llvm::Intrinsic::s390_vpkshs, llvm::Intrinsic::s390_vsbcbiq, llvm::Intrinsic::s390_vsbiq,   llvm::Intrinsic::s390_vscbib, llvm::Intrinsic::s390_vscbif, llvm::Intrinsic::s390_vscbig, llvm::Intrinsic::s390_vscbih,   llvm::Intrinsic::s390_vscbiq, llvm::Intrinsic::s390_vsl, llvm::Intrinsic::s390_vslb, llvm::Intrinsic::s390_vsldb,   llvm::Intrinsic::s390_vsq, llvm::Intrinsic::s390_vsra, llvm::Intrinsic::s390_vsrab, llvm::Intrinsic::s390_vsrl,   llvm::Intrinsic::s390_vsrlb, llvm::Intrinsic::s390_vstl, llvm::Intrinsic::s390_vstrcb, llvm::Intrinsic::s390_vstrcbs,   llvm::Intrinsic::s390_vstrcf, llvm::Intrinsic::s390_vstrcfs, llvm::Intrinsic::s390_vstrch, llvm::Intrinsic::s390_vstrchs,   llvm::Intrinsic::s390_vstrczb, llvm::Intrinsic::s390_vstrczbs, llvm::Intrinsic::s390_vstrczf, llvm::Intrinsic::s390_vstrczfs,   llvm::Intrinsic::s390_vstrczh, llvm::Intrinsic::s390_vstrczhs, llvm::Intrinsic::s390_vstrl, llvm::Intrinsic::s390_vsumb,   llvm::Intrinsic::s390_vsumgf, llvm::Intrinsic::s390_vsumgh, llvm::Intrinsic::s390_vsumh, llvm::Intrinsic::s390_vsumqf,   llvm::Intrinsic::s390_vsumqg, llvm::Intrinsic::s390_vtm, llvm::Intrinsic::s390_vuphb, llvm::Intrinsic::s390_vuphf,   llvm::Intrinsic::s390_vuphh, llvm::Intrinsic::s390_vuplb, llvm::Intrinsic::s390_vuplf, llvm::Intrinsic::s390_vuplhb,   llvm::Intrinsic::s390_vuplhf, llvm::Intrinsic::s390_vuplhh, llvm::Intrinsic::s390_vuplhw, llvm::Intrinsic::s390_vupllb,   llvm::Intrinsic::s390_vupllf, llvm::Intrinsic::s390_vupllh, llvm::Intrinsic::wasm_alltrue, llvm::Intrinsic::wasm_anytrue,   llvm::Intrinsic::wasm_atomic_notify, llvm::Intrinsic::wasm_atomic_wait_i32, llvm::Intrinsic::wasm_atomic_wait_i64, llvm::Intrinsic::wasm_bitselect,   llvm::Intrinsic::wasm_catch, llvm::Intrinsic::wasm_get_ehselector, llvm::Intrinsic::wasm_get_exception, llvm::Intrinsic::wasm_landingpad_index,   llvm::Intrinsic::wasm_lsda, llvm::Intrinsic::wasm_memory_grow, llvm::Intrinsic::wasm_memory_size, llvm::Intrinsic::wasm_rethrow,   llvm::Intrinsic::wasm_sub_saturate_signed, llvm::Intrinsic::wasm_sub_saturate_unsigned, llvm::Intrinsic::wasm_throw, llvm::Intrinsic::wasm_trunc_saturate_signed,   llvm::Intrinsic::wasm_trunc_saturate_unsigned, llvm::Intrinsic::x86_3dnow_pavgusb, llvm::Intrinsic::x86_3dnow_pf2id, llvm::Intrinsic::x86_3dnow_pfacc,   llvm::Intrinsic::x86_3dnow_pfadd, llvm::Intrinsic::x86_3dnow_pfcmpeq, llvm::Intrinsic::x86_3dnow_pfcmpge, llvm::Intrinsic::x86_3dnow_pfcmpgt,   llvm::Intrinsic::x86_3dnow_pfmax, llvm::Intrinsic::x86_3dnow_pfmin, llvm::Intrinsic::x86_3dnow_pfmul, llvm::Intrinsic::x86_3dnow_pfrcp,   llvm::Intrinsic::x86_3dnow_pfrcpit1, llvm::Intrinsic::x86_3dnow_pfrcpit2, llvm::Intrinsic::x86_3dnow_pfrsqit1, llvm::Intrinsic::x86_3dnow_pfrsqrt,   llvm::Intrinsic::x86_3dnow_pfsub, llvm::Intrinsic::x86_3dnow_pfsubr, llvm::Intrinsic::x86_3dnow_pi2fd, llvm::Intrinsic::x86_3dnow_pmulhrw,   llvm::Intrinsic::x86_3dnowa_pf2iw, llvm::Intrinsic::x86_3dnowa_pfnacc, llvm::Intrinsic::x86_3dnowa_pfpnacc, llvm::Intrinsic::x86_3dnowa_pi2fw,   llvm::Intrinsic::x86_3dnowa_pswapd, llvm::Intrinsic::x86_addcarry_32, llvm::Intrinsic::x86_addcarry_64, llvm::Intrinsic::x86_aesni_aesdec,   llvm::Intrinsic::x86_aesni_aesdec_256, llvm::Intrinsic::x86_aesni_aesdec_512, llvm::Intrinsic::x86_aesni_aesdeclast, llvm::Intrinsic::x86_aesni_aesdeclast_256,   llvm::Intrinsic::x86_aesni_aesdeclast_512, llvm::Intrinsic::x86_aesni_aesenc, llvm::Intrinsic::x86_aesni_aesenc_256, llvm::Intrinsic::x86_aesni_aesenc_512,   llvm::Intrinsic::x86_aesni_aesenclast, llvm::Intrinsic::x86_aesni_aesenclast_256, llvm::Intrinsic::x86_aesni_aesenclast_512, llvm::Intrinsic::x86_aesni_aesimc,   llvm::Intrinsic::x86_aesni_aeskeygenassist, llvm::Intrinsic::x86_avx_addsub_pd_256, llvm::Intrinsic::x86_avx_addsub_ps_256, llvm::Intrinsic::x86_avx_blendv_pd_256,   llvm::Intrinsic::x86_avx_blendv_ps_256, llvm::Intrinsic::x86_avx_cmp_pd_256, llvm::Intrinsic::x86_avx_cmp_ps_256, llvm::Intrinsic::x86_avx_cvt_pd2_ps_256,   llvm::Intrinsic::x86_avx_cvt_pd2dq_256, llvm::Intrinsic::x86_avx_cvt_ps2dq_256, llvm::Intrinsic::x86_avx_cvtt_pd2dq_256, llvm::Intrinsic::x86_avx_cvtt_ps2dq_256,   llvm::Intrinsic::x86_avx_dp_ps_256, llvm::Intrinsic::x86_avx_hadd_pd_256, llvm::Intrinsic::x86_avx_hadd_ps_256, llvm::Intrinsic::x86_avx_hsub_pd_256,   llvm::Intrinsic::x86_avx_hsub_ps_256, llvm::Intrinsic::x86_avx_ldu_dq_256, llvm::Intrinsic::x86_avx_maskload_pd, llvm::Intrinsic::x86_avx_maskload_pd_256,   llvm::Intrinsic::x86_avx_maskload_ps, llvm::Intrinsic::x86_avx_maskload_ps_256, llvm::Intrinsic::x86_avx_maskstore_pd, llvm::Intrinsic::x86_avx_maskstore_pd_256,   llvm::Intrinsic::x86_avx_maskstore_ps, llvm::Intrinsic::x86_avx_maskstore_ps_256, llvm::Intrinsic::x86_avx_max_pd_256, llvm::Intrinsic::x86_avx_max_ps_256,   llvm::Intrinsic::x86_avx_min_pd_256, llvm::Intrinsic::x86_avx_min_ps_256, llvm::Intrinsic::x86_avx_movmsk_pd_256, llvm::Intrinsic::x86_avx_movmsk_ps_256,   llvm::Intrinsic::x86_avx_ptestc_256, llvm::Intrinsic::x86_avx_ptestnzc_256, llvm::Intrinsic::x86_avx_ptestz_256, llvm::Intrinsic::x86_avx_rcp_ps_256,   llvm::Intrinsic::x86_avx_round_pd_256, llvm::Intrinsic::x86_avx_round_ps_256, llvm::Intrinsic::x86_avx_rsqrt_ps_256, llvm::Intrinsic::x86_avx_vpermilvar_pd,   llvm::Intrinsic::x86_avx_vpermilvar_pd_256, llvm::Intrinsic::x86_avx_vpermilvar_ps, llvm::Intrinsic::x86_avx_vpermilvar_ps_256, llvm::Intrinsic::x86_avx_vtestc_pd,   llvm::Intrinsic::x86_avx_vtestc_pd_256, llvm::Intrinsic::x86_avx_vtestc_ps, llvm::Intrinsic::x86_avx_vtestc_ps_256, llvm::Intrinsic::x86_avx_vtestnzc_pd,   llvm::Intrinsic::x86_avx_vtestnzc_pd_256, llvm::Intrinsic::x86_avx_vtestnzc_ps, llvm::Intrinsic::x86_avx_vtestnzc_ps_256, llvm::Intrinsic::x86_avx_vtestz_pd,   llvm::Intrinsic::x86_avx_vtestz_pd_256, llvm::Intrinsic::x86_avx_vtestz_ps, llvm::Intrinsic::x86_avx_vtestz_ps_256, llvm::Intrinsic::x86_avx_vzeroall,   llvm::Intrinsic::x86_avx_vzeroupper, llvm::Intrinsic::x86_avx2_gather_d_d, llvm::Intrinsic::x86_avx2_gather_d_d_256, llvm::Intrinsic::x86_avx2_gather_d_pd,   llvm::Intrinsic::x86_avx2_gather_d_pd_256, llvm::Intrinsic::x86_avx2_gather_d_ps, llvm::Intrinsic::x86_avx2_gather_d_ps_256, llvm::Intrinsic::x86_avx2_gather_d_q,   llvm::Intrinsic::x86_avx2_gather_d_q_256, llvm::Intrinsic::x86_avx2_gather_q_d, llvm::Intrinsic::x86_avx2_gather_q_d_256, llvm::Intrinsic::x86_avx2_gather_q_pd,   llvm::Intrinsic::x86_avx2_gather_q_pd_256, llvm::Intrinsic::x86_avx2_gather_q_ps, llvm::Intrinsic::x86_avx2_gather_q_ps_256, llvm::Intrinsic::x86_avx2_gather_q_q,   llvm::Intrinsic::x86_avx2_gather_q_q_256, llvm::Intrinsic::x86_avx2_maskload_d, llvm::Intrinsic::x86_avx2_maskload_d_256, llvm::Intrinsic::x86_avx2_maskload_q,   llvm::Intrinsic::x86_avx2_maskload_q_256, llvm::Intrinsic::x86_avx2_maskstore_d, llvm::Intrinsic::x86_avx2_maskstore_d_256, llvm::Intrinsic::x86_avx2_maskstore_q,   llvm::Intrinsic::x86_avx2_maskstore_q_256, llvm::Intrinsic::x86_avx2_mpsadbw, llvm::Intrinsic::x86_avx2_packssdw, llvm::Intrinsic::x86_avx2_packsswb,   llvm::Intrinsic::x86_avx2_packusdw, llvm::Intrinsic::x86_avx2_packuswb, llvm::Intrinsic::x86_avx2_pblendvb, llvm::Intrinsic::x86_avx2_permd,   llvm::Intrinsic::x86_avx2_permps, llvm::Intrinsic::x86_avx2_phadd_d, llvm::Intrinsic::x86_avx2_phadd_sw, llvm::Intrinsic::x86_avx2_phadd_w,   llvm::Intrinsic::x86_avx2_phsub_d, llvm::Intrinsic::x86_avx2_phsub_sw, llvm::Intrinsic::x86_avx2_phsub_w, llvm::Intrinsic::x86_avx2_pmadd_ub_sw,   llvm::Intrinsic::x86_avx2_pmadd_wd, llvm::Intrinsic::x86_avx2_pmovmskb, llvm::Intrinsic::x86_avx2_pmul_hr_sw, llvm::Intrinsic::x86_avx2_pmulh_w,   llvm::Intrinsic::x86_avx2_pmulhu_w, llvm::Intrinsic::x86_avx2_psad_bw, llvm::Intrinsic::x86_avx2_pshuf_b, llvm::Intrinsic::x86_avx2_psign_b,   llvm::Intrinsic::x86_avx2_psign_d, llvm::Intrinsic::x86_avx2_psign_w, llvm::Intrinsic::x86_avx2_psll_d, llvm::Intrinsic::x86_avx2_psll_q,   llvm::Intrinsic::x86_avx2_psll_w, llvm::Intrinsic::x86_avx2_pslli_d, llvm::Intrinsic::x86_avx2_pslli_q, llvm::Intrinsic::x86_avx2_pslli_w,   llvm::Intrinsic::x86_avx2_psllv_d, llvm::Intrinsic::x86_avx2_psllv_d_256, llvm::Intrinsic::x86_avx2_psllv_q, llvm::Intrinsic::x86_avx2_psllv_q_256,   llvm::Intrinsic::x86_avx2_psra_d, llvm::Intrinsic::x86_avx2_psra_w, llvm::Intrinsic::x86_avx2_psrai_d, llvm::Intrinsic::x86_avx2_psrai_w,   llvm::Intrinsic::x86_avx2_psrav_d, llvm::Intrinsic::x86_avx2_psrav_d_256, llvm::Intrinsic::x86_avx2_psrl_d, llvm::Intrinsic::x86_avx2_psrl_q,   llvm::Intrinsic::x86_avx2_psrl_w, llvm::Intrinsic::x86_avx2_psrli_d, llvm::Intrinsic::x86_avx2_psrli_q, llvm::Intrinsic::x86_avx2_psrli_w,   llvm::Intrinsic::x86_avx2_psrlv_d, llvm::Intrinsic::x86_avx2_psrlv_d_256, llvm::Intrinsic::x86_avx2_psrlv_q, llvm::Intrinsic::x86_avx2_psrlv_q_256,   llvm::Intrinsic::x86_avx512_add_pd_512, llvm::Intrinsic::x86_avx512_add_ps_512, llvm::Intrinsic::x86_avx512_broadcastmb_128, llvm::Intrinsic::x86_avx512_broadcastmb_256,   llvm::Intrinsic::x86_avx512_broadcastmb_512, llvm::Intrinsic::x86_avx512_broadcastmw_128, llvm::Intrinsic::x86_avx512_broadcastmw_256, llvm::Intrinsic::x86_avx512_broadcastmw_512,   llvm::Intrinsic::x86_avx512_cmp_pd_128, llvm::Intrinsic::x86_avx512_cmp_pd_256, llvm::Intrinsic::x86_avx512_cmp_pd_512, llvm::Intrinsic::x86_avx512_cmp_ps_128,   llvm::Intrinsic::x86_avx512_cmp_ps_256, llvm::Intrinsic::x86_avx512_cmp_ps_512, llvm::Intrinsic::x86_avx512_cvtsi2sd64, llvm::Intrinsic::x86_avx512_cvtsi2ss32,   llvm::Intrinsic::x86_avx512_cvtsi2ss64, llvm::Intrinsic::x86_avx512_cvttsd2si, llvm::Intrinsic::x86_avx512_cvttsd2si64, llvm::Intrinsic::x86_avx512_cvttsd2usi,   llvm::Intrinsic::x86_avx512_cvttsd2usi64, llvm::Intrinsic::x86_avx512_cvttss2si, llvm::Intrinsic::x86_avx512_cvttss2si64, llvm::Intrinsic::x86_avx512_cvttss2usi,   llvm::Intrinsic::x86_avx512_cvttss2usi64, llvm::Intrinsic::x86_avx512_cvtusi2ss, llvm::Intrinsic::x86_avx512_cvtusi642sd, llvm::Intrinsic::x86_avx512_cvtusi642ss,   llvm::Intrinsic::x86_avx512_dbpsadbw_128, llvm::Intrinsic::x86_avx512_dbpsadbw_256, llvm::Intrinsic::x86_avx512_dbpsadbw_512, llvm::Intrinsic::x86_avx512_div_pd_512,   llvm::Intrinsic::x86_avx512_div_ps_512, llvm::Intrinsic::x86_avx512_exp2_pd, llvm::Intrinsic::x86_avx512_exp2_ps, llvm::Intrinsic::x86_avx512_fpclass_pd_128,   llvm::Intrinsic::x86_avx512_fpclass_pd_256, llvm::Intrinsic::x86_avx512_fpclass_pd_512, llvm::Intrinsic::x86_avx512_fpclass_ps_128, llvm::Intrinsic::x86_avx512_fpclass_ps_256,   llvm::Intrinsic::x86_avx512_fpclass_ps_512, llvm::Intrinsic::x86_avx512_gather_dpd_512, llvm::Intrinsic::x86_avx512_gather_dpi_512, llvm::Intrinsic::x86_avx512_gather_dpq_512,   llvm::Intrinsic::x86_avx512_gather_dps_512, llvm::Intrinsic::x86_avx512_gather_qpd_512, llvm::Intrinsic::x86_avx512_gather_qpi_512, llvm::Intrinsic::x86_avx512_gather_qpq_512,   llvm::Intrinsic::x86_avx512_gather_qps_512, llvm::Intrinsic::x86_avx512_gather3div2_df, llvm::Intrinsic::x86_avx512_gather3div2_di, llvm::Intrinsic::x86_avx512_gather3div4_df,   llvm::Intrinsic::x86_avx512_gather3div4_di, llvm::Intrinsic::x86_avx512_gather3div4_sf, llvm::Intrinsic::x86_avx512_gather3div4_si, llvm::Intrinsic::x86_avx512_gather3div8_sf,   llvm::Intrinsic::x86_avx512_gather3div8_si, llvm::Intrinsic::x86_avx512_gather3siv2_df, llvm::Intrinsic::x86_avx512_gather3siv2_di, llvm::Intrinsic::x86_avx512_gather3siv4_df,   llvm::Intrinsic::x86_avx512_gather3siv4_di, llvm::Intrinsic::x86_avx512_gather3siv4_sf, llvm::Intrinsic::x86_avx512_gather3siv4_si, llvm::Intrinsic::x86_avx512_gather3siv8_sf,   llvm::Intrinsic::x86_avx512_gather3siv8_si, llvm::Intrinsic::x86_avx512_gatherpf_dpd_512, llvm::Intrinsic::x86_avx512_gatherpf_dps_512, llvm::Intrinsic::x86_avx512_gatherpf_qpd_512,   llvm::Intrinsic::x86_avx512_gatherpf_qps_512, llvm::Intrinsic::x86_avx512_kadd_b, llvm::Intrinsic::x86_avx512_kadd_d, llvm::Intrinsic::x86_avx512_kadd_q,   llvm::Intrinsic::x86_avx512_kadd_w, llvm::Intrinsic::x86_avx512_ktestc_b, llvm::Intrinsic::x86_avx512_ktestc_d, llvm::Intrinsic::x86_avx512_ktestc_q,   llvm::Intrinsic::x86_avx512_ktestc_w, llvm::Intrinsic::x86_avx512_ktestz_b, llvm::Intrinsic::x86_avx512_ktestz_d, llvm::Intrinsic::x86_avx512_ktestz_q,   llvm::Intrinsic::x86_avx512_ktestz_w, llvm::Intrinsic::x86_avx512_mask_add_sd_round, llvm::Intrinsic::x86_avx512_mask_add_ss_round, llvm::Intrinsic::x86_avx512_mask_cmp_sd,   llvm::Intrinsic::x86_avx512_mask_cmp_ss, llvm::Intrinsic::x86_avx512_mask_compress_b_128, llvm::Intrinsic::x86_avx512_mask_compress_b_256, llvm::Intrinsic::x86_avx512_mask_compress_b_512,   llvm::Intrinsic::x86_avx512_mask_compress_d_128, llvm::Intrinsic::x86_avx512_mask_compress_d_256, llvm::Intrinsic::x86_avx512_mask_compress_d_512, llvm::Intrinsic::x86_avx512_mask_compress_pd_128,   llvm::Intrinsic::x86_avx512_mask_compress_pd_256, llvm::Intrinsic::x86_avx512_mask_compress_pd_512, llvm::Intrinsic::x86_avx512_mask_compress_ps_128, llvm::Intrinsic::x86_avx512_mask_compress_ps_256,   llvm::Intrinsic::x86_avx512_mask_compress_ps_512, llvm::Intrinsic::x86_avx512_mask_compress_q_128, llvm::Intrinsic::x86_avx512_mask_compress_q_256, llvm::Intrinsic::x86_avx512_mask_compress_q_512,   llvm::Intrinsic::x86_avx512_mask_compress_w_128, llvm::Intrinsic::x86_avx512_mask_compress_w_256, llvm::Intrinsic::x86_avx512_mask_compress_w_512, llvm::Intrinsic::x86_avx512_mask_conflict_d_128,   llvm::Intrinsic::x86_avx512_mask_conflict_d_256, llvm::Intrinsic::x86_avx512_mask_conflict_d_512, llvm::Intrinsic::x86_avx512_mask_conflict_q_128, llvm::Intrinsic::x86_avx512_mask_conflict_q_256,   llvm::Intrinsic::x86_avx512_mask_conflict_q_512, llvm::Intrinsic::x86_avx512_mask_cvtdq2ps_512, llvm::Intrinsic::x86_avx512_mask_cvtpd2dq_128, llvm::Intrinsic::x86_avx512_mask_cvtpd2dq_512,   llvm::Intrinsic::x86_avx512_mask_cvtpd2ps, llvm::Intrinsic::x86_avx512_mask_cvtpd2ps_512, llvm::Intrinsic::x86_avx512_mask_cvtpd2qq_128, llvm::Intrinsic::x86_avx512_mask_cvtpd2qq_256,   llvm::Intrinsic::x86_avx512_mask_cvtpd2qq_512, llvm::Intrinsic::x86_avx512_mask_cvtpd2udq_128, llvm::Intrinsic::x86_avx512_mask_cvtpd2udq_256, llvm::Intrinsic::x86_avx512_mask_cvtpd2udq_512,   llvm::Intrinsic::x86_avx512_mask_cvtpd2uqq_128, llvm::Intrinsic::x86_avx512_mask_cvtpd2uqq_256, llvm::Intrinsic::x86_avx512_mask_cvtpd2uqq_512, llvm::Intrinsic::x86_avx512_mask_cvtps2dq_128,   llvm::Intrinsic::x86_avx512_mask_cvtps2dq_256, llvm::Intrinsic::x86_avx512_mask_cvtps2dq_512, llvm::Intrinsic::x86_avx512_mask_cvtps2pd_512, llvm::Intrinsic::x86_avx512_mask_cvtps2qq_128,   llvm::Intrinsic::x86_avx512_mask_cvtps2qq_256, llvm::Intrinsic::x86_avx512_mask_cvtps2qq_512, llvm::Intrinsic::x86_avx512_mask_cvtps2udq_128, llvm::Intrinsic::x86_avx512_mask_cvtps2udq_256,   llvm::Intrinsic::x86_avx512_mask_cvtps2udq_512, llvm::Intrinsic::x86_avx512_mask_cvtps2uqq_128, llvm::Intrinsic::x86_avx512_mask_cvtps2uqq_256, llvm::Intrinsic::x86_avx512_mask_cvtps2uqq_512,   llvm::Intrinsic::x86_avx512_mask_cvtqq2pd_512, llvm::Intrinsic::x86_avx512_mask_cvtqq2ps_128, llvm::Intrinsic::x86_avx512_mask_cvtqq2ps_256, llvm::Intrinsic::x86_avx512_mask_cvtqq2ps_512,   llvm::Intrinsic::x86_avx512_mask_cvtsd2ss_round, llvm::Intrinsic::x86_avx512_mask_cvtss2sd_round, llvm::Intrinsic::x86_avx512_mask_cvttpd2dq_128, llvm::Intrinsic::x86_avx512_mask_cvttpd2dq_512,   llvm::Intrinsic::x86_avx512_mask_cvttpd2qq_128, llvm::Intrinsic::x86_avx512_mask_cvttpd2qq_256, llvm::Intrinsic::x86_avx512_mask_cvttpd2qq_512, llvm::Intrinsic::x86_avx512_mask_cvttpd2udq_128,   llvm::Intrinsic::x86_avx512_mask_cvttpd2udq_256, llvm::Intrinsic::x86_avx512_mask_cvttpd2udq_512, llvm::Intrinsic::x86_avx512_mask_cvttpd2uqq_128, llvm::Intrinsic::x86_avx512_mask_cvttpd2uqq_256,   llvm::Intrinsic::x86_avx512_mask_cvttpd2uqq_512, llvm::Intrinsic::x86_avx512_mask_cvttps2dq_512, llvm::Intrinsic::x86_avx512_mask_cvttps2qq_128, llvm::Intrinsic::x86_avx512_mask_cvttps2qq_256,   llvm::Intrinsic::x86_avx512_mask_cvttps2qq_512, llvm::Intrinsic::x86_avx512_mask_cvttps2udq_128, llvm::Intrinsic::x86_avx512_mask_cvttps2udq_256, llvm::Intrinsic::x86_avx512_mask_cvttps2udq_512,   llvm::Intrinsic::x86_avx512_mask_cvttps2uqq_128, llvm::Intrinsic::x86_avx512_mask_cvttps2uqq_256, llvm::Intrinsic::x86_avx512_mask_cvttps2uqq_512, llvm::Intrinsic::x86_avx512_mask_cvtudq2ps_512,   llvm::Intrinsic::x86_avx512_mask_cvtuqq2pd_512, llvm::Intrinsic::x86_avx512_mask_cvtuqq2ps_128, llvm::Intrinsic::x86_avx512_mask_cvtuqq2ps_256, llvm::Intrinsic::x86_avx512_mask_cvtuqq2ps_512,   llvm::Intrinsic::x86_avx512_mask_div_sd_round, llvm::Intrinsic::x86_avx512_mask_div_ss_round, llvm::Intrinsic::x86_avx512_mask_expand_b_128, llvm::Intrinsic::x86_avx512_mask_expand_b_256,   llvm::Intrinsic::x86_avx512_mask_expand_b_512, llvm::Intrinsic::x86_avx512_mask_expand_d_128, llvm::Intrinsic::x86_avx512_mask_expand_d_256, llvm::Intrinsic::x86_avx512_mask_expand_d_512,   llvm::Intrinsic::x86_avx512_mask_expand_pd_128, llvm::Intrinsic::x86_avx512_mask_expand_pd_256, llvm::Intrinsic::x86_avx512_mask_expand_pd_512, llvm::Intrinsic::x86_avx512_mask_expand_ps_128,   llvm::Intrinsic::x86_avx512_mask_expand_ps_256, llvm::Intrinsic::x86_avx512_mask_expand_ps_512, llvm::Intrinsic::x86_avx512_mask_expand_q_128, llvm::Intrinsic::x86_avx512_mask_expand_q_256,   llvm::Intrinsic::x86_avx512_mask_expand_q_512, llvm::Intrinsic::x86_avx512_mask_expand_w_128, llvm::Intrinsic::x86_avx512_mask_expand_w_256, llvm::Intrinsic::x86_avx512_mask_expand_w_512,   llvm::Intrinsic::x86_avx512_mask_fixupimm_pd_128, llvm::Intrinsic::x86_avx512_mask_fixupimm_pd_256, llvm::Intrinsic::x86_avx512_mask_fixupimm_pd_512, llvm::Intrinsic::x86_avx512_mask_fixupimm_ps_128,   llvm::Intrinsic::x86_avx512_mask_fixupimm_ps_256, llvm::Intrinsic::x86_avx512_mask_fixupimm_ps_512, llvm::Intrinsic::x86_avx512_mask_fixupimm_sd, llvm::Intrinsic::x86_avx512_mask_fixupimm_ss,   llvm::Intrinsic::x86_avx512_mask_fpclass_sd, llvm::Intrinsic::x86_avx512_mask_fpclass_ss, llvm::Intrinsic::x86_avx512_mask_gather_dpd_512, llvm::Intrinsic::x86_avx512_mask_gather_dpi_512,   llvm::Intrinsic::x86_avx512_mask_gather_dpq_512, llvm::Intrinsic::x86_avx512_mask_gather_dps_512, llvm::Intrinsic::x86_avx512_mask_gather_qpd_512, llvm::Intrinsic::x86_avx512_mask_gather_qpi_512,   llvm::Intrinsic::x86_avx512_mask_gather_qpq_512, llvm::Intrinsic::x86_avx512_mask_gather_qps_512, llvm::Intrinsic::x86_avx512_mask_gather3div2_df, llvm::Intrinsic::x86_avx512_mask_gather3div2_di,   llvm::Intrinsic::x86_avx512_mask_gather3div4_df, llvm::Intrinsic::x86_avx512_mask_gather3div4_di, llvm::Intrinsic::x86_avx512_mask_gather3div4_sf, llvm::Intrinsic::x86_avx512_mask_gather3div4_si,   llvm::Intrinsic::x86_avx512_mask_gather3div8_sf, llvm::Intrinsic::x86_avx512_mask_gather3div8_si, llvm::Intrinsic::x86_avx512_mask_gather3siv2_df, llvm::Intrinsic::x86_avx512_mask_gather3siv2_di,   llvm::Intrinsic::x86_avx512_mask_gather3siv4_df, llvm::Intrinsic::x86_avx512_mask_gather3siv4_di, llvm::Intrinsic::x86_avx512_mask_gather3siv4_sf, llvm::Intrinsic::x86_avx512_mask_gather3siv4_si,   llvm::Intrinsic::x86_avx512_mask_gather3siv8_sf, llvm::Intrinsic::x86_avx512_mask_gather3siv8_si, llvm::Intrinsic::x86_avx512_mask_getexp_pd_128, llvm::Intrinsic::x86_avx512_mask_getexp_pd_256,   llvm::Intrinsic::x86_avx512_mask_getexp_pd_512, llvm::Intrinsic::x86_avx512_mask_getexp_ps_128, llvm::Intrinsic::x86_avx512_mask_getexp_ps_256, llvm::Intrinsic::x86_avx512_mask_getexp_ps_512,   llvm::Intrinsic::x86_avx512_mask_getexp_sd, llvm::Intrinsic::x86_avx512_mask_getexp_ss, llvm::Intrinsic::x86_avx512_mask_getmant_pd_128, llvm::Intrinsic::x86_avx512_mask_getmant_pd_256,   llvm::Intrinsic::x86_avx512_mask_getmant_pd_512, llvm::Intrinsic::x86_avx512_mask_getmant_ps_128, llvm::Intrinsic::x86_avx512_mask_getmant_ps_256, llvm::Intrinsic::x86_avx512_mask_getmant_ps_512,   llvm::Intrinsic::x86_avx512_mask_getmant_sd, llvm::Intrinsic::x86_avx512_mask_getmant_ss, llvm::Intrinsic::x86_avx512_mask_max_sd_round, llvm::Intrinsic::x86_avx512_mask_max_ss_round,   llvm::Intrinsic::x86_avx512_mask_min_sd_round, llvm::Intrinsic::x86_avx512_mask_min_ss_round, llvm::Intrinsic::x86_avx512_mask_mul_sd_round, llvm::Intrinsic::x86_avx512_mask_mul_ss_round,   llvm::Intrinsic::x86_avx512_mask_pmov_db_128, llvm::Intrinsic::x86_avx512_mask_pmov_db_256, llvm::Intrinsic::x86_avx512_mask_pmov_db_512, llvm::Intrinsic::x86_avx512_mask_pmov_db_mem_128,   llvm::Intrinsic::x86_avx512_mask_pmov_db_mem_256, llvm::Intrinsic::x86_avx512_mask_pmov_db_mem_512, llvm::Intrinsic::x86_avx512_mask_pmov_dw_128, llvm::Intrinsic::x86_avx512_mask_pmov_dw_256,   llvm::Intrinsic::x86_avx512_mask_pmov_dw_512, llvm::Intrinsic::x86_avx512_mask_pmov_dw_mem_128, llvm::Intrinsic::x86_avx512_mask_pmov_dw_mem_256, llvm::Intrinsic::x86_avx512_mask_pmov_dw_mem_512,   llvm::Intrinsic::x86_avx512_mask_pmov_qb_128, llvm::Intrinsic::x86_avx512_mask_pmov_qb_256, llvm::Intrinsic::x86_avx512_mask_pmov_qb_512, llvm::Intrinsic::x86_avx512_mask_pmov_qb_mem_128,   llvm::Intrinsic::x86_avx512_mask_pmov_qb_mem_256, llvm::Intrinsic::x86_avx512_mask_pmov_qb_mem_512, llvm::Intrinsic::x86_avx512_mask_pmov_qd_128, llvm::Intrinsic::x86_avx512_mask_pmov_qd_256,   llvm::Intrinsic::x86_avx512_mask_pmov_qd_512, llvm::Intrinsic::x86_avx512_mask_pmov_qd_mem_128, llvm::Intrinsic::x86_avx512_mask_pmov_qd_mem_256, llvm::Intrinsic::x86_avx512_mask_pmov_qd_mem_512,   llvm::Intrinsic::x86_avx512_mask_pmov_qw_128, llvm::Intrinsic::x86_avx512_mask_pmov_qw_256, llvm::Intrinsic::x86_avx512_mask_pmov_qw_512, llvm::Intrinsic::x86_avx512_mask_pmov_qw_mem_128,   llvm::Intrinsic::x86_avx512_mask_pmov_qw_mem_256, llvm::Intrinsic::x86_avx512_mask_pmov_qw_mem_512, llvm::Intrinsic::x86_avx512_mask_pmov_wb_128, llvm::Intrinsic::x86_avx512_mask_pmov_wb_256,   llvm::Intrinsic::x86_avx512_mask_pmov_wb_512, llvm::Intrinsic::x86_avx512_mask_pmov_wb_mem_128, llvm::Intrinsic::x86_avx512_mask_pmov_wb_mem_256, llvm::Intrinsic::x86_avx512_mask_pmov_wb_mem_512,   llvm::Intrinsic::x86_avx512_mask_pmovs_db_128, llvm::Intrinsic::x86_avx512_mask_pmovs_db_256, llvm::Intrinsic::x86_avx512_mask_pmovs_db_512, llvm::Intrinsic::x86_avx512_mask_pmovs_db_mem_128,   llvm::Intrinsic::x86_avx512_mask_pmovs_db_mem_256, llvm::Intrinsic::x86_avx512_mask_pmovs_db_mem_512, llvm::Intrinsic::x86_avx512_mask_pmovs_dw_128, llvm::Intrinsic::x86_avx512_mask_pmovs_dw_256,   llvm::Intrinsic::x86_avx512_mask_pmovs_dw_512, llvm::Intrinsic::x86_avx512_mask_pmovs_dw_mem_128, llvm::Intrinsic::x86_avx512_mask_pmovs_dw_mem_256, llvm::Intrinsic::x86_avx512_mask_pmovs_dw_mem_512,   llvm::Intrinsic::x86_avx512_mask_pmovs_qb_128, llvm::Intrinsic::x86_avx512_mask_pmovs_qb_256, llvm::Intrinsic::x86_avx512_mask_pmovs_qb_512, llvm::Intrinsic::x86_avx512_mask_pmovs_qb_mem_128,   llvm::Intrinsic::x86_avx512_mask_pmovs_qb_mem_256, llvm::Intrinsic::x86_avx512_mask_pmovs_qb_mem_512, llvm::Intrinsic::x86_avx512_mask_pmovs_qd_128, llvm::Intrinsic::x86_avx512_mask_pmovs_qd_256,   llvm::Intrinsic::x86_avx512_mask_pmovs_qd_512, llvm::Intrinsic::x86_avx512_mask_pmovs_qd_mem_128, llvm::Intrinsic::x86_avx512_mask_pmovs_qd_mem_256, llvm::Intrinsic::x86_avx512_mask_pmovs_qd_mem_512,   llvm::Intrinsic::x86_avx512_mask_pmovs_qw_128, llvm::Intrinsic::x86_avx512_mask_pmovs_qw_256, llvm::Intrinsic::x86_avx512_mask_pmovs_qw_512, llvm::Intrinsic::x86_avx512_mask_pmovs_qw_mem_128,   llvm::Intrinsic::x86_avx512_mask_pmovs_qw_mem_256, llvm::Intrinsic::x86_avx512_mask_pmovs_qw_mem_512, llvm::Intrinsic::x86_avx512_mask_pmovs_wb_128, llvm::Intrinsic::x86_avx512_mask_pmovs_wb_256,   llvm::Intrinsic::x86_avx512_mask_pmovs_wb_512, llvm::Intrinsic::x86_avx512_mask_pmovs_wb_mem_128, llvm::Intrinsic::x86_avx512_mask_pmovs_wb_mem_256, llvm::Intrinsic::x86_avx512_mask_pmovs_wb_mem_512,   llvm::Intrinsic::x86_avx512_mask_pmovus_db_128, llvm::Intrinsic::x86_avx512_mask_pmovus_db_256, llvm::Intrinsic::x86_avx512_mask_pmovus_db_512, llvm::Intrinsic::x86_avx512_mask_pmovus_db_mem_128,   llvm::Intrinsic::x86_avx512_mask_pmovus_db_mem_256, llvm::Intrinsic::x86_avx512_mask_pmovus_db_mem_512, llvm::Intrinsic::x86_avx512_mask_pmovus_dw_128, llvm::Intrinsic::x86_avx512_mask_pmovus_dw_256,   llvm::Intrinsic::x86_avx512_mask_pmovus_dw_512, llvm::Intrinsic::x86_avx512_mask_pmovus_dw_mem_128, llvm::Intrinsic::x86_avx512_mask_pmovus_dw_mem_256, llvm::Intrinsic::x86_avx512_mask_pmovus_dw_mem_512,   llvm::Intrinsic::x86_avx512_mask_pmovus_qb_128, llvm::Intrinsic::x86_avx512_mask_pmovus_qb_256, llvm::Intrinsic::x86_avx512_mask_pmovus_qb_512, llvm::Intrinsic::x86_avx512_mask_pmovus_qb_mem_128,   llvm::Intrinsic::x86_avx512_mask_pmovus_qb_mem_256, llvm::Intrinsic::x86_avx512_mask_pmovus_qb_mem_512, llvm::Intrinsic::x86_avx512_mask_pmovus_qd_128, llvm::Intrinsic::x86_avx512_mask_pmovus_qd_256,   llvm::Intrinsic::x86_avx512_mask_pmovus_qd_512, llvm::Intrinsic::x86_avx512_mask_pmovus_qd_mem_128, llvm::Intrinsic::x86_avx512_mask_pmovus_qd_mem_256, llvm::Intrinsic::x86_avx512_mask_pmovus_qd_mem_512,   llvm::Intrinsic::x86_avx512_mask_pmovus_qw_128, llvm::Intrinsic::x86_avx512_mask_pmovus_qw_256, llvm::Intrinsic::x86_avx512_mask_pmovus_qw_512, llvm::Intrinsic::x86_avx512_mask_pmovus_qw_mem_128,   llvm::Intrinsic::x86_avx512_mask_pmovus_qw_mem_256, llvm::Intrinsic::x86_avx512_mask_pmovus_qw_mem_512, llvm::Intrinsic::x86_avx512_mask_pmovus_wb_128, llvm::Intrinsic::x86_avx512_mask_pmovus_wb_256,   llvm::Intrinsic::x86_avx512_mask_pmovus_wb_512, llvm::Intrinsic::x86_avx512_mask_pmovus_wb_mem_128, llvm::Intrinsic::x86_avx512_mask_pmovus_wb_mem_256, llvm::Intrinsic::x86_avx512_mask_pmovus_wb_mem_512,   llvm::Intrinsic::x86_avx512_mask_range_pd_128, llvm::Intrinsic::x86_avx512_mask_range_pd_256, llvm::Intrinsic::x86_avx512_mask_range_pd_512, llvm::Intrinsic::x86_avx512_mask_range_ps_128,   llvm::Intrinsic::x86_avx512_mask_range_ps_256, llvm::Intrinsic::x86_avx512_mask_range_ps_512, llvm::Intrinsic::x86_avx512_mask_range_sd, llvm::Intrinsic::x86_avx512_mask_range_ss,   llvm::Intrinsic::x86_avx512_mask_reduce_pd_128, llvm::Intrinsic::x86_avx512_mask_reduce_pd_256, llvm::Intrinsic::x86_avx512_mask_reduce_pd_512, llvm::Intrinsic::x86_avx512_mask_reduce_ps_128,   llvm::Intrinsic::x86_avx512_mask_reduce_ps_256, llvm::Intrinsic::x86_avx512_mask_reduce_ps_512, llvm::Intrinsic::x86_avx512_mask_reduce_sd, llvm::Intrinsic::x86_avx512_mask_reduce_ss,   llvm::Intrinsic::x86_avx512_mask_rndscale_pd_128, llvm::Intrinsic::x86_avx512_mask_rndscale_pd_256, llvm::Intrinsic::x86_avx512_mask_rndscale_pd_512, llvm::Intrinsic::x86_avx512_mask_rndscale_ps_128,   llvm::Intrinsic::x86_avx512_mask_rndscale_ps_256, llvm::Intrinsic::x86_avx512_mask_rndscale_ps_512, llvm::Intrinsic::x86_avx512_mask_rndscale_sd, llvm::Intrinsic::x86_avx512_mask_rndscale_ss,   llvm::Intrinsic::x86_avx512_mask_scalef_pd_128, llvm::Intrinsic::x86_avx512_mask_scalef_pd_256, llvm::Intrinsic::x86_avx512_mask_scalef_pd_512, llvm::Intrinsic::x86_avx512_mask_scalef_ps_128,   llvm::Intrinsic::x86_avx512_mask_scalef_ps_256, llvm::Intrinsic::x86_avx512_mask_scalef_ps_512, llvm::Intrinsic::x86_avx512_mask_scalef_sd, llvm::Intrinsic::x86_avx512_mask_scalef_ss,   llvm::Intrinsic::x86_avx512_mask_scatter_dpd_512, llvm::Intrinsic::x86_avx512_mask_scatter_dpi_512, llvm::Intrinsic::x86_avx512_mask_scatter_dpq_512, llvm::Intrinsic::x86_avx512_mask_scatter_dps_512,   llvm::Intrinsic::x86_avx512_mask_scatter_qpd_512, llvm::Intrinsic::x86_avx512_mask_scatter_qpi_512, llvm::Intrinsic::x86_avx512_mask_scatter_qpq_512, llvm::Intrinsic::x86_avx512_mask_scatter_qps_512,   llvm::Intrinsic::x86_avx512_mask_scatterdiv2_df, llvm::Intrinsic::x86_avx512_mask_scatterdiv2_di, llvm::Intrinsic::x86_avx512_mask_scatterdiv4_df, llvm::Intrinsic::x86_avx512_mask_scatterdiv4_di,   llvm::Intrinsic::x86_avx512_mask_scatterdiv4_sf, llvm::Intrinsic::x86_avx512_mask_scatterdiv4_si, llvm::Intrinsic::x86_avx512_mask_scatterdiv8_sf, llvm::Intrinsic::x86_avx512_mask_scatterdiv8_si,   llvm::Intrinsic::x86_avx512_mask_scattersiv2_df, llvm::Intrinsic::x86_avx512_mask_scattersiv2_di, llvm::Intrinsic::x86_avx512_mask_scattersiv4_df, llvm::Intrinsic::x86_avx512_mask_scattersiv4_di,   llvm::Intrinsic::x86_avx512_mask_scattersiv4_sf, llvm::Intrinsic::x86_avx512_mask_scattersiv4_si, llvm::Intrinsic::x86_avx512_mask_scattersiv8_sf, llvm::Intrinsic::x86_avx512_mask_scattersiv8_si,   llvm::Intrinsic::x86_avx512_mask_sqrt_sd, llvm::Intrinsic::x86_avx512_mask_sqrt_ss, llvm::Intrinsic::x86_avx512_mask_sub_sd_round, llvm::Intrinsic::x86_avx512_mask_sub_ss_round,   llvm::Intrinsic::x86_avx512_mask_vcvtph2ps_128, llvm::Intrinsic::x86_avx512_mask_vcvtph2ps_256, llvm::Intrinsic::x86_avx512_mask_vcvtph2ps_512, llvm::Intrinsic::x86_avx512_mask_vcvtps2ph_128,   llvm::Intrinsic::x86_avx512_mask_vcvtps2ph_256, llvm::Intrinsic::x86_avx512_mask_vcvtps2ph_512, llvm::Intrinsic::x86_avx512_maskz_fixupimm_pd_128, llvm::Intrinsic::x86_avx512_maskz_fixupimm_pd_256,   llvm::Intrinsic::x86_avx512_maskz_fixupimm_pd_512, llvm::Intrinsic::x86_avx512_maskz_fixupimm_ps_128, llvm::Intrinsic::x86_avx512_maskz_fixupimm_ps_256, llvm::Intrinsic::x86_avx512_maskz_fixupimm_ps_512,   llvm::Intrinsic::x86_avx512_maskz_fixupimm_sd, llvm::Intrinsic::x86_avx512_maskz_fixupimm_ss, llvm::Intrinsic::x86_avx512_max_pd_512, llvm::Intrinsic::x86_avx512_max_ps_512,   llvm::Intrinsic::x86_avx512_min_pd_512, llvm::Intrinsic::x86_avx512_min_ps_512, llvm::Intrinsic::x86_avx512_mul_pd_512, llvm::Intrinsic::x86_avx512_mul_ps_512,   llvm::Intrinsic::x86_avx512_packssdw_512, llvm::Intrinsic::x86_avx512_packsswb_512, llvm::Intrinsic::x86_avx512_packusdw_512, llvm::Intrinsic::x86_avx512_packuswb_512,   llvm::Intrinsic::x86_avx512_permvar_df_256, llvm::Intrinsic::x86_avx512_permvar_df_512, llvm::Intrinsic::x86_avx512_permvar_di_256, llvm::Intrinsic::x86_avx512_permvar_di_512,   llvm::Intrinsic::x86_avx512_permvar_hi_128, llvm::Intrinsic::x86_avx512_permvar_hi_256, llvm::Intrinsic::x86_avx512_permvar_hi_512, llvm::Intrinsic::x86_avx512_permvar_qi_128,   llvm::Intrinsic::x86_avx512_permvar_qi_256, llvm::Intrinsic::x86_avx512_permvar_qi_512, llvm::Intrinsic::x86_avx512_permvar_sf_512, llvm::Intrinsic::x86_avx512_permvar_si_512,   llvm::Intrinsic::x86_avx512_pmaddubs_w_512, llvm::Intrinsic::x86_avx512_pmaddw_d_512, llvm::Intrinsic::x86_avx512_pmul_hr_sw_512, llvm::Intrinsic::x86_avx512_pmulh_w_512,   llvm::Intrinsic::x86_avx512_pmulhu_w_512, llvm::Intrinsic::x86_avx512_pmultishift_qb_128, llvm::Intrinsic::x86_avx512_pmultishift_qb_256, llvm::Intrinsic::x86_avx512_pmultishift_qb_512,   llvm::Intrinsic::x86_avx512_psad_bw_512, llvm::Intrinsic::x86_avx512_pshuf_b_512, llvm::Intrinsic::x86_avx512_psll_d_512, llvm::Intrinsic::x86_avx512_psll_q_512,   llvm::Intrinsic::x86_avx512_psll_w_512, llvm::Intrinsic::x86_avx512_pslli_d_512, llvm::Intrinsic::x86_avx512_pslli_q_512, llvm::Intrinsic::x86_avx512_pslli_w_512,   llvm::Intrinsic::x86_avx512_psllv_d_512, llvm::Intrinsic::x86_avx512_psllv_q_512, llvm::Intrinsic::x86_avx512_psllv_w_128, llvm::Intrinsic::x86_avx512_psllv_w_256,   llvm::Intrinsic::x86_avx512_psllv_w_512, llvm::Intrinsic::x86_avx512_psra_d_512, llvm::Intrinsic::x86_avx512_psra_q_128, llvm::Intrinsic::x86_avx512_psra_q_256,   llvm::Intrinsic::x86_avx512_psra_q_512, llvm::Intrinsic::x86_avx512_psra_w_512, llvm::Intrinsic::x86_avx512_psrai_d_512, llvm::Intrinsic::x86_avx512_psrai_q_128,   llvm::Intrinsic::x86_avx512_psrai_q_256, llvm::Intrinsic::x86_avx512_psrai_q_512, llvm::Intrinsic::x86_avx512_psrai_w_512, llvm::Intrinsic::x86_avx512_psrav_d_512,   llvm::Intrinsic::x86_avx512_psrav_q_128, llvm::Intrinsic::x86_avx512_psrav_q_256, llvm::Intrinsic::x86_avx512_psrav_q_512, llvm::Intrinsic::x86_avx512_psrav_w_128,   llvm::Intrinsic::x86_avx512_psrav_w_256, llvm::Intrinsic::x86_avx512_psrav_w_512, llvm::Intrinsic::x86_avx512_psrl_d_512, llvm::Intrinsic::x86_avx512_psrl_q_512,   llvm::Intrinsic::x86_avx512_psrl_w_512, llvm::Intrinsic::x86_avx512_psrli_d_512, llvm::Intrinsic::x86_avx512_psrli_q_512, llvm::Intrinsic::x86_avx512_psrli_w_512,   llvm::Intrinsic::x86_avx512_psrlv_d_512, llvm::Intrinsic::x86_avx512_psrlv_q_512, llvm::Intrinsic::x86_avx512_psrlv_w_128, llvm::Intrinsic::x86_avx512_psrlv_w_256,   llvm::Intrinsic::x86_avx512_psrlv_w_512, llvm::Intrinsic::x86_avx512_pternlog_d_128, llvm::Intrinsic::x86_avx512_pternlog_d_256, llvm::Intrinsic::x86_avx512_pternlog_d_512,   llvm::Intrinsic::x86_avx512_pternlog_q_128, llvm::Intrinsic::x86_avx512_pternlog_q_256, llvm::Intrinsic::x86_avx512_pternlog_q_512, llvm::Intrinsic::x86_avx512_rcp14_pd_128,   llvm::Intrinsic::x86_avx512_rcp14_pd_256, llvm::Intrinsic::x86_avx512_rcp14_pd_512, llvm::Intrinsic::x86_avx512_rcp14_ps_128, llvm::Intrinsic::x86_avx512_rcp14_ps_256,   llvm::Intrinsic::x86_avx512_rcp14_ps_512, llvm::Intrinsic::x86_avx512_rcp14_sd, llvm::Intrinsic::x86_avx512_rcp14_ss, llvm::Intrinsic::x86_avx512_rcp28_pd,   llvm::Intrinsic::x86_avx512_rcp28_ps, llvm::Intrinsic::x86_avx512_rcp28_sd, llvm::Intrinsic::x86_avx512_rcp28_ss, llvm::Intrinsic::x86_avx512_rsqrt14_pd_128,   llvm::Intrinsic::x86_avx512_rsqrt14_pd_256, llvm::Intrinsic::x86_avx512_rsqrt14_pd_512, llvm::Intrinsic::x86_avx512_rsqrt14_ps_128, llvm::Intrinsic::x86_avx512_rsqrt14_ps_256,   llvm::Intrinsic::x86_avx512_rsqrt14_ps_512, llvm::Intrinsic::x86_avx512_rsqrt14_sd, llvm::Intrinsic::x86_avx512_rsqrt14_ss, llvm::Intrinsic::x86_avx512_rsqrt28_pd,   llvm::Intrinsic::x86_avx512_rsqrt28_ps, llvm::Intrinsic::x86_avx512_rsqrt28_sd, llvm::Intrinsic::x86_avx512_rsqrt28_ss, llvm::Intrinsic::x86_avx512_scatter_dpd_512,   llvm::Intrinsic::x86_avx512_scatter_dpi_512, llvm::Intrinsic::x86_avx512_scatter_dpq_512, llvm::Intrinsic::x86_avx512_scatter_dps_512, llvm::Intrinsic::x86_avx512_scatter_qpd_512,   llvm::Intrinsic::x86_avx512_scatter_qpi_512, llvm::Intrinsic::x86_avx512_scatter_qpq_512, llvm::Intrinsic::x86_avx512_scatter_qps_512, llvm::Intrinsic::x86_avx512_scatterdiv2_df,   llvm::Intrinsic::x86_avx512_scatterdiv2_di, llvm::Intrinsic::x86_avx512_scatterdiv4_df, llvm::Intrinsic::x86_avx512_scatterdiv4_di, llvm::Intrinsic::x86_avx512_scatterdiv4_sf,   llvm::Intrinsic::x86_avx512_scatterdiv4_si, llvm::Intrinsic::x86_avx512_scatterdiv8_sf, llvm::Intrinsic::x86_avx512_scatterdiv8_si, llvm::Intrinsic::x86_avx512_scatterpf_dpd_512,   llvm::Intrinsic::x86_avx512_scatterpf_dps_512, llvm::Intrinsic::x86_avx512_scatterpf_qpd_512, llvm::Intrinsic::x86_avx512_scatterpf_qps_512, llvm::Intrinsic::x86_avx512_scattersiv2_df,   llvm::Intrinsic::x86_avx512_scattersiv2_di, llvm::Intrinsic::x86_avx512_scattersiv4_df, llvm::Intrinsic::x86_avx512_scattersiv4_di, llvm::Intrinsic::x86_avx512_scattersiv4_sf,   llvm::Intrinsic::x86_avx512_scattersiv4_si, llvm::Intrinsic::x86_avx512_scattersiv8_sf, llvm::Intrinsic::x86_avx512_scattersiv8_si, llvm::Intrinsic::x86_avx512_sqrt_pd_512,   llvm::Intrinsic::x86_avx512_sqrt_ps_512, llvm::Intrinsic::x86_avx512_sub_pd_512, llvm::Intrinsic::x86_avx512_sub_ps_512, llvm::Intrinsic::x86_avx512_vcomi_sd,   llvm::Intrinsic::x86_avx512_vcomi_ss, llvm::Intrinsic::x86_avx512_vcvtsd2si32, llvm::Intrinsic::x86_avx512_vcvtsd2si64, llvm::Intrinsic::x86_avx512_vcvtsd2usi32,   llvm::Intrinsic::x86_avx512_vcvtsd2usi64, llvm::Intrinsic::x86_avx512_vcvtss2si32, llvm::Intrinsic::x86_avx512_vcvtss2si64, llvm::Intrinsic::x86_avx512_vcvtss2usi32,   llvm::Intrinsic::x86_avx512_vcvtss2usi64, llvm::Intrinsic::x86_avx512_vfmadd_f32, llvm::Intrinsic::x86_avx512_vfmadd_f64, llvm::Intrinsic::x86_avx512_vfmadd_pd_512,   llvm::Intrinsic::x86_avx512_vfmadd_ps_512, llvm::Intrinsic::x86_avx512_vfmaddsub_pd_512, llvm::Intrinsic::x86_avx512_vfmaddsub_ps_512, llvm::Intrinsic::x86_avx512_vpdpbusd_128,   llvm::Intrinsic::x86_avx512_vpdpbusd_256, llvm::Intrinsic::x86_avx512_vpdpbusd_512, llvm::Intrinsic::x86_avx512_vpdpbusds_128, llvm::Intrinsic::x86_avx512_vpdpbusds_256,   llvm::Intrinsic::x86_avx512_vpdpbusds_512, llvm::Intrinsic::x86_avx512_vpdpwssd_128, llvm::Intrinsic::x86_avx512_vpdpwssd_256, llvm::Intrinsic::x86_avx512_vpdpwssd_512,   llvm::Intrinsic::x86_avx512_vpdpwssds_128, llvm::Intrinsic::x86_avx512_vpdpwssds_256, llvm::Intrinsic::x86_avx512_vpdpwssds_512, llvm::Intrinsic::x86_avx512_vpermi2var_d_128,   llvm::Intrinsic::x86_avx512_vpermi2var_d_256, llvm::Intrinsic::x86_avx512_vpermi2var_d_512, llvm::Intrinsic::x86_avx512_vpermi2var_hi_128, llvm::Intrinsic::x86_avx512_vpermi2var_hi_256,   llvm::Intrinsic::x86_avx512_vpermi2var_hi_512, llvm::Intrinsic::x86_avx512_vpermi2var_pd_128, llvm::Intrinsic::x86_avx512_vpermi2var_pd_256, llvm::Intrinsic::x86_avx512_vpermi2var_pd_512,   llvm::Intrinsic::x86_avx512_vpermi2var_ps_128, llvm::Intrinsic::x86_avx512_vpermi2var_ps_256, llvm::Intrinsic::x86_avx512_vpermi2var_ps_512, llvm::Intrinsic::x86_avx512_vpermi2var_q_128,   llvm::Intrinsic::x86_avx512_vpermi2var_q_256, llvm::Intrinsic::x86_avx512_vpermi2var_q_512, llvm::Intrinsic::x86_avx512_vpermi2var_qi_128, llvm::Intrinsic::x86_avx512_vpermi2var_qi_256,   llvm::Intrinsic::x86_avx512_vpermi2var_qi_512, llvm::Intrinsic::x86_avx512_vpermilvar_pd_512, llvm::Intrinsic::x86_avx512_vpermilvar_ps_512, llvm::Intrinsic::x86_avx512_vpmadd52h_uq_128,   llvm::Intrinsic::x86_avx512_vpmadd52h_uq_256, llvm::Intrinsic::x86_avx512_vpmadd52h_uq_512, llvm::Intrinsic::x86_avx512_vpmadd52l_uq_128, llvm::Intrinsic::x86_avx512_vpmadd52l_uq_256,   llvm::Intrinsic::x86_avx512_vpmadd52l_uq_512, llvm::Intrinsic::x86_avx512_vpshufbitqmb_128, llvm::Intrinsic::x86_avx512_vpshufbitqmb_256, llvm::Intrinsic::x86_avx512_vpshufbitqmb_512,   llvm::Intrinsic::x86_bmi_bextr_32, llvm::Intrinsic::x86_bmi_bextr_64, llvm::Intrinsic::x86_bmi_bzhi_32, llvm::Intrinsic::x86_bmi_bzhi_64,   llvm::Intrinsic::x86_bmi_pdep_32, llvm::Intrinsic::x86_bmi_pdep_64, llvm::Intrinsic::x86_bmi_pext_32, llvm::Intrinsic::x86_bmi_pext_64,   llvm::Intrinsic::x86_cldemote, llvm::Intrinsic::x86_clflushopt, llvm::Intrinsic::x86_clrssbsy, llvm::Intrinsic::x86_clwb,   llvm::Intrinsic::x86_clzero, llvm::Intrinsic::x86_directstore32, llvm::Intrinsic::x86_directstore64, llvm::Intrinsic::x86_flags_read_u32,   llvm::Intrinsic::x86_flags_read_u64, llvm::Intrinsic::x86_flags_write_u32, llvm::Intrinsic::x86_flags_write_u64, llvm::Intrinsic::x86_fxrstor,   llvm::Intrinsic::x86_fxrstor64, llvm::Intrinsic::x86_fxsave, llvm::Intrinsic::x86_fxsave64, llvm::Intrinsic::x86_incsspd,   llvm::Intrinsic::x86_incsspq, llvm::Intrinsic::x86_int, llvm::Intrinsic::x86_invpcid, llvm::Intrinsic::x86_llwpcb,   llvm::Intrinsic::x86_lwpins32, llvm::Intrinsic::x86_lwpins64, llvm::Intrinsic::x86_lwpval32, llvm::Intrinsic::x86_lwpval64,   llvm::Intrinsic::x86_mmx_emms, llvm::Intrinsic::x86_mmx_femms, llvm::Intrinsic::x86_mmx_maskmovq, llvm::Intrinsic::x86_mmx_movnt_dq,   llvm::Intrinsic::x86_mmx_packssdw, llvm::Intrinsic::x86_mmx_packsswb, llvm::Intrinsic::x86_mmx_packuswb, llvm::Intrinsic::x86_mmx_padd_b,   llvm::Intrinsic::x86_mmx_padd_d, llvm::Intrinsic::x86_mmx_padd_q, llvm::Intrinsic::x86_mmx_padd_w, llvm::Intrinsic::x86_mmx_padds_b,   llvm::Intrinsic::x86_mmx_padds_w, llvm::Intrinsic::x86_mmx_paddus_b, llvm::Intrinsic::x86_mmx_paddus_w, llvm::Intrinsic::x86_mmx_palignr_b,   llvm::Intrinsic::x86_mmx_pand, llvm::Intrinsic::x86_mmx_pandn, llvm::Intrinsic::x86_mmx_pavg_b, llvm::Intrinsic::x86_mmx_pavg_w,   llvm::Intrinsic::x86_mmx_pcmpeq_b, llvm::Intrinsic::x86_mmx_pcmpeq_d, llvm::Intrinsic::x86_mmx_pcmpeq_w, llvm::Intrinsic::x86_mmx_pcmpgt_b,   llvm::Intrinsic::x86_mmx_pcmpgt_d, llvm::Intrinsic::x86_mmx_pcmpgt_w, llvm::Intrinsic::x86_mmx_pextr_w, llvm::Intrinsic::x86_mmx_pinsr_w,   llvm::Intrinsic::x86_mmx_pmadd_wd, llvm::Intrinsic::x86_mmx_pmaxs_w, llvm::Intrinsic::x86_mmx_pmaxu_b, llvm::Intrinsic::x86_mmx_pmins_w,   llvm::Intrinsic::x86_mmx_pminu_b, llvm::Intrinsic::x86_mmx_pmovmskb, llvm::Intrinsic::x86_mmx_pmulh_w, llvm::Intrinsic::x86_mmx_pmulhu_w,   llvm::Intrinsic::x86_mmx_pmull_w, llvm::Intrinsic::x86_mmx_pmulu_dq, llvm::Intrinsic::x86_mmx_por, llvm::Intrinsic::x86_mmx_psad_bw,   llvm::Intrinsic::x86_mmx_psll_d, llvm::Intrinsic::x86_mmx_psll_q, llvm::Intrinsic::x86_mmx_psll_w, llvm::Intrinsic::x86_mmx_pslli_d,   llvm::Intrinsic::x86_mmx_pslli_q, llvm::Intrinsic::x86_mmx_pslli_w, llvm::Intrinsic::x86_mmx_psra_d, llvm::Intrinsic::x86_mmx_psra_w,   llvm::Intrinsic::x86_mmx_psrai_d, llvm::Intrinsic::x86_mmx_psrai_w, llvm::Intrinsic::x86_mmx_psrl_d, llvm::Intrinsic::x86_mmx_psrl_q,   llvm::Intrinsic::x86_mmx_psrl_w, llvm::Intrinsic::x86_mmx_psrli_d, llvm::Intrinsic::x86_mmx_psrli_q, llvm::Intrinsic::x86_mmx_psrli_w,   llvm::Intrinsic::x86_mmx_psub_b, llvm::Intrinsic::x86_mmx_psub_d, llvm::Intrinsic::x86_mmx_psub_q, llvm::Intrinsic::x86_mmx_psub_w,   llvm::Intrinsic::x86_mmx_psubs_b, llvm::Intrinsic::x86_mmx_psubs_w, llvm::Intrinsic::x86_mmx_psubus_b, llvm::Intrinsic::x86_mmx_psubus_w,   llvm::Intrinsic::x86_mmx_punpckhbw, llvm::Intrinsic::x86_mmx_punpckhdq, llvm::Intrinsic::x86_mmx_punpckhwd, llvm::Intrinsic::x86_mmx_punpcklbw,   llvm::Intrinsic::x86_mmx_punpckldq, llvm::Intrinsic::x86_mmx_punpcklwd, llvm::Intrinsic::x86_mmx_pxor, llvm::Intrinsic::x86_monitorx,   llvm::Intrinsic::x86_movdir64b, llvm::Intrinsic::x86_mwaitx, llvm::Intrinsic::x86_pclmulqdq, llvm::Intrinsic::x86_pclmulqdq_256,   llvm::Intrinsic::x86_pclmulqdq_512, llvm::Intrinsic::x86_ptwrite32, llvm::Intrinsic::x86_ptwrite64, llvm::Intrinsic::x86_rdfsbase_32,   llvm::Intrinsic::x86_rdfsbase_64, llvm::Intrinsic::x86_rdgsbase_32, llvm::Intrinsic::x86_rdgsbase_64, llvm::Intrinsic::x86_rdpid,   llvm::Intrinsic::x86_rdpkru, llvm::Intrinsic::x86_rdpmc, llvm::Intrinsic::x86_rdrand_16, llvm::Intrinsic::x86_rdrand_32,   llvm::Intrinsic::x86_rdrand_64, llvm::Intrinsic::x86_rdseed_16, llvm::Intrinsic::x86_rdseed_32, llvm::Intrinsic::x86_rdseed_64,   llvm::Intrinsic::x86_rdsspd, llvm::Intrinsic::x86_rdsspq, llvm::Intrinsic::x86_rdtsc, llvm::Intrinsic::x86_rdtscp,   llvm::Intrinsic::x86_rstorssp, llvm::Intrinsic::x86_saveprevssp, llvm::Intrinsic::x86_seh_ehguard, llvm::Intrinsic::x86_seh_ehregnode,   llvm::Intrinsic::x86_seh_lsda, llvm::Intrinsic::x86_setssbsy, llvm::Intrinsic::x86_sha1msg1, llvm::Intrinsic::x86_sha1msg2,   llvm::Intrinsic::x86_sha1nexte, llvm::Intrinsic::x86_sha1rnds4, llvm::Intrinsic::x86_sha256msg1, llvm::Intrinsic::x86_sha256msg2,   llvm::Intrinsic::x86_sha256rnds2, llvm::Intrinsic::x86_slwpcb, llvm::Intrinsic::x86_sse_cmp_ps, llvm::Intrinsic::x86_sse_cmp_ss,   llvm::Intrinsic::x86_sse_comieq_ss, llvm::Intrinsic::x86_sse_comige_ss, llvm::Intrinsic::x86_sse_comigt_ss, llvm::Intrinsic::x86_sse_comile_ss,   llvm::Intrinsic::x86_sse_comilt_ss, llvm::Intrinsic::x86_sse_comineq_ss, llvm::Intrinsic::x86_sse_cvtpd2pi, llvm::Intrinsic::x86_sse_cvtpi2pd,   llvm::Intrinsic::x86_sse_cvtpi2ps, llvm::Intrinsic::x86_sse_cvtps2pi, llvm::Intrinsic::x86_sse_cvtss2si, llvm::Intrinsic::x86_sse_cvtss2si64,   llvm::Intrinsic::x86_sse_cvttpd2pi, llvm::Intrinsic::x86_sse_cvttps2pi, llvm::Intrinsic::x86_sse_cvttss2si, llvm::Intrinsic::x86_sse_cvttss2si64,   llvm::Intrinsic::x86_sse_ldmxcsr, llvm::Intrinsic::x86_sse_max_ps, llvm::Intrinsic::x86_sse_max_ss, llvm::Intrinsic::x86_sse_min_ps,   llvm::Intrinsic::x86_sse_min_ss, llvm::Intrinsic::x86_sse_movmsk_ps, llvm::Intrinsic::x86_sse_pshuf_w, llvm::Intrinsic::x86_sse_rcp_ps,   llvm::Intrinsic::x86_sse_rcp_ss, llvm::Intrinsic::x86_sse_rsqrt_ps, llvm::Intrinsic::x86_sse_rsqrt_ss, llvm::Intrinsic::x86_sse_sfence,   llvm::Intrinsic::x86_sse_stmxcsr, llvm::Intrinsic::x86_sse_ucomieq_ss, llvm::Intrinsic::x86_sse_ucomige_ss, llvm::Intrinsic::x86_sse_ucomigt_ss,   llvm::Intrinsic::x86_sse_ucomile_ss, llvm::Intrinsic::x86_sse_ucomilt_ss, llvm::Intrinsic::x86_sse_ucomineq_ss, llvm::Intrinsic::x86_sse2_clflush,   llvm::Intrinsic::x86_sse2_cmp_pd, llvm::Intrinsic::x86_sse2_cmp_sd, llvm::Intrinsic::x86_sse2_comieq_sd, llvm::Intrinsic::x86_sse2_comige_sd,   llvm::Intrinsic::x86_sse2_comigt_sd, llvm::Intrinsic::x86_sse2_comile_sd, llvm::Intrinsic::x86_sse2_comilt_sd, llvm::Intrinsic::x86_sse2_comineq_sd,   llvm::Intrinsic::x86_sse2_cvtpd2dq, llvm::Intrinsic::x86_sse2_cvtpd2ps, llvm::Intrinsic::x86_sse2_cvtps2dq, llvm::Intrinsic::x86_sse2_cvtsd2si,   llvm::Intrinsic::x86_sse2_cvtsd2si64, llvm::Intrinsic::x86_sse2_cvtsd2ss, llvm::Intrinsic::x86_sse2_cvttpd2dq, llvm::Intrinsic::x86_sse2_cvttps2dq,   llvm::Intrinsic::x86_sse2_cvttsd2si, llvm::Intrinsic::x86_sse2_cvttsd2si64, llvm::Intrinsic::x86_sse2_lfence, llvm::Intrinsic::x86_sse2_maskmov_dqu,   llvm::Intrinsic::x86_sse2_max_pd, llvm::Intrinsic::x86_sse2_max_sd, llvm::Intrinsic::x86_sse2_mfence, llvm::Intrinsic::x86_sse2_min_pd,   llvm::Intrinsic::x86_sse2_min_sd, llvm::Intrinsic::x86_sse2_movmsk_pd, llvm::Intrinsic::x86_sse2_packssdw_128, llvm::Intrinsic::x86_sse2_packsswb_128,   llvm::Intrinsic::x86_sse2_packuswb_128, llvm::Intrinsic::x86_sse2_pause, llvm::Intrinsic::x86_sse2_pmadd_wd, llvm::Intrinsic::x86_sse2_pmovmskb_128,   llvm::Intrinsic::x86_sse2_pmulh_w, llvm::Intrinsic::x86_sse2_pmulhu_w, llvm::Intrinsic::x86_sse2_psad_bw, llvm::Intrinsic::x86_sse2_psll_d,   llvm::Intrinsic::x86_sse2_psll_q, llvm::Intrinsic::x86_sse2_psll_w, llvm::Intrinsic::x86_sse2_pslli_d, llvm::Intrinsic::x86_sse2_pslli_q,   llvm::Intrinsic::x86_sse2_pslli_w, llvm::Intrinsic::x86_sse2_psra_d, llvm::Intrinsic::x86_sse2_psra_w, llvm::Intrinsic::x86_sse2_psrai_d,   llvm::Intrinsic::x86_sse2_psrai_w, llvm::Intrinsic::x86_sse2_psrl_d, llvm::Intrinsic::x86_sse2_psrl_q, llvm::Intrinsic::x86_sse2_psrl_w,   llvm::Intrinsic::x86_sse2_psrli_d, llvm::Intrinsic::x86_sse2_psrli_q, llvm::Intrinsic::x86_sse2_psrli_w, llvm::Intrinsic::x86_sse2_ucomieq_sd,   llvm::Intrinsic::x86_sse2_ucomige_sd, llvm::Intrinsic::x86_sse2_ucomigt_sd, llvm::Intrinsic::x86_sse2_ucomile_sd, llvm::Intrinsic::x86_sse2_ucomilt_sd,   llvm::Intrinsic::x86_sse2_ucomineq_sd, llvm::Intrinsic::x86_sse3_addsub_pd, llvm::Intrinsic::x86_sse3_addsub_ps, llvm::Intrinsic::x86_sse3_hadd_pd,   llvm::Intrinsic::x86_sse3_hadd_ps, llvm::Intrinsic::x86_sse3_hsub_pd, llvm::Intrinsic::x86_sse3_hsub_ps, llvm::Intrinsic::x86_sse3_ldu_dq,   llvm::Intrinsic::x86_sse3_monitor, llvm::Intrinsic::x86_sse3_mwait, llvm::Intrinsic::x86_sse41_blendvpd, llvm::Intrinsic::x86_sse41_blendvps,   llvm::Intrinsic::x86_sse41_dppd, llvm::Intrinsic::x86_sse41_dpps, llvm::Intrinsic::x86_sse41_insertps, llvm::Intrinsic::x86_sse41_mpsadbw,   llvm::Intrinsic::x86_sse41_packusdw, llvm::Intrinsic::x86_sse41_pblendvb, llvm::Intrinsic::x86_sse41_phminposuw, llvm::Intrinsic::x86_sse41_ptestc,   llvm::Intrinsic::x86_sse41_ptestnzc, llvm::Intrinsic::x86_sse41_ptestz, llvm::Intrinsic::x86_sse41_round_pd, llvm::Intrinsic::x86_sse41_round_ps,   llvm::Intrinsic::x86_sse41_round_sd, llvm::Intrinsic::x86_sse41_round_ss, llvm::Intrinsic::x86_sse42_crc32_32_16, llvm::Intrinsic::x86_sse42_crc32_32_32,   llvm::Intrinsic::x86_sse42_crc32_32_8, llvm::Intrinsic::x86_sse42_crc32_64_64, llvm::Intrinsic::x86_sse42_pcmpestri128, llvm::Intrinsic::x86_sse42_pcmpestria128,   llvm::Intrinsic::x86_sse42_pcmpestric128, llvm::Intrinsic::x86_sse42_pcmpestrio128, llvm::Intrinsic::x86_sse42_pcmpestris128, llvm::Intrinsic::x86_sse42_pcmpestriz128,   llvm::Intrinsic::x86_sse42_pcmpestrm128, llvm::Intrinsic::x86_sse42_pcmpistri128, llvm::Intrinsic::x86_sse42_pcmpistria128, llvm::Intrinsic::x86_sse42_pcmpistric128,   llvm::Intrinsic::x86_sse42_pcmpistrio128, llvm::Intrinsic::x86_sse42_pcmpistris128, llvm::Intrinsic::x86_sse42_pcmpistriz128, llvm::Intrinsic::x86_sse42_pcmpistrm128,   llvm::Intrinsic::x86_sse4a_extrq, llvm::Intrinsic::x86_sse4a_extrqi, llvm::Intrinsic::x86_sse4a_insertq, llvm::Intrinsic::x86_sse4a_insertqi,   llvm::Intrinsic::x86_ssse3_pabs_b, llvm::Intrinsic::x86_ssse3_pabs_d, llvm::Intrinsic::x86_ssse3_pabs_w, llvm::Intrinsic::x86_ssse3_phadd_d,   llvm::Intrinsic::x86_ssse3_phadd_d_128, llvm::Intrinsic::x86_ssse3_phadd_sw, llvm::Intrinsic::x86_ssse3_phadd_sw_128, llvm::Intrinsic::x86_ssse3_phadd_w,   llvm::Intrinsic::x86_ssse3_phadd_w_128, llvm::Intrinsic::x86_ssse3_phsub_d, llvm::Intrinsic::x86_ssse3_phsub_d_128, llvm::Intrinsic::x86_ssse3_phsub_sw,   llvm::Intrinsic::x86_ssse3_phsub_sw_128, llvm::Intrinsic::x86_ssse3_phsub_w, llvm::Intrinsic::x86_ssse3_phsub_w_128, llvm::Intrinsic::x86_ssse3_pmadd_ub_sw,   llvm::Intrinsic::x86_ssse3_pmadd_ub_sw_128, llvm::Intrinsic::x86_ssse3_pmul_hr_sw, llvm::Intrinsic::x86_ssse3_pmul_hr_sw_128, llvm::Intrinsic::x86_ssse3_pshuf_b,   llvm::Intrinsic::x86_ssse3_pshuf_b_128, llvm::Intrinsic::x86_ssse3_psign_b, llvm::Intrinsic::x86_ssse3_psign_b_128, llvm::Intrinsic::x86_ssse3_psign_d,   llvm::Intrinsic::x86_ssse3_psign_d_128, llvm::Intrinsic::x86_ssse3_psign_w, llvm::Intrinsic::x86_ssse3_psign_w_128, llvm::Intrinsic::x86_subborrow_32,   llvm::Intrinsic::x86_subborrow_64, llvm::Intrinsic::x86_tbm_bextri_u32, llvm::Intrinsic::x86_tbm_bextri_u64, llvm::Intrinsic::x86_tpause,   llvm::Intrinsic::x86_umonitor, llvm::Intrinsic::x86_umwait, llvm::Intrinsic::x86_vcvtph2ps_128, llvm::Intrinsic::x86_vcvtph2ps_256,   llvm::Intrinsic::x86_vcvtps2ph_128, llvm::Intrinsic::x86_vcvtps2ph_256, llvm::Intrinsic::x86_vgf2p8affineinvqb_128, llvm::Intrinsic::x86_vgf2p8affineinvqb_256,   llvm::Intrinsic::x86_vgf2p8affineinvqb_512, llvm::Intrinsic::x86_vgf2p8affineqb_128, llvm::Intrinsic::x86_vgf2p8affineqb_256, llvm::Intrinsic::x86_vgf2p8affineqb_512,   llvm::Intrinsic::x86_vgf2p8mulb_128, llvm::Intrinsic::x86_vgf2p8mulb_256, llvm::Intrinsic::x86_vgf2p8mulb_512, llvm::Intrinsic::x86_wbinvd,   llvm::Intrinsic::x86_wbnoinvd, llvm::Intrinsic::x86_wrfsbase_32, llvm::Intrinsic::x86_wrfsbase_64, llvm::Intrinsic::x86_wrgsbase_32,   llvm::Intrinsic::x86_wrgsbase_64, llvm::Intrinsic::x86_wrpkru, llvm::Intrinsic::x86_wrssd, llvm::Intrinsic::x86_wrssq,   llvm::Intrinsic::x86_wrussd, llvm::Intrinsic::x86_wrussq, llvm::Intrinsic::x86_xabort, llvm::Intrinsic::x86_xbegin,   llvm::Intrinsic::x86_xend, llvm::Intrinsic::x86_xgetbv, llvm::Intrinsic::x86_xop_vfrcz_pd, llvm::Intrinsic::x86_xop_vfrcz_pd_256,   llvm::Intrinsic::x86_xop_vfrcz_ps, llvm::Intrinsic::x86_xop_vfrcz_ps_256, llvm::Intrinsic::x86_xop_vfrcz_sd, llvm::Intrinsic::x86_xop_vfrcz_ss,   llvm::Intrinsic::x86_xop_vpcomb, llvm::Intrinsic::x86_xop_vpcomd, llvm::Intrinsic::x86_xop_vpcomq, llvm::Intrinsic::x86_xop_vpcomub,   llvm::Intrinsic::x86_xop_vpcomud, llvm::Intrinsic::x86_xop_vpcomuq, llvm::Intrinsic::x86_xop_vpcomuw, llvm::Intrinsic::x86_xop_vpcomw,   llvm::Intrinsic::x86_xop_vpermil2pd, llvm::Intrinsic::x86_xop_vpermil2pd_256, llvm::Intrinsic::x86_xop_vpermil2ps, llvm::Intrinsic::x86_xop_vpermil2ps_256,   llvm::Intrinsic::x86_xop_vphaddbd, llvm::Intrinsic::x86_xop_vphaddbq, llvm::Intrinsic::x86_xop_vphaddbw, llvm::Intrinsic::x86_xop_vphadddq,   llvm::Intrinsic::x86_xop_vphaddubd, llvm::Intrinsic::x86_xop_vphaddubq, llvm::Intrinsic::x86_xop_vphaddubw, llvm::Intrinsic::x86_xop_vphaddudq,   llvm::Intrinsic::x86_xop_vphadduwd, llvm::Intrinsic::x86_xop_vphadduwq, llvm::Intrinsic::x86_xop_vphaddwd, llvm::Intrinsic::x86_xop_vphaddwq,   llvm::Intrinsic::x86_xop_vphsubbw, llvm::Intrinsic::x86_xop_vphsubdq, llvm::Intrinsic::x86_xop_vphsubwd, llvm::Intrinsic::x86_xop_vpmacsdd,   llvm::Intrinsic::x86_xop_vpmacsdqh, llvm::Intrinsic::x86_xop_vpmacsdql, llvm::Intrinsic::x86_xop_vpmacssdd, llvm::Intrinsic::x86_xop_vpmacssdqh,   llvm::Intrinsic::x86_xop_vpmacssdql, llvm::Intrinsic::x86_xop_vpmacsswd, llvm::Intrinsic::x86_xop_vpmacssww, llvm::Intrinsic::x86_xop_vpmacswd,   llvm::Intrinsic::x86_xop_vpmacsww, llvm::Intrinsic::x86_xop_vpmadcsswd, llvm::Intrinsic::x86_xop_vpmadcswd, llvm::Intrinsic::x86_xop_vpperm,   llvm::Intrinsic::x86_xop_vpshab, llvm::Intrinsic::x86_xop_vpshad, llvm::Intrinsic::x86_xop_vpshaq, llvm::Intrinsic::x86_xop_vpshaw,   llvm::Intrinsic::x86_xop_vpshlb, llvm::Intrinsic::x86_xop_vpshld, llvm::Intrinsic::x86_xop_vpshlq, llvm::Intrinsic::x86_xop_vpshlw,   llvm::Intrinsic::x86_xrstor, llvm::Intrinsic::x86_xrstor64, llvm::Intrinsic::x86_xrstors, llvm::Intrinsic::x86_xrstors64,   llvm::Intrinsic::x86_xsave, llvm::Intrinsic::x86_xsave64, llvm::Intrinsic::x86_xsavec, llvm::Intrinsic::x86_xsavec64,   llvm::Intrinsic::x86_xsaveopt, llvm::Intrinsic::x86_xsaveopt64, llvm::Intrinsic::x86_xsaves, llvm::Intrinsic::x86_xsaves64,   llvm::Intrinsic::x86_xsetbv, llvm::Intrinsic::x86_xtest, llvm::Intrinsic::xcore_bitrev, llvm::Intrinsic::xcore_checkevent,   llvm::Intrinsic::xcore_chkct, llvm::Intrinsic::xcore_clre, llvm::Intrinsic::xcore_clrpt, llvm::Intrinsic::xcore_clrsr,   llvm::Intrinsic::xcore_crc32, llvm::Intrinsic::xcore_crc8, llvm::Intrinsic::xcore_edu, llvm::Intrinsic::xcore_eeu,   llvm::Intrinsic::xcore_endin, llvm::Intrinsic::xcore_freer, llvm::Intrinsic::xcore_geted, llvm::Intrinsic::xcore_getet,   llvm::Intrinsic::xcore_getid, llvm::Intrinsic::xcore_getps, llvm::Intrinsic::xcore_getr, llvm::Intrinsic::xcore_getst,   llvm::Intrinsic::xcore_getts, llvm::Intrinsic::xcore_in, llvm::Intrinsic::xcore_inct, llvm::Intrinsic::xcore_initcp,   llvm::Intrinsic::xcore_initdp, llvm::Intrinsic::xcore_initlr, llvm::Intrinsic::xcore_initpc, llvm::Intrinsic::xcore_initsp,   llvm::Intrinsic::xcore_inshr, llvm::Intrinsic::xcore_int, llvm::Intrinsic::xcore_mjoin, llvm::Intrinsic::xcore_msync,   llvm::Intrinsic::xcore_out, llvm::Intrinsic::xcore_outct, llvm::Intrinsic::xcore_outshr, llvm::Intrinsic::xcore_outt,   llvm::Intrinsic::xcore_peek, llvm::Intrinsic::xcore_setc, llvm::Intrinsic::xcore_setclk, llvm::Intrinsic::xcore_setd,   llvm::Intrinsic::xcore_setev, llvm::Intrinsic::xcore_setps, llvm::Intrinsic::xcore_setpsc, llvm::Intrinsic::xcore_setpt,   llvm::Intrinsic::xcore_setrdy, llvm::Intrinsic::xcore_setsr, llvm::Intrinsic::xcore_settw, llvm::Intrinsic::xcore_setv,   llvm::Intrinsic::xcore_sext, llvm::Intrinsic::xcore_ssync, llvm::Intrinsic::xcore_syncr, llvm::Intrinsic::xcore_testct,   llvm::Intrinsic::xcore_testwct, llvm::Intrinsic::xcore_waitevent, llvm::Intrinsic::xcore_zext, llvm::Intrinsic::num_intrinsics }

Functions
StringRef	llvm::Intrinsic::getName (ID id)
	Return the LLVM name for an intrinsic, such as "llvm.ppc.altivec.lvx". More...
std::string	llvm::Intrinsic::getName (ID id, ArrayRef< Type *> Tys)
	Return the LLVM name for an intrinsic, such as "llvm.ppc.altivec.lvx". More...
FunctionType *	llvm::Intrinsic::getType (LLVMContext &Context, ID id, ArrayRef< Type *> Tys=None)
	Return the function type for an intrinsic. More...
bool	llvm::Intrinsic::isOverloaded (ID id)
	Returns true if the intrinsic can be overloaded. More...
bool	llvm::Intrinsic::isLeaf (ID id)
	Returns true if the intrinsic is a leaf, i.e. More...
AttributeList	llvm::Intrinsic::getAttributes (LLVMContext &C, ID id)
	Return the attributes for an intrinsic. More...
Function *	llvm::Intrinsic::getDeclaration (Module *M, ID id, ArrayRef< Type *> Tys=None)
	Create or insert an LLVM Function declaration for an intrinsic, and return it. More...
int	llvm::Intrinsic::lookupLLVMIntrinsicByName (ArrayRef< const char *> NameTable, StringRef Name)
	Looks up Name in NameTable via binary search. More...
ID	llvm::Intrinsic::getIntrinsicForGCCBuiltin (const char *Prefix, StringRef BuiltinName)
	Map a GCC builtin name to an intrinsic ID. More...
ID	llvm::Intrinsic::getIntrinsicForMSBuiltin (const char *Prefix, StringRef BuiltinName)
	Map a MS builtin name to an intrinsic ID. More...
void	llvm::Intrinsic::getIntrinsicInfoTableEntries (ID id, SmallVectorImpl< IITDescriptor > &T)
	Return the IIT table descriptor for the specified intrinsic into an array of IITDescriptors. More...
bool	llvm::Intrinsic::matchIntrinsicType (Type *Ty, ArrayRef< IITDescriptor > &Infos, SmallVectorImpl< Type *> &ArgTys)
	Match the specified type (which comes from an intrinsic argument or return value) with the type constraints specified by the .td file. More...
bool	llvm::Intrinsic::matchIntrinsicVarArg (bool isVarArg, ArrayRef< IITDescriptor > &Infos)
	Verify if the intrinsic has variable arguments. More...
llvm::Optional< Function * >	llvm::Intrinsic::remangleIntrinsicFunction (Function *F)

Macro Definition Documentation

GET_INTRINSIC_ENUM_VALUES

#define GET_INTRINSIC_ENUM_VALUES

Definition at line 41 of file Intrinsics.h.