#include "Target/AMDGPU/GCNSchedStrategy.h"
Inheritance diagram for llvm::GCNScheduleDAGMILive:
Collaboration diagram for llvm::GCNScheduleDAGMILive:
Public Member Functions | |
| GCNScheduleDAGMILive (MachineSchedContext *C, std::unique_ptr< MachineSchedStrategy > S) | |
| void | schedule () override |
| Implement ScheduleDAGInstrs interface for scheduling a sequence of reorderable instructions. More... | |
| void | finalizeSchedule () override |
| Allow targets to perform final scheduling actions at the level of the whole MachineFunction. More... | |
 Public Member Functions inherited from llvm::ScheduleDAGMILive | |
| ScheduleDAGMILive (MachineSchedContext *C, std::unique_ptr< MachineSchedStrategy > S) | |
| ~ScheduleDAGMILive () override | |
| bool | hasVRegLiveness () const override |
| Return true if this DAG supports VReg liveness and RegPressure. More... | |
| bool | isTrackingPressure () const |
| Return true if register pressure tracking is enabled. More... | |
| const IntervalPressure & | getTopPressure () const |
| Get current register pressure for the top scheduled instructions. More... | |
| const RegPressureTracker & | getTopRPTracker () const |
| const IntervalPressure & | getBotPressure () const |
| Get current register pressure for the bottom scheduled instructions. More... | |
| const RegPressureTracker & | getBotRPTracker () const |
| const IntervalPressure & | getRegPressure () const |
| Get register pressure for the entire scheduling region before scheduling. More... | |
| const std::vector< PressureChange > & | getRegionCriticalPSets () const |
| PressureDiff & | getPressureDiff (const SUnit *SU) |
| const PressureDiff & | getPressureDiff (const SUnit *SU) const |
| void | computeDFSResult () |
| Compute a DFSResult after DAG building is complete, and before any queue comparisons. More... | |
| const SchedDFSResult * | getDFSResult () const |
| Return a non-null DFS result if the scheduling strategy initialized it. More... | |
| BitVector & | getScheduledTrees () |
| void | enterRegion (MachineBasicBlock *bb, MachineBasicBlock::iterator begin, MachineBasicBlock::iterator end, unsigned regioninstrs) override |
| Implement the ScheduleDAGInstrs interface for handling the next scheduling region. More... | |
| unsigned | computeCyclicCriticalPath () |
| Compute the cyclic critical path through the DAG. More... | |
| void | dump () const override |
| Public Member Functions inherited from llvm::ScheduleDAGMI | |
| ScheduleDAGMI (MachineSchedContext *C, std::unique_ptr< MachineSchedStrategy > S, bool RemoveKillFlags) | |
| ~ScheduleDAGMI () override | |
| bool | doMBBSchedRegionsTopDown () const override |
| If this method returns true, handling of the scheduling regions themselves (in case of a scheduling boundary in MBB) will be done beginning with the topmost region of MBB. More... | |
| LiveIntervals * | getLIS () const |
| void | addMutation (std::unique_ptr< ScheduleDAGMutation > Mutation) |
| Add a postprocessing step to the DAG builder. More... | |
| bool | canAddEdge (SUnit *SuccSU, SUnit *PredSU) |
| True if an edge can be added from PredSU to SuccSU without creating a cycle. More... | |
| bool | addEdge (SUnit *SuccSU, const SDep &PredDep) |
| Add a DAG edge to the given SU with the given predecessor dependence data. More... | |
| MachineBasicBlock::iterator | top () const |
| MachineBasicBlock::iterator | bottom () const |
| void | startBlock (MachineBasicBlock *bb) override |
| Prepares to perform scheduling in the given block. More... | |
| void | finishBlock () override |
| Cleans up after scheduling in the given block. More... | |
| void | moveInstruction (MachineInstr *MI, MachineBasicBlock::iterator InsertPos) |
| Change the position of an instruction within the basic block and update live ranges and region boundary iterators. More... | |
| const SUnit * | getNextClusterPred () const |
| const SUnit * | getNextClusterSucc () const |
| void | viewGraph (const Twine &Name, const Twine &Title) override |
| viewGraph - Pop up a ghostview window with the reachable parts of the DAG rendered using 'dot'. More... | |
| void | viewGraph () override |
| Out-of-line implementation with no arguments is handy for gdb. More... | |
| Public Member Functions inherited from llvm::ScheduleDAGInstrs | |
| ScheduleDAGInstrs (MachineFunction &mf, const MachineLoopInfo *mli, bool RemoveKillFlags=false) | |
| ~ScheduleDAGInstrs () override=default | |
| const TargetSchedModel * | getSchedModel () const |
| Gets the machine model for instruction scheduling. More... | |
| const MCSchedClassDesc * | getSchedClass (SUnit *SU) const |
| Resolves and cache a resolved scheduling class for an SUnit. More... | |
| MachineBasicBlock::iterator | begin () const |
| Returns an iterator to the top of the current scheduling region. More... | |
| MachineBasicBlock::iterator | end () const |
| Returns an iterator to the bottom of the current scheduling region. More... | |
| SUnit * | newSUnit (MachineInstr *MI) |
| Creates a new SUnit and return a ptr to it. More... | |
| SUnit * | getSUnit (MachineInstr *MI) const |
| Returns an existing SUnit for this MI, or nullptr. More... | |
| virtual void | exitRegion () |
| Called when the scheduler has finished scheduling the current region. More... | |
| void | buildSchedGraph (AliasAnalysis *AA, RegPressureTracker *RPTracker=nullptr, PressureDiffs *PDiffs=nullptr, LiveIntervals *LIS=nullptr, bool TrackLaneMasks=false) |
| Builds SUnits for the current region. More... | |
| void | addSchedBarrierDeps () |
| Adds dependencies from instructions in the current list of instructions being scheduled to scheduling barrier. More... | |
| void | dumpNode (const SUnit &SU) const override |
| void | dump () const override |
| std::string | getGraphNodeLabel (const SUnit *SU) const override |
| Returns a label for a DAG node that points to an instruction. More... | |
| std::string | getDAGName () const override |
| Returns a label for the region of code covered by the DAG. More... | |
| void | fixupKills (MachineBasicBlock &MBB) |
| Fixes register kill flags that scheduling has made invalid. More... | |
| Public Member Functions inherited from llvm::ScheduleDAG | |
| ScheduleDAG (MachineFunction &mf) | |
| virtual | ~ScheduleDAG () |
| void | clearDAG () |
| Clears the DAG state (between regions). More... | |
| const MCInstrDesc * | getInstrDesc (const SUnit *SU) const |
| Returns the MCInstrDesc of this SUnit. More... | |
| void | dumpNodeName (const SUnit &SU) const |
| virtual void | addCustomGraphFeatures (GraphWriter< ScheduleDAG *> &) const |
| Adds custom features for a visualization of the ScheduleDAG. More... | |
| unsigned | VerifyScheduledDAG (bool isBottomUp) |
| Verifies that all SUnits were scheduled and that their state is consistent. More... | |
Additional Inherited Members | |
| Public Types inherited from llvm::ScheduleDAGInstrs | |
| using | SUList = std::list< SUnit * > |
| A list of SUnits, used in Value2SUsMap, during DAG construction. More... | |
| Public Attributes inherited from llvm::ScheduleDAG | |
| const LLVMTargetMachine & | TM |
| Target processor. More... | |
| const TargetInstrInfo * | TII |
| Target instruction information. More... | |
| const TargetRegisterInfo * | TRI |
| Target processor register info. More... | |
| MachineFunction & | MF |
| Machine function. More... | |
| MachineRegisterInfo & | MRI |
| Virtual/real register map. More... | |
| std::vector< SUnit > | SUnits |
| The scheduling units. More... | |
| SUnit | EntrySU |
| Special node for the region entry. More... | |
| SUnit | ExitSU |
| Special node for the region exit. More... | |
| bool | StressSched |
| Protected Types inherited from llvm::ScheduleDAGInstrs | |
| using | DbgValueVector = std::vector< std::pair< MachineInstr *, MachineInstr * > > |
| Protected Member Functions inherited from llvm::ScheduleDAGMILive | |
| void | buildDAGWithRegPressure () |
| Call ScheduleDAGInstrs::buildSchedGraph with register pressure tracking enabled. More... | |
| void | initQueues (ArrayRef< SUnit *> TopRoots, ArrayRef< SUnit *> BotRoots) |
| Release ExitSU predecessors and setup scheduler queues. More... | |
| void | scheduleMI (SUnit *SU, bool IsTopNode) |
| Move an instruction and update register pressure. More... | |
| void | initRegPressure () |
| void | updatePressureDiffs (ArrayRef< RegisterMaskPair > LiveUses) |
| Update the PressureDiff array for liveness after scheduling this instruction. More... | |
| void | updateScheduledPressure (const SUnit *SU, const std::vector< unsigned > &NewMaxPressure) |
| void | collectVRegUses (SUnit &SU) |
| Protected Member Functions inherited from llvm::ScheduleDAGMI | |
| void | postprocessDAG () |
| Apply each ScheduleDAGMutation step in order. More... | |
| void | initQueues (ArrayRef< SUnit *> TopRoots, ArrayRef< SUnit *> BotRoots) |
| Release ExitSU predecessors and setup scheduler queues. More... | |
| void | updateQueues (SUnit *SU, bool IsTopNode) |
| Update scheduler DAG and queues after scheduling an instruction. More... | |
| void | placeDebugValues () |
| Reinsert debug_values recorded in ScheduleDAGInstrs::DbgValues. More... | |
| void | dumpSchedule () const |
| dump the scheduled Sequence. More... | |
| bool | checkSchedLimit () |
| void | findRootsAndBiasEdges (SmallVectorImpl< SUnit *> &TopRoots, SmallVectorImpl< SUnit *> &BotRoots) |
| void | releaseSucc (SUnit *SU, SDep *SuccEdge) |
| ReleaseSucc - Decrement the NumPredsLeft count of a successor. More... | |
| void | releaseSuccessors (SUnit *SU) |
| releaseSuccessors - Call releaseSucc on each of SU's successors. More... | |
| void | releasePred (SUnit *SU, SDep *PredEdge) |
| ReleasePred - Decrement the NumSuccsLeft count of a predecessor. More... | |
| void | releasePredecessors (SUnit *SU) |
| releasePredecessors - Call releasePred on each of SU's predecessors. More... | |
| Protected Member Functions inherited from llvm::ScheduleDAGInstrs | |
| void | reduceHugeMemNodeMaps (Value2SUsMap &stores, Value2SUsMap &loads, unsigned N) |
| Reduces maps in FIFO order, by N SUs. More... | |
| void | addChainDependency (SUnit *SUa, SUnit *SUb, unsigned Latency=0) |
| Adds a chain edge between SUa and SUb, but only if both AliasAnalysis and Target fail to deny the dependency. More... | |
| void | addChainDependencies (SUnit *SU, SUList &SUs, unsigned Latency) |
| Adds dependencies as needed from all SUs in list to SU. More... | |
| void | addChainDependencies (SUnit *SU, Value2SUsMap &Val2SUsMap) |
| Adds dependencies as needed from all SUs in map, to SU. More... | |
| void | addChainDependencies (SUnit *SU, Value2SUsMap &Val2SUsMap, ValueType V) |
| Adds dependencies as needed to SU, from all SUs mapped to V. More... | |
| void | addBarrierChain (Value2SUsMap &map) |
| Adds barrier chain edges from all SUs in map, and then clear the map. More... | |
| void | insertBarrierChain (Value2SUsMap &map) |
| Inserts a barrier chain in a huge region, far below current SU. More... | |
| void | initSUnits () |
| Creates an SUnit for each real instruction, numbered in top-down topological order. More... | |
| void | addPhysRegDataDeps (SUnit *SU, unsigned OperIdx) |
| MO is an operand of SU's instruction that defines a physical register. More... | |
| void | addPhysRegDeps (SUnit *SU, unsigned OperIdx) |
| Adds register dependencies (data, anti, and output) from this SUnit to following instructions in the same scheduling region that depend the physical register referenced at OperIdx. More... | |
| void | addVRegDefDeps (SUnit *SU, unsigned OperIdx) |
| Adds register output and data dependencies from this SUnit to instructions that occur later in the same scheduling region if they read from or write to the virtual register defined at OperIdx. More... | |
| void | addVRegUseDeps (SUnit *SU, unsigned OperIdx) |
| Adds a register data dependency if the instruction that defines the virtual register used at OperIdx is mapped to an SUnit. More... | |
| void | startBlockForKills (MachineBasicBlock *BB) |
| Initializes register live-range state for updating kills. More... | |
| void | toggleKillFlag (MachineInstr &MI, MachineOperand &MO) |
| Toggles a register operand kill flag. More... | |
| LaneBitmask | getLaneMaskForMO (const MachineOperand &MO) const |
| Returns a mask for which lanes get read/written by the given (register) machine operand. More... | |
| Protected Member Functions inherited from llvm::ScheduleDAG | |
| void | dumpNodeAll (const SUnit &SU) const |
| Protected Attributes inherited from llvm::ScheduleDAGMILive | |
| RegisterClassInfo * | RegClassInfo |
| SchedDFSResult * | DFSResult = nullptr |
| Information about DAG subtrees. More... | |
| BitVector | ScheduledTrees |
| MachineBasicBlock::iterator | LiveRegionEnd |
| VReg2SUnitMultiMap | VRegUses |
| Maps vregs to the SUnits of their uses in the current scheduling region. More... | |
| PressureDiffs | SUPressureDiffs |
| bool | ShouldTrackPressure = false |
| Register pressure in this region computed by initRegPressure. More... | |
| bool | ShouldTrackLaneMasks = false |
| IntervalPressure | RegPressure |
| RegPressureTracker | RPTracker |
| std::vector< PressureChange > | RegionCriticalPSets |
| List of pressure sets that exceed the target's pressure limit before scheduling, listed in increasing set ID order. More... | |
| IntervalPressure | TopPressure |
| The top of the unscheduled zone. More... | |
| RegPressureTracker | TopRPTracker |
| IntervalPressure | BotPressure |
| The bottom of the unscheduled zone. More... | |
| RegPressureTracker | BotRPTracker |
| bool | DisconnectedComponentsRenamed = false |
| True if disconnected subregister components are already renamed. More... | |
| Protected Attributes inherited from llvm::ScheduleDAGMI | |
| AliasAnalysis * | AA |
| LiveIntervals * | LIS |
| std::unique_ptr< MachineSchedStrategy > | SchedImpl |
| ScheduleDAGTopologicalSort | Topo |
| Topo - A topological ordering for SUnits which permits fast IsReachable and similar queries. More... | |
| std::vector< std::unique_ptr< ScheduleDAGMutation > > | Mutations |
| Ordered list of DAG postprocessing steps. More... | |
| MachineBasicBlock::iterator | CurrentTop |
| The top of the unscheduled zone. More... | |
| MachineBasicBlock::iterator | CurrentBottom |
| The bottom of the unscheduled zone. More... | |
| const SUnit * | NextClusterPred = nullptr |
| Record the next node in a scheduled cluster. More... | |
| const SUnit * | NextClusterSucc = nullptr |
| unsigned | NumInstrsScheduled = 0 |
| The number of instructions scheduled so far. More... | |
| Protected Attributes inherited from llvm::ScheduleDAGInstrs | |
| const MachineLoopInfo * | MLI |
| const MachineFrameInfo & | MFI |
| TargetSchedModel | SchedModel |
| TargetSchedModel provides an interface to the machine model. More... | |
| bool | RemoveKillFlags |
| True if the DAG builder should remove kill flags (in preparation for rescheduling). More... | |
| bool | CanHandleTerminators = false |
| The standard DAG builder does not normally include terminators as DAG nodes because it does not create the necessary dependencies to prevent reordering. More... | |
| bool | TrackLaneMasks = false |
| Whether lane masks should get tracked. More... | |
| MachineBasicBlock * | BB |
| The block in which to insert instructions. More... | |
| MachineBasicBlock::iterator | RegionBegin |
| The beginning of the range to be scheduled. More... | |
| MachineBasicBlock::iterator | RegionEnd |
| The end of the range to be scheduled. More... | |
| unsigned | NumRegionInstrs |
| Instructions in this region (distance(RegionBegin, RegionEnd)). More... | |
| DenseMap< MachineInstr *, SUnit * > | MISUnitMap |
| After calling BuildSchedGraph, each machine instruction in the current scheduling region is mapped to an SUnit. More... | |
| Reg2SUnitsMap | Defs |
| Defs, Uses - Remember where defs and uses of each register are as we iterate upward through the instructions. More... | |
| Reg2SUnitsMap | Uses |
| VReg2SUnitMultiMap | CurrentVRegDefs |
| Tracks the last instruction(s) in this region defining each virtual register. More... | |
| VReg2SUnitOperIdxMultiMap | CurrentVRegUses |
| Tracks the last instructions in this region using each virtual register. More... | |
| AliasAnalysis * | AAForDep = nullptr |
| SUnit * | BarrierChain = nullptr |
| Remember a generic side-effecting instruction as we proceed. More... | |
| UndefValue * | UnknownValue |
| For an unanalyzable memory access, this Value is used in maps. More... | |
| DbgValueVector | DbgValues |
| Remember instruction that precedes DBG_VALUE. More... | |
| MachineInstr * | FirstDbgValue = nullptr |
| LivePhysRegs | LiveRegs |
| Set of live physical registers for updating kill flags. More... | |
Detailed Description
Definition at line 63 of file GCNSchedStrategy.h.
Constructor & Destructor Documentation
◆ GCNScheduleDAGMILive()
| GCNScheduleDAGMILive::GCNScheduleDAGMILive | ( | MachineSchedContext * | C, |
| std::unique_ptr< MachineSchedStrategy > | S | ||
| ) |
Definition at line 294 of file GCNSchedStrategy.cpp.
References llvm::dbgs(), and LLVM_DEBUG.
Member Function Documentation
◆ finalizeSchedule()
|
overridevirtual |
Allow targets to perform final scheduling actions at the level of the whole MachineFunction.
By default does nothing.
Reimplemented from llvm::ScheduleDAGInstrs.
Definition at line 481 of file GCNSchedStrategy.cpp.
References llvm::ScheduleDAGInstrs::begin(), llvm::dbgs(), llvm::MachineBasicBlock::end(), llvm::ScheduleDAGInstrs::end(), llvm::ScheduleDAGMILive::enterRegion(), llvm::ScheduleDAGInstrs::exitRegion(), llvm::ScheduleDAGMI::finishBlock(), llvm::MachineBasicBlock::getName(), llvm::MachineFunction::getName(), llvm::ScheduleDAGMI::LIS, LLVM_DEBUG, llvm::ScheduleDAG::MF, llvm::ScheduleDAGInstrs::NumRegionInstrs, llvm::printMBBReference(), llvm::ScheduleDAGInstrs::RegionBegin, llvm::ScheduleDAGInstrs::RegionEnd, llvm::ScheduleDAGMI::SchedImpl, schedule(), llvm::GCNMaxOccupancySchedStrategy::setTargetOccupancy(), and llvm::ScheduleDAGMI::startBlock().
◆ schedule()
|
overridevirtual |
Implement ScheduleDAGInstrs interface for scheduling a sequence of reorderable instructions.
schedule - Called back from MachineScheduler::runOnMachineFunction after setting up the current scheduling region.
[RegionBegin, RegionEnd) only includes instructions that have DAG nodes, not scheduling boundaries.
This is a skeletal driver, with all the functionality pushed into helpers, so that it can be easily extended by experimental schedulers. Generally, implementing MachineSchedStrategy should be sufficient to implement a new scheduling algorithm. However, if a scheduler further subclasses ScheduleDAGMILive then it will want to override this virtual method in order to update any specialized state.
Reimplemented from llvm::ScheduleDAGMILive.
Definition at line 305 of file GCNSchedStrategy.cpp.
References llvm::RegisterOperands::adjustLaneLiveness(), llvm::GCNDownwardRPTracker::advance(), llvm::GCNDownwardRPTracker::advanceBeforeNext(), llvm::GCNDownwardRPTracker::advanceToNext(), llvm::ScheduleDAGInstrs::BB, llvm::MachineBasicBlock::begin(), llvm::ScheduleDAGInstrs::begin(), llvm::GCNRPTracker::clearMaxPressure(), llvm::RegisterOperands::collect(), llvm::dbgs(), llvm::RegisterOperands::detectDeadDefs(), E, llvm::empty(), llvm::MachineBasicBlock::end(), llvm::ScheduleDAGInstrs::end(), first, llvm::LiveIntervals::getInstructionIndex(), llvm::GCNRPTracker::getLiveRegs(), llvm::SlotIndexes::getMBBStartIdx(), llvm::SIMachineFunctionInfo::getMinAllowedOccupancy(), llvm::GCNDownwardRPTracker::getNext(), llvm::GCNRegPressure::getOccupancy(), llvm::SIMachineFunctionInfo::getOccupancy(), llvm::getRegPressure(), llvm::SlotIndex::getRegSlot(), llvm::LiveIntervals::getSlotIndexes(), llvm::LiveIntervals::handleMove(), I, llvm::MachineBasicBlock::insert(), llvm::SIMachineFunctionInfo::limitOccupancy(), llvm::ScheduleDAGMI::LIS, LLVM_DEBUG, llvm::max(), MI, llvm::GCNRPTracker::moveLiveRegs(), llvm::GCNRPTracker::moveMaxPressure(), llvm::ScheduleDAG::MRI, llvm::ScheduleDAGInstrs::NumRegionInstrs, llvm::ScheduleDAGMI::placeDebugValues(), llvm::GCNRegPressure::print(), llvm::GCNRPTracker::printLiveRegs(), llvm::ScheduleDAGInstrs::RegionBegin, llvm::ScheduleDAGInstrs::RegionEnd, llvm::MachineBasicBlock::remove(), llvm::GCNDownwardRPTracker::reset(), llvm::ScheduleDAGMILive::RPTracker, llvm::ScheduleDAGMI::SchedImpl, llvm::ScheduleDAGMILive::schedule(), second, llvm::ScheduleDAGMILive::ShouldTrackLaneMasks, llvm::MachineBasicBlock::succ_begin(), llvm::MachineBasicBlock::succ_size(), and llvm::ScheduleDAG::TRI.
Referenced by finalizeSchedule().
The documentation for this class was generated from the following files:
- lib/Target/AMDGPU/GCNSchedStrategy.h
- lib/Target/AMDGPU/GCNSchedStrategy.cpp
