LLVM
8.0.1
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R600 Implementation of TargetInstrInfo. More...
#include "R600InstrInfo.h"
#include "AMDGPU.h"
#include "AMDGPUInstrInfo.h"
#include "AMDGPUSubtarget.h"
#include "R600Defines.h"
#include "R600FrameLowering.h"
#include "R600RegisterInfo.h"
#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
#include "Utils/AMDGPUBaseInfo.h"
#include "llvm/ADT/BitVector.h"
#include "llvm/ADT/SmallSet.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/Support/ErrorHandling.h"
#include <algorithm>
#include <cassert>
#include <cstdint>
#include <cstring>
#include <iterator>
#include <utility>
#include <vector>
#include "R600GenDFAPacketizer.inc"
#include "R600GenInstrInfo.inc"
Go to the source code of this file.
Macros | |
#define | GET_INSTRINFO_CTOR_DTOR |
#define | GET_INSTRINFO_CTOR_DTOR |
#define | GET_INSTRMAP_INFO |
#define | GET_INSTRINFO_NAMED_OPS |
#define | OPERAND_CASE(Label) |
Functions | |
static std::vector< std::pair< int, unsigned > > | Swizzle (std::vector< std::pair< int, unsigned >> Src, R600InstrInfo::BankSwizzle Swz) |
static unsigned | getTransSwizzle (R600InstrInfo::BankSwizzle Swz, unsigned Op) |
static bool | NextPossibleSolution (std::vector< R600InstrInfo::BankSwizzle > &SwzCandidate, unsigned Idx) |
Given a swizzle sequence SwzCandidate and an index Idx, returns the next (in lexicographic term) swizzle sequence assuming that all swizzles after Idx can be skipped. More... | |
static bool | isConstCompatible (R600InstrInfo::BankSwizzle TransSwz, const std::vector< std::pair< int, unsigned >> &TransOps, unsigned ConstCount) |
Instructions in Trans slot can't read gpr at cycle 0 if they also read a const, and can't read a gpr at cycle 1 if they read 2 const. More... | |
static bool | isPredicateSetter (unsigned Opcode) |
static MachineInstr * | findFirstPredicateSetterFrom (MachineBasicBlock &MBB, MachineBasicBlock::iterator I) |
static bool | isJump (unsigned Opcode) |
static bool | isBranch (unsigned Opcode) |
static MachineBasicBlock::iterator | FindLastAluClause (MachineBasicBlock &MBB) |
static unsigned | getSlotedOps (unsigned Op, unsigned Slot) |
R600 Implementation of TargetInstrInfo.
Definition in file R600InstrInfo.cpp.
#define GET_INSTRINFO_CTOR_DTOR |
Definition at line 50 of file R600InstrInfo.cpp.
#define GET_INSTRINFO_CTOR_DTOR |
Definition at line 50 of file R600InstrInfo.cpp.
#define GET_INSTRINFO_NAMED_OPS |
Definition at line 52 of file R600InstrInfo.cpp.
#define GET_INSTRMAP_INFO |
Definition at line 51 of file R600InstrInfo.cpp.
#define OPERAND_CASE | ( | Label | ) |
Definition at line 1280 of file R600InstrInfo.cpp.
Referenced by getSlotedOps().
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Definition at line 653 of file R600InstrInfo.cpp.
References llvm::MachineBasicBlock::begin(), llvm::MachineInstr::getOpcode(), I, isPredicateSetter(), and MI.
Referenced by llvm::R600InstrInfo::insertBranch(), and llvm::R600InstrInfo::removeBranch().
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Definition at line 747 of file R600InstrInfo.cpp.
References E, llvm::MachineBasicBlock::end(), llvm::MachineInstrBundleIterator< Ty, IsReverse >::getReverse(), llvm::MachineBasicBlock::rbegin(), and llvm::MachineBasicBlock::rend().
Referenced by llvm::R600InstrInfo::insertBranch(), and llvm::R600InstrInfo::removeBranch().
Definition at line 1292 of file R600InstrInfo.cpp.
References llvm_unreachable, OPERAND_CASE, and write().
Referenced by llvm::R600InstrInfo::buildSlotOfVectorInstruction().
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Definition at line 404 of file R600InstrInfo.cpp.
References llvm::R600InstrInfo::ALU_VEC_012_SCL_210, llvm::R600InstrInfo::ALU_VEC_021_SCL_122, llvm::R600InstrInfo::ALU_VEC_102_SCL_221, llvm::R600InstrInfo::ALU_VEC_120_SCL_212, and llvm_unreachable.
Referenced by isConstCompatible(), and llvm::R600InstrInfo::isLegalUpTo().
Definition at line 670 of file R600InstrInfo.cpp.
Referenced by llvm::R600InstrInfo::analyzeBranch(), llvm::HexagonShuffler::check(), llvm::MCInstrDesc::isConditionalBranch(), llvm::HexagonInstrInfo::isNewValueJump(), llvm::HexagonInstrInfo::isPredictedTaken(), llvm::MCInstrDesc::isUnconditionalBranch(), llvm::HexagonInstrInfo::reverseBranchCondition(), and translateImmediate().
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Instructions in Trans slot can't read gpr at cycle 0 if they also read a const, and can't read a gpr at cycle 1 if they read 2 const.
Definition at line 516 of file R600InstrInfo.cpp.
References getTransSwizzle().
Referenced by llvm::R600InstrInfo::fitsReadPortLimitations().
Definition at line 666 of file R600InstrInfo.cpp.
Referenced by llvm::R600InstrInfo::analyzeBranch().
Definition at line 643 of file R600InstrInfo.cpp.
Referenced by llvm::R600InstrInfo::analyzeBranch(), llvm::R600InstrInfo::DefinesPredicate(), and findFirstPredicateSetterFrom().
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Given a swizzle sequence SwzCandidate and an index Idx, returns the next (in lexicographic term) swizzle sequence assuming that all swizzles after Idx can be skipped.
Definition at line 480 of file R600InstrInfo.cpp.
References llvm::R600InstrInfo::ALU_VEC_012_SCL_210, llvm::R600InstrInfo::ALU_VEC_210, and assert().
Referenced by llvm::R600InstrInfo::FindSwizzleForVectorSlot().
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Definition at line 376 of file R600InstrInfo.cpp.
References llvm::R600InstrInfo::ALU_VEC_012_SCL_210, llvm::R600InstrInfo::ALU_VEC_021_SCL_122, llvm::R600InstrInfo::ALU_VEC_102_SCL_221, llvm::R600InstrInfo::ALU_VEC_120_SCL_212, llvm::R600InstrInfo::ALU_VEC_201, llvm::R600InstrInfo::ALU_VEC_210, and std::swap().
Referenced by getReassignedChan(), and llvm::R600InstrInfo::isLegalUpTo().