10 #ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONBITTRACKER_H 11 #define LLVM_LIB_TARGET_HEXAGON_HEXAGONBITTRACKER_H 19 class HexagonInstrInfo;
20 class HexagonRegisterInfo;
21 class MachineFrameInfo;
22 class MachineFunction;
24 class MachineRegisterInfo;
58 unsigned getNextPhysReg(
unsigned PReg,
unsigned Width)
const;
59 unsigned getVirtRegFor(
unsigned PReg)
const;
78 #endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONBITTRACKER_H This class represents lattice values for constants.
BitTracker::BitMask mask(unsigned Reg, unsigned Sub) const override
const HexagonInstrInfo & TII
HexagonEvaluator(const HexagonRegisterInfo &tri, MachineRegisterInfo &mri, const HexagonInstrInfo &tii, MachineFunction &mf)
bool evaluate(const MachineInstr &MI, const CellMapType &Inputs, CellMapType &Outputs) const override
SetVector< const MachineBasicBlock * > BranchTargetList
BitTracker::CellMapType CellMapType
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
const TargetRegisterClass & composeWithSubRegIndex(const TargetRegisterClass &RC, unsigned Idx) const override
The instances of the Type class are immutable: once they are created, they are never changed...
uint16_t getPhysRegBitWidth(unsigned Reg) const override
std::map< unsigned, RegisterCell > CellMapType
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
A vector that has set insertion semantics.