29 #define DEBUG_TYPE "mccodeemitter" 41 : MCII(mcii),
MRI(mri), IsLittleEndian(IsLittleEndian) {}
42 BPFMCCodeEmitter(
const BPFMCCodeEmitter &) =
delete;
43 void operator=(
const BPFMCCodeEmitter &) =
delete;
44 ~BPFMCCodeEmitter()
override =
default;
48 uint64_t getBinaryCodeForInstr(
const MCInst &
MI,
58 uint64_t getMemoryOpValue(
const MCInst &MI,
unsigned Op,
67 uint64_t computeAvailableFeatures(
const FeatureBitset &FB)
const;
68 void verifyInstructionPredicates(
const MCInst &MI,
69 uint64_t AvailableFeatures)
const;
77 return new BPFMCCodeEmitter(MCII, MRI,
true);
83 return new BPFMCCodeEmitter(MCII, MRI,
false);
86 unsigned BPFMCCodeEmitter::getMachineOpValue(
const MCInst &
MI,
93 return static_cast<unsigned>(MO.
getImm());
104 else if (MI.
getOpcode() == BPF::LD_imm64)
115 return (Val & 0x0F) << 4 | (Val & 0xF0) >> 4;
121 verifyInstructionPredicates(MI,
128 if (Opcode == BPF::LD_imm64 || Opcode == BPF::LD_pseudo) {
129 uint64_t
Value = getBinaryCodeForInstr(MI, Fixups, STI);
130 OS << char(Value >> 56);
132 OS << char((Value >> 48) & 0xff);
134 OS << char(SwapBits((Value >> 48) & 0xff));
135 OSE.
write<uint16_t>(0);
139 uint64_t Imm = MO.
isImm() ? MO.getImm() : 0;
140 OSE.
write<uint8_t>(0);
141 OSE.
write<uint8_t>(0);
142 OSE.
write<uint16_t>(0);
146 uint64_t
Value = getBinaryCodeForInstr(MI, Fixups, STI);
147 OS << char(Value >> 56);
149 OS << char((Value >> 48) & 0xff);
151 OS << char(SwapBits((Value >> 48) & 0xff));
152 OSE.
write<uint16_t>((Value >> 32) & 0xffff);
158 uint64_t BPFMCCodeEmitter::getMemoryOpValue(
const MCInst &MI,
unsigned Op,
163 assert(Op1.
isReg() &&
"First operand is not register.");
164 Encoding =
MRI.getEncodingValue(Op1.
getReg());
167 assert(Op2.
isImm() &&
"Second operand is not immediate.");
168 Encoding |= Op2.
getImm() & 0xffff;
172 #define ENABLE_INSTR_PREDICATE_VERIFIER 173 #include "BPFGenMCCodeEmitter.inc"
This class represents lattice values for constants.
void push_back(const T &Elt)
const FeatureBitset & getFeatureBits() const
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Base class for the full range of assembler expressions which are needed for parsing.
unsigned getReg() const
Returns the register number.
Context object for machine code objects.
MCCodeEmitter * createBPFbeMCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, MCContext &Ctx)
const MCExpr * getExpr() const
Instances of this class represent a single low-level machine instruction.
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
unsigned const MachineRegisterInfo * MRI
Container class for subtarget features.
MCCodeEmitter - Generic instruction encoding interface.
Interface to description of machine instruction set.
static MCFixup create(uint32_t Offset, const MCExpr *Value, MCFixupKind Kind, SMLoc Loc=SMLoc())
static uint8_t SwapBits(uint8_t Val)
A two-byte pc relative fixup.
A four-byte pc relative fixup.
void write(ArrayRef< value_type > Val)
const MCOperand & getOperand(unsigned i) const
Adapter to write values to a stream in a particular byte order.
A eight-byte section relative fixup.
Generic base class for all target subtargets.
References to labels and assigned expressions.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
LLVM Value Representation.
MCCodeEmitter * createBPFMCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, MCContext &Ctx)
This class implements an extremely fast bulk output stream that can only output to a stream...
unsigned getOpcode() const
Instances of this class represent operands of the MCInst class.